RetroSearch Browse

Home - News ( United States | United Kingdom | Italy | Germany ) - Football scores

Showing content from https://stm32-rs.github.io/stm32-rs/stm32u585.svd.patched below:

STM32U585 1.4 STM32U585 CM33 r0p1 little true true 4 false 8 32 0x20 0x00000000 0xFFFFFFFF EXTI External interrupt/event controller EXTI 0x46022000 0x0 0x400 registers PVD_PVM Power voltage monitor/Analog voltage monitor 1 EXTI0 EXTI line0 interrupt 11 EXTI1 EXTI line1 interrupt 12 EXTI2 EXTI line2 interrupt 13 EXTI3 EXTI line3 interrupt 14 EXTI4 EXTI line4 interrupt 15 EXTI5 EXTI line5 interrupt 16 EXTI6 EXTI line6 interrupt 17 EXTI7 EXTI line7 interrupt 18 EXTI8 EXTI line8 interrupt 19 EXTI9 EXTI line9 interrupt 20 EXTI10 EXTI line10 interrupt 21 EXTI11 EXTI line11 interrupt 22 EXTI12 EXTI line12 interrupt 23 EXTI13 EXTI line13 interrupt 24 EXTI14 EXTI line14 interrupt 25 EXTI15 EXTI line15 interrupt 26 FPU Floating point interrupt 95 LSECSSD LSECSSD interrupt 125 GPU2D_IRQ GPU2D interrupt 132 GPU2D_IRQSYS GPU2D system interrupt 133 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 0x00000000 0xFFFFFFFF RT0 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT1 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write RT2 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write RT3 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write RT4 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write RT5 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write RT6 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write RT7 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write RT8 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write RT9 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write RT10 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write RT11 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write RT12 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write RT13 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write RT14 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write RT15 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write RT16 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write RT17 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write RT18 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write RT19 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write RT20 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write RT21 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write RT22 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write RT23 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write RT24 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write RT25 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 0x00000000 0xFFFFFFFF FT0 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT1 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write FT2 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write FT3 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write FT4 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write FT5 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write FT6 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write FT7 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write FT8 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write FT9 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write FT10 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write FT11 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write FT12 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write FT13 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write FT14 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write FT15 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write FT16 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write FT17 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write FT18 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write FT19 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write FT20 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write FT21 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write FT22 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write FT23 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write FT24 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write FT25 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 0x00000000 0xFFFFFFFF SWI0 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write SoftwareInterrupt write Pend Generates an interrupt request 1 SWI1 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write SWI2 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write SWI3 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write SWI4 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write SWI5 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write SWI6 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write SWI7 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write SWI8 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write SWI9 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write SWI10 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write SWI11 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write SWI12 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write SWI13 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write SWI14 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write SWI15 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write SWI16 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write SWI17 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write SWI18 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write SWI19 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write SWI20 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write SWI21 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write SWI22 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write SWI23 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write SWI24 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write SWI25 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write RPR1 RPR1 EXTI rising edge pending register 0xC 0x20 0x00000000 0xFFFFFFFF RPIF0 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 0 1 read-write oneToClear RPIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 RPIF0W write Clear Clears pending bit 1 RPIF1 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 1 1 read-write oneToClear read write RPIF2 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 2 1 read-write oneToClear read write RPIF3 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 3 1 read-write oneToClear read write RPIF4 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 4 1 read-write oneToClear read write RPIF5 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 5 1 read-write oneToClear read write RPIF6 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 6 1 read-write oneToClear read write RPIF7 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 7 1 read-write oneToClear read write RPIF8 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 8 1 read-write oneToClear read write RPIF9 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 9 1 read-write oneToClear read write RPIF10 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 10 1 read-write oneToClear read write RPIF11 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 11 1 read-write oneToClear read write RPIF12 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 12 1 read-write oneToClear read write RPIF13 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 13 1 read-write oneToClear read write RPIF14 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 14 1 read-write oneToClear read write RPIF15 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 15 1 read-write oneToClear read write RPIF16 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 16 1 read-write oneToClear read write RPIF17 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 17 1 read-write oneToClear read write RPIF18 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 18 1 read-write oneToClear read write RPIF19 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 19 1 read-write oneToClear read write RPIF20 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 20 1 read-write oneToClear read write RPIF21 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 21 1 read-write oneToClear read write RPIF22 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 22 1 read-write oneToClear read write RPIF23 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 23 1 read-write oneToClear read write RPIF24 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 24 1 read-write oneToClear read write RPIF25 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 25 1 read-write oneToClear read write FPR1 FPR1 EXTI falling edge pending register 0x10 0x20 0x00000000 0xFFFFFFFF FPIF0 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write oneToClear FPIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 FPIF0W write Clear Clears pending bit 1 FPIF1 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write oneToClear read write FPIF2 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write oneToClear read write FPIF3 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write oneToClear read write FPIF4 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write oneToClear read write FPIF5 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write oneToClear read write FPIF6 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write oneToClear read write FPIF7 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write oneToClear read write FPIF8 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write oneToClear read write FPIF9 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write oneToClear read write FPIF10 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write oneToClear read write FPIF11 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write oneToClear read write FPIF12 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write oneToClear read write FPIF13 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write oneToClear read write FPIF14 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write oneToClear read write FPIF15 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write oneToClear read write FPIF16 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write oneToClear read write FPIF17 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write oneToClear read write FPIF18 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write oneToClear read write FPIF19 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write oneToClear read write FPIF20 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write oneToClear read write FPIF21 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write oneToClear read write FPIF22 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write oneToClear read write FPIF23 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write oneToClear read write FPIF24 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write oneToClear read write FPIF25 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write oneToClear read write SECCFGR1 SECCFGR1 EXTI security configuration register 0x14 0x20 0x00000000 0xFFFFFFFF SEC0 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write SEC1 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write SEC2 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write SEC3 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write SEC4 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write SEC5 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write SEC6 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write SEC7 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write SEC8 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write SEC9 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write SEC10 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write SEC11 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write SEC12 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write SEC13 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write SEC14 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write SEC15 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write SEC16 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write SEC17 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write SEC18 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write SEC19 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write SEC20 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write SEC21 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write SEC22 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write SEC23 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write SEC24 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write SEC25 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write PRIVCFGR1 PRIVCFGR1 EXTI privilege configuration register 0x18 0x20 0x00000000 0xFFFFFFFF PRIV0 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write EventPrivilege Unprivileged Event privilege disabled 0 Privileged Event privilege enabled 1 PRIV1 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write PRIV2 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write PRIV3 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write PRIV4 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write PRIV5 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write PRIV6 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write PRIV7 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write PRIV8 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write PRIV9 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write PRIV10 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write PRIV11 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write PRIV12 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write PRIV13 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write PRIV14 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write PRIV15 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write PRIV16 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write PRIV17 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write PRIV18 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write PRIV19 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write PRIV20 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write PRIV21 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write PRIV22 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write PRIV23 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write PRIV24 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write PRIV25 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 0x00000000 0xFFFFFFFF EXTI0 EXTIm GPIO port selection 0 8 read-write EXTI0 PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 PE Select PEx as the source input for the EXTIx external interrupt 4 PF Select PFx as the source input for the EXTIx external interrupt 5 PG Select PGx as the source input for the EXTIx external interrupt 6 PH Select PHx as the source input for the EXTIx external interrupt 7 PI Select PIx as the source input for the EXTIx external interrupt 8 PJ Select PJx as the source input for the EXTIx external interrupt 9 EXTI1 EXTIm+1 GPIO port selection 8 8 read-write EXTI2 EXTIm+2 GPIO port selection 16 8 read-write EXTI3 EXTIm+3 GPIO port selection 24 8 read-write EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 0x00000000 0xFFFFFFFF EXTI4 EXTIm GPIO port selection 0 8 read-write EXTI5 EXTIm+1 GPIO port selection 8 8 read-write EXTI6 EXTIm+2 GPIO port selection 16 8 read-write EXTI7 EXTIm+3 GPIO port selection 24 8 read-write EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 0x20 0x00000000 0xFFFFFFFF EXTI8 EXTIm GPIO port selection 0 8 read-write EXTI9 EXTIm+1 GPIO port selection 8 8 read-write EXTI10 EXTIm+2 GPIO port selection 16 8 read-write EXTI11 EXTIm+3 GPIO port selection 24 8 read-write EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 0x20 0x00000000 0xFFFFFFFF EXTI12 EXTIm GPIO port selection 0 8 read-write EXTI13 EXTIm+1 GPIO port selection 8 8 read-write EXTI14 EXTIm+2 GPIO port selection 16 8 read-write EXTI15 EXTIm+3 GPIO port selection 24 8 read-write LOCKR LOCKR EXTI lock register 0x70 0x20 0x00000000 0xFFFFFFFF LOCK Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock This bit is written once after reset. 0 1 read-write IMR1 IMR1 EXTI CPU wake-up with interrupt mask register 0x80 0x20 0x00000000 0xFFFFFFFF IM0 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 IM1 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write IM2 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write IM3 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write IM4 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write IM5 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write IM6 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write IM7 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write IM8 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write IM9 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write IM10 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write IM11 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write IM12 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write IM13 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write IM14 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write IM15 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write IM16 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write IM17 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write IM18 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write IM19 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write IM20 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write IM21 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write IM22 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write IM23 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write IM24 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write IM25 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write EMR1 EMR1 EXTI CPU wake-up with event mask register 0x84 0x20 0x00000000 0xFFFFFFFF EM0 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM1 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write EM2 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write EM3 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write EM4 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write EM5 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write EM6 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write EM7 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write EM8 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write EM9 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write EM10 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write EM11 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write EM12 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write EM13 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write EM14 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write EM15 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write EM16 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write EM17 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write EM18 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write EM19 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write EM20 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write EM21 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write EM22 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write EM23 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write EM24 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write EM25 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write SEC_EXTI 0x56022000 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash memory non-secure global interrupt 6 FLASH_S Flash memory secure global interrupt 7 ACR ACR FLASH access control register 0x0 0x20 0x00000000 0xFFFFFFFF LATENCY Latency These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time. ... 0 4 read-write PRFTEN Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory. 8 1 read-write LPM Low-power read mode This bit puts the Flash memory in low-power read mode. 11 1 read-write PDREQ1 Bank 1 power-down mode request This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked. 12 1 read-write PDREQ2 Bank 2 power-down mode request This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked. 13 1 read-write SLEEP_PD Flash memory power-down mode during Sleep mode This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode. The Flash must not be put in power-down while a program or an erase operation is on-going. 14 1 read-write NSKEYR NSKEYR FLASH non-secure key register 0x8 0x20 0x00000000 0xFFFFFFFF NSKEY Flash memory non-secure key 0 32 write-only SECKEYR SECKEYR FLASH secure key register 0xC 0x20 0x00000000 0xFFFFFFFF SECKEY Flash memory secure key 0 32 write-only OPTKEYR OPTKEYR FLASH option key register 0x10 0x20 0x00000000 0xFFFFFFFF OPTKEY Option byte key 0 32 write-only PDKEY1R PDKEY1R FLASH bank 1 power-down key register 0x18 0x20 0x00000000 0xFFFFFFFF PDKEY1 Bank 1 power-down key 0 32 write-only PDKEY2R PDKEY2R FLASH bank 2 power-down key register 0x1C 0x20 0x00000000 0xFFFFFFFF PDKEY2 Bank 2 power-down key 0 32 write-only NSSR NSSR FLASH non-secure status register 0x20 0x20 0x00000000 0xFFF0FFFF EOP Non-secure end of operation 0 1 read-write OPERR Non-secure operation error 1 1 read-write PROGERR Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. 3 1 read-write WRPERR Non-secure write protection error This bit is set by hardware when an non-secure address to be erased/programmed belongs to a write-protected part (by WRP, HDP or RDP level 1) of the Flash memory. This bit is cleared by writing 1. Refer to for full conditions of error flag setting. 4 1 read-write PGAERR Non-secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1. 5 1 read-write SIZERR Non-secure size error This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1. 6 1 read-write PGSERR Non-secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting. 7 1 read-write OPTWERR Option write error This bit is set by hardware when the options bytes are written with an invalid configuration. It is cleared by writing 1. Refer to for full conditions of error flag setting. 13 1 read-write BSY Non-secure busy This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs. 16 1 read-only WDW Non-secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory. 17 1 read-only OEM1LOCK OEM1 lock This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the OEM1 RDP lock mechanism is active. 18 1 read-only OEM2LOCK OEM2 lock This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the OEM2 RDP lock mechanism is active. 19 1 read-only PD1 Bank 1 in power-down mode This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bankÂ 1 is in normal mode or being awaken. 20 1 read-only PD2 Bank 2 in power-down mode This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bankÂ 2 is in normal mode or being awaken. 21 1 read-only SECSR SECSR FLASH secure status register 0x24 0x20 0x00000000 0xFFFFFFFF EOP Secure end of operation This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writingÂ 1. 0 1 read-write OPERR Secure operation error This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1. 1 1 read-write PROGERR Secure programming error This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. 3 1 read-write WRPERR Secure write protection error This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory.This bit is cleared by writing 1. Refer to for full conditions of error flag setting. 4 1 read-write PGAERR Secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1. 5 1 read-write SIZERR Secure size error This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1. 6 1 read-write PGSERR Secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting. 7 1 read-write BSY Secure busy This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs. 16 1 read-only WDW Secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory. 17 1 read-only NSCR NSCR FLASH non-secure control register 0x28 0x20 0xC0000000 0xFFFFFFFF PG Non-secure programming 0 1 read-write PER Non-secure page erase 1 1 read-write MER1 Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set. 2 1 read-write PNB Non-secure page number selection These bits select the page to erase. ... 3 7 read-write BKER Non-secure bank selection for page erase 11 1 read-write BWR Non-secure burst write programming mode When set, this bit selects the burst write programming mode. 14 1 read-write MER2 Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set. 15 1 read-write STRT Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR. 16 1 read-write OPTSTRT Options modification start This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR. 17 1 read-write EOPIE Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1. 24 1 read-write ERRIE Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1. 25 1 read-write OBL_LAUNCH Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set. 27 1 read-write OPTLOCK Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset. 30 1 read-write LOCK Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. 31 1 read-write SECCR SECCR FLASH secure control register 0x2C 0x20 0x80000000 0xFFFFFFFF PG Secure programming 0 1 read-write PER Secure page erase 1 1 read-write MER1 Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set. 2 1 read-write PNB Secure page number selection These bits select the page to erase: ... 3 7 read-write BKER Secure bank selection for page erase 11 1 read-write BWR Secure burst write programming mode When set, this bit selects the burst write programming mode. 14 1 read-write MER2 Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set. 15 1 read-write STRT Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR. 16 1 read-write EOPIE Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1. 24 1 read-write ERRIE Secure error interrupt enable 25 1 read-write RDERRIE Secure PCROP read error interrupt enable 26 1 read-write INV Flash memory security state invert This bit inverts the Flash memory security state. 29 1 read-write LOCK Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. 31 1 read-write ECCR ECCR FLASH ECC register 0x30 0x20 0x00000000 0xFFFFFFFF ADDR_ECC ECC fail address 0 20 read-only BK_ECC ECC fail bank 21 1 read-only SYSF_ECC System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory. 22 1 read-only ECCIE ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set. 24 1 read-write ECCC ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1. 30 1 read-write ECCD ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1. 31 1 read-write OPSR OPSR FLASH operation status register 0x34 0x20 0x00000000 0x0F000000 ADDR_OP Interrupted operation address This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0Â 0000 to 0xFÂ FFF0. 0 20 read-only BK_OP Interrupted operation bank This bit indicates which Flash memory bank was accessed when reset occurred 21 1 read-only SYSF_OP Operation in system Flash memory interrupted This bit indicates that the reset occurred during an operation in the system Flash memory. 22 1 read-only CODE_OP Flash memory operation code This field indicates which Flash memory operation has been interrupted by a system reset: 29 3 read-only OPTR OPTR FLASH option register 0x40 0x20 0x00000000 0x00000000 RDP Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to for more details. 0 8 read-write BOR_LEV BOR reset level These bits contain the VDD supply level threshold that activates/releases the reset. 8 3 read-write nRST_STOP Reset generation in Stop mode 12 1 read-write nRST_STDBY Reset generation in Standby mode 13 1 read-write nRST_SHDW Reset generation in Shutdown mode 14 1 read-write SRAM1345_RST SRAM1, SRAM3 and SRAM4 erase upon system reset 15 1 read-write IWDG_SW Independent watchdog selection 16 1 read-write IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 read-write IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 read-write WWDG_SW Window watchdog selection 19 1 read-write SWAP_BANK Swap banks 20 1 read-write DUALBANK Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices 21 1 read-write BKPRAM_ECC Backup RAM ECC detection and correction enable 22 1 read-write SRAM3_ECC SRAM3 ECC detection and correction enable 23 1 read-write SRAM2_ECC SRAM2 ECC detection and correction enable 24 1 read-write SRAM2_RST SRAM2 erase when system reset 25 1 read-write nSWBOOT0 Software BOOT0 26 1 read-write nBOOT0 nBOOT0 option bit 27 1 read-write PA15_PUPEN PA15 pull-up enable 28 1 read-write IO_VDD_HSLV High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V 29 1 read-write IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.5Â V. 30 1 read-write TZEN Global TrustZone security enable 31 1 read-write NSBOOTADD0R NSBOOTADD0R FLASH non-secure boot address 0 register 0x44 0x20 0x0000000F 0x0000000F NSBOOTADD0 Non-secure boot base address 0 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000) 7 25 read-write NSBOOTADD1R NSBOOTADD1R FLASH non-secure boot address 1 register 0x48 0x20 0x0000000F 0x0000000F NSBOOTADD1 Non-secure boot address 1 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000) 7 25 read-write SECBOOTADD0R SECBOOTADD0R FLASH secure boot address 0 register 0x4C 0x20 0x00000000 0x00000000 BOOT_LOCK Boot lock When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0. 0 1 read-write SECBOOTADD0 Secure boot base address 0 The secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash memory (0x0C00 0000) SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000) SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000) 7 25 read-write SECWM1R1 SECWM1R1 FLASH secure watermark1 register 1 0x50 0x20 0xFF00FF00 0xFF00FF00 SECWM1_PSTRT Start page of first secure area This field contains the first page of the secure area in bank 1. 0 7 read-write SECWM1_PEND End page of first secure area This field contains the last page of the secure area in bank 1. 16 7 read-write SECWM1R2 SECWM1R2 FLASH secure watermark1 register 2 0x54 0x20 0x0F00FFFF 0x0F00FFFF HDP1_PEND End page of first hide protection area This field contains the last page of the HDP area in bank 1. 16 7 read-write HDP1EN Hide protection first area enable 31 1 read-write WRP1AR WRP1AR FLASH WRP1 area A address register 0x58 0x20 0x0F00FF00 0x0F00FF00 WRP1A_PSTRT bank 1 WPR first area A start page This field contains the first page of the first WPR area for bank 1. 0 7 read-write WRP1A_PEND Bank 1 WPR first area A end page This field contains the last page of the first WPR area in bank 1. 16 7 read-write UNLOCK Bank 1 WPR first area A unlock 31 1 read-write WRP1BR WRP1BR FLASH WRP1 area B address register 0x5C 0x20 0x0F00FF00 0x0F00FF00 WRP1B_PSTRT Bank 1 WRP second area B start page This field contains the first page of the second WRP area for bank 1. 0 7 read-write WRP1B_PEND Bank 1 WRP second area B end page This field contains the last page of the second WRP area in bank 1. 16 7 read-write UNLOCK Bank 1 WPR second area B unlock 31 1 read-write SECWM2R1 SECWM2R1 FLASH secure watermark2 register 1 0x60 0x20 0xFF00FF00 0xFF00FF00 SECWM2_PSTRT Start page of second secure area This field contains the first page of the secure area in bank 2. 0 7 read-write SECWM2_PEND End page of second secure area This field contains the last page of the secure area in bank 2. 16 7 read-write SECWM2R2 SECWM2R2 FLASH secure watermark2 register 2 0x64 0x20 0x0F00FFFF 0x0F00FFFF HDP2_PEND End page of hide protection second area HDP2_PEND contains the last page of the HDP area in bank 2. 16 7 read-write HDP2EN Hide protection second area enable 31 1 read-write WRP2AR WRP2AR FLASH WPR2 area A address register 0x68 0x20 0x0F00FF00 0x0F00FF00 WRP2A_PSTRT Bank 2 WPR first area A start page This field contains the first page of the first WRP area for bank 2. 0 7 read-write WRP2A_PEND Bank 2 WPR first area A end page This field contains the last page of the first WRP area in bank 2. 16 7 read-write UNLOCK Bank 2 WPR first area A unlock 31 1 read-write WRP2BR WRP2BR FLASH WPR2 area B address register 0x6C 0x20 0x0F00FF00 0x0F00FF00 WRP2B_PSTRT Bank 2 WPR second area B start page This field contains the first page of the second WRP area for bank 2. 0 7 read-write WRP2B_PEND Bank 2 WPR second area B end page This field contains the last page of the second WRP area in bank 2. 16 7 read-write UNLOCK Bank 2 WPR second area B unlock 31 1 read-write OEM1KEYR1 OEM1KEYR1 FLASH OEM1 key register 1 0x70 0x20 0x00000000 0xFFFFFFFF OEM1KEY OEM1 least significant bytes key 0 32 write-only OEM1KEYR2 OEM1KEYR2 FLASH OEM1 key register 2 0x74 0x20 0x00000000 0xFFFFFFFF OEM1KEY OEM1 most significant bytes key 0 32 write-only OEM2KEYR1 OEM2KEYR1 FLASH OEM2 key register 1 0x78 0x20 0x00000000 0xFFFFFFFF OEM2KEY OEM2 least significant bytes key 0 32 write-only OEM2KEYR2 OEM2KEYR2 FLASH OEM2 key register 2 0x7C 0x20 0x00000000 0xFFFFFFFF OEM2KEY OEM2 most significant bytes key 0 32 write-only SEC1BBR1 SEC1BBR1 FLASH secure block based bank 1 register 1 0x80 0x20 0x00000000 0xFFFFFFFF SEC1BB0 page secure/non-secure attribution 0 1 read-write SEC1BB1 page secure/non-secure attribution 1 1 read-write SEC1BB2 page secure/non-secure attribution 2 1 read-write SEC1BB3 page secure/non-secure attribution 3 1 read-write SEC1BB4 page secure/non-secure attribution 4 1 read-write SEC1BB5 page secure/non-secure attribution 5 1 read-write SEC1BB6 page secure/non-secure attribution 6 1 read-write SEC1BB7 page secure/non-secure attribution 7 1 read-write SEC1BB8 page secure/non-secure attribution 8 1 read-write SEC1BB9 page secure/non-secure attribution 9 1 read-write SEC1BB10 page secure/non-secure attribution 10 1 read-write SEC1BB11 page secure/non-secure attribution 11 1 read-write SEC1BB12 page secure/non-secure attribution 12 1 read-write SEC1BB13 page secure/non-secure attribution 13 1 read-write SEC1BB14 page secure/non-secure attribution 14 1 read-write SEC1BB15 page secure/non-secure attribution 15 1 read-write SEC1BB16 page secure/non-secure attribution 16 1 read-write SEC1BB17 page secure/non-secure attribution 17 1 read-write SEC1BB18 page secure/non-secure attribution 18 1 read-write SEC1BB19 page secure/non-secure attribution 19 1 read-write SEC1BB20 page secure/non-secure attribution 20 1 read-write SEC1BB21 page secure/non-secure attribution 21 1 read-write SEC1BB22 page secure/non-secure attribution 22 1 read-write SEC1BB23 page secure/non-secure attribution 23 1 read-write SEC1BB24 page secure/non-secure attribution 24 1 read-write SEC1BB25 page secure/non-secure attribution 25 1 read-write SEC1BB26 page secure/non-secure attribution 26 1 read-write SEC1BB27 page secure/non-secure attribution 27 1 read-write SEC1BB28 page secure/non-secure attribution 28 1 read-write SEC1BB29 page secure/non-secure attribution 29 1 read-write SEC1BB30 page secure/non-secure attribution 30 1 read-write SEC1BB31 page secure/non-secure attribution 31 1 read-write SEC1BBR2 SEC1BBR2 FLASH secure block based bank 1 register 2 0x84 0x20 0x00000000 0xFFFFFFFF SEC1BB0 page secure/non-secure attribution 0 1 read-write SEC1BB1 page secure/non-secure attribution 1 1 read-write SEC1BB2 page secure/non-secure attribution 2 1 read-write SEC1BB3 page secure/non-secure attribution 3 1 read-write SEC1BB4 page secure/non-secure attribution 4 1 read-write SEC1BB5 page secure/non-secure attribution 5 1 read-write SEC1BB6 page secure/non-secure attribution 6 1 read-write SEC1BB7 page secure/non-secure attribution 7 1 read-write SEC1BB8 page secure/non-secure attribution 8 1 read-write SEC1BB9 page secure/non-secure attribution 9 1 read-write SEC1BB10 page secure/non-secure attribution 10 1 read-write SEC1BB11 page secure/non-secure attribution 11 1 read-write SEC1BB12 page secure/non-secure attribution 12 1 read-write SEC1BB13 page secure/non-secure attribution 13 1 read-write SEC1BB14 page secure/non-secure attribution 14 1 read-write SEC1BB15 page secure/non-secure attribution 15 1 read-write SEC1BB16 page secure/non-secure attribution 16 1 read-write SEC1BB17 page secure/non-secure attribution 17 1 read-write SEC1BB18 page secure/non-secure attribution 18 1 read-write SEC1BB19 page secure/non-secure attribution 19 1 read-write SEC1BB20 page secure/non-secure attribution 20 1 read-write SEC1BB21 page secure/non-secure attribution 21 1 read-write SEC1BB22 page secure/non-secure attribution 22 1 read-write SEC1BB23 page secure/non-secure attribution 23 1 read-write SEC1BB24 page secure/non-secure attribution 24 1 read-write SEC1BB25 page secure/non-secure attribution 25 1 read-write SEC1BB26 page secure/non-secure attribution 26 1 read-write SEC1BB27 page secure/non-secure attribution 27 1 read-write SEC1BB28 page secure/non-secure attribution 28 1 read-write SEC1BB29 page secure/non-secure attribution 29 1 read-write SEC1BB30 page secure/non-secure attribution 30 1 read-write SEC1BB31 page secure/non-secure attribution 31 1 read-write SEC1BBR3 SEC1BBR3 FLASH secure block based bank 1 register 3 0x88 0x20 0x00000000 0xFFFFFFFF SEC1BB0 page secure/non-secure attribution 0 1 read-write SEC1BB1 page secure/non-secure attribution 1 1 read-write SEC1BB2 page secure/non-secure attribution 2 1 read-write SEC1BB3 page secure/non-secure attribution 3 1 read-write SEC1BB4 page secure/non-secure attribution 4 1 read-write SEC1BB5 page secure/non-secure attribution 5 1 read-write SEC1BB6 page secure/non-secure attribution 6 1 read-write SEC1BB7 page secure/non-secure attribution 7 1 read-write SEC1BB8 page secure/non-secure attribution 8 1 read-write SEC1BB9 page secure/non-secure attribution 9 1 read-write SEC1BB10 page secure/non-secure attribution 10 1 read-write SEC1BB11 page secure/non-secure attribution 11 1 read-write SEC1BB12 page secure/non-secure attribution 12 1 read-write SEC1BB13 page secure/non-secure attribution 13 1 read-write SEC1BB14 page secure/non-secure attribution 14 1 read-write SEC1BB15 page secure/non-secure attribution 15 1 read-write SEC1BB16 page secure/non-secure attribution 16 1 read-write SEC1BB17 page secure/non-secure attribution 17 1 read-write SEC1BB18 page secure/non-secure attribution 18 1 read-write SEC1BB19 page secure/non-secure attribution 19 1 read-write SEC1BB20 page secure/non-secure attribution 20 1 read-write SEC1BB21 page secure/non-secure attribution 21 1 read-write SEC1BB22 page secure/non-secure attribution 22 1 read-write SEC1BB23 page secure/non-secure attribution 23 1 read-write SEC1BB24 page secure/non-secure attribution 24 1 read-write SEC1BB25 page secure/non-secure attribution 25 1 read-write SEC1BB26 page secure/non-secure attribution 26 1 read-write SEC1BB27 page secure/non-secure attribution 27 1 read-write SEC1BB28 page secure/non-secure attribution 28 1 read-write SEC1BB29 page secure/non-secure attribution 29 1 read-write SEC1BB30 page secure/non-secure attribution 30 1 read-write SEC1BB31 page secure/non-secure attribution 31 1 read-write SEC1BBR4 SEC1BBR4 FLASH secure block based bank 1 register 4 0x8C 0x20 0x00000000 0xFFFFFFFF SEC1BB0 page secure/non-secure attribution 0 1 read-write SEC1BB1 page secure/non-secure attribution 1 1 read-write SEC1BB2 page secure/non-secure attribution 2 1 read-write SEC1BB3 page secure/non-secure attribution 3 1 read-write SEC1BB4 page secure/non-secure attribution 4 1 read-write SEC1BB5 page secure/non-secure attribution 5 1 read-write SEC1BB6 page secure/non-secure attribution 6 1 read-write SEC1BB7 page secure/non-secure attribution 7 1 read-write SEC1BB8 page secure/non-secure attribution 8 1 read-write SEC1BB9 page secure/non-secure attribution 9 1 read-write SEC1BB10 page secure/non-secure attribution 10 1 read-write SEC1BB11 page secure/non-secure attribution 11 1 read-write SEC1BB12 page secure/non-secure attribution 12 1 read-write SEC1BB13 page secure/non-secure attribution 13 1 read-write SEC1BB14 page secure/non-secure attribution 14 1 read-write SEC1BB15 page secure/non-secure attribution 15 1 read-write SEC1BB16 page secure/non-secure attribution 16 1 read-write SEC1BB17 page secure/non-secure attribution 17 1 read-write SEC1BB18 page secure/non-secure attribution 18 1 read-write SEC1BB19 page secure/non-secure attribution 19 1 read-write SEC1BB20 page secure/non-secure attribution 20 1 read-write SEC1BB21 page secure/non-secure attribution 21 1 read-write SEC1BB22 page secure/non-secure attribution 22 1 read-write SEC1BB23 page secure/non-secure attribution 23 1 read-write SEC1BB24 page secure/non-secure attribution 24 1 read-write SEC1BB25 page secure/non-secure attribution 25 1 read-write SEC1BB26 page secure/non-secure attribution 26 1 read-write SEC1BB27 page secure/non-secure attribution 27 1 read-write SEC1BB28 page secure/non-secure attribution 28 1 read-write SEC1BB29 page secure/non-secure attribution 29 1 read-write SEC1BB30 page secure/non-secure attribution 30 1 read-write SEC1BB31 page secure/non-secure attribution 31 1 read-write SEC2BBR1 SEC2BBR1 FLASH secure block based bank 2 register 1 0xA0 0x20 0x00000000 0xFFFFFFFF SEC2BB0 page secure/non-secure attribution 0 1 read-write SEC2BB1 page secure/non-secure attribution 1 1 read-write SEC2BB2 page secure/non-secure attribution 2 1 read-write SEC2BB3 page secure/non-secure attribution 3 1 read-write SEC2BB4 page secure/non-secure attribution 4 1 read-write SEC2BB5 page secure/non-secure attribution 5 1 read-write SEC2BB6 page secure/non-secure attribution 6 1 read-write SEC2BB7 page secure/non-secure attribution 7 1 read-write SEC2BB8 page secure/non-secure attribution 8 1 read-write SEC2BB9 page secure/non-secure attribution 9 1 read-write SEC2BB10 page secure/non-secure attribution 10 1 read-write SEC2BB11 page secure/non-secure attribution 11 1 read-write SEC2BB12 page secure/non-secure attribution 12 1 read-write SEC2BB13 page secure/non-secure attribution 13 1 read-write SEC2BB14 page secure/non-secure attribution 14 1 read-write SEC2BB15 page secure/non-secure attribution 15 1 read-write SEC2BB16 page secure/non-secure attribution 16 1 read-write SEC2BB17 page secure/non-secure attribution 17 1 read-write SEC2BB18 page secure/non-secure attribution 18 1 read-write SEC2BB19 page secure/non-secure attribution 19 1 read-write SEC2BB20 page secure/non-secure attribution 20 1 read-write SEC2BB21 page secure/non-secure attribution 21 1 read-write SEC2BB22 page secure/non-secure attribution 22 1 read-write SEC2BB23 page secure/non-secure attribution 23 1 read-write SEC2BB24 page secure/non-secure attribution 24 1 read-write SEC2BB25 page secure/non-secure attribution 25 1 read-write SEC2BB26 page secure/non-secure attribution 26 1 read-write SEC2BB27 page secure/non-secure attribution 27 1 read-write SEC2BB28 page secure/non-secure attribution 28 1 read-write SEC2BB29 page secure/non-secure attribution 29 1 read-write SEC2BB30 page secure/non-secure attribution 30 1 read-write SEC2BB31 page secure/non-secure attribution 31 1 read-write SEC2BBR2 SEC2BBR2 FLASH secure block based bank 2 register 2 0xA4 0x20 0x00000000 0xFFFFFFFF SEC2BB0 page secure/non-secure attribution 0 1 read-write SEC2BB1 page secure/non-secure attribution 1 1 read-write SEC2BB2 page secure/non-secure attribution 2 1 read-write SEC2BB3 page secure/non-secure attribution 3 1 read-write SEC2BB4 page secure/non-secure attribution 4 1 read-write SEC2BB5 page secure/non-secure attribution 5 1 read-write SEC2BB6 page secure/non-secure attribution 6 1 read-write SEC2BB7 page secure/non-secure attribution 7 1 read-write SEC2BB8 page secure/non-secure attribution 8 1 read-write SEC2BB9 page secure/non-secure attribution 9 1 read-write SEC2BB10 page secure/non-secure attribution 10 1 read-write SEC2BB11 page secure/non-secure attribution 11 1 read-write SEC2BB12 page secure/non-secure attribution 12 1 read-write SEC2BB13 page secure/non-secure attribution 13 1 read-write SEC2BB14 page secure/non-secure attribution 14 1 read-write SEC2BB15 page secure/non-secure attribution 15 1 read-write SEC2BB16 page secure/non-secure attribution 16 1 read-write SEC2BB17 page secure/non-secure attribution 17 1 read-write SEC2BB18 page secure/non-secure attribution 18 1 read-write SEC2BB19 page secure/non-secure attribution 19 1 read-write SEC2BB20 page secure/non-secure attribution 20 1 read-write SEC2BB21 page secure/non-secure attribution 21 1 read-write SEC2BB22 page secure/non-secure attribution 22 1 read-write SEC2BB23 page secure/non-secure attribution 23 1 read-write SEC2BB24 page secure/non-secure attribution 24 1 read-write SEC2BB25 page secure/non-secure attribution 25 1 read-write SEC2BB26 page secure/non-secure attribution 26 1 read-write SEC2BB27 page secure/non-secure attribution 27 1 read-write SEC2BB28 page secure/non-secure attribution 28 1 read-write SEC2BB29 page secure/non-secure attribution 29 1 read-write SEC2BB30 page secure/non-secure attribution 30 1 read-write SEC2BB31 page secure/non-secure attribution 31 1 read-write SEC2BBR3 SEC2BBR3 FLASH secure block based bank 2 register 3 0xA8 0x20 0x00000000 0xFFFFFFFF SEC2BB0 page secure/non-secure attribution 0 1 read-write SEC2BB1 page secure/non-secure attribution 1 1 read-write SEC2BB2 page secure/non-secure attribution 2 1 read-write SEC2BB3 page secure/non-secure attribution 3 1 read-write SEC2BB4 page secure/non-secure attribution 4 1 read-write SEC2BB5 page secure/non-secure attribution 5 1 read-write SEC2BB6 page secure/non-secure attribution 6 1 read-write SEC2BB7 page secure/non-secure attribution 7 1 read-write SEC2BB8 page secure/non-secure attribution 8 1 read-write SEC2BB9 page secure/non-secure attribution 9 1 read-write SEC2BB10 page secure/non-secure attribution 10 1 read-write SEC2BB11 page secure/non-secure attribution 11 1 read-write SEC2BB12 page secure/non-secure attribution 12 1 read-write SEC2BB13 page secure/non-secure attribution 13 1 read-write SEC2BB14 page secure/non-secure attribution 14 1 read-write SEC2BB15 page secure/non-secure attribution 15 1 read-write SEC2BB16 page secure/non-secure attribution 16 1 read-write SEC2BB17 page secure/non-secure attribution 17 1 read-write SEC2BB18 page secure/non-secure attribution 18 1 read-write SEC2BB19 page secure/non-secure attribution 19 1 read-write SEC2BB20 page secure/non-secure attribution 20 1 read-write SEC2BB21 page secure/non-secure attribution 21 1 read-write SEC2BB22 page secure/non-secure attribution 22 1 read-write SEC2BB23 page secure/non-secure attribution 23 1 read-write SEC2BB24 page secure/non-secure attribution 24 1 read-write SEC2BB25 page secure/non-secure attribution 25 1 read-write SEC2BB26 page secure/non-secure attribution 26 1 read-write SEC2BB27 page secure/non-secure attribution 27 1 read-write SEC2BB28 page secure/non-secure attribution 28 1 read-write SEC2BB29 page secure/non-secure attribution 29 1 read-write SEC2BB30 page secure/non-secure attribution 30 1 read-write SEC2BB31 page secure/non-secure attribution 31 1 read-write SEC2BBR4 SEC2BBR4 FLASH secure block based bank 2 register 4 0xAC 0x20 0x00000000 0xFFFFFFFF SEC2BB0 page secure/non-secure attribution 0 1 read-write SEC2BB1 page secure/non-secure attribution 1 1 read-write SEC2BB2 page secure/non-secure attribution 2 1 read-write SEC2BB3 page secure/non-secure attribution 3 1 read-write SEC2BB4 page secure/non-secure attribution 4 1 read-write SEC2BB5 page secure/non-secure attribution 5 1 read-write SEC2BB6 page secure/non-secure attribution 6 1 read-write SEC2BB7 page secure/non-secure attribution 7 1 read-write SEC2BB8 page secure/non-secure attribution 8 1 read-write SEC2BB9 page secure/non-secure attribution 9 1 read-write SEC2BB10 page secure/non-secure attribution 10 1 read-write SEC2BB11 page secure/non-secure attribution 11 1 read-write SEC2BB12 page secure/non-secure attribution 12 1 read-write SEC2BB13 page secure/non-secure attribution 13 1 read-write SEC2BB14 page secure/non-secure attribution 14 1 read-write SEC2BB15 page secure/non-secure attribution 15 1 read-write SEC2BB16 page secure/non-secure attribution 16 1 read-write SEC2BB17 page secure/non-secure attribution 17 1 read-write SEC2BB18 page secure/non-secure attribution 18 1 read-write SEC2BB19 page secure/non-secure attribution 19 1 read-write SEC2BB20 page secure/non-secure attribution 20 1 read-write SEC2BB21 page secure/non-secure attribution 21 1 read-write SEC2BB22 page secure/non-secure attribution 22 1 read-write SEC2BB23 page secure/non-secure attribution 23 1 read-write SEC2BB24 page secure/non-secure attribution 24 1 read-write SEC2BB25 page secure/non-secure attribution 25 1 read-write SEC2BB26 page secure/non-secure attribution 26 1 read-write SEC2BB27 page secure/non-secure attribution 27 1 read-write SEC2BB28 page secure/non-secure attribution 28 1 read-write SEC2BB29 page secure/non-secure attribution 29 1 read-write SEC2BB30 page secure/non-secure attribution 30 1 read-write SEC2BB31 page secure/non-secure attribution 31 1 read-write SECHDPCR SECHDPCR FLASH secure HDP control register 0xC0 0x20 0x00000000 0xFFFFFFFF HDP1_ACCDIS HDP1 area access disable When set, this bit is only cleared by a system reset. 0 1 read-write HDP2_ACCDIS HDP2 area access disable When set, this bit is only cleared by a system reset. 1 1 read-write PRIVCFGR PRIVCFGR FLASH privilege configuration register 0xC4 0x20 0x00000000 0xFFFFFFFF SPRIV Privileged protection for secure registers This bit can be accessed only when TrustZone is enabled (TZENÂ =Â 1). This bit can be read by both privileged or unprivileged, secure and non-secure access. The SPRIV bit can be written only by a secure privileged access. A non-secure write access on SPRIV bit is ignored. A secure unprivileged write access on SPRIV bit is ignored. 0 1 read-write NSPRIV Privileged protection for non-secure registers This bit can be read by both privileged or unprivileged, secure and non-secure access. The NSPRIV bit can be written by a secure or non-secure privileged access. A secure or non-secure unprivileged write access on NSPRIV bit is ignored. 1 1 read-write PRIV1BBR1 PRIV1BBR1 FLASH privilege block based bank 1 register 1 0xD0 0x20 0x00000000 0xFFFFFFFF PRIV1BB0 page privileged/unprivileged attribution 0 1 read-write PRIV1BB1 page privileged/unprivileged attribution 1 1 read-write PRIV1BB2 page privileged/unprivileged attribution 2 1 read-write PRIV1BB3 page privileged/unprivileged attribution 3 1 read-write PRIV1BB4 page privileged/unprivileged attribution 4 1 read-write PRIV1BB5 page privileged/unprivileged attribution 5 1 read-write PRIV1BB6 page privileged/unprivileged attribution 6 1 read-write PRIV1BB7 page privileged/unprivileged attribution 7 1 read-write PRIV1BB8 page privileged/unprivileged attribution 8 1 read-write PRIV1BB9 page privileged/unprivileged attribution 9 1 read-write PRIV1BB10 page privileged/unprivileged attribution 10 1 read-write PRIV1BB11 page privileged/unprivileged attribution 11 1 read-write PRIV1BB12 page privileged/unprivileged attribution 12 1 read-write PRIV1BB13 page privileged/unprivileged attribution 13 1 read-write PRIV1BB14 page privileged/unprivileged attribution 14 1 read-write PRIV1BB15 page privileged/unprivileged attribution 15 1 read-write PRIV1BB16 page privileged/unprivileged attribution 16 1 read-write PRIV1BB17 page privileged/unprivileged attribution 17 1 read-write PRIV1BB18 page privileged/unprivileged attribution 18 1 read-write PRIV1BB19 page privileged/unprivileged attribution 19 1 read-write PRIV1BB20 page privileged/unprivileged attribution 20 1 read-write PRIV1BB21 page privileged/unprivileged attribution 21 1 read-write PRIV1BB22 page privileged/unprivileged attribution 22 1 read-write PRIV1BB23 page privileged/unprivileged attribution 23 1 read-write PRIV1BB24 page privileged/unprivileged attribution 24 1 read-write PRIV1BB25 page privileged/unprivileged attribution 25 1 read-write PRIV1BB26 page privileged/unprivileged attribution 26 1 read-write PRIV1BB27 page privileged/unprivileged attribution 27 1 read-write PRIV1BB28 page privileged/unprivileged attribution 28 1 read-write PRIV1BB29 page privileged/unprivileged attribution 29 1 read-write PRIV1BB30 page privileged/unprivileged attribution 30 1 read-write PRIV1BB31 page privileged/unprivileged attribution 31 1 read-write PRIV1BBR2 PRIV1BBR2 FLASH privilege block based bank 1 register 2 0xD4 0x20 0x00000000 0xFFFFFFFF PRIV1BB0 page privileged/unprivileged attribution 0 1 read-write PRIV1BB1 page privileged/unprivileged attribution 1 1 read-write PRIV1BB2 page privileged/unprivileged attribution 2 1 read-write PRIV1BB3 page privileged/unprivileged attribution 3 1 read-write PRIV1BB4 page privileged/unprivileged attribution 4 1 read-write PRIV1BB5 page privileged/unprivileged attribution 5 1 read-write PRIV1BB6 page privileged/unprivileged attribution 6 1 read-write PRIV1BB7 page privileged/unprivileged attribution 7 1 read-write PRIV1BB8 page privileged/unprivileged attribution 8 1 read-write PRIV1BB9 page privileged/unprivileged attribution 9 1 read-write PRIV1BB10 page privileged/unprivileged attribution 10 1 read-write PRIV1BB11 page privileged/unprivileged attribution 11 1 read-write PRIV1BB12 page privileged/unprivileged attribution 12 1 read-write PRIV1BB13 page privileged/unprivileged attribution 13 1 read-write PRIV1BB14 page privileged/unprivileged attribution 14 1 read-write PRIV1BB15 page privileged/unprivileged attribution 15 1 read-write PRIV1BB16 page privileged/unprivileged attribution 16 1 read-write PRIV1BB17 page privileged/unprivileged attribution 17 1 read-write PRIV1BB18 page privileged/unprivileged attribution 18 1 read-write PRIV1BB19 page privileged/unprivileged attribution 19 1 read-write PRIV1BB20 page privileged/unprivileged attribution 20 1 read-write PRIV1BB21 page privileged/unprivileged attribution 21 1 read-write PRIV1BB22 page privileged/unprivileged attribution 22 1 read-write PRIV1BB23 page privileged/unprivileged attribution 23 1 read-write PRIV1BB24 page privileged/unprivileged attribution 24 1 read-write PRIV1BB25 page privileged/unprivileged attribution 25 1 read-write PRIV1BB26 page privileged/unprivileged attribution 26 1 read-write PRIV1BB27 page privileged/unprivileged attribution 27 1 read-write PRIV1BB28 page privileged/unprivileged attribution 28 1 read-write PRIV1BB29 page privileged/unprivileged attribution 29 1 read-write PRIV1BB30 page privileged/unprivileged attribution 30 1 read-write PRIV1BB31 page privileged/unprivileged attribution 31 1 read-write PRIV1BBR3 PRIV1BBR3 FLASH privilege block based bank 1 register 3 0xD8 0x20 0x00000000 0xFFFFFFFF PRIV1BB0 page privileged/unprivileged attribution 0 1 read-write PRIV1BB1 page privileged/unprivileged attribution 1 1 read-write PRIV1BB2 page privileged/unprivileged attribution 2 1 read-write PRIV1BB3 page privileged/unprivileged attribution 3 1 read-write PRIV1BB4 page privileged/unprivileged attribution 4 1 read-write PRIV1BB5 page privileged/unprivileged attribution 5 1 read-write PRIV1BB6 page privileged/unprivileged attribution 6 1 read-write PRIV1BB7 page privileged/unprivileged attribution 7 1 read-write PRIV1BB8 page privileged/unprivileged attribution 8 1 read-write PRIV1BB9 page privileged/unprivileged attribution 9 1 read-write PRIV1BB10 page privileged/unprivileged attribution 10 1 read-write PRIV1BB11 page privileged/unprivileged attribution 11 1 read-write PRIV1BB12 page privileged/unprivileged attribution 12 1 read-write PRIV1BB13 page privileged/unprivileged attribution 13 1 read-write PRIV1BB14 page privileged/unprivileged attribution 14 1 read-write PRIV1BB15 page privileged/unprivileged attribution 15 1 read-write PRIV1BB16 page privileged/unprivileged attribution 16 1 read-write PRIV1BB17 page privileged/unprivileged attribution 17 1 read-write PRIV1BB18 page privileged/unprivileged attribution 18 1 read-write PRIV1BB19 page privileged/unprivileged attribution 19 1 read-write PRIV1BB20 page privileged/unprivileged attribution 20 1 read-write PRIV1BB21 page privileged/unprivileged attribution 21 1 read-write PRIV1BB22 page privileged/unprivileged attribution 22 1 read-write PRIV1BB23 page privileged/unprivileged attribution 23 1 read-write PRIV1BB24 page privileged/unprivileged attribution 24 1 read-write PRIV1BB25 page privileged/unprivileged attribution 25 1 read-write PRIV1BB26 page privileged/unprivileged attribution 26 1 read-write PRIV1BB27 page privileged/unprivileged attribution 27 1 read-write PRIV1BB28 page privileged/unprivileged attribution 28 1 read-write PRIV1BB29 page privileged/unprivileged attribution 29 1 read-write PRIV1BB30 page privileged/unprivileged attribution 30 1 read-write PRIV1BB31 page privileged/unprivileged attribution 31 1 read-write PRIV1BBR4 PRIV1BBR4 FLASH privilege block based bank 1 register 4 0xDC 0x20 0x00000000 0xFFFFFFFF PRIV1BB0 page privileged/unprivileged attribution 0 1 read-write PRIV1BB1 page privileged/unprivileged attribution 1 1 read-write PRIV1BB2 page privileged/unprivileged attribution 2 1 read-write PRIV1BB3 page privileged/unprivileged attribution 3 1 read-write PRIV1BB4 page privileged/unprivileged attribution 4 1 read-write PRIV1BB5 page privileged/unprivileged attribution 5 1 read-write PRIV1BB6 page privileged/unprivileged attribution 6 1 read-write PRIV1BB7 page privileged/unprivileged attribution 7 1 read-write PRIV1BB8 page privileged/unprivileged attribution 8 1 read-write PRIV1BB9 page privileged/unprivileged attribution 9 1 read-write PRIV1BB10 page privileged/unprivileged attribution 10 1 read-write PRIV1BB11 page privileged/unprivileged attribution 11 1 read-write PRIV1BB12 page privileged/unprivileged attribution 12 1 read-write PRIV1BB13 page privileged/unprivileged attribution 13 1 read-write PRIV1BB14 page privileged/unprivileged attribution 14 1 read-write PRIV1BB15 page privileged/unprivileged attribution 15 1 read-write PRIV1BB16 page privileged/unprivileged attribution 16 1 read-write PRIV1BB17 page privileged/unprivileged attribution 17 1 read-write PRIV1BB18 page privileged/unprivileged attribution 18 1 read-write PRIV1BB19 page privileged/unprivileged attribution 19 1 read-write PRIV1BB20 page privileged/unprivileged attribution 20 1 read-write PRIV1BB21 page privileged/unprivileged attribution 21 1 read-write PRIV1BB22 page privileged/unprivileged attribution 22 1 read-write PRIV1BB23 page privileged/unprivileged attribution 23 1 read-write PRIV1BB24 page privileged/unprivileged attribution 24 1 read-write PRIV1BB25 page privileged/unprivileged attribution 25 1 read-write PRIV1BB26 page privileged/unprivileged attribution 26 1 read-write PRIV1BB27 page privileged/unprivileged attribution 27 1 read-write PRIV1BB28 page privileged/unprivileged attribution 28 1 read-write PRIV1BB29 page privileged/unprivileged attribution 29 1 read-write PRIV1BB30 page privileged/unprivileged attribution 30 1 read-write PRIV1BB31 page privileged/unprivileged attribution 31 1 read-write PRIV2BBR1 PRIV2BBR1 FLASH privilege block based bank 2 register 1 0xF0 0x20 0x00000000 0xFFFFFFFF PRIV2BB0 page privileged/unprivileged attribution 0 1 read-write PRIV2BB1 page privileged/unprivileged attribution 1 1 read-write PRIV2BB2 page privileged/unprivileged attribution 2 1 read-write PRIV2BB3 page privileged/unprivileged attribution 3 1 read-write PRIV2BB4 page privileged/unprivileged attribution 4 1 read-write PRIV2BB5 page privileged/unprivileged attribution 5 1 read-write PRIV2BB6 page privileged/unprivileged attribution 6 1 read-write PRIV2BB7 page privileged/unprivileged attribution 7 1 read-write PRIV2BB8 page privileged/unprivileged attribution 8 1 read-write PRIV2BB9 page privileged/unprivileged attribution 9 1 read-write PRIV2BB10 page privileged/unprivileged attribution 10 1 read-write PRIV2BB11 page privileged/unprivileged attribution 11 1 read-write PRIV2BB12 page privileged/unprivileged attribution 12 1 read-write PRIV2BB13 page privileged/unprivileged attribution 13 1 read-write PRIV2BB14 page privileged/unprivileged attribution 14 1 read-write PRIV2BB15 page privileged/unprivileged attribution 15 1 read-write PRIV2BB16 page privileged/unprivileged attribution 16 1 read-write PRIV2BB17 page privileged/unprivileged attribution 17 1 read-write PRIV2BB18 page privileged/unprivileged attribution 18 1 read-write PRIV2BB19 page privileged/unprivileged attribution 19 1 read-write PRIV2BB20 page privileged/unprivileged attribution 20 1 read-write PRIV2BB21 page privileged/unprivileged attribution 21 1 read-write PRIV2BB22 page privileged/unprivileged attribution 22 1 read-write PRIV2BB23 page privileged/unprivileged attribution 23 1 read-write PRIV2BB24 page privileged/unprivileged attribution 24 1 read-write PRIV2BB25 page privileged/unprivileged attribution 25 1 read-write PRIV2BB26 page privileged/unprivileged attribution 26 1 read-write PRIV2BB27 page privileged/unprivileged attribution 27 1 read-write PRIV2BB28 page privileged/unprivileged attribution 28 1 read-write PRIV2BB29 page privileged/unprivileged attribution 29 1 read-write PRIV2BB30 page privileged/unprivileged attribution 30 1 read-write PRIV2BB31 page privileged/unprivileged attribution 31 1 read-write PRIV2BBR2 PRIV2BBR2 FLASH privilege block based bank 2 register 2 0xF4 0x20 0x00000000 0xFFFFFFFF PRIV2BB0 page privileged/unprivileged attribution 0 1 read-write PRIV2BB1 page privileged/unprivileged attribution 1 1 read-write PRIV2BB2 page privileged/unprivileged attribution 2 1 read-write PRIV2BB3 page privileged/unprivileged attribution 3 1 read-write PRIV2BB4 page privileged/unprivileged attribution 4 1 read-write PRIV2BB5 page privileged/unprivileged attribution 5 1 read-write PRIV2BB6 page privileged/unprivileged attribution 6 1 read-write PRIV2BB7 page privileged/unprivileged attribution 7 1 read-write PRIV2BB8 page privileged/unprivileged attribution 8 1 read-write PRIV2BB9 page privileged/unprivileged attribution 9 1 read-write PRIV2BB10 page privileged/unprivileged attribution 10 1 read-write PRIV2BB11 page privileged/unprivileged attribution 11 1 read-write PRIV2BB12 page privileged/unprivileged attribution 12 1 read-write PRIV2BB13 page privileged/unprivileged attribution 13 1 read-write PRIV2BB14 page privileged/unprivileged attribution 14 1 read-write PRIV2BB15 page privileged/unprivileged attribution 15 1 read-write PRIV2BB16 page privileged/unprivileged attribution 16 1 read-write PRIV2BB17 page privileged/unprivileged attribution 17 1 read-write PRIV2BB18 page privileged/unprivileged attribution 18 1 read-write PRIV2BB19 page privileged/unprivileged attribution 19 1 read-write PRIV2BB20 page privileged/unprivileged attribution 20 1 read-write PRIV2BB21 page privileged/unprivileged attribution 21 1 read-write PRIV2BB22 page privileged/unprivileged attribution 22 1 read-write PRIV2BB23 page privileged/unprivileged attribution 23 1 read-write PRIV2BB24 page privileged/unprivileged attribution 24 1 read-write PRIV2BB25 page privileged/unprivileged attribution 25 1 read-write PRIV2BB26 page privileged/unprivileged attribution 26 1 read-write PRIV2BB27 page privileged/unprivileged attribution 27 1 read-write PRIV2BB28 page privileged/unprivileged attribution 28 1 read-write PRIV2BB29 page privileged/unprivileged attribution 29 1 read-write PRIV2BB30 page privileged/unprivileged attribution 30 1 read-write PRIV2BB31 page privileged/unprivileged attribution 31 1 read-write PRIV2BBR3 PRIV2BBR3 FLASH privilege block based bank 2 register 3 0xF8 0x20 0x00000000 0xFFFFFFFF PRIV2BB0 page privileged/unprivileged attribution 0 1 read-write PRIV2BB1 page privileged/unprivileged attribution 1 1 read-write PRIV2BB2 page privileged/unprivileged attribution 2 1 read-write PRIV2BB3 page privileged/unprivileged attribution 3 1 read-write PRIV2BB4 page privileged/unprivileged attribution 4 1 read-write PRIV2BB5 page privileged/unprivileged attribution 5 1 read-write PRIV2BB6 page privileged/unprivileged attribution 6 1 read-write PRIV2BB7 page privileged/unprivileged attribution 7 1 read-write PRIV2BB8 page privileged/unprivileged attribution 8 1 read-write PRIV2BB9 page privileged/unprivileged attribution 9 1 read-write PRIV2BB10 page privileged/unprivileged attribution 10 1 read-write PRIV2BB11 page privileged/unprivileged attribution 11 1 read-write PRIV2BB12 page privileged/unprivileged attribution 12 1 read-write PRIV2BB13 page privileged/unprivileged attribution 13 1 read-write PRIV2BB14 page privileged/unprivileged attribution 14 1 read-write PRIV2BB15 page privileged/unprivileged attribution 15 1 read-write PRIV2BB16 page privileged/unprivileged attribution 16 1 read-write PRIV2BB17 page privileged/unprivileged attribution 17 1 read-write PRIV2BB18 page privileged/unprivileged attribution 18 1 read-write PRIV2BB19 page privileged/unprivileged attribution 19 1 read-write PRIV2BB20 page privileged/unprivileged attribution 20 1 read-write PRIV2BB21 page privileged/unprivileged attribution 21 1 read-write PRIV2BB22 page privileged/unprivileged attribution 22 1 read-write PRIV2BB23 page privileged/unprivileged attribution 23 1 read-write PRIV2BB24 page privileged/unprivileged attribution 24 1 read-write PRIV2BB25 page privileged/unprivileged attribution 25 1 read-write PRIV2BB26 page privileged/unprivileged attribution 26 1 read-write PRIV2BB27 page privileged/unprivileged attribution 27 1 read-write PRIV2BB28 page privileged/unprivileged attribution 28 1 read-write PRIV2BB29 page privileged/unprivileged attribution 29 1 read-write PRIV2BB30 page privileged/unprivileged attribution 30 1 read-write PRIV2BB31 page privileged/unprivileged attribution 31 1 read-write PRIV2BBR4 PRIV2BBR4 FLASH privilege block based bank 2 register 4 0xFC 0x20 0x00000000 0xFFFFFFFF PRIV2BB0 page privileged/unprivileged attribution 0 1 read-write PRIV2BB1 page privileged/unprivileged attribution 1 1 read-write PRIV2BB2 page privileged/unprivileged attribution 2 1 read-write PRIV2BB3 page privileged/unprivileged attribution 3 1 read-write PRIV2BB4 page privileged/unprivileged attribution 4 1 read-write PRIV2BB5 page privileged/unprivileged attribution 5 1 read-write PRIV2BB6 page privileged/unprivileged attribution 6 1 read-write PRIV2BB7 page privileged/unprivileged attribution 7 1 read-write PRIV2BB8 page privileged/unprivileged attribution 8 1 read-write PRIV2BB9 page privileged/unprivileged attribution 9 1 read-write PRIV2BB10 page privileged/unprivileged attribution 10 1 read-write PRIV2BB11 page privileged/unprivileged attribution 11 1 read-write PRIV2BB12 page privileged/unprivileged attribution 12 1 read-write PRIV2BB13 page privileged/unprivileged attribution 13 1 read-write PRIV2BB14 page privileged/unprivileged attribution 14 1 read-write PRIV2BB15 page privileged/unprivileged attribution 15 1 read-write PRIV2BB16 page privileged/unprivileged attribution 16 1 read-write PRIV2BB17 page privileged/unprivileged attribution 17 1 read-write PRIV2BB18 page privileged/unprivileged attribution 18 1 read-write PRIV2BB19 page privileged/unprivileged attribution 19 1 read-write PRIV2BB20 page privileged/unprivileged attribution 20 1 read-write PRIV2BB21 page privileged/unprivileged attribution 21 1 read-write PRIV2BB22 page privileged/unprivileged attribution 22 1 read-write PRIV2BB23 page privileged/unprivileged attribution 23 1 read-write PRIV2BB24 page privileged/unprivileged attribution 24 1 read-write PRIV2BB25 page privileged/unprivileged attribution 25 1 read-write PRIV2BB26 page privileged/unprivileged attribution 26 1 read-write PRIV2BB27 page privileged/unprivileged attribution 27 1 read-write PRIV2BB28 page privileged/unprivileged attribution 28 1 read-write PRIV2BB29 page privileged/unprivileged attribution 29 1 read-write PRIV2BB30 page privileged/unprivileged attribution 30 1 read-write PRIV2BB31 page privileged/unprivileged attribution 31 1 read-write SEC_FLASH 0x50022000 GPIOA General-purpose I/Os GPIO 0x42020000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xABFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x64000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 0x00000000 0xFFFF0000 16 0x1 0-15 ID%s Port input data pin %s 0 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 OD%s Port output data pin %s 0 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 BS%s Port x set pin %s 0 1 write-only BitSet Set Sets the corresponding ODx bit 1 16 0x1 0-15 BR%s Port x reset pin %s 16 1 write-only BitReset Reset Resets the corresponding ODx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 AFSEL%s Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 AFSEL%s Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write BRR BRR GPIO port bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 BR%s Port x reset pin %s 0 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 HSLV%s Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write HighSpeedLowVoltage Disabled I/O speed optimization disabled 0 Enabled I/O speed optimization enabled 1 SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 SEC_GPIOA 0x52020000 GPIOB General-purpose I/Os GPIO 0x42020400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xFFFFFEBF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x000000C0 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x00000100 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write SEC_GPIOB 0x52020400 GPIOC General-purpose I/Os GPIO 0x42020800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write SEC_GPIOC 0x52020800 GPIOD 0x42020C00 SEC_GPIOD 0x52020C00 GPIOE 0x42021000 SEC_GPIOE 0x52021000 GPIOF 0x42021400 SEC_GPIOF 0x52021400 GPIOG 0x42021800 SEC_GPIOG 0x52021800 GPIOH General-purpose I/Os GPIO 0x42021C00 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write SEC_GPIOH 0x52021C00 GPIOI General-purpose I/Os GPIO 0x42022000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write SEC_GPIOI 0x52022000 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 55 I2C1_ER I2C1 error interrupt 56 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match interrupt enable (slave only) 3 1 ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received interrupt enable 4 1 NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE STOP detection Interrupt enable 5 1 STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable 6 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable 7 1 ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter 8 4 DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF 12 1 ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control 16 1 SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable 17 1 NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from STOP enable 18 1 WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus Host address enable 20 1 SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus Device Default address enable 21 1 SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBUS alert enable 22 1 ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable 23 1 PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 FMP Fast-mode Plus 20 mA drive enable 24 1 FMP Disabled 20 mA I/O drive disabled 0 Enabled 20 mA I/O drive enabled 1 ADDRACLR Address match flag (ADDR) automatic clear 30 1 ADDRACLR Disabled ADDR flag is set by hardware, cleared by software 0 Enabled ADDR flag remains cleared by hardware 1 STOPFACLR STOP detection flag (STOPF) automatic clear 31 1 STOPFACLR Disabled STOPF flag is set by hardware, cleared by software 0 Enabled STOPF flag remains cleared by hardware 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 AUTOEND Automatic end mode (master mode) 25 1 AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 RELOAD NBYTES reload mode 24 1 RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 NBYTES Number of bytes 16 8 0 255 NACK NACK generation (slave mode) 15 1 oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 STOP Stop generation (master mode) 14 1 oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 START Start generation 13 1 oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 ADD10 10-bit addressing mode (master mode) 11 1 ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 RD_WRN Transfer direction (master mode) 10 1 RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 SADD Slave address bit (master mode) 0 10 0 1023 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 0 1023 OA1MODE Own Address 1 10-bit mode 10 1 OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 0 127 OA2MSK Own Address 2 masks 8 3 OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and donât care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and donât care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and donât care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and donât care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and donât care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and donât care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and donât care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 0 255 SCLH SCL high period (master mode) 8 8 0 255 SDADEL Data hold time 16 4 0 15 SCLDEL Data setup time 20 4 0 15 PRESC Timing prescaler 28 4 0 15 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 0 4095 TIDLE Idle clock timeout detection 12 1 TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B 16 12 0 4095 TEXTEN Extended clock timeout enable 31 1 TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only 0 127 DIR Transfer direction (Slave mode) 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 BUSY Bus busy 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 ALERT SMBus alert 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 TIMEOUT Timeout or t_low detection flag 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 PECERR PEC Error in reception 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 OVR Overrun/Underrun (slave mode) 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 ARLO Arbitration lost 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 BERR Bus error 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 TCR Transfer Complete Reload 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TC Transfer Complete (master mode) 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 STOPF Stop detection flag 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 NACKF Not acknowledge received flag 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 ADDR Address matched (slave mode) 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 RXNE Receive data register not empty (receivers) 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 TXIS Transmit interrupt status (transmitters) 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 TXE Transmit data register empty (transmitters) 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 TIMOUTCF Timeout detection flag clear 12 1 oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 PECCF PEC Error flag clear 11 1 oneToClear PECCF Clear Clears the PEC flag in ISR register 1 OVRCF Overrun/Underrun flag clear 10 1 oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 ARLOCF Arbitration lost flag clear 9 1 oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 BERRCF Bus error flag clear 8 1 oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 STOPCF Stop detection flag clear 5 1 oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 NACKCF Not Acknowledge flag clear 4 1 oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 ADDRCF Address Matched flag clear 3 1 oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 0 255 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 0 255 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 0 255 AUTOCR AUTOCR I2C Autonomous mode control register 0x2C 0x20 read-write 0x00000000 TCDMAEN DMA request enable on Transfer Complete event 6 1 TCRDMAEN DMA request enable on Transfer Complete Reload event 7 1 TRIGSEL Trigger selection 16 4 TRIGPOL Trigger polarity 20 1 TRIGEN Trigger enable 21 1 SEC_I2C1 0x50005400 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 57 I2C2_ER I2C2 error interrupt 58 SEC_I2C2 0x50005800 I2C3 0x46002800 I2C3_EV I2C3 event interrupt 88 I2C3_ER I2C3 error interrupt 89 SEC_I2C3 0x56002800 I2C4 0x40008400 I2C4_ER I2C4 error interrupt 100 I2C4_EV I2C4 event interrupt 101 SEC_I2C4 0x50008400 ICACHE ICache ICache 0x40030400 0x0 0x400 registers ICACHE Instruction cache global interrupt 107 CR CR ICACHE control register 0x0 0x20 0x00000004 EN EN 0 1 read-write CACHEINV CACHEINV 1 1 write-only WAYSEL WAYSEL 2 1 read-write HITMEN HITMEN 16 1 read-write MISSMEN MISSMEN 17 1 read-write HITMRST HITMRST 18 1 read-write MISSMRST MISSMRST 19 1 read-write SR SR ICACHE status register 0x4 0x20 read-only 0x00000001 BUSYF BUSYF 0 1 BSYENDF BSYENDF 1 1 ERRF ERRF 2 1 IER IER ICACHE interrupt enable register 0x8 0x20 read-write 0x00000000 BSYENDIE BSYENDIE 1 1 ERRIE ERRIE 2 1 FCR FCR ICACHE flag clear register 0xC 0x20 write-only 0x00000000 CBSYENDF CBSYENDF 1 1 CERRF CERRF 2 1 HMONR HMONR ICACHE hit monitor register 0x10 0x20 read-only 0x00000000 HITMON HITMON 0 32 MMONR MMONR ICACHE miss monitor register 0x14 0x20 read-only 0x00000000 MISSMON MISSMON 0 16 CRR0 CRR0 ICACHE region configuration register 0x20 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 CRR1 CRR1 ICACHE region configuration register 0x24 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 CRR2 CRR2 ICACHE region configuration register 0x28 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 CRR3 CRR3 ICACHE region configuration register 0x2C 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 SEC_ICache 0x50030400 DCACHE DCACHE DCACHE 0x40031400 0x0 0x400 registers DCACHE Data cache global interrupt 111 CR CR DCACHE control register 0x0 0x20 0x00000000 EN EN 0 1 read-write CACHEINV CACHEINV 1 1 write-only CACHECMD CACHECMD 8 3 read-write STARTCMD STARTCMD 11 1 write-only RHITMEN RHITMEN 16 1 read-write RMISSMEN RMISSMEN 17 1 read-write RHITMRST RHITMRST 18 1 read-write RMISSMRST RMISSMRST 19 1 read-write WHITMEN WHITMEN 20 1 read-write WMISSMEN WMISSMEN 21 1 read-write WHITMRST WHITMRST 22 1 read-write WMISSMRST WMISSMRST 23 1 read-write HBURST HBURST 31 1 read-write SR SR DCACHE status register 0x4 0x20 read-only 0x00000001 BUSYF BUSYF 0 1 BSYENDF BSYENDF 1 1 ERRF ERRF 2 1 BUSYCMDF BUSYCMDF 3 1 CMDENDF CMDENDF 4 1 IER IER DCACHE interrupt enable register 0x8 0x20 read-write 0x00000000 BSYENDIE BSYENDIE 1 1 ERRIE ERRIE 2 1 CMDENDIE CMDENDIE 4 1 FCR FCR DCACHE flag clear register 0xC 0x20 write-only 0x00000000 CBSYENDF CBSYENDF 1 1 CERRF CERRF 2 1 CCMDENDF CCMDENDF 4 1 RHMONR RHMONR DCACHE read-hit monitor register 0x10 0x20 read-only 0x00000000 RHITMON RHITMON 0 32 RMMONR RMMONR DCACHE read-miss monitor register 0x14 0x20 read-only 0x00000000 MRISSMON RMISSMON 0 16 WHMONR WHMONR write-hit monitor register 0x20 0x20 read-only 0x00000000 WHITMON WHITMON 0 32 WMMONR WMMONR write-miss monitor register 0x24 0x20 read-only 0x00000000 WMISSMON WMISSMON 0 16 CMDRSADDRR CMDRSADDRR command range start address register 0x28 0x20 read-write 0x00000000 CMDSTARTADDR CMDSTARTADDR 0 32 CMDREADDRR CMDREADDRR command range start address register 0x2C 0x20 read-write 0x00000000 CMDENDADDR CMDENDADDR 0 32 SEC_DCACHE 0x50031400 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x10 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 0x10 read-write 0x00000000 PR Prescaler divider 0 4 RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x10 read-only 0x00000000 EWIF Watchdog Early interrupt flag 14 1 EWU Watchdog interrupt comparator value update 3 1 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x10 read-write 0x00000FFF WIN Watchdog counter window value 0 12 EWCR EWCR IWDG early wakeup interrupt register 0x14 0x10 read-write 0x00000000 EWIT Watchdog counter window value 0 12 EWIC Watchdog early interrupt acknowledge 14 1 EWIE Watchdog early interrupt enable 15 1 SEC_IWDG 0x50003000 LPTIM1 Low power timer LPTIM 0x46004400 0x0 0x400 registers LPTIM1 LPTIM1 global interrupt 67 ISR_output ISR_output Interrupt and Status Register (output mode) 0x0 0x20 read-only 0x00000000 DIEROK Interrupt enable register update OK 24 1 CMP2OK Compare register 2 update OK 19 1 CC2IF Compare 2 interrupt flag 9 1 REPOK Repetition register update Ok 8 1 UE LPTIM update event occurred 7 1 DOWN Counter direction change up to down 6 1 UP Counter direction change down to up 5 1 ARROK Autoreload register update OK 4 1 CMP1OK Compare register 1 update OK 3 1 EXTTRIG External trigger edge event 2 1 ARRM Autoreload match 1 1 CC1IF Compare 1 interrupt flag 0 1 ISR_input ISR_input Interrupt and Status Register (intput mode) ISR_output 0x0 0x20 read-only 0x00000000 DIEROK Interrupt enable register update OK 24 1 CC2OF Capture 2 over-capture flag 13 1 CC1OF Capture 1 over-capture flag 12 1 CC2IF Capture 2 interrupt flag 9 1 REPOK Repetition register update Ok 8 1 UE LPTIM update event occurred 7 1 DOWN Counter direction change up to down 6 1 UP Counter direction change down to up 5 1 ARROK Autoreload register update OK 4 1 EXTTRIG External trigger edge event 2 1 ARRM Autoreload match 1 1 CC1IF Compare 1 interrupt flag 0 1 ICR_output ICR_output Interrupt Clear Register (output mode) 0x4 0x20 write-only 0x00000000 DIEROKCF Interrupt enable register update OK clear flag 24 1 CMP2OKCF Compare register 2 update OK clear flag 19 1 CC2CF Capture/compare 2 clear flag 9 1 REPOKCF Repetition register update OK clear flag 8 1 UECF Update event clear flag 7 1 DOWNCF Direction change to down Clear Flag 6 1 UPCF Direction change to UP Clear Flag 5 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMP1OKCF Compare register 1 update OK Clear Flag 3 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 ARRMCF Autoreload match Clear Flag 1 1 CC1IF Capture/compare 1 clear flag 0 1 ICR_input ICR_input Interrupt Clear Register (intput mode) ICR_output 0x4 0x20 write-only 0x00000000 DIEROKCF Interrupt enable register update OK clear flag 24 1 CC2OCF Capture/compare 2 over-capture clear flag 13 1 CC1OCF Capture/compare 1 over-capture clear flag 12 1 CC2CF Capture/compare 2 clear flag 9 1 REPOKCF Repetition register update OK clear flag 8 1 UECF Update event clear flag 7 1 DOWNCF Direction change to down Clear Flag 6 1 UPCF Direction change to UP Clear Flag 5 1 ARROKCF Autoreload register update OK Clear Flag 4 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 ARRMCF Autoreload match Clear Flag 1 1 CC1IF Capture/compare 1 clear flag 0 1 DIER_output DIER_output LPTIM interrupt Enable Register (output mode) 0x8 0x20 read-write 0x00000000 UEDE Update event DMA request enable 23 1 CMP2OKIE Compare register 2 update OK interrupt enable 19 1 CC2IE Capture/compare 2 interrupt enable 9 1 REPOKIE REPOKIE 8 1 UEIE Update event interrupt enable 7 1 DOWNIE Direction change to down Interrupt Enable 6 1 UPIE Direction change to UP Interrupt Enable 5 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMP1OKIE Compare register 1 update OK Interrupt Enable 3 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 ARRMIE Autoreload match Interrupt Enable 1 1 CC1IF Capture/compare 1 clear flag 0 1 DIER_input DIER_input LPTIM interrupt Enable Register (intput mode) DIER_output 0x8 0x20 read-write 0x00000000 CC2DE Capture/compare 2 DMA request enable 25 1 CC1DE Capture/compare 1 DMA request enable 16 1 CC2OIE Capture/compare 2 over-capture interrupt enable 13 1 CC1OIE Capture/compare 1 over-capture interrupt enable 12 1 CC2IE Capture/compare 2 interrupt enable 9 1 REPOKIE REPOKIE 8 1 UEIE Update event interrupt enable 7 1 DOWNIE Direction change to down Interrupt Enable 6 1 UPIE Direction change to UP Interrupt Enable 5 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 ARRMIE Autoreload match Interrupt Enable 1 1 CC1IF Capture/compare 1 clear flag 0 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 COUNTMODE counter mode enabled 23 1 PRELOAD Registers update mode 22 1 WAVPOL Waveform shape polarity 21 1 WAVE Waveform shape 20 1 TIMOUT Timeout enable 19 1 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 PRESC Clock prescaler 9 3 TRGFLT Configurable digital filter for trigger 6 2 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 RSTARE Reset after read enable 4 1 COUNTRST Counter reset 3 1 CNTSTRT Timer start in continuous mode 2 1 SNGSTRT LPTIM start in single mode 1 1 ENABLE LPTIM Enable 0 1 CCR1 CCR1 Compare Register 0x14 0x20 read-write 0x00000000 CCR1 Capture/compare 1 value 0 16 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 CFGR2 CFGR2 LPTIM configuration register 2 0x24 0x20 read-write 0x00000000 IC2SEL LPTIM input capture 2 selection 20 2 IC1SEL LPTIM input capture 1 selection 16 2 IN2SEL LPTIM input 2 selection 4 2 IN1SEL LPTIM input 1 selection 0 2 RCR RCR LPTIM repetition register 0x28 0x20 read-write 0x00000000 REP Repetition register value 0 8 CCMR1 CCMR1 LPTIM capture/compare mode register 1 0x2C 0x20 read-write 0x00000000 CC1SEL Capture/compare 1 selection 0 1 CC1E Capture/compare 1 output enable 1 1 CC1P Capture/compare 1 output polarity 2 2 IC1PSC Input capture 1 prescaler 8 2 IC1F Input capture 1 filter 12 2 CC2SEL Capture/compare 2 selection 16 1 CC2E Capture/compare 2 output enable 17 1 CC2P Capture/compare 2 output polarity 18 2 IC2PSC Input capture 2 prescaler 24 2 IC2F Input capture 2 filter 28 2 CCR2 CCR2 LPTIM Compare Register 2 0x34 0x20 read-write 0x00000000 CCR2 Capture/compare 2 value 0 16 HWCFGR2 HWCFGR2 LPTIM peripheral hardware configuration register 2 0x3EC 0x20 read-only 0x00000000 CFG1 peripheral hardware configuration 1 0 4 CFG2 peripheral hardware configuration 2 8 8 CFG3 peripheral hardware configuration 3 16 1 HWCFGR1 HWCFGR1 LPTIM peripheral hardware configuration register 1 0x3F0 0x20 read-only 0x00000000 CFG1 peripheral hardware configuration 1 0 8 CFG2 peripheral hardware configuration 2 8 8 CFG3 peripheral hardware configuration 3 16 4 CFG4 peripheral hardware configuration 4 24 8 SEC_LPTIM1 0x56004400 LPTIM2 0x40009400 LPTIM2 LPTIM2 global interrupt 68 SEC_LPTIM2 0x50009400 LPTIM3 0x46004800 LPTIM3 LPTIM3 global interrupt 98 SEC_LPTIM3 0x56004800 LPTIM4 Low power timer LPTIM 0x46004C00 0x0 0x400 registers LPTIM4 LPTIM4 global interrupt 110 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DIEROK Interrupt enable register update OK 24 1 REPOK Repetition register update Ok 8 1 UE LPTIM update event occurred 7 1 DOWN Counter direction change up to down 6 1 UP Counter direction change down to up 5 1 ARROK Autoreload register update OK 4 1 CMP1OK Compare register 1 update OK 3 1 EXTTRIG External trigger edge event 2 1 ARRM Autoreload match 1 1 CC1IF Compare 1 interrupt flag 0 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DIEROKCF Interrupt enable register update OK clear flag 24 1 REPOKCF Repetition register update OK clear flag 8 1 UECF Update event clear flag 7 1 DOWNCF Direction change to down Clear Flag 6 1 UPCF Direction change to UP Clear Flag 5 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMP1OKCF Compare register 1 update OK Clear Flag 3 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 ARRMCF Autoreload match Clear Flag 1 1 CC1IF Capture/compare 1 clear flag 0 1 DIER DIER LPTIM interrupt Enable Register 0x8 0x20 read-write 0x00000000 REPOKIE REPOKIE 8 1 UEIE Update event interrupt enable 7 1 DOWNIE Direction change to down Interrupt Enable 6 1 UPIE Direction change to UP Interrupt Enable 5 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMP1OKIE Compare register 1 update OK Interrupt Enable 3 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 ARRMIE Autoreload match Interrupt Enable 1 1 CC1IF Capture/compare 1 clear flag 0 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 COUNTMODE counter mode enabled 23 1 PRELOAD Registers update mode 22 1 WAVPOL Waveform shape polarity 21 1 WAVE Waveform shape 20 1 TIMOUT Timeout enable 19 1 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 PRESC Clock prescaler 9 3 TRGFLT Configurable digital filter for trigger 6 2 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 RSTARE Reset after read enable 4 1 COUNTRST Counter reset 3 1 CNTSTRT Timer start in continuous mode 2 1 SNGSTRT LPTIM start in single mode 1 1 ENABLE LPTIM Enable 0 1 CCR1 CCR1 Compare Register 0x14 0x20 read-write 0x00000000 CCR1 Capture/compare 1 value 0 16 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 CFGR2 CFGR2 LPTIM configuration register 2 0x24 0x20 read-write 0x00000000 IC2SEL LPTIM input capture 2 selection 20 2 IC1SEL LPTIM input capture 1 selection 16 2 IN2SEL LPTIM input 2 selection 4 2 IN1SEL LPTIM input 1 selection 0 2 RCR RCR LPTIM repetition register 0x28 0x20 read-write 0x00000000 REP Repetition register value 0 8 CCMR1 CCMR1 LPTIM capture/compare mode register 1 0x2C 0x20 read-write 0x00000000 CC1SEL Capture/compare 1 selection 0 1 CC1E Capture/compare 1 output enable 1 1 CC1P Capture/compare 1 output polarity 2 2 IC1PSC Input capture 1 prescaler 8 2 IC1F Input capture 1 filter 12 2 CC2SEL Capture/compare 2 selection 16 1 CC2E Capture/compare 2 output enable 17 1 CC2P Capture/compare 2 output polarity 18 2 IC2PSC Input capture 2 prescaler 24 2 IC2F Input capture 2 filter 28 2 CCR2 CCR2 LPTIM Compare Register 2 0x34 0x20 read-write 0x00000000 CCR2 Capture/compare 2 value 0 16 HWCFGR2 HWCFGR2 LPTIM peripheral hardware configuration register 2 0x3EC 0x20 read-only 0x00000000 CFG1 peripheral hardware configuration 1 0 4 CFG2 peripheral hardware configuration 2 8 8 CFG3 peripheral hardware configuration 3 16 1 HWCFGR1 HWCFGR1 LPTIM peripheral hardware configuration register 1 0x3F0 0x20 read-only 0x00000000 CFG1 peripheral hardware configuration 1 0 8 CFG2 peripheral hardware configuration 2 8 8 CFG3 peripheral hardware configuration 3 16 4 CFG4 peripheral hardware configuration 4 24 8 SEC_LPTIM4 0x56004C00 GTZC1_MPCBB1 GTZC1_MPCBB1 GTZC 0x40032C00 0x0 0x400 registers CR CR MPCBB control register 0x0 0x20 read-write 0x00000000 GLOCK lock the control register of the MPCBB until next reset 0 1 INVSECSTATE SRAMx clocks security state 30 1 SRWILADIS secure read/write illegal access disable 31 1 CFGLOCKR1 CFGLOCKR1 GTZC1 SRAMz MPCBB configuration lock register 0x10 0x20 read-write 0x00000000 32 0x1 0-31 SPLCK%s SPLCK%s 0 1 32 0x4 0-31 SECCFGR%s SECCFGR%s MPCBBz security configuration for super-block %s register 0x100 0x20 read-write 0xFFFFFFFF 32 0x1 0-31 SEC%s SEC%s 0 1 32 0x4 0-31 PRIVCFGR%s PRIVCFGR%s MPCBBz privileged configuration for super-block %s register 0x200 0x20 read-write 0xFFFFFFFF 32 0x1 0-31 PRIV%s PRIV%s 0 1 SEC_GTZC1_MPCBB1 0x50032C00 GTZC1_MPCBB2 GTZC1_MPCBB2 GTZC 0x40033000 0x0 0x400 registers CR CR MPCBB control register 0x0 0x20 read-write 0x00000000 GLOCK lock the control register of the MPCBB until next reset 0 1 INVSECSTATE SRAMx clocks security state 30 1 SRWILADIS secure read/write illegal access disable 31 1 CFGLOCKR1 CFGLOCKR1 GTZC1 SRAMz MPCBB configuration lock register 0x10 0x20 read-write 0x00000000 32 0x1 0-31 SPLCK%s SPLCK%s 0 1 32 0x4 0-31 SECCFGR%s SECCFGR%s MPCBBz security configuration for super-block %s register 0x100 0x20 read-write 0xFFFFFFFF 32 0x1 0-31 SEC%s SEC%s 0 1 32 0x4 0-31 PRIVCFGR%s PRIVCFGR%s MPCBBz privileged configuration for super-block %s register 0x200 0x20 read-write 0xFFFFFFFF 32 0x1 0-31 PRIV%s PRIV%s 0 1 SEC_GTZC1_MPCBB2 0x50033000 GTZC1_MPCBB3 GTZC1_MPCBB3 GTZC 0x40033400 0x0 0x400 registers CR CR MPCBB control register 0x0 0x20 read-write 0x00000000 GLOCK lock the control register of the MPCBB until next reset 0 1 INVSECSTATE SRAMx clocks security state 30 1 SRWILADIS secure read/write illegal access disable 31 1 CFGLOCKR1 CFGLOCKR1 GTZC1 SRAMz MPCBB configuration lock register 0x10 0x20 read-write 0x00000000 32 0x1 0-31 SPLCK%s SPLCK%s 0 1 32 0x4 0-31 SECCFGR%s SECCFGR%s MPCBBz security configuration for super-block %s register 0x100 0x20 read-write 0xFFFFFFFF 32 0x1 0-31 SEC%s SEC%s 0 1 32 0x4 0-31 PRIVCFGR%s PRIVCFGR%s MPCBBz privileged configuration for super-block %s register 0x200 0x20 read-write 0xFFFFFFFF 32 0x1 0-31 PRIV%s PRIV%s 0 1 SEC_GTZC1_MPCBB3 0x50033400 GTZC1_TZIC GTZC1_TZIC GTZC 0x40032800 0x0 0x400 registers IER1 IER1 TZIC interrupt enable register 1 0x0 0x20 read-write 0x00000000 TIM2IE TIM2IE 0 1 TIM3IE TIM3IE 1 1 TIM4IE TIM4IE 2 1 TIM5IE TIM5IE 3 1 TIM6IE TIM6IE 4 1 TIM7IE TIM7IE 5 1 WWDGIE WWDGIE 6 1 IWDGIE IWDGIE 7 1 SPI2IE SPI2IE 8 1 USART2IE illegal access interrupt enable for USART2 9 1 USART3IE illegal access interrupt enable for USART3 10 1 USART4IE illegal access interrupt enable for UART4 11 1 UART5IE illegal access interrupt enable for UART5 12 1 I2C1IE illegal access interrupt enable for I2C1 13 1 I2C2IE illegal access interrupt enable for I2C2 14 1 CRSIE illegal access interrupt enable for CRS 15 1 I2C4IE illegal access interrupt enable for I2C4 16 1 LPTIM2IE illegal access interrupt enable for LPTIM2 17 1 FDCAN1IE illegal access interrupt enable for FDCAN1 18 1 UCPD1IE illegal access interrupt enable for UCPD1 19 1 IER2 IER2 TZIC interrupt enable register 2 0x4 0x20 read-write 0x00000000 TIM1IE illegal access interrupt enable for TIM1 0 1 SPI1IE illegal access interrupt enable for SPI1 1 1 TIM8IE illegal access interrupt enable for TIM8 2 1 USART1IE illegal access interrupt enable for USART1 3 1 TIM15IE illegal access interrupt enable for TIM5 4 1 TIM16IE illegal access interrupt enable for TIM6 5 1 TIM17IE illegal access interrupt enable for TIM7 6 1 SAI1IE illegal access interrupt enable for SAI1 7 1 SAI2IE illegal access interrupt enable for SAI2 8 1 IER3 IER3 TZIC interrupt enable register 3 0x8 0x20 read-write 0x00000000 MDF1IE illegal access interrupt enable for MDF1 0 1 CORDICIE illegal access interrupt enable for CORDIC 1 1 FMACIE illegal access interrupt enable for FMAC 2 1 CRCIE illegal access interrupt enable for CRC 3 1 TSCIE illegal access interrupt enable for TSC 4 1 DMA2DIE illegal access interrupt enable for register of DMA2D 5 1 ICACHEIE illegal access interrupt enable for ICACHE registers 6 1 DCACHEIE illegal access interrupt enable for DCACHE registers 7 1 ADC1IE illegal access interrupt enable for ADC1 8 1 DCMIIE illegal access interrupt enable for DCMI 9 1 OTGFSIE illegal access interrupt enable for OTG_FS 10 1 AESIE illegal access interrupt enable for AES 11 1 HASHIE illegal access interrupt enable for HASH 12 1 RNGIE illegal access interrupt enable for RNG 13 1 PKAIE illegal access interrupt enable for PKA 14 1 SAESIE illegal access interrupt enable for SAES 15 1 OCTOSPIMIE illegal access interrupt enable for OCTOSPIM 16 1 SDMMC1IE illegal access interrupt enable for SDMMC2 17 1 SDMMC2IE illegal access interrupt enable for SDMMC1 18 1 FSMCIE illegal access interrupt enable for FSMC registers 19 1 OCTOSPI1IE illegal access interrupt enable for OCTOSPI1 registers 20 1 OCTOSPI2IE illegal access interrupt enable for OCTOSPI2 registers 21 1 RAMCFGIE illegal access interrupt enable for RAMCFG 22 1 IER4 IER4 TZIC interrupt enable register 4 0xC 0x20 read-write 0x00000000 GPDMA1IE illegal access interrupt enable for GPDMA1 0 1 FLASH_REGIE illegal access interrupt enable for FLASH registers 1 1 FLASHIE illegal access interrupt enable for FLASH memory 2 1 OTFDEC1IE illegal access interrupt enable for OTFDEC1 3 1 OTFDEC2IE illegal access interrupt enable for OTFDEC2 4 1 TZSC1IE illegal access interrupt enable for GTZC1 TZSC registers 14 1 TZIC1IE illegal access interrupt enable for GTZC1 TZIC registers 15 1 OCTOSPI1_MEMIE illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank 16 1 FSMC_MEMIE illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3 17 1 BKPSRAMIE illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank 18 1 OCTOSPI2_MEMIE illegal access interrupt enable for OCTOSPI2 memory bank 19 1 SRAM1IE illegal access interrupt enable for SRAM1 24 1 MPCBB1_REGIE illegal access interrupt enable for MPCBB1 registers 25 1 SRAM2IE illegal access interrupt enable for SRAM2 26 1 MPCBB2_REGIE illegal access interrupt enable for MPCBB2 registers 27 1 SRAM3IE illegal access interrupt enable for SRAM3 28 1 MPCBB3_REGIE illegal access interrupt enable for MPCBB3 registers 29 1 SR1 SR1 TZIC status register 1 0x10 0x20 read-only 0x00000000 TIM2F illegal access flag for TIM2 0 1 TIM3F illegal access flag for TIM3 1 1 TIM4F illegal access flag for TIM4 2 1 TIM5F illegal access flag for TIM5 3 1 TIM6F illegal access flag for TIM6 4 1 TIM7F illegal access flag for TIM7 5 1 WWDGF illegal access flag for WWDG 6 1 IWDGF illegal access flag for IWDG 7 1 SPI2F illegal access flag for SPI2 8 1 USART2F illegal access flag for USART2 9 1 USART3F illegal access flag for USART3 10 1 UART4F illegal access flag for UART4 11 1 UART5F illegal access flag for UART5 12 1 I2C1F illegal access flag for I2C1 13 1 I2C2F illegal access flag for I2C2 14 1 CRSF illegal access flag for CRS 15 1 I2C4F illegal access flag for I2C4 16 1 LPTIM2F illegal access flag for LPTIM2 17 1 FDCAN1F illegal access flag for FDCAN1 18 1 UCPD1F illegal access flag for UCPD1 19 1 SR2 SR2 TZIC status register 2 0x14 0x20 read-only 0x00000000 TIM1F illegal access flag for TIM1 0 1 SPI1F illegal access flag for SPI1 1 1 TIM8F illegal access flag for TIM8 2 1 USART1F illegal access flag for USART1 3 1 TIM15F illegal access flag for TIM5 4 1 TIM16F illegal access flag for TIM6 5 1 TIM17F illegal access flag for TIM7 6 1 SAI1F illegal access flag for SAI1 7 1 SAI2F illegal access flag for SAI2 8 1 SR3 SR3 TZIC status register 3 0x18 0x20 read-only 0x00000000 MDF1F illegal access flag for MDF1 0 1 CORDICF illegal access flag for CORDIC 1 1 FMACF illegal access flag for FMAC 2 1 CRCF illegal access flag for CRC 3 1 TSCF illegal access flag for TSC 4 1 DMA2DF illegal access flag for register of DMA2D 5 1 ICACHEF illegal access flag for ICACHE registers 6 1 DCACHEF illegal access flag for DCACHE registers 7 1 ADC1F illegal access flag for ADC1 8 1 DCMIF illegal access flag for DCMI 9 1 OTGFSF illegal access flag for OTG_FS 10 1 AESF illegal access flag for AES 11 1 HASHF illegal access flag for HASH 12 1 RNGF illegal access flag for RNG 13 1 PKAF illegal access flag for PKA 14 1 SAESF illegal access flag for SAES 15 1 OCTOSPIMF illegal access flag for OCTOSPIM 16 1 SDMMC1F illegal access flag for SDMMC2 17 1 SDMMC2F illegal access flag for SDMMC1 18 1 FSMCF illegal access flag for FSMC registers 19 1 OCTOSPI1F illegal access flag for OCTOSPI1 registers 20 1 OCTOSPI2F illegal access flag for OCTOSPI2 registers 21 1 RAMCFGF illegal access flag for RAMCFG 22 1 SR4 SR4 TZIC status register 4 0x1C 0x20 read-only 0x00000000 GPDMA1F illegal access flag for GPDMA1 0 1 FLASH_REGF illegal access flag for FLASH registers 1 1 FLASHF illegal access flag for FLASH memory 2 1 OTFDEC1F illegal access flag for OTFDEC1 3 1 OTFDEC2F illegal access flag for OTFDEC2 4 1 TZSC1F illegal access flag for GTZC1 TZSC registers 14 1 TZIC1F illegal access flag for GTZC1 TZIC registers 15 1 OCTOSPI1_MEMF illegal access flag for MPCWM1 (OCTOSPI1) memory bank 16 1 FSMC_MEMF illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR) 17 1 BKPSRAMF illegal access flag for MPCWM3 (BKPSRAM) memory bank 18 1 OCTOSPI2_MEMF illegal access flag for OCTOSPI2 memory bank 19 1 SRAM1F illegal access flag for SRAM1 24 1 MPCBB1_REGF illegal access flag for MPCBB1 registers 25 1 SRAM2F illegal access flag for SRAM2 26 1 MPCBB2_REGF illegal access flag for MPCBB2 registers 27 1 SRAM3F illegal access flag for SRAM3 28 1 MPCBB3_REGF illegal access flag for MPCBB3 registers 29 1 FCR1 FCR1 TZIC flag clear register 1 0x20 0x20 write-only 0x00000000 CTIM2F clear the illegal access flag for TIM2 0 1 CTIM3F clear the illegal access flag for TIM3 1 1 CTIM4F clear the illegal access flag for TIM4 2 1 CTIM5F clear the illegal access flag for TIM5 3 1 CTIM6F clear the illegal access flag for TIM6 4 1 CTIM7F clear the illegal access flag for TIM7 5 1 CWWDGF clear the illegal access flag for WWDG 6 1 CIWDGF clear the illegal access flag for IWDG 7 1 CSPI2F clear the illegal access flag for SPI2 8 1 CUSART2F clear the illegal access flag for USART2 9 1 CUSART3F clear the illegal access flag for USART3 10 1 CUART4F clear the illegal access flag for UART4 11 1 CUART5F clear the illegal access flag for UART5 12 1 CI2C1F clear the illegal access flag for I2C1 13 1 CI2C2F clear the illegal access flag for I2C2 14 1 CCRSF clear the illegal access flag for CRS 15 1 CI2C4F clear the illegal access flag for I2C4 16 1 CLPTIM2F clear the illegal access flag for LPTIM2 17 1 CFDCAN1F clear the illegal access flag for FDCAN1 18 1 CUCPD1F clear the illegal access flag for UCPD1 19 1 FCR2 FCR2 TZIC flag clear register 2 0x24 0x20 write-only 0x00000000 CTIM1F clear the illegal access flag for TIM1 0 1 CSPI1F clear the illegal access flag for SPI1 1 1 CTIM8F clear the illegal access flag for TIM8 2 1 CUSART1F clear the illegal access flag for USART1 3 1 CTIM15F clear the illegal access flag for TIM5 4 1 CTIM16F clear the illegal access flag for TIM6 5 1 CTIM17F clear the illegal access flag for TIM7 6 1 CSAI1F clear the illegal access flag for SAI1 7 1 CSAI2F clear the illegal access flag for SAI2 8 1 FCR3 FCR3 TZIC flag clear register 3 0x28 0x20 write-only 0x00000000 CMDF1F clear the illegal access flag for MDF1 0 1 CCORDICF clear the illegal access flag for CORDIC 1 1 CFMACF clear the illegal access flag for FMAC 2 1 CCRCF clear the illegal access flag for CRC 3 1 CTSCF clear the illegal access flag for TSC 4 1 CDMA2DF clear the illegal access flag for register of DMA2D 5 1 CICACHEF clear the illegal access flag for ICACHE registers 6 1 CDCACHEF clear the illegal access flag for DCACHE registers 7 1 CADC1F clear the illegal access flag for ADC1 8 1 CDCMIF clear the illegal access flag for DCMI 9 1 COTGFSF clear the illegal access flag for OTG_FS 10 1 CAESF clear the illegal access flag for AES 11 1 CHASHF clear the illegal access flag for HASH 12 1 CRNGF clear the illegal access flag for RNG 13 1 CPKAF clear the illegal access flag for PKA 14 1 CSAESF clear the illegal access flag for SAES 15 1 COCTOSPIMF clear the illegal access flag for OCTOSPIM 16 1 CSDMMC1F clear the illegal access flag for SDMMC2 17 1 CSDMMC2F clear the illegal access flag for SDMMC1 18 1 CFSMCF clear the illegal access flag for FSMC registers 19 1 COCTOSPI1F clear the illegal access flag for OCTOSPI1 registers 20 1 COCTOSPI2F clear the illegal access flag for OCTOSPI2 registers 21 1 CRAMCFGF clear the illegal access flag for RAMCFG 22 1 FCR4 FCR4 TZIC flag clear register 3 0x2C 0x20 write-only 0x00000000 CGPDMA1F clear the illegal access flag for GPDMA1 0 1 CFLASH_REGF clear the illegal access flag for FLASH registers 1 1 CFLASHF clear the illegal access flag for FLASH memory 2 1 COTFDEC1F clear the illegal access flag for OTFDEC1 3 1 COTFDEC2F clear the illegal access flag for OTFDEC2 4 1 CTZSC1F clear the illegal access flag for GTZC1 TZSC registers 14 1 CTZIC1F clear the illegal access flag for GTZC1 TZIC registers 15 1 COCTOSPI1_MEMF clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank 16 1 CFSMC_MEMF clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 17 1 CBKPSRAMF clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank 18 1 COCTOSPI2_MEMF clear the illegal access flag for OCTOSPI2 memory bank 19 1 CSRAM1F clear the illegal access flag for SRAM1 24 1 CMPCBB1_REGF clear the illegal access flag for MPCBB1 registers 25 1 CSRAM2F clear the illegal access flag for SRAM2 26 1 CMPCBB2_REGF clear the illegal access flag for MPCBB2 registers 27 1 CSRAM3F clear the illegal access flag for SRAM3 28 1 CMPCBB3_REGF clear the illegal access flag for MPCBB3 registers 29 1 SEC_GTZC1_TZIC 0x50032800 GTZC1_TZSC GTZC1_TZSC GTZC 0x40032400 0x0 0x400 registers CR CR TZSC control register 0x0 0x20 read-write 0x00000000 LCK lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset 0 1 SECCFGR1 SECCFGR1 TZSC secure configuration register 1 0x10 0x20 read-write 0x00000000 TIM2SEC secure access mode for TIM2 0 1 TIM3SEC secure access mode for TIM3 1 1 TIM4SEC secure access mode for TIM4 2 1 TIM5SEC secure access mode for TIM5 3 1 TIM6SEC secure access mode for TIM6 4 1 TIM7SEC secure access mode for TIM7 5 1 WWDGSEC secure access mode for WWDG 6 1 IWDGSEC secure access mode for IWDG 7 1 SPI2SEC secure access mode for SPI2 8 1 USART2SEC secure access mode for USART2 9 1 USART3SEC secure access mode for USART3 10 1 UART4SEC secure access mode for UART4 11 1 UART5SEC secure access mode for UART5 12 1 I2C1SEC secure access mode for I2C1 13 1 I2C2SEC secure access mode for I2C2 14 1 CRSSEC secure access mode for CRS 15 1 I2C4SEC secure access mode for I2C4 16 1 LPTIM2SEC secure access mode for LPTIM2 17 1 FDCAN1SEC secure access mode for FDCAN1 18 1 UCPD1SEC secure access mode for UCPD1 19 1 SECCFGR2 SECCFGR2 TZSC secure configuration register 2 0x14 0x20 read-write 0x00000000 TIM1SEC secure access mode for TIM1 0 1 SPI1SEC secure access mode for SPI1 1 1 TIM8SEC secure access mode for TIM8 2 1 USART1SEC secure access mode for USART1 3 1 TIM15SEC secure access mode for TIM5 4 1 TIM16SEC secure access mode for TIM6 5 1 TIM17SEC secure access mode for TIM7 6 1 SAI1SEC secure access mode for SAI1 7 1 SAI2SEC secure access mode for SAI2 8 1 SECCFGR3 SECCFGR3 TZSC secure configuration register 3 0x18 0x20 read-write 0x00000000 MDF1SEC secure access mode for MDF1 0 1 CORDICSEC secure access mode for CORDIC 1 1 FMACSEC secure access mode for FMAC 2 1 CRCSEC secure access mode for CRC 3 1 TSCSEC secure access mode for TSC 4 1 DMA2DSEC secure access mode for register of DMA2D 5 1 ICACHE_REGSEC secure access mode for ICACHE registers 6 1 DCACHE_REGSEC secure access mode for DCACHE registers 7 1 ADC1SEC secure access mode for ADC1 8 1 DCMISEC secure access mode for DCMI 9 1 OTGFSSEC secure access mode for OTG_FS 10 1 AESSEC secure access mode for AES 11 1 HASHSEC secure access mode for HASH 12 1 RNGSEC secure access mode for RNG 13 1 PKASEC secure access mode for PKA 14 1 SAESSEC secure access mode for SAES 15 1 OCTOSPIMSEC secure access mode for OCTOSPIM 16 1 SDMMC1SEC secure access mode for SDMMC2 17 1 SDMMC2SEC secure access mode for SDMMC1 18 1 FSMC_REGSEC secure access mode for FSMC registers 19 1 OCTOSPI1_REGSEC secure access mode for OCTOSPI1 registers 20 1 OCTOSPI2_REGSEC secure access mode for OCTOSPI2 registers 21 1 RAMCFGSEC secure access mode for RAMCFG 22 1 PRIVCFGR1 PRIVCFGR1 TZSC privilege configuration register 1 0x20 0x20 read-write 0x00000000 TIM2PRIV privileged access mode for TIM2 0 1 TIM3PRIV privileged access mode for TIM3 1 1 TIM4PRIV privileged access mode for TIM4 2 1 TIM5PRIV privileged access mode for TIM5 3 1 TIM6PRIV privileged access mode for TIM6 4 1 TIM7PRIV privileged access mode for TIM7 5 1 WWDGPRIV privileged access mode for WWDG 6 1 IWDGPRIV privileged access mode for IWDG 7 1 SPI2PRIV privileged access mode for SPI2 8 1 USART2PRIV privileged access mode for USART2 9 1 USART3PRIV privileged access mode for USART3 10 1 UART4PRIV privileged access mode for UART4 11 1 UART5PRIV privileged access mode for UART5 12 1 I2C1PRIV privileged access mode for I2C1 13 1 I2C2PRIV privileged access mode for I2C2 14 1 CRSPRIV privileged access mode for CRS 15 1 I2C4PRIV privileged access mode for I2C4 16 1 LPTIM2PRIV privileged access mode for LPTIM2 17 1 FDCAN1PRIV privileged access mode for FDCAN1 18 1 UCPD1PRIV privileged access mode for UCPD1 19 1 PRIVCFGR2 PRIVCFGR2 TZSC privilege configuration register 2 0x24 0x20 read-write 0x00000000 TIM1PRIV privileged access mode for TIM1 0 1 SPI1PRIV privileged access mode for SPI1PRIV 1 1 TIM8PRIV privileged access mode for TIM8 2 1 USART1PRIV privileged access mode for USART1 3 1 TIM15PRIV privileged access mode for TIM15 4 1 TIM16PRIV privileged access mode for TIM16 5 1 TIM17PRIV privileged access mode for TIM17 6 1 SAI1PRIV privileged access mode for SAI1 7 1 SAI2PRIV privileged access mode for SAI2 8 1 PRIVCFGR3 PRIVCFGR3 TZSC privilege configuration register 3 0x28 0x20 read-write 0x00000000 MDF1PRIV privileged access mode for MDF1 0 1 CORDICPRIV privileged access mode for CORDIC 1 1 FMACPRIV privileged access mode for FMAC 2 1 CRCPRIV privileged access mode for CRC 3 1 TSCPRIV privileged access mode for TSC 4 1 DMA2DPRIV privileged access mode for register of DMA2D 5 1 ICACHE_REGPRIV privileged access mode for ICACHE registers 6 1 DCACHE_REGPRIV privileged access mode for DCACHE registers 7 1 ADC1PRIV privileged access mode for ADC1 8 1 DCMIPRIV privileged access mode for DCMI 9 1 OTGFSPRIV privileged access mode for OTG_FS 10 1 AESPRIV privileged access mode for AES 11 1 HASHPRIV privileged access mode for HASH 12 1 RNGPRIV privileged access mode for RNG 13 1 PKAPRIV privileged access mode for PKA 14 1 SAESPRIV privileged access mode for SAES 15 1 OCTOSPIMPRIV privileged access mode for OCTOSPIM 16 1 SDMMC1PRIV privileged access mode for SDMMC2 17 1 SDMMC2PRIV privileged access mode for SDMMC1 18 1 FSMC_REGPRIV privileged access mode for FSMC registers 19 1 OCTOSPI1_REGPRIV privileged access mode for OCTOSPI1 20 1 OCTOSPI2_REGPRIV privileged access mode for OCTOSPI2 21 1 RAMCFGPRIV privileged access mode for RAMCFG 22 1 MPCWM1ACFGR MPCWM1ACFGR TZSC memory 1 sub-region A watermark configuration register 0x40 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 MPCWM1AR MPCWM1AR TZSC memory 1 sub-region A watermark register 0x44 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 MPCWM1BCFGR MPCWM1BCFGR TZSC memory 1 sub-region B watermark configuration register 0x48 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 MPCWM1BR MPCWM1BR TZSC memory 1 sub-region B watermark register 0x4C 0x20 read-write 0x00000000 SUBB_START Start of sub-region A 0 11 SUBB_LENGTH Length of sub-region A 16 12 MPCWM2ACFGR MPCWM2ACFGR TZSC memory 2 sub-region A watermark configuration register 0x50 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 MPCWM2AR MPCWM2AR TZSC memory 2 sub-region A watermark register 0x54 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 MPCWM2BCFGR MPCWM2BCFGR TZSC memory 2 sub-region B watermark configuration register 0x58 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 MPCWM2BR MPCWM2BR TZSC memory 2 sub-region B watermark register 0x5C 0x20 read-write 0x00000000 SUBB_START Start of sub-region A 0 11 SUBB_LENGTH Length of sub-region A 16 12 MPCWM3ACFGR MPCWM3ACFGR TZSC memory 3 sub-region A watermark configuration register 0x60 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 MPCWM3AR MPCWM3AR TZSC memory 3 sub-region A watermark register 0x64 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 MPCWM4ACFGR MPCWM4ACFGR TZSC memory 4 sub-region A watermark configuration register 0x70 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 MPCWM4AR MPCWM4AR TZSC memory 4 sub-region A watermark register 0x74 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 MPCWM5ACFGR MPCWM5ACFGR TZSC memory 5 sub-region A watermark configuration register 0x80 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 MPCWM5AR MPCWM5AR TZSC memory 5 sub-region A watermark register 0x84 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 MPCWM5BCFGR MPCWM5BCFGR TZSC memory 5 sub-region B watermark configuration register 0x88 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 MPCWM5BR MPCWM5BR TZSC memory 5 sub-region B watermark register 0x8C 0x20 read-write 0x00000000 SUBB_START Start of sub-region A 0 11 SUBB_LENGTH Length of sub-region A 16 12 SEC_GTZC1_TZSC 0x50032400 GTZC2_MPCBB4 GTZC2_MPCBB4 GTZC 0x46023800 0x0 0x400 registers CR CR MPCBB control register 0x0 0x20 read-write 0x00000000 GLOCK lock the control register of the MPCBB until next reset 0 1 INVSECSTATE SRAMx clocks security state 30 1 SRWILADIS secure read/write illegal access disable 31 1 CFGLOCK CFGLOCK GTZC2 SRAM4 MPCBB configuration lock register 0x10 0x20 read-write 0x00000000 1 0x0 0-0 SPLCK%s Security/privilege configuration lock for super-block %s 0 1 1 0x4 0-0 SECCFGR%s SECCFGR%s MPCBBz security configuration for super-block %s register 0x100 0x20 read-write 0xFFFFFFFF 32 0x1 0-31 SEC%s SEC%s 0 1 1 0x4 0-0 PRIVCFGR%s PRIVCFGR%s MPCBBz privileged configuration for super-block %s register 0x200 0x20 read-write 0xFFFFFFFF 32 0x1 0-31 PRIV%s PRIV%s 0 1 SEC_GTZC2_MPCBB4 0x56023800 GTZC2_TZIC GTZC2_TZIC GTZC 0x46023400 0x0 0x400 registers IER1 IER1 TZIC interrupt enable register 1 0x0 0x20 read-write 0x00000000 SPI3IE illegal access interrupt enable for SPI3 0 1 LPUART1IE illegal access interrupt enable for LPUART1 1 1 I2C3IE illegal access interrupt enable for I2C3 2 1 LPTIM1IE illegal access interrupt enable for LPTIM1 3 1 LPTIM3IE illegal access interrupt enable for LPTIM3 4 1 LPTIM4IE illegal access interrupt enable for LPTIM4 5 1 OPAMPIE illegal access interrupt enable for OPAMP 6 1 COMPIE illegal access interrupt enable for COMP 7 1 ADC4IE illegal access interrupt enable for ADC4 8 1 VREFBUFIE illegal access interrupt enable for VREFBUF 9 1 DAC1IE illegal access interrupt enable for DAC1 11 1 ADF1IE illegal access interrupt enable for ADF1 12 1 IER2 IER2 TZIC interrupt enable register 2 0x4 0x20 read-write 0x00000000 SYSCFGIE illegal access interrupt enable for SYSCFG 0 1 RTCIE illegal access interrupt enable for RTC 1 1 TAMPIE illegal access interrupt enable for TAMP 2 1 PWRIE illegal access interrupt enable for PWR 3 1 RCCIE illegal access interrupt enable for RCC 4 1 LPDMA1IE illegal access interrupt enable for LPDMA 5 1 EXTIIE illegal access interrupt enable for EXTI 6 1 TZSC2IE illegal access interrupt enable for GTZC2 TZSC registers 14 1 TZIC2IE illegal access interrupt enable for GTZC2 TZIC registers 15 1 SRAM4IE illegal access interrupt enable for SRAM4 24 1 MPCBB4_REGIE illegal access interrupt enable for MPCBB4 registers 25 1 SR1 SR1 TZIC status register 1 0x10 0x20 read-only 0x00000000 SPI3F illegal access flag for SPI3 0 1 LPUART1F illegal access flag for LPUART1 1 1 I2C3F illegal access flag for I2C3 2 1 LPTIM1F illegal access flag for LPTIM1 3 1 LPTIM3F illegal access flag for LPTIM3 4 1 LPTIM4F illegal access flag for LPTIM4 5 1 OPAMPF illegal access flag for OPAMP 6 1 COMPF illegal access flag for COMP 7 1 ADC4F illegal access flag for ADC4 8 1 VREFBUFF illegal access flag for VREFBUF 9 1 DAC1F illegal access flag for DAC1 11 1 ADF1F illegal access flag for ADF1 12 1 SR2 SR2 TZIC status register 2 0x14 0x20 read-only 0x00000000 SYSCFGF illegal access flag for SYSCFG 0 1 RTCF illegal access flag for RTC 1 1 TAMPF illegal access flag for TAMP 2 1 PWRF illegal access flag for PWRUSART1F 3 1 RCCF illegal access flag for RCC 4 1 LPDMA1F illegal access flag for LPDMA 5 1 EXTIF illegal access flag for EXTI 6 1 TZSC2F illegal access flag for GTZC2 TZSC registers 14 1 TZIC2F illegal access flag for GTZC2 TZIC registers 15 1 SRAM4F illegal access flag for SRAM4 24 1 MPCBB4_REGF illegal access flag for MPCBB4 registers 25 1 FCR1 FCR1 TZIC flag clear register 1 0x20 0x20 write-only 0x00000000 CSPI3F clear the illegal access flag for SPI3 0 1 CLPUART1F clear the illegal access flag for LPUART1 1 1 CI2C3F clear the illegal access flag for I2C3 2 1 CLPTIM1F clear the illegal access flag for LPTIM1 3 1 CLPTIM3F clear the illegal access flag for LPTIM3 4 1 CLPTIM4F clear the illegal access flag for LPTIM4 5 1 COPAMPF clear the illegal access flag for OPAMP 6 1 CCOMPF clear the illegal access flag for COMP 7 1 CADC4F clear the illegal access flag for ADC4 8 1 CVREFBUFF clear the illegal access flag for VREFBUF 9 1 CDAC1F clear the illegal access flag for DAC1 11 1 CADF1F clear the illegal access flag for ADF1 12 1 FCR2 FCR2 TZIC flag clear register 2 0x24 0x20 write-only 0x00000000 CSYSCFGF clear the illegal access flag for SYSCFG 0 1 CRTCF clear the illegal access flag for RTC 1 1 CTAMPF clear the illegal access flag for TAMP 2 1 CPWRF clear the illegal access flag for PWR 3 1 CRCCF clear the illegal access flag for RCC 4 1 CLPDMA1F clear the illegal access flag for LPDMA 5 1 CEXTIF clear the illegal access flag for EXTI 6 1 CTZSC2F clear the illegal access flag for GTZC2 TZSC registers 14 1 CTZIC2F clear the illegal access flag for GTZC2 TZIC registers 15 1 CSRAM4F clear the illegal access flag for SRAM4 24 1 CMPCBB4_REGF clear the illegal access flag for MPCBB4 registers 25 1 SEC_GTZC2_TZIC 0x56023400 GTZC2_TZSC GTZC2_TZSC GTZC 0x46023000 0x0 0x400 registers TZSC_CR TZSC_CR TZSC control register 0x0 0x20 read-write 0x00000000 LCK lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset 0 1 TZSC_SECCFGR1 TZSC_SECCFGR1 TZSC secure configuration register 1 0x10 0x20 read-write 0x00000000 SPI3SEC secure access mode for SPI3 0 1 LPUART1SEC secure access mode for LPUART1 1 1 I2C3SEC secure access mode for I2C3 2 1 LPTIM1SEC secure access mode for LPTIM1 3 1 LPTIM3SEC secure access mode for LPTIM3 4 1 LPTIM4SEC secure access mode for LPTIM4 5 1 OPAMPSEC secure access mode for OPAMP 6 1 COMPSEC secure access mode for COMP 7 1 ADC4SEC secure access mode for ADC4 8 1 VREFBUFSEC secure access mode for VREFBUF 9 1 DAC1SEC secure access mode for DAC1 11 1 ADF1SEC secure access mode for ADF1 12 1 TZSC_PRIVCFGR1 TZSC_PRIVCFGR1 TZSC privilege configuration register 1 0x20 0x20 read-write 0x00000000 SPI3PRIV privileged access mode for SPI3 0 1 LPUART1PRIV privileged access mode for LPUART1 1 1 I2C3PRIV privileged access mode for I2C3 2 1 LPTIM1PRIV privileged access mode for LPTIM1 3 1 LPTIM3PRIV privileged access mode for LPTIM3 4 1 LPTIM4PRIV privileged access mode for LPTIM4 5 1 OPAMPPRIV privileged access mode for OPAMP 6 1 COMPPRIV privileged access mode for COMP 7 1 ADC4PRIV privileged access mode for ADC4 8 1 VREFBUFPRIV privileged access mode for VREFBUF 9 1 DAC1PRIV privileged access mode for DAC1 11 1 ADF1PRIV privileged access mode for ADF1 12 1 SEC_GTZC2_TZSC 0x56023000 PWR Power control PWR 0x46020800 0x0 0x400 registers PWR_S3WU PWR wakeup from Stop 3 interrupt 77 CR1 CR1 PWR control register 1 0x0 0x20 0x00000000 0xFFFFFFFF LPMS Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deepsleep mode. 10x: Standby mode (Standby mode also entered if LPMSÂ =Â 11X in PWR_CR1 with BRENÂ =Â 1 in PWR_BDCR1) 11x: Shutdown mode if BREN = 0 in PWR_BDCR1 0 3 read-write LPMS Stop0 Stop 0 mode 0 Stop1 Stop 1 mode 1 Stop2 Stop 2 mode 2 Stop3 Stop 3 mode 3 Standby Standby mode (Standby mode also entered if LPMS = 11X in PWR_CR1 with BREN = 1 in PWR_BDCR1) 4 Shutdown Shutdown mode if BREN = 0 in PWR_BDCR1 6 RRSB1 SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 (from SRAM2 base address to SRAM2 base address + 0x1FFF). Note: This bit has no effect in Shutdown mode. 5 1 read-write RRSB1 Disabled SRAM2 page1 content not retained in Stop3 and Standby modes 0 Enabled SRAM2 page1 content retained in Stop 3 and Standby modes 1 RRSB2 SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2 (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF). Note: This bit has no effect in Shutdown mode. 6 1 read-write RRSB2 Disabled SRAM2 page2 content not retained in Stop3 and Standby modes 0 Enabled SRAM2 page2 content retained in Stop 3 and Standby modes 1 ULPMEN BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. This bit must be set to reach the lowest power consumption in the low-power modes. 7 1 read-write ULPMEN Disabled BOR level 0 operating in continuous (normal) mode in Standby mode 0 Enabled BOR level 0 operating in discontinuous (ultra-low power) mode in Standby mode 1 SRAM1PD SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1. 8 1 read-write SRAM1PD On SRAMx powered on 0 Off SRAMx powered off 1 SRAM2PD SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2. 9 1 read-write SRAM3PD SRAM3 power down This bit is used to reduce the consumption by powering off the SRAM3. 10 1 read-write SRAM4PD SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4. 11 1 read-write CR2 CR2 PWR control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SRAM1PDS1 SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 0 1 read-write SRAM1PDS1 Disabled SRAM1 page x content retained in Stop modes 0 Enabled SRAM1 page x content lost in Stop modes 1 SRAM1PDS2 SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 1 1 read-write SRAM1PDS3 SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 2 1 read-write SRAM2PDS1 SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in PWR_CR1. 4 1 read-write SRAM2PDS1 Disabled SRAM2 page x content retained in Stop modes 0 Enabled SRAM2 page x content lost in Stop modes 1 SRAM2PDS2 SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in PWR_CR1. 5 1 read-write SRAM4PDS SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3) 6 1 read-write SRAM4PDS Disabled SRAM4 content retained in Stop modes 0 Enabled SRAM4 content lost in Stop modes 1 ICRAMPDS ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3) 8 1 read-write ICRAMPDS Disabled ICACHE SRAM content retained in Stop modes 0 Enabled ICACHE SRAM content lost in Stop modes 1 DC1RAMPDS DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) 9 1 read-write DC1RAMPDS Disabled DCACHE1 SRAM content retained in Stop modes 0 Enabled DCACHE1 SRAM content lost in Stop modes 1 DMA2DRAMPDS DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3) 10 1 read-write DMA2DRAMPDS Disabled DMA2D SRAM content retained in Stop modes 0 Enabled DMA2D SRAM content lost in Stop modes 1 PRAMPDS FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (StopÂ 0,Â 1,Â 2,Â 3) 11 1 read-write PRAMPDS Disabled FMAC, FDCAN, and USB/OTG_FS/OTG_HS SRAM content retained in Stop modes 0 Enabled FMAC, FDCAN, and USB/OTG_FS/OTG_HS SRAM content lost in Stop modes 1 PKARAMPDS PKA SRAM power-down 12 1 read-write PKARAMPDS Disabled PKA SRAM content retained in Stop modes 0 Enabled PKA SRAM content lost in Stop modes 1 SRAM4FWU SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes. 13 1 read-write SRAM4FWU Disabled SRAM4 enters low-power mode in Stop 0/1/2 modes (source biasing for lower-power consumption) 0 Enabled SRAM4 remains in normal mode in Stop 0/1/2 modes (higher consumption but no SRAM4 wake-up time) 1 FLASHFWU Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption. 14 1 read-write FLASHFWU Disabled Flash memory enters low-power mode in Stop 0/1 modes (lower-power consumption) 0 Enabled Flash memory remains in normal mode in Stop 0/1 modes (faster wake-up time) 1 SRAM3PDS1 SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 16 1 read-write SRAM3PDS1 Disabled SRAM3 page x content retained in Stop modes 0 Enabled SRAM3 page x content lost in Stop modes 1 SRAM3PDS2 SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 17 1 read-write SRAM3PDS3 SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 18 1 read-write SRAM3PDS4 SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 19 1 read-write SRAM3PDS5 SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 20 1 read-write SRAM3PDS6 SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 21 1 read-write SRAM3PDS7 SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 22 1 read-write SRAM3PDS8 SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 23 1 read-write SRDRUN SmartRun domain in Run mode 31 1 read-write SRDRUN Disabled SmartRun domain AHB3 and APB3 clocks disabled by default in Stop 0/1/2 modes 0 Enabled SmartRun domain AHB3 and APB3 clocks kept enabled in Stop 0/1/2 modes 1 CR3 CR3 PWR control register 3 0x8 0x20 0x00000000 0xFFFFFFFF REGSEL Regulator selection Note: REGSEL is reserved and must be kept at reset value in packages without SMPS. 1 1 read-write REGSEL LDO LDO selected 0 SMPS SMPS selected 1 FSTEN Fast soft start 2 1 read-write FSTEN Disabled LDO/SMPS fast startup disabled (limited inrush current) 0 Enabled LDO/SMPS fast startup enabled 1 VOSR VOSR PWR voltage scaling register 0xC 0x20 0x00008000 0xFFFFFFFF BOOSTRDY EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set. 14 1 read-only BOOSTRDY NotReady Power booster not ready 0 Ready Power booster ready 1 VOSRDY Ready bit for VCORE voltage scaling output selection 15 1 read-only VOSRDY NotReady Not ready, voltage level < VOS selected level 0 Ready Ready, voltage level â¥ VOS selected level 1 VOS Voltage scaling range selection This field is protected against non-secure access when SYSCLKSECÂ =Â 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSECÂ =Â 1 in RCC_SECCFGR and SPRIVÂ =Â 1 in PWR_PRIVCFGR, or when SYSCLKSECÂ =Â 0 and NSPRIVÂ =Â 1. 16 2 read-write VOS Range4 Range 4 (lowest power) 0 Range3 Range 3 1 Range2 Range 2 2 Range1 Range 1 (highest frequency) 3 BOOSTEN EPOD booster enable 18 1 read-write BOOSTEN Disabled Booster disabled 0 Enabled Booster enabled 1 SVMCR SVMCR PWR supply voltage monitoring control register 0x10 0x20 0x00000000 0xFFFFFFFF PVDE Power voltage detector enable 4 1 read-write PVDE Disabled PVD disabled 0 Enabled PVD enabled 1 PVDLS Power voltage detector level selection These bits select the voltage threshold detected by the power voltage detector: 5 3 read-write PVDLS VPVD0 VPVD0 around 2.0 V 0 VPVD1 VPVD1 around 2.2 V 1 VPVD2 VPVD2 around 2.4 V 2 VPVD3 VPVD3 around 2.5 V 3 VPVD4 VPVD4 around 2.6 V 4 VPVD5 VPVD5 around 2.8 V 5 VPVD6 VPVD6 around 2.9 V 6 PVDIN External input analog voltage PVD_IN (compared internally to VREFINT) 7 UVMEN VDDUSB independent USB voltage monitor enable 24 1 read-write UVMEN Disabled VDDUSB voltage monitor disabled 0 Enabled VDDUSB voltage monitor enabled 1 IO2VMEN VDDIO2 independent I/Os voltage monitor enable 25 1 read-write IO2VMEN Disabled VDDIO2 voltage monitor disabled 0 Enabled VDDIO2 voltage monitor enabled 1 AVM1EN VDDA independent analog supply voltage monitor 1 enable (1.6Â V threshold) 26 1 read-write AVM1EN Disabled VDDA voltage monitor 1 disabled 0 Enabled VDDA voltage monitor 1 enabled 1 AVM2EN VDDA independent analog supply voltage monitor 2 enable (1.8Â V threshold) 27 1 read-write AVM2EN Disabled VDDA voltage monitor 2 disabled 0 Enabled VDDA voltage monitor 2 enabled 1 USV VDDUSB independent USB supply valid 28 1 read-write USV NotPresent VDDUSB not present: logical and electrical isolation is applied to ignore this supply 0 Present VDDUSB valid 1 IO2SV VDDIO2 independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not. 29 1 read-write IO2SV NotPresent VDDIO2 not present: logical and electrical isolation is applied to ignore this supply 0 Present VDDIO2 valid 1 ASV VDDA independent analog supply valid 30 1 read-write ASV NotPresent VDDA not present: logical and electrical isolation is applied to ignore this supply 0 Present VDDA valid 1 WUCR1 WUCR1 PWR wakeup control register 1 0x14 0x20 0x00000000 0xFFFFFFFF WUPEN1 Wakeup pin WKUP1 enable 0 1 read-write WUPEN1 Disabled Wakeup pin disabled 0 Enabled Wakeup pin enabled 1 WUPEN2 Wakeup pin WKUP2 enable 1 1 read-write WUPEN3 Wakeup pin WKUP3 enable 2 1 read-write WUPEN4 Wakeup pin WKUP4 enable 3 1 read-write WUPEN5 Wakeup pin WKUP5 enable 4 1 read-write WUPEN6 Wakeup pin WKUP6 enable 5 1 read-write WUPEN7 Wakeup pin WKUP7 enable 6 1 read-write WUPEN8 Wakeup pin WKUP8 enable 7 1 read-write WUCR2 WUCR2 PWR wakeup control register 2 0x18 0x20 0x00000000 0xFFFFFFFF WUPP1 Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. 0 1 read-write WUPP1 RisingEdge Detection on high level (rising edge) 0 FallingEdge Detection on low level (falling edge) 1 WUPP2 Wakeup pin WKUP2 polarity This bit must be configured when WUPEN2 = 0. 1 1 read-write WUPP3 Wakeup pin WKUP3 polarity This bit must be configured when WUPEN3 = 0. 2 1 read-write WUPP4 Wakeup pin WKUP4 polarity This bit must be configured when WUPEN4 = 0. 3 1 read-write WUPP5 Wakeup pin WKUP5 polarity This bit must be configured when WUPEN5 = 0. 4 1 read-write WUPP6 Wakeup pin WKUP6 polarity This bit must be configured when WUPEN6 = 0. 5 1 read-write WUPP7 Wakeup pin WKUP7 polarity This bit must be configured when WUPEN7 = 0. 6 1 read-write WUPP8 Wakeup pin WKUP8 polarity This bit must be configured when WUPEN8Â =Â 0. 7 1 read-write WUCR3 WUCR3 PWR wakeup control register 3 0x1C 0x20 0x00000000 0xFFFFFFFF WUSEL1 Wakeup pin WKUP1 selection This field must be configured when WUPEN1 = 0. 0 2 read-write WUSEL1 WKUPx_0 Wakeup pin WKUPx_0 selected 0 WKUPx_1 Wakeup pin WKUPx_1 selected 1 WKUPx_2 Wakeup pin WKUPx_2 selected 2 WKUPx_3 Wakeup pin WKUPx_3 selected 3 WUSEL2 Wakeup pin WKUP2 selection This field must be configured when WUPEN2 = 0. 2 2 read-write WUSEL3 Wakeup pin WKUP3 selection This field must be configured when WUPEN3 = 0. 4 2 read-write WUSEL4 Wakeup pin WKUP4 selection This field must be configured when WUPEN4 = 0. 6 2 read-write WUSEL5 Wakeup pin WKUP5 selection This field must be configured when WUPEN5 = 0. 8 2 read-write WUSEL6 Wakeup pin WKUP6 selection This field must be configured when WUPEN6 = 0. 10 2 read-write WUSEL7 Wakeup pin WKUP7 selection This field must be configured when WUPEN7 = 0. 12 2 read-write WUSEL8 Wakeup pin WKUP8 selection This field must be configured when WUPEN8 = 0. 14 2 read-write BDCR1 BDCR1 PWR Backup domain control register 1 0x20 0x20 0x00000000 0xFFFFFFFF BREN Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept in Standby and VBAT modes. If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS. Note: Backup RAM cannot be preserved in Shutdown mode. 0 1 read-write BREN Disabled Backup RAM content lost in Standby and VBAT modes 0 Enabled Backup RAM content preserved in Standby and VBAT modes 1 MONEN Backup domain voltage and temperature monitoring enable 4 1 read-write MONEN Disabled Backup domain voltage and temperature monitoring disabled 0 Enabled Backup domain voltage and temperature monitoring enabled 1 BDCR2 BDCR2 PWR Backup domain control register 2 0x24 0x20 0x00000000 0xFFFFFFFF VBE VBAT charging enable 0 1 read-write VBE Disabled VBAT battery charging disabled 0 Enabled VBAT battery charging enabled 1 VBRS VBAT charging resistor selection 1 1 read-write VBRS R_5k Charge VBAT through a 5 kOhm resistor 0 R_1k5 Charge VBAT through a 1.5 kOhm resistor 1 DBPR DBPR PWR disable Backup domain register 0x28 0x20 0x00000000 0xFFFFFFFF DBP Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. 0 1 read-write DBP Disabled Write access to backup domain disabled 0 Enabled Write access to backup domain enabled 1 UCPDR UCPDR PWR USB Type-Câ¢ and Power Delivery register 0x2C 0x20 0x00000000 0xFFFFFFFF UCPD_DBDIS UCPD dead battery disable After exiting reset, the USB Type-C âdead batteryâ behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable). 0 1 read-write UCPD_DBDIS Enabled UCPD dead battery pull-down behavior enabled on UCPDx_CC1 and UCPDx_CC2 pins 0 Disabled UCPD dead battery pull-down behavior disabled on UCPDx_CC1 and UCPDx_CC2 pins 1 UCPD_STBY UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers. 1 1 read-write UCPD_STBY Disabled UCPD configuration is not memorized in Standby mode (Must be in this state after exiting Stop 3 or Standby mode, and before writing any UCPD registers) 0 Enabled UCPD configuration is memorized in Stop 3 and Standby modes 1 SECCFGR SECCFGR PWR security configuration register 0x30 0x20 0x00000000 0xFFFFFFFF WUP1SEC WUP1 secure protection 0 1 read-write WUP1SEC NonSecure Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written with secure or nonsecure access 0 Secure Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written only with secure access 1 WUP2SEC WUP2 secure protection 1 1 read-write WUP3SEC WUP3 secure protection 2 1 read-write WUP4SEC WUP4 secure protection 3 1 read-write WUP5SEC WUP5 secure protection 4 1 read-write WUP6SEC WUP6 secure protection 5 1 read-write WUP7SEC WUP7 secure protection 6 1 read-write WUP8SEC WUP8 secure protection 7 1 read-write LPMSEC Low-power modes secure protection 12 1 read-write LPMSEC NonSecure PWR_CR1, PWR_CR2 and CSSF in the PWR_SR can be read and written with secure or nonsecure access 0 Secure PWR_CR1, PWR_CR2, and CSSF in the PWR_SR can be read and written only with secure access 1 VDMSEC Voltage detection and monitoring secure protection 13 1 read-write VDMSEC NonSecure PWR_SVMCR and PWR_CR3 can be read and written with secure or nonsecure access 0 Secure PWR_SVMCR and PWR_CR3 can be read and written only with secure access 1 VBSEC Backup domain secure protection 14 1 read-write VBSEC NonSecure PWR_BDCR1, PWR_BDCR2, and PWR_DBPR can be read and written with secure or nonsecure access 0 Secure PWR_BDCR1, PWR_BDCR2, and PWR_DBPR can be read and written only with secure access 1 APCSEC Pull-up/pull-down secure protection 15 1 read-write APCSEC NonSecure PWR_APCR can be read and written with secure or nonsecure access 0 Secure PWR_APCR can be read and written only with secure access 1 PRIVCFGR PRIVCFGR PWR privilege control register 0x34 0x20 0x00000000 0xFFFFFFFF SPRIV PWR secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access. 0 1 read-write SPRIV NonSecure Read and write to PWR secure functions can be done by privileged or unprivileged access 0 Secure Read and write to PWR secure functions can be done by privileged access only 1 NSPRIV PWR non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. 1 1 read-write NSPRIV NonSecure Read and write to PWR nonsecure functions can be done by privileged or unprivileged access 0 Secure Read and write to PWR nonsecure functions can be done by privileged access only 1 SR SR PWR status register 0x38 0x20 0x00000000 0xFFFFFFFF CSSF Clear Stop and Standby flags This bit is protected against non-secure access when LPMSECÂ =Â 1 in PWR_SECCFGR. This bit is protected against unprivileged access when LPMSECÂ =Â 1 and SPRIVÂ =Â 1 in PWR_PRIVCFGR, or when LPMSECÂ =Â 0 and NSPRIVÂ =Â 1. Writing 1 to this bit clears the STOPF and SBF flags. 0 1 write-only CSSFW Clear Clear the STOPF and SBF flags 1 STOPF Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit. 1 1 read-only STOPFR NoStop The device did not enter any Stop mode 0 Stop The device entered a Stop mode 1 SBF Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. 2 1 read-only SBFR NoStandby The device did not enter Standby mode 0 Standby The device entered Standby mode 1 SVMSR SVMSR 0x3C 0x20 0x00008000 0xFFFFFFFF REGS Regulator selection 1 1 read-only REGS LDO LDO selected 0 SMPS SMPS selected 1 PVDO VDD voltage detector output 4 1 read-only PVDO EqualOrAboveThreshold VDD is equal or above the PVD threshold selected by PVDLS[2:0] 0 BelowThreshold VDD is below the PVD threshold selected by PVDLS[2:0] 1 ACTVOSRDY Voltage level ready for currently used VOS 15 1 read-only ACTVOSRDY NotReady VCORE is above or below the current voltage scaling provided by ACTVOS[1:0] 0 Ready VCORE is equal to the current voltage scaling provided by ACTVOS[1:0] 1 ACTVOS VOS currently applied to VCORE This field provides the last VOS value. 16 2 read-only ACTVOS Range4 Range 4 (lowest power) 0 Range3 Range 3 1 Range2 Range 2 2 Range1 Range 1 (highest frequency) 3 VDDUSBRDY VDDUSB ready 24 1 read-only VDDUSBRDY BelowThreshold VDDUSB is below the threshold of the VDDUSB voltage monitor 0 EqualOrAboveThreshold VDDUSB is equal or above the threshold of the VDDUSB voltage monitor 1 VDDIO2RDY VDDIO2 ready 25 1 read-only VDDIO2RDY BelowThreshold VDDIO2 is below the threshold of the VDDIO2 voltage monitor 0 EqualOrAboveThreshold VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor 1 VDDA1RDY VDDA ready versus 1.6V voltage monitor 26 1 read-only VDDA1RDY BelowThreshold VDDA is below the threshold of the VDDA voltage monitor 1 (around 1.6 V) 0 EqualOrAboveThreshold VDDA is equal or above the threshold of the VDDA voltage monitor 1 (around 1.6 V) 1 VDDA2RDY VDDA ready versus 1.8Â V voltage monitor 27 1 read-only VDDA2RDY BelowThreshold VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V) 0 AboveThreshold VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V) 1 BDSR BDSR PWR Backup domain status register 0x40 0x20 0x00000000 0xFFFFFFFF VBATH Backup domain voltage level monitoring versus high threshold 1 1 read-only VBATH BelowHigh VBAT < high threshold 0 AboveHigh VBAT â¥ high threshold 1 TEMPL Temperature level monitoring versus low threshold 2 1 read-only TEMPL AboveLow Temperature > low threshold 0 BelowLow Temperature â¤ low threshold 1 TEMPH Temperature level monitoring versus high threshold 3 1 read-only TEMPH BelowHigh Temperature < high threshold 0 AboveHigh Temperature â¥ high threshold 1 WUSR WUSR PWR wakeup status register 0x44 0x20 0x00000000 0xFFFFFFFF WUF1 Wakeup flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of PWR_WUSCR when WUSEL â 11, or by hardware when WUPEN1Â =Â 0. 0 1 read-only WUF1 NoWakeup No wakeup event occurred on WKUPx pin 0 Wakeup A wakeup event occurred on WKUPx pin 1 WUF2 Wakeup flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of PWR_WUSCR when WUSEL â 11, or by hardware when WUPEN2Â =Â 0. 1 1 read-only WUF3 Wakeup flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of PWR_WUSCR when WUSEL â 11, or by hardware when WUPEN3Â =Â 0. 2 1 read-only WUF4 Wakeup flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of PWR_WUSCR when WUSEL â 11, or by hardware when WUPEN4Â =Â 0. 3 1 read-only WUF5 Wakeup flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of PWR_WUSCR when WUSEL â 11, or by hardware when WUPEN5Â =Â 0. 4 1 read-only WUF6 Wakeup flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of PWR_WUSCR when WUSEL â 11, or by hardware when WUPEN6Â =Â 0. If WUSELÂ =Â 11, this bit is cleared by hardware when all internal wakeup source are cleared. 5 1 read-only WUF7 Wakeup flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of PWR_WUSCR when WUSEL â 11, or by hardware when WUPEN7Â =Â 0. If WUSELÂ =Â 11, this bit is cleared by hardware when all internal wakeup source are cleared. 6 1 read-only WUF8 Wakeup flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of PWR_WUSCR when WUSEL â 11, or by hardware when WUPEN8Â =Â 0. If WUSELÂ =Â 11, this bit is cleared by hardware when all internal wakeup source are cleared. 7 1 read-only WUSCR WUSCR PWR wakeup status clear register 0x48 0x20 0x00000000 0xFFFFFFFF CWUF1 Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in PWR_WUSR. 0 1 write-only CWUF1 Clear Clear the WUFx flag in PWR_WUSR 1 CWUF2 Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in PWR_WUSR. 1 1 write-only CWUF3 Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in PWR_WUSR. 2 1 write-only CWUF4 Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in PWR_WUSR. 3 1 write-only CWUF5 Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in PWR_WUSR. 4 1 write-only CWUF6 Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in PWR_WUSR. 5 1 write-only CWUF7 Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in PWR_WUSR. 6 1 write-only CWUF8 Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in PWR_WUSR. 7 1 write-only APCR APCR PWR apply pull configuration register 0x4C 0x20 0x00000000 0xFFFFFFFF APC Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx are applied. When this bit is cleared, PWR_PUCRx and PWR_PDCRx are not applied to the I/Os. 0 1 read-write APC Disabled PWR_PUCRx and PWR_PDCRx are not applied to the I/Os 0 Enabled I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx are applied 1 PUCRA PUCRA PWR port A pull-up control register 0x50 0x20 0x00000000 0xFFFFFFFF PU0 Port A pull-up bit 0 1 read-write PU0 Disabled Pull-up disabled 0 Enabled Pull-up enabled 1 PU1 Port A pull-up bit 1 1 read-write PU2 Port A pull-up bit 2 1 read-write PU3 Port A pull-up bit 3 1 read-write PU4 Port A pull-up bit 4 1 read-write PU5 Port A pull-up bit 5 1 read-write PU6 Port A pull-up bit 6 1 read-write PU7 Port A pull-up bit 7 1 read-write PU8 Port A pull-up bit 8 1 read-write PU9 Port A pull-up bit 9 1 read-write PU10 Port A pull-up bit 10 1 read-write PU11 Port A pull-up bit 11 1 read-write PU12 Port A pull-up bit 12 1 read-write PU13 Port A pull-up bit 13 1 read-write PU15 Port A pull-up bit 15 When set, this bit activates the pull-up on PA15 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD15 bit is also set. 15 1 read-write PDCRA PDCRA PWR port A pull-down control register 0x54 0x20 0x00000000 0xFFFFFFFF PD0 Port A pull-down bit 0 1 read-write PD0 Disabled Pull-down disabled 0 Enabled Pull-down enabled 1 PD1 Port A pull-down bit 1 1 read-write PD2 Port A pull-down bit 2 1 read-write PD3 Port A pull-down bit 3 1 read-write PD4 Port A pull-down bit 4 1 read-write PD5 Port A pull-down bit 5 1 read-write PD6 Port A pull-down bit 6 1 read-write PD7 Port A pull-down bit 7 1 read-write PD8 Port A pull-down bit 8 1 read-write PD9 Port A pull-down bit 9 1 read-write PD10 Port A pull-down bit 10 1 read-write PD11 Port A pull-down bit 11 1 read-write PD12 Port A pull-down bit 12 1 read-write PD14 Port A pull-down bit 14 1 read-write PUCRB PUCRB PWR port B pull-up control register 0x58 0x20 0x00000000 0xFFFFFFFF PU0 Port B pull-up bit 0 1 read-write PU0 Disabled Pull-up disabled 0 Enabled Pull-up enabled 1 PU1 Port B pull-up bit 1 1 read-write PU2 Port B pull-up bit 2 1 read-write PU3 Port B pull-up bit 3 1 read-write PU4 Port B pull-up bit 4 1 read-write PU5 Port B pull-up bit 5 1 read-write PU6 Port B pull-up bit 6 1 read-write PU7 Port B pull-up bit 7 1 read-write PU8 Port B pull-up bit 8 1 read-write PU9 Port B pull-up bit 9 1 read-write PU10 Port B pull-up bit 10 1 read-write PU11 Port B pull-up bit 11 1 read-write PU12 Port B pull-up bit 12 1 read-write PU13 Port B pull-up bit 13 1 read-write PU14 Port B pull-up bit 14 1 read-write PU15 Port B pull-up bit 15 1 read-write PDCRB PDCRB PWR port B pull-down control register 0x5C 0x20 0x00000000 0xFFFFFFFF PD0 Port B pull-down bit 0 1 read-write PD0 Disabled Pull-down disabled 0 Enabled Pull-down enabled 1 PD1 Port B pull-down bit 1 1 read-write PD2 Port B pull-down bit 2 1 read-write PD3 Port B pull-down bit 3 1 read-write PD5 Port B pull-down bit 5 1 read-write PD6 Port B pull-down bit 6 1 read-write PD7 Port B pull-down bit 7 1 read-write PD8 Port B pull-down bit 8 1 read-write PD9 Port B pull-down bit 9 1 read-write PD10 Port B pull-down bit 10 1 read-write PD11 Port B pull-down bit 11 1 read-write PD12 Port B pull-down bit 12 1 read-write PD13 Port B pull-down bit 13 1 read-write PD14 Port B pull-down bit 14 1 read-write PD15 Port B pull-down bit 15 1 read-write PUCRC PUCRC PWR port C pull-up control register 0x60 0x20 0x00000000 0xFFFFFFFF PU0 Port C pull-up bit 0 1 read-write PU0 Disabled Pull-up disabled 0 Enabled Pull-up enabled 1 PU1 Port C pull-up bit 1 1 read-write PU2 Port C pull-up bit 2 1 read-write PU3 Port C pull-up bit 3 1 read-write PU4 Port C pull-up bit 4 1 read-write PU5 Port C pull-up bit 5 1 read-write PU6 Port C pull-up bit 6 1 read-write PU7 Port C pull-up bit 7 1 read-write PU8 Port C pull-up bit 8 1 read-write PU9 Port C pull-up bit 9 1 read-write PU10 Port C pull-up bit 10 1 read-write PU11 Port C pull-up bit 11 1 read-write PU12 Port C pull-up bit 12 1 read-write PU13 Port C pull-up bit 13 1 read-write PU14 Port C pull-up bit 14 1 read-write PU15 Port C pull-up bit 15 1 read-write PDCRC PDCRC PWR port C pull-down control register 0x64 0x20 0x00000000 0xFFFFFFFF PD0 Port C pull-down bit 0 1 read-write PD0 Disabled Pull-down disabled 0 Enabled Pull-down enabled 1 PD1 Port C pull-down bit 1 1 read-write PD2 Port C pull-down bit 2 1 read-write PD3 Port C pull-down bit 3 1 read-write PD4 Port C pull-down bit 4 1 read-write PD5 Port C pull-down bit 5 1 read-write PD6 Port C pull-down bit 6 1 read-write PD7 Port C pull-down bit 7 1 read-write PD8 Port C pull-down bit 8 1 read-write PD9 Port C pull-down bit 9 1 read-write PD10 Port C pull-down bit 10 1 read-write PD11 Port C pull-down bit 11 1 read-write PD12 Port C pull-down bit 12 1 read-write PD13 Port C pull-down bit 13 1 read-write PD14 Port C pull-down bit 14 1 read-write PD15 Port C pull-down bit 15 1 read-write PUCRD PUCRD PWR port D pull-up control register 0x68 0x20 0x00000000 0xFFFFFFFF PU0 Port D pull-up bit 0 1 read-write PU0 Disabled Pull-up disabled 0 Enabled Pull-up enabled 1 PU1 Port D pull-up bit 1 1 read-write PU2 Port D pull-up bit 2 1 read-write PU3 Port D pull-up bit 3 1 read-write PU4 Port D pull-up bit 4 1 read-write PU5 Port D pull-up bit 5 1 read-write PU6 Port D pull-up bit 6 1 read-write PU7 Port D pull-up bit 7 1 read-write PU8 Port D pull-up bit 8 1 read-write PU9 Port D pull-up bit 9 1 read-write PU10 Port D pull-up bit 10 1 read-write PU11 Port D pull-up bit 11 1 read-write PU12 Port D pull-up bit 12 1 read-write PU13 Port D pull-up bit 13 1 read-write PU14 Port D pull-up bit 14 1 read-write PU15 Port D pull-up bit 15 1 read-write PDCRD PDCRD PWR port D pull-down control register 0x6C 0x20 0x00000000 0xFFFFFFFF PD0 Port D pull-down bit 0 1 read-write PD0 Disabled Pull-down disabled 0 Enabled Pull-down enabled 1 PD1 Port D pull-down bit 1 1 read-write PD2 Port D pull-down bit 2 1 read-write PD3 Port D pull-down bit 3 1 read-write PD4 Port D pull-down bit 4 1 read-write PD5 Port D pull-down bit 5 1 read-write PD6 Port D pull-down bit 6 1 read-write PD7 Port D pull-down bit 7 1 read-write PD8 Port D pull-down bit 8 1 read-write PD9 Port D pull-down bit 9 1 read-write PD10 Port D pull-down bit 10 1 read-write PD11 Port D pull-down bit 11 1 read-write PD12 Port D pull-down bit 12 1 read-write PD13 Port D pull-down bit 13 1 read-write PD14 Port D pull-down bit 14 1 read-write PD15 Port D pull-down bit 15 1 read-write PUCRE PUCRE PWR port E pull-up control register 0x70 0x20 0x00000000 0xFFFFFFFF PU0 Port E pull-up bit 0 1 read-write PU0 Disabled Pull-up disabled 0 Enabled Pull-up enabled 1 PU1 Port E pull-up bit 1 1 read-write PU2 Port E pull-up bit 2 1 read-write PU3 Port E pull-up bit 3 1 read-write PU4 Port E pull-up bit 4 1 read-write PU5 Port E pull-up bit 5 1 read-write PU6 Port E pull-up bit 6 1 read-write PU7 Port E pull-up bit 7 1 read-write PU8 Port E pull-up bit 8 1 read-write PU9 Port E pull-up bit 9 1 read-write PU10 Port E pull-up bit 10 1 read-write PU11 Port E pull-up bit 11 1 read-write PU12 Port E pull-up bit 12 1 read-write PU13 Port E pull-up bit 13 1 read-write PU14 Port E pull-up bit 14 1 read-write PU15 Port E pull-up bit 15 1 read-write PDCRE PDCRE PWR port E pull-down control register 0x74 0x20 0x00000000 0xFFFFFFFF PD0 Port E pull-down bit 0 1 read-write PD0 Disabled Pull-down disabled 0 Enabled Pull-down enabled 1 PD1 Port E pull-down bit 1 1 read-write PD2 Port E pull-down bit 2 1 read-write PD3 Port E pull-down bit 3 1 read-write PD4 Port E pull-down bit 4 1 read-write PD5 Port E pull-down bit 5 1 read-write PD6 Port E pull-down bit 6 1 read-write PD7 Port E pull-down bit 7 1 read-write PD8 Port E pull-down bit 8 1 read-write PD9 Port E pull-down bit 9 1 read-write PD10 Port E pull-down bit 10 1 read-write PD11 Port E pull-down bit 11 1 read-write PD12 Port E pull-down bit 12 1 read-write PD13 Port E pull-down bit 13 1 read-write PD14 Port E pull-down bit 14 1 read-write PD15 Port E pull-down bit 15 1 read-write PUCRF PUCRF PWR port F pull-up control register 0x78 0x20 0x00000000 0xFFFFFFFF PU0 Port F pull-up bit 0 1 read-write PU0 Disabled Pull-up disabled 0 Enabled Pull-up enabled 1 PU1 Port F pull-up bit 1 1 read-write PU2 Port F pull-up bit 2 1 read-write PU3 Port F pull-up bit 3 1 read-write PU4 Port F pull-up bit 4 1 read-write PU5 Port F pull-up bit 5 1 read-write PU6 Port F pull-up bit 6 1 read-write PU7 Port F pull-up bit 7 1 read-write PU8 Port F pull-up bit 8 1 read-write PU9 Port F pull-up bit 9 1 read-write PU10 Port F pull-up bit 10 1 read-write PU11 Port F pull-up bit 11 1 read-write PU12 Port F pull-up bit 12 1 read-write PU13 Port F pull-up bit 13 1 read-write PU14 Port F pull-up bit 14 1 read-write PU15 Port F pull-up bit 15 1 read-write PDCRF PDCRF PWR port F pull-down control register 0x7C 0x20 0x00000000 0xFFFFFFFF PD0 Port F pull-down bit 0 1 read-write PD0 Disabled Pull-down disabled 0 Enabled Pull-down enabled 1 PD1 Port F pull-down bit 1 1 read-write PD2 Port F pull-down bit 2 1 read-write PD3 Port F pull-down bit 3 1 read-write PD4 Port F pull-down bit 4 1 read-write PD5 Port F pull-down bit 5 1 read-write PD6 Port F pull-down bit 6 1 read-write PD7 Port F pull-down bit 7 1 read-write PD8 Port F pull-down bit 8 1 read-write PD9 Port F pull-down bit 9 1 read-write PD10 Port F pull-down bit 10 1 read-write PD11 Port F pull-down bit 11 1 read-write PD12 Port F pull-down bit 12 1 read-write PD13 Port F pull-down bit 13 1 read-write PD14 Port F pull-down bit 14 1 read-write PD15 Port F pull-down bit 15 1 read-write PUCRG PUCRG PWR port G pull-up control register 0x80 0x20 0x00000000 0xFFFFFFFF PU0 Port G pull-up bit 0 1 read-write PU0 Disabled Pull-up disabled 0 Enabled Pull-up enabled 1 PU1 Port G pull-up bit 1 1 read-write PU2 Port G pull-up bit 2 1 read-write PU3 Port G pull-up bit 3 1 read-write PU4 Port G pull-up bit 4 1 read-write PU5 Port G pull-up bit 5 1 read-write PU6 Port G pull-up bit 6 1 read-write PU7 Port G pull-up bit 7 1 read-write PU8 Port G pull-up bit 8 1 read-write PU9 Port G pull-up bit 9 1 read-write PU10 Port G pull-up bit 10 1 read-write PU11 Port G pull-up bit 11 1 read-write PU12 Port G pull-up bit 12 1 read-write PU13 Port G pull-up bit 13 1 read-write PU14 Port G pull-up bit 14 1 read-write PU15 Port G pull-up bit 15 1 read-write PDCRG PDCRG PWR port G pull-down control register 0x84 0x20 0x00000000 0xFFFFFFFF PD0 Port G pull-down bit 0 1 read-write PD0 Disabled Pull-down disabled 0 Enabled Pull-down enabled 1 PD1 Port G pull-down bit 1 1 read-write PD2 Port G pull-down bit 2 1 read-write PD3 Port G pull-down bit 3 1 read-write PD4 Port G pull-down bit 4 1 read-write PD5 Port G pull-down bit 5 1 read-write PD6 Port G pull-down bit 6 1 read-write PD7 Port G pull-down bit 7 1 read-write PD8 Port G pull-down bit 8 1 read-write PD9 Port G pull-down bit 9 1 read-write PD10 Port G pull-down bit 10 1 read-write PD11 Port G pull-down bit 11 1 read-write PD12 Port G pull-down bit 12 1 read-write PD13 Port G pull-down bit 13 1 read-write PD14 Port G pull-down bit 14 1 read-write PD15 Port G pull-down bit 15 1 read-write PUCRH PUCRH PWR port H pull-up control register 0x88 0x20 0x00000000 0xFFFFFFFF PU0 Port H pull-up bit 0 1 read-write PU0 Disabled Pull-up disabled 0 Enabled Pull-up enabled 1 PU1 Port H pull-up bit 1 1 read-write PU2 Port H pull-up bit 2 1 read-write PU3 Port H pull-up bit 3 1 read-write PU4 Port H pull-up bit 4 1 read-write PU5 Port H pull-up bit 5 1 read-write PU6 Port H pull-up bit 6 1 read-write PU7 Port H pull-up bit 7 1 read-write PU8 Port H pull-up bit 8 1 read-write PU9 Port H pull-up bit 9 1 read-write PU10 Port H pull-up bit 10 1 read-write PU11 Port H pull-up bit 11 1 read-write PU12 Port H pull-up bit 12 1 read-write PU13 Port H pull-up bit 13 1 read-write PU14 Port H pull-up bit 14 1 read-write PU15 Port H pull-up bit 15 1 read-write PDCRH PDCRH PWR port H pull-down control register 0x8C 0x20 0x00000000 0xFFFFFFFF PD0 Port H pull-down bit 0 1 read-write PD0 Disabled Pull-down disabled 0 Enabled Pull-down enabled 1 PD1 Port H pull-down bit 1 1 read-write PD2 Port H pull-down bit 2 1 read-write PD3 Port H pull-down bit 3 1 read-write PD4 Port H pull-down bit 4 1 read-write PD5 Port H pull-down bit 5 1 read-write PD6 Port H pull-down bit 6 1 read-write PD7 Port H pull-down bit 7 1 read-write PD8 Port H pull-down bit 8 1 read-write PD9 Port H pull-down bit 9 1 read-write PD10 Port H pull-down bit 10 1 read-write PD11 Port H pull-down bit 11 1 read-write PD12 Port H pull-down bit 12 1 read-write PD13 Port H pull-down bit 13 1 read-write PD14 Port H pull-down bit 14 1 read-write PD15 Port H pull-down bit 15 1 read-write PUCRI PUCRI PWR port I pull-up control register 0x90 0x20 0x00000000 0xFFFFFFFF PU0 Port I pull-up bit 0 1 read-write PU0 Disabled Pull-up disabled 0 Enabled Pull-up enabled 1 PU1 Port I pull-up bit 1 1 read-write PU2 Port I pull-up bit 2 1 read-write PU3 Port I pull-up bit 3 1 read-write PU4 Port I pull-up bit 4 1 read-write PU5 Port I pull-up bit 5 1 read-write PU6 Port I pull-up bit 6 1 read-write PU7 Port I pull-up bit 7 1 read-write PDCRI PDCRI PWR port I pull-down control register 0x94 0x20 0x00000000 0xFFFFFFFF PD0 Port I pull-down bit 0 1 read-write PD0 Disabled Pull-down disabled 0 Enabled Pull-down enabled 1 PD1 Port I pull-down bit 1 1 read-write PD2 Port I pull-down bit 2 1 read-write PD3 Port I pull-down bit 3 1 read-write PD4 Port I pull-down bit 4 1 read-write PD5 Port I pull-down bit 5 1 read-write PD6 Port I pull-down bit 6 1 read-write PD7 Port I pull-down bit 7 1 read-write CR4 PWR control register 4 0xA8 0x20 read-write 0x00000000 SRAM1PDS4 0 1 SRAM1PDS4 Disabled SRAM1 page x content retained in Stop modes 0 Enabled SRAM1 page x content lost in Stop modes 1 SRAM1PDS5 1 1 SRAM1PDS6 2 1 SRAM1PDS7 3 1 SRAM1PDS8 4 1 SRAM1PDS9 5 1 SRAM1PDS10 6 1 SRAM1PDS11 7 1 SRAM1PDS12 8 1 SRAM3PDS9 10 1 SRAM3PDS9 Disabled SRAM3 page x content retained in Stop modes 0 Enabled SRAM3 page x content lost in Stop modes 1 SRAM3PDS10 11 1 SRAM3PDS11 12 1 SRAM3PDS12 13 1 SRAM3PDS13 14 1 CR5 0xAC 0x20 0x00000000 SEC_PWR 0x56020800 RCC Reset and clock control RCC 0x46020C00 0x0 0x400 registers RCC RCC non-secure global interrupt 9 RCC_S RCC secure global interrupt 10 CR CR RCC clock control register 0x0 0x20 0x00000035 0xFFFFFFFF MSISON MSIS clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. This bit is set by hardware to force theï¿½MSIS oscillator on when exiting Standby or Shutdown mode. It is set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes, or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock. 0 1 read-write MSISON Disabled MSIS (MSI system) oscillator off 0 Enabled MSIS (MSI system) oscillator on 1 MSIKERON MSI enable for some peripheral kernels This bit is set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI on in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see Sectionï¿½11.4.24 for more details). This bit must be configured at 0 before entering Stop 3 mode. 1 1 read-write MSIKERON NotForced No effect on MSI oscillator 0 Forced MSI oscillator forced ON even in Stop mode 1 MSISRDY MSIS clock ready flag This bit is set by hardware to indicate that the MSIS oscillator is stable. It is set only when MSIS is enabled by software (by setting MSISON). Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles. 2 1 read-only MSISRDYR NotReady MSIS (MSI system) oscillator not ready 0 Ready MSIS (MSI system) oscillator ready 1 MSIPLLEN MSI clock PLL-mode enable This bit is set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR). 3 1 read-write MSIPLLEN Disabled MSI PLL-mode OFF 0 Enabled MSI PLL-mode ON 1 MSIKON MSIK clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MSIK when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. It is set by hardware to force the MSIK oscillator on when STOPWUCK = 0 or STOPKERWUCKï¿½=ï¿½0 when exiting Stop modes, or in case of a failure of the HSE oscillator. 4 1 read-write MSIKON Disabled MSIK (MSI kernel) oscillator disabled 0 Enabled MSIK (MSI kernel) oscillator enabled 1 MSIKRDY MSIK clock ready flag This bit is set by hardware to indicate that the MSIK is stable. It is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles. 5 1 read-only MSIKRDYR NotReady MSIK (MSI kernel) oscillator not ready 0 Ready MSIK (MSI kernel) oscillator ready 1 MSIPLLSEL MSI clock with PLL mode selection This bit is set and cleared by software to select which MSI output clock uses the PLL mode. Itï¿½can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to both clock outputs. 6 1 read-write MSIPLLSEL MSIK PLL mode applied to MSIK (MSI kernel) clock output 0 MSIS PLL mode applied to MSIS (MSI system) clock output 1 MSIPLLFAST MSI PLL mode fast startup This bit is set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. Theï¿½fast start-up is active when the MSI in PLL mode returns from switch off. 7 1 read-write MSIPLLFAST Normal MSI PLL normal start-up 0 Fast MSI PLL fast start-up 1 HSION HSI16 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force theï¿½HSI16 oscillator on when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. 8 1 read-write HSION Disabled HSI16 oscillator off 0 Enabled HSI16 oscillator on 1 HSIKERON HSI16 enable for some peripheral kernels This bit is set and cleared by software to force HSI16 ON even in Stop modes. Keeping HSI16 on in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value. Refer to Sectionï¿½11.4.24 for more details. This bit must be configured at 0 before entering Stop 3 mode. 9 1 read-write HSIKERON NotForced No effect on HSI16 oscillator 0 Forced HSI16 oscillator forced on even in Stop mode 1 HSIRDY HSI16 clock ready flag This bit is set by hardware to indicate that HSI16 oscillator is stable. It is set only when HSI16 is enabled by software (by setting HSION). Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles. 10 1 read-only HSIRDYR NotReady HSI16 oscillator not ready 0 Ready HSI16 oscillator ready 1 HSI48ON HSI48 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSI48 when entering in Stop, Standby, or Shutdown modes. 12 1 read-write HSI48ON Disabled HSI48 oscillator off 0 Enabled HSI48 oscillator on 1 HSI48RDY HSI48 clock ready flag This bit is set by hardware to indicate that HSI48 oscillator is stable. Itis set only when HSI48 is enabled by software (by setting HSI48ON). 13 1 read-only HSI48RDYR NotReady HSI48 oscillator not ready 0 Ready HSI48 oscillator ready 1 SHSION SHSI clock enable This bit is set and cleared by software. It is cleared by hardware to stop the SHSI when entering in Stop, Standby, or Shutdown modes. 14 1 read-write SHSION Disabled SHSI oscillator off 0 Enabled SHSI oscillator on 1 SHSIRDY SHSI clock ready flag This bit is set by hardware to indicate that the SHSI oscillator is stable. It is set only when SHSI is enabled by software (by setting SHSION). Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles. 15 1 read-only SHSIRDYR NotReady SHSI oscillator not ready 0 Ready SHSI oscillator ready 1 HSEON HSE clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 16 1 read-write HSEON Disabled HSE oscillator off 0 Enabled HSE oscillator on 1 HSERDY HSE clock ready flag This bit is set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles. 17 1 read-only HSERDYR NotReady HSE oscillator not ready 0 Ready HSE oscillator ready 1 HSEBYP HSE crystal oscillator bypass This bit is set and cleared by software to bypass the oscillator with an external clock. Theï¿½external clock must be enabled with the HSEON bit set, to be used by the device. Thisï¿½bit can be written only if the HSE oscillator is disabled. 18 1 read-write HSEBYP NotBypassed HSE crystal oscillator not bypassed 0 Bypassed HSE crystal oscillator bypassed with external clock 1 CSSON Clock security system enable This bit is set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. 19 1 read-write CSSON Disabled Clock security system OFF (clock detector OFF) 0 Enabled Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not) 1 HSEEXT HSE external clock bypass mode This bit is set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled. 20 1 read-write HSEEXT Analog external HSE clock analog mode 0 Digital external HSE clock digital mode (through I/O Schmitt trigger) 1 PLL1ON PLL1 enable This bit is set and cleared by software to enable the main PLL. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock. 24 1 read-write PLL1ON Disabled PLL1 OFF 0 Enabled PLL1 ON 1 PLL1RDY PLL1 clock ready flag This bit is set by hardware to indicate that the PLL1 is locked. 25 1 read-only PLL1RDYR Unlocked PLL1 unlocked 0 Locked PLL1 locked 1 PLL2ON PLL2 enable This bit is set and cleared by software to enable PLL2. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. 26 1 read-write PLL2ON Disabled PLL2 OFF 0 Enabled PLL2 ON 1 PLL2RDY PLL2 clock ready flag This bit is set by hardware to indicate that the PLL2 is locked. 27 1 read-only PLL2RDYR Unlocked PLL2 unlocked 0 Locked PLL2 locked 1 PLL3ON PLL3 enable This bit is set and cleared by software to enable PLL3. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. 28 1 read-write PLL3ON Disabled PLL3 OFF 0 Enabled PLL3 ON 1 PLL3RDY PLL3 clock ready flag This bit is set by hardware to indicate that the PLL3 is locked. 29 1 read-only PLL3RDYR Unlocked PLL3 unlocked 0 Locked PLL3 locked 1 ICSCR1 ICSCR1 RCC internal clock sources calibration register 1 0x8 0x20 0x44000000 0xFFF00000 MSICAL3 MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. 0 5 read-only 0 31 MSICAL2 MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. 5 5 read-only 0 31 MSICAL1 MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. 10 5 read-only 0 31 MSICAL0 MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. 15 5 read-only 0 31 MSIBIAS MSI bias mode selection This bit is set by software to select the MSI bias mode. By default, the MSI bias is inï¿½continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption when the regulator is in range 4, or when the device is in Stop 1 or Stopï¿½2 mode, but itï¿½decreases the MSI accuracy 22 1 read-write MSIBIAS Continuous MSI bias continuous mode (clock accuracy fast settling time) 0 Sampling MSI bias sampling mode when the regulator is in range 4, or when the device is in Stop 1 or Stop 2 (ultra-low-power mode) 1 MSIRGSEL MSI clock range selection This bit is set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect. After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR. 23 1 read-write MSIRGSEL CSR MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR 0 ICSCR1 MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1 1 MSIKRANGE MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSIKRANGE can be modified when MSIK is off (MSISON = 0) or when MSIK is ready (MSIKRDYï¿½=ï¿½1). MSIKRANGE must NOT be modified when MSIK is on and NOT ready (MSIKON = 1 and MSIKRDY = 0) Note: MSIKRANGE is kept when the device wakes up from Stop mode, except when theï¿½MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware intoï¿½range 2 (24 MHz). 24 4 read-write MSIKRANGE f_48MHz Range 0 around 48 MHz 0 f_24MHz Range 1 around 24 MHz 1 f_16MHz Range 2 around 16 MHz 2 f_12MHz Range 3 around 12 MHz 3 f_4MHz Range 4 around 4 MHz 4 f_2MHz Range 5 around 2 MHz 5 f_1_333MHz Range 6 around 1.33 MHz 6 f_1MHz Range 7 around 1 MHz 7 f_3_072MHz Range 8 around 3.072 MHz 8 f_1_536MHz Range 9 around 1.536 MHz 9 f_1_024MHz Range 10 around 1.024 MHz 10 f_768kHz Range 11 around 768 kHz 11 f_400kHz Range 12 around 400 kHz 12 f_200kHz Range 13 around 200 kHz 13 f_133kHz Range 14 around 133 kHz 14 f_100kHz Range 15 around 100 kHz 15 MSISRANGE MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSISRANGE can be modified when MSIS is off (MSISON = 0) or when MSIS is ready (MSISRDYï¿½=ï¿½1). MSISRANGE must NOT be modified when MSIS is on and NOT ready (MSISONï¿½=ï¿½1 and MSISRDYï¿½=ï¿½0) Note: MSISRANGE is kept when the device wakes up from Stop mode, except when theï¿½MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into range 2 (24 MHz). 28 4 read-write ICSCR2 ICSCR2 RCC internal clock sources calibration register 2 0xC 0x20 0x00084210 0xFFFFFFFF MSITRIM3 MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. 0 5 read-write 0 31 MSITRIM2 MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. 5 5 read-write 0 31 MSITRIM1 MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. 10 5 read-write 0 31 MSITRIM0 MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. 15 5 read-write 0 31 ICSCR3 ICSCR3 RCC internal clock sources calibration register 3 0x10 0x20 0x00100000 0xFFFFF000 HSICAL HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. 0 12 read-only 0 4095 HSITRIM HSI clock trimming These bits provide an additional user-programmable trimming value that is added to HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI. 16 5 read-write 0 31 CRRCR CRRCR RCC clock recovery RC register 0x14 0x20 0x00000000 0xFFFFF000 HSI48CAL HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. 0 9 read-only 0 511 CFGR1 CFGR1 RCC clock configuration register 1 0x1C 0x20 0x00000000 0xFFFFFFFF SW system clock switch This bitfield is set and cleared by software to select system clock source (SYSCLK). It is configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. This bitfield is configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK. 0 2 read-write SW MSIS MSIS selected as system clock 0 HSI16 HSI16 selected as system clock 1 HSE HSE selected as system clock 2 PLL PLL pll1_r_ck selected as system clock 3 SWS system clock switch status This bitfield is set and cleared by hardware to indicate which clock source is used as system clock. 2 2 read-only SWSR MSIS MSIS oscillator used as system clock 0 HSI16 HSI16 oscillator used as system clock 1 HSE HSE used as system clock 2 PLL PLL pll1_r_ck used as system clock 3 STOPWUCK wake-up from Stop and CSS backup clock selection This bit is set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system onï¿½HSE. STOPWUCK must not be modified when the CSS is enabled by HSECSSON inï¿½RCC_CR, and the system clock is HSE (SWS = 10) or a switch on HSE isï¿½requested (SWï¿½=ï¿½10). 4 1 read-write STOPWUCK MSIS MSIS oscillator selected as wake-up from stop clock and CSS backup clock 0 HSI16 HSI16 oscillator selected as wake-up from stop clock and CSS backup clock 1 STOPKERWUCK wake-up from Stop kernel clock automatic enable selection This bit is set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals. 5 1 read-write STOPKERWUCK MSIK MSIK oscillator automatically enabled when exiting Stop mode or when a CSS on HSE event occurs. 0 HSI16 HSI16 oscillator automatically enabled when exiting Stop mode or when a CSS on HSE event occurs. 1 MCOSEL microcontroller clock output This bitfield is set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. 24 4 read-write MCOSEL None MCO output disabled, no clock on MCO 0 SYSCLK SYSCLK system clock selected 1 MSIS MSIS clock selected 2 HSI16 HSI16 clock selected 3 HSE HSE clock selected 4 PLL Main PLL clock pll1_r_ck selected 5 LSI LSI clock selected 6 LSE LSE clock selected 7 HSI48 Internal HSI48 clock selected 8 MSIK MSIK clock selected 9 MCOPRE microcontroller clock output prescaler This bitfield is set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed 28 3 read-write MCOPRE Div1 MCO divided by 1 0 Div2 MCO divided by 2 1 Div4 MCO divided by 4 2 Div8 MCO divided by 8 3 Div16 MCO divided by 16 4 CFGR2 CFGR2 RCC clock configuration register 2 0x20 0x20 0x00006000 0xFFFFFFFF HPRE AHB prescaler This bitfiled is set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Tableï¿½118). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided 0 4 read-write HPRE Div2 HCLK divided by 2 8 Div4 HCLK divided by 4 9 Div8 HCLK divided by 8 10 Div16 HCLK divided by 16 11 Div64 HCLK divided by 64 12 Div128 HCLK divided by 128 13 Div256 HCLK divided by 256 14 Div512 HCLK divided by 512 15 Div1 HCLK not divided true PPRE1 APB1 prescaler This bitfiled is set and cleared by software to control the division factor of APB1 clock (PCLK1). 0xx: PCLK1 not divided 4 3 read-write PPRE1 Div2 PCLK divided by 2 4 Div4 PCLK divided by 4 5 Div8 PCLK divided by 8 6 Div16 PCLK divided by 16 7 Div1 PCLK not divided true PPRE2 APB2 prescaler This bitfiled is set and cleared by software to control the division factor of APB2 clock (PCLK2). 0xx: PCLK2 not divided 8 3 read-write DPRE DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK). 0xx: DCLK not divided Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 12 3 read-write DPRE Div2 DCLK divided by 2 4 Div4 DCLK divided by 4 5 Div8 DCLK divided by 8 6 Div16 DCLK divided by 16 7 Div1 DCLK not divided true AHB1DIS AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1. 16 1 read-write AHB1DIS Enabled AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0 Disabled AHB1 clock disabled 1 AHB2DIS1 AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3. 17 1 read-write AHB2DIS1 Enabled AHB2_1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0 Disabled AHB2_1 clock disabled 1 AHB2DIS2 AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR2 are off. 18 1 read-write AHB2DIS2 Enabled AHB2_2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0 Disabled AHB2_2 clock disabled 1 APB1DIS APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. 19 1 read-write APB1DIS Enabled APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0 Disabled APB1 clock disabled 1 APB2DIS APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all APB2 peripherals clocks are off. 20 1 read-write APB2DIS Enabled APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0 Disabled APB2 clock disabled 1 CFGR3 CFGR3 RCC clock configuration register 3 0x24 0x20 0x00000000 0xFFFFFFFF PPRE3 APB3 prescaler This bitfield is set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided 4 3 read-write PPRE3 Div2 PCLK divided by 2 4 Div4 PCLK divided by 4 5 Div8 PCLK divided by 8 6 Div16 PCLK divided by 16 7 Div1 PCLK not divided true AHB3DIS AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4. 16 1 read-write AHB3DIS Enabled AHB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0 Disabled AHB3 clock disabled 1 APB3DIS APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. 17 1 read-write APB3DIS Enabled APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0 Disabled APB3 clock disabled 1 PLL1CFGR PLL1CFGR RCC PLL1 configuration register 0x28 0x20 0x00000000 0xFFFFFFFF PLL1SRC PLL1 entry clock source This bitfield is set and cleared by software to select PLL1 clock source. It can be written only when the PLL1 is disabled. In order to save power, when no PLL1 is used, this bitfield value must be zero. 0 2 read-write PLL1SRC NoClock No clock sent to PLLx 0 MSIS MSIS clock selected as PLLx clock entry 1 HSI16 HSI16 clock selected as PLLx clock entry 2 HSE HSE clock selected as PLLx clock entry 3 PLL1RGE PLL1 input frequency range This bit is set and reset by software to select the proper reference frequency range used for PLL1. It must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz 2 2 read-write PLL1RGE Range2 PLLx input (refx_ck) clock range frequency between 8 and 16 MHz 3 Range1 PLLx input (refx_ck) clock range frequency between 4 and 8 MHz true PLL1FRACEN PLL1 fractional latch enable This bit is set and reset by software to latch the content of PLL1FRACN in the Î£Î modulator. InÂ order to latch the PLL1FRACN value into the Î£Î modulator, PLL1FRACEN must be setÂ toÂ 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL initialization phase for details). 4 1 read-write PLL1FRACEN NoEffect No effect 0 Latch Content of PLLxFRACN latched in the Î£â modulator on PLLxFRACEN transition from 0 to 1 1 PLL1M Prescaler for PLL1 This bitfield is set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 8 4 read-write PLL1M Div1 division by 1 (bypass) 0 Div2 division by 2 1 Div3 division by 3 2 Div4 division by 4 3 Div5 division by 5 4 Div6 division by 6 5 Div7 division by 7 6 Div8 division by 8 7 Div9 division by 9 8 Div10 division by 10 9 Div11 division by 11 10 Div12 division by 12 11 Div13 division by 13 12 Div14 division by 14 13 Div15 division by 15 14 Div16 division by 16 15 PLL1MBOOST Prescaler for EPOD booster input clock This bitfield is set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1ï¿½inputï¿½clockï¿½frequency/PLL1MBOOST. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPODboost mode is disabled (see Sectionï¿½10: Power control (PWR)). others: reserved 12 4 read-write PLL1MBOOST Div1 division by 1 (bypass) 0 Div2 division by 2 1 Div4 division by 4 2 Div6 division by 6 3 Div8 division by 8 4 Div10 division by 10 5 Div12 division by 12 6 Div14 division by 14 7 Div16 division by 16 8 PLL1PEN PLL1 DIVP divider output enable This bit is set and reset by software to enable the pll1_p_ck output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when pll1_p_ck is not used. 16 1 read-write PLL1PEN Disabled pllx_p_ck output disabled 0 Enabled pllx_p_ck output enabled 1 PLL1QEN PLL1 DIVQ divider output enable This bit is set and reset by software to enable the pll1_q_ck output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when pll1_q_ck is not used. 17 1 read-write PLL1QEN Disabled pllx_q_ck output disabled 0 Enabled pllx_q_ck output enabled 1 PLL1REN PLL1 DIVR divider output enable This bit is set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when pll1_r_ck is not used. This bit can be cleared only when the PLL1 is not used as SYSCLK. 18 1 read-write PLL1REN Disabled pllx_r_ck ready interrupt disabled 0 Enabled pllx_r_ck ready interrupt enabled 1 PLL2CFGR PLL2CFGR RCC PLL2 configuration register 0x2C 0x20 0x00000000 0xFFFFFFFF PLL2SRC PLL2 entry clock source This bitfield is set and cleared by software to select PLL2 clock source. It can be written only when the PLL2 is disabled. To save power, when no PLL2 is used, this bitfield value must beï¿½zero. 0 2 read-write PLL2SRC NoClock No clock sent to PLLx 0 MSIS MSIS clock selected as PLLx clock entry 1 HSI16 HSI16 clock selected as PLLx clock entry 2 HSE HSE clock selected as PLLx clock entry 3 PLL2RGE PLL2 input frequency range This bitfield is set and reset by software to select the proper reference frequency range used forï¿½PLL2. It must be written before enabling the PLL2. 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz 2 2 read-write PLL2RGE Range2 PLLx input (refx_ck) clock range frequency between 8 and 16 MHz 3 Range1 PLLx input (refx_ck) clock range frequency between 4 and 8 MHz true PLL2FRACEN PLL2 fractional latch enable This bit is set and reset by software to latch the content of PLL2FRACN in the Î£Î modulator. In order to latch the PLL2FRACN value into the Î£Î modulator, PLL2FRACEN must be setÂ toÂ 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see PLL initialization phase for details). 4 1 read-write PLL2FRACEN NoEffect No effect 0 Latch Content of PLLxFRACN latched in the Î£â modulator on PLLxFRACEN transition from 0 to 1 1 PLL2M Prescaler for PLL2 This bitfield is set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 8 4 read-write PLL2M Div1 division by 1 (bypass) 0 Div2 division by 2 1 Div3 division by 3 2 Div4 division by 4 3 Div5 division by 5 4 Div6 division by 6 5 Div7 division by 7 6 Div8 division by 8 7 Div9 division by 9 8 Div10 division by 10 9 Div11 division by 11 10 Div12 division by 12 11 Div13 division by 13 12 Div14 division by 14 13 Div15 division by 15 14 Div16 division by 16 15 PLL2PEN PLL2 DIVP divider output enable This bit is set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2PEN and PLL2P bits must be set to 0 when pll2_p_ck is not used. 16 1 read-write PLL2PEN Disabled pllx_p_ck output disabled 0 Enabled pllx_p_ck output enabled 1 PLL2QEN PLL2 DIVQ divider output enable This bit is set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL2QEN and PLL2Q bits must be set to 0 when pll2_q_ck is not used. 17 1 read-write PLL2QEN Disabled pllx_q_ck output disabled 0 Enabled pllx_q_ck output enabled 1 PLL2REN PLL2 DIVR divider output enable This bit is set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, PLL2REN and PLL2R bits must be set to 0 when pll2_r_ck is not used. 18 1 read-write PLL2REN Disabled pllx_r_ck ready interrupt disabled 0 Enabled pllx_r_ck ready interrupt enabled 1 PLL3CFGR PLL3CFGR RCC PLL3 configuration register 0x30 0x20 0x00000000 0xFFFFFFFF PLL3SRC PLL3 entry clock source This bitfield is set and cleared by software to select PLL3 clock source. It can be written only when the PLL3 is disabled. To save power, when no PLL3 is used, this bitfield value must beï¿½zero. 0 2 read-write PLL3SRC NoClock No clock sent to PLLx 0 MSIS MSIS clock selected as PLLx clock entry 1 HSI16 HSI16 clock selected as PLLx clock entry 2 HSE HSE clock selected as PLLx clock entry 3 PLL3RGE PLL3 input frequency range This bit is set and reset by software to select the proper reference frequency range used forï¿½PLL3. It must be written before enabling the PLL3. 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz 2 2 read-write PLL3RGE Range2 PLLx input (refx_ck) clock range frequency between 8 and 16 MHz 3 Range1 PLLx input (refx_ck) clock range frequency between 4 and 8 MHz true PLL3FRACEN PLL3 fractional latch enable This bit is set and reset by software to latch the content of PLL3FRACN in the Î£Î modulator. In order to latch the PLL3FRACN value into the Î£Î modulator, PLL3FRACEN must be setÂ toÂ 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see PLL initialization phase for details). 4 1 read-write PLL3FRACEN NoEffect No effect 0 Latch Content of PLLxFRACN latched in the Î£â modulator on PLLxFRACEN transition from 0 to 1 1 PLL3M Prescaler for PLL3 This bitfield is set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M. This bitfield can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ... 8 4 read-write PLL3M Div1 division by 1 (bypass) 0 Div2 division by 2 1 Div3 division by 3 2 Div4 division by 4 3 Div5 division by 5 4 Div6 division by 6 5 Div7 division by 7 6 Div8 division by 8 7 Div9 division by 9 8 Div10 division by 10 9 Div11 division by 11 10 Div12 division by 12 11 Div13 division by 13 12 Div14 division by 14 13 Div15 division by 15 14 Div16 division by 16 15 PLL3PEN PLL3 DIVP divider output enable This bit is set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3PEN and PLL3P bits must be set to 0 when pll3_p_ck is not used. 16 1 read-write PLL3PEN Disabled pllx_p_ck output disabled 0 Enabled pllx_p_ck output enabled 1 PLL3QEN PLL3 DIVQ divider output enable This bit is set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3QEN and PLL3Q bits must be set to 0 when pll3_q_ck is not used. 17 1 read-write PLL3QEN Disabled pllx_q_ck output disabled 0 Enabled pllx_q_ck output enabled 1 PLL3REN PLL3 DIVR divider output enable This bit is set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3REN and PLL3R bits must be set to 0 when pll3_r_ck is not used. 18 1 read-write PLL3REN Disabled pllx_r_ck ready interrupt disabled 0 Enabled pllx_r_ck ready interrupt enabled 1 PLL1DIVR PLL1DIVR RCC PLL1 dividers register 0x34 0x20 0x01010280 0xFFFFFFFF PLL1N Multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded in PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16ï¿½MHz 0 9 read-write 3 511 PLL1P PLL1 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll1_p_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 9 7 read-write PLL1P Div1 pllx_p_ck = vcox_ck 0 Div2 pllx_p_ck = vcox_ck / 2 1 Div4 pllx_p_ck = vcox_ck / 4 3 Div6 pllx_p_ck = vcox_ck / 6 5 Div8 pllx_p_ck = vcox_ck / 8 7 Div10 pllx_p_ck = vcox_ck / 10 9 Div12 pllx_p_ck = vcox_ck / 12 11 Div14 pllx_p_ck = vcox_ck / 14 13 Div16 pllx_p_ck = vcox_ck / 16 15 Div18 pllx_p_ck = vcox_ck / 18 17 Div20 pllx_p_ck = vcox_ck / 20 19 Div22 pllx_p_ck = vcox_ck / 22 21 Div24 pllx_p_ck = vcox_ck / 24 23 Div26 pllx_p_ck = vcox_ck / 26 25 Div28 pllx_p_ck = vcox_ck / 28 27 Div30 pllx_p_ck = vcox_ck / 30 29 Div32 pllx_p_ck = vcox_ck / 32 31 Div34 pllx_p_ck = vcox_ck / 34 33 Div36 pllx_p_ck = vcox_ck / 36 35 Div38 pllx_p_ck = vcox_ck / 38 37 Div40 pllx_p_ck = vcox_ck / 40 39 Div42 pllx_p_ck = vcox_ck / 42 41 Div44 pllx_p_ck = vcox_ck / 44 43 Div46 pllx_p_ck = vcox_ck / 46 45 Div48 pllx_p_ck = vcox_ck / 48 47 Div50 pllx_p_ck = vcox_ck / 50 49 Div52 pllx_p_ck = vcox_ck / 52 51 Div54 pllx_p_ck = vcox_ck / 54 53 Div56 pllx_p_ck = vcox_ck / 56 55 Div58 pllx_p_ck = vcox_ck / 58 57 Div60 pllx_p_ck = vcox_ck / 60 59 Div62 pllx_p_ck = vcox_ck / 62 61 Div64 pllx_p_ck = vcox_ck / 64 63 Div66 pllx_p_ck = vcox_ck / 66 65 Div68 pllx_p_ck = vcox_ck / 68 67 Div70 pllx_p_ck = vcox_ck / 70 69 Div72 pllx_p_ck = vcox_ck / 72 71 Div74 pllx_p_ck = vcox_ck / 74 73 Div76 pllx_p_ck = vcox_ck / 76 75 Div78 pllx_p_ck = vcox_ck / 78 77 Div80 pllx_p_ck = vcox_ck / 80 79 Div82 pllx_p_ck = vcox_ck / 82 81 Div84 pllx_p_ck = vcox_ck / 84 83 Div86 pllx_p_ck = vcox_ck / 86 85 Div88 pllx_p_ck = vcox_ck / 88 87 Div90 pllx_p_ck = vcox_ck / 90 89 Div92 pllx_p_ck = vcox_ck / 92 91 Div94 pllx_p_ck = vcox_ck / 94 93 Div96 pllx_p_ck = vcox_ck / 96 95 Div98 pllx_p_ck = vcox_ck / 98 97 Div100 pllx_p_ck = vcox_ck / 100 99 Div102 pllx_p_ck = vcox_ck / 102 101 Div104 pllx_p_ck = vcox_ck / 104 103 Div106 pllx_p_ck = vcox_ck / 106 105 Div108 pllx_p_ck = vcox_ck / 108 107 Div110 pllx_p_ck = vcox_ck / 110 109 Div112 pllx_p_ck = vcox_ck / 112 111 Div114 pllx_p_ck = vcox_ck / 114 113 Div116 pllx_p_ck = vcox_ck / 116 115 Div118 pllx_p_ck = vcox_ck / 118 117 Div120 pllx_p_ck = vcox_ck / 120 119 Div122 pllx_p_ck = vcox_ck / 122 121 Div124 pllx_p_ck = vcox_ck / 124 123 Div126 pllx_p_ck = vcox_ck / 126 125 Div128 pllx_p_ck = vcox_ck / 128 127 PLL1Q PLL1 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll1_q_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 16 7 read-write PLL1Q Div1 pllx_q_ck = vcox_ck 0 Div2 pllx_q_ck = vcox_ck / 2 1 Div4 pllx_q_ck = vcox_ck / 4 3 Div6 pllx_q_ck = vcox_ck / 6 5 Div8 pllx_q_ck = vcox_ck / 8 7 Div10 pllx_q_ck = vcox_ck / 10 9 Div12 pllx_q_ck = vcox_ck / 12 11 Div14 pllx_q_ck = vcox_ck / 14 13 Div16 pllx_q_ck = vcox_ck / 16 15 Div18 pllx_q_ck = vcox_ck / 18 17 Div20 pllx_q_ck = vcox_ck / 20 19 Div22 pllx_q_ck = vcox_ck / 22 21 Div24 pllx_q_ck = vcox_ck / 24 23 Div26 pllx_q_ck = vcox_ck / 26 25 Div28 pllx_q_ck = vcox_ck / 28 27 Div30 pllx_q_ck = vcox_ck / 30 29 Div32 pllx_q_ck = vcox_ck / 32 31 Div34 pllx_q_ck = vcox_ck / 34 33 Div36 pllx_q_ck = vcox_ck / 36 35 Div38 pllx_q_ck = vcox_ck / 38 37 Div40 pllx_q_ck = vcox_ck / 40 39 Div42 pllx_q_ck = vcox_ck / 42 41 Div44 pllx_q_ck = vcox_ck / 44 43 Div46 pllx_q_ck = vcox_ck / 46 45 Div48 pllx_q_ck = vcox_ck / 48 47 Div50 pllx_q_ck = vcox_ck / 50 49 Div52 pllx_q_ck = vcox_ck / 52 51 Div54 pllx_q_ck = vcox_ck / 54 53 Div56 pllx_q_ck = vcox_ck / 56 55 Div58 pllx_q_ck = vcox_ck / 58 57 Div60 pllx_q_ck = vcox_ck / 60 59 Div62 pllx_q_ck = vcox_ck / 62 61 Div64 pllx_q_ck = vcox_ck / 64 63 Div66 pllx_q_ck = vcox_ck / 66 65 Div68 pllx_q_ck = vcox_ck / 68 67 Div70 pllx_q_ck = vcox_ck / 70 69 Div72 pllx_q_ck = vcox_ck / 72 71 Div74 pllx_q_ck = vcox_ck / 74 73 Div76 pllx_q_ck = vcox_ck / 76 75 Div78 pllx_q_ck = vcox_ck / 78 77 Div80 pllx_q_ck = vcox_ck / 80 79 Div82 pllx_q_ck = vcox_ck / 82 81 Div84 pllx_q_ck = vcox_ck / 84 83 Div86 pllx_q_ck = vcox_ck / 86 85 Div88 pllx_q_ck = vcox_ck / 88 87 Div90 pllx_q_ck = vcox_ck / 90 89 Div92 pllx_q_ck = vcox_ck / 92 91 Div94 pllx_q_ck = vcox_ck / 94 93 Div96 pllx_q_ck = vcox_ck / 96 95 Div98 pllx_q_ck = vcox_ck / 98 97 Div100 pllx_q_ck = vcox_ck / 100 99 Div102 pllx_q_ck = vcox_ck / 102 101 Div104 pllx_q_ck = vcox_ck / 104 103 Div106 pllx_q_ck = vcox_ck / 106 105 Div108 pllx_q_ck = vcox_ck / 108 107 Div110 pllx_q_ck = vcox_ck / 110 109 Div112 pllx_q_ck = vcox_ck / 112 111 Div114 pllx_q_ck = vcox_ck / 114 113 Div116 pllx_q_ck = vcox_ck / 116 115 Div118 pllx_q_ck = vcox_ck / 118 117 Div120 pllx_q_ck = vcox_ck / 120 119 Div122 pllx_q_ck = vcox_ck / 122 121 Div124 pllx_q_ck = vcox_ck / 124 123 Div126 pllx_q_ck = vcox_ck / 126 125 Div128 pllx_q_ck = vcox_ck / 128 127 PLL1R PLL1 DIVR division factor This bitfield is set and reset by software to control frequency of the pll1_r_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Only division by one and even division factors are allowed. ... 24 7 read-write PLL1R Div1 pllx_r_ck = vcox_ck 0 Div2 pllx_r_ck = vcox_ck / 2 1 Div4 pllx_r_ck = vcox_ck / 4 3 Div6 pllx_r_ck = vcox_ck / 6 5 Div8 pllx_r_ck = vcox_ck / 8 7 Div10 pllx_r_ck = vcox_ck / 10 9 Div12 pllx_r_ck = vcox_ck / 12 11 Div14 pllx_r_ck = vcox_ck / 14 13 Div16 pllx_r_ck = vcox_ck / 16 15 Div18 pllx_r_ck = vcox_ck / 18 17 Div20 pllx_r_ck = vcox_ck / 20 19 Div22 pllx_r_ck = vcox_ck / 22 21 Div24 pllx_r_ck = vcox_ck / 24 23 Div26 pllx_r_ck = vcox_ck / 26 25 Div28 pllx_r_ck = vcox_ck / 28 27 Div30 pllx_r_ck = vcox_ck / 30 29 Div32 pllx_r_ck = vcox_ck / 32 31 Div34 pllx_r_ck = vcox_ck / 34 33 Div36 pllx_r_ck = vcox_ck / 36 35 Div38 pllx_r_ck = vcox_ck / 38 37 Div40 pllx_r_ck = vcox_ck / 40 39 Div42 pllx_r_ck = vcox_ck / 42 41 Div44 pllx_r_ck = vcox_ck / 44 43 Div46 pllx_r_ck = vcox_ck / 46 45 Div48 pllx_r_ck = vcox_ck / 48 47 Div50 pllx_r_ck = vcox_ck / 50 49 Div52 pllx_r_ck = vcox_ck / 52 51 Div54 pllx_r_ck = vcox_ck / 54 53 Div56 pllx_r_ck = vcox_ck / 56 55 Div58 pllx_r_ck = vcox_ck / 58 57 Div60 pllx_r_ck = vcox_ck / 60 59 Div62 pllx_r_ck = vcox_ck / 62 61 Div64 pllx_r_ck = vcox_ck / 64 63 Div66 pllx_r_ck = vcox_ck / 66 65 Div68 pllx_r_ck = vcox_ck / 68 67 Div70 pllx_r_ck = vcox_ck / 70 69 Div72 pllx_r_ck = vcox_ck / 72 71 Div74 pllx_r_ck = vcox_ck / 74 73 Div76 pllx_r_ck = vcox_ck / 76 75 Div78 pllx_r_ck = vcox_ck / 78 77 Div80 pllx_r_ck = vcox_ck / 80 79 Div82 pllx_r_ck = vcox_ck / 82 81 Div84 pllx_r_ck = vcox_ck / 84 83 Div86 pllx_r_ck = vcox_ck / 86 85 Div88 pllx_r_ck = vcox_ck / 88 87 Div90 pllx_r_ck = vcox_ck / 90 89 Div92 pllx_r_ck = vcox_ck / 92 91 Div94 pllx_r_ck = vcox_ck / 94 93 Div96 pllx_r_ck = vcox_ck / 96 95 Div98 pllx_r_ck = vcox_ck / 98 97 Div100 pllx_r_ck = vcox_ck / 100 99 Div102 pllx_r_ck = vcox_ck / 102 101 Div104 pllx_r_ck = vcox_ck / 104 103 Div106 pllx_r_ck = vcox_ck / 106 105 Div108 pllx_r_ck = vcox_ck / 108 107 Div110 pllx_r_ck = vcox_ck / 110 109 Div112 pllx_r_ck = vcox_ck / 112 111 Div114 pllx_r_ck = vcox_ck / 114 113 Div116 pllx_r_ck = vcox_ck / 116 115 Div118 pllx_r_ck = vcox_ck / 118 117 Div120 pllx_r_ck = vcox_ck / 120 119 Div122 pllx_r_ck = vcox_ck / 122 121 Div124 pllx_r_ck = vcox_ck / 124 123 Div126 pllx_r_ck = vcox_ck / 126 125 Div128 pllx_r_ck = vcox_ck / 128 127 PLL1FRACR PLL1FRACR RCC PLL1 fractional divider register 0x38 0x20 0x00000000 0xFFFFFFFF PLL1FRACN Fractional part of the multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed asï¿½follows: Set PLL1FRACEN = 0. Write the new fractional value into PLL1FRACN. Set PLL1FRACEN = 1. 3 13 read-write 0 511 PLL2DIVR PLL2DIVR RCC PLL2 dividers configuration register 0x3C 0x20 0x01010280 0xFFFFFFFF PLL2N Multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0). ... ... Others: reserved VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded in PLL2FRACN, with: PLL2N between 4 and 512 input frequency Fref2_ck between 1MHz and 16MHz 0 9 read-write 3 511 PLL2P PLL2 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll2_p_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 9 7 read-write PLL2P Div1 pllx_p_ck = vcox_ck 0 Div2 pllx_p_ck = vcox_ck / 2 1 Div4 pllx_p_ck = vcox_ck / 4 3 Div6 pllx_p_ck = vcox_ck / 6 5 Div8 pllx_p_ck = vcox_ck / 8 7 Div10 pllx_p_ck = vcox_ck / 10 9 Div12 pllx_p_ck = vcox_ck / 12 11 Div14 pllx_p_ck = vcox_ck / 14 13 Div16 pllx_p_ck = vcox_ck / 16 15 Div18 pllx_p_ck = vcox_ck / 18 17 Div20 pllx_p_ck = vcox_ck / 20 19 Div22 pllx_p_ck = vcox_ck / 22 21 Div24 pllx_p_ck = vcox_ck / 24 23 Div26 pllx_p_ck = vcox_ck / 26 25 Div28 pllx_p_ck = vcox_ck / 28 27 Div30 pllx_p_ck = vcox_ck / 30 29 Div32 pllx_p_ck = vcox_ck / 32 31 Div34 pllx_p_ck = vcox_ck / 34 33 Div36 pllx_p_ck = vcox_ck / 36 35 Div38 pllx_p_ck = vcox_ck / 38 37 Div40 pllx_p_ck = vcox_ck / 40 39 Div42 pllx_p_ck = vcox_ck / 42 41 Div44 pllx_p_ck = vcox_ck / 44 43 Div46 pllx_p_ck = vcox_ck / 46 45 Div48 pllx_p_ck = vcox_ck / 48 47 Div50 pllx_p_ck = vcox_ck / 50 49 Div52 pllx_p_ck = vcox_ck / 52 51 Div54 pllx_p_ck = vcox_ck / 54 53 Div56 pllx_p_ck = vcox_ck / 56 55 Div58 pllx_p_ck = vcox_ck / 58 57 Div60 pllx_p_ck = vcox_ck / 60 59 Div62 pllx_p_ck = vcox_ck / 62 61 Div64 pllx_p_ck = vcox_ck / 64 63 Div66 pllx_p_ck = vcox_ck / 66 65 Div68 pllx_p_ck = vcox_ck / 68 67 Div70 pllx_p_ck = vcox_ck / 70 69 Div72 pllx_p_ck = vcox_ck / 72 71 Div74 pllx_p_ck = vcox_ck / 74 73 Div76 pllx_p_ck = vcox_ck / 76 75 Div78 pllx_p_ck = vcox_ck / 78 77 Div80 pllx_p_ck = vcox_ck / 80 79 Div82 pllx_p_ck = vcox_ck / 82 81 Div84 pllx_p_ck = vcox_ck / 84 83 Div86 pllx_p_ck = vcox_ck / 86 85 Div88 pllx_p_ck = vcox_ck / 88 87 Div90 pllx_p_ck = vcox_ck / 90 89 Div92 pllx_p_ck = vcox_ck / 92 91 Div94 pllx_p_ck = vcox_ck / 94 93 Div96 pllx_p_ck = vcox_ck / 96 95 Div98 pllx_p_ck = vcox_ck / 98 97 Div100 pllx_p_ck = vcox_ck / 100 99 Div102 pllx_p_ck = vcox_ck / 102 101 Div104 pllx_p_ck = vcox_ck / 104 103 Div106 pllx_p_ck = vcox_ck / 106 105 Div108 pllx_p_ck = vcox_ck / 108 107 Div110 pllx_p_ck = vcox_ck / 110 109 Div112 pllx_p_ck = vcox_ck / 112 111 Div114 pllx_p_ck = vcox_ck / 114 113 Div116 pllx_p_ck = vcox_ck / 116 115 Div118 pllx_p_ck = vcox_ck / 118 117 Div120 pllx_p_ck = vcox_ck / 120 119 Div122 pllx_p_ck = vcox_ck / 122 121 Div124 pllx_p_ck = vcox_ck / 124 123 Div126 pllx_p_ck = vcox_ck / 126 125 Div128 pllx_p_ck = vcox_ck / 128 127 PLL2Q PLL2 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll2_q_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 16 7 read-write PLL2Q Div1 pllx_q_ck = vcox_ck 0 Div2 pllx_q_ck = vcox_ck / 2 1 Div4 pllx_q_ck = vcox_ck / 4 3 Div6 pllx_q_ck = vcox_ck / 6 5 Div8 pllx_q_ck = vcox_ck / 8 7 Div10 pllx_q_ck = vcox_ck / 10 9 Div12 pllx_q_ck = vcox_ck / 12 11 Div14 pllx_q_ck = vcox_ck / 14 13 Div16 pllx_q_ck = vcox_ck / 16 15 Div18 pllx_q_ck = vcox_ck / 18 17 Div20 pllx_q_ck = vcox_ck / 20 19 Div22 pllx_q_ck = vcox_ck / 22 21 Div24 pllx_q_ck = vcox_ck / 24 23 Div26 pllx_q_ck = vcox_ck / 26 25 Div28 pllx_q_ck = vcox_ck / 28 27 Div30 pllx_q_ck = vcox_ck / 30 29 Div32 pllx_q_ck = vcox_ck / 32 31 Div34 pllx_q_ck = vcox_ck / 34 33 Div36 pllx_q_ck = vcox_ck / 36 35 Div38 pllx_q_ck = vcox_ck / 38 37 Div40 pllx_q_ck = vcox_ck / 40 39 Div42 pllx_q_ck = vcox_ck / 42 41 Div44 pllx_q_ck = vcox_ck / 44 43 Div46 pllx_q_ck = vcox_ck / 46 45 Div48 pllx_q_ck = vcox_ck / 48 47 Div50 pllx_q_ck = vcox_ck / 50 49 Div52 pllx_q_ck = vcox_ck / 52 51 Div54 pllx_q_ck = vcox_ck / 54 53 Div56 pllx_q_ck = vcox_ck / 56 55 Div58 pllx_q_ck = vcox_ck / 58 57 Div60 pllx_q_ck = vcox_ck / 60 59 Div62 pllx_q_ck = vcox_ck / 62 61 Div64 pllx_q_ck = vcox_ck / 64 63 Div66 pllx_q_ck = vcox_ck / 66 65 Div68 pllx_q_ck = vcox_ck / 68 67 Div70 pllx_q_ck = vcox_ck / 70 69 Div72 pllx_q_ck = vcox_ck / 72 71 Div74 pllx_q_ck = vcox_ck / 74 73 Div76 pllx_q_ck = vcox_ck / 76 75 Div78 pllx_q_ck = vcox_ck / 78 77 Div80 pllx_q_ck = vcox_ck / 80 79 Div82 pllx_q_ck = vcox_ck / 82 81 Div84 pllx_q_ck = vcox_ck / 84 83 Div86 pllx_q_ck = vcox_ck / 86 85 Div88 pllx_q_ck = vcox_ck / 88 87 Div90 pllx_q_ck = vcox_ck / 90 89 Div92 pllx_q_ck = vcox_ck / 92 91 Div94 pllx_q_ck = vcox_ck / 94 93 Div96 pllx_q_ck = vcox_ck / 96 95 Div98 pllx_q_ck = vcox_ck / 98 97 Div100 pllx_q_ck = vcox_ck / 100 99 Div102 pllx_q_ck = vcox_ck / 102 101 Div104 pllx_q_ck = vcox_ck / 104 103 Div106 pllx_q_ck = vcox_ck / 106 105 Div108 pllx_q_ck = vcox_ck / 108 107 Div110 pllx_q_ck = vcox_ck / 110 109 Div112 pllx_q_ck = vcox_ck / 112 111 Div114 pllx_q_ck = vcox_ck / 114 113 Div116 pllx_q_ck = vcox_ck / 116 115 Div118 pllx_q_ck = vcox_ck / 118 117 Div120 pllx_q_ck = vcox_ck / 120 119 Div122 pllx_q_ck = vcox_ck / 122 121 Div124 pllx_q_ck = vcox_ck / 124 123 Div126 pllx_q_ck = vcox_ck / 126 125 Div128 pllx_q_ck = vcox_ck / 128 127 PLL2R PLL2 DIVR division factor This bitfield is set and reset by software to control the frequency of the pll2_r_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 24 7 read-write PLL2R Div1 pllx_r_ck = vcox_ck 0 Div2 pllx_r_ck = vcox_ck / 2 1 Div4 pllx_r_ck = vcox_ck / 4 3 Div6 pllx_r_ck = vcox_ck / 6 5 Div8 pllx_r_ck = vcox_ck / 8 7 Div10 pllx_r_ck = vcox_ck / 10 9 Div12 pllx_r_ck = vcox_ck / 12 11 Div14 pllx_r_ck = vcox_ck / 14 13 Div16 pllx_r_ck = vcox_ck / 16 15 Div18 pllx_r_ck = vcox_ck / 18 17 Div20 pllx_r_ck = vcox_ck / 20 19 Div22 pllx_r_ck = vcox_ck / 22 21 Div24 pllx_r_ck = vcox_ck / 24 23 Div26 pllx_r_ck = vcox_ck / 26 25 Div28 pllx_r_ck = vcox_ck / 28 27 Div30 pllx_r_ck = vcox_ck / 30 29 Div32 pllx_r_ck = vcox_ck / 32 31 Div34 pllx_r_ck = vcox_ck / 34 33 Div36 pllx_r_ck = vcox_ck / 36 35 Div38 pllx_r_ck = vcox_ck / 38 37 Div40 pllx_r_ck = vcox_ck / 40 39 Div42 pllx_r_ck = vcox_ck / 42 41 Div44 pllx_r_ck = vcox_ck / 44 43 Div46 pllx_r_ck = vcox_ck / 46 45 Div48 pllx_r_ck = vcox_ck / 48 47 Div50 pllx_r_ck = vcox_ck / 50 49 Div52 pllx_r_ck = vcox_ck / 52 51 Div54 pllx_r_ck = vcox_ck / 54 53 Div56 pllx_r_ck = vcox_ck / 56 55 Div58 pllx_r_ck = vcox_ck / 58 57 Div60 pllx_r_ck = vcox_ck / 60 59 Div62 pllx_r_ck = vcox_ck / 62 61 Div64 pllx_r_ck = vcox_ck / 64 63 Div66 pllx_r_ck = vcox_ck / 66 65 Div68 pllx_r_ck = vcox_ck / 68 67 Div70 pllx_r_ck = vcox_ck / 70 69 Div72 pllx_r_ck = vcox_ck / 72 71 Div74 pllx_r_ck = vcox_ck / 74 73 Div76 pllx_r_ck = vcox_ck / 76 75 Div78 pllx_r_ck = vcox_ck / 78 77 Div80 pllx_r_ck = vcox_ck / 80 79 Div82 pllx_r_ck = vcox_ck / 82 81 Div84 pllx_r_ck = vcox_ck / 84 83 Div86 pllx_r_ck = vcox_ck / 86 85 Div88 pllx_r_ck = vcox_ck / 88 87 Div90 pllx_r_ck = vcox_ck / 90 89 Div92 pllx_r_ck = vcox_ck / 92 91 Div94 pllx_r_ck = vcox_ck / 94 93 Div96 pllx_r_ck = vcox_ck / 96 95 Div98 pllx_r_ck = vcox_ck / 98 97 Div100 pllx_r_ck = vcox_ck / 100 99 Div102 pllx_r_ck = vcox_ck / 102 101 Div104 pllx_r_ck = vcox_ck / 104 103 Div106 pllx_r_ck = vcox_ck / 106 105 Div108 pllx_r_ck = vcox_ck / 108 107 Div110 pllx_r_ck = vcox_ck / 110 109 Div112 pllx_r_ck = vcox_ck / 112 111 Div114 pllx_r_ck = vcox_ck / 114 113 Div116 pllx_r_ck = vcox_ck / 116 115 Div118 pllx_r_ck = vcox_ck / 118 117 Div120 pllx_r_ck = vcox_ck / 120 119 Div122 pllx_r_ck = vcox_ck / 122 121 Div124 pllx_r_ck = vcox_ck / 124 123 Div126 pllx_r_ck = vcox_ck / 126 125 Div128 pllx_r_ck = vcox_ck / 128 127 PLL2FRACR PLL2FRACR RCC PLL2 fractional divider register 0x40 0x20 0x00000000 0xFFFFFFFF PLL2FRACN Fractional part of the multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with PLL2N must be between 4 and 512. PLL2FRACN can be between 0 and 213 - 1. The input frequency Fref2_ck must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL2FRACEN to 0. Write the new fractional value into PLL2FRACN. Set the bit PLL2FRACEN to 1. 3 13 read-write 0 511 PLL3DIVR PLL3DIVR RCC PLL3 dividers configuration register 0x44 0x20 0x01010280 0xFFFFFFFF PLL3N Multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0). ... ... Others: reserved VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded in PLL3FRACN, with: PLL3N between 4 and 512 input frequency Fref3_ck between 4 and 16MHz 0 9 read-write 3 511 PLL3P PLL3 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll3_p_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ... 9 7 read-write PLL3P Div1 pllx_p_ck = vcox_ck 0 Div2 pllx_p_ck = vcox_ck / 2 1 Div4 pllx_p_ck = vcox_ck / 4 3 Div6 pllx_p_ck = vcox_ck / 6 5 Div8 pllx_p_ck = vcox_ck / 8 7 Div10 pllx_p_ck = vcox_ck / 10 9 Div12 pllx_p_ck = vcox_ck / 12 11 Div14 pllx_p_ck = vcox_ck / 14 13 Div16 pllx_p_ck = vcox_ck / 16 15 Div18 pllx_p_ck = vcox_ck / 18 17 Div20 pllx_p_ck = vcox_ck / 20 19 Div22 pllx_p_ck = vcox_ck / 22 21 Div24 pllx_p_ck = vcox_ck / 24 23 Div26 pllx_p_ck = vcox_ck / 26 25 Div28 pllx_p_ck = vcox_ck / 28 27 Div30 pllx_p_ck = vcox_ck / 30 29 Div32 pllx_p_ck = vcox_ck / 32 31 Div34 pllx_p_ck = vcox_ck / 34 33 Div36 pllx_p_ck = vcox_ck / 36 35 Div38 pllx_p_ck = vcox_ck / 38 37 Div40 pllx_p_ck = vcox_ck / 40 39 Div42 pllx_p_ck = vcox_ck / 42 41 Div44 pllx_p_ck = vcox_ck / 44 43 Div46 pllx_p_ck = vcox_ck / 46 45 Div48 pllx_p_ck = vcox_ck / 48 47 Div50 pllx_p_ck = vcox_ck / 50 49 Div52 pllx_p_ck = vcox_ck / 52 51 Div54 pllx_p_ck = vcox_ck / 54 53 Div56 pllx_p_ck = vcox_ck / 56 55 Div58 pllx_p_ck = vcox_ck / 58 57 Div60 pllx_p_ck = vcox_ck / 60 59 Div62 pllx_p_ck = vcox_ck / 62 61 Div64 pllx_p_ck = vcox_ck / 64 63 Div66 pllx_p_ck = vcox_ck / 66 65 Div68 pllx_p_ck = vcox_ck / 68 67 Div70 pllx_p_ck = vcox_ck / 70 69 Div72 pllx_p_ck = vcox_ck / 72 71 Div74 pllx_p_ck = vcox_ck / 74 73 Div76 pllx_p_ck = vcox_ck / 76 75 Div78 pllx_p_ck = vcox_ck / 78 77 Div80 pllx_p_ck = vcox_ck / 80 79 Div82 pllx_p_ck = vcox_ck / 82 81 Div84 pllx_p_ck = vcox_ck / 84 83 Div86 pllx_p_ck = vcox_ck / 86 85 Div88 pllx_p_ck = vcox_ck / 88 87 Div90 pllx_p_ck = vcox_ck / 90 89 Div92 pllx_p_ck = vcox_ck / 92 91 Div94 pllx_p_ck = vcox_ck / 94 93 Div96 pllx_p_ck = vcox_ck / 96 95 Div98 pllx_p_ck = vcox_ck / 98 97 Div100 pllx_p_ck = vcox_ck / 100 99 Div102 pllx_p_ck = vcox_ck / 102 101 Div104 pllx_p_ck = vcox_ck / 104 103 Div106 pllx_p_ck = vcox_ck / 106 105 Div108 pllx_p_ck = vcox_ck / 108 107 Div110 pllx_p_ck = vcox_ck / 110 109 Div112 pllx_p_ck = vcox_ck / 112 111 Div114 pllx_p_ck = vcox_ck / 114 113 Div116 pllx_p_ck = vcox_ck / 116 115 Div118 pllx_p_ck = vcox_ck / 118 117 Div120 pllx_p_ck = vcox_ck / 120 119 Div122 pllx_p_ck = vcox_ck / 122 121 Div124 pllx_p_ck = vcox_ck / 124 123 Div126 pllx_p_ck = vcox_ck / 126 125 Div128 pllx_p_ck = vcox_ck / 128 127 PLL3Q PLL3 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll3_q_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ... 16 7 read-write PLL3Q Div1 pllx_q_ck = vcox_ck 0 Div2 pllx_q_ck = vcox_ck / 2 1 Div4 pllx_q_ck = vcox_ck / 4 3 Div6 pllx_q_ck = vcox_ck / 6 5 Div8 pllx_q_ck = vcox_ck / 8 7 Div10 pllx_q_ck = vcox_ck / 10 9 Div12 pllx_q_ck = vcox_ck / 12 11 Div14 pllx_q_ck = vcox_ck / 14 13 Div16 pllx_q_ck = vcox_ck / 16 15 Div18 pllx_q_ck = vcox_ck / 18 17 Div20 pllx_q_ck = vcox_ck / 20 19 Div22 pllx_q_ck = vcox_ck / 22 21 Div24 pllx_q_ck = vcox_ck / 24 23 Div26 pllx_q_ck = vcox_ck / 26 25 Div28 pllx_q_ck = vcox_ck / 28 27 Div30 pllx_q_ck = vcox_ck / 30 29 Div32 pllx_q_ck = vcox_ck / 32 31 Div34 pllx_q_ck = vcox_ck / 34 33 Div36 pllx_q_ck = vcox_ck / 36 35 Div38 pllx_q_ck = vcox_ck / 38 37 Div40 pllx_q_ck = vcox_ck / 40 39 Div42 pllx_q_ck = vcox_ck / 42 41 Div44 pllx_q_ck = vcox_ck / 44 43 Div46 pllx_q_ck = vcox_ck / 46 45 Div48 pllx_q_ck = vcox_ck / 48 47 Div50 pllx_q_ck = vcox_ck / 50 49 Div52 pllx_q_ck = vcox_ck / 52 51 Div54 pllx_q_ck = vcox_ck / 54 53 Div56 pllx_q_ck = vcox_ck / 56 55 Div58 pllx_q_ck = vcox_ck / 58 57 Div60 pllx_q_ck = vcox_ck / 60 59 Div62 pllx_q_ck = vcox_ck / 62 61 Div64 pllx_q_ck = vcox_ck / 64 63 Div66 pllx_q_ck = vcox_ck / 66 65 Div68 pllx_q_ck = vcox_ck / 68 67 Div70 pllx_q_ck = vcox_ck / 70 69 Div72 pllx_q_ck = vcox_ck / 72 71 Div74 pllx_q_ck = vcox_ck / 74 73 Div76 pllx_q_ck = vcox_ck / 76 75 Div78 pllx_q_ck = vcox_ck / 78 77 Div80 pllx_q_ck = vcox_ck / 80 79 Div82 pllx_q_ck = vcox_ck / 82 81 Div84 pllx_q_ck = vcox_ck / 84 83 Div86 pllx_q_ck = vcox_ck / 86 85 Div88 pllx_q_ck = vcox_ck / 88 87 Div90 pllx_q_ck = vcox_ck / 90 89 Div92 pllx_q_ck = vcox_ck / 92 91 Div94 pllx_q_ck = vcox_ck / 94 93 Div96 pllx_q_ck = vcox_ck / 96 95 Div98 pllx_q_ck = vcox_ck / 98 97 Div100 pllx_q_ck = vcox_ck / 100 99 Div102 pllx_q_ck = vcox_ck / 102 101 Div104 pllx_q_ck = vcox_ck / 104 103 Div106 pllx_q_ck = vcox_ck / 106 105 Div108 pllx_q_ck = vcox_ck / 108 107 Div110 pllx_q_ck = vcox_ck / 110 109 Div112 pllx_q_ck = vcox_ck / 112 111 Div114 pllx_q_ck = vcox_ck / 114 113 Div116 pllx_q_ck = vcox_ck / 116 115 Div118 pllx_q_ck = vcox_ck / 118 117 Div120 pllx_q_ck = vcox_ck / 120 119 Div122 pllx_q_ck = vcox_ck / 122 121 Div124 pllx_q_ck = vcox_ck / 124 123 Div126 pllx_q_ck = vcox_ck / 126 125 Div128 pllx_q_ck = vcox_ck / 128 127 PLL3R PLL3 DIVR division factor This bitfield is set and reset by software to control the frequency of the pll3_r_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ... 24 7 read-write PLL3R Div1 pllx_r_ck = vcox_ck 0 Div2 pllx_r_ck = vcox_ck / 2 1 Div4 pllx_r_ck = vcox_ck / 4 3 Div6 pllx_r_ck = vcox_ck / 6 5 Div8 pllx_r_ck = vcox_ck / 8 7 Div10 pllx_r_ck = vcox_ck / 10 9 Div12 pllx_r_ck = vcox_ck / 12 11 Div14 pllx_r_ck = vcox_ck / 14 13 Div16 pllx_r_ck = vcox_ck / 16 15 Div18 pllx_r_ck = vcox_ck / 18 17 Div20 pllx_r_ck = vcox_ck / 20 19 Div22 pllx_r_ck = vcox_ck / 22 21 Div24 pllx_r_ck = vcox_ck / 24 23 Div26 pllx_r_ck = vcox_ck / 26 25 Div28 pllx_r_ck = vcox_ck / 28 27 Div30 pllx_r_ck = vcox_ck / 30 29 Div32 pllx_r_ck = vcox_ck / 32 31 Div34 pllx_r_ck = vcox_ck / 34 33 Div36 pllx_r_ck = vcox_ck / 36 35 Div38 pllx_r_ck = vcox_ck / 38 37 Div40 pllx_r_ck = vcox_ck / 40 39 Div42 pllx_r_ck = vcox_ck / 42 41 Div44 pllx_r_ck = vcox_ck / 44 43 Div46 pllx_r_ck = vcox_ck / 46 45 Div48 pllx_r_ck = vcox_ck / 48 47 Div50 pllx_r_ck = vcox_ck / 50 49 Div52 pllx_r_ck = vcox_ck / 52 51 Div54 pllx_r_ck = vcox_ck / 54 53 Div56 pllx_r_ck = vcox_ck / 56 55 Div58 pllx_r_ck = vcox_ck / 58 57 Div60 pllx_r_ck = vcox_ck / 60 59 Div62 pllx_r_ck = vcox_ck / 62 61 Div64 pllx_r_ck = vcox_ck / 64 63 Div66 pllx_r_ck = vcox_ck / 66 65 Div68 pllx_r_ck = vcox_ck / 68 67 Div70 pllx_r_ck = vcox_ck / 70 69 Div72 pllx_r_ck = vcox_ck / 72 71 Div74 pllx_r_ck = vcox_ck / 74 73 Div76 pllx_r_ck = vcox_ck / 76 75 Div78 pllx_r_ck = vcox_ck / 78 77 Div80 pllx_r_ck = vcox_ck / 80 79 Div82 pllx_r_ck = vcox_ck / 82 81 Div84 pllx_r_ck = vcox_ck / 84 83 Div86 pllx_r_ck = vcox_ck / 86 85 Div88 pllx_r_ck = vcox_ck / 88 87 Div90 pllx_r_ck = vcox_ck / 90 89 Div92 pllx_r_ck = vcox_ck / 92 91 Div94 pllx_r_ck = vcox_ck / 94 93 Div96 pllx_r_ck = vcox_ck / 96 95 Div98 pllx_r_ck = vcox_ck / 98 97 Div100 pllx_r_ck = vcox_ck / 100 99 Div102 pllx_r_ck = vcox_ck / 102 101 Div104 pllx_r_ck = vcox_ck / 104 103 Div106 pllx_r_ck = vcox_ck / 106 105 Div108 pllx_r_ck = vcox_ck / 108 107 Div110 pllx_r_ck = vcox_ck / 110 109 Div112 pllx_r_ck = vcox_ck / 112 111 Div114 pllx_r_ck = vcox_ck / 114 113 Div116 pllx_r_ck = vcox_ck / 116 115 Div118 pllx_r_ck = vcox_ck / 118 117 Div120 pllx_r_ck = vcox_ck / 120 119 Div122 pllx_r_ck = vcox_ck / 122 121 Div124 pllx_r_ck = vcox_ck / 124 123 Div126 pllx_r_ck = vcox_ck / 126 125 Div128 pllx_r_ck = vcox_ck / 128 127 PLL3FRACR PLL3FRACR RCC PLL3 fractional divider register 0x48 0x20 0x00000000 0xFFFFFFFF PLL3FRACN Fractional part of the multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with: PLL3N must be between 4 and 512. PLL3FRACN can be between 0 and 213 - 1. The input frequency Fref3_ck must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL3FRACEN to 0. Write the new fractional value into PLL3FRACN. Set the bit PLL3FRACEN to 1. 3 13 read-write 0 511 CIER CIER RCC clock interrupt enable register 0x50 0x20 0x00000000 0xFFFFFFFF LSIRDYIE LSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0 1 read-write LSIRDYIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 LSERDYIE LSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. 1 1 read-write MSISRDYIE MSIS ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization. 2 1 read-write HSIRDYIE HSI16 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. 3 1 read-write HSERDYIE HSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. 4 1 read-write HSI48RDYIE HSI48 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. 5 1 read-write PLL1RDYIE PLL ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL1 lock. 6 1 read-write PLL2RDYIE PLL2 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL2 lock. 7 1 read-write PLL3RDYIE PLL3 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL3 lock. 8 1 read-write MSIKRDYIE MSIK ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization. 11 1 read-write SHSIRDYIE SHSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization. 12 1 read-write CIFR CIFR RCC clock interrupt flag register 0x54 0x20 0x00000000 0xFFFFFFFF LSIRDYF LSI ready interrupt flag This bit is set by hardware when the LSI clock becomes stable and LSIRDYIE is set. It is cleared by software byï¿½setting the LSIRDYC bit. 0 1 read-only LSIRDYFR NotInterrupted No clock ready interrupt 0 Interrupted Clock ready interrupt 1 LSERDYF LSE ready interrupt flag This bit is set by hardware when the LSE clock becomes stable and LSERDYIE is set. It is cleared by software by setting the LSERDYC bit. 1 1 read-only MSISRDYF MSIS ready interrupt flag This bit is set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. Itï¿½is cleared by software by setting the MSISRDYC bit. 2 1 read-only HSIRDYF HSI16 ready interrupt flag This bit is set by hardware when the HSI16 clock becomes stable and HSIRDYIE = 1 inï¿½response to setting the HSION (see RCC_CR). When HSION = 0 but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. This bit is cleared by software by setting the HSIRDYC bit. 3 1 read-only HSERDYF HSE ready interrupt flag This bit is set by hardware when the HSE clock becomes stable and HSERDYIE is set. It is cleared by software by setting the HSERDYC bit. 4 1 read-only HSI48RDYF HSI48 ready interrupt flag This bit is set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. itï¿½is cleared by software by setting the HSI48RDYC bit. 5 1 read-only PLL1RDYF PLL1 ready interrupt flag This bit is set by hardware when the PLL1 locks and PLL1RDYIE is set. It is cleared by software by setting the PLL1RDYC bit. 6 1 read-only PLL2RDYF PLL2 ready interrupt flag This bit is set by hardware when the PLL2 locks and PLL2RDYIE is set. It is cleared by software by setting the PLL2RDYC bit. 7 1 read-only PLL3RDYF PLL3 ready interrupt flag This bit is set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software by setting the PLL3RDYC bit. 8 1 read-only CSSF Clock security system interrupt flag This bit is set by hardware when a failure is detected in the HSE oscillator. It is cleared by software by setting the CSSC bit. 10 1 read-only MSIKRDYF MSIK ready interrupt flag This bit is set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. It is cleared by software by setting the MSIKRDYC bit. 11 1 read-only SHSIRDYF SHSI ready interrupt flag This bit is set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. It is cleared by software by setting the SHSIRDYC bit. 12 1 read-only CICR CICR RCC clock interrupt clear register 0x58 0x20 0x00000000 0xFFFFFFFF LSIRDYC LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect. 0 1 write-only LSIRDYCW Clear Clear flag 1 LSERDYC LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect. 1 1 write-only MSISRDYC MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect. 2 1 write-only HSIRDYC HSI16 ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect. 3 1 write-only HSERDYC HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect. 4 1 write-only HSI48RDYC HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect. 5 1 write-only PLL1RDYC PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. 6 1 write-only PLL2RDYC PLL2 ready interrupt clear Writing this bit to 1 clears the PLL2RDYF flag. Writing 0 has no effect. 7 1 write-only PLL3RDYC PLL3 ready interrupt clear Writing this bit to 1 clears the PLL3RDYF flag. Writing 0 has no effect. 8 1 write-only CSSC Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect. 10 1 write-only MSIKRDYC MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect. 11 1 write-only SHSIRDYC SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect. 12 1 write-only AHB1RSTR AHB1RSTR RCC AHB1 peripheral reset register 0x60 0x20 0x00000000 0xFFFFFFFF GPDMA1RST GPDMA1 reset This bit is set and cleared by software. 0 1 read-write GPDMA1RST NoEffect No effect 0 Reset Reset peripheral 1 CORDICRST CORDIC reset This bit is set and cleared by software. 1 1 read-write FMACRST FMAC reset This bit is set and cleared by software. 2 1 read-write MDF1RST MDF1 reset This bit is set and cleared by software. 3 1 read-write CRCRST CRC reset This bit is set and cleared by software. 12 1 read-write JPEGRST JPEG reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write TSCRST TSC reset This bit is set and cleared by software. 16 1 read-write RAMCFGRST RAMCFG reset This bit is set and cleared by software. 17 1 read-write DMA2DRST DMA2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 18 1 read-write GFXMMURST GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write GPU2DRST GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write AHB2RSTR1 AHB2RSTR1 RCC AHB2 peripheral reset register 1 0x64 0x20 0x00000000 0xFFFFFFFF GPIOARST I/O port A reset This bit is set and cleared by software. 0 1 read-write GPIOARST NoEffect No effect 0 Reset Reset peripheral 1 GPIOBRST I/O port B reset This bit is set and cleared by software. 1 1 read-write GPIOCRST I/O port C reset This bit is set and cleared by software. 2 1 read-write GPIODRST I/O port D reset This bit is set and cleared by software. 3 1 read-write GPIOERST I/O port E reset This bit is set and cleared by software. 4 1 read-write GPIOFRST I/O port F reset This bit is set and cleared by software. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value. 5 1 read-write GPIOGRST I/O port G reset This bit is set and cleared by software. 6 1 read-write GPIOHRST I/O port H reset This bit is set and cleared by software. 7 1 read-write GPIOIRST I/O port I reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write GPIOJRST I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 9 1 read-write ADC12RST ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 inï¿½STM32U59x/5Ax/5Fx/5Gx. 10 1 read-write DCMI_PSSIRST DCMI and PSSI reset This bit is set and cleared by software. 12 1 read-write OTGRST OTG_FS or OTG_HS reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 14 1 read-write AESRST AES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 16 1 read-write HASHRST HASH reset This bit is set and cleared by software. 17 1 read-write RNGRST RNG reset This bit is set and cleared by software. 18 1 read-write PKARST PKA reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write SAESRST SAES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write OCTOSPIMRST OCTOSPIM reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 21 1 read-write OTFDEC1RST OTFDEC1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write OTFDEC2RST OTFDEC2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write SDMMC1RST SDMMC1 reset This bit is set and cleared by software. 27 1 read-write SDMMC2RST SDMMC2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 28 1 read-write AHB2RSTR2 AHB2RSTR2 RCC AHB2 peripheral reset register 2 0x68 0x20 0x00000000 0xFFFFFFFF FSMCRST Flexible memory controller reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 1 read-write FSMCRST NoEffect No effect 0 Reset Reset peripheral 1 OCTOSPI1RST OCTOSPI1 reset This bit is set and cleared by software. 4 1 read-write OCTOSPI2RST OCTOSPI2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write HSPI1RST HSPI1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 12 1 read-write AHB3RSTR AHB3RSTR RCC AHB3 peripheral reset register 0x6C 0x20 0x00000000 0xFFFFFFFF LPGPIO1RST LPGPIO1 reset This bit is set and cleared by software. 0 1 read-write LPGPIO1RST NoEffect No effect 0 Reset Reset peripheral 1 ADC4RST ADC4 reset This bit is set and cleared by software. 5 1 read-write DAC1RST DAC1 reset This bit is set and cleared by software. 6 1 read-write LPDMA1RST LPDMA1 reset This bit is set and cleared by software. 9 1 read-write ADF1RST ADF1 reset This bit is set and cleared by software. 10 1 read-write APB1RSTR1 APB1RSTR1 RCC APB1 peripheral reset register 1 0x74 0x20 0x00000000 0xFFFFFFFF TIM2RST TIM2 reset This bit is set and cleared by software. 0 1 read-write TIM2RST NoEffect No effect 0 Reset Reset peripheral 1 TIM3RST TIM3 reset This bit is set and cleared by software. 1 1 read-write TIM4RST TIM4 reset This bit is set and cleared by software. 2 1 read-write TIM5RST TIM5 reset This bit is set and cleared by software. 3 1 read-write TIM6RST TIM6 reset This bit is set and cleared by software. 4 1 read-write TIM7RST TIM7 reset This bit is set and cleared by software. 5 1 read-write SPI2RST SPI2 reset This bit is set and cleared by software. 14 1 read-write USART2RST USART2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 17 1 read-write USART3RST USART3 reset This bit is set and cleared by software. 18 1 read-write UART4RST UART4 reset This bit is set and cleared by software. 19 1 read-write UART5RST UART5 reset This bit is set and cleared by software. 20 1 read-write I2C1RST I2C1 reset This bit is set and cleared by software. 21 1 read-write I2C2RST I2C2 reset This bit is set and cleared by software. 22 1 read-write CRSRST CRS reset This bit is set and cleared by software. 24 1 read-write USART6RST USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write APB1RSTR2 APB1RSTR2 RCC APB1 peripheral reset register 2 0x78 0x20 0x00000000 0xFFFFFFFF I2C4RST I2C4 reset This bit is set and cleared by software 1 1 read-write I2C4RST NoEffect No effect 0 Reset Reset peripheral 1 LPTIM2RST LPTIM2 reset This bit is set and cleared by software. 5 1 read-write I2C5RST I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 6 1 read-write I2C6RST I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 7 1 read-write FDCAN1RST FDCAN1 reset This bit is set and cleared by software. 9 1 read-write UCPD1RST UCPD1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write APB2RSTR APB2RSTR RCC APB2 peripheral reset register 0x7C 0x20 0x00000000 0xFFFFFFFF TIM1RST TIM1 reset This bit is set and cleared by software. 11 1 read-write TIM1RST NoEffect No effect 0 Reset Reset peripheral 1 SPI1RST SPI1 reset This bit is set and cleared by software. 12 1 read-write TIM8RST TIM8 reset This bit is set and cleared by software. 13 1 read-write USART1RST USART1 reset This bit is set and cleared by software. 14 1 read-write TIM15RST TIM15 reset This bit is set and cleared by software. 16 1 read-write TIM16RST TIM16 reset This bit is set and cleared by software. 17 1 read-write TIM17RST TIM17 reset This bit is set and cleared by software. 18 1 read-write SAI1RST SAI1 reset This bit is set and cleared by software. 21 1 read-write SAI2RST SAI2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 22 1 read-write USBRST USB reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write GFXTIMRST GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write LTDCRST LTDC reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 26 1 read-write DSIRST DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 27 1 read-write APB3RSTR APB3RSTR RCC APB3 peripheral reset register 0x80 0x20 0x00000000 0xFFFFFFFF SYSCFGRST SYSCFG reset This bit is set and cleared by software. 1 1 read-write SYSCFGRST NoEffect No effect 0 Reset Reset peripheral 1 SPI3RST SPI3 reset This bit is set and cleared by software. 5 1 read-write LPUART1RST LPUART1 reset This bit is set and cleared by software. 6 1 read-write I2C3RST I2C3 reset This bit is set and cleared by software. 7 1 read-write LPTIM1RST LPTIM1 reset This bit is set and cleared by software. 11 1 read-write LPTIM3RST LPTIM3 reset This bit is set and cleared by software. 12 1 read-write LPTIM4RST LPTIM4 reset This bit is set and cleared by software. 13 1 read-write OPAMPRST OPAMP reset This bit is set and cleared by software. 14 1 read-write COMPRST COMP reset This bit is set and cleared by software. 15 1 read-write VREFRST VREFBUF reset This bit is set and cleared by software. 20 1 read-write AHB1ENR AHB1ENR RCC AHB1 peripheral clock enable register 0x88 0x20 0xD0200100 0xFFFFFFFF GPDMA1EN GPDMA1 clock enable This bit is set and cleared by software. 0 1 read-write GPDMA1EN Disabled Peripheral clock disabled 0 Enabled Peripheral clock enabled 1 CORDICEN CORDIC clock enable This bit is set and cleared by software. 1 1 read-write FMACEN FMAC clock enable This bit is set and reset by software. 2 1 read-write MDF1EN MDF1 clock enable This bit is set and reset by software. 3 1 read-write FLASHEN FLASH clock enable This bit is set and cleared by software. This bit can be disabled only when the flash memory is in power-down mode. 8 1 read-write CRCEN CRC clock enable This bit is set and cleared by software. 12 1 read-write JPEGEN JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write TSCEN Touch sensing controller clock enable This bit is set and cleared by software. 16 1 read-write RAMCFGEN RAMCFG clock enable This bit is set and cleared by software. 17 1 read-write DMA2DEN DMA2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 18 1 read-write GFXMMUEN GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write GPU2DEN GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write DCACHE2EN DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 21 1 read-write GTZC1EN GTZC1 clock enable This bit is set and reset by software. 24 1 read-write BKPSRAMEN BKPSRAM clock enable This bit is set and reset by software. 28 1 read-write DCACHE1EN DCACHE1 clock enable This bit is set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2, HSPI1 or FSMC, even if the DCACHE1 is bypassed. 30 1 read-write SRAM1EN SRAM1 clock enable This bit is set and reset by software. 31 1 read-write AHB2ENR1 AHB2ENR1 RCC AHB2 peripheral clock enable register 1 0x8C 0x20 0xC0000000 0xFFFFFFFF GPIOAEN I/O port A clock enable This bit is set and cleared by software. 0 1 read-write GPIOAEN Disabled Peripheral clock disabled 0 Enabled Peripheral clock enabled 1 GPIOBEN I/O port B clock enable This bit is set and cleared by software. 1 1 read-write GPIOCEN I/O port C clock enable This bit is set and cleared by software. 2 1 read-write GPIODEN I/O port D clock enable This bit is set and cleared by software. 3 1 read-write GPIOEEN I/O port E clock enable This bit is set and cleared by software. 4 1 read-write GPIOFEN I/O port F clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 5 1 read-write GPIOGEN I/O port G clock enable This bit is set and cleared by software. 6 1 read-write GPIOHEN I/O port H clock enable This bit is set and cleared by software. 7 1 read-write GPIOIEN I/O port I clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write GPIOJEN I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 9 1 read-write ADC12EN ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 inï¿½STM32U59x/5Ax/5Fx/5Gx. 10 1 read-write DCMI_PSSIEN DCMI and PSSI clock enable This bit is set and cleared by software. 12 1 read-write OTGEN OTG_FS or OTG_HS clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 14 1 read-write OTGHSPHYEN OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write AESEN AES clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 16 1 read-write HASHEN HASH clock enable This bit is set and cleared by software 17 1 read-write RNGEN RNG clock enable This bit is set and cleared by software. 18 1 read-write PKAEN PKA clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write SAESEN SAES clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write OCTOSPIMEN OCTOSPIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 21 1 read-write OTFDEC1EN OTFDEC1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write OTFDEC2EN OTFDEC2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write SDMMC1EN SDMMC1 clock enable This bit is set and cleared by software. 27 1 read-write SDMMC2EN SDMMC2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 28 1 read-write SRAM2EN SRAM2 clock enable This bit is set and reset by software. 30 1 read-write SRAM3EN SRAM3 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 31 1 read-write AHB2ENR2 AHB2ENR2 RCC AHB2 peripheral clock enable register 2 0x90 0x20 0x80000000 0xFFFFFFFF FSMCEN FSMC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 1 read-write FSMCEN Disabled Peripheral clock disabled 0 Enabled Peripheral clock enabled 1 OCTOSPI1EN OCTOSPI1 clock enable This bit is set and cleared by software. 4 1 read-write OCTOSPI2EN OCTOSPI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write HSPI1EN HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 12 1 read-write SRAM6EN SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 30 1 read-write SRAM5EN SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 31 1 read-write AHB3ENR AHB3ENR RCC AHB3 peripheral clock enable register 0x94 0x20 0x80000000 0xFFFFFFFF LPGPIO1EN LPGPIO1 enable This bit is set and cleared by software. 0 1 read-write LPGPIO1EN Disabled Peripheral clock disabled 0 Enabled Peripheral clock enabled 1 PWREN PWR clock enable This bit is set and cleared by software. 2 1 read-write ADC4EN ADC4 clock enable This bit is set and cleared by software. 5 1 read-write DAC1EN DAC1 clock enable This bit is set and cleared by software. 6 1 read-write LPDMA1EN LPDMA1 clock enable This bit is set and cleared by software. 9 1 read-write ADF1EN ADF1 clock enable This bit is set and cleared by software. 10 1 read-write GTZC2EN GTZC2 clock enable This bit is set and cleared by software. 12 1 read-write SRAM4EN SRAM4 clock enable This bit is set and reset by software. 31 1 read-write APB1ENR1 APB1ENR1 RCC APB1 peripheral clock enable register 1 0x9C 0x20 0x00000000 0xFFFFFFFF TIM2EN TIM2 clock enable This bit is set and cleared by software. 0 1 read-write TIM2EN Disabled Peripheral clock disabled 0 Enabled Peripheral clock enabled 1 TIM3EN TIM3 clock enable This bit is set and cleared by software. 1 1 read-write TIM4EN TIM4 clock enable This bit is set and cleared by software. 2 1 read-write TIM5EN TIM5 clock enable This bit is set and cleared by software. 3 1 read-write TIM6EN TIM6 clock enable This bit is set and cleared by software. 4 1 read-write TIM7EN TIM7 clock enable This bit is set and cleared by software. 5 1 read-write WWDGEN WWDG clock enable This bit is set by software to enable the window watchdog clock. It is reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. 11 1 read-write SPI2EN SPI2 clock enable This bit is set and cleared by software. 14 1 read-write USART2EN USART2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 17 1 read-write USART3EN USART3 clock enable This bit is set and cleared by software. 18 1 read-write UART4EN UART4 clock enable This bit is set and cleared by software. 19 1 read-write UART5EN UART5 clock enable This bit is set and cleared by software. 20 1 read-write I2C1EN I2C1 clock enable This bit is set and cleared by software. 21 1 read-write I2C2EN I2C2 clock enable This bit is set and cleared by software. 22 1 read-write CRSEN CRS clock enable This bit is set and cleared by software. 24 1 read-write USART6EN USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write APB1ENR2 APB1ENR2 RCC APB1 peripheral clock enable register 2 0xA0 0x20 0x00000000 0xFFFFFFFF I2C4EN I2C4 clock enable This bit is set and cleared by software 1 1 read-write I2C4EN Disabled Peripheral clock disabled 0 Enabled Peripheral clock enabled 1 LPTIM2EN LPTIM2 clock enable This bit is set and cleared by software. 5 1 read-write I2C5EN I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 6 1 read-write I2C6EN I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 7 1 read-write FDCAN1EN FDCAN1 clock enable This bit is set and cleared by software. 9 1 read-write UCPD1EN UCPD1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write APB2ENR APB2ENR RCC APB2 peripheral clock enable register 0xA4 0x20 0x00000000 0xFFFFFFFF TIM1EN TIM1 clock enable This bit is set and cleared by software. 11 1 read-write TIM1EN Disabled Peripheral clock disabled 0 Enabled Peripheral clock enabled 1 SPI1EN SPI1 clock enable This bit is set and cleared by software. 12 1 read-write TIM8EN TIM8 clock enable This bit is set and cleared by software. 13 1 read-write USART1EN USART1clock enable This bit is set and cleared by software. 14 1 read-write TIM15EN TIM15 clock enable This bit is set and cleared by software. 16 1 read-write TIM16EN TIM16 clock enable This bit is set and cleared by software. 17 1 read-write TIM17EN TIM17 clock enable This bit is set and cleared by software. 18 1 read-write SAI1EN SAI1 clock enable This bit is set and cleared by software. 21 1 read-write SAI2EN SAI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 22 1 read-write USBEN USB clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write GFXTIMEN GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write LTDCEN LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 26 1 read-write DSIEN DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 27 1 read-write APB3ENR APB3ENR RCC APB3 peripheral clock enable register 0xA8 0x20 0x00000000 0xFFFFFFFF SYSCFGEN SYSCFG clock enable This bit is set and cleared by software. 1 1 read-write SYSCFGEN Disabled Peripheral clock disabled 0 Enabled Peripheral clock enabled 1 SPI3EN SPI3 clock enable This bit is set and cleared by software. 5 1 read-write LPUART1EN LPUART1 clock enable This bit is set and cleared by software. 6 1 read-write I2C3EN I2C3 clock enable This bit is set and cleared by software. 7 1 read-write LPTIM1EN LPTIM1 clock enable This bit is set and cleared by software. 11 1 read-write LPTIM3EN LPTIM3 clock enable This bit is set and cleared by software. 12 1 read-write LPTIM4EN LPTIM4 clock enable This bit is set and cleared by software. 13 1 read-write OPAMPEN OPAMP clock enable This bit is set and cleared by software. 14 1 read-write COMPEN COMP clock enable This bit is set and cleared by software. 15 1 read-write VREFEN VREFBUF clock enable This bit is set and cleared by software. 20 1 read-write RTCAPBEN RTC and TAMP APB clock enable This bit is set and cleared by software. 21 1 read-write AHB1SMENR AHB1SMENR RCC AHB1 peripheral clock enable in Sleep and Stop modes register 0xB0 0x20 0xFFFFFFFF 0xFFFFFFFF GPDMA1SMEN GPDMA1 clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 1 read-write GPDMA1SMEN Disabled Peripheral clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Peripheral clocks enabled by the clock gating during Sleep and Stop modes 1 CORDICSMEN CORDIC clocks enable during Sleep and Stop modes This bit is set and cleared by software during Sleep mode. 1 1 read-write FMACSMEN FMAC clocks enable during Sleep and Stop modes. This bit is set and cleared by software. 2 1 read-write MDF1SMEN MDF1 clocks enable during Sleep and Stop modes. This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 3 1 read-write FLASHSMEN FLASH clocks enable during Sleep and Stop modes This bit is set and cleared by software. 8 1 read-write CRCSMEN CRC clocks enable during Sleep and Stop modes This bit is set and cleared by software. 12 1 read-write JPEGSMEN JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write TSCSMEN TSC clocks enable during Sleep and Stop modes This bit is set and cleared by software. 16 1 read-write RAMCFGSMEN RAMCFG clock enable during Sleep and Stop modes This bit is set and cleared by software. 17 1 read-write DMA2DSMEN DMA2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 18 1 read-write GFXMMUSMEN GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write GPU2DSMEN GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write DCACHE2SMEN DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 21 1 read-write GTZC1SMEN GTZC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 24 1 read-write BKPSRAMSMEN BKPSRAM clock enable during Sleep and Stop modes This bit is set and cleared by software 28 1 read-write ICACHESMEN ICACHE clock enable during Sleep and Stop modes This bit is set and cleared by software. 29 1 read-write DCACHE1SMEN DCACHE1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 30 1 read-write SRAM1SMEN SRAM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 31 1 read-write AHB2SMENR1 AHB2SMENR1 RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1 0xB4 0x20 0xFFFFFFFF 0xFFFFFFFF GPIOASMEN I/O port A clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 1 read-write GPIOASMEN Disabled Peripheral clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Peripheral clocks enabled by the clock gating during Sleep and Stop modes 1 GPIOBSMEN I/O port B clocks enable during Sleep and Stop modes This bit is set and cleared by software. 1 1 read-write GPIOCSMEN I/O port C clocks enable during Sleep and Stop modes This bit is set and cleared by software. 2 1 read-write GPIODSMEN I/O port D clocks enable during Sleep and Stop modes This bit is set and cleared by software. 3 1 read-write GPIOESMEN I/O port E clocks enable during Sleep and Stop modes This bit is set and cleared by software. 4 1 read-write GPIOFSMEN I/O port F clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 5 1 read-write GPIOGSMEN I/O port G clocks enable during Sleep and Stop modes This bit is set and cleared by software. 6 1 read-write GPIOHSMEN I/O port H clocks enable during Sleep and Stop modes This bit is set and cleared by software. 7 1 read-write GPIOISMEN I/O port I clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write GPIOJSMEN I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 9 1 read-write ADC12SMEN ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 inï¿½STM32U59x/5Ax/5Fx/5Gx. 10 1 read-write DCMI_PSSISMEN DCMI and PSSI clock enable during Sleep and Stop modes This bit is set and cleared by software. 12 1 read-write OTGSMEN OTG_FS and OTG_HS clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 14 1 read-write OTGHSPHYSMEN OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write AESSMEN AES clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 16 1 read-write HASHSMEN HASH clock enable during Sleep and Stop modes This bit is set and cleared by software 17 1 read-write RNGSMEN RNG clock enable during Sleep and Stop modes This bit is set and cleared by software. 18 1 read-write PKASMEN PKA clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write SAESSMEN SAES accelerator clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write OCTOSPIMSMEN OCTOSPIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 21 1 read-write OTFDEC1SMEN OTFDEC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write OTFDEC2SMEN OTFDEC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write SDMMC1SMEN SDMMC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 27 1 read-write SDMMC2SMEN SDMMC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 28 1 read-write SRAM2SMEN SRAM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. 30 1 read-write SRAM3SMEN SRAM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 31 1 read-write AHB2SMENR2 AHB2SMENR2 RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2 0xB8 0x20 0xFFFFFFFF 0xFFFFFFFF FSMCSMEN FSMC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 1 read-write FSMCSMEN Disabled Peripheral clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Peripheral clocks enabled by the clock gating during Sleep and Stop modes 1 OCTOSPI1SMEN OCTOSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 4 1 read-write OCTOSPI2SMEN OCTOSPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write HSPI1SMEN HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 12 1 read-write SRAM6SMEN SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 30 1 read-write SRAM5SMEN SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 31 1 read-write AHB3SMENR AHB3SMENR RCC AHB3 peripheral clock enable in Sleep and Stop modes register 0xBC 0x20 0xFFFFFFFF 0xFFFFFFFF LPGPIO1SMEN LPGPIO1 enable during Sleep and Stop modes This bit is set and cleared by software. 0 1 read-write LPGPIO1SMEN Disabled Peripheral clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Peripheral clocks enabled by the clock gating during Sleep and Stop modes 1 PWRSMEN PWR clock enable during Sleep and Stop modes This bit is set and cleared by software. 2 1 read-write ADC4SMEN ADC4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write DAC1SMEN DAC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 6 1 read-write LPDMA1SMEN LPDMA1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 9 1 read-write ADF1SMEN ADF1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 10 1 read-write GTZC2SMEN GTZC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. 12 1 read-write SRAM4SMEN SRAM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. 31 1 read-write APB1SMENR1 APB1SMENR1 RCC APB1 peripheral clock enable in Sleep and Stop modes register 1 0xC4 0x20 0xFFFFFFFF 0xFFFFFFFF TIM2SMEN TIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 1 read-write TIM2SMEN Disabled Peripheral clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Peripheral clocks enabled by the clock gating during Sleep and Stop modes 1 TIM3SMEN TIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. 1 1 read-write TIM4SMEN TIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. 2 1 read-write TIM5SMEN TIM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. 3 1 read-write TIM6SMEN TIM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. 4 1 read-write TIM7SMEN TIM7 clock enable during Sleep and Stop modes This bit is set and cleared by software. 5 1 read-write WWDGSMEN Window watchdog clock enable during Sleep and Stop modes This bit is set and cleared by software. It is forced to one by hardware when the hardware WWDG option is activated. 11 1 read-write SPI2SMEN SPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 14 1 read-write USART2SMEN USART2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 17 1 read-write USART3SMEN USART3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 18 1 read-write UART4SMEN UART4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 19 1 read-write UART5SMEN UART5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 20 1 read-write I2C1SMEN I2C1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 21 1 read-write I2C2SMEN I2C2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 22 1 read-write CRSSMEN CRS clock enable during Sleep and Stop modes This bit is set and cleared by software. 24 1 read-write USART6SMEN USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write APB1SMENR2 APB1SMENR2 RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 0xC8 0x20 0xFFFFFFFF 0xFFFFFFFF I2C4SMEN I2C4 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. 1 1 read-write I2C4SMEN Disabled Peripheral clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Peripheral clocks enabled by the clock gating during Sleep and Stop modes 1 LPTIM2SMEN LPTIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write I2C5SMEN I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 6 1 read-write I2C6SMEN I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 7 1 read-write FDCAN1SMEN FDCAN1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 9 1 read-write UCPD1SMEN UCPD1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write APB2SMENR APB2SMENR RCC APB2 peripheral clocks enable in Sleep and Stop modes register 0xCC 0x20 0xFFFFFFFF 0xFFFFFFFF TIM1SMEN TIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 11 1 read-write TIM1SMEN Disabled Peripheral clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Peripheral clocks enabled by the clock gating during Sleep and Stop modes 1 SPI1SMEN SPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 12 1 read-write TIM8SMEN TIM8 clock enable during Sleep and Stop modes This bit is set and cleared by software. 13 1 read-write USART1SMEN USART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 14 1 read-write TIM15SMEN TIM15 clock enable during Sleep and Stop modes This bit is set and cleared by software. 16 1 read-write TIM16SMEN TIM16 clock enable during Sleep and Stop modes This bit is set and cleared by software. 17 1 read-write TIM17SMEN TIM17 clock enable during Sleep and Stop modes This bit is set and cleared by software. 18 1 read-write SAI1SMEN SAI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 21 1 read-write SAI2SMEN SAI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 22 1 read-write USBSMEN USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write GFXTIMSMEN GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write LTDCSMEN LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 26 1 read-write DSISMEN DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 27 1 read-write APB3SMENR APB3SMENR RCC APB3 peripheral clock enable in Sleep and Stop modes register 0xD0 0x20 0xFFFFFFFF 0xFFFFFFFF SYSCFGSMEN SYSCFG clock enable during Sleep and Stop modes This bit is set and cleared by software. 1 1 read-write SYSCFGSMEN Disabled Peripheral clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Peripheral clocks enabled by the clock gating during Sleep and Stop modes 1 SPI3SMEN SPI3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write LPUART1SMEN LPUART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 6 1 read-write I2C3SMEN I2C3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 7 1 read-write LPTIM1SMEN LPTIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 11 1 read-write LPTIM3SMEN LPTIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 12 1 read-write LPTIM4SMEN LPTIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 13 1 read-write OPAMPSMEN OPAMP clock enable during Sleep and Stop modes This bit is set and cleared by software. 14 1 read-write COMPSMEN COMP clock enable during Sleep and Stop modes This bit is set and cleared by software. 15 1 read-write VREFSMEN VREFBUF clock enable during Sleep and Stop modes This bit is set and cleared by software. 20 1 read-write RTCAPBSMEN RTC and TAMP APB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 21 1 read-write SRDAMR SRDAMR RCC SmartRun domain peripheral autonomous mode register 0xD8 0x20 0x00000000 0xFFFFFFFF SPI3AMEN SPI3 autonomous mode enable in Stop 0,1, 2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write SPI3AMEN Disabled Peripheral autonomous mode disabled during Stop 0/1/2 mode 0 Enabled Peripheral autonomous mode enabled during Stop 0/1/2 mode 1 LPUART1AMEN LPUART1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 6 1 read-write I2C3AMEN I2C3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 7 1 read-write LPTIM1AMEN LPTIM1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 11 1 read-write LPTIM3AMEN LPTIM3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 12 1 read-write LPTIM4AMEN LPTIM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 13 1 read-write OPAMPAMEN OPAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. 14 1 read-write COMPAMEN COMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. 15 1 read-write VREFAMEN VREFBUF autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. 20 1 read-write RTCAPBAMEN RTC and TAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 21 1 read-write ADC4AMEN ADC4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 25 1 read-write LPGPIO1AMEN LPGPIO1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. 26 1 read-write DAC1AMEN DAC1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 27 1 read-write LPDMA1AMEN LPDMA1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 28 1 read-write ADF1AMEN ADF1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 29 1 read-write SRAM4AMEN SRAM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. 31 1 read-write CCIPR1 CCIPR1 RCC peripherals independent clock configuration register 1 0xE0 0x20 0x00000000 0xFFFFFFFF USART1SEL USART1 kernel clock source selection These bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 0 2 read-write USART1SEL PCLK PCLKx selected 0 SYSCLK SYSCLK selected 1 HSI16 HSI16 selected 2 MSIK MSIK selected 3 USART2SEL USART2 kernel clock source selection These bits are used to select the USART2 kernel clock source. The USART2 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 2 2 read-write USART3SEL USART3 kernel clock source selection These bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 4 2 read-write UART4SEL UART4 kernel clock source selection These bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 6 2 read-write UART5SEL UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 8 2 read-write I2C1SEL I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16ï¿½or MSIK. 10 2 read-write I2C2SEL I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16ï¿½or MSIK. 12 2 read-write I2C4SEL I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16ï¿½or MSIK. 14 2 read-write SPI2SEL SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK. 16 2 read-write LPTIM2SEL Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1. 18 2 read-write LPTIM2SEL PCLK1 PCLK1 selected 0 LSI LSI selected 1 HSI16 HSI16 selected 2 MSIK MSIK selected 3 SPI1SEL SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK. 20 2 read-write SYSTICKSEL SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry. 22 2 read-write SYSTICKSEL HCLK_Div8 HCLK/8 selected 0 LSI LSI selected 1 LSE LSE selected 2 FDCAN1SEL FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source. 24 2 read-write FDCAN1SEL HSE HSE clock selected 0 PLL1Q PLL1 "Q" (pll2_q_ck) selected 1 PLL2P PLL2 "P" (pll1_p_ck) selected 2 ICLKSEL Intermediate clock source selection These bits are used to select the clock source for the OTG_FS, the USB, and the SDMMC. 26 2 read-write ICLKSEL HSI HSI48 clock selected 0 PLL2Q PLL2 "Q" (pll2_q_ck) selected 1 PLL1Q PLL1 "Q" (pll1_q_ck) selected 2 MSIK MSIK clock selected 3 TIMICSEL Clock sources for TIM16,TIM17, and LPTIM2 internal input capture When TIMICSEL2 is set, the TIM16, TIM17, and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4, or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK, and MSIS clock sources cannot be selected asï¿½TIM16, TIM17, or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division. 29 3 read-write TIMICSEL HsiMsisMsis HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture 4 HsiMsisMsik HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture 5 HsiMsikMsis HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture 6 HsiMsikMsik HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture 7 Disabled HSI, MSIK and MSIS dividers disabled true CCIPR2 CCIPR2 RCC peripherals independent clock configuration register 2 0xE4 0x20 0x00000000 0xFFFFFFFF MDF1SEL MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved 0 3 read-write MDF1SEL HCLK HCLK selected 0 PLL1P PLL1 "P" (pll1_p_ck) selected 1 PLL3Q PLL3 "Q" (pll3_q_ck) selected 2 AUDIOCLK input pin AUDIOCLK selected 3 MSIK MSIK clock selected 4 SAI1SEL SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. 5 3 read-write SAI1SEL PLL2P PLL2 "P" (pll2_p_ck) selected 0 PLL3P PLL3 "P" (pll3_p_ck) selected 1 PLL1P PLL1 "P" (pll1_p_ck) selected 2 AUDIOCLK input pin AUDIOCLK selected 3 HSI16 HSI16 clock selected 4 SAI2SEL SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 8 3 read-write SAESSEL SAES kernel clock source selection This bit is used to select the SAES kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 11 1 read-write SAESSEL SHSI SHSI selected 0 SHSI_Div2 SHSI / 2 selected, can be used in range 4 1 RNGSEL RNG kernel clock source selection These bits are used to select the RNG kernel clock source. 12 2 read-write RNGSEL HSI48 HSI48 clock selected 0 HSI48_Div2 HSI48 / 2 selected, can be used in range 4 1 HSI16 HSI16 selected 2 SDMMCSEL SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change it only after reset and before enabling the SDMMC. 14 1 read-write SDMMCSEL ICLK ICLK clock selected 0 PLL1P PLL1 "P" (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) 1 DSISEL DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write DSISEL PLL3P PLL3 "P" (pll3_p_ck) selected 0 DSI_PHY_PLL DSI PHY PLL output selected 1 USART6SEL USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source. The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 16 2 read-write USART6SEL PCLK1 PCLK1 selected 0 SYSCLK SYSCLK selected 1 HSI16 HSI16 selected 2 MSIK MSIK selected 3 LTDCSEL LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 18 1 read-write LTDCSEL PLL3R PLL3 "R" (pll3_r_ck) selected 0 PLL2R PLL2 "R" (pll2_r_ck) selected 1 OCTOSPISEL OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source. 20 2 read-write OCTOSPISEL SYSCLK SYSCLK selected 0 MSIK MSIK selected 1 PLL1Q PLL1 "Q" (pll1_q_ck) selected, can be up to 200 MHz 2 PLL2Q PLL2 "Q" (pll2_q_ck) selected, can be up to 200 MHz 3 HSPI1SEL HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 22 2 read-write HSPI1SEL SYSCLK SYSCLK selected 0 PLL1Q PLL1 "Q" (pll1_q_ck) selected, can be up to 200 MHz 1 PLL2Q PLL2 "Q" (pll2_q_ck) selected, can be up to 200 MHz 2 PLL3R PLL3 "R" (pll3_r_ck) selected, can be up to 200 MHz 3 I2C5SEL I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16ï¿½or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 24 2 read-write I2C6SEL I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16ï¿½or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 26 2 read-write OTGHSSEL OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 30 2 read-write OTGHSSEL HSE HSE selected 0 PLL1P PLL1 "Q" (pll1_q_ck) selected 1 HSE2 HSE/2 selected 2 PLL1P_Div2 PLL1 "P" divided by 2 (pll1_p_ck/2) selected 3 CCIPR3 CCIPR3 RCC peripherals independent clock configuration register 3 0xE8 0x20 0x00000000 0xFFFFFFFF LPUART1SEL LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. others: reserved Note: The LPUART1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16, LSE, or MSIK. 0 3 read-write LPUART1SEL PCLK3 PCLK3 selected 0 SYSCLK SYSCLK selected 1 HSI16 HSI16 selected 2 LSE LSE selected 3 MSIK MSIK selected 4 SPI3SEL SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note: The SPI3 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK. 3 2 read-write SPI3SEL PCLK3 PCLK3 selected 0 SYSCLK SYSCLK selected 1 HSI16 HSI16 selected 2 MSIK MSIK selected 3 I2C3SEL I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note: The I2C3 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK. 6 2 read-write LPTIM34SEL LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1, or MSIK with MSIKERONï¿½=ï¿½1. 8 2 read-write LPTIM34SEL MSIK MSIK clock selected 0 LSI LSI selected 1 HSI HSI selected 2 LSE LSE selected 3 LPTIM1SEL LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Note: The LPTIM1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1, or MSIK with MSIKERON = 1. 10 2 read-write LPTIM1SEL MSIK MSIK clock selected 0 LSI LSI selected 1 HSI16 HSI16 selected 2 LSE LSE selected 3 ADCDACSEL ADC1, ADC2, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC2, ADC4, and DAC1 kernel clock source. others: reserved Note: The ADC1, ADC2, ADC4, and DAC1 are functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional inï¿½Stop 2 mode). 12 3 read-write ADCDACSEL HCLK HCLK clock selected 0 SYSCLK SYSCLK selected 1 PLL2R PLL2 "R" (pll2_r_ck) selected 2 HSE HSE clock selected 3 HSI16 HSI16 clock selected 4 MSIK MSIK clock selected 5 DAC1SEL DAC1 sample-and-hold clock source selection This bit is used to select the DAC1 sample-and-hold clock source. 15 1 read-write DAC1SEL LSE LSE selected 0 LSI LSI selected 1 ADF1SEL ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. others: reserved Note: The ADF1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK. 16 3 read-write ADF1SEL HCLK HCLK selected 0 PLL1P PLL1 "P" (pll1_p_ck) selected 1 PLL3Q PLL3 "Q" (pll3_q_ck) selected 2 AUDIOCLK input pin AUDIOCLK selected 3 MSIK MSIK clock selected 4 BDCR BDCR RCC backup domain control register 0xF0 0x20 0x00000000 0xFFFFFFFF LSEON LSE oscillator enable This bit is set and cleared by software. 0 1 read-write LSEON Disabled LSE oscillator off 0 Enabled LSE oscillator on 1 LSERDY LSE oscillator ready This bit is set and cleared by hardware to indicate when the external 32ï¿½kHz oscillator is stable. After LSEON is cleared, this LSERDY bit goes low after six external low-speed oscillator clock cycles. 1 1 read-only LSERDYR NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEBYP LSE oscillator bypass This bit is set and cleared by software to bypass oscillator in debug mode. It can be written only when the external 32ï¿½kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). 2 1 read-write LSEBYP NotBypassed LSE oscillator not bypassed 0 Bypassed LSE oscillator bypassed 1 LSEDRV LSE oscillator drive capability This bitfield is set by software to modulate the drive capability of the LSE oscillator. It can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in âXtal modeâ when it is not in bypass mode. 3 2 read-write LSEDRV Lower 'Xtal mode' lower driving capability 0 MediumLow 'Xtal mode' medium-low driving capability 1 MediumHigh 'Xtal mode' medium-high driving capability 2 Higher 'Xtal mode' higher driving capability 3 LSECSSON CSS on LSE enable This bit is set by software to enable the CSS on LSE. It must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSDï¿½=ï¿½1). In that case, the software must disable this LSECSSON bit. 5 1 read-write LSECSSON Disabled CSS on LSE OFF 0 Enabled CSS on LSE ON 1 LSECSSD CSS on LSE failure detection This bit is set by hardware to indicate when a failure is detected by the CCS on the external 32ï¿½kHz oscillator (LSE). 6 1 read-only LSECSSDR NoFailure No failure detected on LSE 0 Failure Failure detected on LSE 1 LSESYSEN LSE system clock (LSESYS) enable This bit is set by software to enable always the LSE system clock generated by RCC, which can be used by any peripheral when its source clock is the LSE, or at system level if one of LSCOSEL, MCO, or MSI PLL mode is needed. 7 1 read-write LSESYSEN Disabled LSE can be used only for RTC, TAMP, and CSS on LSE 0 Enabled LSE can be used by any other peripheral or function 1 RTCSEL RTC and TAMP clock source selection This bit is set by software to select the clock source for the RTC and TAMP. Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless theï¿½backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). BDRST bit can be used to reset them. 8 2 read-write RTCSEL NoClock No clock selected 0 LSE LSE oscillator clock selected 1 LSI LSI oscillator clock selected 2 HSE_Div32 HSE oscillator clock divided by 32 selected 3 LSESYSRDY LSE system clock (LSESYS) ready This bit is set and cleared by hardware to indicate when the LSE system clock is stable.When LSESYSEN is set, this LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. 11 1 read-only LSESYSRDYR NotReady LSESYS clock not ready 0 Ready LSESYS clock ready 1 LSEGFON LSE clock glitch filter enable This bit is set and cleared by hardware to enable the LSE glitch filter. It can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0). 12 1 read-write LSEGFON Disabled LSE glitch filter disabled 0 Enabled LSE glitch filter enabled 1 RTCEN RTC and TAMP clock enable This bit is set and cleared by software. 15 1 read-write RTCEN Disabled RTC and TAMP clock disabled 0 Enabled RTC and TAMP clock enabled 1 BDRST Backup domain software reset This bit is set and cleared by software. 16 1 read-write BDRST NoReset Reset not activated 0 Reset Reset the entire backup domain 1 LSCOEN Low-speed clock output (LSCO) enable This bit is set and cleared by software. 24 1 read-write LSCOEN Disabled LSCO disabled 0 Enabled LSCO enabled 1 LSCOSEL Low-speed clock output selection This bit is set and cleared by software. 25 1 read-write LSCOSEL LSI LSI clock selected 0 LSE LSE clock selected 1 LSION LSI oscillator enable This bit is set and cleared by software. The LSI oscillator is disabled 60ï¿½ï¿½s maximum after the LSION bit is cleared. 26 1 read-write LSION Disabled LSI oscillator OFF 0 Enabled LSI oscillator ON 1 LSIRDY LSI oscillator ready This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. Afterï¿½LSION is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. 27 1 read-write LSIRDYR read NotReady LSI oscillator not ready 0 Ready LSI oscillator ready 1 LSIPREDIV Low-speed clock divider configuration This bit is set and cleared by software to enable the LSI division. It can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 Î¼s after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. 28 1 read-write LSIPREDIV Div1 LSI not divided 0 Div128 LSI divided by 128 1 CSR CSR RCC control/status register 0xF4 0x20 0x0C004400 0xFFFFFFFF MSIKSRANGE MSIK range after Standby mode This bit is set by software to chose the MSIK frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4ï¿½MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing this bitfield does not change the current MSIK frequency. 8 4 read-write MSIKSRANGE f_4MHz Range 4 around 4 MHz 4 f_2MHz Range 5 around 2 MHz 5 f_1_33MHz Range 6 around 1.33 MHz 6 f_1MHz Range 7 around 1 MHz 7 f_3_072MHz Range 8 around 3.072 MHz 8 MSISSRANGE MSIS range after Standby mode This bitfield is set by software to chose the MSIS frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4ï¿½MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing this bitfield does not change the current MSIS frequency. 12 4 read-write RMVF Remove reset flag This bit is set by software to clear the reset flags. 23 1 read-write RMVFW write Clear Clear the reset flags 1 OBLRSTF Option-byte loader reset flag This bit is set by hardware when a reset from the option-byte loading occurs. It is cleared byï¿½writing to the RMVF bit. 25 1 read-only OBLRSTFR NotOccured No reset from option-byte loading occurred 0 Occured Reset from option-byte loading occurred 1 PINRSTF NRST pin reset flag This bit is set by hardware when a reset from the NRST pin occurs. It is cleared by writing toï¿½the RMVF bit. 26 1 read-only PINRSTFR NotOccured No reset from NRST pin occurred 0 Occured Reset from NRST pin occurred 1 BORRSTF Brownout reset or an exit from Shutdown mode reset flag This bit is set by hardware when a brownout reset or an exit from Shutdown mode reset occurs. It is cleared by writing to the RMVF bit. 27 1 read-only BORRSTFR NotOccured No BOR/exit from Shutdown mode reset occurred 0 Occured BOR/exit from Shutdown mode reset occurred 1 SFTRSTF Software reset flag This bit is set by hardware when a software reset occurs. It is cleared by writing to RMVF. 28 1 read-only SFTRSTFR NotOccured No software reset occurred 0 Occured Software reset occurred 1 IWDGRSTF Independent watchdog reset flag This bit is set by hardware when an independent watchdog reset domain occurs. It is cleared by writing to the RMVF bit. 29 1 read-only IWDGRSTFR NotOccured No independent watchdog reset occurred 0 Occured Independent watchdog reset occurred 1 WWDGRSTF Window watchdog reset flag This bit is set by hardware when a window watchdog reset occurs. It is cleared by writing toï¿½the RMVF bit. 30 1 read-only WWDGRSTFR NotOccured No window watchdog reset occurred 0 Occured Window watchdog reset occurred 1 LPWRRSTF Low-power reset flag This bit is set by hardware when a reset occurs due to a Stop, Standby, or Shutdown mode entry, whereas the corresponding NRST_STOP, NRST_STBY, or NRST_SHDW option bit is cleared. This bit is cleared by writing to the RMVF bit. 31 1 read-only LPWRRSTFR NotOccured No illegal low-power mode reset occurred 0 Occured Illegal low-power mode reset occurred 1 SECCFGR SECCFGR RCC secure configuration register 0x110 0x20 0x00000000 0xFFFFFFFF HSISEC HSI clock configuration and status bit security This bit is set and reset by software. 0 1 read-write HSISEC NonSecure Nonsecure 0 Secure Secure 1 HSESEC HSE clock configuration bits, status bit and HSE_CSS security This bit is set and reset by software. 1 1 read-write MSISEC MSI clock configuration and status bit security This bit is set and reset by software. 2 1 read-write LSISEC LSI clock configuration and status bit security This bit is set and reset by software. 3 1 read-write LSESEC LSE clock configuration and status bit security This bit is set and reset by software. 4 1 read-write SYSCLKSEC SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security This bit is set and reset by software. 5 1 read-write PRESCSEC AHBx/APBx prescaler configuration bits security This bit is set and reset by software. 6 1 read-write PLL1SEC PLL1 clock configuration and status bit security This bit is set and reset by software. 7 1 read-write PLL2SEC PLL2 clock configuration and status bit security Set and reset by software. 8 1 read-write PLL3SEC PLL3 clock configuration and status bit security This bit is set and reset by software. 9 1 read-write ICLKSEC Intermediate clock source selection security This bit is set and reset by software. 10 1 read-write HSI48SEC HSI48 clock configuration and status bit security This bit is set and reset by software. 11 1 read-write RMVFSEC Remove reset flag security This bit is set and reset by software. 12 1 read-write PRIVCFGR PRIVCFGR RCC privilege configuration register 0x114 0x20 0x00000000 0xFFFFFFFF SPRIV RCC secure function privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access. 0 1 read-write SPRIV Unprivileged Read and write to RCC secure functions can be done by privileged or unprivileged access 0 Privileged Read and write to RCC secure functions can be done by privileged access only 1 NSPRIV RCC non-secure function privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. 1 1 read-write NSPRIV Unprivileged Read and write to RCC nonsecure functions can be done by privileged or unprivileged access 0 Privileged Read and write to RCC nonsecure functions can be done by privileged access only 1 SEC_RCC 0x56020C00 RTC Real-time clock RTC 0x46007800 0x0 0x400 registers RTC RTC global non-secure interrupts 2 RTC_S RTC secure global secure interrupts 3 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 0 15 YU Year units in BCD format 16 4 0 15 WDU Week day units 13 3 1 7 MT Month tens in BCD format 12 1 0 1 MU Month units in BCD format 8 4 0 15 DT Date tens in BCD format 4 2 0 3 DU Date units in BCD format 0 4 0 15 SSR SSR RTC sub second register 0x8 0x20 read-only 0x00000000 SS SS 0 32 0 65535 ICSR ICSR RTC initialization control and status register 0xC 0x20 0x00000007 WUTWF Wakeup timer write flag 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 BIN BIN 8 2 read-write BCDU BCDU 10 3 read-write RECALPF Recalibration pending Flag 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 0 127 PREDIV_S Synchronous prescaler factor 0 15 0 32767 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 0 65535 WUTOCLR WUTOCLR 16 16 CR CR RTC control register 0x18 0x20 0x00000000 WUCKSEL WUCKSEL 0 3 read-write WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE TSEDGE 3 1 read-write TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON REFCKON 4 1 read-write REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD BYPSHAD 5 1 read-write BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT FMT 6 1 read-write FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 SSRUIE SSRUIE 7 1 read-write 2 0x1 A,B ALR%sE Alarm %s enable 8 1 read-write ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE WUTE 10 1 read-write WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE TSE 11 1 read-write TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 read-write ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE WUTIE 14 1 read-write WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE TSIE 15 1 read-write TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H ADD1H 16 1 write-only ADD1HW Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H SUB1H 17 1 write-only SUB1HW Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP BKP 18 1 read-write BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 COSEL COSEL 19 1 read-write COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL POL 20 1 read-write POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL OSEL 21 2 read-write OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE COE 23 1 read-write COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ITSE ITSE 24 1 read-write ITSE Disabled Internal event timestamp disabled 0 Enabled Internal event timestamp enabled 1 TAMPTS TAMPTS 25 1 read-write TAMPTS Disabled Tamper detection event does not cause a RTC timestamp to be saved 0 Enabled Save RTC timestamp on tamper detection event 1 TAMPOE TAMPOE 26 1 read-write TAMPOE Disabled The tamper flag is not routed on TAMPALRM 0 Enabled The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL 1 ALRAFCLR ALRAFCLR 27 1 read-write ALRBFCLR ALRBFCLR 28 1 read-write TAMPALRM_PU TAMPALRM_PU 29 1 read-write TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPALRM_TYPE TAMPALRM_TYPE 30 1 read-write TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 OUT2EN OUT2EN 31 1 read-write OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 PRIVCR PRIVCR RTC privilege mode control register 0x1C 0x20 read-write 0x00000000 PRIV PRIV 15 1 INITPRIV INITPRIV 14 1 CALPRIV CALPRIV 13 1 TSPRIV TSPRIV 3 1 WUTPRIV WUTPRIV 2 1 ALRBPRIV ALRBPRIV 1 1 ALRAPRIV ALRAPRIV 0 1 SECCFGR SECCFGR RTC secure mode control register 0x20 0x20 read-write 0x00000000 SEC SEC 15 1 INITSEC INITSEC 14 1 CALSEC CALSEC 13 1 TSSEC TSSEC 3 1 WUTSEC WUTSEC 2 1 ALRBSEC ALRBSEC 1 1 ALRASEC ALRASEC 0 1 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR calibration register 0x28 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW8 EightSeconds When CALW8 is set to â1â, the 8-second calibration cycle period is selected 1 CALW16 Use a 16-second calibration cycle period 13 1 CALW16 SixteenSeconds When CALW16 is set to â1â, the 16-second calibration cycle period is selected.This bit must not be set to â1â if CALW8=1 1 LPCAL LPCAL 12 1 CALM Calibration minus 0 9 0 511 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 SUBFS Subtract a fraction of a second 0 15 0 32767 TSTR TSTR time stamp time register 0x30 TSDR TSDR time stamp date register 0x34 TSSSR TSSSR timestamp sub second register 0x38 2 0x8 A,B ALRM%sR ALRM%sR Alarm %s register 0x40 0x20 read-write 0x00000000 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day donât care in Alarm comparison 1 MSK4 Alarm date mask 31 1 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is donât care. 1 DT Date tens in BCD format 28 2 0 3 DU Date units or day in BCD format 24 4 0 15 MSK3 Alarm hours mask 23 1 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MSK2 Alarm minutes mask 15 1 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 2 0x8 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 SSCLR SSCLR 31 1 MASKSS Mask the most-significant bits starting at this bit 24 6 SS Sub seconds value 0 15 0 32767 SR SR RTC status register 0x50 0x20 read-only 0x00000000 2 0x1 A,B ALR%sF Alarm %s flag 0 1 ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 WUTF WUTF 2 1 WUTF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSF TSF 3 1 TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVF TSOVF 4 1 TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSF ITSF 5 1 ITSF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SSRUF SSRUF 6 1 MISR MISR RTC non-secure masked interrupt status register 0x54 0x20 read-only 0x00000000 2 0x1 A,B ALR%sMF Alarm %s masked flag 0 1 ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 WUTMF WUTMF 2 1 WUTMF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSMF TSMF 3 1 TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVMF TSOVMF 4 1 TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSMF ITSMF 5 1 ITSMF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SSRUMF SSRUMF 6 1 SMISR SMISR RTC secure masked interrupt status register 0x58 0x20 read-only 0x00000000 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 WUTMF WUTMF 2 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 ITSMF ITSMF 5 1 SSRUMF SSRUMF 6 1 SCR SCR RTC status clear register 0x5C 0x20 write-only 0x00000000 CALRAF CALRAF 0 1 CALRAF Clear Clear interrupt flag 1 CALRBF CALRBF 1 1 CWUTF CWUTF 2 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CITSF CITSF 5 1 CSSRUF CSSRUF 6 1 2 0x4 A,B ALR%sBINR ALR%sBINR Alarm %s binary mode register 0x70 0x20 read-write 0x00000000 SS Synchronous counter alarm value in Binary mode 0 32 SEC_RTC 0x56007800 SAI1 Serial audio interface SAI 0x40015400 0x0 0x400 registers SAI1 SAI1 global interrupt 90 GCR GCR Global configuration register 0x0 0x20 read-write 0x00000000 SYNCIN Synchronization inputs 0 2 SYNCOUT Synchronization outputs 4 2 ACR1 ACR1 A Configuration register 1 0x4 0x20 read-write 0x00000040 MCKEN MCKEN 27 1 OSR OSR 26 1 MCKDIV Master clock divider 20 6 NODIV No divider 19 1 DMAEN DMA enable 17 1 SAIAEN Audio block A enable 16 1 OUTDRIV Output drive 13 1 MONO Mono mode 12 1 SYNCEN Synchronization enable 10 2 CKSTR Clock strobing edge 9 1 LSBFIRST Least significant bit first 8 1 DS Data size 5 3 PRTCFG Protocol configuration 2 2 MODE Audio block mode 0 2 BCR1 BCR1 B Configuration register 1 0x24 0x20 read-write 0x00000040 MCKEN MCKEN 27 1 OSR OSR 26 1 MCKDIV Master clock divider 20 6 NODIV No divider 19 1 DMAEN DMA enable 17 1 SAIAEN Audio block A enable 16 1 OUTDRIV Output drive 13 1 MONO Mono mode 12 1 SYNCEN Synchronization enable 10 2 CKSTR Clock strobing edge 9 1 LSBFIRST Least significant bit first 8 1 DS Data size 5 3 PRTCFG Protocol configuration 2 2 MODE Audio block mode 0 2 ACR2 ACR2 A Configuration register 2 0x8 0x20 read-write 0x00000000 COMP Companding mode 14 2 CPL Complement bit 13 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTE Mute 5 1 TRIS Tristate management on data line 4 1 FFLUSH FIFO flush 3 1 FTH FIFO threshold 0 3 BCR2 BCR2 B Configuration register 2 0x28 0x20 read-write 0x00000000 COMP Companding mode 14 2 CPL Complement bit 13 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTE Mute 5 1 TRIS Tristate management on data line 4 1 FFLUSH FIFO flush 3 1 FTH FIFO threshold 0 3 AFRCR AFRCR A frame configuration register 0xC 0x20 0x00000007 FSOFF Frame synchronization offset 18 1 read-write FSPOL Frame synchronization polarity 17 1 read-write FSDEF Frame synchronization definition 16 1 read-write FSALL Frame synchronization active level length 8 7 read-write FRL Frame length 0 8 read-write BFRCR BFRCR B frame configuration register 0x2C 0x20 0x00000007 FSOFF Frame synchronization offset 18 1 read-write FSPOL Frame synchronization polarity 17 1 read-write FSDEF Frame synchronization definition 16 1 read-write FSALL Frame synchronization active level length 8 7 read-write FRL Frame length 0 8 read-write ASLOTR ASLOTR A Slot register 0x10 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 FBOFF First bit offset 0 5 BSLOTR BSLOTR B Slot register 0x30 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 FBOFF First bit offset 0 5 AIM AIM A Interrupt mask register 0x14 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 WCKCFGIE Wrong clock configuration interrupt enable 2 1 MUTEDETIE Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 BIM BIM B Interrupt mask register 0x34 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 WCKCFGIE Wrong clock configuration interrupt enable 2 1 MUTEDETIE Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 ASR ASR A Status register 0x18 0x20 read-only 0x00000008 FLVL FIFO level threshold 16 3 LFSDET Late frame synchronization detection 6 1 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FREQ FIFO request 3 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 BSR BSR B Status register 0x38 0x20 read-only 0x00000008 FLVL FIFO level threshold 16 3 LFSDET Late frame synchronization detection 6 1 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FREQ FIFO request 3 1 WCKCFG Wrong clock configuration flag 2 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 ACLRFR ACLRFR A Clear flag register 0x1C 0x20 write-only 0x00000000 CLFSDET Clear late frame synchronization detection flag 6 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CCNRDY Clear codec not ready flag 4 1 CWCKCFG Clear wrong clock configuration flag 2 1 CMUTEDET Mute detection flag 1 1 COVRUDR Clear overrun / underrun 0 1 BCLRFR BCLRFR B Clear flag register 0x3C 0x20 write-only 0x00000000 CLFSDET Clear late frame synchronization detection flag 6 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CCNRDY Clear codec not ready flag 4 1 CWCKCFG Clear wrong clock configuration flag 2 1 CMUTEDET Mute detection flag 1 1 COVRUDR Clear overrun / underrun 0 1 ADR ADR A Data register 0x20 0x20 read-write 0x00000000 DATA Data 0 32 BDR BDR B Data register 0x40 0x20 read-write 0x00000000 DATA Data 0 32 PDMCR PDMCR PDM control register 0x44 0x20 read-write 0x00000000 PDMEN PDM enable 0 1 MICNBR MICNBR 4 2 CKEN1 Clock enable of bitstream clock number 1 8 1 CKEN2 CKEN2 9 1 CKEN3 CKEN3 10 1 CKEN4 CKEN4 11 1 PDMDLY PDMDLY PDM delay register 0x48 0x20 read-write 0x00000000 DLYM1L Delay line adjust for first microphone of pair 1 0 3 DLYM1R Delay line adjust for second microphone of pair 1 4 3 DLYM2L Delay line for first microphone of pair 2 8 3 DLYM2R Delay line for second microphone of pair 2 12 3 DLYM3L DLYM3L 16 3 DLYM3R DLYM3R 20 3 DLYM4L DLYM4L 24 3 DLYM4R DLYM4R 28 3 SEC_SAI1 0x50015400 SAI2 0x40015800 SAI2 SAI2 global interrupt 91 SEC_SAI2 0x50015800 GPDMA1 GPDMA1 GPDMA 0x40020000 0x0 0x1000 registers GPDMA1_CH0 GPDMA1 channel 0 global interrupt 29 GPDMA1_CH1 GPDMA1 channel 1 global interrupt 30 GPDMA1_CH2 GPDMA1 channel 2 global interrupt 31 GPDMA1_CH3 GPDMA1 channel 3 global interrupt 32 GPDMA1_CH4 GPDMA1 channel 4 global interrupt 33 GPDMA1_CH5 GPDMA1 channel 5 global interrupt 34 GPDMA1_CH6 GPDMA1 channel 6 global interrupt 35 GPDMA1_CH7 GPDMA1 channel 7 global interrupt 36 GPDMA1_CH8 GPDMA1 channel 8 global interrupt 80 GPDMA1_CH9 GPDMA1 channel 9 global interrupt 81 GPDMA1_CH10 GPDMA1 channel 10 global interrupt 82 GPDMA1_CH11 GPDMA1 channel 11 global interrupt 83 GPDMA1_CH12 GPDMA1 channel 12 global interrupt 84 GPDMA1_CH13 GPDMA1 channel 13 global interrupt 85 GPDMA1_CH14 GPDMA1 channel 14 global interrupt 86 GPDMA1_CH15 GPDMA1 channel 15 global interrupt 87 SECCFGR SECCFGR GPDMA secure configuration register 0x0 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 SEC%s SEC%s 0 1 read-write PRIVCFGR PRIVCFGR GPDMA privileged configuration register 0x4 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 PRIV%s PRIV%s 0 1 read-write RCFGLOCKR RCFGLOCKR GPDMA configuration lock register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 LOCK%s LOCK%s 0 1 read-write MISR MISR GPDMA non-secure masked interrupt status register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 MIS%s MIS%s 0 1 read-only SMISR SMISR GPDMA secure masked interrupt status register 0x10 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 MIS%s MIS%s 0 1 read-only 12 0x80 0-11 CH%s Channel cluster 0x50 LBAR C0LBAR GPDMA channel 0 linked-list base address register 0x0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write FCR C0FCR GPDMA channel 0 flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only SR C0SR GPDMA channel 0 status register 0x10 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.ENÂ =Â 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). 0 1 read-only TCF transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]). 8 1 read-only HTF half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2)) has been transferred to the destination. 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (see GPDMA_CxTR1.DDW_LOG2[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (GPDMA_CxSR.SUSPFÂ =Â 1). 16 8 read-only CR C0CR GPDMA channel 0 control register 0x14 0x20 0x00000000 0xFFFFFFFF EN enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 read-write RESET reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (GPDMA_CxSR.SUSPFÂ =Â 1 and GPDMA_CxSR.IDLEFÂ =Â GPDMA_CxCR.ENÂ =Â 1) - channel in disabled state (GPDMA_CxSR.IDLEFÂ =Â 1 and GPDMA_CxCR.ENÂ =Â 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR) before enabling again the channel (see the programming sequence in ). 1 1 write-only SUSP suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in . 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until GPDMA_CxBR1.BNDT[15:0]Â =Â 0 and GPDMA_CxBR1.BRC[10:0]Â =Â 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 read-write LAP linked-list allocated port This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others Note: This bit must be written when ENÂ =Â 0. This bit is read-only when ENÂ =Â 1. 22 2 read-write TR1 C0TR1 GPDMA channel 0 transfer register 1 0x40 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (GPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address GPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. 0 2 read-write SINC source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If SBL_1[5:0]Â =0Â , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed. 4 6 read-write PAM padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer - Case 2: If destination data width < source data width 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination Note: 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word If the source data width is shorter than a word, this bit is ignored. If the source data width is a word: 13 1 read-write SAP source allocated port This bit is used to allocate the master port for the source transfer Note: This bit must be written when ENÂ =Â 0. This bit is read-only when ENÂ =Â 1. 14 1 read-write SSEC security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECxÂ =Â 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECxÂ =1Â . A secure write is ignored when GPDMA_SECCFGR.SECxÂ =Â 0. When GPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure. 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0], versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and no transfer is issued. 16 2 read-write DINC destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If DBL_1[5:0]Â =0Â , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed. 20 6 read-write DBX destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte: 26 1 read-write DHX destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word: 27 1 read-write DAP destination allocated port This bit is used to allocate the master port for the destination transfer Note: This bit must be written when ENÂ =Â 0. This bit is read-only when ENÂ =Â 1. 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECxÂ =Â 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECxÂ =Â 1. A secure write is ignored when GPDMA_SECCFGR.SECxÂ =Â 0. When GPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure. 31 1 read-write TR2 C0TR2 GPDMA channel 0 transfer register 2 0x44 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQÂ =Â 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (GPDMA_CxCR.ENÂ =Â 1 and GPDMA_CxTR2.SWREQÂ =Â 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 read-write SWREQ software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted. 9 1 read-write DREQ destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQÂ =Â 1 (software request for a memory-to-memory transfer). Else: Note: 10 1 read-write BREQ Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQÂ =Â 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: 11 1 read-write TRIGM trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (GPDMA_CxCR.EN asserted) with TRIGPOL[1:0]Â =Â 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. â If the peripheral is programmed as a source (DREQÂ =Â 0) of the LLI data transfer, each programmed burst read is conditioned. â If the peripheral is programmed as a destination (DREQÂ =Â 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0]Â =Â 01 or respectively TRIGPOL[1:0]Â =Â 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (GPDMA_CxSR.TOFÂ =1Â ), and an interrupt is generated if enabled (GPDMA_CxCR.TOIEÂ =Â 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]Â =Â 11 and (SWREQÂ =1Â or (SWREQÂ =Â 0 and DREQÂ =0Â )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]Â =Â 11 and SWREQÂ =Â 0 and DREQÂ =Â 1), this shortened destination burst transfer is conditioned once by the trigger. 14 2 read-write TRIGSEL trigger event input selection These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0]Â â Â 00. 16 6 read-write TRIGPOL trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. 24 2 read-write TCEM transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]Â =Â 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]Â =Â 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]Â =0Â ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. 30 2 read-write BR1 C0BR1 GPDMA channel 0 block register 1 0x48 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64Â Kbytes -1. Once the last data transfer is completed (BNDT[15:0]Â =Â 0): - if GPDMA_CxLLR.UB1Â =Â 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1Â =Â 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.UxxÂ =Â 0 and if GPDMA_CxLLR.LA[15:0]Â =Â 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLRÂ =Â 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (GPDMA_CxTR1.PAM[1]Â =Â 1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 0 16 read-write SAR C0SAR GPDMA channel 0 source address register 0x4C 0x20 0x00000000 0xFFFFFFFF SA source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (GPDMA_CxTR1.SINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. During the channel activity, this address is updated after each completed source burst, consequently to: the programmed source burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.SINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.SBL_1[5:0] and GPDMA_CxTR1.SDW_LOG2[21:0] the additional source incremented/decremented offset value as programmed by GPDMA_CxBR1.SDEC and GPDMA_CxTR3.SAO[12:0] once/if completed source block transfer, for a channel x with 2D addressing capability (x = 12 to 15). additional block repeat source incremented/decremented offset value as programmed by GPDMA_CxBR1.BRSDEC and GPDMA_CxBR2.BRSAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.USAÂ =Â 1. Note: A source address must be aligned with the programmed data width of a source single (SA[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. When the source block size is not a multiple of the source burst size and is a multiple of the source data width, the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. 0 32 read-write DAR C0DAR GPDMA channel 0 destination address register 0x50 0x20 0x00000000 0xFFFFFFFF DA destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (GPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. During the channel activity, this address is updated after each completed destination burst, consequently to: the programmed destination burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.DINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.DBL_1[5:0] and GPDMA_CxTR1.DDW_LOG2[1:0] the additional destination incremented/decremented offset value as programmed by GPDMA_CxBR1.DDEC and GPDMA_CxTR3.DAO[12:0] once/if completed destination block transfer, for a channel x with 2D addressing capability (xÂ =Â 12Â toÂ 15), the additional block repeat destination incremented/decremented offset value as programmed by GPDMA_CxBR1.BRDDEC and GPDMA_CxBR2.BRDAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by the GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.UDAÂ =Â 1. Note: A destination address must be aligned with the programmed data width of a destination burst (DA[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 0 32 read-write LLR C0LLR GPDMA channel 0 linked-list address register 0x7C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure If UT1Â =Â UT2Â =Â UB1Â =Â USAÂ =Â UDAÂ =Â ULLÂ =Â 0 and if LA[15:20]Â =Â 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. 2 14 read-write ULL Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer. 16 1 read-write UDA Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer. 27 1 read-write USA update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer. 28 1 read-write UB1 Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during the link transfer. If UB1Â =Â 0 and if GPDMA_CxLLRÂ â Â 0, the linked-list is not completed. GPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 29 1 read-write UT2 Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer. 30 1 read-write UT1 Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer. 31 1 read-write 4 0x80 12-15 CH2D%s Extended channel cluster 0x650 LBAR C12LBAR GPDMA channel 12 linked-list base address register 0x0 FCR C12FCR GPDMA channel 12 flag clear register 0xC SR C12SR GPDMA channel 12 status register 0x10 CR C12CR GPDMA channel 12 control register 0x14 TR1 C12TR1 GPDMA channel 12 transfer register 1 0x40 TR2 C12TR2 GPDMA channel 12 transfer register 2 0x44 BR1 C12BR1 GPDMA channel 12 alternate block register 1 0x48 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64Â Kbytes -1. Once the last data transfer is completed (BNDT[15:0]Â =Â 0): - if GPDMA_CxLLR.UB1Â =Â 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1Â =Â 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.UxxÂ =Â 0 and if GPDMA_CxLLR.LA[15:0]Â â Â 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLRÂ =Â 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (GPDMA_CxTR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 0 16 read-write BRC Block repeat counter This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0]Â =Â BNDT[15:0]Â =Â 0): If GPDMA_CxLLR.UB1Â =Â 1, all GPDMA_CxBR1 fields are updated by the next LLI in the memory. If GPDMA_CxLLR.UB1Â =Â 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all GPDMA_CxLLR.UxxÂ =Â 0 and if GPDMA_CxLLR.LA[15:0]Â â Â 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if GPDMA_CxLLRÂ =Â 0, this field is kept as zero following the last LLI and data transfer. 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDEC), GPDMA_CxSAR is in the same time also updated by the increment/decrement (depending on SDEC) of the GPDMA_CxTR3.SAO value, as it is done after any programmed burst transfer. 30 1 read-write BRDDEC Block repeat destination address decrement Note: On top of this increment/decrement (depending on BRDDEC), GPDMA_CxDAR is in the same time also updated by the increment/decrement (depending on DDEC) of the GPDMA_CxTR3.DAO value, as it is usually done at the end of each programmed burst transfer. 31 1 read-write SAR C12SAR GPDMA channel 12 source address register 0x4C DAR C12DAR GPDMA channel 12 destination address register 0x50 TR3 C12TR3 GPDMA channel 12 transfer register 3 0x54 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (GPDMA_CxTR1.SINCÂ =Â 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. 0 13 read-write DAO destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (GPDMA_CxTR1.DINCÂ =Â 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 16 13 read-write BR2 C12BR2 GPDMA channel 12 block register 2 0x58 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 0 16 read-write BRDAO Block repeated destination address offset For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 16 16 read-write LLR C12LLR GPDMA channel 12 alternate linked-list address register 0x7C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure If UT1Â =Â UT2Â =Â UB1Â =Â USAÂ =Â UDAÂ =Â ULLÂ =Â 0 and if LA[15:20]Â =Â 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. 2 14 read-write ULL Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer. 16 1 read-write UB2 Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during the link transfer. 25 1 read-write UT3 Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during the link transfer. 26 1 read-write UDA Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer. 27 1 read-write USA update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer. 28 1 read-write UB1 Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during the link transfer. If UB1Â =Â 0 and if GPDMA_CxLLRÂ â Â 0, the linked-list is not completed. GPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 29 1 read-write UT2 Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer. 30 1 read-write UT1 Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer. 31 1 read-write SEC_GPDMA1 0x50020000 LPDMA1 LPDMA1 LPDMA 0x46025000 0x0 0x1000 registers LPDMA1_CH0 LPDMA1 SmartRun channel 0 global interrupt 114 LPDMA1_CH1 LPDMA1 SmartRun channel 1 global interrupt 115 LPDMA1_CH2 LPDMA1 SmartRun channel 2 global interrupt 116 LPDMA1_CH3 LPDMA1 SmartRun channel 3 global interrupt 117 SECCFGR SECCFGR LPDMA secure configuration register 0x0 0x20 0x00000000 0xFFFFFFFF 4 0x1 0-3 SEC%s SEC%s 0 1 read-write PRIVCFGR PRIVCFGR LPDMA privileged configuration register 0x4 0x20 0x00000000 0xFFFFFFFF 4 0x1 0-3 PRIV%s PRIV%s 0 1 read-write RCFGLOCKR RCFGLOCKR LPDMA configuration lock register 0x8 0x20 0x00000000 0xFFFFFFFF 4 0x1 0-3 LOCK%s LOCK%s 0 1 read-write MISR MISR LPDMA non-secure masked interrupt status register 0xC 0x20 0x00000000 0xFFFFFFFF 4 0x1 0-3 MIS%s MIS%s 0 1 read-only SMISR SMISR LPDMA secure masked interrupt status register 0x10 0x20 0x00000000 0xFFFFFFFF 4 0x1 0-3 MIS%s MIS%s 0 1 read-only 4 0x80 0-3 CH%s Cluster CH%s, containing C?LBAR, C?FCR, C?SR, C?CR, C?TR1, C?TR2, C?BR1, C?SAR, C?DAR, C?LLR 0x50 LBAR C0LBAR LPDMA channel 0 linked-list base address register 0x0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of LPDMA channel x 16 16 read-write FCR C0FCR LPDMA channel 0 flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only SR C0SR LPDMA channel 0 status register 0x10 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.ENÂ =Â 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). 0 1 read-only TCF transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode LPDMA_CxTR2.TCEM[1:0]. 8 1 read-only HTF half transfer flag An half transfer event is an half block transfer that occurs when half of the bytes of the source block size (rounded-up integer of LPDMA_CxBR1.BNDT[15:0]Â /Â 2) has been transferred to the destination. 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag clear 14 1 read-only CR C0CR LPDMA channel 0 control register 0x14 0x20 0x00000000 0xFFFFFFFF EN enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 read-write RESET reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (LPDMA_CxSR.SUSPFÂ =Â 1 and LPDMA_CxSR.IDLEFÂ =Â LPDMA_CxCR.ENÂ =Â 1) - channel in disabled state (LPDMA_CxSR.IDLEFÂ =Â 1 and LPDMA_CxCR.ENÂ =Â 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR) before enabling again the channel (see the programming sequence in ). 1 1 write-only SUSP suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in sequence. 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode First the block transfer is executed as defined by the current internal register file until LPDMA_CxBR1.BNDT[15:0Â ]Â =0). Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 read-write PRIO priority level of the channel x LPDMA transfer versus others Note: This bit must be written when ENÂ =Â 0. This bit is read-only when ENÂ =Â 1. 22 2 read-write TR1 C0TR1 LPDMA channel 0 transfer register 1 0x40 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. a source block size must be a multiple of the source data width (LPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address LPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. 0 2 read-write SINC source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a single transfer or is incremented by the offset value corresponding to a contiguous data after a single transfer. 3 1 read-write PAM padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination transfer is equal to the data width of a single source transfer, this bit is ignored. Else: Case 1: If destination data width > source data width Case 2: If destination data width < source data width 11 1 read-write SSEC security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECxÂ =Â 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECxÂ =1Â . A secure write is ignored when LPDMA_SECCFGR.SECxÂ =Â 0. When LPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure. 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination single transfer must have an aligned address with its data width (start address LPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and none transfer is issued. 16 2 read-write DINC destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant after a single transfer, or is incremented by the offset value corresponding to a contiguous data after a single transfer. 19 1 read-write DSEC security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECxÂ =Â 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECxÂ =Â 1. A secure write is ignored when LPDMA_SECCFGR.SECxÂ =Â 0. When LPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure. 31 1 read-write TR2 C0TR2 LPDMA channel 0 transfer register 2 0x44 0x20 0x00000000 0xFFFFFFFF REQSEL DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asserted) with SWREQÂ =Â 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per request. Note: The user must not assign a same input hardware request (same REQSEL[4:0] value) to different active DMA channels (LPDMA_CxCR.ENÂ =Â 1 and LPDMA_CxTR2.SWREQÂ =Â 0 for these channels). DMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 5 read-write SWREQ software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted. 9 1 read-write BREQ block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: 11 1 read-write TRIGM trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (LPDMA_CxCR.EN asserted) with TRIGPOL[1:0]Â =Â 0b00 or 0b11, these TRIGM[1:0] bits are ignored. Else, a DMA transfer is conditioned by at least one trigger hit: The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0]Â =Â 0b01 or respectively TRIGPOL[1:0]Â =Â 0b10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[4:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the LPDMA_CxTR2 with a new value for any of TRIGSEL[4:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized, and a trigger overrun flag is reported (LPDMA_CxSR.TOFÂ =Â 1), an interrupt is generated if enabled (LPDMA_CxCR.TOIEÂ =Â 1). The channel is not automatically disabled by hardware due to a trigger overrun. 14 2 read-write TRIGSEL trigger event input selection These bits select the trigger event input of the LPDMA transfer (as per Programmed LPDMA1 trigger), with an active trigger event if TRIGPOL[1:0]Â =Â 00. 16 5 read-write TRIGPOL trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0]. 24 2 read-write TCEM transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]Â =Â 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]Â =0Â ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. 30 2 read-write BR1 C0BR1 LPDMA channel 0 block register 1 0x48 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64Â Kbytes -1. Once the last data transfer is completed (BNDT[15:0]Â =Â 0): - if LPDMA_CxLLR.UB1Â =Â 1, this field is updated by the LLI in the memory. - if LPDMA_CxLLR.UB1Â =Â 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all LPDMA_CxLLR.UxxÂ =Â 0 and if LPDMA_CxLLR.LA[15:0]Â =Â 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if LPDMA_CxLLRÂ =Â 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 16 read-write SAR C0SAR LPDMA channel 0 source address register 0x4C 0x20 0x00000000 0xFFFFFFFF SA source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (LPDMA_CxTR1.SINC), this field is either kept fixed or incremented by the data width (LPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by LPDMA from the memory, provided the LLI is set with LPDMA_CxLLR.USAÂ =Â 1. Note: A source address must be aligned with the programmed data width of a source single (SA[32:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 0 32 read-write DAR C0DAR LPDMA channel 0 destination address register 0x50 0x20 0x00000000 0xFFFFFFFF DA destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (LPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (LPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by DMA from the memory, provided the LLI is set with LPDMA_CxLLR.UDAÂ =Â 1. Note: A destination address must be aligned with the programmed data width of a destination single (DA[2:0] versus LPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 0 32 read-write LLR C0LLR LPDMA channel 0 linked-list address register 0x7C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure If UT1Â =Â UT2Â =Â UB1Â =Â USAÂ =Â UDAÂ =Â ULLÂ =Â 0 and if LA[15:20]Â =Â 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file (LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. 2 14 read-write ULL Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR register from the memory during the link transfer. 16 1 read-write UDA Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR register from the memory during the link transfer. 27 1 read-write USA update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. 28 1 read-write UB1 Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. 29 1 read-write UT2 Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. 30 1 read-write UT1 Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. 31 1 read-write SEC_LPDMA1 0x56025000 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 59 CR1 CR1 0x0 0x20 0x00000000 0xFFFFFFFF SPE serial peripheral enable This bit is set by and cleared by software. When SPE=1, SPI data transfer is enabled, SPI_CFG1 and SPI_CFG2 configuration registers, CRCPOLY, UDRDR, part of SPI_AUTOCR register and IOLOCK bit in the SPI_CR1 register are write protected. They can be changed only when SPE=0. When SPE=0 any SPI operation is stopped and disabled, all the pending requests of the events with enabled interrupt are blocked except the MODF interrupt request (but their pending still propagates the request of the spi_plck clock), the SS output is deactivated at master, the RDY signal keeps not ready status at slave, the internal state machine is reseted, all the FIFOs content is flushed, CRC calculation initialized, receive data register is read zero. SPE is cleared and cannot be set when MODF error flag is active. 0 1 read-write SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 MASRX master automatic suspension in Receive mode This bit is set and cleared by software to control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. When SPI communication is suspended by hardware automatically, it could happen that few bits of next frame are already clocked out due to internal synchronization delay. This is why, the automatic suspension is not quite reliable when size of data drops below 8 bits. In this case, a safe suspension can be achieved by combination with delay inserted between data frames applied when MIDI parameter keeps a non zero value; sum of data size and the interleaved SPI cycles should always produce interval at length of 8 SPI clock periods at minimum. After software clearing of the SUSP bit, the communication resumes and continues by subsequent bits transaction without any next constraint. Prior the SUSP bit is cleared, the user must release the RxFIFO space as much as possible by reading out all the data packets available at RxFIFO based on the RXP flag indication to prevent any subsequent suspension. 8 1 read-write MASRX Disabled Automatic suspend in master receive-only mode disabled 0 Enabled Automatic suspend in master receive-only mode enabled 1 CSTART master transfer start This bit can be set by software if SPI is enabled only to start an SPI communication. it is cleared by hardware when end of transfer (EOT) flag is set or when a transaction suspend request is accepted. In SPI mode, the bit is taken into account at master mode only. If transmission is enabled, communication starts or continues only if any data is available in the transmission FIFO. 9 1 read-write CSTART NotStarted Do not start master transfer 0 Started Start master transfer 1 CSUSP master SUSPend request This bit reads as zero. In Master mode, when this bit is set by software, the CSTART bit is reset at the end of the current frame and SPI communication is suspended. The user has to check SUSP flag to check end of the frame transaction. The Master mode communication must be suspended (using this bit or keeping TXDR empty) before disabling the SPI or going to Low-power mode. After software suspension, SUSP flag has to be cleared and SPI disabled and re-enabled before the next transaction starts. 10 1 write-only CSUSPW NotRequested Do not request master suspend 0 Requested Request master suspend 1 HDDIR Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/Tx direction of the data transfer. This bit is ignored in Full-Duplex or any Simplex configuration. 11 1 read-write HDDIR Receiver Receiver in half duplex mode 0 Transmitter Transmitter in half duplex mode 1 SSI internal SS signal input level This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the peripheral SS input internally and the I/O value of the SS pin is ignored. 12 1 read-write SSI SlaveSelected 0 is forced onto the SS signal and the I/O value of the SS pin is ignored 0 SlaveNotSelected 1 is forced onto the SS signal and the I/O value of the SS pin is ignored 1 CRC33_17 32-bit CRC polynomial configuration 13 1 read-write CRC33_17 Disabled Full size (33/17 bit) CRC polynomial is not used 0 Enabled Full size (33/17 bit) CRC polynomial is used 1 RCRCINI CRC calculation initialization pattern control for receiver 14 1 read-write RCRCINI AllZeros All zeros RX CRC initialization pattern 0 AllOnes All ones RX CRC initialization pattern 1 TCRCINI CRC calculation initialization pattern control for transmitter 15 1 read-write TCRCINI AllZeros All zeros TX CRC initialization pattern 0 AllOnes All ones TX CRC initialization pattern 1 IOLOCK locking the AF configuration of associated IOs This bit is set by software and cleared by hardware whenever the SPE bit is changed from 1 to 0. When this bit is set, SPI_CFG2 register content cannot be modified. This bit can be set when SPI is disabled only else it is write protected. It is cleared and cannot be set when MODF bit is set. 16 1 read-write IOLOCK Unlocked IO configuration unlocked 0 Locked IO configuration locked 1 CR2 CR2 0x4 0x20 0x00000000 0xFFFFFFFF TSIZE number of data at current transfer When these bits are changed by software, the SPI has to be disabled. Endless transaction is initialized when CSTART is set while zero value is stored at TSIZE. TSIZE cannot be set to 0xFFFF respective 0x3FFF value when CRC is enabled. Note: TSIZE[15:10] bits are reserved at limited feature set instances and must be kept at reset value. 0 16 read-write 0 65535 CFG1 CFG1 SPI configuration register 1 0x8 0x20 0x00070007 0xFFFFFFFF DSIZE number of bits in at single SPI data frame ..... Note: Maximum data size can be limited up to 16-bits at some instances. At instances with limited set of features, DSIZE2:0] bits are reserved and must be kept at reset state. DSIZE[4:3] bits then control next settings of data size: 00xxx: 8-bits 01xxx: 16-bits 10xxx: 24-bits 11xxx: 32-bits. 0 5 read-write 0 31 FTHLV FIFO threshold level Defines number of data frames at single data packet. Size of the packet should not exceed 1/2 of FIFO space. SPI interface is more efficient if configured packet sizes are aligned with data register access parallelism: If SPI data register is accessed as a 16-bit register and DSIZE ÂÂ¤ 8 bit, better to select FTHLVÂ =Â 2, 4, 6. If SPI data register is accessed as a 32-bit register and DSIZE> 8 bit, better to select FTHLVÂ =Â 2, 4, 6, while if DSIZE ÂÂ¤Â 8bit, better to select FTHLVÂ =Â 4, 8, 12. Note: FTHLV[3:2] bits are reserved at instances with limited set of features 5 4 read-write FTHLV OneFrame 1 frame 0 TwoFrames 2 frames 1 ThreeFrames 3 frames 2 FourFrames 4 frames 3 FiveFrames 5 frames 4 SixFrames 6 frames 5 SevenFrames 7 frames 6 EightFrames 8 frames 7 NineFrames 9 frames 8 TenFrames 10 frames 9 ElevenFrames 11 frames 10 TwelveFrames 12 frames 11 ThirteenFrames 13 frames 12 FourteenFrames 14 frames 13 FifteenFrames 15 frames 14 SixteenFrames 16 frames 15 UDRCFG behavior of slave transmitter at underrun condition For more details see underrun condition. 9 1 read-write UDRCFG Constant Slave sends a constant underrun pattern 0 RepeatReceived Slave repeats last received data frame from master 1 RXDMAEN Rx DMA stream enable 14 1 read-write RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx DMA stream enable 15 1 read-write TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 CRCSIZE length of CRC frame to be transacted and compared Most significant bits are taken into account from polynomial calculation when CRC result is transacted or compared. The length of the polynomial is not affected by this setting. ..... The value must be set equal or multiply of data size (DSIZE[4:0]). Its maximum size corresponds to DSIZE maximum at the instance. Note: The most significant bit at CRCSIZE bit field is reserved at the peripheral instances where data size is limited to 16-bit. 16 5 read-write 0 31 CRCEN hardware CRC computation enable 22 1 read-write CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 MBR master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too (see mode). 28 3 read-write MBR Div2 f_spi_ker_ck / 2 0 Div4 f_spi_ker_ck / 4 1 Div8 f_spi_ker_ck / 8 2 Div16 f_spi_ker_ck / 16 3 Div32 f_spi_ker_ck / 32 4 Div64 f_spi_ker_ck / 64 5 Div128 f_spi_ker_ck / 128 6 Div256 f_spi_ker_ck / 256 7 BPASS bypass of the prescaler at master baud rate clock generator 31 1 read-write BPASS Disabled Bypass is disabled 0 Enabled Bypass is enabled 1 CFG2 CFG2 SPI configuration register 2 0xC 0x20 0x00000000 0xFFFFFFFF MSSI Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS opening a session and the beginning of the first data frame of the session in Master mode when SSOE is enabled. ... Note: This feature is not supported in TI mode. To include the delay, the SPI must be disabled and re-enabled between sessions. 0 4 read-write 0 15 MIDI master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in Master mode. ... Note: This feature is not supported in TI mode. 4 4 read-write 0 15 RDIOM RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero. 13 1 read-write RDIOM Active RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) 0 Pin RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) 1 RDIOP RDY signal input/output polarity 14 1 read-write RDIOP High high level of the signal means the slave is ready for communication 0 Low low level of the signal means the slave is ready for communication 1 IOSWP swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins alternate functions are inverted. Original MISO pin becomes MOSI and original MOSI pin becomes MISO. 15 1 read-write IOSWP Disabled MISO and MOSI not swapped 0 Enabled MISO and MOSI swapped 1 COMM SPI Communication Mode 17 2 read-write COMM FullDuplex Full duplex 0 Transmitter Simplex transmitter only 1 Receiver Simplex receiver only 2 HalfDuplex Half duplex 3 SP serial protocol others: reserved, must not be used 19 3 read-write SP Motorola Motorola SPI protocol 0 TI TI SPI protocol 1 MASTER SPI Master 22 1 read-write MASTER Slave Slave configuration 0 Master Master configuration 1 LSBFRST data frame format 23 1 read-write LSBFRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 CPHA clock phase 24 1 read-write CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CPOL clock polarity 25 1 read-write CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 SSM software management of SS signal input When master uses hardware SS output (SSM=0 and SSOE=1) the SS signal input is forced to not active state internally to prevent master mode fault error. 26 1 read-write SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSIOP SS input/output polarity 28 1 read-write SSIOP ActiveLow Low level is active for SS signal 0 ActiveHigh High level is active for SS signal 1 SSOE SS output enable This bit is taken into account in Master mode only 29 1 read-write SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 SSOM SS output management in Master mode This bit is taken into account in Master mode when SSOE is enabled. It allows the SS output to be configured between two consecutive data transfers. 30 1 read-write SSOM Asserted SS is asserted until data transfer complete 0 NotAsserted Data frames interleaved with SS not asserted during MIDI 1 AFCNTR alternate function GPIOs control This bit is taken into account when SPE=0 only When SPI has to be disabled temporary for a specific configuration reason (e.g. CRC reset, CPHA or HDDIR change) setting this bit prevents any glitches on the associated outputs configured at alternate function mode by keeping them forced at state corresponding the current SPI configuration. 31 1 read-write AFCNTR NotControlled Peripheral takes no control of GPIOs while disabled 0 Controlled Peripheral controls GPIOs while disabled 1 IER IER 0x10 0x20 0x00000000 0xFFFFFFFF RXPIE RXP interrupt enable 0 1 read-write RXPIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TXPIE TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event. 1 1 read-write DXPIE DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event. 2 1 read-write EOTIE EOT, SUSP and TXC interrupt enable 3 1 read-write TXTFIE TXTFIE interrupt enable 4 1 read-write UDRIE UDR interrupt enable 5 1 read-write OVRIE OVR interrupt enable 6 1 read-write CRCEIE CRC error interrupt enable 7 1 read-write TIFREIE TIFRE interrupt enable 8 1 read-write MODFIE mode Fault interrupt enable 9 1 read-write SR SR 0x14 0x20 0x00001002 0xFFFFFFFF RXP Rx-Packet available RXP flag is changed by hardware. It monitors number of overall data currently available at RxFIFO if SPI is enabled. It has to be checked once a data packet is completely read out from RxFIFO. 0 1 read-only RXP Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXP Tx-Packet space available TXP flag is changed by hardware. It monitors overall space currently available at TxFIFO no matter if SPI is enabled or not. It has to be checked once a complete data packet is stored at TxFIFO. 1 1 read-only TXP Full Tx buffer full 0 NotFull Tx buffer not full 1 DXP duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode. 2 1 read-only DXP Unavailable Duplex packet unavailable: no space for transmission and/or no data received 0 Available Duplex packet available: space for transmission and data received 1 EOT end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when TSIZE number of data have been transmitted and/or received on the SPI. EOT is cleared by software write 1 to EOTC bit at SPI_IFCR. EOT flag triggers an interrupt if EOTIE bit is set. If DXP flag is used until TXTF flag is set and DXPIE is cleared, EOT can be used to download the last packets contained into RxFIFO in one-shot. In master, EOT event terminates the data transaction and handles SS output optionally. When CRC is applied, the EOT event is extended over the CRC frame transaction. To restart the internal state machine properly, SPI is strongly suggested to be disabled and re-enabled before next transaction starts despite its setting is not changed. 3 1 read-only EOT NotCompleted Transfer ongoing or not started 0 Completed Transfer complete 1 TXTF transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transfer have been submitted for transmission by application software or DMA, that is when TSIZE number of data have been pushed into the TxFIFO. This bit is cleared by software write 1 to TXTFC bit at SPI_IFCR TXTF flag triggers an interrupt if TXTFIE bit is set. TXTF setting clears the TXPIE and DXPIE masks so to off-load application software from calculating when to disable TXP and DXP interrupts. 4 1 read-only TXTF NotCompleted Transmission buffer incomplete 0 Completed Transmission buffer filled with at least one transfer 1 UDR underrun at slave transmission mode This bit is cleared by writing 1 to UDRC bit at SPI_IFCR Note: UDR flag applies to Slave mode only 5 1 read-only UDR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 OVR overrun This bit is cleared by writing 1 to OVRC bit at SPI_IFCR 6 1 read-only OVR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 CRCE CRC error This bit is cleared by writing 1 to CRCEC bit at SPI_IFCR 7 1 read-only CRCE NoError No CRC error detected 0 Error CRC error detected 1 TIFRE TI frame format error This bit is cleared by writing 1 to TIFREC bit at SPI_IFCR 8 1 read-only TIFRE NoError TI frame format error detected 0 Error TI frame format error detected 1 MODF mode fault This bit is cleared by writing 1 to MODFC bit at SPI_IFCR 9 1 read-only MODF NoFault No mode fault detected 0 Fault Mode fault detected 1 SUSP suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is completed after CSUSP request is done or at master automatic suspend receive mode (MASRX bit is set at SPI_CR1 register) on RxFIFO full condition. SUSP generates an interrupt when EOTIE is set. This bit has to be cleared prior SPI is disabled by writing 1 to SUSPC bit at SPI_IFCR. 11 1 read-only SUSP NotSuspended Master not suspended 0 Suspended Master suspended 1 TXC TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE=0 the TXC is changed by hardware exclusively and it raises each time the TxFIFO becomes empty and there is no activity on the bus. If TSIZE <>0 there is no specific reason to monitor TXC as it just copies the EOT flag value including its software clearing. The TXC generates an interrupt when EOTIE is set. 12 1 read-only TXC Ongoing Transmission ongoing 0 Completed Transmission completed 1 RXPLVL RxFIFO packing level When RXWNE=0 and data size is set up to 16-bit, the value gives number of remaining data frames persisting at RxFIFO. Note: (*): Optional value when data size is set up to 8-bit only. When data size is greater than 16-bit, these bits are always read as 00. In that consequence, the single data frame received at the FIFO cannot be detected neither by RWNE nor by RXPLVL bits if data size is set from 17 to 24 bits. The user then must apply other methods like TSIZE>0 or FTHLV=0. 13 2 read-only RXPLVL ZeroFrames Zero frames beyond packing ratio available 0 OneFrame One frame beyond packing ratio available 1 TwoFrames Two frame beyond packing ratio available 2 ThreeFrames Three frame beyond packing ratio available 3 RXWNE RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with RXPLVL[1:0] information about RxFIFO occupancy by residual data. 15 1 read-only RXWNE LessThan32 Less than 32-bit data frame received 0 AtLeast32 At least 32-bit data frame received 1 CTSIZE number of data frames remaining in current TSIZE session The value is not quite reliable when traffic is ongoing on bus or during autonomous operation at low-power mode. Note: CTSIZE[15:0] bits are not available at instances with limited set of features 16 16 read-only 0 65535 IFCR IFCR 0x18 0x20 0x00000000 0xFFFFFFFF EOTC end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register 3 1 write-only oneToClear EOTCW Clear Clear interrupt flag 1 TXTFC transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR register 4 1 write-only oneToClear UDRC underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register 5 1 write-only oneToClear OVRC overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register 6 1 write-only oneToClear CRCEC CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register 7 1 write-only oneToClear TIFREC TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register 8 1 write-only oneToClear MODFC mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register 9 1 write-only oneToClear SUSPC SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register 11 1 write-only oneToClear AUTOCR AUTOCR 0x1C 0x20 0x00000000 0xFFFFFFFF TRIGSEL trigger selection (refer ). ... Note: these bits can be written only when SPEÂ =Â 0. 16 4 read-write TRIGPOL trigger polarity Note: This bit can be written only when SPEÂ =Â 0. 20 1 read-write TRIGPOL RaisingEdge trigger is active on raising edge 0 FallingEdge trigger is active on falling edge 1 TRIGEN trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled 21 1 read-write TRIGEN Disabled Hardware control disabled 0 Enabled Hardware control enabled 1 TXDR TXDR 0x20 0x20 0x00000000 0xFFFFFFFF TXDR transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFIFO. Note: data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is written by single access. halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be written by single access. word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be written by single access. Write access of this register less than the configured data size is forbidden. 0 32 write-only 0 4294967295 TXDR16 Direct 16-bit access to transmit data register TXDR 0x20 0x10 write-only TXDR Transmit data register 0 16 0 65535 TXDR8 Direct 8-bit access to transmit data register TXDR 0x20 0x8 write-only TXDR Transmit data register 0 8 0 255 RXDR RXDR 0x30 0x20 0x00000000 0xFFFFFFFF RXDR receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is accessed. Note: data is always right-aligned. Unused bits are read as zero when the register is read. Writing to the register is ignored. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is read by single access halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be read by single access word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be read by single access. Read access of this register less than the configured data size is forbidden. 0 32 read-only RXDR16 Direct 16-bit access to receive data register RXDR 0x30 0x10 read-only RXDR Receive data register 0 16 RXDR8 Direct 8-bit access to receive data register RXDR 0x30 0x8 read-only RXDR Receive data register 0 8 CRCPOLY CRCPOLY SPI polynomial register 0x40 0x20 0x00000107 0xFFFFFFFF CRCPOLY CRC polynomial register This register contains the polynomial for the CRC calculation. The default 9-bit polynomial setting 0x107 corresponds to default 8-bit setting of DSIZE. It is compatible with setting 0x07 used at some other ST products with fixed length of the polynomial string where the most significant bit of the string is always kept hidden. Length of the polynomial is given by the most significant bit of the value stored at this register. It has to be set greater than DSIZE. CRC33_17 bit has to be set additionally with CRCPOLY register when DSIZE is configured to maximum 32-bit or 16-bit size and CRC is enabled (to keep polynomial length grater than data size). Note: CRCPOLY[31:16] bits are reserved at instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 0 32 read-write 0 4294967295 TXCRC TXCRC 0x44 0x20 0x00000000 0xFFFFFFFF TXCRC CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the computed CRC value of the subsequently transmitted bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. Note: a read to this register when the communication is ongoing could return an incorrect value. Note: TXCRC[31-16] bits are reserved at instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. Note: The configuration of CRCSIZE bit field is not taken into account when the content of this register is read by software. No masking is applied for unused bits at this case. 0 32 read-only 0 4294967295 RXCRC RXCRC 0x48 0x20 0x00000000 0xFFFFFFFF RXCRC CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the computed CRC value of the subsequently received bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. Note: a read to this register when the communication is ongoing could return an incorrect value. RXCRC[31-16] bits are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. Note: The configuration of CRCSIZE bit field is not taken into account when the content of this register is read by software. No masking is applied for unused bits at this case. 0 32 read-only 0 4294967295 UDRDR UDRDR SPI underrun data register 0x4C 0x20 0x00000000 0xFFFFFFFF UDRDR data at slave underrun condition The register is taken into account in Slave mode and at underrun condition only. The number of bits considered depends on DSIZE bit settings of the SPI_CFG1 register. Underrun condition handling depends on setting UDRCFG bit at SPI_CFG1 register. Note: UDRDR[31-16] bits are reserved at the peripheral instances with data size limited to 16-bit. There is no constraint when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 0 32 read-write 0 4294967295 SEC_SPI1 0x50013000 SPI2 0x40003800 SPI2 SPI2 global interrupt 60 SEC_SPI2 0x50003800 SPI3 0x46002000 SPI3 SPI3 global interrupt 99 SEC_SPI3 0x56002000 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK TIM1 Break - transition error -index error 41 TIM1_UP TIM1 Update 42 TIM1_TRG_COM TIM1 Trigger and Commutation - direction change interrupt -index 43 TIM1_CC TIM1 Capture Compare interrupt 44 CR1 CR1 TIM1 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (tim_etr_in, tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS_3 Master mode selection 2 25 1 MMS2 Master mode selection 2 20 4 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 4 0x2 1-4 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 SMCR SMCR TIM1 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo or the tim_trgo2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write OCCS OCREF clear selection This bit is used to select the OCREF clear source. 3 1 read-write TS Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bitfield is combined with TS[4:3] bits. This bit-field selects the trigger input to be used to synchronize the counter. others: Reserved See for more details on tim_itrx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write MSM Master/slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be connected to tim_etrf in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo or the tim_trgo2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write TS2 Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bitfield is combined with TS[4:3] bits. This bit-field selects the trigger input to be used to synchronize the counter. others: Reserved See for more details on tim_itrx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write SMSPE SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded 24 1 read-write SMSPS SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active 25 1 read-write DIER DIER TIM1 DMA/interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 read-write COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write DIRIE Direction change interrupt enable 21 1 read-write IERRIE Index error interrupt enable 22 1 read-write TERRIE Transition error interrupt enable 23 1 read-write SR SR TIM1 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIMx_SMCR)(x = 1, 8)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag This flag is set by hardware on COM event (when capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 B2IF Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 8 1 read-write zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 SBIF System break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 13 1 read-write zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 CC5IF Compare 5 interrupt flag Refer to CC1IF description Note: Channel 5 can only be configured as output. 16 1 read-write zeroToClear read write CC6IF Compare 6 interrupt flag Refer to CC1IF description Note: Channel 6 can only be configured as output. 17 1 read-write zeroToClear read write IDXF Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by software by writing it to '0Ã¢ÂÂ. 20 1 read-write DIRF Direction change interrupt flag This flag is set by hardware when the direction changes in encoder mode (DIR bit value in TIMx_CR is changing). It is cleared by software by writing it to '0Ã¢ÂÂ. 21 1 read-write IERRF Index error interrupt flag This flag is set by hardware when an index error is detected. It is cleared by software by writing it to '0Ã¢ÂÂ. 22 1 read-write TERRF Transition error interrupt flag This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to '0Ã¢ÂÂ. 23 1 read-write EGR EGR TIM1 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 B2G Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 8 1 write-only B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input TIM1 capture/compare mode register 1 [alternate] CCMR1_Output 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0Ã¢ÂÂ in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0Ã¢ÂÂ in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input TIM1 capture/compare mode register 2 [alternate] CCMR2_Output 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0Ã¢ÂÂ in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0Ã¢ÂÂ in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCER CCER TIM1 capture/compare enable register 0x20 0x20 0x00000000 0xFFFFFFFF 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM1 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM1 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (ftim_cnt_ck) is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in Ã¢ÂÂreset modeÃ¢ÂÂ). 0 16 read-write 0 65535 ARR ARR TIM1 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 RCR RCR TIM1 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable. It also defines the update interrupt generation rate, if this interrupt is enable. When the repetition down-counter reaches zero, an update event is generated and it restarts counting from REP value. As the repetition counter is reloaded with REP value only at the repetition update event UEV, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode. 0 16 read-write 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 BDTR BDTR TIM1 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIMx_CCER)(x = 1, 8)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIMx_CCER)(x = 1, 8)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (tim_brk or tim_brk2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. enable register (TIMx_CCER)(x = 1, 8)). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample tim_brk input and the length of the digital filter applied to tim_brk. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write BK2F Break 2 filter This bit-field defines the frequency used to sample tim_brk2 input and the length of the digital filter applied to tim_brk2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 20 4 read-write BK2E Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: The BRKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 24 1 read-write BK2P Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 25 1 read-write BKDSRM Break disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write BK2DSRM Break2 disarm Refer to BKDSRM description 27 1 read-write BKBID Break bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write BK2BID Break2 bidirectional Refer to BKBID description 29 1 read-write CCR5 CCR5 capture/compare register 0x48 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 GC5C1 Group channel 5 and channel 1 Distortion on channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 29 1 read-write GC5C2 Group channel 5 and channel 2 Distortion on channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 30 1 read-write GC5C3 Group channel 5 and channel 3 Distortion on channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. 31 1 read-write CCR6 CCR6 capture/compare register 0x4C 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 CCMR3_Output CCMR3_Output TIM1 capture/compare mode register 3 0x50 0x20 0x00000000 0xFFFFFFFF 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 5-6 OC%sM Output compare %s mode 4 3 read-write 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write DTR2 DTR2 TIM1 timer deadtime register 2 0x54 0x20 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs, on the falling edge. DTGF[7:5]=0xx => DTF=DTGF[7:0]x tdtg with tdtg=tDTS. DTGF[7:5]=10x => DTF=(64+DTGF[5:0])xtdtg with Tdtg=2xtDTS. DTGF[7:5]=110 => DTF=(32+DTGF[4:0])xtdtg with Tdtg=8xtDTS. DTGF[7:5]=111 => DTF=(32+DTGF[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write DTAE Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 16 1 read-write DTPE Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 17 1 read-write ECR ECR TIM1 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable This bit indicates if the Index event resets the counter. 0 1 read-write IDIR Index direction This bit indicates in which direction the Index event resets the counter. Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled). 1 2 read-write IBLK Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input 3 2 read-write FIDX First index This bit indicates if the first index only is taken into account 5 1 read-write IPOS Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit indicates in which AB input configuration the Index event resets the counter. In directional clock mode or clock plus direction mode (SMS[3:0] = 1010, 1011, 1100, 1101), these bits indicates on which level the Index event resets the counter. In bidirectional clock mode, this applies for both clock inputs. x0: Index resets the counter when clock is 0 x1: Index resets the counter when clock is 1 Note: IPOS[1]Ã¢ÂÂbit is not significant 6 2 read-write PW Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG 16 8 read-write PWPRSC Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following: tPWG = (2(PWPRSC[2:0])) x ttim_ker_ck 24 3 read-write TISEL TISEL TIM1 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[0..15] input ... Refer to for interconnects list. 0 4 read-write TI2SEL Selects tim_ti2[0..15] input ... Refer to for interconnects list. 8 4 read-write TI3SEL Selects tim_ti3[0..15] input ... Refer to for interconnects list. 16 4 read-write TI4SEL Selects tim_ti4[0..15] input ... Refer to for interconnects list. 24 4 read-write AF1 AF1 TIM1 alternate function option register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timerÃ¢ÂÂs tim_brk input. TIMx_BKIN input is 'ORedÃ¢ÂÂ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKCMP1E tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timerÃ¢ÂÂs tim_brk input. tim_brk_cmp1 output is 'ORedÃ¢ÂÂ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP2E tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timerÃ¢ÂÂs tim_brk input. tim_brk_cmp2 output is 'ORedÃ¢ÂÂ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKCMP3E tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timerÃ¢ÂÂs tim_brk input. tim_brk_cmp3 output is 'ORedÃ¢ÂÂ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 3 1 read-write BKCMP4E tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timerÃ¢ÂÂs tim_brk input. tim_brk_cmp4 output is 'ORedÃ¢ÂÂ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 4 1 read-write BKCMP5E tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timerÃ¢ÂÂs tim_brk input. tim_brk_cmp5 output is 'ORedÃ¢ÂÂ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 5 1 read-write BKCMP6E tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timerÃ¢ÂÂs tim_brk input. tim_brk_cmp6 output is 'ORedÃ¢ÂÂ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 6 1 read-write BKCMP7E tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timerÃ¢ÂÂs tim_brk input. tim_brk_cmp7 output is 'ORedÃ¢ÂÂ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 7 1 read-write BKCMP8E tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timerÃ¢ÂÂs tim_brk input. tim_brk_cmp8 output is 'ORedÃ¢ÂÂ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BKINP TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 13 1 read-write ETRSEL etr_in source selection These bits select the etr_in input source. ... Refer to for product specific implementation. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 4 read-write AF2 AF2 TIM1 alternate function register 2 0x64 0x20 0x00000001 0xFFFFFFFF BK2INE TIMx_BKIN2 input enable This bit enables the TIMx_BKIN2 alternate function input for the timerÃ¢ÂÂs tim_brk2 input. TIMx_BKIN2 input is 'ORedÃ¢ÂÂ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BK2CMP1E tim_brk2_cmp1 enable This bit enables the tim_brk2_cmp1 for the timerÃ¢ÂÂs tim_brk2 input. tim_brk2_cmp1 output is 'ORedÃ¢ÂÂ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BK2CMP2E tim_brk2_cmp2 enable This bit enables the tim_brk2_cmp2 for the timerÃ¢ÂÂs tim_brk2 input. tim_brk2_cmp2 output is 'ORedÃ¢ÂÂ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BK2CMP3E tim_brk2_cmp3 enable This bit enables the tim_brk2_cmp3 for the timerÃ¢ÂÂs tim_brk2 input. tim_brk2_cmp3 output is 'ORedÃ¢ÂÂ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 3 1 read-write BK2CMP4E tim_brk2_cmp4 enable This bit enables the tim_brk2_cmp4 for the timerÃ¢ÂÂs tim_brk2 input. tim_brk2_cmp4 output is 'ORedÃ¢ÂÂ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 4 1 read-write BK2CMP5E tim_brk2_cmp5 enable This bit enables the tim_brk2_cmp5 for the timerÃ¢ÂÂs tim_brk2 input. tim_brk2_cmp5 output is 'ORedÃ¢ÂÂ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 5 1 read-write BK2CMP6E tim_brk2_cmp6 enable This bit enables the tim_brk2_cmp6 for the timerÃ¢ÂÂs tim_brk2 input. tim_brk2_cmp6 output is 'ORedÃ¢ÂÂ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 6 1 read-write BK2CMP7E tim_brk2_cmp7 enable This bit enables the tim_brk2_cmp7 for the timerÃ¢ÂÂs tim_brk2 input. tim_brk2_cmp7 output is 'ORedÃ¢ÂÂ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 7 1 read-write BK2CMP8E tim_brk2_cmp8 enable This bit enables the tim_brk2_cmp8 for the timerÃ¢ÂÂs tim_brk2 input. tim_brk2_cmp8 output is 'ORedÃ¢ÂÂ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BK2INP TIMx_BKIN2 input polarity This bit selects the TIMx_BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BK2CMP1P tim_brk2_cmp1 input polarity This bit selects the tim_brk2_cmp1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BK2CMP2P tim_brk2_cmp2 input polarity This bit selects the tim_brk2_cmp2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write BK2CMP3P tim_brk2_cmp3 input polarity This bit selects the tim_brk2_cmp3 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 12 1 read-write BK2CMP4P tim_brk2_cmp4 input polarity This bit selects the tim_brk2_cmp4 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 13 1 read-write OCRSEL ocref_clr source selection These bits select the ocref_clr input source. ... Refer to for product specific information. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 3 read-write DCR DCR TIM1 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data are copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data are transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data are also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write 0 18 DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Others: reserved 16 4 read-write DMAR DMAR TIM1 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write SEC_TIM1 0x50012C00 TIM8 0x40013400 TIM8_BRK TIM8 Break Interrupt 51 TIM8_UP TIM8 Update Interrupt 52 TIM8_TRG_COM TIM8 Trigger and Commutation Interrupt 53 TIM8_CC TIM8 Capture Compare Interrupt 54 SEC_TIM8 0x50013400 TIM2 General-purpose-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 45 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 DITHEN Dithering Enable 12 1 DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS_3 Master mode selection 25 1 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMSPS SMS preload source 25 1 SMSPE SMS preload enable 24 1 TS2 Trigger selection 20 2 SMS_3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TERRIE Transition error interrupt enable 23 1 IERRIE Index error interrupt enable 22 1 DIRIE Direction change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 TERRF Transition error interrupt flag 23 1 IERRF Index error interrupt flag 22 1 DIRF Direction change interrupt flag 21 1 IDXF Index interrupt flag 20 1 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Counter value 0 32 0 4294967295 UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR Auto-reload value 0 32 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 32 0 4294967295 ECR ECR encoder control register 0x58 0x20 read-write 0x00000000 PWPRSC Pulse width prescaler 24 3 PW Pulse width 16 8 IPOS Index positioning 6 2 FIDX First index 5 1 IBLK Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input 3 2 IDIR Index direction 1 2 IE Index enable 0 1 TISEL TISEL timer input selection register 0x5C 0x20 read-write 0x00000000 TI4SEL Selects tim_ti4[0..15] input 24 4 TI3SEL Selects tim_ti3[0..15] input 16 4 TI2SEL Selects tim_ti2[0..15] input 8 4 TI1SEL Selects tim_ti1[0..15] input 0 4 AF1 AF1 alternate function register 1 0x60 0x20 read-write 0x00000000 ETRSEL etr_in source selection 14 4 AF2 AF2 alternate function register 2 0x64 0x20 read-write 0x00000000 OCRSEL ocref_clr source selection 16 3 DCR DCR DMA control register 0x3DC 0x20 read-write 0x00000000 DBSS DMA burst source selection 16 4 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 ETRSEL DMA register for burst accesses 0 32 SEC_TIM2 0x50000000 TIM3 0x40000400 TIM3 TIM3 global interrupt 46 SEC_TIM3 0x50000400 TIM4 0x40000800 TIM4 TIM4 global interrupt 47 SEC_TIM4 0x50000800 TIM5 0x40000C00 TIM5 TIM5 global interrupt 48 SEC_TIM5 0x50000C00 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers TIM15 TIM15 global interrupt 69 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 DITHEN Dithering enable 12 1 DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 2 0x2 1-2 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 2 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 TS2 Trigger selection 20 2 SMS_3 Slave mode selection 16 1 CC1DE Capture/Compare 1 DMA request enable 9 1 MSM Master/slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 2 0x1 1-2 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 0x00000000 BG Break generation 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 TG Trigger generation 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 read-write COMGW write Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 CNT CNT counter 0x24 0x20 0x00000000 UIFCPY UIF Copy 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 20 0 1048575 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 8 0 255 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 20 0 1048575 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 BKF Break filter 16 4 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 DTG Dead-time generator setup 0 8 0 255 DTR2 DTR2 timer deadtime register 2 0x54 0x20 read-write 0x00000000 DTPE Deadtime preload enable 17 1 DTAE Deadtime asymmetric enable 16 1 DTGF Dead-time falling edge generator setup 0 8 TISEL TISEL input selection register 0x5C 0x20 read-write 0x00000000 TI2SEL selects tim_ti2_in[0..15] input 8 4 TI1SEL selects tim_ti1_in[0..15] input 0 4 AF1 AF1 alternate function register 1 0x60 0x20 read-write 0x00000000 BKCMP4P tim_brk_cmp4 input polarity 13 1 BKCMP3P tim_brk_cmp3 input polarity 12 1 BKCMP2P tim_brk_cmp2 input polarity 11 1 BKCMP1P tim_brk_cmp1 input polarity 10 1 BKINP TIMx_BKIN input polarity 9 1 BKCMP7E tim_brk_cmp7 enable 7 1 BKCMP6E tim_brk_cmp6 enable 6 1 BKCMP5E tim_brk_cmp5 enable 5 1 BKCMP4E tim_brk_cmp4 enable 4 1 BKCMP3E tim_brk_cmp3 enable 3 1 BKCMP2E tim_brk_cmp2 enable 2 1 BKCMP1E tim_brk_cmp1 enable 1 1 BKINE TIMx_BKIN input enable 0 1 AF2 AF2 alternate function register 2 0x64 0x20 read-write 0x00000001 OCRSEL ocref_clr source selection 16 3 DCR DCR DMA control register 0x3DC 0x20 read-write 0x00000000 DBSS DMA burst source selection 16 4 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 SEC_TIM15 0x50014000 TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global interrupt 70 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 DITHEN Dithering Enable 12 1 DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 DIER DIER DMA/interrupt enable register 0xC 0x20 read-write 0x00000000 COMDE COM DMA request enable 13 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 1 0x0 1-1 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 1 0x0 1-1 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 0x00000000 UIFCPY UIF Copy 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 CNT CNT 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 20 0 1048575 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 8 0 255 1 0x4 1-1 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 20 0 1048575 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 DTG Dead-time generator setup 0 8 0 255 DTR2 DTR2 timer deadtime register 2 0x54 0x20 read-write 0x00000000 DTPE Deadtime preload enable 17 1 DTAE Deadtime asymmetric enable 16 1 DTGF Deadtime asymmetric enable 0 8 TISEL TISEL TIM17 option register 1 0x5C 0x20 read-write 0x00000000 TI1SEL selects tim_ti1_in[0..15] input 0 4 AF1 AF1 alternate function register 1 0x60 0x20 read-write 0x00000001 BKCMP4P tim_brk_cmp4 input polarity 13 1 BKCMP3P tim_brk_cmp3 input polarity 12 1 BKCMP2P tim_brk_cmp2 input polarity 11 1 BKCMP1P tim_brk_cmp1 input polarity 10 1 BKINP TIMx_BKIN input polarity 9 1 BKCMP7E tim_brk_cmp7 enable 7 1 BKCMP6E tim_brk_cmp6 enable 6 1 BKCMP5E tim_brk_cmp5 enable 5 1 BKCMP4E tim_brk_cmp4 enable 4 1 BKCMP3E tim_brk_cmp3 enable 3 1 BKCMP2E tim_brk_cmp2 enable 2 1 BKCMP1E tim_brk_cmp1 enable 1 1 BKINE TIMx_BKIN input enable 0 1 AF2 AF2 alternate function register 2 0x64 0x20 read-write 0x00000001 OCRSEL tim_ocref_clr source selection 16 3 DCR DCR DMA control register 0x3DC 0x20 read-write 0x00000001 DBSS DMA burst source selection 16 4 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR TIM17 option register 1 0x3E0 0x20 read-write 0x00000001 DMAB DMA register for burst accesses 0 32 SEC_TIM16 0x50014400 TIM17 0x40014800 TIM17 TIM17 global interrupt 71 SEC_TIM17 0x50014800 TIM6 General-purpose-timers TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 global interrupt 49 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 DITHEN Dithering Enable 12 1 DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS Master mode selection 4 3 MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 UDE UDE 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 UIE UIE 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 UIF UIF 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 UG UG 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 UIFCPY UIFCPY 31 1 UIFCPYR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 CNT CNT 0 16 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC PSC 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR ARR 0 20 0 1048575 SEC_TIM6 0x50001000 TIM7 0x40001400 TIM7 TIM7 global interrupt 50 SEC_TIM7 0x50001400 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR Control register 0x0 0x10 read-write 0x0000007F WDGA Activation bit 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 T 7-bit counter (MSB to LSB) 0 7 0 127 CFR CFR Configuration register 0x4 0x10 read-write 0x0000007F WDGTB Timer base 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 Div16 Counter clock (PCLK1 div 4096) div 16 4 Div32 Counter clock (PCLK1 div 4096) div 32 5 Div64 Counter clock (PCLK1 div 4096) div 64 6 Div128 Counter clock (PCLK1 div 4096) div 128 7 EWI Early wakeup interrupt 9 1 EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 W 7-bit window value 0 7 0 127 SR SR Status register 0x8 0x10 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 SEC_WWDG 0x50002C00 SYSCFG System configuration controller SYSCFG 0x46000400 0x0 0x400 registers SECCFGR SECCFGR SYSCFG secure configuration register 0x0 0x20 read-write 0x00000000 SYSCFGSEC SYSCFG clock control security 0 1 CLASSBSEC CLASSBSEC 1 1 FPUSEC FPUSEC 3 1 CFGR1 CFGR1 configuration register 1 0x4 0x20 read-write 0x00000000 PB9_FMP PB9_FMP 19 1 PB8_FMP PB8_FMP 18 1 PB7_FMP PB7_FMP 17 1 PB6_FMP PB6_FMP 16 1 ANASWVDD GPIO analog switch control voltage selection 9 1 BOOSTEN I/O analog switch voltage booster enable 8 1 FPUIMR FPUIMR FPU interrupt mask register 0x8 0x20 read-write 0x0000001F FPU_IE Floating point unit interrupts enable bits 0 6 CNSLCKR CNSLCKR SYSCFG CPU non-secure lock register 0xC 0x20 read-write 0x00000000 LOCKNSVTOR VTOR_NS register lock 0 1 LOCKNSMPU Non-secure MPU registers lock 1 1 CSLOCKR CSLOCKR SYSCFG CPU secure lock register 0x10 0x20 read-write 0x00000000 LOCKSVTAIRCR LOCKSVTAIRCR 0 1 LOCKSMPU LOCKSMPU 1 1 LOCKSAU LOCKSAU 2 1 CFGR2 CFGR2 configuration register 2 0x14 0x20 read-write 0x00000000 ECCL ECC Lock 3 1 PVDL PVD lock enable bit 2 1 SPL SRAM ECC lock bit 1 1 CLL LOCKUP (hardfault) output enable bit 0 1 MESR MESR memory erase status register 0x18 0x20 read-write 0x00000000 IPMEE IPMEE 16 1 MCLR MCLR 0 1 CCCSR CCCSR compensation cell control/status register 0x1C 0x20 0x0000000A EN1 EN1 0 1 read-write CS1 CS1 1 1 read-write EN2 EN2 2 1 read-write CS2 CS2 3 1 read-write RDY1 RDY1 8 1 read-only RDY2 RDY2 9 1 read-only CCVR CCVR compensation cell value register 0x20 0x20 read-only 0x00000000 NCV1 NCV1 0 4 PCV1 PCV1 4 4 NCV2 NCV2 8 4 PCV2 PCV2 12 4 CCCR CCCR compensation cell code register 0x24 0x20 read-write 0x00007878 NCC1 NCC1 0 4 PCC1 PCC1 4 4 NCC2 NCC2 8 4 PCC2 PCC2 12 4 RSSCMDR RSSCMDR RSS command register 0x2C 0x20 read-write 0x00000000 RSSCMD RSS commands 0 16 UCPDR UCPDR USB Type C and Power Delivery register 0x70 0x20 read-write 0x00000000 CC1ENRXFILTER CC1ENRXFILTER 0 1 CC2ENRXFILTER CC2ENRXFILTER 1 1 SEC_SYSCFG 0x56000400 PKA Private key accelerator PKA 0x420C2000 0x0 0x2000 registers PKA PKA global interrupt 97 CR CR Control register 0x0 0x20 read-write 0x00000000 OPERRIE Operation error interrupt enable 21 1 ADDRERRIE Address error interrupt enable 20 1 RAMERRIE RAM error interrupt enable 19 1 PROCENDIE End of operation interrupt enable 17 1 MODE PKA Operation Mode 8 6 START Start the operation 1 1 EN Peripheral Enable 0 1 SR SR PKA status register 0x4 0x20 read-only 0x00000000 INITOK INITOK 0 1 BUSY PKA operation is in progress 16 1 PROCENDF PKA End of Operation flag 17 1 RAMERRF RAMERRF 19 1 ADDRERRF ADDRERRF 20 1 OPERRF OPERRF 21 1 CLRFR CLRFR PKA clear flag register 0x8 0x20 write-only 0x00000000 PROCENDFC Clear PKA End of Operation flag 17 1 RAMERRFC RAMERRFC 19 1 ADDRERRFC ADDRERRFC 20 1 OPERRFC OPERRFC 21 1 SEC_PKA 0x520C2000 DBGMCU MCU debug component DBGMCU 0xE0044000 0x0 0x1000 registers IDCODE IDCODE DBGMCU_IDCODE 0x0 0x20 read-only 0x30016482 DEV_ID Device dentification 0 12 REV_ID Revision 16 16 CR CR Debug MCU configuration register 0x4 0x20 read-write 0x00000000 DBG_STOP Debug Stop mode 1 1 DBG_STANDBY Debug Standby mode 2 1 TRACE_IOEN Trace pin assignment control 4 1 TRACE_EN trace port and clock enable 5 1 TRACE_MODE Trace pin assignment control 6 2 APB1LFZR APB1LFZR Debug MCU APB1L peripheral freeze register 0x8 0x20 read-write 0x00000000 DBG_TIM2_STOP TIM2 stop in debug 0 1 DBG_TIM3_STOP TIM3 stop in debug 1 1 DBG_TIM4_STOP TIM4 stop in debug 2 1 DBG_TIM5_STOP TIM5 stop in debug 3 1 DBG_TIM6_STOP TIM6 stop in debug 4 1 DBG_TIM7_STOP TIM7 stop in debug 5 1 DBG_WWDG_STOP Window watchdog counter stop in debug 11 1 DBG_IWDG_STOP Independent watchdog counter stop in debug 12 1 DBG_I2C1_STOP I2C1 SMBUS timeout stop in debug 21 1 DBG_I2C2_STOP I2C2 SMBUS timeout stop in debug 22 1 APB1HFZR APB1HFZR Debug MCU APB1H peripheral freeze register 0xC 0x20 read-write 0x00000000 DBG_I2C4_STOP I2C4 stop in debug 1 1 DBG_LPTIM2_STOP LPTIM2 stop in debug 5 1 APB2FZR APB2FZR Debug MCU APB2 peripheral freeze register 0x10 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM8_STOP TIM8 stop in debug 13 1 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM17_STOP DBG_TIM17_STOP 18 1 APB3FZR APB3FZR Debug MCU APB3 peripheral freeze register 0x14 0x20 read-write 0x00000000 DBG_I2C3_STOP I2C3 stop in debug 10 1 DBG_LPTIM1_STOP LPTIM1 stop in debug 17 1 DBG_LPTIM3_STOP LPTIM3 stop in debug 18 1 DBG_LPTIM4_STOP LPTIM4 stop in debug 19 1 DBG_RTC_STOP RTC stop in debug 30 1 AHB1FZR AHB1FZR Debug MCU AHB1 peripheral freeze register 0x20 0x20 read-write 0x00000000 DBG_GPDMA0_STOP GPDMA channel 0 stop in debug 0 1 DBG_GPDMA1_STOP GPDMA channel 1 stop in debug 1 1 DBG_GPDMA2_STOP GPDMA channel 2 stop in debug 2 1 DBG_GPDMA3_STOP GPDMA channel 3 stop in debug 3 1 DBG_GPDMA4_STOP GPDMA channel 4 stop in debug 4 1 DBG_GPDMA5_STOP GPDMA channel 5 stop in debug 5 1 DBG_GPDMA6_STOP GPDMA channel 6 stop in debug 6 1 DBG_GPDMA7_STOP GPDMA channel 7 stop in debug 7 1 DBG_GPDMA8_STOP GPDMA channel 8 stop in debug 8 1 DBG_GPDMA9_STOP GPDMA channel 9 stop in debug 9 1 DBG_GPDMA10_STOP GPDMA channel 10 stop in debug 10 1 DBG_GPDMA11_STOP GPDMA channel 11 stop in debug 11 1 DBG_GPDMA12_STOP GPDMA channel 12 stop in debug 12 1 DBG_GPDMA13_STOP GPDMA channel 13 stop in debug 13 1 DBG_GPDMA14_STOP GPDMA channel 14 stop in debug 14 1 DBG_GPDMA15_STOP GPDMA channel 15 stop in debug 15 1 AHB3FZR AHB3FZR Debug MCU AHB3 peripheral freeze register 0x28 0x20 read-write 0x00000000 DBG_LPDMA0_STOP LPDMA channel 0 stop in debug 0 1 DBG_LPDMA1_STOP LPDMA channel 1 stop in debug 1 1 DBG_LPDMA2_STOP LPDMA channel 2 stop in debug 2 1 DBG_LPDMA3_STOP LPDMA channel 3 stop in debug 3 1 DBGMCU_SR DBGMCU_SR DBGMCU status register 0xFC 0x20 read-only 0x00000001 AP_PRESENT Bit n identifies whether access port AP n is present in device Bit nÂ =Â 0: APn absent Bit nÂ =Â 1: APn present 0 8 AP_LOCKED DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) Bit nÂ =Â 0: APn locked Bit nÂ =Â 1: APn enabled 8 8 DBGMCU_DBG_AUTH_HOST DBGMCU_DBG_AUTH_HOST DBGMCU debug host authentication register 0x100 0x20 read-only 0x00000000 AUTH_KEY Device authentication key The device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory. 0 32 DBGMCU_DBG_AUTH_DEVICE DBGMCU_DBG_AUTH_DEVICE DBGMCU debug device authentication register 0x104 0x20 read-only 0x00000000 AUTH_ID Device specific ID Device specific ID used for RDP regression. 0 32 PIDR4 PIDR4 Debug MCU CoreSight peripheral identity register 4 0xFD0 0x20 read-only 0x00000000 JEP106CON JEP106 continuation code 0 4 KCOUNT_4 register file size 4 4 PIDR0 PIDR0 Debug MCU CoreSight peripheral identity register 0 0xFE0 0x20 read-only 0x00000000 PARTNUM part number bits [7:0] 0 8 PIDR1 PIDR1 Debug MCU CoreSight peripheral identity register 1 0xFE4 0x20 read-only 0x00000000 PARTNUM part number bits [11:8] 0 4 JEP106ID JEP106 identity code bits [3:0] 4 4 PIDR2 PIDR2 Debug MCU CoreSight peripheral identity register 2 0xFE8 0x20 read-only 0x0000000A JEP106ID JEP106 identity code bits [6:4] 0 3 JEDEC JEDEC assigned value 3 1 REVISION component revision number 4 4 PIDR3 PIDR3 Debug MCU CoreSight peripheral identity register 3 0xFEC 0x20 read-only 0x00000000 CMOD customer modified 0 4 REVAND metal fix version 4 4 CIDR0 CIDR0 Debug MCU CoreSight component identity register 0 0xFF0 0x20 read-only 0x0000000D PREAMBLE component identification bits [7:0] 0 8 CIDR1 CIDR1 Debug MCU CoreSight component identity register 1 0xFF4 0x20 read-only 0x000000F0 PREAMBLE component identification bits [11:8] 0 4 CLASS component identification bits [15:12] - component class 4 4 CIDR2 CIDR2 Debug MCU CoreSight component identity register 2 0xFF8 0x20 read-only 0x00000005 PREAMBLE component identification bits [23:16] 0 8 CIDR3 CIDR3 Debug MCU CoreSight component identity register 3 0xFFC 0x20 read-only 0x000000B1 PREAMBLE component identification bits [31:24] 0 8 OCTOSPI1 OctoSPI OctoSPI 0x420D1400 0x0 0x400 registers OCTOSPI1 OCTOSPI1 global interrupt 76 CR CR control register 0x0 0x20 read-write 0x00000000 FMODE Functional mode 28 2 FMODE IndirectWrite Indirect-write mode 0 IndirectRead Indirect-read mode 1 AutomaticPolling Automatic status-polling mode 2 MemoryMapped Memory-mapped mode 3 PMM Polling match mode 23 1 PMM ANDMatchMode AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register 0 ORMatchmode OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register 1 APMS Automatic poll mode stop 22 1 APMS Running Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI 0 StopMatch Automatic status-polling mode stops as soon as there is a match 1 TEIE Transfer error interrupt enable 16 1 TEIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TOIE TimeOut interrupt enable 20 1 SMIE Status match interrupt enable 19 1 FTIE FIFO threshold interrupt enable 18 1 TCIE Transfer complete interrupt enable 17 1 FTHRES FIFO threshold level 8 5 0 31 MSEL External memory select 7 1 MSEL EXT1 External memory 1 selected (data exchanged over IO[3:0]) 0 EXT2 External memory 2 selected (data exchanged over IO[7:4]) 1 DMM Dual-memory configuration 6 1 DMM Disabled Dual-memory configuration disabled 0 Enabled Dual-memory configuration enabled 1 TCEN Timeout counter enable 3 1 TCEN Disabled Timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in Memory-mapped mode 0 Enabled Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity 1 DMAEN DMA enable 2 1 DMAEN Disabled DMA disabled for Indirect mode 0 Enabled DMA enabled for Indirect mode 1 ABORT Abort request 1 1 ABORT NotRequested No abort requested 0 Requested Abort requested 1 EN Enable 0 1 EN Disabled OCTOSPI disabled 0 Enabled OCTOSPI enabled 1 DCR1 DCR1 device configuration register 1 0x8 0x20 read-write 0x00000000 CKMODE Mode 0 / mode 3 0 1 CKMODE Mode0 CLK must stay low while NCS is high (chip-select released). This is referred to as Mode 0 0 Mode3 CLK must stay high while NCS is high (chip-select released). This is referred to as Mode 3 1 FRCK Free running clock 1 1 FRCK Disabled CLK is not free running 0 Enabled CLK is free running (always provided) 1 DLYBYP Delay block bypass 3 1 DLYBYP DelayBlockEnabled The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral) 0 DelayBlockBypassed The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. The delay is shorter than when the delay block is not bypassed, even with the delay value set to minimum value in delay block 1 CSHT Chip-select high time 8 6 0 63 DEVSIZE Device size 16 5 0 31 MTYP Memory type 24 3 MTYP MicronMode Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes 0 MacronixMode Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes 1 StandardMode Standard Mode 2 MacronixRamMode Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping 3 HyperBusMemoryMode HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected 4 HyperBusMode HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used 5 DCR2 DCR2 device configuration register 2 0xC 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 8 0 255 WRAPSIZE Wrap size 16 3 WRAPSIZE NoWrappingSupport Wrapped reads are not supported by the memory 0 WrappingSize16 External memory supports wrap size of 16 bytes 2 WrappingSize32 External memory supports wrap size of 32 bytes 3 WrappingSize64 External memory supports wrap size of 64 bytes 4 WrappingSize128 External memory supports wrap size of 128 bytes 5 DCR3 DCR3 device configuration register 3 0x10 0x20 read-write 0x00000000 MAXTRAN Maximum transfer 0 8 0 255 CSBOUND CS boundary 16 5 0 31 DCR4 DCR4 DCR4 0x14 0x20 read-write 0x00000000 REFRESH Refresh rate 0 32 0 4294967295 SR SR status register 0x20 0x20 read-only 0x00000000 TEF Transfer error flag 0 1 TEF Cleared This bit is cleared by writing 1 to CTEF 0 InvalidAddressAccessed This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode 1 TCF transfer complete flag 1 1 TCF Cleared This bit is cleared by writing 1 to CTCF 0 TransferCompleted This bit is set when the programmed number of data has been transferred 1 FTF FIFO threshold flag 2 1 FTF Cleared It is cleared automatically as soon as the threshold condition is no longer true 0 ThresholdReached This bit is set when the FIFO threshold has been reached 1 SMF status match flag 3 1 SMF Cleared It is cleared by writing 1 to CSMF 0 Matched This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (OCTOSPI_PSMAR) 1 TOF timeout flag 4 1 TOF Cleared This bit is cleared by writing 1 to CTOF 0 Timeout This bit is set when timeout occurs 1 BUSY BUSY 5 1 BUSY Cleared This bit is cleared automatically when the operation with the external device is finished and the FIFO is empty 0 Busy This bit is set when an operation is ongoing 1 FLEVEL FIFO level 8 6 0 63 FCR FCR flag clear register 0x24 0x20 write-only 0x00000000 CTEF Clear Transfer error flag 0 1 CTEF Clear Writing 1 clears the TEF flag in the OCTOSPI_SR register 1 CTCF Clear transfer complete flag 1 1 CTCF Clear Writing 1 clears the TCF flag in the OCTOSPI_SR register 1 CSMF Clear status match flag 3 1 CSMF Clear Writing 1 clears the SMF flag in the OCTOSPI_SR register 1 CTOF Clear timeout flag 4 1 CTOF Clear Writing 1 clears the TOF flag in the OCTOSPI_SR register 1 DLR DLR data length register 0x40 0x20 read-write 0x00000000 DL Data length 0 32 0 4294967295 AR AR address register 0x48 0x20 read-write 0x00000000 ADDRESS ADDRESS 0 32 0 4294967295 DR DR data register 0x50 0x20 read-write 0x00000000 DATA DATA 0 32 0 4294967295 PSMKR PSMKR polling status mask register 0x80 0x20 read-write 0x00000000 MASK Status MASK 0 32 0 4294967295 PSMAR PSMAR polling status match register 0x88 0x20 read-write 0x00000000 MATCH Status match 0 32 0 4294967295 PIR PIR polling interval register 0x90 0x20 read-write 0x00000000 INTERVAL polling interval 0 16 0 65535 CCR CCR communication configuration register 0x100 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR Instruction double transfer rate 3 1 IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE Instruction size 4 2 ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE Address mode 8 3 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR Address double transfer rate 11 1 ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE Address size 12 2 ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE Alternate byte mode 16 3 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR Alternate bytes double transfer rate 19 1 ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE Alternate bytes size 20 2 ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE Data mode 24 3 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR Alternate bytes double transfer rate 27 1 DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQS enable 29 1 DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 SIOO Send instruction only once mode 31 1 SIOO SendEveryTransaction Send instruction on every transaction 0 SendOnlyFirstCmd Send instruction only for the first command 1 TCR TCR timing configuration register 0x108 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 0 31 DHQC Delay hold quarter cycle 28 1 DHQC NoDelay No delay hold 0 QuarterCycleHold 1/4 cycle hold 1 SSHIFT Sample shift 30 1 SSHIFT NoShift No shift 0 HalfCycleShift 1/2 cycle shift 1 IR IR instruction register 0x110 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 0 4294967295 ABR ABR alternate bytes register 0x120 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 0 4294967295 LPTR LPTR low-power timeout register 0x130 0x20 read-write 0x00000000 TIMEOUT Timeout period 0 16 0 65535 WPCCR WPCCR wrap communication configuration register 0x140 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR Instruction double transfer rate 3 1 IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE Instruction size 4 2 ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE Address mode 8 3 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR Address double transfer rate 11 1 ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE Address size 12 2 ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE Alternate byte mode 16 3 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR Alternate bytes double transfer rate 19 1 ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE Alternate bytes size 20 2 ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE Data mode 24 3 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR alternate bytes double transfer rate 27 1 DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQS enable 29 1 DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 WPTCR WPTCR wrap timing configuration register 0x148 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 0 31 DHQC Delay hold quarter cycle 28 1 DHQC NoDelay No delay hold 0 QuarterCycleHold 1/4 cycle hold 1 SSHIFT Sample shift 30 1 SSHIFT NoShift No shift 0 HalfCycleShift 1/2 cycle shift 1 WPIR WPIR wrap instruction register 0x150 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 0 4294967295 WPABR WPABR wrap alternate bytes register 0x160 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 0 4294967295 WCCR WCCR write communication configuration register 0x180 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR Instruction double transfer rate 3 1 IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE Instruction size 4 2 ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE Address mode 8 3 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR Address double transfer rate 11 1 ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE Address size 12 2 ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE Alternate byte mode 16 3 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR Alternate bytes double transfer rate 19 1 ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE Alternate bytes size 20 2 ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE Data mode 24 3 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR alternate bytes double transfer rate 27 1 DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQS enable 29 1 DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 WTCR WTCR write timing configuration register 0x188 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 0 31 WIR WIR write instruction register 0x190 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 0 4294967295 WABR WABR write alternate bytes register 0x1A0 0x20 read-write 0x00000000 ALTERNATE ALTERNATE 0 32 0 4294967295 HLCR HLCR HyperBus latency configuration register 0x200 0x20 read-write 0x00000000 LM Latency mode 0 1 LM Variable Variable initial latency 0 Fixed Fixed latency 1 WZL Write zero latency 1 1 WZL Disabled Latency on write accesses 0 Enabled No latency on write accesses 1 TACC Access time 8 8 0 255 TRWR Read write recovery time 16 8 0 255 SEC_OCTOSPI1 0x520D1400 OCTOSPI2 0x420D2400 OCTOSPI2 OCTOSPI2 global interrupt 120 SEC_OCTOSPI2 0x520D2400 LPUART1 Universal synchronous asynchronous receiver transmitter LPUART 0x46002400 0x0 0x400 registers LPUART1 LPUART1 global interrupt 66 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFFIE 31 1 TXFEIE TXFEIE 30 1 FIFOEN FIFOEN 29 1 M1 Word length 28 1 DEAT DEAT 21 5 DEDT DEDT 16 5 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE TXFIFO not full interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXFNEIE 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the LPUART node 24 8 MSBFIRST Most significant bit first 19 1 DATAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 STOP STOP bits 12 2 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFTCFG 29 3 RXFTIE RXFTIE 28 1 RXFTCFG RXFTCFG 25 3 TXFTIE TXFTIE 23 1 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 HDSEL Half-duplex selection 3 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR BRR 0 20 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ TXFRQ 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ISR ISR Interrupt and status register 0x1C 0x20 read-only 0x008000C0 TXFT TXFT 27 1 RXFT RXFT 26 1 RXFF RXFF 24 1 TXFE TXFE 23 1 REACK REACK 22 1 TEACK TEACK 21 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 CTS CTS 10 1 CTSIF CTSIF 9 1 TXFNF TXFNF 7 1 TC TC 6 1 RXFNE RXFNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NE NE 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NECF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 PRESC PRESC prescaler register 0x2C 0x20 read-write 0x00000000 PRESCALER PRESCALER 0 4 AUTOCR AUTOCR Autonomous mode control register 0x30 0x20 read-write 0x80000000 TDN TDN 0 16 TRIGPOL TRIGPOL 16 1 TRIGEN TRIGEN 17 1 IDLEDIS IDLEDIS 18 1 TRIGSEL TRIGSEL 19 4 TECLREN TECLREN 31 1 SEC_LPUART1 0x56002400 COMP Comparator COMP 0x46005400 0x0 0x400 registers COMP COMP1 and COMP2 interrupts 72 COMP1_CSR COMP1_CSR Comparator 1 control and status register 0x0 0x20 0x00000000 COMP1_EN Comparator 1 enable bit 0 1 read-write COMP1_INMSEL Comparator 1 Input Minus connection configuration bit 4 4 read-write COMP1_INPSEL Comparator1 input plus selection bit 8 2 read-write COMP1_WINMODE COMP1_WINMODE 11 1 read-write COMP1_WINOUT COMP1_WINOUT 14 1 read-write COMP1_POLARITY Comparator 1 polarity selection bit 15 1 read-write COMP1_HYST Comparator 1 hysteresis selection bits 16 2 read-write COMP1_PWRMODE COMP1_PWRMODE 18 2 read-write COMP1_BLANKSEL COMP1_BLANKSEL 20 5 read-write COMP1_VALUE Comparator 1 output status bit 30 1 read-only COMP1_LOCK COMP1_CSR register lock bit 31 1 read-write COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x4 0x20 0x00000000 COM2_EN Comparator 2 enable bit 0 1 read-write COM2_INMSEL Comparator 2 Input Minus connection configuration bit 4 4 read-write COM2_INPSEL Comparator 2 input plus selection bit 8 2 read-write COM2_WINMODE COM2_WINMODE 11 1 read-write COM2_WINOUT COM2_WINOUT 14 1 read-write COM2_POLARITY Comparator 2 polarity selection bit 15 1 read-write COM2_HYST Comparator 2 hysteresis selection bits 16 2 read-write COM2_PWRMODE COM2_PWRMODE 18 2 read-write COM2_BLANKSEL COM2_BLANKSEL 20 5 read-write COM2_VALUE Comparator 2 output status bit 30 1 read-only COM2_LOCK COMP2_CSR register lock bit 31 1 read-write SEC_COMP 0x56005400 VREFBUF Voltage reference buffer VREF 0x46007400 0x0 0x400 registers CSR CSR VREFBUF control and status register 0x0 0x20 0x00000002 ENVR ENVR 0 1 read-write HIZ HIZ 1 1 read-write VRR VRR 3 1 read-only VRS VRS 4 3 read-write CCR CCR VREFBUF calibration control register 0x4 0x20 read-write 0x00000000 TRIM TRIM 0 6 SEC_VREFBUF 0x56007400 TSC Touch sensing controller TSC 0x40024000 0x0 0x400 registers TSC TSC global interrupt 92 CR CR control register 0x0 0x20 read-write 0x00000000 CTPH Charge transfer pulse high 28 4 CTPL Charge transfer pulse low 24 4 SSD Spread spectrum deviation 17 7 SSE Spread spectrum enable 16 1 SSE Disabled Spread spectrum disabled 0 Enabled Spread spectrum enabled 1 SSPSC Spread spectrum prescaler 15 1 PGPSC pulse generator prescaler 12 3 MCV Max count value 5 3 IODEF I/O Default mode 4 1 IODEF PushPull I/Os are forced to output push-pull low 0 Floating I/Os are in input floating 1 SYNCPOL Synchronization pin polarity 3 1 SYNCPOL FallingEdge Falling edge only 0 RisingEdge Rising edge and high level 1 AM Acquisition mode 2 1 AM Normal Normal acquisition mode (acquisition starts as soon as START bit is set) 0 Synchronized Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) 1 START Start a new acquisition 1 1 START NoStarted Acquisition not started 0 Started Start a new acquisition 1 TSCE Touch sensing controller enable 0 1 TSCE Disabled Touch sensing controller disabled 0 Enabled Touch sensing controller enabled 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 MCEIE Max count error interrupt enable 1 1 MCEIE Disabled Max count error interrupt disabled 0 Enabled Max count error interrupt enabled 1 EOAIE End of acquisition interrupt enable 0 1 EOAIE Disabled End of acquisition interrupt disabled 0 Enabled End of acquisition interrupt enabled 1 ICR ICR interrupt clear register 0x8 0x20 read-write 0x00000000 MCEIC Max count error interrupt clear 1 1 EOAIC End of acquisition interrupt clear 0 1 ISR ISR interrupt status register 0xC 0x20 read-only 0x00000000 MCEF Max count error flag 1 1 EOAF End of acquisition flag 0 1 IOHCR IOHCR I/O hysteresis control register 0x10 0x20 read-write 0xFFFFFFFF 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy Schmitt trigger hysteresis disabled 0 Enabled Gx_IOy Schmitt trigger hysteresis enabled 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOASCR IOASCR I/O analog switch control register 0x18 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy analog switch disabled (opened) 0 Enabled Gx_IOy analog switch enabled (closed) 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOSCR IOSCR I/O sampling control register 0x20 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as sampling capacitor 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOCCR IOCCR I/O channel control register 0x28 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as channel 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOGCSR IOGCSR I/O group control status register 0x30 0x20 0x00000000 8 0x1 1-8 G%sS Analog I/O group x status 16 1 read-only G1S Ongoing Acquisition on analog I/O group x is ongoing or not started 0 Complete Acquisition on analog I/O group x is complete 1 8 0x1 1-8 G%sE Analog I/O group x enable 0 1 read-write G1E Disabled Acquisition on analog I/O group x disabled 0 Enabled Acquisition on analog I/O group x enabled 1 8 0x4 1-8 IOG%sCR IOG%sCR I/O group x counter register 0x34 0x20 read-only 0x00000000 CNT Counter value 0 14 SEC_TSC 0x50024000 UCPD1 USB Power Delivery interface UCPD 0x4000DC00 0x0 0x400 registers UCPD1 UCPD1 global interrupt 106 CFGR1 CFGR1 UCPD configuration register 1 0x0 0x20 0x00000000 0xFFFFFFFF HBITCLKDIV Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a ucpd_clk divider producing half-bit clock (hbit_clk). 0 6 read-write 0 63 IFRGAP Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a ucpd_clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal. 6 5 read-write 1 31 TRANSWIN Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the ucpd_clk frequency and the HBITCLKDIV[5:0] bitfield setting. 11 5 read-write 1 31 PSC_USBPDCLK Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a kernel clock pre-scaler producing UCPD peripheral clock (ucpd_clk). It is recommended to use the pre-scaler so as to set the ucpd_clk frequency in the range from 6 to 9 MHz. 17 3 read-write PSC_USBPDCLK Div1 Divide by 1 0 Div2 Divide by 2 1 Div4 Divide by 4 2 Div8 Divide by 8 3 Div16 Divide by 16 4 TXDMAEN Transmission DMA mode enable When set, the bit enables DMA mode for transmission. 29 1 read-write TXDMAEN Disabled DMA mode for transmission disabled 0 Enabled DMA mode for transmission enabled 1 RXDMAEN Reception DMA mode enable When set, the bit enables DMA mode for reception. 30 1 read-write RXDMAEN Disabled DMA mode for reception disabled 0 Enabled DMA mode for reception enabled 1 UCPDEN UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state. 31 1 read-write UCPDEN Disabled UCPD peripheral disabled 0 Enabled UCPD peripheral enabled 1 RXORDSETEN0 SOP detection 20 1 RXORDSETEN0 Disabled Flag disabled 0 Enabled Flag enabled 1 RXORDSETEN1 SOP' detection 21 1 RXORDSETEN2 SOP'' detection 22 1 RXORDSETEN3 Hard Reset detection 23 1 RXORDSETEN4 Cable Detect reset 24 1 RXORDSETEN5 SOP'_Debug 25 1 RXORDSETEN6 SOP'' Debug 26 1 RXORDSETEN7 SOP extension #1 27 1 RXORDSETEN8 SOP extension #2 28 1 CFGR2 CFGR2 UCPD configuration register 2 0x4 0x20 0x00000000 0xFFFFFFFF RXFILTDIS BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler). 0 1 read-write RXFILTDIS Enabled Rx pre-filter enabled 0 Disabled Rx pre-filter disabled 1 RXFILT2N3 BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value. 1 1 read-write RXFILT2N3 Samp3 3 samples 0 Samp2 2 samples 1 FORCECLK Force ClkReq clock request 2 1 read-write FORCECLK NoForce Do not force clock request 0 Force Force clock request 1 WUPEN Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal. 3 1 read-write WUPEN Disabled Disabled 0 Enabled Enabled 1 CFGR3 CFGR3 UCPD configuration register 3 0x8 0x20 0x00000000 0xFFFFFFFF TRIM1_NG_CCRPD SW trim value for RPD resistors on the CC1 line 0 4 read-write 0 15 TRIM1_NG_CC3A0 SW trim value for Iref on the CC1 line 9 4 read-write 0 15 TRIM2_NG_CCRPD SW trim value for RPD resistors on the CC2 line 16 4 read-write 0 15 TRIM2_NG_CC3A0 SW trim value for Iref on the CC2 line 25 4 read-write 0 15 CR CR UCPD control register 0xC 0x20 0x00000000 0xFFFFFFFF TXMODE Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the "tBISTContMode" delay), disable the peripheral (UCPDEN = 0). 0 2 read-write TXMODE RegisterSet Transmission of Tx packet previously defined in other registers 0 CableReset Cable Reset sequence 1 BISTTest BIST test sequence (BIST Carrier Mode 2) 2 TXSEND Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded. 2 1 read-write TXSEND NoEffect No effect 0 Start Start Tx packet transmission 1 TXHRST Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded. 3 1 read-write TXHRST NoEffect No effect 0 Start Start Tx Hard Reset message 1 RXMODE Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message. 4 1 read-write RXMODE Normal Normal receive mode 0 BIST BIST receive mode (BIST test data mode) 1 PHYRXEN USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set. 5 1 read-write PHYRXEN Disabled USB Power Delivery receiver disabled 0 Enabled USB Power Delivery receiver enabled 1 PHYCCSEL CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach. 6 1 read-write PHYCCSEL CC1 Use CC1 IO for Power Delivery communication 0 CC2 Use CC2 IO for Power Delivery communication 1 ANASUBMODE Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield. 7 2 read-write ANASUBMODE Disabled Disabled 0 Rp_DefaultUSB Default USB Rp 1 Rp_1_5A 1.5A Rp 2 Rp_3A 3A Rp 3 ANAMODE Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0]. 9 1 read-write ANAMODE Source Source 0 Sink Sink 1 CCENABLE CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source. 10 2 read-write CCENABLE Disabled Both PHYs disabled 0 CC1Enabled CC1 PHY enabled 1 CC2Enabled CC2 PHY enabled 2 BothEnabled CC1 and CC2 PHYs enabled 3 CC1VCONNEN VCONN switch enable for CC1 13 1 read-write CC2VCONNEN VCONN switch enable for CC2 14 1 read-write FRSRXEN FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink. 16 1 read-write FRSRXEN Disabled FRS Rx event detection disabled 0 Enabled FRS Rx event detection enabled 1 FRSTX FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0. 17 1 read-write FRSTX NoEffect No effect 0 Enabled FRS Tx signaling enabled 1 RDCH Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to "USB Type-C ECN for Source VCONN Discharge". The CCENABLE[1:0] bitfield must be set accordingly, too. 18 1 read-write RDCH NoEffect No effect 0 ConditionDrive Rdch condition drive 1 CC1TCDIS CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0]. 20 1 read-write CC1TCDIS Enabled Type-C detector on the CCx line enabled 0 Disabled Type-C detector on the CCx line disabled 1 CC2TCDIS CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0]. 21 1 read-write IMR IMR UCPD interrupt mask register 0x10 0x20 0x00000000 0xFFFFFFFF TXISIE TXIS interrupt enable 0 1 read-write TXISIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TXMSGDISCIE TXMSGDISC interrupt enable 1 1 read-write TXMSGSENTIE TXMSGSENT interrupt enable 2 1 read-write TXMSGABTIE TXMSGABT interrupt enable 3 1 read-write HRSTDISCIE HRSTDISC interrupt enable 4 1 read-write HRSTSENTIE HRSTSENT interrupt enable 5 1 read-write TXUNDIE TXUND interrupt enable 6 1 read-write RXNEIE RXNE interrupt enable 8 1 read-write RXORDDETIE RXORDDET interrupt enable 9 1 read-write RXHRSTDETIE RXHRSTDET interrupt enable 10 1 read-write RXOVRIE RXOVR interrupt enable 11 1 read-write RXMSGENDIE RXMSGEND interrupt enable 12 1 read-write TYPECEVT1IE TYPECEVT1 interrupt enable 14 1 read-write TYPECEVT2IE TYPECEVT2 interrupt enable 15 1 read-write FRSEVTIE FRSEVT interrupt enable 20 1 read-only SR SR UCPD status register 0x14 0x20 0x00000000 0xFFFFFFFF TXIS Transmit interrupt status The flag indicates that the UCPD_TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the UCPD_TXDR register. 0 1 read-only TXIS NotRequired New Tx data write not required 0 Required New Tx data write required 1 TXMSGDISC Message transmission discarded The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit. Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle. 1 1 read-only TXMSGDISC NotDiscarded No Tx message discarded 0 Discarded Tx message discarded 1 TXMSGSENT Message transmission completed The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit. In the event of a message transmission interrupted by a Hard Reset, the flag is not raised. 2 1 read-only TXMSGSENT NotCompleted No Tx message completed 0 Completed Tx message completed 1 TXMSGABT Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit. 3 1 read-only TXMSGABT NoAbort No transmit message abort 0 Abort Transmit message abort 1 HRSTDISC Hard Reset discarded The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit. 4 1 read-only HRSTDISC NotDiscarded No Hard Reset discarded 0 Discarded Hard Reset discarded 1 HRSTSENT Hard Reset message sent The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit. 5 1 read-only HRSTSENT NotSent No Hard Reset message sent 0 Sent Hard Reset message sent 1 TXUND Tx data underrun detection The flag indicates that the Tx data register (UCPD_TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit. 6 1 read-only TXUND NoUnderrun No Tx data underrun detected 0 Underrun Tx data underrun detected 1 RXNE Receive data register not empty detection The flag indicates that the UCPD_RXDR register is not empty. It is automatically cleared upon reading UCPD_RXDR. 8 1 read-only RXNE Empty Rx data register empty 0 NotEmpty Rx data register not empty 1 RXORDDET Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the UCPD_RX_ORDSET register. It is cleared by setting the RXORDDETCF bit. 9 1 read-only RXORDDET NoOrderedSet No ordered set detected 0 OrderedSet Ordered set detected 1 RXHRSTDET Rx Hard Reset receipt detection The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit. 10 1 read-only RXHRSTDET NoHardReset Hard Reset not received 0 HardReset Hard Reset received 1 RXOVR Rx data overflow detection The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit. The buffer overflow can occur if the received data are not read fast enough. 11 1 read-only RXOVR NoOverflow No overflow 0 Overflow Overflow 1 RXMSGEND Rx message received The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit. The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message. 12 1 read-only RXMSGEND NoNewMessage No new Rx message received 0 NewMessage A new Rx message received 1 RXERR Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set. 13 1 read-only RXERR NoError No error detected 0 Error Error(s) detected 1 TYPECEVT1 Type-C voltage level event on CC1 line The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit. 14 1 read-only TYPECEVT1 NoNewEvent No new event 0 NewEvent A new Type-C event occurred 1 TYPECEVT2 Type-C voltage level event on CC2 line The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit. 15 1 read-only TYPEC_VSTATE_CC1 The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value. 16 2 read-only TYPEC_VSTATE_CC1 Lowest Lowest 0 Low Low 1 High High 2 Highest Highest 3 TYPEC_VSTATE_CC2 CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its steady state. The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value. 18 2 read-only FRSEVT FRS detection event The flag is cleared by setting the FRSEVTCF bit. 20 1 read-only FRSEVT NoNewEvent No new event 0 NewEvent New FRS receive event occurred 1 ICR ICR UCPD interrupt clear register 0x18 0x20 0x00000000 0xFFFFFFFF TXMSGDISCCF Tx message discard flag (TXMSGDISC) clear Setting the bit clears the TXMSGDISC flag in the UCPD_SR register. 1 1 write-only TXMSGDISCCFW Clear Clear flag in UCPD_SR 1 TXMSGSENTCF Tx message send flag (TXMSGSENT) clear Setting the bit clears the TXMSGSENT flag in the UCPD_SR register. 2 1 write-only TXMSGABTCF Tx message abort flag (TXMSGABT) clear Setting the bit clears the TXMSGABT flag in the UCPD_SR register. 3 1 write-only HRSTDISCCF Hard reset discard flag (HRSTDISC) clear Setting the bit clears the HRSTDISC flag in the UCPD_SR register. 4 1 write-only HRSTSENTCF Hard reset send flag (HRSTSENT) clear Setting the bit clears the HRSTSENT flag in the UCPD_SR register. 5 1 write-only TXUNDCF Tx underflow flag (TXUND) clear Setting the bit clears the TXUND flag in the UCPD_SR register. 6 1 write-only RXORDDETCF Rx ordered set detect flag (RXORDDET) clear Setting the bit clears the RXORDDET flag in the UCPD_SR register. 9 1 write-only RXHRSTDETCF Rx Hard Reset detect flag (RXHRSTDET) clear Setting the bit clears the RXHRSTDET flag in the UCPD_SR register. 10 1 write-only RXOVRCF Rx overflow flag (RXOVR) clear Setting the bit clears the RXOVR flag in the UCPD_SR register. 11 1 write-only RXMSGENDCF Rx message received flag (RXMSGEND) clear Setting the bit clears the RXMSGEND flag in the UCPD_SR register. 12 1 write-only TYPECEVT1CF Type-C CC1 event flag (TYPECEVT1) clear Setting the bit clears the TYPECEVT1 flag in the UCPD_SR register 14 1 write-only TYPECEVT2CF Type-C CC2 line event flag (TYPECEVT2) clear Setting the bit clears the TYPECEVT2 flag in the UCPD_SR register 15 1 write-only FRSEVTCF FRS event flag (FRSEVT) clear Setting the bit clears the FRSEVT flag in the UCPD_SR register. 20 1 write-only TX_ORDSETR TX_ORDSETR UCPD Tx ordered set type register 0x1C 0x20 0x00000000 0xFFFFFFFF TXORDSET Ordered set to transmit The bitfield determines a full 20-bit sequence to transmit, consisting of four K-codes, each of five bits, defining the packet to transmit. The bit 0 (bit 0 of K-code1) is the first, the bit 19 (bit 4 of Kâcode4) the last. 0 20 read-write 0 1048575 TX_PAYSZR TX_PAYSZR UCPD Tx payload size register 0x20 0x20 0x00000000 0xFFFFFFFF TXPAYSZ Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the UCPD_TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission. 0 10 read-write 0 1023 TXDR TXDR UCPD Tx data register 0x24 0x20 0x00000000 0xFFFFFFFF TXDATA Data byte to transmit 0 8 read-write 0 255 RX_ORDSETR RX_ORDSETR 0x28 0x20 0x00000000 0xFFFFFFFF RXORDSET Rx ordered set code detected 0 3 read-only RXORDSET SOP SOP code detected in receiver 0 SOPPrime SOP' code detected in receiver 1 SOPDoublePrime SOP'' code detected in receiver 2 SOPPrimeDebug SOP'_Debug detected in receiver 3 SOPDoublePrimeDebug SOP''_Debug detected in receiver 4 CableReset Cable Reset detected in receiver 5 SOPExtension1 SOP extension #1 detected in receiver 6 SOPExtension2 SOP extension #2 detected in receiver 7 RXSOP3OF4 The bit indicates the number of correct Kâcodes. For debug purposes only. 3 1 read-only RXSOP3OF4 AllCorrect 4 correct K-codes out of 4 0 OneIncorrect 3 correct K-codes out of 4 1 RXSOPKINVALID The bitfield is for debug purposes only. Others: Invalid 4 3 read-only RXSOPKINVALID Valid No K-code corrupted 0 FirstCorrupted First K-code corrupted 1 SecondCorrupted Second K-code corrupted 2 ThirdCorrupted Third K-code corrupted 3 FourthCorrupted Fourth K-code corrupted 4 RX_PAYSZR RX_PAYSZR 0x2C 0x20 0x00000000 0xFFFFFFFF RXPAYSZ Rx payload size received This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the UCPD_RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled). The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low). 0 10 read-only 0 1023 RXDR RXDR 0x30 0x20 0x00000000 0xFFFFFFFF RXDATA Data byte received 0 8 read-only 0 255 RX_ORDEXTR1 RX_ORDEXTR1 UCPD Rx ordered set extension register 1 0x34 0x20 0x00000000 0xFFFFFFFF RXSOPX1 Ordered set 1 received The bitfield contains a full 20-bit sequence received, consisting of four Kâcodes, each of five bits. The bit 0 (bit 0 of Kâcode1) is receive first, the bit 19 (bit 4 of Kâcode4) last. 0 20 read-write 0 1048575 RX_ORDEXTR2 RX_ORDEXTR2 UCPD Rx ordered set extension register 2 0x38 0x20 0x00000000 0xFFFFFFFF RXSOPX2 Ordered set 2 received The bitfield contains a full 20-bit sequence received, consisting of four Kâcodes, each of five bits. The bit 0 (bit 0 of Kâcode1) is receive first, the bit 19 (bit 4 of Kâcode4) last. 0 20 read-write 0 1048575 SEC_UCPD1 0x5000DC00 FDCAN1_RAM FDCAN1_RAM FDCAN 0x4000AC00 0x0 0x400 registers FDCAN1_IT0 FDCAN1 Interrupt 0 39 FDCAN1_IT1 FDCAN1 Interrupt 1 40 CREL CREL FDCAN Core Release Register 0x0 0x20 read-only 0x32141218 REL Core release 28 4 STEP Step of Core release 24 4 SUBSTEP Sub-step of Core release 20 4 YEAR Timestamp Year 16 4 MON Timestamp Month 8 8 DAY Timestamp Day 0 8 ENDN ENDN FDCAN endian register 0x4 0x20 read-only 0x87654321 ETV Endiannes Test Value 0 32 DBTP DBTP FDCAN Data Bit Timing and Prescaler Register 0xC 0x20 read-write 0x00000A33 DSJW Synchronization Jump Width 0 4 DTSEG2 Data time segment after sample point 4 4 DTSEG1 Data time segment after sample point 8 5 DBRP Data BIt Rate Prescaler 16 5 TDC Transceiver Delay Compensation 23 1 TEST TEST FDCAN Test Register 0x10 0x20 0x00000000 LBCK Loop Back mode 4 1 read-write TX Loop Back mode 5 2 read-write RX Control of Transmit Pin 7 1 read-only RWD RWD FDCAN RAM Watchdog Register 0x14 0x20 0x00000000 WDV Watchdog value 8 8 read-only WDC Watchdog configuration 0 8 read-write CCCR CCCR FDCAN CC Control Register 0x18 0x20 read-write 0x00000001 INIT Initialization 0 1 CCE Configuration Change Enable 1 1 ASM ASM Restricted Operation Mode 2 1 CSA Clock Stop Acknowledge 3 1 CSR Clock Stop Request 4 1 MON Bus Monitoring Mode 5 1 DAR Disable Automatic Retransmission 6 1 TEST Test Mode Enable 7 1 FDOE FD Operation Enable 8 1 BRSE FDCAN Bit Rate Switching 9 1 PXHD Protocol Exception Handling Disable 12 1 EFBI Edge Filtering during Bus Integration 13 1 TXP TXP 14 1 NISO Non ISO Operation 15 1 NBTP NBTP FDCAN Nominal Bit Timing and Prescaler Register 0x1C 0x20 read-write 0x06000A03 NSJW Nominal (Re)Synchronization Jump Width 25 7 NBRP Bit Rate Prescaler 16 9 NTSEG1 Nominal Time segment before sample point 8 8 NTSEG2 Nominal Time segment after sample point 0 7 TSCC TSCC FDCAN Timestamp Counter Configuration Register 0x20 0x20 read-write 0x00000000 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 TSCV TSCV FDCAN Timestamp Counter Value Register 0x24 0x20 read-write 0x00000000 TSC Timestamp Counter 0 16 TOCC TOCC FDCAN Timeout Counter Configuration Register 0x28 0x20 read-write 0xFFFF0000 ETOC Enable Timeout Counter 0 1 TOS Timeout Select 1 2 TOP Timeout Period 16 16 TOCV TOCV FDCAN Timeout Counter Value Register 0x2C 0x20 read-write 0x0000FFFF TOC Timeout Counter 0 16 ECR ECR FDCAN Error Counter Register 0x40 0x20 0x00000000 CEL AN Error Logging 16 8 read-write RP Receive Error Passive 15 1 read-only REC Receive Error Counter 8 7 read-only TEC Transmit Error Counter 0 8 read-only PSR PSR FDCAN Protocol Status Register 0x44 0x20 0x00000707 LEC Last Error Code 0 3 read-write ACT Activity 3 2 read-only EP Error Passive 5 1 read-only EW Warning Status 6 1 read-only BO Bus_Off Status 7 1 read-only DLEC Data Last Error Code 8 3 read-write RESI ESI flag of last received FDCAN Message 11 1 read-write RBRS BRS flag of last received FDCAN Message 12 1 read-write REDL Received FDCAN Message 13 1 read-write PXE Protocol Exception Event 14 1 read-write TDCV Transmitter Delay Compensation Value 16 7 read-only TDCR TDCR FDCAN Transmitter Delay Compensation Register 0x48 0x20 read-write 0x00000000 TDCF Transmitter Delay Compensation Filter Window Length 0 7 TDCO Transmitter Delay Compensation Offset 8 7 IR IR FDCAN Interrupt Register 0x50 0x20 read-write 0x00000000 RF0N RF0N 0 1 RF0F RF0F 1 1 RF0L RF0L 2 1 RF1N RF1N 3 1 RF1F RF1F 4 1 RF1L RF1L 5 1 HPM HPM 6 1 TC TC 7 1 TCF TCF 8 1 TFE TFE 9 1 TEFN TEFN 10 1 TEFF TEFF 11 1 TEFL TEFL 12 1 TSW TSW 13 1 MRAF MRAF 14 1 TOO TOO 15 1 ELO ELO 16 1 EP EP 17 1 EW EW 18 1 BO BO 19 1 WDI WDI 20 1 PEA PEA 21 1 PED PED 22 1 ARA ARA 23 1 IE IE FDCAN Interrupt Enable Register 0x54 0x20 read-write 0x00000000 RF0NE Rx FIFO 0 New Message Enable 0 1 RF0FE Rx FIFO 0 Full Enable 1 1 RF0LE Rx FIFO 0 Message Lost Enable 2 1 RF1NE Rx FIFO 1 New Message Enable 3 1 RF1FE Rx FIFO 1 Watermark Reached Enable 4 1 RF1LE Rx FIFO 1 Message Lost Enable 5 1 HPME High Priority Message Enable 6 1 TCE Transmission Completed Enable 7 1 TCFE Transmission Cancellation Finished Enable 8 1 TEFE Tx FIFO Empty Enable 9 1 TEFNE Tx Event FIFO New Entry Enable 10 1 TEFFE Tx Event FIFO Full Enable 11 1 TEFLE Tx Event FIFO Element Lost Enable 12 1 TSWE TSWE 13 1 MRAFE Message RAM Access Failure Enable 14 1 TOOE Timeout Occurred Enable 15 1 ELOE Error Logging Overflow Enable 16 1 EPE Error Passive Enable 17 1 EWE Warning Status Enable 18 1 BOE Bus_Off Status Enable 19 1 WDIE Watchdog Interrupt Enable 20 1 PEAE Protocol Error in Arbitration Phase Enable 21 1 PEDE Protocol Error in Data Phase Enable 22 1 ARAE Access to Reserved Address Enable 23 1 ILS ILS FDCAN Interrupt Line Select Register 0x58 0x20 read-write 0x00000000 RxFIFO0 RxFIFO0 0 1 RxFIFO1 RxFIFO1 1 1 SMSG SMSG 2 1 TFERR TFERR 3 1 MISC MISC 4 1 BERR BERR 5 1 PERR PERR 6 1 ILE ILE FDCAN Interrupt Line Enable Register 0x5C 0x20 read-write 0x00000000 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 RXGFC RXGFC FDCAN Global Filter Configuration Register 0x80 0x20 read-write 0x00000000 RRFE Reject Remote Frames Extended 0 1 RRFS Reject Remote Frames Standard 1 1 ANFE Accept Non-matching Frames Extended 2 2 ANFS Accept Non-matching Frames Standard 4 2 F1OM F1OM 8 1 F0OM F0OM 9 1 LSS LSS 16 5 LSE LSE 24 4 XIDAM XIDAM FDCAN Extended ID and Mask Register 0x84 0x20 read-write 0x1FFFFFFF EIDM Extended ID Mask 0 29 HPMS HPMS FDCAN High Priority Message Status Register 0x88 0x20 read-only 0x00000000 BIDX Buffer Index 0 3 MSI Message Storage Indicator 6 2 FIDX Filter Index 8 5 FLST Filter List 15 1 RXF0S RXF0S FDCAN Rx FIFO 0 Status Register 0x90 0x20 read-only 0x00000000 F0FL Rx FIFO 0 Fill Level 0 4 F0GI Rx FIFO 0 Get Index 8 2 F0PI Rx FIFO 0 Put Index 16 2 F0F Rx FIFO 0 Full 24 1 RF0L Rx FIFO 0 Message Lost 25 1 RXF0A RXF0A CAN Rx FIFO 0 Acknowledge Register 0x94 0x20 read-write 0x00000000 F0AI Rx FIFO 0 Acknowledge Index 0 3 RXF1S RXF1S FDCAN Rx FIFO 1 Status Register 0x98 0x20 read-only 0x00000000 F1FL Rx FIFO 1 Fill Level 0 4 F1GI Rx FIFO 1 Get Index 8 2 F1PI Rx FIFO 1 Put Index 16 2 F1F Rx FIFO 1 Full 24 1 RF1L Rx FIFO 1 Message Lost 25 1 RXF1A RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0x9C 0x20 read-write 0x00000000 F1AI Rx FIFO 1 Acknowledge Index 0 3 TXBC TXBC FDCAN Tx buffer configuration register 0xC0 0x20 read-write 0x00000000 TFQM Tx FIFO/Queue Mode 24 1 TXFQS TXFQS FDCAN Tx FIFO/Queue Status Register 0xC4 0x20 read-only 0x00000003 TFFL Tx FIFO Free Level 0 3 TFGI TFGI 8 2 TFQPI Tx FIFO/Queue Put Index 16 2 TFQF Tx FIFO/Queue Full 21 1 TXBRP TXBRP FDCAN Tx Buffer Request Pending Register 0xC8 0x20 read-only 0x00000000 TRP Transmission Request Pending 0 3 TXBAR TXBAR FDCAN Tx Buffer Add Request Register 0xCC 0x20 read-write 0x00000000 AR Add Request 0 3 TXBCR TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD0 0x20 read-write 0x00000000 CR Cancellation Request 0 3 TXBTO TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD4 0x20 read-only 0x00000000 TO Transmission Occurred. 0 3 TXBCF TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xD8 0x20 read-only 0x00000000 CF Cancellation Finished 0 3 TXBTIE TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xDC 0x20 read-write 0x00000000 TIE Transmission Interrupt Enable 0 3 TXBCIE TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE0 0x20 read-write 0x00000000 CFIE Cancellation Finished Interrupt Enable 0 3 TXEFS TXEFS FDCAN Tx Event FIFO Status Register 0xE4 0x20 read-only 0x00000000 EFFL Event FIFO Fill Level 0 3 EFGI Event FIFO Get Index. 8 2 EFPI Event FIFO Put Index 16 2 EFF Event FIFO Full. 24 1 TEFL Tx Event FIFO Element Lost. 25 1 TXEFA TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xE8 0x20 read-write 0x00000000 EFAI Event FIFO Acknowledge Index 0 2 CKDIV CKDIV FDCAN CFG clock divider register 0x100 0x20 read-write 0x00000000 PDIV PDIV 0 4 SEC_FDCAN1_RAM 0x5000AC00 FDCAN1 0x4000A400 TIM17 TIM17 global interrupt 71 SEC_FDCAN1 0x5000A400 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 32 0 4294967295 CR CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 REV_IN Reverse input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 POLYSIZE Polynomial size 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 RESET RESET bit 0 1 read-write RESETW write Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF INIT Programmable initial CRC value 0 32 0 4294967295 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 0 4294967295 SEC_CRC 0x50023000 CRS Clock recovery system CRS 0x40006000 0x0 0x400 registers CRS Clock recovery system global interrupt 74 CR CR control register 0x0 0x20 read-write 0x00004000 TRIM HSI48 oscillator smooth trimming 8 7 0 63 SWSYNC Generate software SYNC event 7 1 SWSYNC Sync A software sync is generated 1 AUTOTRIMEN Automatic trimming enable 6 1 AUTOTRIMEN Disabled Automatic trimming disabled 0 Enabled Automatic trimming enabled 1 CEN Frequency error counter enable 5 1 CEN Disabled Frequency error counter disabled 0 Enabled Frequency error counter enabled 1 SYNCOKIE SYNC event OK interrupt enable 0 1 SYNCOKIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 ESYNCIE Expected SYNC interrupt enable 3 1 ERRIE Synchronization or trimming error interrupt enable 2 1 SYNCWARNIE SYNC warning interrupt enable 1 1 CFGR CFGR configuration register 0x4 0x20 read-write 0x2022BB7F SYNCPOL SYNC polarity selection 31 1 SYNCPOL RisingEdge SYNC active on rising edge 0 FallingEdge SYNC active on falling edge 1 SYNCSRC SYNC signal source selection 28 2 SYNCSRC GPIO_AF GPIO AF (crs_sync_in_1) selected as SYNC signal source 0 LSE LSE (crs_sync_in_2) selected as SYNC signal source 1 USB_SOF USB SOF (crs_sync_in_3) selected as SYNC signal source 2 SYNCDIV SYNC divider 24 3 SYNCDIV Div1 SYNC not divided 0 Div2 SYNC divided by 2 1 Div4 SYNC divided by 4 2 Div8 SYNC divided by 8 3 Div16 SYNC divided by 16 4 Div32 SYNC divided by 32 5 Div64 SYNC divided by 64 6 Div128 SYNC divided by 128 7 FELIM Frequency error limit 16 8 0 255 RELOAD Counter reload value 0 16 0 65535 ISR ISR interrupt and status register 0x8 0x20 read-only 0x00000000 FECAP Frequency error capture 16 16 0 65535 FEDIR Frequency error direction 15 1 FEDIR UpCounting Error in up-counting direction 0 DownCounting Error in down-counting direction 1 SYNCOKF SYNC event OK flag 0 1 SYNCOKF NotSignaled Signal not set 0 Signaled Signal set 1 TRIMOVF Trimming overflow or underflow 10 1 SYNCMISS SYNC missed 9 1 SYNCERR SYNC error 8 1 ESYNCF Expected SYNC flag 3 1 ERRF Error flag 2 1 SYNCWARNF SYNC warning flag 1 1 ICR ICR interrupt flag clear register 0xC 0x20 read-write 0x00000000 SYNCOKC SYNC event OK clear flag 0 1 SYNCOKC Clear Clear flag 1 ESYNCC Expected SYNC clear flag 3 1 ERRC Error clear flag 2 1 SYNCWARNC SYNC warning clear flag 1 1 SEC_CRS 0x50006000 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 61 CR1 CR1_enabled Control register 1 0x0 0x20 read-write 0x00000000 M1 Word length 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 EOBIE End of Block interruptenable 27 1 EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 RTOIE Receiver timeout interrupt 26 1 RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 DEAT DEAT 21 5 0 31 DEDT DEDT 16 5 0 31 OVER8 Oversampling mode 15 1 OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 FIFOEN FIFOEN 29 1 FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFEIE 30 1 TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFFIE 31 1 RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 RTOEN Receiver timeout enable 23 1 RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ABRMOD Auto baud rate mode 21 2 ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 ABREN Auto baud rate enable 20 1 ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 LINEN LIN mode enable 14 1 LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 CPOL Clock polarity 10 1 CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CPHA Clock phase 9 1 CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 LBCL Last bit clock pulse 8 1 LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 LBDIE LIN break detection interrupt enable 6 1 LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBDL LIN break detection length 5 1 LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 SLVEN SLVEN 0 1 SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 DIS_NSS DIS_NSS 3 1 DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 SCARCNT Smartcard auto-retry count 17 3 0 7 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 ONEBIT One sample bit method enable 11 1 ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 SCEN Smartcard mode enable 5 1 SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 NACK Smartcard NACK enable 4 1 NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 IRLP Ir low-power 2 1 IRLP Normal Normal mode 0 LowPower Low-power mode 1 IREN Ir mode enable 1 1 IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 TXFTIE TXFTIE 23 1 TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 TCBGTIE TCBGTIE 24 1 TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 RXFTCFG RXFTCFG 25 3 RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFTIE 28 1 RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFTCFG 29 3 TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR BRR 0 16 0 65535 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 0 255 PSC Prescaler value 0 8 0 255 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 0 255 RTO Receiver timeout value 0 24 0 16777215 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ABRRQ Auto baud rate request 0 1 ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 ISR ISR_enabled Interrupt & status register 0x1C 0x20 read-only 0x028000C0 REACK REACK 22 1 TEACK TEACK 21 1 RWU RWU 19 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 ABRF ABRF 15 1 ABRE ABRE 14 1 EOBF EOBF 12 1 EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 RTOF RTOF 11 1 RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 LBDF LBDF 8 1 LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 TXFNF TXFNF 7 1 TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXFNE RXFNE 5 1 RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NE NE 2 1 NE NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 TXFE TXFE 23 1 TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFF 24 1 RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TCBGT TCBGT 25 1 TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFT RXFT 26 1 RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFT 27 1 TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 UDR SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to . 13 1 read-only UDR NoUnderrun No underrun error 0 Underrun underrun error 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 EOBCF End of block clear flag 12 1 oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 RTOCF Receiver timeout clear flag 11 1 oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 LBDCF LIN break detection clear flag 8 1 oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NECF Noise detected clear flag 2 1 oneToClear NECF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 TXFECF TXFECF 5 1 oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 TCBGTCF TCBGTCF 7 1 oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 UDRCF UDRCF 13 1 oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 PRESC PRESC PRESC 0x2C 0x20 read-write 0x00000000 PRESCALER PRESCALER 0 4 PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 AUTOCR AUTOCR AUTOCR 0x30 0x20 read-write 0x80000000 TECLREN TECLREN 31 1 IDLEDIS IDLEDIS 18 1 TRIGSEL TRIGSEL 19 4 TRIGEN TRIGEN 17 1 TRIGPOL TRIPOL 16 1 TDN TDN 0 16 SEC_USART1 0x50013800 USART2 0x40004400 USART2 USART2 global interrupt 62 SEC_USART2 0x50004400 USART3 0x40004800 USART3 USART3 global interrupt 63 SEC_USART3 0x50004800 UART4 0x40004C00 UART4 UART4 global interrupt 64 SEC_UART4 0x50004C00 UART5 0x40005000 UART5 UART5 global interrupt 65 SEC_UART5 0x50005000 HASH Hash processor HASH 0x420C0400 0x0 0x400 registers HASH HASH interrupt 96 CR CR control register 0x0 0x20 0x00000000 INIT Initialize message digest calculation 2 1 write-only DMAE DMA enable 3 1 read-write DATATYPE Data type selection 4 2 read-write MODE Mode selection 6 1 read-write ALGO Algorithm selection 17 2 read-write NBW Number of words already pushed 8 4 read-only DINNE DIN not empty 12 1 read-only MDMAT Multiple DMA Transfers 13 1 read-write LKEY Long key selection 16 1 read-write DIN DIN data input register 0x4 0x20 write-only 0x00000000 DATAIN Data input 0 32 STR STR start register 0x8 0x20 0x00000000 DCAL Digest calculation 8 1 write-only NBLW Number of valid bits in the last word of the message 0 5 read-write HRA0 HRA0 HASH aliased digest register 0 0xC 0x20 read-only 0x00000000 H0 H0 0 32 HRA1 HRA1 HASH aliased digest register 1 0x10 0x20 read-only 0x00000000 H1 H1 0 32 HRA2 HRA2 HASH aliased digest register 2 0x14 0x20 read-only 0x00000000 H2 H2 0 32 HRA3 HRA3 HASH aliased digest register 3 0x18 0x20 read-only 0x00000000 H3 H3 0 32 HRA4 HRA4 HASH aliased digest register 4 0x1C 0x20 read-only 0x00000000 H4 H4 0 32 HR0 HR0 digest register 0 0x310 0x20 read-only 0x00000000 H0 H0 0 32 HR1 HR1 digest register 1 0x314 0x20 read-only 0x00000000 H1 H1 0 32 HR2 HR2 digest register 4 0x318 0x20 read-only 0x00000000 H2 H2 0 32 HR3 HR3 digest register 3 0x31C 0x20 read-only 0x00000000 H3 H3 0 32 HR4 HR4 digest register 4 0x320 0x20 read-only 0x00000000 H4 H4 0 32 HR5 HR5 supplementary digest register 5 0x324 0x20 read-only 0x00000000 H5 H5 0 32 HR6 HR6 supplementary digest register 6 0x328 0x20 read-only 0x00000000 H6 H6 0 32 HR7 HR7 supplementary digest register 7 0x32C 0x20 read-only 0x00000000 H7 H7 0 32 IMR IMR interrupt enable register 0x20 0x20 read-write 0x00000000 DCIE Digest calculation completion interrupt enable 1 1 DINIE Data input interrupt enable 0 1 SR SR status register 0x24 0x20 0x00000001 BUSY Busy bit 3 1 read-only DMAS DMA Status 2 1 read-only DCIS Digest calculation completion interrupt status 1 1 read-write DINIS Data input interrupt status 0 1 read-write NBWE Number of words expected 16 5 read-only DINNE DIN not empty 15 1 read-only NBWP Number of words already pushed 9 5 read-only CSR0 CSR0 context swap registers 0xF8 0x20 read-write 0x00000000 CSR0 CSR0 0 32 CSR1 CSR1 context swap registers 0xFC 0x20 read-write 0x00000000 CSR1 CSR1 0 32 CSR2 CSR2 context swap registers 0x100 0x20 read-write 0x00000000 CSR2 CSR2 0 32 CSR3 CSR3 context swap registers 0x104 0x20 read-write 0x00000000 CSR3 CSR3 0 32 CSR4 CSR4 context swap registers 0x108 0x20 read-write 0x00000000 CSR4 CSR4 0 32 CSR5 CSR5 context swap registers 0x10C 0x20 read-write 0x00000000 CSR5 CSR5 0 32 CSR6 CSR6 context swap registers 0x110 0x20 read-write 0x00000000 CSR6 CSR6 0 32 CSR7 CSR7 context swap registers 0x114 0x20 read-write 0x00000000 CSR7 CSR7 0 32 CSR8 CSR8 context swap registers 0x118 0x20 read-write 0x00000000 CSR8 CSR8 0 32 CSR9 CSR9 context swap registers 0x11C 0x20 read-write 0x00000000 CSR9 CSR9 0 32 CSR10 CSR10 context swap registers 0x120 0x20 read-write 0x00000000 CSR10 CSR10 0 32 CSR11 CSR11 context swap registers 0x124 0x20 read-write 0x00000000 CSR11 CSR11 0 32 CSR12 CSR12 context swap registers 0x128 0x20 read-write 0x00000000 CSR12 CSR12 0 32 CSR13 CSR13 context swap registers 0x12C 0x20 read-write 0x00000000 CSR13 CSR13 0 32 CSR14 CSR14 context swap registers 0x130 0x20 read-write 0x00000000 CSR14 CSR14 0 32 CSR15 CSR15 context swap registers 0x134 0x20 read-write 0x00000000 CSR15 CSR15 0 32 CSR16 CSR16 context swap registers 0x138 0x20 read-write 0x00000000 CSR16 CSR16 0 32 CSR17 CSR17 context swap registers 0x13C 0x20 read-write 0x00000000 CSR17 CSR17 0 32 CSR18 CSR18 context swap registers 0x140 0x20 read-write 0x00000000 CSR18 CSR18 0 32 CSR19 CSR19 context swap registers 0x144 0x20 read-write 0x00000000 CSR19 CSR19 0 32 CSR20 CSR20 context swap registers 0x148 0x20 read-write 0x00000000 CSR20 CSR20 0 32 CSR21 CSR21 context swap registers 0x14C 0x20 read-write 0x00000000 CSR21 CSR21 0 32 CSR22 CSR22 context swap registers 0x150 0x20 read-write 0x00000000 CSR22 CSR22 0 32 CSR23 CSR23 context swap registers 0x154 0x20 read-write 0x00000000 CSR23 CSR23 0 32 CSR24 CSR24 context swap registers 0x158 0x20 read-write 0x00000000 CSR24 CSR24 0 32 CSR25 CSR25 context swap registers 0x15C 0x20 read-write 0x00000000 CSR25 CSR25 0 32 CSR26 CSR26 context swap registers 0x160 0x20 read-write 0x00000000 CSR26 CSR26 0 32 CSR27 CSR27 context swap registers 0x164 0x20 read-write 0x00000000 CSR27 CSR27 0 32 CSR28 CSR28 context swap registers 0x168 0x20 read-write 0x00000000 CSR28 CSR28 0 32 CSR29 CSR29 context swap registers 0x16C 0x20 read-write 0x00000000 CSR29 CSR29 0 32 CSR30 CSR30 context swap registers 0x170 0x20 read-write 0x00000000 CSR30 CSR30 0 32 CSR31 CSR31 context swap registers 0x174 0x20 read-write 0x00000000 CSR31 CSR31 0 32 CSR32 CSR32 context swap registers 0x178 0x20 read-write 0x00000000 CSR32 CSR32 0 32 CSR33 CSR33 context swap registers 0x17C 0x20 read-write 0x00000000 CSR33 CSR33 0 32 CSR34 CSR34 context swap registers 0x180 0x20 read-write 0x00000000 CSR34 CSR34 0 32 CSR35 CSR35 context swap registers 0x184 0x20 read-write 0x00000000 CSR35 CSR35 0 32 CSR36 CSR36 context swap registers 0x188 0x20 read-write 0x00000000 CSR36 CSR36 0 32 CSR37 CSR37 context swap registers 0x18C 0x20 read-write 0x00000000 CSR37 CSR37 0 32 CSR38 CSR38 context swap registers 0x190 0x20 read-write 0x00000000 CSR38 CSR38 0 32 CSR39 CSR39 context swap registers 0x194 0x20 read-write 0x00000000 CSR39 CSR39 0 32 CSR40 CSR40 context swap registers 0x198 0x20 read-write 0x00000000 CSR40 CSR40 0 32 CSR41 CSR41 context swap registers 0x19C 0x20 read-write 0x00000000 CSR41 CSR41 0 32 CSR42 CSR42 context swap registers 0x1A0 0x20 read-write 0x00000000 CSR42 CSR42 0 32 CSR43 CSR43 context swap registers 0x1A4 0x20 read-write 0x00000000 CSR43 CSR43 0 32 CSR44 CSR44 context swap registers 0x1A8 0x20 read-write 0x00000000 CSR44 CSR44 0 32 CSR45 CSR45 context swap registers 0x1AC 0x20 read-write 0x00000000 CSR45 CSR45 0 32 CSR46 CSR46 context swap registers 0x1B0 0x20 read-write 0x00000000 CSR46 CSR46 0 32 CSR47 CSR47 context swap registers 0x1B4 0x20 read-write 0x00000000 CSR47 CSR47 0 32 CSR48 CSR48 context swap registers 0x1B8 0x20 read-write 0x00000000 CSR48 CSR48 0 32 CSR49 CSR49 context swap registers 0x1BC 0x20 read-write 0x00000000 CSR49 CSR49 0 32 CSR50 CSR50 context swap registers 0x1C0 0x20 read-write 0x00000000 CSR50 CSR50 0 32 CSR51 CSR51 context swap registers 0x1C4 0x20 read-write 0x00000000 CSR51 CSR51 0 32 CSR52 CSR52 context swap registers 0x1C8 0x20 read-write 0x00000000 CSR52 CSR52 0 32 CSR53 CSR53 context swap registers 0x1CC 0x20 read-write 0x00000000 CSR53 CSR53 0 32 SEC_HASH 0x520C0400 TAMP Tamper and backup registers TAMP 0x46007C00 0x0 0x400 registers TAMP Tamper global interrupts 4 CR1 CR1 TAMP control register 1 0x0 0x20 0x00000000 0xFFFFFFFF TAMP1E Tamper detection on TAMP_IN1 enable 0 1 read-write TAMP2E Tamper detection on TAMP_IN2 enable 1 1 read-write TAMP3E Tamper detection on TAMP_IN3 enable 2 1 read-write TAMP4E Tamper detection on TAMP_IN4 enable 3 1 read-write TAMP5E Tamper detection on TAMP_IN5 enable 4 1 read-write TAMP6E Tamper detection on TAMP_IN6 enable 5 1 read-write TAMP7E Tamper detection on TAMP_IN7 enable 6 1 read-write TAMP8E Tamper detection on TAMP_IN8 enable 7 1 read-write ITAMP1E Internal tamper 1 enable 16 1 read-write ITAMP2E Internal tamper 2 enable 17 1 read-write ITAMP3E Internal tamper 3 enable 18 1 read-write ITAMP5E Internal tamper 5 enable 20 1 read-write ITAMP6E Internal tamper 6 enable 21 1 read-write ITAMP7E Internal tamper 7 enable 22 1 read-write ITAMP8E Internal tamper 8 enable 23 1 read-write ITAMP9E Internal tamper 9 enable 24 1 read-write ITAMP11E Internal tamper 11 enable 26 1 read-write ITAMP12E Internal tamper 12 enable 27 1 read-write ITAMP13E Internal tamper 13 enable 28 1 read-write CR2 CR2 TAMP control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TAMP1NOER Tamper 1 no erase 0 1 read-write TAMP2NOER Tamper 2 no erase 1 1 read-write TAMP3NOER Tamper 3 no erase 2 1 read-write TAMP4NOER Tamper 4 no erase 3 1 read-write TAMP5NOER Tamper 5 no erase 4 1 read-write TAMP6NOER Tamper 6 no erase 5 1 read-write TAMP7NOER Tamper 7 no erase 6 1 read-write TAMP8NOER Tamper 8 no erase 7 1 read-write TAMP1MSK Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set. 16 1 read-write TAMP2MSK Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set. 17 1 read-write TAMP3MSK Tamper 3 mask The tamper 3 interrupt must not be enabled when TAMP3MSK is set. 18 1 read-write BKBLOCK Backup registers and device secrets access blocked 22 1 read-write BKERASE Backup registers and device secrets erase Writing '1ÂÂ to this bit reset the backup registers and device secrets(1). Writing 0 has no effect. This bit is always read as 0. 23 1 write-only TAMP1TRG Active level for tamper 1 input If TAMPFLTÂ =Â 00 Tamper 1 input rising edge and high level triggers a tamper detection event. If TAMPFLTÂ =Â 00 Tamper 1 input falling edge and low level triggers a tamper detection event. 24 1 read-write TAMP2TRG Active level for tamper 2 input If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection event. If TAMPFLTÂ =Â 00 Tamper 2 input falling edge and low level triggers a tamper detection event. 25 1 read-write TAMP3TRG Active level for tamper 3 input If TAMPFLTÂ =Â 00 Tamper 3 input rising edge and high level triggers a tamper detection event. If TAMPFLTÂ =Â 00 Tamper 3 input falling edge and low level triggers a tamper detection event. 26 1 read-write TAMP4TRG Active level for tamper 4 input (active mode disabled) If TAMPFLTÂ =Â 00 Tamper 4 input rising edge and high level triggers a tamper detection event. If TAMPFLTÂ =Â 00 Tamper 4 input falling edge and low level triggers a tamper detection event. 27 1 read-write TAMP5TRG Active level for tamper 5 input (active mode disabled) If TAMPFLTÂ =Â 00 Tamper 5 input rising edge and high level triggers a tamper detection event. If TAMPFLTÂ =Â 00 Tamper 5 input falling edge and low level triggers a tamper detection event. 28 1 read-write TAMP6TRG Active level for tamper 6 input (active mode disabled) If TAMPFLTÂ =Â 00 Tamper 6 input rising edge and high level triggers a tamper detection event. If TAMPFLTÂ =Â 00 Tamper 6 input falling edge and low level triggers a tamper detection event. 29 1 read-write TAMP7TRG Active level for tamper 7 input (active mode disabled) If TAMPFLTÂ =Â 00 Tamper 7 input rising edge and high level triggers a tamper detection event. If TAMPFLTÂ =Â 00 Tamper 7 input falling edge and low level triggers a tamper detection event. 30 1 read-write TAMP8TRG Active level for tamper 8 input (active mode disabled) If TAMPFLTÂ =Â 00 Tamper 8 input rising edge and high level triggers a tamper detection event. If TAMPFLTÂ =Â 00 Tamper 8 input falling edge and low level triggers a tamper detection event. 31 1 read-write CR3 CR3 TAMP control register 3 0x8 0x20 0x00000000 0xFFFFFFFF ITAMP1NOER Internal Tamper 1 no erase 0 1 read-write ITAMP2NOER Internal Tamper 2 no erase 1 1 read-write ITAMP3NOER Internal Tamper 3 no erase 2 1 read-write ITAMP5NOER Internal Tamper 5 no erase 4 1 read-write ITAMP6NOER Internal Tamper 6 no erase 5 1 read-write ITAMP7NOER Internal Tamper 7 no erase 6 1 read-write ITAMP8NOER Internal Tamper 8 no erase 7 1 read-write ITAMP9NOER Internal Tamper 9 no erase 8 1 read-write ITAMP11NOER Internal Tamper 11 no erase 10 1 read-write ITAMP12NOER Internal Tamper 12 no erase 11 1 read-write ITAMP13NOER Internal Tamper 13 no erase 12 1 read-write FLTCR FLTCR TAMP filter control register 0xC 0x20 0x00000000 0xFFFFFFFF TAMPFREQ Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled. 0 3 read-write TAMPFLT TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs. 3 2 read-write TAMPPRCH TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. 5 2 read-write TAMPPUDIS TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample. 7 1 read-write ATCR1 ATCR1 TAMP active tamper control register 1 0x10 0x20 0x00070000 0xFFFFFFFF TAMP1AM Tamper 1 active mode 0 1 read-write TAMP2AM Tamper 2 active mode 1 1 read-write TAMP3AM Tamper 3 active mode 2 1 read-write TAMP4AM Tamper 4 active mode 3 1 read-write TAMP5AM Tamper 5 active mode 4 1 read-write TAMP6AM Tamper 6 active mode 5 1 read-write TAMP7AM Tamper 7 active mode 6 1 read-write TAMP8AM Tamper 8 active mode 7 1 read-write ATOSEL1 Active tamper shared output 1 selection The selected output must be available in the package pinout 8 2 read-write ATOSEL2 Active tamper shared output 2 selection The selected output must be available in the package pinout 10 2 read-write ATOSEL3 Active tamper shared output 3 selection The selected output must be available in the package pinout 12 2 read-write ATOSEL4 Active tamper shared output 4 selection The selected output must be available in the package pinout. 14 2 read-write ATCKSEL Active tamper RTC asynchronous prescaler clock selection These bits selects the RTC asynchronous prescaler stage output.The selected clock is CK_ATPRE. fCK_ATPRE = fRTCCLK / 2ATCKSEL when (PREDIV_A+1) = 128. ... These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 ck_atpre cycles after all the active tampers are disable. 16 3 read-write ATPER Active tamper output change period The tamper output is changed every CK_ATPER = (2ATPER x CK_ATPRE) cycles. Refer to . 24 3 read-write ATOSHARE Active tamper output sharing TAMP_IN1 is compared with TAMPOUTSEL1 TAMP_IN2 is compared with TAMPOUTSEL2 TAMP_IN3 is compared with TAMPOUTSEL3 TAMP_IN4 is compared with TAMPOUTSEL4 TAMP_IN5 is compared with TAMPOUTSEL5 TAMP_IN6 is compared with TAMPOUTSEL6 TAMP_IN7 is compared with TAMPOUTSEL7 TAMP_IN8 is compared with TAMPOUTSEL8 30 1 read-write FLTEN Active tamper filter enable 31 1 read-write ATSEEDR ATSEEDR TAMP active tamper seed register 0x14 0x20 0x00000000 0xFFFFFFFF SEED Pseudo-random generator seed value This register must be written four times with 32-bit values to provide the 128-bit seed to the PRNG. Writing to this register automatically sends the seed value to the PRNG. 0 32 write-only ATOR ATOR TAMP active tamper output register 0x18 0x20 0x00000000 0xFFFFFFFF PRNG Pseudo-random generator value This field provides the values of the PRNG output. Because of potential inconsistencies due to synchronization delays, PRNG must be read at least twice. The read value is correct if it is equal to previous read value. This field can only be read when the APB is in secure mode. 0 8 read-only SEEDF Seed running flag This flag is set by hardware when a new seed is written in the TAMP_ATSEEDR. It is cleared by hardware when the PRNG has absorbed this new seed, and by system reset. The TAMP APB cock must not be switched off as long as SEEDF is set. 14 1 read-only INITS Active tamper initialization status This flag is set by hardware when the PRNG has absorbed the first 128-bit seed, meaning that the enabled active tampers are functional. This flag is cleared when the active tampers are disabled. 15 1 read-only ATCR2 ATCR2 TAMP active tamper control register 2 0x1C 0x20 0x00000000 0xFFFFFFFF ATOSEL1 Active tamper shared output 1 selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 8 3 read-write ATOSEL2 Active tamper shared output 2 selection The selected output must be available in the package pinout. Bits 12:11 are the mirror of ATOSEL2[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 11 3 read-write ATOSEL3 Active tamper shared output 3 selection The selected output must be available in the package pinout. Bits 15:14 are the mirror of ATOSEL3[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 14 3 read-write ATOSEL4 Active tamper shared output 4 selection The selected output must be available in the package pinout. Bits 18:17 are the mirror of ATOSEL2[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 17 3 read-write ATOSEL5 Active tamper shared output 5 selection The selected output must be available in the package pinout. 20 3 read-write ATOSEL6 Active tamper shared output 6 selection The selected output must be available in the package pinout. 23 3 read-write ATOSEL7 Active tamper shared output 7 selection The selected output must be available in the package pinout. 26 3 read-write ATOSEL8 Active tamper shared output 8 selection The selected output must be available in the package pinout. 29 3 read-write SECCFGR SECCFGR TAMP secure mode register 0x20 0x20 0x00000000 0xFFFFFFFF BKPRWSEC Backup registers read/write protection offset Protection zone 1 is defined for backup registers from TAMP_BKP0R to TAMP_BKPxR (x = BKPRWSEC-1, from 0 to 128). if TZEN=1, these backup registers can be read and written only with secure access. If TZEN=0: the protection zone 1 can be read and written with non-secure access. If BKPRWSEC = 0: there is no protection zone 1. If BKPRWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode. 0 8 read-write CNT1SEC Monotonic counter 1 secure protection 15 1 read-write BKPWSEC Backup registers write protection offset Protection zone 2 is defined for backup registers from TAMP_BKPyR (y = BKPRWSEC, from 0 to 128) to TAMP_BKPzR (z = BKPWSEC-1, from 0 to 128, BKPWSECÂ ÂÂ¥Â BKPRWSEC): if TZEN=1, these backup registers can be written only with secure access. They can be read with secure or non-secure access. Protection zone 3 defined for backup registers from TAMP_BKPtR (t = BKPWSEC, from 0 to 127). They can be read or written with secure or non-secure access. If TZEN=0: the protection zone 2 can be read and written with non-secure access. If BKPWSEC = 0 or if BKPWSECÂ ÂÂ¤Â BKPRWSEC: there is no protection zone 2. If BKPWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode. 16 8 read-write BHKLOCK Boot hardware key lock This bit can be read and can only be written to 1 by software. It is cleared by hardware together with the backup registers following a tamper detection event or when the readout protection (RDP) is disabled. 30 1 read-write TAMPSEC Tamper protection (excluding monotonic counters and backup registers) Note: Refer to for details on the read protection. 31 1 read-write PRIVCR PRIVCR TAMP privilege mode control register 0x24 0x20 0x00000000 0xFFFFFFFF CNT1PRIV Monotonic counter 1 privilege protection 15 1 read-write BKPRWPRIV Backup registers zone 1 privilege protection 29 1 read-write BKPWPRIV Backup registers zone 2 privilege protection 30 1 read-write TAMPPRIV Tamper privilege protection (excluding backup registers) Note: Refer to for details on the read protection. 31 1 read-write IER IER TAMP interrupt enable register 0x2C 0x20 0x00000000 0xFFFFFFFF TAMP1IE Tamper 1 interrupt enable 0 1 read-write TAMP2IE Tamper 2 interrupt enable 1 1 read-write TAMP3IE Tamper 3 interrupt enable 2 1 read-write TAMP4IE Tamper 4 interrupt enable 3 1 read-write TAMP5IE Tamper 5 interrupt enable 4 1 read-write TAMP6IE Tamper 6 interrupt enable 5 1 read-write TAMP7IE Tamper 7interrupt enable 6 1 read-write TAMP8IE Tamper 8 interrupt enable 7 1 read-write ITAMP1IE Internal tamper 1 interrupt enable 16 1 read-write ITAMP2IE Internal tamper 2 interrupt enable 17 1 read-write ITAMP3IE Internal tamper 3 interrupt enable 18 1 read-write ITAMP5IE Internal tamper 5 interrupt enable 20 1 read-write ITAMP6IE Internal tamper 6 interrupt enable 21 1 read-write ITAMP7IE Internal tamper 7 interrupt enable 22 1 read-write ITAMP8IE Internal tamper 8 interrupt enable 23 1 read-write ITAMP9IE Internal tamper 9 interrupt enable 24 1 read-write ITAMP11IE Internal tamper 11 interrupt enable 26 1 read-write ITAMP12IE Internal tamper 12 interrupt enable 27 1 read-write ITAMP13IE Internal tamper 13 interrupt enable 28 1 read-write SR SR TAMP status register 0x30 0x20 0x00000000 0xFFFFFFFF TAMP1F TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP1 input. 0 1 read-only TAMP2F TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP2 input. 1 1 read-only TAMP3F TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP3 input. 2 1 read-only TAMP4F TAMP4 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP4 input. 3 1 read-only TAMP5F TAMP5 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP5 input. 4 1 read-only TAMP6F TAMP6 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP6 input. 5 1 read-only TAMP7F TAMP7 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP7 input. 6 1 read-only TAMP8F TAMP8 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP8 input 7 1 read-only ITAMP1F Internal tamper 1 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 1. 16 1 read-only ITAMP2F Internal tamper 2 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 2. 17 1 read-only ITAMP3F Internal tamper 3 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3. 18 1 read-only ITAMP5F Internal tamper 5 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5. 20 1 read-only ITAMP6F Internal tamper 6 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. 21 1 read-only ITAMP7F Internal tamper 7 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 7. 22 1 read-only ITAMP8F Internal tamper 8 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 8. 23 1 read-only ITAMP9F Internal tamper 9 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 9. 24 1 read-only ITAMP11F Internal tamper 11 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 11. 26 1 read-only ITAMP12F Internal tamper 12 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 12. 27 1 read-only ITAMP13F Internal tamper 13 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 13. 28 1 read-only MISR MISR TAMP non-secure masked interrupt status register 0x34 0x20 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. 0 1 read-only TAMP2MF TAMP2 non-secure interrupt masked flag This flag is set by hardware when the tamper 2 non-secure interrupt is raised. 1 1 read-only TAMP3MF TAMP3 non-secure interrupt masked flag This flag is set by hardware when the tamper 3 non-secure interrupt is raised. 2 1 read-only TAMP4MF TAMP4 non-secure interrupt masked flag This flag is set by hardware when the tamper 4 non-secure interrupt is raised. 3 1 read-only TAMP5MF TAMP5 non-secure interrupt masked flag This flag is set by hardware when the tamper 5 non-secure interrupt is raised. 4 1 read-only TAMP6MF TAMP6 non-secure interrupt masked flag This flag is set by hardware when the tamper 6 non-secure interrupt is raised. 5 1 read-only TAMP7MF TAMP7 non-secure interrupt masked flag This flag is set by hardware when the tamper 7 non-secure interrupt is raised. 6 1 read-only TAMP8MF TAMP8 non-secure interrupt masked flag This flag is set by hardware when the tamper 8 non-secure interrupt is raised. 7 1 read-only ITAMP1MF Internal tamper 1 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 1 non-secure interrupt is raised. 16 1 read-only ITAMP2MF Internal tamper 2 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 2 non-secure interrupt is raised. 17 1 read-only ITAMP3MF Internal tamper 3 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 3 non-secure interrupt is raised. 18 1 read-only ITAMP5MF Internal tamper 5 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 5 non-secure interrupt is raised. 20 1 read-only ITAMP6MF Internal tamper 6 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 6 non-secure interrupt is raised. 21 1 read-only ITAMP7MF VCORE monitoring tamper non-secure interrupt masked flag This flag is set by hardware when the internal tamper 7 non-secure interrupt is raised. 22 1 read-only ITAMP8MF Internal tamper 8 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 8 non-secure interrupt is raised. 23 1 read-only ITAMP9MF internal tamper 9 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 9 non-secure interrupt is raised. 24 1 read-only ITAMP11MF internal tamper 11 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 11 non-secure interrupt is raised. 26 1 read-only ITAMP12MF internal tamper 12 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 12 non-secure interrupt is raised. 27 1 read-only ITAMP13MF internal tamper 13 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 13 non-secure interrupt is raised. 28 1 read-only SMISR SMISR TAMP secure masked interrupt status register 0x38 0x20 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 secure interrupt masked flag This flag is set by hardware when the tamper 1 secure interrupt is raised. 0 1 read-only TAMP2MF TAMP2 secure interrupt masked flag This flag is set by hardware when the tamper 2 secure interrupt is raised. 1 1 read-only TAMP3MF TAMP3 secure interrupt masked flag This flag is set by hardware when the tamper 3 secure interrupt is raised. 2 1 read-only TAMP4MF TAMP4 secure interrupt masked flag This flag is set by hardware when the tamper 4 secure interrupt is raised. 3 1 read-only TAMP5MF TAMP5 secure interrupt masked flag This flag is set by hardware when the tamper 5 secure interrupt is raised. 4 1 read-only TAMP6MF TAMP6 secure interrupt masked flag This flag is set by hardware when the tamper 6 secure interrupt is raised. 5 1 read-only TAMP7MF TAMP7 secure interrupt masked flag This flag is set by hardware when the tamper 7 secure interrupt is raised. 6 1 read-only TAMP8MF TAMP8 secure interrupt masked flag This flag is set by hardware when the tamper 8 secure interrupt is raised. 7 1 read-only ITAMP1MF Internal tamper 1 secure interrupt masked flag This flag is set by hardware when the internal tamper 1 secure interrupt is raised. 16 1 read-only ITAMP2MF Internal tamper 2 secure interrupt masked flag This flag is set by hardware when the internal tamper 2 secure interrupt is raised. 17 1 read-only ITAMP3MF Internal tamper 3 secure interrupt masked flag This flag is set by hardware when the internal tamper 3 secure interrupt is raised. 18 1 read-only ITAMP5MF Internal tamper 5 secure interrupt masked flag This flag is set by hardware when the internal tamper 5 secure interrupt is raised. 20 1 read-only ITAMP6MF Internal tamper 6 secure interrupt masked flag This flag is set by hardware when the internal tamper 6 secure interrupt is raised. 21 1 read-only ITAMP7MF VCORE monitoring tamper secure interrupt masked flag This flag is set by hardware when the internal tamper 7 secure interrupt is raised. 22 1 read-only ITAMP8MF Internal tamper 8 secure interrupt masked flag This flag is set by hardware when the internal tamper 8 secure interrupt is raised. 23 1 read-only ITAMP9MF internal tamper 9 secure interrupt masked flag This flag is set by hardware when the internal tamper 9 secure interrupt is raised. 24 1 read-only ITAMP11MF internal tamper 11 secure interrupt masked flag This flag is set by hardware when the internal tamper 11 secure interrupt is raised. 26 1 read-only ITAMP12MF internal tamper 12 secure interrupt masked flag This flag is set by hardware when the internal tamper 12 secure interrupt is raised. 27 1 read-only ITAMP13MF internal tamper 13 secure interrupt masked flag This flag is set by hardware when the internal tamper 13 secure interrupt is raised. 28 1 read-only SCR SCR TAMP status clear register 0x3C 0x20 0x00000000 0xFFFFFFFF CTAMP1F Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register. 0 1 write-only CTAMP2F Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register. 1 1 write-only CTAMP3F Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register. 2 1 write-only CTAMP4F Clear TAMP4 detection flag Writing 1 in this bit clears the TAMP4F bit in the TAMP_SR register. 3 1 write-only CTAMP5F Clear TAMP5 detection flag Writing 1 in this bit clears the TAMP5F bit in the TAMP_SR register. 4 1 write-only CTAMP6F Clear TAMP6 detection flag Writing 1 in this bit clears the TAMP6F bit in the TAMP_SR register. 5 1 write-only CTAMP7F Clear TAMP7 detection flag Writing 1 in this bit clears the TAMP7F bit in the TAMP_SR register. 6 1 write-only CTAMP8F Clear TAMP8 detection flag Writing 1 in this bit clears the TAMP8F bit in the TAMP_SR register. 7 1 write-only CITAMP1F Clear ITAMP1 detection flag Writing 1 in this bit clears the ITAMP1F bit in the TAMP_SR register. 16 1 write-only CITAMP2F Clear ITAMP2 detection flag Writing 1 in this bit clears the ITAMP2F bit in the TAMP_SR register. 17 1 write-only CITAMP3F Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register. 18 1 write-only CITAMP5F Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register. 20 1 write-only CITAMP6F Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register. 21 1 write-only CITAMP7F Clear ITAMP7 detection flag Writing 1 in this bit clears the ITAMP7F bit in the TAMP_SR register. 22 1 write-only CITAMP8F Clear ITAMP8 detection flag Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register. 23 1 write-only CITAMP9F Clear ITAMP9 detection flag Writing 1 in this bit clears the ITAMP9F bit in the TAMP_SR register. 24 1 write-only CITAMP11F Clear ITAMP11 detection flag Writing 1 in this bit clears the ITAMP11F bit in the TAMP_SR register. 26 1 write-only CITAMP12F Clear ITAMP12 detection flag Writing 1 in this bit clears the ITAMP12F bit in the TAMP_SR register. 27 1 write-only CITAMP13F Clear ITAMP13 detection flag Writing 1 in this bit clears the ITAMP13F bit in the TAMP_SR register. 28 1 write-only COUNT1R COUNT1R TAMP monotonic counter 1 register 0x40 0x20 0x00000000 0xFFFFFFFF COUNT This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value. 0 32 read-only ERCFGR ERCFGR TAMP erase configuration register 0x54 0x20 0x00000000 0xFFFFFFFF ERCFG0 Configurable device secrets configuration 0 1 read-write 32 0x4 0-31 BKP%sR BKP%sR TAMP backup %s register 0x100 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write SEC_TAMP 0x56007C00 MDF1 Multi-function digital filter MDF 0x40025000 0x0 0x1000 registers MDF1_FLT0 MDF1 filter 0 global interrupt 102 MDF1_FLT1 MDF1 filter 1 global interrupt 103 MDF1_FLT2 MDF1 filter 2 global interrupt 104 MDF1_FLT3 MDF1 filter 3 global interrupt 105 MDF1_FLT4 MDF1 filter 4 global interrupt 121 MDF1_FLT5 MDF1 filter 5 global interrupt 122 GCR GCR MDF global control register 0x0 0x20 read-write 0x00000000 TRGO TRGO 0 1 ILVNB ILVNB 4 4 CKGCR CKGCR MDF clock generator control register 0x4 0x20 read-write 0x00000000 CKGDEN CKGDEN 0 1 CCK0EN CCK0EN 1 1 CCK1EN CCK1EN 2 1 CKGMOD CKGMOD 4 1 CCK0DIR CCK0DIR 5 1 CCK1DIR CCK1DIR 6 1 TRGSENS TRGSENS 8 1 TRGSRC TRGSRC 12 4 CCKDIV CCKDIV 16 4 PROCDIV PROCDIV 24 7 CKGACTIVE CKGACTIVE 31 1 6 0x80 0-5 FLT%s Cluster FLT%s, containing SITF?CR, BSMX?CR, DFLT?CR, DFLT?CICR, DFLT?RSFR, DFLT?INTR, OLD?CR, OLD?THLR, OLD?THHR, DLY?CR, SCD?CR, DFLT?IER, DFLT?ISR, OEC?CR, SNPS?DR, DFLT?DR 0x80 SITFCR SITF0CR This register is used to control the serial interfaces (SITFx). 0x0 0x20 0x00001F00 SITFEN Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled 0 1 read-write SCKSRC Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 2 read-write SITFMOD Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 2 read-write STH Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 5 read-write SITFACTIVE Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured. 31 1 read-only BSMXCR BSMX0CR This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. 0x4 0x20 0x00000000 BSSEL Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 5 read-write BSMXACTIVE BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. 31 1 read-only DFLTCR DFLT0CR This register is used to control the digital filter x. 0x8 0x20 0x00000000 DFLTEN Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , 0 1 write-only DMAEN DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write FTH RXFIFO Threshold selection Set and cleared by software. 2 1 read-write ACQMOD Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 read-write TRGSENS Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 1 read-write TRGSRC Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 4 read-write SNPSFMT Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 16 1 read-write NBDIS Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 20 8 read-write DFLTRUN Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running 30 1 read-only DFLTACTIVE Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active 31 1 read-only DFLTCICR DFLT0CICR This register is used to control the main CIC filter. 0xC 0x20 read-write 0x00000000 DATSRC Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 CICMOD Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 MCICD CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 9 SCALE Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits 20 6 DFLTRSFR DFLT0RSFR This register is used to control the reshape and HPF filters. 0x10 0x20 read-write 0x00000000 RSFLTBYP Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 1 RSFLTD Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 1 HPFBYP High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 7 1 HPFC High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 2 DFLTINTR DFLT0INTR This register is used to the integrator (INT) settings. 0x14 0x20 read-write 0x00000000 INTDIV Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 INTVAL Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 7 OLDCR OLD0CR This register is used to configure the Out-of Limit Detector function. 0x18 0x20 0x00000000 OLDEN Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. 0 1 read-write THINB Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write BKOLD Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write ACICN OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 2 read-write ACICD OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 17 5 read-write OLDACTIVE OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. 31 1 read-only OLDTHLR OLD0THLR This register is used for the adjustment of the Out-off Limit low threshold. 0x1C 0x20 read-write 0x00000000 OLDTHL OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 26 OLDTHHR OLD0THHR This register is used for the adjustment of the Out-off Limit high threshold. 0x20 0x20 read-write 0x00000000 OLDTHH OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details 0 26 DLYCR DLY0CR This register is used for the adjustment stream delays. 0x24 0x20 0x00000000 SKPDLY Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, 0 7 read-write SKPBF Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. 31 1 read-only SCDCR SCD0CR This register is used for the adjustment stream delays. 0x28 0x20 0x00000000 SCDEN Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, 0 1 read-write BKSCD Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write SCDT Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 8 read-write SCDACTIVE SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. 31 1 read-only DFLTIER DFLT0IER This register is used for allowing or not the events to generate an interrupt. 0x2C 0x20 read-write 0x00000000 FTHIE RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled 0 1 DOVRIE Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled 1 1 SSDRIE Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled 2 1 OLDIE Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled 4 1 SSOVRIE Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled 7 1 read-write SCDIE Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled 8 1 read-write SATIE Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled 9 1 read-write CKABIE Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled 10 1 RFOVRIE Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled 11 1 DFLTISR DFLT0ISR MDF DFLT0 interrupt status register 0 0x30 0x20 0x00000000 FTHF FTHF 0 1 read-only DOVRF Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. 1 1 read-write SSDRF Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on , writing 0 has no effect. - 1: Reading 1 means that a new data is available on , writing 1 clears this flag. 2 1 read-write RXNEF RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. 3 1 read-only OLDF Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. 4 1 read-write THLF Low threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was higher than OLDTHL when the last OLD event occurred. - 1: The signal was lower than OLDTHL when the last OLD event occurred. 5 1 read-only THHF High threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH when the last OLD event occurred. - 1: The signal was higher than OLDTHH when the last OLD event occurred. 6 1 read-only SSOVRF Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. 7 1 read-write SCDF Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. 8 1 read-write SATF Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. 9 1 read-write CKABF Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. 10 1 read-write RFOVRF Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. 11 1 read-write OECCR OEC0CR This register contains the offset compensation value. 0x34 0x20 read-write 0x00000000 OFFSET Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. 0 26 read-write SNPSDR SNPS0DR This register is used to read the data processed by each digital filter in snapshot mode. 0x6C 0x20 read-only 0x00000000 MCICDC Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) 0 9 EXTSDR Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). 9 7 SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 DFLTDR DFLT0DR This register is used to read the data processed by each digital filter. 0x70 0x20 read-only 0x00000000 DR Data processed by digital filter. 8 24 SEC_MDF1 0x50025000 ADF1 ADF1 ADF 0x46024000 0x0 0x1000 registers ADF1_FLT0 ADF1 filter 0 global interrupt 112 GCR GCR ADF Global Control Register 0x0 0x20 read-write 0x00000000 TRGO Trigger output control Set by software and reset by 0 1 CKGCR CKGCR ADF clock generator control register 0x4 0x20 read-write 0x00000000 CKGACTIVE Clock generator active flag 31 1 PROCDIV Divider to control the serial interface clock 24 7 CCKDIV Divider to control the ADF_CCK clock 16 4 TRGSRC Digital filter trigger signal selection 12 4 TRGSENS CKGEN trigger sensitivity selection 8 1 CCK1DIR ADF_CCK1 direction 6 1 CCK0DIR ADF_CCK0 direction 5 1 CKGMOD Clock generator mode 4 1 CCK1EN ADF_CCK1 clock enable 2 1 CCK0EN ADF_CCK0 clock enable 1 1 CKGDEN CKGEN dividers enable 0 1 SITF0CR SITF0CR ADF serial interface control register 0 0x80 0x20 read-write 0x00001F00 SITFACTIVE SITFACTIVE 31 1 STH STH 8 5 SITFMOD SITFMOD 4 2 SCKSRC SCKSRC 1 2 SITFEN SITFEN 0 1 BSMX0CR BSMX0CR ADF bitstream matrix control register 0 0x84 0x20 read-write 0x00000000 BSMXACTIVE BSMX active flag 31 1 BSSEL Bitstream selection 0 5 DFLT0CR DFLT0CR ADF digital filter control register 0 0x88 0x20 read-write 0x00000000 DFLTACTIVE DFLT0 active flag 31 1 DFLTRUN DFLT0 run status flag 30 1 NBDIS Number of samples to be discarded 20 8 TRGSRC DFLT0 trigger signal selection 12 4 ACQMOD DFLT0 trigger mode 4 3 FTH RXFIFO threshold selection 2 1 DMAEN DMA requests enable 1 1 DFLTEN DFLT0 enable 0 1 DFLT0CICR DFLT0CICR ADF digital filer configuration register 0 0x8C 0x20 read-write 0x00000000 SCALE Scaling factor selection 20 6 MCICD CIC decimation ratio selection 8 9 CICMOD Select the CIC order 4 3 DATSRC Source data for the digital filter 0 2 DFLT0RSFR DFLT0RSFR ADF reshape filter configuration register 0 0x90 0x20 read-write 0x00000000 HPFC High-pass filter cut-off frequency 8 2 HPFBYP High-pass filter bypass 7 1 RSFLTD Reshaper filter decimation ratio 4 1 RSFLTBYP Reshaper filter bypass 0 1 DLY0CR DLY0CR ADF delay control register 0 0xA4 0x20 read-write 0x00000000 SKPBF Skip busy flag 31 1 SKPDLY Delay to apply to a bitstream 0 7 DFLT0IER DFLT0IER ADF DFLT0 interrupt enable register 0xAC 0x20 read-write 0x00000000 SDLVLIE SAD sound-level value ready enable 13 1 SDDETIE Sound activity detection interrupt enable 12 1 RFOVRIE Reshape filter overrun interrupt enable 11 1 CKABIE Clock absence detection interrupt enable 10 1 SATIE Saturation detection interrupt enable 9 1 DOVRIE Data overflow interrupt enable 1 1 FTHIE RXFIFO threshold interrupt enable 0 1 DFLT0ISR DFLT0ISR ADF DFLT0 interrupt status register 0 0xB0 0x20 0x00000000 SDLVLF Sound level value ready flag 13 1 read-write SDDETF Sound activity detection flag 12 1 read-write RFOVRF Reshape filter overrun detection flag 11 1 read-write CKABF Clock absence detection flag 10 1 read-write SATF Saturation detection flag 9 1 read-write RXNEF RXFIFO not empty flag 3 1 read-only DOVRF Data overflow flag 1 1 read-write FTHF RXFIFO threshold flag 0 1 read-only SADCR SADCR ADF SAD control register 0xB8 0x20 0x00000000 SADACTIVE SAD Active flag 31 1 read-only SADMOD SAD working mode 12 2 read-write FRSIZE Frame size 8 3 read-write HYSTEN Hysteresis enable 7 1 read-write SADST SAD state 4 2 read-only DETCFG Sound trigger event configuration 3 1 read-write DATCAP Data capture mode 1 2 read-write SADEN Sound activity detector enable 0 1 read-write SADCFGR SADCFGR ADF SAD configuration register 0xBC 0x20 read-write 0x00000000 ANMIN ANMIN 16 13 HGOVR Hangover time window 12 3 LFRNB LFRNB 8 3 ANSLP ANSLP 4 3 SNTHR SNTHR 0 4 SADSDLVR SADSDLVR ADF SAD sound level register 0xC0 0x20 read-only 0x00000000 SDLVL SDLVL 0 15 SADANLVR SADANLVR ADF SAD ambient noise level register 0xC4 0x20 read-only 0x00000000 ANLVL ANLVL 0 15 DFLT0DR DFLT0DR ADF digital filter data register 0 0xF0 0x20 read-only 0x00000000 DR DR 8 24 SEC_ADF1 0x56024000 LPGPIO1 LPGPIO1 LPGPIO 0x46020000 0x0 0x400 registers MODER MODER LPGPIO port mode register 0x0 0x20 read-write 0x00000000 16 0x1 0-15 MODE%s MODE%s 0 1 IDR IDR LPGPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 ID%s ID%s 0 1 ODR ODR LPGPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 OD%s OD%s 0 1 BSRR BSRR LPGPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BR%s BR%s 16 1 16 0x1 0-15 BS%s BS%s 0 1 BRR BRR LPGPIO port bit reset register 0x28 0x20 write-only 0x00000000 16 0x1 0-15 BR%s BR%s 0 1 SEC_LPGPIO1 0x56020000 OCTOSPIM OCTOSPI I/O manager OctoSPI 0x420C4000 0x0 0x400 registers CR CR control register 0x0 0x20 read-write 0x00000000 REQ2ACK_TIME REQ to ACK time 16 8 MUXEN Multiplexed mode enable 0 1 P1CR P1CR OCTOSPI I/O manager Port 1 configuration register 0x4 0x20 read-write 0x03010111 IOHSRC IOHSR 25 2 IOHEN IOHEN 24 1 IOLSRC IOLSRC 17 2 IOLEN IOLEN 16 1 NCSSRC NCSSRC 9 1 NCSEN NCSEN 8 1 DQSSRC DQSSRC 5 1 DQSEN DQSEN 4 1 CLKSRC CLKSRC 1 1 CLKEN CLKEN 0 1 P2CR P2CR OCTOSPI I/O manager Port 2 configuration register 0x8 0x20 read-write 0x07050333 IOHSRC IOHSR 25 2 IOHEN IOHEN 24 1 IOLSRC IOLSRC 17 2 IOLEN IOLEN 16 1 NCSSRC NCSSRC 9 1 NCSEN NCSEN 8 1 DQSSRC DQSSRC 5 1 DQSEN DQSEN 4 1 CLKSRC CLKSRC 1 1 CLKEN CLKEN 0 1 SEC_OCTOSPIM 0x520C4000 ADC1 ADC1 ADC 0x42028000 0x0 0x400 registers ADC1 ADC1 (16 bits) global interrupt 37 ISR ISR ADC interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF ADRDY ADC ready This bit is set by hardware after the ADC has been enabled (bit ADENÂ =Â 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0 1 read-write ADRDYR read NotReady ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) 0 Ready ADC is ready to start conversion 1 ADRDYW write Clear Clear the ADC ready flag 1 EOSMP End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase. 1 1 read-write EOSMPR read NotAtEnd Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) 0 AtEnd End of sampling phase reached 1 EOSMPW write Clear Clear the sampling phase flag 1 EOC End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register 2 1 read-write EOCR read NotComplete Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software) 0 Complete Regular channel conversion complete 1 EOCW write Clear Clear the regular channel conversion flag 1 EOS End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it. 3 1 read-write EOSR read NotComplete Regular conversions sequence not complete (or the flag event was already acknowledged and cleared by software) 0 Complete Regular conversions sequence complete 1 EOSW write Clear Clear the regular conversion sequence flag 1 OVR ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it. 4 1 read-write OVRR read NoOverrun No overrun occurred (or the flag event was already acknowledged and cleared by software) 0 Overrun Overrun has occurred 1 OVRW write Clear Clear the overrun flag 1 JEOC Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register 5 1 read-write JEOCR read NotComplete Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software) 0 Complete Injected channel conversion complete 1 JEOCW write Clear Clear the injected channel conversion flag 1 JEOS Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it. 6 1 read-write JEOSR read NotComplete Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software) 0 Complete Injected conversions sequence complete 1 JEOSW write Clear Clear the injected conversion sequence flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 read-write AWD1R read NoEvent No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software) 0 Event Analog watchdog x event occurred 1 AWD1W write Clear Clear the analog watchdog x event flag 1 LDORDY ADC voltage regulator ready This bit is set by hardware. It indicates that the ADC internal supply is ready. The ADC is available after tADCVREG_SETUP time. 12 1 read-only LDORDYR Disabled ADC voltage regulator disabled 0 Enabled ADC voltage regulator enabled 1 IER IER ADC interrupt enable register 0x4 0x20 0x00000000 0xFFFFFFFF ADRDYIE ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 1 read-write ADRDYIE Disabled ADRDY interrupt disabled 0 Enabled ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. 1 EOSMPIE End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 1 1 read-write EOSMPIE Disabled EOSMP interrupt disabled 0 Enabled EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. 1 EOCIE End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 2 1 read-write EOCIE Disabled EOC interrupt disabled 0 Enabled EOC interrupt enabled. An interrupt is generated when the EOC bit is set. 1 EOSIE End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 3 1 read-write EOSIE Disabled EOS interrupt disabled 0 Enabled EOS interrupt enabled. An interrupt is generated when the EOS bit is set. 1 OVRIE Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 4 1 read-write OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. 1 JEOCIE End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: Software is allowed to write this bit only when JADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 5 1 read-write JEOCIE Disabled JEOC interrupt disable 0 Enabled JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. 1 JEOSIE End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: Software is allowed to write this bit only when JADSTARTÂ =Â 0 (which ensures that no injected conversion is ongoing). 6 1 read-write JEOSIE Disabled JEOS interrupt disabled 0 Enabled JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set. 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 read-write AWD1IE Disabled Analog watchdog x interrupt disabled 0 Enabled Analog watchdog x interrupt enabled 1 CR CR ADC control register 0x8 0x20 0x20000000 0xFFFFFFFF ADEN ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCALÂ =Â 0, JADSTARTÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator) 0 1 read-write ADENR read Disabled ADC is disabled 0 Enabled ADC is enabled 1 ADENW write Enabled Enable the ADC 1 ADDIS ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADENÂ =Â 1 and both ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing) 1 1 read-write ADDISR read NotOngoing No ADDIS command ongoing 0 InProgress An ADDIS command is in progress 1 ADDISW write Disable Disable the ADC 1 ADSTART ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN[1:0], a conversion starts immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: Â in Single conversion mode (CONTÂ =Â 0, DISCENÂ =Â 0) when software trigger is selected (EXTEN[1:0]Â =Â 0x0): at the assertion of the end of regular conversion sequence (EOS) flag. In Discontinuous conversion mode (CONTÂ =Â 0, DISCENÂ =Â 1), when the software trigger is selected (EXTEN[1:0]Â =Â 0x0): at the end of conversion (EOC) flag. in all other cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADENÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and there is no pending request to disable the ADC) In Auto-injection mode (JAUTOÂ =Â 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) 2 1 read-write ADSTARTR read NotActive No ADC regular conversion is ongoing 0 Active ADC is operating and eventually converting a regular channel 1 ADSTARTW write Start Start regular conversions 1 JADSTART ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN[1:0], a conversion starts immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (JEXTSELÂ =Â 0x0): at the assertion of the end of injected conversion sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time as JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADENÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and there is no pending request to disable the ADC). In Auto-injection mode (JAUTOÂ =Â 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) 3 1 read-write JADSTARTR read NotActive No ADC injected conversion is ongoing 0 Active ADC is operating and eventually converting an injected channel 1 JADSTARTW write Start Start injected conversions 1 ADSTP ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTARTÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In Auto-injection mode (JAUTOÂ =Â 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). 4 1 read-write ADSTPR read NotStopping No ADC stop regular conversion command ongoing 0 Stopping ADSTP command is in progress 1 ADSTPW write StopConversion Stop regular conversions ongoing 1 JADSTP ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTARTÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC). In Auto-injection mode (JAUTOÂ =Â 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP) 5 1 read-write JADSTPR read NotStopped No ADC stop injected conversion command ongoing 0 Stopped ADSTP command is in progress 1 JADSTPW write Stop Stop injected conversions ongoing 1 ADCALLIN Linearity calibration This bit is set and cleared by software to enable the linearity calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCALÂ =Â 0, JADSTARTÂ =Â 0, JADSTPÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). 16 1 read-write ADCALLIN Disabled Writing ADCAL launches a calibration without the linearity calibration 0 Enabled Writing ADCAL launches a calibration with he linearity calibration 1 CALINDEX Calibration factor This bitfield controls the calibration factor to be read or written. Calibration index 0 is dedicated to single-ended and differential offsets, calibration index 1 to 7 to the linearity calibration factors, and index 8 to the internal offset: Others: Reserved, must not be used Note: ADC_CALFACT2[31:0] correspond to the location of CALINDEX[3:0] calibration factor data (see for details). 24 4 read-write CALINDEX OffsetCalFactor Offset calibration factor 0 CalFactor1 Calibration factor 1 1 CalFactor2 Calibration factor 2 2 CalFactor3 Calibration factor 3 3 CalFactor4 Calibration factor 4 4 CalFactor5 Calibration factor 5 5 CalFactor6 Calibration factor 6 6 CalFactor7 Calibration factor 7 and (write access only) internal offset 7 InternalOffset Internal offset (read access only) 8 CalibrationMode Calibration mode selection 9 ADVREGEN ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCALÂ =Â 0, JADSTARTÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). 28 1 read-write ADVREGEN Disabled ADC voltage regulator disabled 0 Enabled ADC voltage regulator enabled 1 DEEPPWD Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCALÂ =Â 0, JADSTARTÂ =Â 0, JADSTPÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). 29 1 read-write DEEPPWD Disabled ADC not in deep-power down 0 Enabled ADC in deep-power down 1 ADCAL ADC calibration This bit is set by software to start the ADC calibration. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADENÂ =Â 0. 31 1 read-write ADCALR read NotCalibrating Calibration complete 0 Calibrating Calibration in progress 1 ADCALW write StartCalibration Calibrate the ADC 1 CFGR1 CFGR1 ADC configuration register 0xC 0x20 0x80000000 0xFFFFFFFF DMNGT Data management configuration This bit is set and cleared by software to select how the ADC interface output data are managed. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 2 read-write DMNGT DR Store output data in DR only 0 DMA_OneShot DMA One Shot Mode selected 1 DFSDM DFSDM mode selected 2 DMA_Circular DMA Circular Mode selected 3 RES Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 2 2 read-write RES FourteenBit 14 bits 0 TwelveBit 12 bits 1 TenBit 10 bits 2 EightBit 8 bits 3 EXTSEL External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Refer to the ADC external trigger for regular channels in signals for details on trigger mapping. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 5 5 read-write EXTSEL TIM1_OC1 tim1_oc1 0 TIM1_OC2 tim1_oc2 1 TIM1_OC3 tim1_oc3 2 TIM2_OC2 tim2_oc2 3 TIM3_TRGO tim3_trgo 4 TIM4_OC4 tim4_oc4 5 EXTI11 exti11 6 TIM8_TRGO tim8_trgo 7 TIM8_TRGO2 tim8_trgo2 8 TIM1_TRGO tim1_trgo 9 TIM1_TRGO2 tim1_trgo2 10 TIM2_TRGO tim2_trgo 11 TIM4_TRGO tim4_trgo 12 TIM6_TRGO tim6_trgo 13 TIM15_TRGO tim15_trgo 14 TIM3_OC4 tim3_oc4 15 EXTI15 exti15 16 LPTIM1_CH1 lptim1_ch1 18 LPTIM2_CH1 lptim2_ch1 19 LPTIM3_CH1 lptim3_ch1 20 LPTIM4_OUT lptim4_out 21 EXTEN External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 10 2 read-write EXTEN Disabled Hardware trigger detection disabled (conversions can be launched by software) 0 RisingEdge Hardware trigger detection on the rising edge 1 FallingEdge Hardware trigger detection on the falling edge 2 BothEdges Hardware trigger detection on both the rising and falling edges 3 OVRMOD Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 12 1 read-write OVRMOD Preserve ADC_DR register is preserved with the old data when an overrun is detected 0 Overwrite ADC_DR register is overwritten with the last conversion result when an overrun is detected 1 CONT Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 13 1 read-write CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 AUTDLY Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 14 1 read-write AUTDLY Disabled Auto-delayed conversion mode off 0 Enabled Auto-delayed conversion mode on 1 DISCEN Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCENÂ =Â 1 and CONTÂ =Â 1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 16 1 read-write DISCEN Disabled Discontinuous mode for regular channels disabled 0 Enabled Discontinuous mode for regular channels enabled 1 DISCNUM Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 17 3 read-write DISCNUM n1 1 channel 0 n2 2 channels 1 n3 3 channels 2 n4 4 channels 3 n5 5 channels 4 n6 6 channels 5 n7 7 channels 6 n8 8 channels 7 JDISCEN Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTARTÂ =Â 0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. 20 1 read-write JDISCEN Disabled Discontinuous mode on injected channels disabled 0 Enabled Discontinuous mode on injected channels enabled 1 AWD1SGL Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 22 1 read-write AWD1SGL AllChannels Analog watchdog 1 enabled on all channels 0 SingleChannel Analog watchdog 1 enabled on a single channel 1 AWD1EN Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 23 1 read-write AWD1EN Disabled Analog watchdog 1 disabled on regular channels 0 Enabled Analog watchdog 1 enabled on regular channels 1 JAWD1EN Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTARTÂ =Â 0 (which ensures that no injected conversion is ongoing). 24 1 read-write JAWD1EN Disabled Analog watchdog 1 disabled on injected channels 0 Enabled Analog watchdog 1 enabled on injected channels 1 JAUTO Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no regular nor injected conversion is ongoing). 25 1 read-write JAUTO Disabled Automatic injected group conversion disabled 0 Enabled Automatic injected group conversion enabled 1 AWD1CH Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved, must not be used Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 26 5 read-write 0 19 CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 0x00000000 0xFFFFFFFF ROVSE Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 0 1 read-write ROVSE Disabled Regular oversampling disabled 0 Enabled Regular oversampling enabled 1 JOVSE Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 1 1 read-write JOVSE Disabled Injected oversampling disabled 0 Enabled Injected oversampling enabled 1 OVSS Oversampling right shift This bit field is set and cleared by software to define the right shifting applied to the raw oversampling result. Others: Reserved, must not be used. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). 5 4 read-write 0 11 TROVS Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 9 1 read-write TROVS Automatic All oversampled conversions for a channel are done consecutively following a trigger 0 Triggered Each oversampled conversion for a channel needs a new trigger 1 ROVSM Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 10 1 read-write ROVSM Continued When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 0 Resumed When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) 1 BULB Bulb sampling mode This bit is set and cleared by software to select the bulb sampling mode. SMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 13 1 read-write BULB Disabled Bulb sampling mode disabled 0 Enabled Bulb sampling mode enabled. The sampling period starts just after the previous end of the conversion. 1 SWTRIG Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 14 1 read-write SWTRIG Disabled Software trigger starts the conversion for sampling time control trigger mode 0 Enabled Software trigger starts the sampling for sampling time control trigger mode 1 SMPTRIG Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN[1:0] bits must be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN[1:0] bits is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 15 1 read-write SMPTRIG Disabled Sampling time control trigger mode disabled 0 Enabled Sampling time control trigger mode enabled 1 OSR Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 2: 3x ... 1023: 1024x Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 16 10 read-write 0 1023 LFTRIG Low-frequency trigger This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 27 1 read-write LFTRIG Disabled Low-frequency trigger mode disabled 0 Enabled Low-frequency trigger mode enabled 1 LSHIFT Left shift factor This bitfield is set and cleared by software to define the left shifting applied to the final result with or without oversampling. Note: The software is allowed to write this bit only when ADSTARTÂ = 0 (which ensures that no conversion is ongoing). 28 4 read-write 0 15 SMPR1 SMPR1 ADC sample time register 1 0x14 0x20 0x00000000 0xFFFFFFFF 10 0x3 0-9 SMP%s Channel %s sample time selection 0 3 read-write SMP0 Cycles5 5 ADC clock cycles 0 Cycles6 6 ADC clock cycles 1 Cycles12 12 ADC clock cycles 2 Cycles20 20 ADC clock cycles 3 Cycles36 36 ADC clock cycles 4 Cycles68 68 ADC clock cycles 5 Cycles391 391 ADC clock cycles 6 Cycles814 814 ADC clock cycles 7 SMPR2 SMPR2 ADC sample time register 2 0x18 0x20 0x00000000 0xFFFFFFFF 10 0x3 10-19 SMP%s Channel %s sample time selection 0 3 read-write PCSEL PCSEL ADC channel preselection register 0x1C 0x20 0x00000000 0xFFFFFFFF PCSEL0 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 1 read-write PCSEL0 NotPreselected Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result. 0 Preselected Input channel x is preselected for conversion 1 PCSEL1 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 1 1 read-write PCSEL2 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 2 1 read-write PCSEL3 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 3 1 read-write PCSEL4 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 4 1 read-write PCSEL5 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 5 1 read-write PCSEL6 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 6 1 read-write PCSEL7 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 7 1 read-write PCSEL8 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 8 1 read-write PCSEL9 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 9 1 read-write PCSEL10 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 10 1 read-write PCSEL11 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 11 1 read-write PCSEL12 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 12 1 read-write PCSEL13 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 13 1 read-write PCSEL14 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 14 1 read-write PCSEL15 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 15 1 read-write PCSEL16 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 16 1 read-write PCSEL17 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 17 1 read-write PCSEL18 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 18 1 read-write PCSEL19 Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 19 1 read-write SQR1 SQR1 ADC regular sequence register 1 0x30 0x20 0x00000000 0xFFFFFFFF L Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 (which ensures that no regular conversion is ongoing). 0 4 read-write 0 15 4 0x6 1-4 SQ%s %s conversion in regular sequence 6 5 read-write 0 31 SQR2 SQR2 ADC regular sequence register 2 0x34 0x20 0x00000000 0xFFFFFFFF 5 0x6 5-9 SQ%s %s conversion in regular sequence 0 5 read-write SQR3 SQR3 ADC regular sequence register 3 0x38 0x20 0x00000000 0xFFFFFFFF 5 0x6 10-14 SQ%s %s conversion in regular sequence 0 5 read-write SQR4 SQR4 ADC regular sequence register 4 0x3C 0x20 0x00000000 0xFFFFFFFF 2 0x6 15-16 SQ%s %s conversion in regular sequence 0 5 read-write DR DR ADC regular Data Register 0x40 0x20 0x00000000 0xFFFFFFFF RDATA Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in . 0 32 read-only JSQR JSQR ADC injected sequence register 0x4C 0x20 0x00000000 0xFFFFFFFF JL Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTARTÂ =Â 0 (which ensures that no injected conversion is ongoing. 0 2 read-write 0 3 JEXTSEL External trigger selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Refer to the ADC external trigger for injected channels in internal signals for details on trigger mapping. Note: The software is allowed to write these bits only when JADSTARTÂ =Â 0 (which ensures that no injected conversion is ongoing. 2 5 read-write JEXTSEL TIM1_TRGO tim1_trgo 0 TIM1_OC4 tim1_oc4 1 TIM2_TRGO tim2_trgo 2 TIM2_OC1 tim2_oc1 3 TIM3_OC4 tim3_oc4 4 TIM4_TRGO tim4_trgo 5 EXTI15 exti15 6 TIM8_OC4 tim8_oc4 7 TIM1_TRGO2 tim1_trgo2 8 TIM8_TRGO tim8_trgo 9 TIM8_TRGO2 tim8_trgo2 10 TIM3_OC3 tim3_oc3 11 TIM3_TRGO tim3_trgo 12 TIM3_OC1 tim3_oc1 13 TIM6_TRGO tim6_trgo 14 TIM15_TRGO tim15_trgo 15 LPTIM1_CH2 lptim1_ch2 16 LPTIM2_CH2 lptim2_ch2 17 LPTIM3_CH1 lptim3_ch1 18 LPTIM4_OUT1 lptim4_out1 19 JEXTEN External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTARTÂ =Â 0 (which ensures that no injected conversion is ongoing. 7 2 read-write JEXTEN Disabled Hardware trigger detection disabled (conversions can be launched by software) 0 RisingEdge Hardware trigger detection on the rising edge 1 FallingEdge Hardware trigger detection on the falling edge 2 BothEdges Hardware trigger detection on both the rising and falling edges 3 4 0x6 1-4 JSQ%s %s conversion in injected sequence 9 5 read-write 0 31 4 0x4 1-4 OFR%s OFR%s ADC offset register 0x60 0x20 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (regular or injected). The channel to which the data offset y applies must be programmed to the OFFSETy_CH[4:0] bits. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[21:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If several offsets (OFFSETy) point to the same channel, only the offset with the lowest y value is considered for the subtraction. For example, if OFFSET1_CH[4:0]Â =Â 4 and OFFSET2_CH[4:0]Â =Â 4, this is OFFSET1[25:0] that is subtracted when converting channel 4. 0 24 read-write 0 16777215 POSOFF offset sign This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 24 1 read-write POSOFF Negative Negative offset 0 Positive Positive offset 1 USAT Unsigned saturation enable This bit is written by software to enable or disable the unsigned saturation feature. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 25 1 read-write USAT Disabled Offset is subtracted maintaining data integrity and keeping converted data size 0 Enabled Offset is subtracted and result is saturated to maintain converted data size 1 SSAT Signed saturation enable This bit is written by software to enable or disable the Signed saturation feature. (see OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT) for details). Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 26 1 read-write SSAT Disabled Offset is subtracted maintaining data integrity and extending converted data size (9-bit and 15-bit signed format) 0 Enabled Offset is subtracted and result is saturated to maintain converted data size 1 OFFSET_CH Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into OFFSETy[25:0] bits applies. Note: The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If OFFSETy_EN bit is set, it is not allowed to select the same channel in different ADC_OFRy registers. 27 5 read-write 0 31 GCOMP GCOMP ADC gain compensation register 0x70 0x20 0x00000000 0xFFFFFFFF GCOMPCOEFF Gain compensation coefficient These bits are set and cleared by software to program the gain compensation coefficient. ... ... The coefficient is divided by 4096 to get the gain factor ranging from 0 to 3.999756. Note: This gain compensation is only applied when GCOMP bit of ADCx_CFGR2 register is 1. 0 14 read-write 0 16383 GCOMP Gain compensation mode This bit is set and cleared by software to enable the gain compensation mode. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 31 1 read-write GCOMP Disabled Regular ADC operating mode 0 Enabled Gain compensation enabled and applied to all channels 1 4 0x4 1-4 JDR%s JDR%s ADC injected data register 0x80 0x20 0x00000000 0xFFFFFFFF JDATA Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in . 0 32 read-only 0 4294967295 AWD2CR AWD2CR ADC analog watchdog 2 configuration register 0xA0 0x20 0x00000000 0xFFFFFFFF 20 0x1 0-19 AWD2CH%s Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 1 AWD2CH Disabled ADC analog input channel x is not monitored by AWDy 0 Enabled ADC analog input channel x is monitored by AWDy 1 AWD3CR AWD3CR ADC analog watchdog 3 configuration register 0xA4 0x20 0x00000000 0xFFFFFFFF 20 0x1 0-19 AWD3CH%s Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel-i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel-i is monitored by AWD3 When AWD3CH[19:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 1 AWD3CH Disabled ADC analog input channel x is not monitored by AWDy 0 Enabled ADC analog input channel x is monitored by AWDy 1 LTR1 LTR1 ADC watchdog threshold register 1 0xA8 0x20 0x00000000 0xFFFFFFFF LTR1 Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). 0 25 read-write 0 33554431 HTR1 HTR1 ADC watchdog threshold register 1 0xAC 0x20 0x01FFFFFF 0xFFFFFFFF HTR1 Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). 0 25 read-write 0 33554431 AWDFILT1 Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 29 3 read-write AWDFILT1 NoFiltering No filtering 0 Detections2 Two consecutive detections generates an AWDx flag or an interrupt 1 Detections3 Three consecutive detections generates an AWDx flag or an interrupt 2 Detections4 Four consecutive detections generates an AWDx flag or an interrupt 3 Detections5 Five consecutive detections generates an AWDx flag or an interrupt 4 Detections6 Six consecutive detections generates an AWDx flag or an interrupt 5 Detections7 Seven consecutive detections generates an AWDx flag or an interrupt 6 Detections8 Eight consecutive detections generates an AWDx flag or an interrupt 7 LTR2 LTR2 ADC watchdog lower threshold register 2 0xB0 0x20 0x00000000 0xFFFFFFFF LTR2 Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). 0 25 read-write 0 33554431 HTR2 HTR2 ADC watchdog higher threshold register 2 0xB4 0x20 0x01FFFFFF 0xFFFFFFFF HTR2 Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). 0 25 read-write 0 33554431 LTR3 LTR3 ADC watchdog lower threshold register 3 0xB8 0x20 0x00000000 0xFFFFFFFF LTR3 Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). 0 25 read-write 0 33554431 HTR3 HTR3 ADC watchdog higher threshold register 3 0xBC 0x20 0x01FFFFFF 0xFFFFFFFF HTR3 Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). 0 25 read-write 0 33554431 DIFSEL DIFSEL ADC differential mode selection register 0xC0 0x20 0x00000000 0xFFFFFFFF 20 0x1 0-19 DIFSEL%s Differential mode for channel %s 0 1 DIFSEL0 SingleEnded ADC analog input channel x is configured in single-ended mode 0 Differential ADC analog input channel x is configured in differential mode 1 CALFACT CALFACT ADC user control register 0xC4 0x20 0x00000000 0xFFFFFFFF I_APB_ADDR Delayed write access address This bitfield contains the address that is being written during delayed write accesses. 0 8 read-only 0 255 I_APB_DATA Delayed write access data This bitfield contains the data that are being written during delayed write accesses. 8 8 read-only 0 255 VALIDITY Delayed write access status bit This bit indicates the communication status between the ADC digital and analog blocks. 16 1 read-only VALIDITYR InProgress Operation still in progress 0 Complete Operation complete 1 LATCH_COEF Calibration factor latch enable bit This bit latches the calibration factor in the CALFACT[31:0] bits. 24 1 read-write LATCH_COEF NoEffect No effect 0 Latch Calibration factor latched in the analog block on LATCH_COEF bit transition from 0 to 1. Prior to latching the calibration factor, CALFACT[31:0] bits must be programmed with the content of CALINDEX[3:0] bits. 1 CAPTURE_COEF Calibration factor capture enable bit This bit enables the internal calibration factor capture. 25 1 read-write CAPTURE_COEF Disabled Calibration factor not captured 0 Enabled Calibration factor available in CALFACT[31:0] bits, the calibration factor index being defined by CALINDEX[3:0] bits 1 CALFACT2 CALFACT2 ADC calibration factor register 0xC8 0x20 0x00000000 0xFFFFFFFF CALFACT Linearity or offset calibration factor These bits can be written either by hardware or by software. They contain the 32-bit offset or linearity calibration factor. When CAPTURE_COEF is set to 1, the calibration factor of the analog block is read back and stored in CALFACT[31:0], indexed by CALINDEX[3:0] bits. When LATCH_COEF is set to 1, the calibration factor of the analog block is updated with the value programmed in CALFACT[31:0], indexed by CALINDEX[3:0] bits. To read all calibration factors, perform nine accesses to the ADC_CALFACT2 register. To write all calibration factors, perform eight accesses to the ADC_CALFACT2 register. Note: The software is allowed to write these bits only when ADENÂ =Â 1, ADSTARTÂ =Â 0 and JADSTARTÂ =Â 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). 0 32 read-write 0 4294967295 SEC_ADC1 0x52028000 ADC4 ADC4 ADC 0x46021000 0x0 0x400 registers ADC4 ADC4 (12 bits) global interrupt 113 ISR ISR ADC interrupt and status register 0x0 0x20 read-write 0x00000000 LDORDY LDORDY 12 1 LDORDYR read Disabled ADC voltage regulator disabled 0 Enabled ADC voltage regulator enabled 1 EOCAL EOCAL 11 1 EOCALR read NotComplete Calibration is not complete 0 Complete Calibration is complete 1 EOCALW write Clear Clear the end of calibration flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 AWD1R read NoEvent No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software) 0 Event Analog watchdog x event occurred 1 AWD1W write Clear Clear the analog watchdog x event flag 1 OVR OVR 4 1 OVRR read NoOverrun No overrun occurred (or the flag event was already acknowledged and cleared by software) 0 Overrun Overrun has occurred 1 OVRW write Clear Clear the overrun flag 1 EOS EOS 3 1 EOSR read NotComplete Regular conversions sequence not complete (or the flag event was already acknowledged and cleared by software) 0 Complete Regular conversions sequence complete 1 EOSW write Clear Clear the regular conversion sequence flag 1 EOC EOC 2 1 EOCR read NotComplete Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software) 0 Complete Regular channel conversion complete 1 EOCW write Clear Clear the regular channel conversion flag 1 EOSMP EOSMP 1 1 EOSMPR read NotAtEnd Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) 0 AtEnd End of sampling phase reached 1 EOSMPW write Clear Clear the sampling phase flag 1 ADRDY ADRDY 0 1 ADRDYR read NotReady ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) 0 Ready ADC is ready to start conversion 1 ADRDYW write Clear Clear the ADC ready flag 1 IER IER ADC interrupt enable register 0x4 0x20 read-write 0x00000000 LDORDYIE LDORDYIE 12 1 LDORDYIE Disabled LDO ready interrupt disabled 0 Enabled LDO ready interrupt enabled. An interrupt is generated when the LDO output is ready. 1 EOCALIE EOCALIE 11 1 EOCALIE Disabled End of calibration interrupt disabled 0 Enabled End of calibration interrupt enabled 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 AWD1IE Disabled Analog watchdog x interrupt disabled 0 Enabled Analog watchdog x interrupt enabled 1 OVRIE OVRIE 4 1 OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. 1 EOSIE EOSIE 3 1 EOSIE Disabled EOS interrupt disabled 0 Enabled EOS interrupt enabled. An interrupt is generated when the EOS bit is set. 1 EOCIE EOCIE 2 1 EOCIE Disabled EOC interrupt disabled 0 Enabled EOC interrupt enabled. An interrupt is generated when the EOC bit is set. 1 EOSMPIE EOSMPIE 1 1 EOSMPIE Disabled EOSMP interrupt disabled 0 Enabled EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. 1 ADRDYIE ADRDYIE 0 1 ADRDYIE Disabled ADRDY interrupt disabled 0 Enabled ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. 1 CR CR ADC control register 0x8 0x20 0x00000000 ADCAL ADCAL 31 1 read-write ADCALR read NotCalibrating Calibration complete 0 Calibrating Calibration in progress 1 ADCALW write StartCalibration Calibrate the ADC 1 ADVREGEN ADVREGEN 28 1 read-write ADVREGEN Disabled ADC voltage regulator disabled 0 Enabled ADC voltage regulator enabled 1 ADSTP ADSTP 4 1 read-write ADSTPR read NotStopping No ADC stop regular conversion command ongoing 0 Stopping ADSTP command is in progress 1 ADSTPW write StopConversion Stop regular conversions ongoing 1 ADSTART ADSTART 2 1 read-write ADSTARTR read NotActive No ADC regular conversion is ongoing 0 Active ADC is operating and eventually converting a regular channel 1 ADSTARTW write Start Start regular conversions 1 ADDIS ADDIS 1 1 read-write ADDISR read NotOngoing No ADDIS command ongoing 0 InProgress An ADDIS command is in progress 1 ADDISW write Disable Disable the ADC 1 ADEN ADEN 0 1 read-write ADENR read Disabled ADC is disabled 0 Enabled ADC is enabled 1 ADENW write Enabled Enable the ADC 1 CFGR1 CFGR1 ADC configuration register 0xC 0x20 read-write 0x00000000 AWD1CH AWD1CH 26 5 0 19 AWD1EN AWD1EN 23 1 AWD1EN Disabled Analog watchdog 1 disabled on regular channels 0 Enabled Analog watchdog 1 enabled on regular channels 1 AWD1SGL AWD1SGL 22 1 AWD1SGL AllChannels Analog watchdog 1 enabled on all channels 0 SingleChannel Analog watchdog 1 enabled on a single channel 1 CHSELRMOD CHSELRMOD 21 1 CHSELRMOD BitPerInput Each bit of the ADC_CHSELR register enables an input 0 Sequence ADC_CHSELR register is able to sequence up to 8 channels 1 DISCEN DISCEN 16 1 DISCEN Disabled Discontinuous mode for regular channels disabled 0 Enabled Discontinuous mode for regular channels enabled 1 WAIT WAIT 14 1 WAIT Disabled Wait conversion mode off 0 Enabled Wait conversion mode on 1 CONT CONT 13 1 CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 OVRMOD OVRMOD 12 1 OVRMOD Preserve ADC_DR register is preserved with the old data when an overrun is detected 0 Overwrite ADC_DR register is overwritten with the last conversion result when an overrun is detected 1 EXTEN EXTEN 10 2 EXTEN Disabled Hardware trigger detection disabled (conversions can be launched by software) 0 RisingEdge Hardware trigger detection on the rising edge 1 FallingEdge Hardware trigger detection on the falling edge 2 BothEdges Hardware trigger detection on both the rising and falling edges 3 EXTSEL EXTSEL 6 3 EXTSEL TIM1_TRGO2 tim1_trgo2 0 TIM1_OC4 tim1_oc4 1 TIM2_TRGO tim2_trgo 2 TIM15_TRGO tim15_trgo 3 TIM6_TRGO tim6_trgo 4 LPTIM1_CH1 lptim1_ch1 5 LPTIM3_CH2 lptim3_ch2 6 EXTI15 exti15 7 ALIGN ALIGN 5 1 ALIGN Right Right alignment 0 Left Left alignment 1 SCANDIR SCANDIR 4 1 SCANDIR Upward Upward scan sequence (from CHSEL0 to CHSEL23) 0 Downward Downward scan sequence (from CHSEL23 to CHSEL0) 1 RES RES 2 2 RES TwelveBit 12 bits 0 TenBit 10 bits 1 EightBit 8 bits 2 SixBit 6 bits 3 DMACFG DMACFG 1 1 DMACFG OneShot One-shot mode selected 0 Circular Circular mode selected 1 DMAEN DMAEN 0 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 LFTRIG LFTRIG 29 1 LFTRIG Disabled Low-frequency trigger mode disabled 0 Enabled Low-frequency trigger mode enabled 1 TOVS TOVS 9 1 TOVS Automatic All oversampled conversions for a channel are done consecutively following a trigger 0 Triggered Each oversampled conversion for a channel needs a new trigger 1 OVSS OVSS 5 4 0 8 OVSR OVSR 2 3 0 7 OVSE OVSE 0 1 OVSE Disabled Oversampler disabled 0 Enabled Oversampler enabled 1 SMPR SMPR ADC sample time register 0x14 0x20 read-write 0x00000000 24 0x1 0-23 SMPSEL%s Channel-%s sampling time selection 8 1 SMPSEL0 SMP1 Sampling time of channel x uses the setting of SMP1 register. 0 SMP2 Sampling time of channel x uses the setting of SMP2 register. 1 2 0x4 1-2 SMP%s Sampling time selection %s 0 3 SMP1 Cycles1_5 1.5 ADC clock cycles 0 Cycles3_5 3.5 ADC clock cycles 1 Cycles7_5 7.5 ADC clock cycles 2 Cycles12_5 12.5 ADC clock cycles 3 Cycles19_5 19.5 ADC clock cycles 4 Cycles39_5 39.5 ADC clock cycles 5 Cycles79_5 79.5 ADC clock cycles 6 Cycles814_5 814.5 ADC clock cycles 7 AWD1TR AWD1TR ADC watchdog threshold register 0x20 0x20 read-write 0x0FFF0000 HT1 HT1 16 12 0 4095 LT1 LT1 0 12 0 4095 AWD2TR AWD2TR ADC watchdog threshold register 0x24 0x20 read-write 0x0FFF0000 HT2 HT2 16 12 0 4095 LT2 LT2 0 12 0 4095 CHSELR0 CHSELRMOD0 ADC channel selection register [alternate] 0x28 0x20 read-write 0x00000000 24 0x1 0-23 CHSEL%s Channel-%s selection 0 1 CHSEL0 Disabled Input channel x is not selected for conversion 0 Enabled Input channel x is selected for conversion 1 CHSELR1 CHSELRMOD1 ADC channel selection register [alternate] CHSELR0 0x28 0x20 read-write 0x00000000 8 0x4 1-8 SQ%s %s conversion of the sequence 0 4 SQ1 Channel0 CH0 0 Channel1 CH1 1 Channel2 CH2 2 Channel3 CH3 3 Channel4 CH4 4 Channel5 CH5 5 Channel6 CH6 6 Channel7 CH7 7 Channel8 CH8 8 Channel9 CH9 9 Channel10 CH10 10 Channel11 CH11 11 Channel12 CH12 12 Channel13 CH13 13 Channel14 CH14 14 NoChannel No channel selected (End of sequence) 15 AWD3TR AWD3TR ADC watchdog threshold register 0x2C 0x20 read-write 0x0FFF0000 HT3 HT3 16 12 0 4095 LT3 LT3 0 12 0 4095 DR DR ADC data register 0x40 0x20 read-only 0x00000000 DATA DATA 0 16 PWRR PWR ADC data register 0x44 0x20 read-write 0x00000000 VREFSECSMP VREFSECSMP 3 1 VREFSECSMP Disabled VREF+ second sample disabled 0 Enabled VREF+ second sample enabled 1 VREFPROT VREFPROT 2 1 VREFPROT Disabled VREF+ protection disabled 0 Enabled VREF+ protection enabled 1 DPD DPD 1 1 DPD Disabled Deep-power-down mode disabled 0 Enabled Deep-power-down mode enabled 1 AUTOFF AUTOFF 0 1 AUTOFF Disabled Auto-off mode disabled 0 Enabled Auto-off mode enabled 1 AWD2CR AWD2CR ADC Analog Watchdog 2 Configuration register 0xA0 0x20 read-write 0x00000000 24 0x1 0-23 AWD2CH%s AWD2CH%s 0 1 AWD2CH0 Disabled ADC analog input channel x is not monitored by AWDy 0 Enabled ADC analog input channel x is monitored by AWDy 1 AWD3CR AWD3CR ADC Analog Watchdog 3 Configuration register 0xA4 0x20 read-write 0x00000000 24 0x1 0-23 AWD3CH%s AWD3CH%s 0 1 AWD3CH0 Disabled ADC analog input channel x is not monitored by AWDy 0 Enabled ADC analog input channel x is monitored by AWDy 1 CALFACT CALFACT ADC Calibration factor 0xC4 0x20 read-write 0x00000000 CALFACT CALFACT 0 7 0 127 OR OR ADC option register 0xD0 0x20 read-write 0x00000000 CHN21SEL CHN21SEL 0 1 CHN21SEL Out1 dac1_out1 selected 0 Out2 dac1_out2 selected 1 CCR CCR ADC common configuration register 0x308 0x20 read-write 0x00000000 VBATEN VBATEN 24 1 VBATEN Disabled VBAT channel disabled 0 Enabled VBAT channel enabled 1 VSENSESEL VSENSESEL 23 1 VSENSESEL Disabled Temperature sensor channel disabled 0 Enabled Temperature sensor channel enabled 1 VREFEN VREFEN 22 1 VREFEN Disabled VREFINT channel disabled 0 Enabled VREFINT channel enabled 1 PRESC PRESC 18 4 PRESC Div1 Input ADC clock not divided 0 Div2 Input ADC clock divided by 2 1 Div4 Input ADC clock divided by 4 2 Div6 Input ADC clock divided by 6 3 Div8 Input ADC clock divided by 8 4 Div10 Input ADC clock divided by 10 5 Div12 Input ADC clock divided by 12 6 Div16 Input ADC clock divided by 16 7 Div32 Input ADC clock divided by 32 8 Div64 Input ADC clock divided by 64 9 Div128 Input ADC clock divided by 128 10 Div256 Input ADC clock divided by 256 11 SEC_ADC4 0x56021000 ADC12_Common ADC common registers ADC 0x42028300 0x0 0xC registers CCR CCR ADC_CCR system control register 0x8 0x20 0x00000000 0xFFFFFFFF PRESC ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCALÂ =Â 0, JADSTARTÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). 18 4 read-write PRESC Div1 Input ADC clock not divided 0 Div2 Input ADC clock divided by 2 1 Div4 Input ADC clock divided by 4 2 Div6 Input ADC clock divided by 6 3 Div8 Input ADC clock divided by 8 4 Div10 Input ADC clock divided by 10 5 Div12 Input ADC clock divided by 12 6 Div16 Input ADC clock divided by 16 7 Div32 Input ADC clock divided by 32 8 Div64 Input ADC clock divided by 64 9 Div128 Input ADC clock divided by 128 10 Div256 Input ADC clock divided by 256 11 VREFEN VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCALÂ =Â 0, JADSTARTÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). 22 1 read-write VREFEN Disabled VREFINT channel disabled 0 Enabled VREFINT channel enabled 1 VSENSESEL Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCALÂ =Â 0, JADSTARTÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). 23 1 read-write VSENSESEL Disabled Temperature sensor channel disabled 0 Enabled Temperature sensor channel enabled 1 VBATEN VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCALÂ =Â 0, JADSTARTÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). 24 1 read-write VBATEN Disabled VBAT channel disabled 0 Enabled VBAT channel enabled 1 SEC_ADC12 0x52028300 FMC FMC FMC 0x420D0400 0x0 0x400 registers FMC FMC global interrupt 75 BCR1 BCR1 SRAM/NOR-Flash chip-select control register for bank 1 0x0 0x20 read-write 0x000030DB MBKEN Memory bank enable bit 0 1 MBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 MUXEN Address/data multiplexing enable bit 1 1 MUXEN Disabled Address/Data non-multiplexed 0 Enabled Address/Data multiplexed on databus 1 MTYP Memory type 2 2 MTYP SRAM SRAM memory type 0 PSRAM PSRAM (CRAM) memory type 1 Flash NOR Flash/OneNAND Flash 2 MWID Memory data bus width 4 2 MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 FACCEN Flash access enable 6 1 FACCEN Disabled Corresponding NOR Flash memory access is disabled 0 Enabled Corresponding NOR Flash memory access is enabled 1 BURSTEN Burst enable bit 8 1 BURSTEN Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 WAITPOL Wait signal polarity bit 9 1 WAITPOL ActiveLow NWAIT active low 0 ActiveHigh NWAIT active high 1 WAITCFG Wait timing configuration 11 1 WAITCFG BeforeWaitState NWAIT signal is active one data cycle before wait state 0 DuringWaitState NWAIT signal is active during wait state 1 WREN Write enable bit 12 1 WREN Disabled Write operations disabled for the bank by the FMC 0 Enabled Write operations enabled for the bank by the FMC 1 WAITEN Wait enable bit 13 1 WAITEN Disabled Values inside the FMC_BWTR are taken into account 0 Enabled NWAIT signal enabled 1 EXTMOD Extended mode enable 14 1 EXTMOD Disabled Values inside the FMC_BWTR are not taken into account 0 Enabled Values inside the FMC_BWTR are taken into account 1 ASYNCWAIT Wait signal during asynchronous transfers 15 1 ASYNCWAIT Disabled Wait signal not used in asynchronous mode 0 Enabled Wait signal used even in asynchronous mode 1 CPSIZE CRAM Page Size 16 3 CPSIZE NoBurstSplit No burst split when crossing page boundary 0 Bytes128 128 bytes CRAM page size 1 Bytes256 256 bytes CRAM page size 2 Bytes512 512 bytes CRAM page size 3 Bytes1024 1024 bytes CRAM page size 4 CBURSTRW Write burst enable 19 1 CBURSTRW Disabled Write operations are always performed in asynchronous mode 0 Enabled Write operations are performed in synchronous mode 1 CCLKEN Continuous clock enable 20 1 WFDIS Write FIFO disable 21 1 NBLSET Byte lane (NBL) setup 22 2 FMCEN FMC controller enable 31 1 3 0x8 2-4 BCR%s BCR%s SRAM/NOR-Flash chip-select control register for bank %s 0x8 0x20 read-write 0x000030D2 MBKEN Memory bank enable bit 0 1 MUXEN Address/data multiplexing enable bit 1 1 MTYP Memory type 2 2 MWID Memory data bus width 4 2 FACCEN Flash access enable 6 1 BURSTEN Burst enable bit 8 1 WAITPOL Wait signal polarity bit 9 1 WAITCFG Wait timing configuration 11 1 WREN Write enable bit 12 1 WAITEN Wait enable bit 13 1 EXTMOD Extended mode enable 14 1 ASYNCWAIT Wait signal during asynchronous transfers 15 1 CPSIZE CRAM Page Size 16 3 CBURSTRW Write burst enable 19 1 NBLSET Byte lane (NBL) setup 22 2 4 0x8 1-4 BTR%s BTR%s SRAM/NOR-Flash chip-select timing register for bank %s 0x4 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration 0 4 0 15 ADDHLD Address-hold phase duration 4 4 1 15 DATAST Data-phase duration 8 8 1 255 BUSTURN Bus turnaround phase duration 16 4 0 15 CLKDIV Clock divide ratio (for FMC_CLK signal) 20 4 1 15 DATLAT Data latency for synchronous memory 24 4 0 15 ACCMOD Access mode 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATAHLD Data hold phase duration 30 2 4 0x8 1-4 BWTR%s BWTR%s SRAM/NOR-Flash write timing registers %s 0x104 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration 0 4 0 15 ADDHLD Address-hold phase duration 4 4 1 15 DATAST Data-phase duration 8 8 1 255 BUSTURN Bus turnaround phase duration 16 4 0 15 ACCMOD Access mode 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATAHLD Data hold phase duration 30 2 PCSCNTR PCSCNTR PSRAM chip select counter register 0x20 0x20 read-write 0x00000000 CSCOUNT Chip select counter 0 16 4 0x1 1-4 CNTB%sEN Counter Bank %s enable 16 1 PCR PCR NAND Flash control registers 0x80 0x20 read-write 0x00000018 PWAITEN Wait feature enable bit 1 1 PWAITEN Disabled Wait feature disabled 0 Enabled Wait feature enabled 1 PBKEN NAND Flash memory bank enable bit 2 1 PBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 PTYP Memory type 3 1 PTYP NANDFlash NAND Flash 1 PWID Data bus width 4 2 PWID Bits8 External memory device width 8 bits 0 Bits16 External memory device width 16 bits 1 ECCEN ECC computation logic enable bit 6 1 ECCEN Disabled ECC logic is disabled and reset 0 Enabled ECC logic is enabled 1 TCLR CLE to RE delay 9 4 0 15 TAR ALE to RE delay 13 4 0 15 ECCPS ECC page size 17 3 ECCPS Bytes256 ECC page size 256 bytes 0 Bytes512 ECC page size 512 bytes 1 Bytes1024 ECC page size 1024 bytes 2 Bytes2048 ECC page size 2048 bytes 3 Bytes4096 ECC page size 4096 bytes 4 Bytes8192 ECC page size 8192 bytes 5 SR SR status and interrupt register 0x84 0x20 0x00000040 IRS Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 0 1 read-write IRS DidNotOccur Interrupt rising edge did not occur 0 Occurred Interrupt rising edge occurred 1 ILS Interrupt high-level status The flag is set by hardware and reset by software. 1 1 read-write ILS DidNotOccur Interrupt high-level did not occur 0 Occurred Interrupt high-level occurred 1 IFS Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 2 1 read-write IFS DidNotOccur Interrupt falling edge did not occur 0 Occurred Interrupt falling edge occurred 1 IREN Interrupt rising edge detection enable bit 3 1 read-write IREN Disabled Interrupt rising edge detection request disabled 0 Enabled Interrupt rising edge detection request enabled 1 ILEN Interrupt high-level detection enable bit 4 1 read-write ILEN Disabled Interrupt high-level detection request disabled 0 Enabled Interrupt high-level detection request enabled 1 IFEN Interrupt falling edge detection enable bit 5 1 read-write IFEN Disabled Interrupt falling edge detection request disabled 0 Enabled Interrupt falling edge detection request enabled 1 FEMPT FIFO empty. Read-only bit that provides the status of the FIFO 6 1 read-only FEMPT NotEmpty FIFO not empty 0 Empty FIFO empty 1 PMEM PMEM Common memory space timing register 0x88 0x20 read-write 0xFCFCFCFC MEMSET Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space: 0 8 0 254 MEMWAIT Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 1 254 MEMHOLD Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space: 16 8 1 254 MEMHIZ Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions: 24 8 0 254 PATT PATT The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature). 0x8C 0x20 read-write 0xFCFCFCFC ATTSET Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 0 8 0 254 ATTWAIT Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 1 254 ATTHOLD Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 16 8 1 254 ATTHIZ Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 24 8 0 254 ECCR ECCR This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. 0x94 0x20 read-only 0x00000000 ECC ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields. 0 32 0 4294967295 SEC_FMC 0x520D0400 RNG Random number generator RNG 0x420C0800 0x0 0x400 registers RNG RNG global interrupt 94 CR CR control register 0x0 0x20 read-write 0x00000000 CONFIGLOCK RNG Config Lock 31 1 CONFIGLOCK Enabled Writes to the RNG_CR configuration bits [29:4] are allowed 0 Disabled Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset 1 CONDRST Conditioning soft reset 30 1 RNG_CONFIG1 RNG configuration 1 20 6 RNG_CONFIG1 ConfigA Recommended value for config A (NIST certifiable) 15 ConfigB Recommended value for config B (not NIST certifiable) 24 CLKDIV Clock divider factor 16 4 CLKDIV Div1 Internal RNG clock after divider is similar to incoming RNG clock 0 Div2 Divide RNG clock by 2^1 1 Div4 Divide RNG clock by 2^2 2 Div8 Divide RNG clock by 2^3 3 Div16 Divide RNG clock by 2^4 4 Div32 Divide RNG clock by 2^5 5 Div64 Divide RNG clock by 2^6 6 Div128 Divide RNG clock by 2^7 7 Div256 Divide RNG clock by 2^8 8 Div512 Divide RNG clock by 2^9 9 Div1024 Divide RNG clock by 2^10 10 Div2048 Divide RNG clock by 2^11 11 Div4096 Divide RNG clock by 2^12 12 Div8192 Divide RNG clock by 2^13 13 Div16384 Divide RNG clock by 2^14 14 Div32768 Divide RNG clock by 2^15 15 RNG_CONFIG2 RNG configuration 2 13 3 RNG_CONFIG2 ConfigA_B Recommended value for config A and B 0 NISTC Non NIST compliant 12 1 NISTC Default Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used 0 Custom Custom values for NIST compliant RNG 1 RNG_CONFIG3 RNG configuration 3 8 4 RNG_CONFIG3 ConfigB Recommended value for config B (not NIST certifiable) 0 ConfigA Recommended value for config A (NIST certifiable) 13 ARDIS Auto reset disable 7 1 CED Clock error detection 5 1 CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 IE Interrupt Enable 3 1 IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 RNGEN True random number generator enable 2 1 RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 SR SR status register 0x4 0x20 0x00000000 CEIS Clock error interrupt status 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 SECS Seed error current status 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CECS Clock error current status 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 DRDY Data ready 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 DR DR data register 0x8 0x20 read-only 0x00000000 RNDATA Random data 0 32 0 4294967295 HTCR HTCR health test control register 0x10 0x20 read-write 0x00006274 HTCFG health test configuration 0 32 HTCFG Recommended Recommended value for RNG certification (0x0000_AA74) 43636 Magic Magic number to be written before any write (0x1759_0ABC) 391711420 SEC_RNG 0x520C0800 AES Advanced encryption standard hardware accelerator AES 0x420C0000 0x0 0x400 registers AES AES global interrupt 93 CR CR control register 0x0 0x20 read-write 0x00000000 IPRST IPRST 31 1 KMOD KMOD 24 2 KMOD NormalKey Normal key mode. Key registers are freely usable 0 SharedKey Shared key mode. If shared key mode is properly initialized in SAES peripheral, the AES peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in AES key registers when BUSY bit is cleared and KEYVALID is set in the AES_SR register. Key error flag KEIF is set otherwise in the AES_ISR register 2 NPBLB NPBLB 20 4 0 15 KEYSIZE KEYSIZE 18 1 KEYSIZE AES128 128 0 AES256 256 1 CHMOD_2 CHMOD_2 16 1 CHMOD_2 CHMOD Mode as per CHMOD (ECB, CBC, CTR, GCM) 0 CCM Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB) 1 GCMPH GCMPH 13 2 GCMPH Init Init phase 0 Header Header phase 1 Payload Payload phase 2 Final Final Phase 3 DMAOUTEN Enable DMA management of data output phase 12 1 DMAOUTEN Disabled Disable DMA Output 0 Enabled Enabled DMA Output 1 DMAINEN Enable DMA management of data input phase 11 1 DMAINEN Disabled Disable DMA Input 0 Enabled Enable DMA Input 1 CHMOD AES chaining mode 5 2 CHMOD ECB Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1 0 CBC Cipher-block chaining (CBC) 1 CTR Counter mode (CTR) 2 GCM Galois counter mode (GCM) and Galois message authentication code (GMAC) 3 MODE AES operating mode 3 2 MODE Mode1 Mode 1: encryption 0 Mode2 Mode 2: key derivation (or key preparation for ECB/CBC decryption) 1 Mode3 Mode 3: decryption 2 Mode4 Mode 4: key derivation then single decryption 3 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 DATATYPE None Word 0 HalfWord Half-word (16-bit) 1 Byte Byte (8-bit) 2 Bit Bit 3 EN AES enable 0 1 EN Disabled Disable AES 0 Enabled Enable AES 1 SR SR status register 0x4 0x20 read-only 0x00000000 KEYVALID Key Valid flag 7 1 BUSY BUSY 3 1 BUSY Idle Idle 0 Busy Busy 1 WRERR Write error flag 2 1 WRERR NoError Write error not detected 0 Error Write error detected 1 RDERR Read error flag 1 1 RDERR NoError Read error not detected 0 Error Read error detected 1 CCF Computation complete flag 0 1 CCF Complete Computation complete 0 NotComplete Computation not complete 1 DINR DINR data input register 0x8 0x20 write-only 0x00000000 DIN Input data word 0 32 0 4294967295 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 DOUT Output data word 0 32 0 4294967295 KEYR0 KEYR0 key register 0 0x10 0x20 write-only 0x00000000 KEY Cryptographic key, bits [31:0] 0 32 0 4294967295 KEYR1 KEYR1 key register 1 0x14 0x20 write-only 0x00000000 KEY Cryptographic key, bits [63:32] 0 32 0 4294967295 KEYR2 KEYR2 key register 2 0x18 0x20 write-only 0x00000000 KEYR Cryptographic key, bits [95:64] 0 32 0 4294967295 KEYR3 KEYR3 key register 3 0x1C 0x20 write-only 0x00000000 AES_KEYR3 Cryptographic key, bits [127:96] 0 32 0 4294967295 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 IVI Initialization vector input, bits [31:0] 0 32 0 4294967295 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 IVI Initialization vector input, bits [63:32] 0 32 0 4294967295 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 IVI Initialization vector input, bits [95:64] 0 32 0 4294967295 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization vector input, bits [127:96] 0 32 0 4294967295 KEYR4 KEYR4 key register 4 0x30 0x20 write-only 0x00000000 KEY Cryptographic key, bits [159:128] 0 32 0 4294967295 KEYR5 KEYR5 key register 5 0x34 0x20 write-only 0x00000000 KEY Cryptographic key, bits [191:160] 0 32 0 4294967295 KEYR6 KEYR6 key register 6 0x38 0x20 write-only 0x00000000 KEY Cryptographic key, bits [223:192] 0 32 0 4294967295 KEYR7 KEYR7 key register 7 0x3C 0x20 write-only 0x00000000 KEY Cryptographic key, bits [255:224] 0 32 0 4294967295 SUSP0R SUSP0R suspend registers 0x40 0x20 write-only 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP1R SUSP1R suspend registers 0x44 0x20 write-only 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP2R SUSP2R suspend registers 0x48 0x20 write-only 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP3R SUSP3R suspend registers 0x4C 0x20 write-only 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP4R SUSP4R suspend registers 0x50 0x20 write-only 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP5R SUSP5R suspend registers 0x54 0x20 write-only 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP6R SUSP6R suspend registers 0x58 0x20 write-only 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP7R SUSP7R suspend registers 0x5C 0x20 write-only 0x00000000 SUSP AES suspend 0 32 0 4294967295 IER IER interrupt enable register 0x300 0x20 read-write 0x00000000 CCFIE Computation complete flag 0 1 CCFIE Disabled Interrupt is disabled (masked) 0 Enabled Interrupt is enabled (not masked) 1 RNGEIE Key error interrupt flag 3 1 KEIE Key error interrupt flag 2 1 RWEIE Read or write error interrupt flag 1 1 ISR ISR interrupt status register 0x304 0x20 read-only 0x00000000 RWEIF Read or write error interrupt flag 1 1 RWEIF NoError No error detected 0 Error The error detected 1 RNGEIF Key error interrupt flag 3 1 KEIF Key error interrupt flag 2 1 CCF Computation complete flag 0 1 CCF NotCompleted Computation not completed 0 Completed Computation completed 1 ICR ICR interrupt clear register 0x308 0x20 write-only 0x00000000 CCF Computation complete flag clear 0 1 CCFW Clear Setting this bit clears corresponding interrupt status bit 1 KEIF Key error interrupt flag clear 2 1 RWEIF Read or write error interrupt flag clear 1 1 SEC_AES 0x520C0000 FMAC Filter Math Accelerator FMAC 0x40021400 0x0 0x400 registers FMAC FMAC interrupt 124 X1BUFCFG X1BUFCFG FMAC X1 Buffer Configuration register 0x0 0x20 read-write 0x00000000 X1_BASE Base address of X1 buffer 0 8 X1_BUF_SIZE Allocated size of X1 buffer in 16-bit words 8 8 FULL_WM Watermark for buffer full flag 24 2 X2BUFCFG X2BUFCFG FMAC X2 Buffer Configuration register 0x4 0x20 read-write 0x00000000 X2_BASE Base address of X2 buffer 0 8 X2_BUF_SIZE Size of X2 buffer in 16-bit words 8 8 YBUFCFG YBUFCFG FMAC Y Buffer Configuration register 0x8 0x20 read-write 0x00000000 Y_BASE Base address of Y buffer 0 8 Y_BUF_SIZE Size of Y buffer in 16-bit words 8 8 EMPTY_WM Watermark for buffer empty flag 24 2 PARAM PARAM FMAC Parameter register 0xC 0x20 read-write 0x00000000 START Enable execution 31 1 FUNC Function 24 7 R Input parameter R 16 8 Q Input parameter Q 8 8 P Input parameter P 0 8 CR CR FMAC Control register 0x10 0x20 read-write 0x00000000 RESET Reset FMAC unit 16 1 CLIPEN Enable clipping 15 1 DMAWEN Enable DMA write channel requests 9 1 DMAREN Enable DMA read channel requests 8 1 SATIEN Enable saturation error interrupts 4 1 UNFLIEN Enable underflow error interrupts 3 1 OVFLIEN Enable overflow error interrupts 2 1 WIEN Enable write interrupt 1 1 RIEN Enable read interrupt 0 1 SR SR FMAC Status register 0x14 0x20 read-only 0x00000001 YEMPTY Y buffer empty flag 0 1 X1FULL X1 buffer full flag 1 1 OVFL Overflow error flag 8 1 UNFL Underflow error flag 9 1 SAT Saturation error flag 10 1 WDATA WDATA FMAC Write Data register 0x18 0x20 write-only 0x00000000 WDATA Write data 0 16 RDATA RDATA FMAC Read Data register 0x1C 0x20 read-only 0x00000000 RDATA Read data 0 16 SEC_FMAC 0x50021400 CORDIC CORDIC Co-processor CORDIC 0x40021000 0x0 0x400 registers Cordic Cordic interrupt 123 CSR CSR CORDIC Control Status register 0x0 0x20 0x00000050 FUNC Function 0 4 read-write PRECISION Precision required (number of iterations) 4 4 read-write SCALE Scaling factor 8 3 read-write IEN Enable interrupt 16 1 read-write DMAREN Enable DMA read channel 17 1 read-write DMAWEN Enable DMA write channel 18 1 read-write NRES Number of results in the CORDIC_RDATA register 19 1 read-write NARGS Number of arguments expected by the CORDIC_WDATA register 20 1 read-write RESSIZE Width of output data 21 1 read-write ARGSIZE Width of input data 22 1 read-write RRDY Result ready flag 31 1 read-only WDATA WDATA FMAC Write Data register 0x4 0x20 write-only 0x00000000 ARG Function input arguments 0 32 RDATA RDATA FMAC Read Data register 0x8 0x20 read-only 0x00000000 RES Function result 0 32 SEC_CORDIC 0x50021000 DAC1 Digital-to-analog converter DAC 0x46021800 0x0 0x400 registers DAC1 DAC1 global interrupt 38 CR CR DAC control register 0x0 0x20 read-write 0x00000000 2 0x10 1-2 EN%s DAC channel%s enable 0 1 EN1 Disabled DAC Channel X disabled 0 Enabled DAC Channel X enabled 1 2 0x10 1-2 TEN%s DAC channel%s trigger enable 1 1 TEN1 Disabled DAC Channel X trigger disabled 0 Enabled DAC Channel X trigger enabled 1 TSEL1 DAC channel1 trigger selection 2 4 TSEL1 Swtrig Software trigger 0 Tim1Trgo Timer 1 TRGO event 1 Tim2Trgo Timer 2 TRGO event 2 Tim4Trgo Timer 4 TRGO event 3 Tim5Trgo Timer 5 TRGO event 4 Tim6Trgo Timer 6 TRGO event 5 Tim7Trgo Timer 7 TRGO event 6 Tim8Trgo Timer 8 TRGO event 7 Tim15Trgo Timer 15 TRGO event 8 Lptim1Ch1 LPTIM1 CH1 event 11 Lptim3Ch1 LPTIM3 CH1 event 12 Exti9 EXTI line 9 13 2 0x10 1-2 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true 2 0x10 1-2 MAMP%s DAC channel%s mask/amplitude selector 8 4 MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 2 0x10 1-2 DMAEN%s DAC channel%s DMA enable 12 1 DMAEN1 Disabled DAC Channel X DMA mode disabled 0 Enabled DAC Channel X DMA mode enabled 1 2 0x10 1-2 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 2 0x10 1-2 CEN%s DAC channel%s calibration enable 14 1 CEN1 Normal DAC Channel X Normal operating mode 0 Calibration DAC Channel X calibration mode 1 TSEL2 DAC channel2 trigger selection 18 4 SWTRGR SWTRGR DAC software trigger register 0x4 0x20 write-only 0x00000000 2 0x1 1-2 SWTRIG%s DAC channel%s software trigger 0 1 SWTRIG1 NoTrigger No trigger 0 Trigger Trigger 1 2 0xC 1-2 DHR12R%s DHR12R%s channel%s 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit right-aligned data 0 12 0 4095 DACC1DHRB DAC channel1 12-bit right-aligned data B 16 12 0 4095 2 0xC 1-2 DHR12L%s DHR12L%s channel%s 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit left-aligned data 4 12 0 4095 DACC1DHRB DAC channel1 12-bit left-aligned data B 20 12 0 4095 2 0xC 1-2 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACCDHR DAC channel1 8-bit right-aligned data 0 8 0 255 DACC1DHRB DAC channel1 8-bit right-aligned Sdata 8 8 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 0 4095 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 0 4095 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 2 0x8 1-2 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 0 255 2 0x4 1-2 DOR%s DOR%s channel%s data output register 0x2C 0x20 read-only 0x00000000 DACCDOR DAC channel1 data output 0 12 0 4095 DACC1DORB DAC channel1 data output 16 12 0 4095 SR SR DAC status register 0x34 0x20 0x00000000 2 0x10 1-2 DAC%sRDY DAC channel%s ready status bit 11 1 read-only DAC1RDY NotReady DAC channelX is not yet ready to accept the trigger nor output data 0 Ready DAC channelX is ready to accept the trigger or output data 1 2 0x10 1-2 DORSTAT%s DAC channel%s output register status bit 12 1 read-only DORSTAT1 Dor DOR[11:0] is used actual DAC output 0 Dorb DORB[11:0] is used actual DAC output 1 2 0x10 1-2 DMAUDR%s DAC channel%s DMA underrun flag 13 1 read-write DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 2 0x10 1-2 CAL_FLAG%s DAC channel%s calibration offset status 14 1 read-only CAL_FLAG1 Lower Calibration trimming value is lower than the offset correction value 0 Equal_Higher Calibration trimming value is equal or greater than the offset correction value 1 2 0x10 1-2 BWST%s DAC channel%s busy writing sample time flag 15 1 read-only BWST1 Idle There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written 0 Busy There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written 1 CCR CCR DAC calibration control register 0x38 0x20 read-write 0x00000000 2 0x10 1-2 OTRIM%s DAC channel%s offset trimming value 0 5 0 31 MCR MCR DAC mode control register 0x3C 0x20 read-write 0x00000000 2 0x10 1-2 MODE%s DAC channel%s mode 0 3 MODE1 NormalPinBuffer Normal mode - DAC channelx is connected to external pin with Buffer enabled 0 NormalPinChipBuffer Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 1 NormalPinNoBuffer Normal mode - DAC channelx is connected to external pin with Buffer disabled 2 NormalChipNoBuffer Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled 3 SHPinBuffer S&H mode - DAC channelx is connected to external pin with Buffer enabled 4 SHPinChipBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 5 SHPinNoBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled 6 SHChipNoBuffer S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled 7 2 0x10 1-2 DMADOUBLE%s DAC channel%s DMA double data mode 8 1 DMADOUBLE1 Normal DMA Normal mode selected 0 DoubleData DMA Double data mode selected 1 2 0x10 1-2 SINFORMAT%s Enable signed format for DAC channel%s 9 1 SINFORMAT1 Unsigned Input data is in unsigned format 0 Signed Input data is in signed format (2's complement). The MSB bit represents the sign. 1 HFSEL High frequency interface mode selection 14 2 HFSEL Disabled High frequency interface mode disabled 0 More80Mhz High frequency interface mode enabled for AHB clock frequency > 80 MHz 1 More160Mhz High frequency interface mode enabled for AHB clock frequency >160 MHz 2 2 0x4 1-2 SHSR%s SHSR%s DAC channel%s sample and hold sample time register 0x40 0x20 read-write 0x00000000 TSAMPLE DAC Channel 1 sample Time (only valid in sample & hold mode) 0 10 0 1023 SHHR SHHR DAC Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 2 0x10 1-2 THOLD%s DAC channel%s hold time (only valid in Sample and hold mode) 0 10 0 1023 SHRR SHRR DAC Sample and Hold refresh time register 0x4C 0x20 read-write 0x00010001 2 0x10 1-2 TREFRESH%s DAC channel%s refresh time (only valid in Sample and hold mode) 0 8 0 255 AUTOCR AUTOCR Autonomous mode control register 0x54 0x20 read-write 0x00000000 AUTOMODE DAC Autonomous mode 22 1 AUTOMODE Disabled DAC Autonomous mode disabled 0 Enabled DAC Autonomous mode enabled 1 SEC_DAC1 0x56021800 SDMMC1 Secure digital input/output MultiMediaCard interface SDMMC 0x420C8000 0x0 0x400 registers SDMMC1 SDMMC1 global interrupt 78 POWER POWER power control register 0x0 0x20 read-write 0x00000000 PWRCTRL SDMMC state control bits 0 2 VSWITCH Voltage switch sequence start 2 1 VSWITCHEN Voltage switch procedure enable 3 1 DIRPOL Data and command direction signals polarity selection 4 1 CLKCR CLKCR clock control register 0x4 0x20 read-write 0x00000000 SELCLKRX Receive clock selection 20 2 BUSSPEED Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104 19 1 DDR Data rate signaling selection 18 1 HWFC_EN HW Flow Control enable 17 1 NEGEDGE SDIO_CK dephasing selection bit 16 1 WIDBUS Wide bus mode enable bit 14 2 PWRSAV Power saving configuration bit 12 1 CLKDIV Clock divide factor 0 10 ARGR ARGR argument register 0x8 0x20 read-write 0x00000000 CMDARG Command argument 0 32 CMDR CMDR command register 0xC 0x20 read-write 0x00000000 CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end 16 1 BOOTEN Enable boot mode procedure 15 1 BOOTMODE Select the boot mode procedure to be used 14 1 DTHOLD Hold new data block transmission and reception in the DPSM 13 1 CPSMEN Command path state machine (CPSM) Enable bit 12 1 WAITPEND CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM 11 1 WAITINT CPSM waits for interrupt request 10 1 WAITRESP Wait for response bits 8 2 CMDSTOP The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM 7 1 CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM 6 1 CMDINDEX Command index 0 6 RESPCMDR RESPCMD command response register 0x10 0x20 read-only 0x00000000 RESPCMD Response command index 0 6 4 0x4 1-4 RESP%s RESP%s SDIO response %s register 0x14 0x20 read-only 0x00000000 CARDSTATUS Status of a card, which is part of the received response 0 32 DTIMER DTIMER data timer register 0x24 0x20 read-write 0x00000000 DATATIME Data and R1b busy timeout period 0 32 DLENR DLENR data length register 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value 0 25 DCTRL DCTRL data control register 0x2C 0x20 read-write 0x00000000 FIFORST FIFO reset, will flush any remaining data 13 1 BOOTACKEN Enable the reception of the boot acknowledgment 12 1 SDIOEN SD I/O enable functions 11 1 RWMOD Read wait mode 10 1 RWSTOP Read wait stop 9 1 RWSTART Read wait start 8 1 DBLOCKSIZE Data block size 4 4 DTMODE Data transfer mode selection 2 2 DTDIR Data transfer direction selection 1 1 DTEN DTEN 0 1 DCNTR DCNTR data counter register 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value 0 25 STAR STAR status register 0x34 0x20 read-only 0x00000000 IDMABTC IDMA buffer transfer complete 28 1 IDMATE IDMA transfer error 27 1 CKSTOP SDMMC_CK stopped in Voltage switch procedure 26 1 VSWEND Voltage switch critical timing section completion 25 1 ACKTIMEOUT Boot acknowledgment timeout 24 1 ACKFAIL Boot acknowledgment received (boot acknowledgment check fail) 23 1 SDIOIT SDIO interrupt received 22 1 BUSYD0END end of SDMMC_D0 Busy following a CMD response detected 21 1 BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response 20 1 RXFIFOE Receive FIFO empty 19 1 TXFIFOE Transmit FIFO empty 18 1 RXFIFOF Receive FIFO full 17 1 TXFIFOF Transmit FIFO full 16 1 RXFIFOHF Receive FIFO half full 15 1 TXFIFOHE Transmit FIFO half empty 14 1 CPSMACT Command path state machine active, i.e. not in Idle state 13 1 DPSMACT Data path state machine active, i.e. not in Idle state 12 1 DABORT Data transfer aborted by CMD12 11 1 DBCKEND Data block sent/received 10 1 DHOLD Data transfer Hold 9 1 DATAEND Data transfer ended correctly 8 1 CMDSENT Command sent (no response required) 7 1 CMDREND Command response received (CRC check passed, or no CRC) 6 1 RXOVERR Received FIFO overrun error (masked by hardware when IDMA is enabled) 5 1 TXUNDERR Transmit FIFO underrun error (masked by hardware when IDMA is enabled) 4 1 DTIMEOUT Data timeout 3 1 CTIMEOUT Command response timeout 2 1 DCRCFAIL Data block sent/received (CRC check failed) 1 1 CCRCFAIL Command response received (CRC check failed) 0 1 ICR ICR interrupt clear register 0x38 0x20 read-write 0x00000000 IDMABTCC IDMA buffer transfer complete clear bit 28 1 IDMATEC IDMA transfer error clear bit 27 1 CKSTOPC CKSTOP flag clear bit 26 1 VSWENDC VSWEND flag clear bit 25 1 ACKTIMEOUTC ACKTIMEOUT flag clear bit 24 1 ACKFAILC ACKFAIL flag clear bit 23 1 SDIOITC SDIOIT flag clear bit 22 1 BUSYD0ENDC BUSYD0END flag clear bit 21 1 DABORTC DABORT flag clear bit 11 1 DBCKENDC DBCKEND flag clear bit 10 1 DHOLDC DHOLD flag clear bit 9 1 DATAENDC DATAEND flag clear bit 8 1 CMDSENTC CMDSENT flag clear bit 7 1 CMDRENDC CMDREND flag clear bit 6 1 RXOVERRC RXOVERR flag clear bit 5 1 TXUNDERRC TXUNDERR flag clear bit 4 1 DTIMEOUTC DTIMEOUT flag clear bit 3 1 CTIMEOUTC CTIMEOUT flag clear bit 2 1 DCRCFAILC DCRCFAIL flag clear bit 1 1 CCRCFAILC CCRCFAIL flag clear bit 0 1 MASKR MASKR mask register 0x3C 0x20 read-write 0x00000000 IDMABTCIE IDMA buffer transfer complete interrupt enable 28 1 CKSTOPIE Voltage Switch clock stopped interrupt enable 26 1 VSWENDIE Voltage switch critical timing section completion interrupt enable 25 1 ACKTIMEOUTIE Acknowledgment timeout interrupt enable 24 1 ACKFAILIE Acknowledgment Fail interrupt enable 23 1 SDIOITIE SDIO mode interrupt received interrupt enable 22 1 BUSYD0ENDIE BUSYD0END interrupt enable 21 1 TXFIFOEIE Tx FIFO empty interrupt enable 18 1 RXFIFOFIE Rx FIFO full interrupt enable 17 1 RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 DABORTIE Data transfer aborted interrupt enable 11 1 DBCKENDIE Data block end interrupt enable 10 1 DHOLDIE Data hold interrupt enable 9 1 DATAENDIE Data end interrupt enable 8 1 CMDSENTIE Command sent interrupt enable 7 1 CMDRENDIE Command response received interrupt enable 6 1 RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 DTIMEOUTIE Data timeout interrupt enable 3 1 CTIMEOUTIE Command timeout interrupt enable 2 1 DCRCFAILIE Data CRC fail interrupt enable 1 1 CCRCFAILIE Command CRC fail interrupt enable 0 1 ACKTIMER ACKTIMER acknowledgment timer register 0x40 0x20 read-write 0x00000000 ACKTIME Boot acknowledgment timeout period 0 25 16 0x4 0-15 FIFOR%s FIFOR%s data FIFO register %s 0x80 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 IDMACTRLR IDMACTRLR DMA control register 0x50 0x20 read-write 0x00000000 IDMAEN IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 1 IDMABMODE Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 IDMABSIZER IDMABSIZER buffer size register 0x54 0x20 read-write 0x00000000 IDMABNDT Number of bytes per buffer 5 12 IDMABASER IDMABASER buffer base address register 0x58 0x20 read-write 0x00000000 IDMABASE Buffer memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only) 0 32 IDMALAR IDMALAR linked list address register 0x64 0x20 read-write 0x00000000 ULA Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode) 31 1 ULS Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1) 30 1 ABR Acknowledge linked list buffer ready 29 1 IDMALA Acknowledge linked list buffer ready 2 14 IDMABAR IDMABAR linked list memory base register 0x68 0x20 read-write 0x00000000 IDMABA Word aligned Linked list memory base address 2 30 SEC_SDMMC1 0x520C8000 SDMMC2 0x420C8C00 SDMMC2 SDMMC2 global interrupt 79 SEC_SDMMC2 0x520C8C00 OPAMP Operational amplifiers OPAMP 0x46005000 0x0 0x400 registers OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 0x20 0x00000000 0xFFFFFFFF OPAEN OPAMP enable 0 1 read-write OPALPM OPAMP low-power mode The OPAMP must be disabled to change this configuration. 1 1 read-write OPAMODE OPAMP PGA mode 00 and 01: internal PGA disabled 2 2 read-write PGA_GAIN OPAMP programmable amplifier gain value 4 2 read-write VM_SEL Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 1x: inverting input not externally connected 8 2 read-write VP_SEL Non-inverted input selection 10 1 read-write CALON Calibration mode enable 12 1 read-write CALSEL Calibration selection 13 1 read-write USERTRIM âfactoryâ or âuserâ offset trimmed values selection This bit is active for normal and low-power modes. 14 1 read-write CALOUT OPAMP calibration output During the calibration mode, the offset is trimmed when this signal toggles. 15 1 read-only OPAHSM OPAMP high-speed mode This bit is effective for both normal and low-power modes. 30 1 read-write OPA_RANGE OPAMP range setting This bit must be set before enabling the OPAMP and this bit affects all OPAMP instances. 31 1 read-write OPAMP1_OTR OPAMP1_OTR OPAMP1 offset trimming register in normal mode 0x4 0x20 0x00000000 0xFFFF0000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 read-write TRIMOFFSETP Trim for PMOS differential pairs 8 5 read-write OPAMP1_LPOTR OPAMP1_LPOTR OPAMP1 offset trimming register in low-power mode 0x8 0x20 0x00000000 0xFFFF0000 TRIMLPOFFSETN Low-power mode trim for NMOS differential pairs 0 5 read-write TRIMLPOFFSETP Low-power mode trim for PMOS differential pairs 8 5 read-write OPAMP2_CRS OPAMP2_CRS OPAMP2 control/status register 0x10 0x20 0x00000000 0xFFFFFFFF OPAEN OPAMP enable 0 1 read-write OPALPM OPAMP low-power mode The OPAMP must be disabled to change this configuration. 1 1 read-write OPAMODE OPAMP PGA mode 00 and 01: internal PGA disabled 2 2 read-write PGA_GAIN OPAMP programmable amplifier gain value 4 2 read-write VM_SEL Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. in PGA mode for filtering) 1x: inverting input not externally connected 8 2 read-write VP_SEL Non inverted input selection 10 1 read-write CALON Calibration mode enable 12 1 read-write CALSEL Calibration selection 13 1 read-write USERTRIM âfactoryâ or âuserâ offset trimmed values selection This bit is active for normal and low-power modes. 14 1 read-write CALOUT OPAMP calibration output During calibration mode, the offset is trimmed when this signal toggles. 15 1 read-only OPAHSM OPAMP high-speed mode This bit is effective for both normal and high-speed modes. 30 1 read-write OPAMP2_OTR OPAMP2_OTR OPAMP2 offset trimming register in normal mode 0x14 0x20 0x00000000 0xFFFF0000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 read-write TRIMOFFSETP Trim for PMOS differential pairs 8 5 read-write OPAMP2_LPOTR OPAMP2_LPOTR OPAMP2 offset trimming register in low-power mode 0x18 0x20 0x00000000 0xFFFF0000 TRIMLPOFFSETN Low-power mode trim for NMOS differential pairs 0 5 read-write TRIMLPOFFSETP Low-power mode trim for PMOS differential pairs 8 5 read-write SEC_OPAMP 0x56005000 DLYBOS1 The delay block (DLYB) is used to generate an output clock that is dephased from the input clock DLYB 0x420CF000 0x0 0x400 registers CR CR control register 0x0 0x20 read-write 0x00000000 DEN Operational amplifier Enable 0 1 SEN OPALPM 1 1 CFGR CFGR configuration register 0x4 0x20 0x00000000 SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only SEC_DLYBOS1 0x520CF000 DLYBOS2 0x420CF400 SEC_DLYBOS2 0x520CF400 DLYBSD1 0x420C8400 SEC_DLYBSD1 0x520C8400 DLYBSD2 0x420C8800 SEC_DLYBSD2 0x520C8800 SAES Secure AES coprocessor SAES 0x420C0C00 0x0 0x400 registers SAES SAES global interrupt 28 CR CR control register 0x0 0x20 read-write 0x00000000 IPRST IPRST 31 1 KEYSEL KEYSEL 28 3 KSHAREID KSHAREID 26 2 KMOD KMOD 24 2 KEYPROT KEYPROT 19 1 KEYSIZE KEYSIZE 18 1 DMAOUTEN DMAOUTEN 12 1 DMAINEN DMAINEN 11 1 CHMOD CHMOD 5 2 MODE MODE 3 2 DATATYPE DATATYPE 1 2 EN SAES enable 0 1 SR SR status register 0x4 0x20 read-only 0x00000000 KEYVALID Key Valid flag 7 1 BUSY BUSY 3 1 WRERR Write error flag 2 1 RDERR Read error flag 1 1 CCF Computation complete flag 0 1 DINR DINR data input register 0x8 0x20 write-only 0x00000000 DIN Input data word 0 32 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 DOUT Output data word 0 32 KEYR0 KEYR0 key register 0 0x10 0x20 write-only 0x00000000 KEY Cryptographic key, bits [31:0] 0 32 KEYR1 KEYR1 key register 1 0x14 0x20 write-only 0x00000000 KEY Cryptographic key, bits [63:32] 0 32 KEYR2 KEYR2 key register 2 0x18 0x20 write-only 0x00000000 KEYR Cryptographic key, bits [95:64] 0 32 KEYR3 KEYR3 key register 3 0x1C 0x20 write-only 0x00000000 SAES_KEYR3 Cryptographic key, bits [127:96] 0 32 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 IVI Initialization vector input, bits [31:0] 0 32 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 IVI Initialization vector input, bits [63:32] 0 32 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 IVI Initialization vector input, bits [95:64] 0 32 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization vector input, bits [127:96] 0 32 KEYR4 KEYR4 key register 4 0x30 0x20 write-only 0x00000000 KEY Cryptographic key, bits [159:128] 0 32 KEYR5 KEYR5 key register 5 0x34 0x20 write-only 0x00000000 KEY Cryptographic key, bits [191:160] 0 32 KEYR6 KEYR6 key register 6 0x38 0x20 write-only 0x00000000 KEY Cryptographic key, bits [223:192] 0 32 KEYR7 KEYR7 key register 7 0x3C 0x20 write-only 0x00000000 KEY Cryptographic key, bits [255:224] 0 32 DPACFGR DPACFGR configuration register 0x100 0x20 0x00000008 CONFIGLOCK CONFIGLOCK 31 1 read-only TRIMCFG TRIMCFG 3 2 read-write RESEED RESEED 2 1 read-write REDCFG REDCFG 1 1 read-write IER IER interrupt enable register 0x300 0x20 read-write 0x00000000 RNGEIE RNGEIE 3 1 KEIE Key error interrupt enable 2 1 RWEIE Read or write error interrupt enable 1 1 CCFIE Computation complete flag interrupt enable 0 1 ISR ISR interrupt status register 0x304 0x20 read-only 0x00000000 RNGEIF RNGEIF 3 1 KEIF Key error interrupt flag 2 1 RWEIF Read or write error interrupt flag 1 1 CCF Computation complete flag 0 1 ICR ICR interrupt clear register 0x308 0x20 write-only 0x00000000 RNGEIF RNGEIF 3 1 KEIF Key error interrupt flag clear 2 1 RWEIF Read or write error interrupt flag clear 1 1 CCF Computation complete flag clear 0 1 SEC_SAES 0x520C0C00 OTG_FS OTG_FS OTG_FS 0x42040000 0x0 0x88000 registers OTG_FS USB OTG FS global interrupt 73 GOTGCTL GOTGCTL The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core. 0x0 0x20 0x00010000 SRQSCS SRQSCS 0 1 read-only SRQ SRQ 1 1 read-write VBVALOEN VBVALOEN 2 1 read-write VBVALOVAL VBVALOVAL 3 1 read-write AVALOEN AVALOEN 4 1 read-write AVALOVAL AVALOVAL 5 1 read-write BVALOEN BVALOEN 6 1 read-write BVALOVAL BVALOVAL 7 1 read-write HNGSCS HNGSCS 8 1 read-only HNPRQ HNPRQ 9 1 read-write HSHNPEN HSHNPEN 10 1 read-write DHNPEN DHNPEN 11 1 read-write EHEN EHEN 12 1 read-write CIDSTS CIDSTS 16 1 read-only DBCT DBCT 17 1 read-only ASVLD ASVLD 18 1 read-only BSVLD BSVLD 19 1 read-only OTGVER OTGVER 20 1 read-write CURMOD CURMOD 21 1 read-only GOTGINT GOTGINT The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. 0x4 0x20 read-write 0x00000000 SEDET SEDET 2 1 SRSSCHG SRSSCHG 8 1 HNSSCHG HNSSCHG 9 1 HNGDET HNGDET 17 1 ADTOCHG ADTOCHG 18 1 DBCDNE DBCDNE 19 1 GAHBCFG GAHBCFG This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB. 0x8 0x20 read-write 0x00000000 GINTMSK GINTMSK 0 1 TXFELVL TXFELVL 7 1 PTXFELVL PTXFELVL 8 1 GUSBCFG GUSBCFG This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming. 0xC 0x20 0x00001440 TOCAL TOCAL 0 3 read-write PHYSEL PHYSEL 6 1 read-only SRPCAP SRPCAP 8 1 read-write HNPCAP HNPCAP 9 1 read-write TRDT TRDT 10 4 read-write FHMOD FHMOD 29 1 read-write FDMOD FDMOD 30 1 read-write GRSTCTL GRSTCTL The application uses this register to reset various hardware features inside the core. 0x10 0x20 0x80000000 CSRST CSRST 0 1 read-only PSRST PSRST 1 1 read-write FSRST FSRST 2 1 read-write RXFFLSH RXFFLSH 4 1 read-write TXFFLSH TXFFLSH 5 1 read-write TXFNUM TXFNUM 6 5 read-write AHBIDL AHBIDL 31 1 read-only GINTSTS GINTSTS This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. 0x14 0x20 0x04000020 CMOD CMOD 0 1 read-only MMIS MMIS 1 1 read-write OTGINT OTGINT 2 1 read-only SOF SOF 3 1 read-write RXFLVL RXFLVL 4 1 read-only NPTXFE NPTXFE 5 1 read-only GINAKEFF GINAKEFF 6 1 read-only GONAKEFF GONAKEFF 7 1 read-only ESUSP ESUSP 10 1 read-write USBSUSP USBSUSP 11 1 read-write USBRST USBRST 12 1 read-write ENUMDNE ENUMDNE 13 1 read-write ISOODRP ISOODRP 14 1 read-write EOPF EOPF 15 1 read-write IEPINT IEPINT 18 1 read-only OEPINT OEPINT 19 1 read-only IISOIXFR IISOIXFR 20 1 read-write IPXFR IPXFR 21 1 read-write RSTDET RSTDET 23 1 read-write HPRTINT HPRTINT 24 1 read-only HCINT HCINT 25 1 read-only PTXFE PTXFE 26 1 read-only LPMINT LPMINT 27 1 read-write CIDSCHG CIDSCHG 28 1 read-write DISCINT DISCINT 29 1 read-write SRQINT SRQINT 30 1 read-write WKUPINT WKUPINT 31 1 read-write GINTMSK GINTMSK This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set. 0x18 0x20 0x00000000 MMISM MMISM 1 1 read-write OTGINT OTGINT 2 1 read-write SOFM SOFM 3 1 read-write RXFLVLM RXFLVLM 4 1 read-write NPTXFEM NPTXFEM 5 1 read-write GINAKEFFM GINAKEFFM 6 1 read-write GONAKEFFM GONAKEFFM 7 1 read-write ESUSPM ESUSPM 10 1 read-write USBSUSPM USBSUSPM 11 1 read-write USBRST USBRST 12 1 read-write ENUMDNEM ENUMDNEM 13 1 read-write ISOODRPM ISOODRPM 14 1 read-write EOPFM EOPFM 15 1 read-write IEPINT IEPINT 18 1 read-write OEPINT OEPINT 19 1 read-write IISOIXFRM IISOIXFRM 20 1 read-write IPXFRM IPXFRM 21 1 read-write RSTDETM RSTDETM 23 1 read-write PRTIM PRTIM 24 1 read-write HCIM HCIM 25 1 read-write PTXFEM PTXFEM 26 1 read-write LPMINTM LPMINTM 27 1 read-write CIDSCHGM CIDSCHGM 28 1 read-write DISCINT DISCINT 29 1 read-write SRQIM SRQIM 30 1 read-write WUIM WUIM 31 1 read-write GRXSTSR_DEVICE GRXSTSR_DEVICE This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000. 0x1C 0x20 read-only 0x00000000 EPNUM EPNUM 0 4 BCNT BCNT 4 11 DPID DPID 15 2 PKTSTS PKTSTS 17 4 FRMNUM FRMNUM 21 4 STSPHST STSPHST 27 1 GRXSTSR_HOST GRXSTSR_HOST This description is for register GRXSTSR in Host mode GRXSTSR_DEVICE 0x1C 0x20 read-only 0x00000000 CHNUM CHNUM 0 4 BCNT BCNT 4 11 DPID DPID 15 2 PKTSTS PKTSTS 17 4 GRXSTSP_DEVICE GRXSTSP__DEVICE This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in GINTSTS) is asserted. 0x20 0x20 read-only 0x00000000 EPNUM EPNUM 0 4 BCNT BCNT 4 11 DPID DPID 15 2 PKTSTS PKTSTS 17 4 FRMNUM FRMNUM 21 4 STSPHST STSPHST 27 1 GRXSTSP_HOST GRXSTSP_HOST This description is for register GRXSTSP in HOST mode GRXSTSP_DEVICE 0x20 0x20 read-only 0x00000000 CHNUM CHNUM 0 4 BCNT BCNT 4 11 DPID DPID 15 2 PKTSTS PKTSTS 17 4 GRXFSIZ GRXFSIZ The application can program the RAM size that must be allocated to the Rx FIFO. 0x24 0x20 read-write 0x00000200 RXFD RXFD 0 16 HNPTXFSIZ HNPTXFSIZ Host mode 0x28 0x20 read-write 0x02000200 NPTXFSA NPTXFSA 0 16 NPTXFD NPTXFD 16 16 HNPTXSTS HNPTXSTS In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue. 0x2C 0x20 read-only 0x00080200 NPTXFSAV NPTXFSAV 0 16 NPTQXSAV NPTQXSAV 16 8 NPTXQTOP NPTXQTOP 24 7 GCCFG GCCFG OTG general core configuration register 0x38 0x20 0x00000000 DCDET DCDET 0 1 read-only PDET PDET 1 1 read-only SDET SDET 2 1 read-only PS2DET PS2DET 3 1 read-only PWRDWN PWRDWN 16 1 read-write BCDEN BCDEN 17 1 read-write DCDEN DCDEN 18 1 read-write PDEN PDEN 19 1 read-write SDEN SDEN 20 1 read-write VBDEN VBDEN 21 1 read-write CID CID This is a register containing the Product ID as reset value. 0x3C 0x20 read-write 0x00003000 PRODUCT_ID PRODUCT_ID 0 32 GLPMCFG GLPMCFG OTG core LPM configuration register 0x54 0x20 0x00000000 LPMEN LPMEN 0 1 read-write LPMACK LPMACK 1 1 read-write BESL BESL 2 4 read-write REMWAKE REMWAKE 6 1 read-write L1SSEN L1SSEN 7 1 read-write BESLTHRS BESLTHRS 8 4 read-write L1DSEN L1DSEN 12 1 read-write LPMRSP LPMRSP 13 2 read-only SLPSTS SLPSTS 15 1 read-only L1RSMOK L1RSMOK 16 1 read-only LPMCHIDX LPMCHIDX 17 4 read-write LPMRCNT LPMRCNT 21 3 read-write SNDLPM SNDLPM 24 1 read-write LPMRCNTSTS LPMRCNTSTS 25 3 read-only ENBESL ENBESL 28 1 read-write HPTXFSIZ HPTXFSIZ OTG host periodic transmit FIFO size register 0x100 0x20 read-write 0x02000400 PTXSA PTXSA 0 16 PTXFSIZ PTXFSIZ 16 16 DIEPTXF1 DIEPTXF1 OTG device IN endpoint transmit FIFO 1 size register 0x104 0x20 read-write 0x02000400 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF2 DIEPTXF2 OTG device IN endpoint transmit FIFO 2 size register 0x108 0x20 read-write 0x02000600 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF3 DIEPTXF3 OTG device IN endpoint transmit FIFO 3 size register 0x10C 0x20 read-write 0x02000800 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF4 DIEPTXF4 OTG device IN endpoint transmit FIFO 4 size register 0x110 0x20 read-write 0x02000A00 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF5 DIEPTXF5 OTG device IN endpoint transmit FIFO 5 size register 0x114 0x20 read-write 0x02000C00 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 HCFG HCFG This register configures the core after power-on. Do not make changes to this register after initializing the host. 0x400 0x20 0x00000000 FSLSPCS FSLSPCS 0 2 read-write FSLSS FSLSS 2 1 read-only HFIR HFIR This register stores the frame interval information for the current speed to which the OTG controller has enumerated. 0x404 0x20 read-write 0x0000EA60 FRIVL FRIVL 0 16 RLDCTRL RLDCTRL 16 1 HFNUM HFNUM This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. 0x408 0x20 read-only 0x00003FFF FRNUM FRNUM 0 16 FTREM FTREM 16 16 HPTXSTS HPTXSTS This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue. 0x410 0x20 read-only 0x00080100 PTXFSAVL PTXFSAVL 0 16 PTXQSAV PTXQSAV 16 8 PTXQTOP PTXQTOP 24 8 HAINT HAINT When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. 0x414 0x20 read-only 0x00000000 HAINT HAINT 0 16 HAINTMSK HAINTMSK The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. 0x418 0x20 read-write 0x00000000 HAINTM HAINTM 0 16 HPRT HPRT This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. 0x440 0x20 0x00000000 PCSTS PCSTS 0 1 read-only PCDET PCDET 1 1 read-write PENA PENA 2 1 read-write PENCHNG PENCHNG 3 1 read-write POCA POCA 4 1 read-only POCCHNG POCCHNG 5 1 read-write PRES PRES 6 1 read-write PSUSP PSUSP 7 1 read-write PRST PRST 8 1 read-write PLSTS PLSTS 10 2 read-only PPWR PPWR 12 1 read-write PTCTL PTCTL 13 4 read-write PSPD PSPD 17 2 read-only HCCHAR0 HCCHAR0 OTG host channel 0 characteristics register 0x500 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT0 HCINT0 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x508 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK0 HCINTMSK0 This register reflects the mask for each channel status described in the previous section. 0x50C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ0 HCTSIZ0 OTG host channel 0 transfer size register 0x510 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR1 HCCHAR1 OTG host channel 1 characteristics register 0x520 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT1 HCINT1 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x528 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK1 HCINTMSK1 This register reflects the mask for each channel status described in the previous section. 0x52C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ1 HCTSIZ1 OTG host channel 1 transfer size register 0x530 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR2 HCCHAR2 OTG host channel 2 characteristics register 0x540 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT2 HCINT2 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x548 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK2 HCINTMSK2 This register reflects the mask for each channel status described in the previous section. 0x54C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ2 HCTSIZ2 OTG host channel 2 transfer size register 0x550 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR3 HCCHAR3 OTG host channel 3 characteristics register 0x560 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT3 HCINT3 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x568 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK3 HCINTMSK3 This register reflects the mask for each channel status described in the previous section. 0x56C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ3 HCTSIZ3 OTG host channel 3 transfer size register 0x570 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR4 HCCHAR4 OTG host channel 4 characteristics register 0x580 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT4 HCINT4 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x588 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK4 HCINTMSK4 This register reflects the mask for each channel status described in the previous section. 0x58C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ4 HCTSIZ4 OTG host channel 4 transfer size register 0x590 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR5 HCCHAR5 OTG host channel 5 characteristics register 0x5A0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT5 HCINT5 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x5A8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK5 HCINTMSK5 This register reflects the mask for each channel status described in the previous section. 0x5AC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ5 HCTSIZ5 OTG host channel 5 transfer size register 0x5B0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR6 HCCHAR6 OTG host channel 6 characteristics register 0x5C0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT6 HCINT6 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x5C8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK6 HCINTMSK6 This register reflects the mask for each channel status described in the previous section. 0x5CC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ6 HCTSIZ6 OTG host channel 6 transfer size register 0x5D0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR7 HCCHAR7 OTG host channel 7 characteristics register 0x5E0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT7 HCINT7 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x5E8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK7 HCINTMSK7 This register reflects the mask for each channel status described in the previous section. 0x5EC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ7 HCTSIZ7 OTG host channel 7 transfer size register 0x5F0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR8 HCCHAR8 OTG host channel 8 characteristics register 0x600 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT8 HCINT8 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x608 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK8 HCINTMSK8 This register reflects the mask for each channel status described in the previous section. 0x60C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ8 HCTSIZ8 OTG host channel 8 transfer size register 0x610 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR9 HCCHAR9 OTG host channel 9 characteristics register 0x620 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT9 HCINT9 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x628 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK9 HCINTMSK9 This register reflects the mask for each channel status described in the previous section. 0x62C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ9 HCTSIZ9 OTG host channel 9 transfer size register 0x630 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR10 HCCHAR10 OTG host channel 10 characteristics register 0x640 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT10 HCINT10 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x648 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK10 HCINTMSK10 This register reflects the mask for each channel status described in the previous section. 0x64C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ10 HCTSIZ10 OTG host channel 10 transfer size register 0x650 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR11 HCCHAR11 OTG host channel 11 characteristics register 0x660 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT11 HCINT11 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x668 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK11 HCINTMSK11 This register reflects the mask for each channel status described in the previous section. 0x66C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ11 HCTSIZ11 OTG host channel 11 transfer size register 0x670 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 DCFG DCFG This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. 0x800 0x20 read-write 0x02200000 DSPD DSPD 0 2 NZLSOHSK NZLSOHSK 2 1 DAD DAD 4 7 PFIVL PFIVL 11 2 ERRATIM ERRATIM 15 1 DCTL DCTL OTG device control register 0x804 0x20 0x00000002 RWUSIG RWUSIG 0 1 read-write SDIS SDIS 1 1 read-write GINSTS GINSTS 2 1 read-only GONSTS GONSTS 3 1 read-only TCTL TCTL 4 3 read-write SGINAK SGINAK 7 1 write-only CGINAK CGINAK 8 1 write-only SGONAK SGONAK 9 1 write-only CGONAK CGONAK 10 1 write-only POPRGDNE POPRGDNE 11 1 read-write DSBESLRJCT DSBESLRJCT 18 1 read-write DSTS DSTS This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register. 0x808 0x20 read-only 0x00000010 SUSPSTS SUSPSTS 0 1 ENUMSPD ENUMSPD 1 2 EERR EERR 3 1 FNSOF FNSOF 8 14 DEVLNSTS DEVLNSTS 22 2 DIEPMSK DIEPMSK This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. 0x810 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 EPDM EPDM 1 1 TOM TOM 3 1 ITTXFEMSK ITTXFEMSK 4 1 INEPNMM INEPNMM 5 1 INEPNEM INEPNEM 6 1 NAKM NAKM 13 1 DOEPMSK DOEPMSK This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. 0x814 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 EPDM EPDM 1 1 STUPM STUPM 3 1 OTEPDM OTEPDM 4 1 STSPHSRXM STSPHSRXM 5 1 OUTPKTERRM OUTPKTERRM 8 1 BERRM BERRM 12 1 NAKMSK NAKMSK 13 1 DAINT DAINT When a significant event occurs on an endpoint, a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (DIEPINTx/DOEPINTx). 0x818 0x20 read-only 0x00000000 IEPINT IEPINT 0 16 OEPINT OEPINT 16 16 DAINTMSK DAINTMSK The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the DAINT register bit corresponding to that interrupt is still set. 0x81C 0x20 read-write 0x00000000 IEPM IEPM 0 16 OEPM OEPM 16 16 DVBUSDIS DVBUSDIS This register specifies the VBUS discharge time after VBUS pulsing during SRP. 0x828 0x20 read-write 0x000017D7 VBUSDT VBUSDT 0 16 DVBUSPULSE DVBUSPULSE This register specifies the VBUS pulsing time during SRP. 0x82C 0x20 read-write 0x000005B8 DVBUSP DVBUSP 0 16 DIEPEMPMSK DIEPEMPMSK This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx). 0x834 0x20 read-write 0x00000000 INEPTXFEM INEPTXFEM 0 16 DIEPCTL0 DIEPCTL0 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x900 0x20 0x00000000 MPSIZ MPSIZ 0 2 read-write USBAEP USBAEP 15 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT0 DIEPINT0 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x908 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ0 DIEPTSIZ0 The application must modify this register before enabling endpoint 0. 0x910 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 7 PKTCNT PKTCNT 19 2 DTXFSTS0 DTXFSTS0 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x918 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL1 DIEPCTL1 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x920 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT1 DIEPINT1 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x928 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ1 DIEPTSIZ1 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x930 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DTXFSTS1 DTXFSTS1 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x938 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL2 DIEPCTL2 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x940 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT2 DIEPINT2 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x948 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ2 DIEPTSIZ2 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x950 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DTXFSTS2 DTXFSTS2 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x958 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL3 DIEPCTL3 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x960 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT3 DIEPINT3 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x968 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ3 DIEPTSIZ3 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x970 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DTXFSTS3 DTXFSTS3 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x978 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL4 DIEPCTL4 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x980 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT4 DIEPINT4 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x988 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ4 DIEPTSIZ4 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x990 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DTXFSTS4 DTXFSTS4 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x998 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL5 DIEPCTL5 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x9A0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT5 DIEPINT5 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x9A8 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ5 DIEPTSIZ5 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x9B0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DTXFSTS5 DTXFSTS5 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x9B8 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DOEPCTL0 DOEPCTL0 This section describes the DOEPCTL0 register. 0xB00 0x20 0x00008000 MPSIZ MPSIZ 0 2 read-only USBAEP USBAEP 15 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only EPDIS EPDIS 30 1 read-only EPENA EPENA 31 1 write-only DOEPINT0 DOEPINT0 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xB08 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ0 DOEPTSIZ0 The application must modify this register before enabling endpoint 0. 0xB10 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 7 PKTCNT PKTCNT 19 1 STUPCNT STUPCNT 29 2 DOEPCTL1 DOEPCTL1 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB20 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT1 DOEPINT1 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xB28 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ1 DOEPTSIZ1 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB30 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPCTL2 DOEPCTL2 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB40 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT2 DOEPINT2 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xB48 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ2 DOEPTSIZ2 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB50 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPCTL3 DOEPCTL3 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB60 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT3 DOEPINT3 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xB68 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ3 DOEPTSIZ3 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB70 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPCTL4 DOEPCTL4 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB80 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT4 DOEPINT4 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xB88 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ4 DOEPTSIZ4 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB90 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPCTL5 DOEPCTL5 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xBA0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT5 DOEPINT5 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xBA8 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ5 DOEPTSIZ5 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xBB0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 PCGCCTL PCGCCTL This register is available in host and device modes. 0xE00 0x20 0x200B8000 STPPCLK STPPCLK 0 1 read-write GATEHCLK GATEHCLK 1 1 read-write PHYSUSP PHYSUSP 4 1 read-only ENL1GTG ENL1GTG 5 1 read-write PHYSLEEP PHYSLEEP 6 1 read-only SUSP SUSP 7 1 read-only SEC_OTG_FS 0x52040000 PSSI PSSI PSSI 0x4202C400 0x0 0x400 registers CR CR PSSI control register 0x0 0x20 read-write 0x40000000 CKPOL Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN. 5 1 CKPOL FallingEdge Falling edge active for inputs or rising edge active for outputs 0 RisingEdge Rising edge active for inputs or falling edge active for outputs 1 DEPOL Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface. 6 1 DEPOL ActiveLow PSSI_DE active low (0 indicates that data is valid) 0 ActiveHigh PSSI_DE active high (1 indicates that data is valid) 1 RDYPOL Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface. 8 1 RDYPOL ActiveLow PSSI_RDY active low (0 indicates that the receiver is ready to receive) 0 ActiveHigh PSSI_RDY active high (1 indicates that the receiver is ready to receive) 1 EDM Extended data mode 10 2 EDM BitWidth8 Interface captures 8-bit data on every parallel data clock 0 BitWidth16 The interface captures 16-bit data on every parallel data clock 3 ENABLE PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time. 14 1 ENABLE Disabled PSSI disabled 0 Enabled PSSI enabled 1 DERDYCFG Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity. 18 3 DERDYCFG Disabled PSSI_DE and PSSI_RDY both disabled 0 Rdy Only PSSI_RDY enabled 1 De Only PSSI_DE enabled 2 RdyDeAlt Both PSSI_RDY and PSSI_DE alternate functions enabled 3 RdyDe Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin 4 RdyRemapped Only PSSI_RDY function enabled, but mapped to PSSI_DE pin 5 DeRemapped Only PSSI_DE function enabled, but mapped to PSSI_RDY pin 6 RdyDeBidi Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin 7 DMAEN DMA enable bit 30 1 DMAEN Disabled DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled. 0 Enabled DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR 1 OUTEN Data direction selection bit 31 1 OUTEN ReceiveMode Data is input synchronously with PSSI_PDCK 0 TransmitMode Data is output synchronously with PSSI_PDCK 1 SR SR PSSI status register 0x4 0x20 read-only 0x00000000 RTT4B RTT4B 2 1 RTT4B NotReady FIFO is not ready for a four-byte transfer 0 Ready FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO 1 RTT1B RTT1B 3 1 RTT1B NotReady FIFO is not ready for a 1-byte transfer 0 Ready FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO 1 RIS RIS PSSI raw interrupt status register 0x8 0x20 read-only 0x00000000 OVR_RIS OVR_RIS 1 1 OVR_RIS Cleared No overrun/underrun occurred 0 Occurred An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR 1 IER IER PSSI interrupt enable register 0xC 0x20 read-write 0x00000000 OVR_IE OVR_IE 1 1 OVR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if either an overrun or an underrun error occurred 1 MIS MIS PSSI masked interrupt status register 0x10 0x20 read-only 0x00000000 OVR_MIS OVR_MIS 1 1 OVR_MIS Disabled No interrupt is generated when an overrun/underrun error occurs 0 Enabled An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER 1 ICR ICR PSSI interrupt clear register 0x14 0x20 write-only 0x00000000 OVR_ISC OVR_ISC 1 1 OVR_ISC Clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS 1 DR DR PSSI data register 0x28 0x20 read-write 0xC0000000 BYTE0 Data byte 0 0 8 0 255 BYTE1 Data byte 1 8 8 0 255 BYTE2 Data byte 2 16 8 0 255 BYTE3 Data byte 3 24 8 0 255 SEC_PSSI 0x5202C400 OTFDEC1 On-The-Fly Decryption engine OTFDEC 0x420C5000 0x0 0x400 registers OTFDEC1 OTFDEC1 interrupt 108 CR CR OTFDEC control register 0x0 0x20 read-write 0x00000000 ENC Encryption mode bit 0 1 PRIVCFGR PRIVCFGR OTFDEC privileged access control configuration register 0x10 0x20 read-write 0x00000000 PRIV Encryption mode bit 0 1 R1CFGR R1CFGR OTFDEC region x configuration register 0x20 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REGx_VERSION region firmware version 16 16 read-write R2CFGR R2CFGR OTFDEC region x configuration register 0x50 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REGx_VERSION region firmware version 16 16 read-write R3CFGR R3CFGR OTFDEC region x configuration register 0x80 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REGx_VERSION region firmware version 16 16 read-write R4CFGR R4CFGR OTFDEC region x configuration register 0xB0 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REGx_VERSION region firmware version 16 16 read-write R1STARTADDR R1STARTADDR OTFDEC region x start address register 0x24 0x20 read-write 0x00000000 REGx_START_ADDR Region AXI start address 0 32 R2STARTADDR R2STARTADDR OTFDEC region x start address register 0x54 0x20 read-write 0x00000000 REGx_START_ADDR Region AXI start address 0 32 R3STARTADDR R3STARTADDR OTFDEC region x start address register 0x84 0x20 read-write 0x00000000 REGx_START_ADDR Region AXI start address 0 32 R4STARTADDR R4STARTADDR OTFDEC region x start address register 0xB4 0x20 read-write 0x00000000 REGx_START_ADDR Region AXI start address 0 32 R1ENDADDR R1ENDADDR OTFDEC region x end address register 0x28 0x20 read-write 0x00000FFF REGx_END_ADDR Region AXI end address 0 32 R2ENDADDR R2ENDADDR OTFDEC region x end address register 0x58 0x20 read-write 0x00000FFF REGx_END_ADDR Region AXI end address 0 32 R3ENDADDR R3ENDADDR OTFDEC region x end address register 0x88 0x20 read-write 0x00000FFF REGx_END_ADDR Region AXI end address 0 32 R4ENDADDR R4ENDADDR OTFDEC region x end address register 0x8C 0x20 read-write 0x00000FFF REGx_END_ADDR Region AXI end address 0 32 R1NONCER0 R1NONCER0 OTFDEC region x nonce register 0 0x2C 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R2NONCER0 R2NONCER0 OTFDEC region x nonce register 0 0x5C 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R3NONCER0 R3NONCER0 OTFDEC region x nonce register 0 R4ENDADDR 0x8C 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R4NONCER0 R4NONCER0 OTFDEC region x nonce register 0 0xBC 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R1NONCER1 R1NONCER1 OTFDEC region x nonce register 1 0x30 0x20 read-write 0x00000000 REGx_NONCE Region nonce 0 32 R2NONCER1 R2NONCER1 OTFDEC region x nonce register 1 0x60 0x20 read-write 0x00000000 REGx_NONCE Region nonce, bits [63:32]REGx_NONCE[63:32] 0 32 R3NONCER1 R3NONCER1 OTFDEC region x nonce register 1 0x90 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R4NONCER1 R4NONCER1 OTFDEC region x nonce register 1 0xC0 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R1KEYR0 R1KEYR0 OTFDEC region x key register 0 0x34 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R2KEYR0 R2KEYR0 OTFDEC region x key register 0 0x64 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R3KEYR0 R3KEYR0 OTFDEC region x key register 0 0x94 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R4KEYR0 R4KEYR0 OTFDEC region x key register 0 0xC4 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R1KEYR1 R1KEYR1 OTFDEC region x key register 1 0x38 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R2KEYR1 R2KEYR1 OTFDEC region x key register 1 0x68 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R3KEYR1 R3KEYR1 OTFDEC region x key register 1 0x98 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R4KEYR1 R4KEYR1 OTFDEC region x key register 1 0xC8 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R1KEYR2 R1KEYR2 OTFDEC region x key register 2 0x3C 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R2KEYR2 R2KEYR2 OTFDEC region x key register 2 0x6C 0x20 write-only 0x00000000 REGx_KEY_ REGx_KEY 0 32 R3KEYR2 R3KEYR2 OTFDEC region x key register 2 0x9C 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R4KEYR2 R4KEYR2 OTFDEC region x key register 2 0xCC 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R1KEYR3 R1KEYR3 OTFDEC region x key register 3 0x40 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R2KEYR3 R2KEYR3 OTFDEC region x key register 3 0x70 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R3KEYR3 R3KEYR3 OTFDEC region x key register 3 0xA0 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R4KEYR3 R4KEYR3 OTFDEC region x key register 3 0xD0 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 ISR ISR OTFDEC interrupt status register 0x300 0x20 read-only 0x00000000 SEIF Security Error Interrupt Flag status 0 1 XONEIF Execute-only execute-Never Error Interrupt Flag status 1 1 KEIF Key Error Interrupt Flag status 2 1 ICR ICR OTFDEC interrupt clear register 0x304 0x20 read-only 0x00000000 SEIF SEIF 0 1 XONEIF Execute-only execute-Never Error Interrupt Flag clear 1 1 KEIF KEIF 2 1 IER IER OTFDEC interrupt enable register 0x308 0x20 read-write 0x00000000 SEIE Security Error Interrupt Enable 0 1 XONEIE XONEIE 1 1 KEIE KEIE 2 1 SEC_OTFDEC1 0x520C5000 OTFDEC2 0x420C5400 OTFDEC2 OTFDEC2 interrupt 109 SEC_OTFDEC2 0x520C5400 DMA2D DMA2D controller DMA2D 0x4002B000 0x0 0xC00 registers DMA2D DMA2D global interrupt 118 CR CR control register 0x0 0x20 read-write 0x00000000 MODE DMA2D mode 16 2 MODE MemoryToMemory Memory-to-memory (FG fetch only) 0 MemoryToMemoryPFC Memory-to-memory with PFC (FG fetch only with FG PFC active) 1 MemoryToMemoryPFCBlending Memory-to-memory with blending (FG and BG fetch with PFC and blending) 2 RegisterToMemory Register-to-memory 3 CEIE Configuration Error Interrupt Enable 13 1 CEIE Disabled CE interrupt disabled 0 Enabled CE interrupt enabled 1 CTCIE CLUT transfer complete interrupt enable 12 1 CTCIE Disabled CTC interrupt disabled 0 Enabled CTC interrupt enabled 1 CAEIE CLUT access error interrupt enable 11 1 CAEIE Disabled CAE interrupt disabled 0 Enabled CAE interrupt enabled 1 TWIE Transfer watermark interrupt enable 10 1 TWIE Disabled TW interrupt disabled 0 Enabled TW interrupt enabled 1 TCIE Transfer complete interrupt enable 9 1 TCIE Disabled TC interrupt disabled 0 Enabled TC interrupt enabled 1 TEIE Transfer error interrupt enable 8 1 TEIE Disabled TE interrupt disabled 0 Enabled TE interrupt enabled 1 LOM Line Offset Mode 6 1 ABORT Abort 2 1 ABORT AbortRequest Transfer abort requested 1 SUSP Suspend 1 1 SUSP NotSuspended Transfer not suspended 0 Suspended Transfer suspended 1 START Start 0 1 START Start Launch the DMA2D 1 ISR ISR Interrupt Status Register 0x4 0x20 read-only 0x00000000 CEIF Configuration error interrupt flag 5 1 CTCIF CLUT transfer complete interrupt flag 4 1 CAEIF CLUT access error interrupt flag 3 1 TWIF Transfer watermark interrupt flag 2 1 TCIF Transfer complete interrupt flag 1 1 TEIF Transfer error interrupt flag 0 1 IFCR IFCR interrupt flag clear register 0x8 0x20 read-write 0x00000000 CCEIF Clear configuration error interrupt flag 5 1 CCEIF Clear Clear the CEIF flag in the ISR register 1 CCTCIF Clear CLUT transfer complete interrupt flag 4 1 CCTCIF Clear Clear the CTCIF flag in the ISR register 1 CAECIF Clear CLUT access error interrupt flag 3 1 CAECIF Clear Clear the CAEIF flag in the ISR register 1 CTWIF Clear transfer watermark interrupt flag 2 1 CTWIF Clear Clear the TWIF flag in the ISR register 1 CTCIF Clear transfer complete interrupt flag 1 1 CTCIF Clear Clear the TCIF flag in the ISR register 1 CTEIF Clear Transfer error interrupt flag 0 1 CTEIF Clear Clear the TEIF flag in the ISR register 1 FGMAR FGMAR foreground memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 FGOR FGOR foreground offset register 0x10 0x20 read-write 0x00000000 LO Line offset 0 16 0 65535 BGMAR BGMAR background memory address register 0x14 0x20 read-write 0x00000000 MA Memory address 0 32 BGOR BGOR background offset register 0x18 0x20 read-write 0x00000000 LO Line offset 0 16 0 65535 FGPFCCR FGPFCCR foreground PFC control register 0x1C 0x20 read-write 0x00000000 ALPHA Alpha value 24 8 0 255 RBS Red Blue Swap 21 1 RBS Regular No Red Blue Swap (RGB or ARGB) 0 Swap Red Blue Swap (BGR or ABGR) 1 AI Alpha Inverted 20 1 AI RegularAlpha Regular alpha 0 InvertedAlpha Inverted alpha 1 AM Alpha mode 16 2 AM NoModify No modification of alpha channel 0 Replace Replace with value in ALPHA[7:0] 1 Multiply Multiply with value in ALPHA[7:0] 2 CS CLUT size 8 8 0 255 START Start 5 1 START Start Start the automatic loading of the CLUT 1 CCM CLUT color mode 4 1 CCM ARGB8888 CLUT color format ARGB8888 0 RGB888 CLUT color format RGB888 1 CM Color mode 0 4 CM ARGB8888 Color mode ARGB8888 0 RGB888 Color mode RGB888 1 RGB565 Color mode RGB565 2 ARGB1555 Color mode ARGB1555 3 ARGB4444 Color mode ARGB4444 4 L8 Color mode L8 5 AL44 Color mode AL44 6 AL88 Color mode AL88 7 L4 Color mode L4 8 A8 Color mode A8 9 A4 Color mode A4 10 YCbCr Color mode YCbCr 11 FGCOLR FGCOLR foreground color register 0x20 0x20 read-write 0x00000000 RED Red Value 16 8 0 255 GREEN Green Value 8 8 0 255 BLUE Blue Value 0 8 0 255 BGPFCCR BGPFCCR background PFC control register 0x24 0x20 read-write 0x00000000 ALPHA Alpha value 24 8 0 255 RBS Red Blue Swap 21 1 RBS Regular No Red Blue Swap (RGB or ARGB) 0 Swap Red Blue Swap (BGR or ABGR) 1 AI Alpha Inverted 20 1 AI RegularAlpha Regular alpha 0 InvertedAlpha Inverted alpha 1 AM Alpha mode 16 2 AM NoModify No modification of alpha channel 0 Replace Replace with value in ALPHA[7:0] 1 Multiply Multiply with value in ALPHA[7:0] 2 CS CLUT size 8 8 0 255 START Start 5 1 START Start Start the automatic loading of the CLUT 1 CCM CLUT Color mode 4 1 CCM ARGB8888 CLUT color format ARGB8888 0 RGB888 CLUT color format RGB888 1 CM Color mode 0 4 CM ARGB8888 Color mode ARGB8888 0 RGB888 Color mode RGB888 1 RGB565 Color mode RGB565 2 ARGB1555 Color mode ARGB1555 3 ARGB4444 Color mode ARGB4444 4 L8 Color mode L8 5 AL44 Color mode AL44 6 AL88 Color mode AL88 7 L4 Color mode L4 8 A8 Color mode A8 9 A4 Color mode A4 10 BGCOLR BGCOLR background color register 0x28 0x20 read-write 0x00000000 RED Red Value 16 8 0 255 GREEN Green Value 8 8 0 255 BLUE Blue Value 0 8 0 255 FGCMAR FGCMAR foreground CLUT memory address register 0x2C 0x20 read-write 0x00000000 MA Memory Address 0 32 BGCMAR BGCMAR background CLUT memory address register 0x30 0x20 read-write 0x00000000 MA Memory address 0 32 OPFCCR OPFCCR output PFC control register 0x34 0x20 read-write 0x00000000 RBS Red Blue Swap 21 1 RBS Regular No Red Blue Swap (RGB or ARGB) 0 Swap Red Blue Swap (BGR or ABGR) 1 AI Alpha Inverted 20 1 AI RegularAlpha Regular alpha 0 InvertedAlpha Inverted alpha 1 SB Swap Bytes 9 1 SB Regular Regular byte order 0 SwapBytes Bytes are swapped two by two 1 CM Color mode 0 3 CM ARGB8888 ARGB8888 0 RGB888 RGB888 1 RGB565 RGB565 2 ARGB1555 ARGB1555 3 ARGB4444 ARGB4444 4 OCOLR_RGB888 OCOLR_RGB888 output color register 0x38 0x20 read-write 0x00000000 APLHA Alpha Channel Value 24 8 RED Red Value 16 8 GREEN Green Value 8 8 BLUE Blue Value 0 8 OCOLR_RGB565 OCOLR_RGB565 output color register OCOLR_RGB888 0x38 0x20 read-write 0x00000000 RED Red value in RGB565 mode 11 5 GREEN Green value in RGB565 mode 5 6 BLUE Blue value in RGB565 mode 0 5 OCOLR_ARGB1555 OCOLR_ARGB1555 output color register OCOLR_RGB888 0x38 0x20 read-write 0x00000000 A Alpha channel value in ARGB1555 mode 15 1 RED Red value in ARGB1555 mode 10 5 GREEN Green value in ARGB1555 mode 5 5 BLUE Blue value in ARGB1555 mode 0 5 OCOLR_ARGB4444 OCOLR_ARGB4444 output color register OCOLR_RGB888 0x38 0x20 read-write 0x00000000 ALPHA Alpha channel value in ARGB4444 12 4 RED Red value in ARGB4444 mode 8 4 GREEN Green value in ARGB4444 mode 4 4 BLUE Blue value in ARGB4444 mode 0 4 OMAR OMAR output memory address register 0x3C 0x20 read-write 0x00000000 MA Memory Address 0 32 OOR OOR output offset register 0x40 0x20 read-write 0x00000000 LO Line Offset 0 16 0 65535 NLR NLR number of line register 0x44 0x20 read-write 0x00000000 PL Pixel per lines 16 14 0 16383 NL Number of lines 0 16 0 65535 LWR LWR line watermark register 0x48 0x20 read-write 0x00000000 LW Line watermark 0 16 AMTCR AMTCR AHB master timer configuration register 0x4C 0x20 read-write 0x00000000 DT Dead Time 8 8 0 255 EN Enable 0 1 EN Disabled Disabled AHB/AXI dead-time functionality 0 Enabled Enabled AHB/AXI dead-time functionality 1 FGCLUT FGCLUT FGCLUT 0x400 0x20 read-write 0x00000000 APLHA APLHA 24 8 RED RED 16 8 GREEN GREEN 8 8 BLUE BLUE 0 8 BGCLUT BGCLUT BGCLUT 0x800 0x20 read-write 0x00000000 APLHA APLHA 24 8 RED RED 16 8 GREEN GREEN 8 8 BLUE BLUE 0 8 SEC_DMA2D 0x5002B000 RAMCFG RAMCFG RAMCFG 0x40026000 0x0 0x1000 registers RAMCFG RAM configuration global interrupt 5 RAM1CR RAM1CR RAMCFG SRAM x control register 0x0 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 RAM1ISR RAM1ISR RAMCFG RAMx interrupt status register 0x8 0x20 read-only 0x00000000 SEDC SEDC 0 1 DED DED 1 1 SRAMBUSY SRAMBUSY 8 1 RAM1ERKEYR RAM1ERKEYR RAMCFG SRAM x erase key register 0x28 0x20 write-only 0x00000000 ERASEKEY ERASEKEY 0 8 RAM2CR RAM2CR RAMCFG SRAM x control register 0x40 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 RAM2IER RAM2IER RAMCFG SRAM x interrupt enable register 0x44 0x20 read-write 0x00000000 SEIE SEIE 0 1 DEIE DEIE 1 1 ECCNMI ECCNMI 3 1 RAM2ISR RAM2ISR RAMCFG RAMx interrupt status register 0x48 0x20 read-only 0x00000000 SEDC SEDC 0 1 DED DED 1 1 SRAMBUSY SRAMBUSY 8 1 RAM2SEAR RAM2SEAR RAMCFG RAM x ECC single error address register 0x4C 0x20 read-only 0x00000000 ESEA ESEA 0 32 RAM2DEAR RAM2DEAR RAMCFG RAM x ECC double error address register 0x50 0x20 read-only 0x00000000 EDEA EDEA 0 32 RAM2ICR RAM2ICR RAMCFG RAM x interrupt clear register x 0x54 0x20 read-write 0x00000000 CSEDC CSEDC 0 1 CDED CDED 1 1 RAM2WPR1 RAM2WPR1 RAMCFG SRAM2 write protection register 1 0x58 0x20 read-write 0x00000000 P0WP P0WP 0 1 P1WP P1WP 1 1 P2WP P2WP 2 1 P3WP P3WP 3 1 P4WP P4WP 4 1 P5WP P5WP 5 1 P6WP P6WP 6 1 P7WP P7WP 7 1 P8WP P8WP 8 1 P9WP P9WP 9 1 P10WP P10WP 10 1 P11WP P11WP 11 1 P12WP P12WP 12 1 P13WP P13WP 13 1 P14WP P14WP 14 1 P15WP P15WP 15 1 P16WP P16WP 16 1 P17WP P17WP 17 1 P18WP P18WP 18 1 P19WP P19WP 19 1 P20WP P20WP 20 1 P21WP P21WP 21 1 P22WP P22WP 22 1 P23WP P23WP 23 1 P24WP P24WP 24 1 P25WP P25WP 25 1 P26WP P26WP 26 1 P27WP P27WP 27 1 P28WP P28WP 28 1 P29WP P29WP 29 1 P30WP P30WP 30 1 P31WP P31WP 31 1 RAM2WPR2 RAM2WPR2 RAMCFG SRAM2 write protection register 2 0x5C 0x20 read-write 0x00000000 P32WP P32WP 0 1 P33WP P33WP 1 1 P34WP P34WP 2 1 P35WP P35WP 3 1 P36WP P36WP 4 1 P37WP P37WP 5 1 P38WP P38WP 6 1 P39WP P39WP 7 1 P40WP P40WP 8 1 P41WP P41WP 9 1 P42WP P42WP 10 1 P43WP P43WP 11 1 P44WP P44WP 12 1 P45WP P45WP 13 1 P46WP P46WP 14 1 P47WP P47WP 15 1 P48WP P48WP 16 1 P49WP P49WP 17 1 P50WP P50WP 18 1 P51WP P51WP 19 1 P52WP P52WP 20 1 P53WP P53WP 21 1 P54WP P54WP 22 1 P55WP P55WP 23 1 P56WP P56WP 24 1 P57WP P57WP 25 1 P58WP P58WP 26 1 P59WP P59WP 27 1 P60WP P60WP 28 1 P61WP P61WP 29 1 P62WP P62WP 30 1 P63WP P63WP 31 1 RAM2ECCKEYR RAM2ECCKEYR RAMCFG SRAM x ECC key register 0x64 0x20 write-only 0x00000000 ECCKEY ECCKEY 0 8 RAM2ERKEYR RAM2ERKEYR RAMCFG SRAM x erase key register 0x68 0x20 write-only 0x00000000 ERASEKEY ERASEKEY 0 8 RAM3CR RAM3CR RAMCFG SRAM x control register 0x80 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 RAM3IER RAM3IER RAMCFG SRAM x interrupt enable register 0x84 0x20 read-write 0x00000000 SEIE SEIE 0 1 DEIE DEIE 1 1 ECCNMI ECCNMI 3 1 RAM3ISR RAM3ISR RAMCFG RAMx interrupt status register 0x88 0x20 read-only 0x00000000 SEDC SEDC 0 1 DED DED 1 1 SRAMBUSY SRAMBUSY 8 1 RAM3SEAR RAM3SEAR RAMCFG RAM x ECC single error address register 0x8C 0x20 read-only 0x00000000 ESEA ESEA 0 32 RAM3DEAR RAM3DEAR RAMCFG RAM x ECC double error address register 0x90 0x20 read-only 0x00000000 EDEA EDEA 0 32 RAM3ICR RAM3ICR RAMCFG RAM x interrupt clear register x 0x94 0x20 read-write 0x00000000 CSEDC CSEDC 0 1 CDED CDED 1 1 RAM3ECCKEYR RAM3ECCKEYR RAMCFG SRAM x ECC key register 0xA4 0x20 write-only 0x00000000 ECCKEY ECCKEY 0 8 RAM3ERKEYR RAM3ERKEYR RAMCFG SRAM x erase key register 0xA8 0x20 write-only 0x00000000 ERASEKEY ERASEKEY 0 8 RAM4CR RAM4CR RAMCFG SRAM x control register 0xC0 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 RAM4ISR RAM4ISR RAMCFG RAMx interrupt status register 0xC8 0x20 read-only 0x00000000 SEDC SEDC 0 1 DED DED 1 1 SRAMBUSY SRAMBUSY 8 1 RAM4ERKEYR RAM4ERKEYR RAMCFG SRAM x erase key register 0xE8 0x20 write-only 0x00000000 ERASEKEY ERASEKEY 0 8 RAM5CR RAM5CR RAMCFG SRAM x control register 0x100 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 RAM5IER RAM5IER RAMCFG SRAM x interrupt enable register 0x104 0x20 read-write 0x00000000 SEIE SEIE 0 1 DEIE DEIE 1 1 ECCNMI ECCNMI 3 1 RAM5ISR RAM5ISR RAMCFG RAMx interrupt status register 0x108 0x20 read-only 0x00000000 SEDC SEDC 0 1 DED DED 1 1 SRAMBUSY SRAMBUSY 8 1 RAM5SEAR RAM5SEAR RAMCFG RAM x ECC single error address register 0x10C 0x20 read-only 0x00000000 ESEA ESEA 0 32 RAM5DEAR RAM5DEAR RAMCFG RAM x ECC double error address register 0x110 0x20 read-only 0x00000000 EDEA EDEA 0 32 RAM5ICR RAM5ICR RAMCFG RAM x interrupt clear register x 0x114 0x20 read-write 0x00000000 CSEDC CSEDC 0 1 CDED CDED 1 1 SEC_RAMCFG 0x50026000 DCMI Digital camera interface DCMI 0x4202C000 0x0 0x400 registers DCMI Digital camera interface 119 CR CR control register 0x0 0x20 read-write 0x00000000 OELS Odd/Even Line Select (Line Select Start) 20 1 OELS Odd Interface captures first line after the frame start, second one being dropped 0 Even Interface captures second line from the frame start, first one being dropped 1 LSM Line Select mode 19 1 LSM All Interface captures all received lines 0 Half Interface captures one line out of two 1 OEBS Odd/Even Byte Select (Byte Select Start) 18 1 OEBS Odd Interface captures first data (byte or double byte) from the frame/line start, second one being dropped 0 Even Interface captures second data (byte or double byte) from the frame/line start, first one being dropped 1 BSM Byte Select mode 16 2 BSM All Interface captures all received data 0 EveryOther Interface captures every other byte from the received data 1 Fourth Interface captures one byte out of four 2 TwoOfFour Interface captures two bytes out of four 3 ENABLE DCMI enable 14 1 ENABLE Disabled DCMI disabled 0 Enabled DCMI enabled 1 EDM Extended data mode 10 2 EDM BitWidth8 Interface captures 8-bit data on every pixel clock 0 BitWidth10 Interface captures 10-bit data on every pixel clock 1 BitWidth12 Interface captures 12-bit data on every pixel clock 2 BitWidth14 Interface captures 14-bit data on every pixel clock 3 FCRC Frame capture rate control 8 2 FCRC All All frames are captured 0 Alternate Every alternate frame captured (50% bandwidth reduction) 1 OneOfFour One frame out of four captured (75% bandwidth reduction) 2 VSPOL Vertical synchronization polarity 7 1 VSPOL ActiveLow DCMI_VSYNC active low 0 ActiveHigh DCMI_VSYNC active high 1 HSPOL Horizontal synchronization polarity 6 1 HSPOL ActiveLow DCMI_HSYNC active low 0 ActiveHigh DCMI_HSYNC active high 1 PCKPOL Pixel clock polarity 5 1 PCKPOL FallingEdge Falling edge active 0 RisingEdge Rising edge active 1 ESS Embedded synchronization select 4 1 ESS Hardware Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals 0 Embedded Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow 1 JPEG JPEG format 3 1 JPEG Uncompressed Uncompressed video format 0 JPEG This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode 1 CROP Crop feature 2 1 CROP Full The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four 0 Cropped Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured 1 CM Capture mode 1 1 CM Continuous Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA 0 Snapshot Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset 1 CAPTURE Capture enable 0 1 CAPTURE Disabled Capture disabled 0 Enabled Capture enabled 1 SR SR status register 0x4 0x20 read-only 0x00000000 FNE FIFO not empty 2 1 FNE NotEmpty FIFO contains valid data 0 Empty FIFO empty 1 VSYNC Vertical synchronization 1 1 VSYNC ActiveFrame Active frame 0 BetweenFrames Synchronization between frames 1 HSYNC Horizontal synchronization 0 1 HSYNC ActiveLine Active line 0 BetweenLines Synchronization between lines 1 RIS RIS raw interrupt status register 0x8 0x20 read-only 0x00000000 LINE_RIS Line raw interrupt status 4 1 LINE_RIS Cleared Interrupt cleared 0 Set Interrupt set 1 VSYNC_RIS DCMI_VSYNC raw interrupt status 3 1 VSYNC_RIS Cleared Interrupt cleared 0 Set Interrupt set 1 ERR_RIS Synchronization error raw interrupt status 2 1 ERR_RIS NoError No synchronization error detected 0 SynchronizationError Embedded synchronization characters are not received in the correct order 1 OVR_RIS Overrun raw interrupt status 1 1 OVR_RIS NoOverrun No data buffer overrun occurred 0 OverrunOccured A data buffer overrun occurred and the data FIFO is corrupted. The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register 1 FRAME_RIS Capture complete raw interrupt status 0 1 FRAME_RIS NoNewCapture No new capture 0 FrameCaptured A frame has been captured 1 IER IER interrupt enable register 0xC 0x20 read-write 0x00000000 LINE_IE Line interrupt enable 4 1 LINE_IE Disabled No interrupt generation when the line is received 0 Enabled An Interrupt is generated when a line has been completely received 1 VSYNC_IE DCMI_VSYNC interrupt enable 3 1 VSYNC_IE Disabled No interrupt generation 0 Enabled An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state 1 ERR_IE Synchronization error interrupt enable 2 1 ERR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if the embedded synchronization codes are not received in the correct order 1 OVR_IE Overrun interrupt enable 1 1 OVR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received 1 FRAME_IE Capture complete interrupt enable 0 1 FRAME_IE Disabled No interrupt generation 0 Enabled An interrupt is generated at the end of each received frame/crop window (in crop mode) 1 MIS MIS masked interrupt status register 0x10 0x20 read-only 0x00000000 LINE_MIS Line masked interrupt status 4 1 LINE_MIS Disabled No interrupt generation when the line is received 0 Enabled An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER 1 VSYNC_MIS VSYNC masked interrupt status 3 1 VSYNC_MIS Disabled No interrupt is generated on DCMI_VSYNC transitions 0 Enabled An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER 1 ERR_MIS Synchronization error masked interrupt status 2 1 ERR_MIS Disabled No interrupt is generated on a synchronization error 0 Enabled An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set 1 OVR_MIS Overrun masked interrupt status 1 1 OVR_MIS Disabled No interrupt is generated on overrun 0 Enabled An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER 1 FRAME_MIS Capture complete masked interrupt status 0 1 FRAME_MIS Disabled No interrupt is generated after a complete capture 0 Enabled An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER 1 ICR ICR interrupt clear register 0x14 0x20 write-only 0x00000000 LINE_ISC line interrupt status clear 4 1 LINE_ISC Clear Setting this bit clears the LINE_RIS flag in the DCMI_RIS register 1 VSYNC_ISC Vertical Synchronization interrupt status clear 3 1 VSYNC_ISC Clear Setting this bit clears the VSYNC_RIS flag in the DCMI_RIS register 1 ERR_ISC Synchronization error interrupt status clear 2 1 ERR_ISC Clear Setting this bit clears the ERR_RIS flag in the DCMI_RIS register 1 OVR_ISC Overrun interrupt status clear 1 1 OVR_ISC Clear Setting this bit clears the OVR_RIS flag in the DCMI_RIS register 1 FRAME_ISC Capture complete interrupt status clear 0 1 FRAME_ISC Clear Setting this bit clears the FRAME_RIS flag in the DCMI_RIS register 1 ESCR ESCR background offset register 0x18 0x20 read-write 0x00000000 FEC Frame end delimiter code 24 8 LEC Line end delimiter code 16 8 LSC Line start delimiter code 8 8 FSC Frame start delimiter code 0 8 ESUR ESUR embedded synchronization unmask register 0x1C 0x20 read-write 0x00000000 FEU Frame end delimiter unmask 24 8 LEU Line end delimiter unmask 16 8 LSU Line start delimiter unmask 8 8 FSU Frame start delimiter unmask 0 8 CWSTRT CWSTRT crop window start 0x20 0x20 read-write 0x00000000 VST Vertical start line count 16 13 0 8191 HOFFCNT Horizontal offset count 0 14 0 16383 CWSIZE CWSIZE crop window size 0x24 0x20 read-write 0x00000000 VLINE Vertical line count 16 14 0 16383 CAPCNT Capture count 0 14 0 16383 DR DR data register 0x28 0x20 read-only 0x00000000 4 0x8 0-3 BYTE%s Data byte %s 0 8 0 255 SEC_DCMI 0x5202C000 DCB Debug Control Block DCB 0xE000EE08 0x0 0x5 registers DSCSR DSCSR Debug Security Control and Status Register 0x0 0x20 read-write 0x00000000 CDS Current domain Secure 16 1

RetroSearch is an open source project built by @garambo | Open a GitHub Issue

Search and Browse the WWW like it's 1997 | Search results from DuckDuckGo

HTML: 3.2 | Encoding: UTF-8 | Version: 0.7.4