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Showing content from https://stm32-rs.github.io/stm32-rs/stm32l562.svd.patched below:

STM32L562 1.0 STM32L562 CM33 r0p1 little true true 3 false 8 32 0x20 0x00000000 0xFFFFFFFF ADC1 Analog-to-Digital Converter ADC 0x42028000 0x0 0xB8 registers ISR ISR interrupt and status register 0x0 0x20 read-write 0x00000000 JQOVF JQOVF 10 1 oneToClear JQOVFR read NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 JQOVFW write Clear Clear injected context queue overflow flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 oneToClear AWD1R read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD1W write Clear Clear analog watchdog event occurred flag 1 JEOS JEOS 6 1 oneToClear JEOSR read NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 JEOSW write Clear Clear Injected sequence complete flag 1 JEOC JEOC 5 1 oneToClear JEOCR read NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOCW write Clear Clear injected conversion complete flag 1 OVR OVR 4 1 oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear overrun occurred flag 1 EOS EOS 3 1 oneToClear EOSR read NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 EOSW write Clear Clear regular sequence complete flag 1 EOC EOC 2 1 oneToClear EOCR read NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOCW write Clear Clear regular conversion complete flag 1 EOSMP EOSMP 1 1 oneToClear EOSMPR read NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOSMPW write Clear Clear end of sampling phase reached flag 1 ADRDY ADRDY 0 1 oneToClear ADRDYR read NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 ADRDYW write Clear Clear ADC is ready to start conversion flag 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 JQOVFIE JQOVFIE 10 1 JQOVFIE Disabled Injected context queue overflow interrupt disabled 0 Enabled Injected context queue overflow interrupt enabled 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 AWD1IE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 JEOSIE JEOSIE 6 1 JEOSIE Disabled End of injected sequence interrupt disabled 0 Enabled End of injected sequence interrupt enabled 1 JEOCIE JEOCIE 5 1 JEOCIE Disabled End of injected conversion interrupt disabled 0 Enabled End of injected conversion interrupt enabled 1 OVRIE OVRIE 4 1 OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled 1 EOSIE EOSIE 3 1 EOSIE Disabled End of regular sequence interrupt disabled 0 Enabled End of regular sequence interrupt enabled 1 EOCIE EOCIE 2 1 EOCIE Disabled End of regular conversion interrupt disabled 0 Enabled End of regular conversion interrupt enabled 1 EOSMPIE EOSMPIE 1 1 EOSMPIE Disabled End of regular conversion sampling phase interrupt disabled 0 Enabled End of regular conversion sampling phase interrupt enabled 1 ADRDYIE ADRDYIE 0 1 ADRDYIE Disabled ADC ready interrupt disabled 0 Enabled ADC ready interrupt enabled 1 CR CR control register 0x8 0x20 read-write 0x00000000 ADCAL ADCAL 31 1 oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 ADCALDIF ADCALDIF 30 1 ADCALDIF SingleEnded Calibration for single-ended mode 0 Differential Calibration for differential mode 1 DEEPPWD DEEPPWD 29 1 DEEPPWD NotDeepPowerDown ADC not in Deep-power down 0 DeepPowerDown ADC in Deep-power-down (default reset state) 1 ADVREGEN ADVREGEN 28 1 ADVREGEN Disabled ADC Voltage regulator disabled 0 Enabled ADC Voltage regulator enabled 1 ADSTP ADSTP 4 1 oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 JADSTP JADSTP 5 1 oneToSet read write ADSTART ADSTART 2 1 oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 JADSTART JADSTART 3 1 oneToSet read write ADDIS ADDIS 1 1 oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADEN ADEN 0 1 oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 CFGR CFGR configuration register 0xC 0x20 read-write 0x00000000 JQDIS JQDIS 31 1 AWD1CH AWDCH1CH 26 5 0 18 JAUTO JAUTO 25 1 JAUTO Disabled Automatic injected group conversion disabled 0 Enabled Automatic injected group conversion enabled 1 JAWD1EN JAWD1EN 24 1 JAWD1EN Disabled Analog watchdog 1 disabled on injected channels 0 Enabled Analog watchdog 1 enabled on injected channels 1 AWD1EN AWD1EN 23 1 AWD1EN Disabled Analog watchdog 1 disabled on regular channels 0 Enabled Analog watchdog 1 enabled on regular channels 1 AWD1SGL AWD1SGL 22 1 AWD1SGL All Analog watchdog 1 enabled on all channels 0 Single Analog watchdog 1 enabled on single channel selected in AWD1CH 1 JQM JQM 21 1 JQM Mode0 JSQR Mode 0: Queue maintains the last written configuration into JSQR 0 Mode1 JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence 1 JDISCEN JDISCEN 20 1 JDISCEN Disabled Discontinuous mode on injected channels disabled 0 Enabled Discontinuous mode on injected channels enabled 1 DISCNUM DISCNUM 17 3 0 7 DISCEN DISCEN 16 1 DISCEN Disabled Discontinuous mode on regular channels disabled 0 Enabled Discontinuous mode on regular channels enabled 1 AUTDLY AUTDLY 14 1 AUTDLY Off Auto delayed conversion mode off 0 On Auto delayed conversion mode on 1 CONT CONT 13 1 CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 OVRMOD OVRMOD 12 1 OVRMOD Preserve Preserve DR register when an overrun is detected 0 Overwrite Overwrite DR register when an overrun is detected 1 EXTEN EXTEN 10 2 EXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 EXTSEL EXTSEL 6 4 EXTSEL TIM1_CC1 Timer 1 CC1 event 0 TIM1_CC2 Timer 1 CC2 event 1 TIM1_CC3 Timer 1 CC3 event 2 TIM2_CC2 Timer 2 CC2 event 3 TIM3_TRGO Timer 3 TRGO event 4 EXTI11 EXTI line 11 6 TIM1_TRGO Timer 1 TRGO event 9 TIM1_TRGO2 Timer 1 TRGO2 event 10 TIM2_TRGO Timer 2 TRGO event 11 TIM6_TRGO Timer 6 TRGO event 13 TIM15_TRGO Timer 15 TRGO event 14 TIM3_CC4 Timer 3 CC4 event 15 ALIGN ALIGN 5 1 ALIGN Right Right alignment 0 Left Left alignment 1 RES RES 3 2 RES Bits12 12-bit 0 Bits10 10-bit 1 Bits8 8-bit 2 Bits6 6-bit 3 DMACFG DMACFG 1 1 DMACFG OneShot DMA One Shot mode selected 0 Circular DMA Circular mode selected 1 DMAEN DMAEN 0 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 CFGR2 CFGR2 configuration register 0x10 0x20 read-write 0x00000000 ROVSM EXTEN 10 1 ROVSM ContinuedMode When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 0 ResumedMode When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) 1 TOVS EXTSEL 9 1 TOVS All All oversampled conversions for a channel are done consecutively following a trigger 0 Single Each oversampled conversion for a channel needs a new trigger 1 OVSS ALIGN 5 4 OVSS NoShift No Shift 0 Shift1Bit Shift 1-bit 1 Shift2Bit Shift 2-bit 2 Shift3Bit Shift 3-bit 3 Shift4Bit Shift 4-bit 4 Shift5Bit Shift 5-bit 5 Shift6Bit Shift 6-bit 6 Shift7Bit Shift 7-bit 7 Shift8Bit Shift 8-bit 8 OVSR RES 2 3 OVSR Ratio2 2x 0 Ratio4 4x 1 Ratio8 8x 2 Ratio16 16x 3 Ratio32 32x 4 Ratio64 64x 5 Ratio128 128x 6 Ratio256 256x 7 JOVSE DMACFG 1 1 JOVSE Disabled Injected Oversampling disabled 0 Enabled Injected Oversampling enabled 1 ROVSE DMAEN 0 1 ROVSE Disabled Regular Oversampling disabled 0 Enabled Regular Oversampling enabled 1 SMPR1 SMPR1 sample time register 1 0x14 0x20 read-write 0x00000000 10 0x3 0-9 SMP%s Channel %s sample time selection 0 3 SMP0 Cycles2_5 2.5 ADC clock cycles 0 Cycles6_5 6.5 ADC clock cycles 1 Cycles12_5 12.5 ADC clock cycles 2 Cycles24_5 24.5 ADC clock cycles 3 Cycles47_5 47.5 ADC clock cycles 4 Cycles92_5 92.5 ADC clock cycles 5 Cycles247_5 247.5 ADC clock cycles 6 Cycles640_5 640.5 ADC clock cycles 7 SMPR2 SMPR2 sample time register 2 0x18 0x20 read-write 0x00000000 9 0x3 10-18 SMP%s Channel %s sample time selection 0 3 TR1 TR1 watchdog threshold register 1 0x20 0x20 read-write 0x0FFF0000 HT1 HT1 16 12 0 4095 LT1 LT1 0 12 0 4095 TR2 TR2 watchdog threshold register 0x24 0x20 read-write 0x0FFF0000 HT2 HT2 16 8 0 255 LT2 LT2 0 8 0 255 TR3 TR3 watchdog threshold register 3 0x28 0x20 read-write 0x0FFF0000 HT3 HT3 16 8 0 255 LT3 LT3 0 8 0 255 SQR1 SQR1 regular sequence register 1 0x30 0x20 read-write 0x00000000 4 0x6 1-4 SQ%s %s conversion in regular sequence 6 5 0 18 L L 0 4 0 15 SQR2 SQR2 regular sequence register 2 0x34 0x20 read-write 0x00000000 5 0x6 5-9 SQ%s %s conversion in regular sequence 0 5 SQR3 SQR3 regular sequence register 3 0x38 0x20 read-write 0x00000000 5 0x6 10-14 SQ%s %s conversion in regular sequence 0 5 SQR4 SQR4 regular sequence register 4 0x3C 0x20 read-write 0x00000000 2 0x6 15-16 SQ%s %s conversion in regular sequence 0 5 DR DR regular Data Register 0x40 0x20 read-only 0x00000000 RDATA regularDATA 0 16 0 65535 JSQR JSQR injected sequence register 0x4C 0x20 read-write 0x00000000 4 0x6 1-4 JSQ%s %s conversion in injected sequence 8 5 0 19 JEXTEN JEXTEN 6 2 JEXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 JEXTSEL JEXTSEL 2 4 JEXTSEL TIM1_TRGO Timer 1 TRGO event 0 TIM1_CC4 Timer 1 CC4 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM2_CC1 Timer 2 CC1 event 3 TIM3_CC4 Timer 3 CC4 event 4 EXTI15 EXTI line 15 6 TIM1_TRGO2 Timer 1 TRGO2 event 8 TIM3_CC3 Timer 3 CC3 event 11 TIM3_TRGO Timer 3 TRGO event 12 TIM3_CC1 Timer 3 CC1 event 13 TIM6_TRGO Timer 6 TRGO event 14 TIM15_TRGO Timer 15 TRGO event 15 JL JL 0 2 0 3 4 0x4 1-4 OFR%s OFR%s offset register %s 0x60 0x20 read-write 0x00000000 OFFSET_EN Offset X Enable 31 1 OFFSET_EN Disabled This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0] 0 Enabled This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0] 1 OFFSET_CH Channel selection for the data offset X 26 5 0 31 OFFSET Data offset X for the channel programmed into bits OFFSET_CH 0 12 0 4095 4 0x4 1-4 JDR%s JDR%s injected data register %s 0x80 0x20 read-only 0x00000000 JDATA JDATA1 0 16 0 65535 AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 0x20 read-write 0x00000000 19 0x1 0-18 AWD2CH%s AWD2CH 0 1 AWD2CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 0x20 read-write 0x00000000 19 0x1 0-18 AWD3CH%s AWD3CH 0 1 AWD3CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 0x20 0x00000000 19 0x1 0-18 DIFSEL%s Differential mode for channel %s 0 1 DIFSEL0 SingleEnded Input channel is configured in single-ended mode 0 Differential Input channel is configured in differential mode 1 CALFACT CALFACT Calibration Factors 0xB4 0x20 read-write 0x00000000 CALFACT_D CALFACT_D 16 7 0 127 CALFACT_S CALFACT_S 0 7 0 127 SEC_ADC1 0x52028000 ADC2 Analog-to-Digital Converter ADC 0x42028100 SEC_ADC2 0x52028100 ADC_Common Analog-to-Digital Converter ADC_Common 0x42028300 0x0 0x10 registers ADC1_2 ADC1_2 global interrupt 37 CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 ADRDY_MST ADDRDY_MST 0 1 ADRDY_MST NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 EOSMP_MST EOSMP_MST 1 1 EOSMP_MST NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOC_MST EOC_MST 2 1 EOC_MST NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOS_MST EOS_MST 3 1 EOS_MST NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 OVR_MST OVR_MST 4 1 OVR_MST NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 JEOC_MST JEOC_MST 5 1 JEOC_MST NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOS_MST JEOS_MST 6 1 JEOS_MST NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 AWD1_MST AWD1_MST 7 1 AWD1_MST NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD2_MST AWD2_MST 8 1 AWD3_MST AWD3_MST 9 1 JQOVF_MST JQOVF_MST 10 1 JQOVF_MST NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 ADRDY_SLV ADRDY_SLV 16 1 EOSMP_SLV EOSMP_SLV 17 1 EOC_SLV EOC_SLV 18 1 EOS_SLV EOS_SLV 19 1 OVR_SLV OVR_SLV 20 1 JEOC_SLV JEOC_SLV 21 1 JEOS_SLV JEOS_SLV 22 1 AWD1_SLV AWD1_SLV 23 1 AWD2_SLV AWD2_SLV 24 1 AWD3_SLV AWD3_SLV 25 1 JQOVF_SLV JQOVF_SLV 26 1 CCR CCR ADC common control register 0x8 0x20 read-write 0x00000000 CKMODE ADC clock mode 16 2 CKMODE Asynchronous Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock 0 SyncDiv1 Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck 1 SyncDiv2 Use AHB clock rcc_hclk3 divided by 2 2 SyncDiv4 Use AHB clock rcc_hclk3 divided by 4 3 PRESC ADC prescaler 18 4 PRESC Div1 Input ADC clock not divided 0 Div2 Input ADC clock divided by 2 1 Div4 Input ADC clock divided by 4 2 Div6 Input ADC clock divided by 6 3 Div8 Input ADC clock divided by 8 4 Div10 Input ADC clock divided by 10 5 Div12 Input ADC clock divided by 12 6 Div16 Input ADC clock divided by 16 7 Div32 Input ADC clock divided by 32 8 Div64 Input ADC clock divided by 64 9 Div128 Input ADC clock divided by 128 10 Div256 Input ADC clock divided by 256 11 VREFEN VREFINT enable 22 1 VREFEN Disabled V_REFINT channel disabled 0 Enabled V_REFINT channel enabled 1 VSENSEEN Temperature sensor selection 23 1 VSENSEEN Disabled The selected ADC channel disabled 0 Enabled The selected ADC channel enabled 1 VBATEN VBAT selection 24 1 MDMA MDMA 14 2 MDMA Disabled MDMA mode disabled 0 Interleaved Enable dual interleaved mode to output to the master channel of DFSDM interface both Master and the Slave result (16-bit data width) 1 Bits12_10 MDMA mode enabled for 12 and 10-bit resolution 2 Bits8_6 MDMA mode enabled for 8 and 6-bit resolution 3 DMACFG DMACFG 13 1 DMACFG OneShotMode DMA One Shot mode selected 0 CircularMode DMA Circular mode selected 1 DELAY DELAY 8 4 0 15 DUAL DUAL 0 5 DUAL Independent Independent mode 0 DualRJ Dual, combined regular simultaneous + injected simultaneous mode 1 DualRA Dual, combined regular simultaneous + alternate trigger mode 2 DualIJ Dual, combined interleaved mode + injected simultaneous mode 3 DualJ Dual, injected simultaneous mode only 5 DualR Dual, regular simultaneous mode only 6 DualI Dual, interleaved mode only 7 DualA Dual, alternate trigger mode only 9 CDR CDR Common regular data register for dual mode 0xC 0x20 read-only 0x00000000 RDATA_MST RDATA_MST 0 16 0 65535 RDATA_SLV RDATA_SLV 16 16 0 65535 SEC_ADC_Common 0x52028300 AES Advanced encryption standard hardware accelerator 1 AES 0x420C0000 0x0 0x400 registers AES AES global interrupts 93 CR CR control register 0x0 0x20 read-write 0x00000000 NPBLB Number of padding bytes in last block of payload 20 4 0 15 KEYSIZE Key size selection 18 1 KEYSIZE AES128 128 0 AES256 256 1 CHMOD_2 AES chaining mode Bit2 16 1 CHMOD_2 CHMOD Mode as per CHMOD (ECB, CBC, CTR, GCM) 0 CCM Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB) 1 GCMPH Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected 13 2 GCMPH Init Init phase 0 Header Header phase 1 Payload Payload phase 2 Final Final Phase 3 DMAOUTEN Enable DMA management of data output phase 12 1 DMAOUTEN Disabled Disable DMA Output 0 Enabled Enabled DMA Output 1 DMAINEN Enable DMA management of data input phase 11 1 DMAINEN Disabled Disable DMA Input 0 Enabled Enable DMA Input 1 ERRIE Error interrupt enable 10 1 ERRIE Disabled Disable (mask) error interrupt 0 Enabled Enable error interrupt 1 CCFIE CCF flag interrupt enable 9 1 CCFIE Disabled Disable (mask) CCF interrupt 0 Enabled Enable CCF interrupt 1 ERRC Error clear 8 1 ERRCW write Clear Clear RDERR and WRERR flags 1 CCFC Computation Complete Flag Clear 7 1 CCFCW write Clear Clear computation complete flag 1 CHMOD AES chaining mode selection Bit1 Bit0 5 2 CHMOD ECB Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1 0 CBC Cipher-block chaining (CBC) 1 CTR Counter mode (CTR) 2 GCM Galois counter mode (GCM) and Galois message authentication code (GMAC) 3 MODE AES operating mode 3 2 MODE Mode1 Mode 1: encryption 0 Mode2 Mode 2: key derivation (or key preparation for ECB/CBC decryption) 1 Mode3 Mode 3: decryption 2 Mode4 Mode 4: key derivation then single decryption 3 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 DATATYPE None Word 0 HalfWord Half-word (16-bit) 1 Byte Byte (8-bit) 2 Bit Bit 3 EN AES enable 0 1 EN Disabled Disable AES 0 Enabled Enable AES 1 SR SR status register 0x4 0x20 read-only 0x00000000 BUSY Busy flag 3 1 BUSY Idle Idle 0 Busy Busy 1 WRERR Write error flag 2 1 WRERR NoError Write error not detected 0 Error Write error detected 1 RDERR Read error flag 1 1 RDERR NoError Read error not detected 0 Error Read error detected 1 CCF Computation complete flag 0 1 CCF Complete Computation complete 0 NotComplete Computation not complete 1 DINR DINR data input register 0x8 0x20 read-write 0x00000000 DIN Data Input Register 0 32 0 4294967295 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 DOUT Data output register 0 32 0 4294967295 KEYR0 KEYR0 key register 0 0x10 0x20 write-only 0x00000000 KEY Cryptographic key, bits[31:0] 0 32 0 4294967295 KEYR1 KEYR1 key register 1 0x14 0x20 write-only 0x00000000 KEY Cryptographic key, bits [63:32]) 0 32 0 4294967295 KEYR2 KEYR2 key register 2 0x18 0x20 write-only 0x00000000 KEY Cryptographic key, bits [95:64]) 0 32 0 4294967295 KEYR3 KEYR3 key register 3 0x1C 0x20 write-only 0x00000000 KEY Cryptographic key, bits [127:96]) 0 32 0 4294967295 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 IVI initialization vector register (LSB IVR [31:0]) 0 32 0 4294967295 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [63:32]) 0 32 0 4294967295 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [95:64]) 0 32 0 4294967295 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization Vector Register (MSB IVR [127:96]) 0 32 0 4294967295 KEYR4 KEYR4 key register 4 0x30 0x20 write-only 0x00000000 KEY Cryptographic key, bits [159:128]) 0 32 0 4294967295 KEYR5 KEYR5 key register 5 0x34 0x20 write-only 0x00000000 KEY Cryptographic key, bits [191:160]) 0 32 0 4294967295 KEYR6 KEYR6 key register 6 0x38 0x20 write-only 0x00000000 KEY Cryptographic key, bits [223:192]) 0 32 0 4294967295 KEYR7 KEYR7 key register 7 0x3C 0x20 write-only 0x00000000 KEY Cryptographic key, bits [255:224]) 0 32 0 4294967295 SUSP0R SUSP0R AES suspend register 0 0x40 0x20 read-write 0x00000000 SUSP AES suspend register 0 0 32 0 4294967295 SUSP1R SUSP1R AES suspend register 1 0x44 0x20 read-write 0x00000000 SUSP AES suspend register 1 0 32 0 4294967295 SUSP2R SUSP2R AES suspend register 2 0x48 0x20 read-write 0x00000000 SUSP AES suspend register 2 0 32 0 4294967295 SUSP3R SUSP3R AES suspend register 3 0x4C 0x20 read-write 0x00000000 SUSP AES suspend register 3 0 32 0 4294967295 SUSP4R SUSP4R AES suspend register 4 0x50 0x20 read-write 0x00000000 SUSP AES suspend register 4 0 32 0 4294967295 SUSP5R SUSP5R AES suspend register 5 0x54 0x20 read-write 0x00000000 SUSP AES suspend register 5 0 32 0 4294967295 SUSP6R SUSP6R AES suspend register 6 0x58 0x20 read-write 0x00000000 SUSP AES suspend register 6 0 32 0 4294967295 SUSP7R SUSP7R AES suspend register 7 0x5C 0x20 read-write 0x00000000 SUSP AES suspend register 7 0 32 0 4294967295 SEC_AES 0x520C0000 COMP Comparator COMP 0x40010200 0x0 0x200 registers COMP COMP1 and COMP2 interrupts 72 COMP1_CSR COMP1_CSR Comparator 1 control and status register 0x0 0x20 0x00000000 COMP1_EN Comparator 1 enable bit 0 1 read-write COMP1_PWRMODE Power Mode of the comparator 1 2 2 read-write COMP1_INMSEL Comparator 1 Input Minus connection configuration bit 4 3 read-write COMP1_INPSEL Comparator1 input plus selection bit 7 1 read-write COMP1_POLARITY Comparator 1 polarity selection bit 15 1 read-write COMP1_HYST Comparator 1 hysteresis selection bits 16 2 read-write COMP1_BLANKING Comparator 1 blanking source selection bits 18 3 read-write COMP1_BRGEN Scaler bridge enable 22 1 read-write COMP1_SCALEN Voltage scaler enable bit 23 1 read-write COMP1_VALUE Comparator 1 output status bit 30 1 read-only COMP1_LOCK COMP1_CSR register lock bit 31 1 write-only COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x4 0x20 0x00000000 COMP2_EN Comparator 2 enable bit 0 1 read-write COMP2_PWRMODE Power Mode of the comparator 2 2 2 read-write COMP2_INMSEL Comparator 2 Input Minus connection configuration bit 4 3 read-write COMP2_INPSEL Comparator 2 Input Plus connection configuration bit 7 1 read-write COMP2_WINMODE Windows mode selection bit 9 1 read-write COMP2_POLARITY Comparator 2 polarity selection bit 15 1 read-write COMP2_HYST Comparator 2 hysteresis selection bits 16 2 read-write COMP2_BLANKING Comparator 2 blanking source selection bits 18 3 read-write COMP2_BRGEN Scaler bridge enable 22 1 read-write COMP2_SCALEN Voltage scaler enable bit 23 1 read-write COMP2_VALUE Comparator 2 output status bit 30 1 read-only COMP2_LOCK COMP2_CSR register lock bit 31 1 write-only SEC_COMP 0x50010200 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 32 0 4294967295 CR CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 REV_IN Reverse input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 POLYSIZE Polynomial size 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 RESET RESET bit 0 1 write-only RESETW Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF INIT Programmable initial CRC value 0 32 0 4294967295 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 0 4294967295 SEC_CRC 0x50023000 CRS Clock recovery system CRS 0x40006000 0x0 0x400 registers CRS Clock recovery system global interrupt 74 CR CR control register 0x0 0x20 read-write 0x00004000 TRIM HSI48 oscillator smooth trimming 8 7 0 63 SWSYNC Generate software SYNC event 7 1 SWSYNC Sync A software sync is generated 1 AUTOTRIMEN Automatic trimming enable 6 1 AUTOTRIMEN Disabled Automatic trimming disabled 0 Enabled Automatic trimming enabled 1 CEN Frequency error counter enable 5 1 CEN Disabled Frequency error counter disabled 0 Enabled Frequency error counter enabled 1 SYNCOKIE SYNC event OK interrupt enable 0 1 SYNCOKIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 ESYNCIE Expected SYNC interrupt enable 3 1 ERRIE Synchronization or trimming error interrupt enable 2 1 SYNCWARNIE SYNC warning interrupt enable 1 1 CFGR CFGR configuration register 0x4 0x20 read-write 0x2022BB7F SYNCPOL SYNC polarity selection 31 1 SYNCPOL RisingEdge SYNC active on rising edge 0 FallingEdge SYNC active on falling edge 1 SYNCSRC SYNC signal source selection 28 2 SYNCSRC GPIO_AF GPIO AF (crs_sync_in_1) selected as SYNC signal source 0 LSE LSE (crs_sync_in_2) selected as SYNC signal source 1 USB_SOF USB SOF (crs_sync_in_3) selected as SYNC signal source 2 SYNCDIV SYNC divider 24 3 SYNCDIV Div1 SYNC not divided 0 Div2 SYNC divided by 2 1 Div4 SYNC divided by 4 2 Div8 SYNC divided by 8 3 Div16 SYNC divided by 16 4 Div32 SYNC divided by 32 5 Div64 SYNC divided by 64 6 Div128 SYNC divided by 128 7 FELIM Frequency error limit 16 8 0 255 RELOAD Counter reload value 0 16 0 65535 ISR ISR interrupt and status register 0x8 0x20 read-only 0x00000000 FECAP Frequency error capture 16 16 0 65535 FEDIR Frequency error direction 15 1 FEDIR UpCounting Error in up-counting direction 0 DownCounting Error in down-counting direction 1 SYNCOKF SYNC event OK flag 0 1 SYNCOKF NotSignaled Signal not set 0 Signaled Signal set 1 TRIMOVF Trimming overflow or underflow 10 1 SYNCMISS SYNC missed 9 1 SYNCERR SYNC error 8 1 ESYNCF Expected SYNC flag 3 1 ERRF Error flag 2 1 SYNCWARNF SYNC warning flag 1 1 ICR ICR interrupt flag clear register 0xC 0x20 read-write 0x00000000 SYNCOKC SYNC event OK clear flag 0 1 SYNCOKC Clear Clear flag 1 ESYNCC Expected SYNC clear flag 3 1 ERRC Error clear flag 2 1 SYNCWARNC SYNC warning clear flag 1 1 SEC_CRS 0x50006000 DAC DAC DAC 0x40007400 0x0 0x400 registers DAC DAC global interrupt 38 CR CR DAC control register 0x0 0x20 read-write 0x00000000 2 0x10 1-2 EN%s DAC channel%s enable 0 1 EN1 Disabled DAC Channel X disabled 0 Enabled DAC Channel X enabled 1 2 0x10 1-2 TEN%s DAC channel%s trigger enable 1 1 TEN1 Disabled DAC Channel X trigger disabled 0 Enabled DAC Channel X trigger enabled 1 TSEL1 TSEL10 2 4 TSEL1 Swtrig Software trigger 0 Tim1Trgo Timer 1 TRGO event 1 Tim2Trgo Timer 2 TRGO event 2 Tim4Trgo Timer 4 TRGO event 3 Tim5Trgo Timer 5 TRGO event 4 Tim6Trgo Timer 6 TRGO event 5 Tim7Trgo Timer 7 TRGO event 6 Tim8Trgo Timer 8 TRGO event 7 Tim15Trgo Timer 15 TRGO event 8 Lptim1Out LPTIM1 OUT event 11 Lptim2Out LPTIM2 OUT event 12 Exti9 EXTI line 9 13 2 0x10 1-2 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true 2 0x10 1-2 MAMP%s DAC channel%s mask/amplitude selector 8 4 MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 2 0x10 1-2 DMAEN%s DAC channel%s DMA enable 12 1 DMAEN1 Disabled DAC Channel X DMA mode disabled 0 Enabled DAC Channel X DMA mode enabled 1 2 0x10 1-2 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 2 0x10 1-2 CEN%s DAC channel%s calibration enable 14 1 CEN1 Normal DAC Channel X Normal operating mode 0 Calibration DAC Channel X calibration mode 1 HFSEL HFSEL 15 1 HFSEL Disabled High frequency interface mode disabled 0 Enabled High frequency interface mode enabled 1 TSEL2 TSEL20 18 4 SWTRGR SWTRGR DAC software trigger register 0x4 0x20 write-only 0x00000000 2 0x1 1-2 SWTRIG%s DAC channel%s software trigger 0 1 SWTRIG1 NoTrigger No trigger 0 Trigger Trigger 1 2 0xC 1-2 DHR12R%s DHR12R%s channel%s 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 0 4095 2 0xC 1-2 DHR12L%s DHR12L%s channel%s 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 0 4095 2 0xC 1-2 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACCDHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 0 4095 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 0 4095 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 2 0x8 1-2 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 0 255 2 0x4 1-2 DOR%s DOR%s channel%s data output register 0x2C 0x20 read-only 0x00000000 DACCDOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 0 4095 SR SR DAC status register 0x34 0x20 0x00000000 2 0x10 1-2 DMAUDR%s DAC channel%s DMA underrun flag 13 1 read-write DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 2 0x10 1-2 CAL_FLAG%s DAC channel%s calibration offset status 14 1 read-only CAL_FLAG1 Lower Calibration trimming value is lower than the offset correction value 0 Equal_Higher Calibration trimming value is equal or greater than the offset correction value 1 2 0x10 1-2 BWST%s DAC channel%s busy writing sample time flag 15 1 read-only BWST1 Idle There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written 0 Busy There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written 1 CCR CCR DAC calibration control register 0x38 0x20 read-write 0x00000000 2 0x10 1-2 OTRIM%s DAC channel%s offset trimming value 0 5 0 31 MCR MCR DAC mode control register 0x3C 0x20 read-write 0x00000000 2 0x10 1-2 MODE%s DAC channel%s mode 0 3 MODE1 NormalPinBuffer Normal mode - DAC channelx is connected to external pin with Buffer enabled 0 NormalPinChipBuffer Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 1 NormalPinNoBuffer Normal mode - DAC channelx is connected to external pin with Buffer disabled 2 NormalChipNoBuffer Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled 3 SHPinBuffer S&H mode - DAC channelx is connected to external pin with Buffer enabled 4 SHPinChipBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 5 SHPinNoBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled 6 SHChipNoBuffer S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled 7 2 0x4 1-2 SHSR%s SHSR%s DAC channel%s sample and hold sample time register 0x40 0x20 read-write 0x00000000 TSAMPLE DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 0 1023 SHHR SHHR DAC Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 2 0x10 1-2 THOLD%s DAC channel%s hold time (only valid in Sample and hold mode) 0 10 0 1023 SHRR SHRR DAC Sample and Hold refresh time register 0x4C 0x20 read-write 0x00010001 2 0x10 1-2 TREFRESH%s DAC channel%s refresh time (only valid in Sample and hold mode) 0 8 0 255 SEC_DAC 0x50007400 DBGMCU MCU debug component DBGMCU 0xE0044000 0x0 0x400 registers IDCODE IDCODE DBGMCU_IDCODE 0x0 0x20 read-only 0x00000000 DEV_ID Device identifier 0 12 REV_ID Revision identifie 16 16 CR CR Debug MCU configuration register 0x4 0x20 read-write 0x00000000 DBG_STOP Debug Stop mode 1 1 DBG_STANDBY Debug Standby mode 2 1 TRACE_IOEN Trace pin assignment control 4 1 TRACE_MODE Trace pin assignment control 6 2 TRACE_EN trace port and clock enable 5 1 APB1LFZR APB1LFZR Debug MCU APB1 freeze register1 0x8 0x20 read-write 0x00000000 DBG_TIM2_STOP TIM2 counter stopped when core is halted 0 1 DBG_TIM6_STOP TIM6 counter stopped when core is halted 4 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_RTC_STOP RTC counter stopped when core is halted 10 1 DBG_WWDG_STOP Window watchdog counter stopped when core is halted 11 1 DBG_IWDG_STOP Independent watchdog counter stopped when core is halted 12 1 DBG_I2C1_STOP I2C1 SMBUS timeout counter stopped when core is halted 21 1 DBG_I2C2_STOP I2C2 SMBUS timeout counter stopped when core is halted 22 1 DBG_I2C3_STOP I2C3 SMBUS timeout counter stopped when core is halted 23 1 DBG_LPTIM1_STOP LPTIM1 counter stopped when core is halted 31 1 DBG_TIM3_STOP TIM3 stop in debug 1 1 DBG_TIM4_STOP TIM4 stop in debug 2 1 DBG_TIM5_STOP TIM5 stop in debug 3 1 APB1HFZR APB1HFZR Debug MCU APB1 freeze register 2 0xC 0x20 read-write 0x00000000 DBG_LPTIM2_STOP LPTIM2 counter stopped when core is halted 5 1 DBG_I2C4_STOP I2C4 stop in debug 1 1 DBG_LPTIM3_STOP LPTIM3 stop in debug 6 1 APB2FZR APB2FZR Debug MCU APB2 freeze register 0x10 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM8_STOP TIM8 stop in debug 13 1 DBG_TIM17_STOP DBG_TIM17_STOP 18 1 DCB Debug Control Block DCB 0xE000EE08 0x0 0x5 registers DSCSR DSCSR Debug Security Control and Status Register 0x0 0x20 read-write 0x00000000 CDS Current domain Secure 16 1 DMA1 Direct memory access controller DMA 0x40020000 0x0 0x400 registers DMA1_CH1 DMA1 Channel1 global interrupt 29 DMA1_CH2 DMA1 Channel2 global interrupt 30 DMA1_CH3 DMA1 Channel3 interrupt 31 DMA1_CH4 DMA1 Channel4 interrupt 32 DMA1_CH5 DMA1 Channel5 interrupt 33 DMA1_CH6 DMA1 Channel6 interrupt 34 DMA1_CH7 DMA1 Channel 7 interrupt 35 DMA1_Channel8 DMA1_Channel8 36 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 8 0x4 1-8 TEIF%s Channel %s Transfer Error flag 3 1 TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 8 0x4 1-8 HTIF%s Channel %s Half Transfer Complete flag 2 1 HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 8 0x4 1-8 TCIF%s Channel %s Transfer Complete flag 1 1 TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 8 0x4 1-8 GIF%s Channel %s Global interrupt flag 0 1 GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 IFCR IFCR interrupt flag clear register 0x4 0x20 write-only 0x00000000 8 0x4 1-8 CTEIF%s Channel %s Transfer Error clear 3 1 CTEIF1 Clear Clears the TEIF flag in the ISR register 1 8 0x4 1-8 CHTIF%s Channel %s Half Transfer clear 2 1 CHTIF1 Clear Clears the HTIF flag in the ISR register 1 8 0x4 1-8 CTCIF%s Channel %s Transfer Complete clear 1 1 CTCIF1 Clear Clears the TCIF flag in the ISR register 1 8 0x4 1-8 CGIF%s Channel %s Global interrupt clear 0 1 CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 8 0x14 1-8 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR?, and CM1AR? registers 0x8 CR CCR1 channel x configuration register 0x0 0x20 read-write 0x00000000 PRIV privileged mode 20 1 DSEC security of the DMA transfer to the destination 19 1 SSEC security of the DMA transfer from the source 18 1 SECM secure mode 17 1 CT current target memory of DMA transfer in double-buffer mode 16 1 DBM double-buffer mode 15 1 MEM2MEM Memory to memory mode 14 1 MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 PL Channel priority level 12 2 PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 PSIZE Peripheral size 8 2 PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC Memory increment mode 7 1 CIRC Circular mode 5 1 CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 DIR Data transfer direction 4 1 DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 TEIE Transfer error interrupt enable 3 1 TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 HTIE Half transfer interrupt enable 2 1 HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TCIE Transfer complete interrupt enable 1 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 EN Channel enable 0 1 EN Disabled Channel disabled 0 Enabled Channel enabled 1 NDTR CNDTR1 channel x number of data register 0x4 0x20 read-write 0x00000000 NDT Number of data to transfer 0 18 0 65535 PAR CPAR1 channel x peripheral address register 0x8 0x20 read-write 0x00000000 PA Peripheral address 0 32 M0AR CM0AR1 channel x memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 M1AR CM1AR1 channel x memory address register 0x10 0x20 read-write 0x00000000 MA peripheral address 0 32 SEC_DMA1 0x50020000 DMA2 0x40020400 DMA2_CH1 DMA2_CH1 80 DMA2_CH2 DMA2_CH2 81 DMA2_CH3 DMA2_CH3 82 DMA2_CH4 DMA2_CH4 83 DMA2_CH5 DMA2_CH5 84 DMA2_CH6 DMA2_CH6 85 DMA2_CH7 DMA2_CH7 86 DMA2_CH8 DMA2_CH8 87 SEC_DMA2 0x50020400 DFSDM1 Digital filter for sigma delta modulators DFSDM 0x40016000 0x0 0x800 registers DFSDM1_FLT0 DFSDM1_FLT0 global interrupt 102 DFSDM1_FLT1 DFSDM1_FLT1 global interrupt 103 DFSDM1_FLT2 DFSDM1_FLT2 global interrupt 104 DFSDM1_FLT3 DFSDM1_FLT3 global interrupt 105 8 0x20 0-7 CH%s DFSDM Channel cluster: contains CH?CFGR1, CH?CFGR2, CH?AWSCDR, CH?WDATR and CH?DATINR registers 0x0 CFGR1 CH0CFGR1 channel configuration y register 0x0 0x20 read-write 0x00000000 DFSDMEN DFSDMEN 31 1 DFSDMEN Disabled DFSDM interface disabled 0 Enabled DFSDM interface enabled 1 CKOUTSRC CKOUTSRC 30 1 CKOUTSRC SYSCLK Source for output clock is from system clock 0 AUDCLK Source for output clock is from audio clock 1 CKOUTDIV CKOUTDIV 16 8 0 255 DATPACK DATPACK 14 2 DATPACK Standard Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y 0 Interleaved : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: âfirst sample in INDAT0[15:0] (assigned to channel y) âsecond sample INDAT1[15:0] (assigned to channel y) 1 Dual Dual: input data in DFSDM_CHyDATINR register are stored as two samples: âfirst sample INDAT0[15:0] (assigned to channel y) âsecond sample INDAT1[15:0] (assigned to channel y+1) 2 DATMPX DATMPX 12 2 DATMPX External Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected 0 ADC Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register 1 Internal Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting 2 CHINSEL CHINSEL 8 1 CHINSEL SameChannel Channel inputs are taken from pins of the same channel y 0 FollowingChannel Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8) 1 CHEN CHEN 7 1 CHEN Disabled Channel y disabled 0 Enabled Channel y enabled 1 CKABEN CKABEN 6 1 CKABEN Disabled Clock absence detector disabled on channel y 0 Enabled Clock absence detector enabled on channel y 1 SCDEN SCDEN 5 1 SCDEN Disabled Input channel y will not be guarded by the short-circuit detector 0 Enabled Input channel y will be continuously guarded by the short-circuit detector 1 SPICKSEL SPICKSEL 2 2 SPICKSEL CKIN Clock coming from external CKINy input - sampling point according SITP[1:0] 0 CKOUT Clock coming from internal CKOUT output - sampling point according SITP[1:0] 1 CKOUTSecondFalling Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Î£â modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge) 2 CKOUTSecondRising Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Î£â modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge) 3 SITP SITP 0 2 SITP SPIRisingEdge SPI with rising edge to strobe data 0 SPIFallingEdge SPI with falling edge to strobe data 1 Manchester Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 2 ManchesterInverted Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 3 CFGR2 CH0CFGR2 channel configuration y register 0x4 0x20 read-write 0x00000000 OFFSET OFFSET 8 24 0 16777215 DTRBS DTRBS 3 5 0 31 AWSCDR CH0AWSCDR analog watchdog and short-circuit detector register 0x8 0x20 read-write 0x00000000 AWFORD AWFORD 22 2 AWFORD FastSinc FastSinc filter type 0 Sinc1 Sinc1 filter type 1 Sinc2 Sinc2 filter type 2 Sinc3 Sinc3 filter type 3 AWFOSR AWFOSR 16 5 0 31 BKSCD BKSCD 12 4 0 15 SCDT SCDT 0 8 0 255 WDATR CH0WDATR channel watchdog filter data register 0xC 0x20 read-write 0x00000000 WDATA WDATA 0 16 0 65535 DATINR CH0DATINR channel data input register 0x10 0x20 read-write 0x00000000 INDAT1 INDAT1 16 16 0 65535 INDAT0 INDAT0 0 16 0 65535 DLYR CH0DLYR DFSDM channel y delay register 0x14 0x20 read-write 0x00000000 PLSSKP Pulses to skip for input data skipping function 0 6 0 63 4 0x80 0-3 FLT%s Cluster FLT%s, containing FLT?CR1, FLT?CR2, FLT?ISR, FLT?ICR, FLT?JCHGR, FLT?FCR, FLT?JDATAR, FLT?RDATAR, FLT?AWHTR, FLT?AWLTR, FLT?AWSR, FLT?AWCFR, FLT?EXMAX, FLT?EXMIN, FLT?CNVTIMR 0x100 CR1 FLT0CR1 control register 1 0x0 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 AWFSEL Output Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 0 Transceiver Analog watchdog on channel transceivers value (after watchdog filter) 1 FAST Fast conversion mode selection for regular conversions 29 1 FAST Disabled Fast conversion mode disabled 0 Enabled Fast conversion mode enabled 1 RCH Regular channel selection 24 3 RCH Channel0 Channel 0 is selected as regular channel 0 Channel1 Channel 1 is selected as regular channel 1 Channel2 Channel 2 is selected as regular channel 2 Channel3 Channel 3 is selected as regular channel 3 Channel4 Channel 4 is selected as regular channel 4 Channel5 Channel 5 is selected as regular channel 5 Channel6 Channel 6 is selected as regular channel 6 Channel7 Channel 7 is selected as regular channel 7 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RDMAEN Disabled The DMA channel is not enabled to read regular data 0 Enabled The DMA channel is enabled to read regular data 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RSYNC NoLaunch Do not launch a regular conversion synchronously with DFSDM_FLT0 0 Launch Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 1 RCONT Continuous mode selection for regular conversions 18 1 RCONT Once The regular channel is converted just once for each conversion request 0 Continuous The regular channel is converted repeatedly after each conversion request 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSWSTARTW write Start Writing â1â makes a request to start a conversion on the regular channel and causes RCIP to become â1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing â1â has no effect if RSYNC=1 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTEN Disabled Trigger detection is disabled 0 RisingEdge Each rising edge on the selected trigger makes a request to launch an injected conversion 1 FallingEdge Each falling edge on the selected trigger makes a request to launch an injected conversion 2 BothEdges Both rising edges and falling edges on the selected trigger make requests to launch injected conversions 3 JEXTSEL Trigger signal selection for launching injected conversions 8 5 0 31 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JDMAEN Disabled The DMA channel is not enabled to read injected data 0 Enabled The DMA channel is enabled to read injected data 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSCAN Single One channel conversion is performed from the injected channel group and next the selected channel from this group is selected 0 Series The series of conversions for the injected group channels is executed, starting over with the lowest selected channel 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSYNC Disabled Do not launch an injected conversion synchronously with DFSDM_FLT0 0 Enabled Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSWSTARTW write Start Writing â1â makes a request to convert the channels in the injected conversion group, causing JCIP to become â1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing â1â has no effect if JSYNC=1 1 DFEN DFSDM enable 0 1 DFEN Disabled DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped 0 Enabled DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting 1 CR2 FLT0CR2 control register 2 0x4 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 AWDCH Disabled Analog watchdog is disabled on channel y 0 Enabled Analog watchdog is enabled on channel y 1 EXCH Extremes detector channel selection 8 8 EXCH Disabled Extremes detector does not accept data from channel y 0 Enabled Extremes detector accepts data from channel y 1 CKABIE Clock absence interrupt enable 6 1 CKABIE Disabled Detection of channel input clock absence interrupt is disabled 0 Enabled Detection of channel input clock absence interrupt is enabled 1 SCDIE Short-circuit detector interrupt enable 5 1 SCDIE Disabled Short-circuit detector interrupt is disabled 0 Enabled Short-circuit detector interrupt is enabled 1 AWDIE Analog watchdog interrupt enable 4 1 AWDIE Disabled Analog watchdog interrupt is disabled 0 Enabled Analog watchdog interrupt is enabled 1 ROVRIE Regular data overrun interrupt enable 3 1 ROVRIE Disabled Regular data overrun interrupt is disabled 0 Enabled Regular data overrun interrupt is enabled 1 JOVRIE Injected data overrun interrupt enable 2 1 JOVRIE Disabled Injected data overrun interrupt is disabled 0 Enabled Injected data overrun interrupt is enabled 1 REOCIE Regular end of conversion interrupt enable 1 1 REOCIE Disabled Regular end of conversion interrupt is disabled 0 Enabled Regular end of conversion interrupt is enabled 1 JEOCIE Injected end of conversion interrupt enable 0 1 JEOCIE Disabled Injected end of conversion interrupt is disabled 0 Enabled Injected end of conversion interrupt is enabled 1 ISR FLT0ISR interrupt and status register 0x8 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 SCDF Clear No short-circuit detector event occurred on channel y 0 Set The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers 1 CKABF Clock absence flag 16 8 CKABF Clear Clock signal on channel y is present. 0 Set Clock signal on channel y is not present 1 RCIP Regular conversion in progress status 14 1 RCIP NotInProgress No request to convert the regular channel has been issued 0 InProgress The conversion of the regular channel is in progress or a request for a regular conversion is pending 1 JCIP Injected conversion in progress status 13 1 JCIP NotInProgress No request to convert the injected channel group (neither by software nor by trigger) has been issued 0 InProgress The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to â1â being written to JSWSTART or to a trigger detection 1 AWDF Analog watchdog 4 1 AWDF Clear No Analog watchdog event occurred 0 Set The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers 1 ROVRF Regular conversion overrun flag 3 1 ROVRF Clear No regular conversion overrun has occurred 0 Set A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already â1â. RDATAR is not affected by overruns 1 JOVRF Injected conversion overrun flag 2 1 JOVRF Clear No injected conversion overrun has occurred 0 Set An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already â1â. JDATAR is not affected by overruns 1 REOCF End of regular conversion flag 1 1 REOCF Clear No regular conversion has completed 0 Set A regular conversion has completed and its data may be read 1 JEOCF End of injected conversion flag 0 1 JEOCF Clear No injected conversion has completed 0 Set An injected conversion has completed and its data may be read 1 ICR FLT0ICR interrupt flag clear register 0xC 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 0 255 CLRCKABF Clear the clock absence flag 16 8 0 255 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRROVRFW write Clear Writing â1â clears the ROVRF bit in the DFSDM_FLTxISR register 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRJOVRFW write Clear Writing â1â clears the JOVRF bit in the DFSDM_FLTxISR register 1 JCHGR FLT0JCHGR injected channel group selection register 0x10 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 0 255 FCR FLT0FCR filter control register 0x14 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FORD FastSinc FastSinc filter type 0 Sinc1 Sinc1 filter type 1 Sinc2 Sinc2 filter type 2 Sinc3 Sinc3 filter type 3 Sinc4 Sinc4 filter type 4 Sinc5 Sinc5 filter type 5 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 0 1023 IOSR Integrator oversampling ratio (averaging length) 0 8 0 255 JDATAR FLT0JDATAR data register for injected group 0x18 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 0 16777215 JDATACH Injected channel most recently converted 0 3 0 7 RDATAR FLT0RDATAR data register for the regular channel 0x1C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 0 16777215 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 0 7 AWHTR FLT0AWHTR analog watchdog high threshold register 0x20 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 0 16777215 4 0x1 0-3 BKAWH%s Break signal assignment to analog watchdog high threshold event 0 1 BKAWH0 NotAssigned Break i signal is not assigned to an analog watchdog high threshold event 0 Assigned Break i signal is assigned to an analog watchdog high threshold event 1 AWLTR FLT0AWLTR analog watchdog low threshold register 0x24 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 0 16777215 4 0x1 0-3 BKAWL%s Break signal assignment to analog watchdog low threshold event 0 1 BKAWL0 NotAssigned Break i signal is not assigned to an analog watchdog low threshold event 0 Assigned Break i signal is assigned to an analog watchdog low threshold event 1 AWSR FLT0AWSR analog watchdog status register 0x28 0x20 read-only 0x00000000 8 0x1 0-7 AWHTF%s Analog watchdog high threshold flag 8 1 AWHTF0 NoError No high threshold error 0 Error A high threshold error on channel y 1 8 0x1 0-7 AWLTF%s Analog watchdog low threshold flag 0 1 AWLTF0 NoError No low threshold error 0 Error A low threshold error on channel y 1 AWCFR FLT0AWCFR analog watchdog clear flag register 0x2C 0x20 read-write 0x00000000 8 0x1 0-7 CLRAWHTF%s Clear the analog watchdog high threshold flag 8 1 oneToClear CLRAWHTF0W write Clear Clear the corresponding AWHTF[y] bit 1 8 0x1 0-7 CLRAWLTF%s Clear the analog watchdog low threshold flag 0 1 oneToClear CLRAWLTF0W write Clear Clear the corresponding AWLTF[y] bit 1 EXMAX FLT0EXMAX Extremes detector maximum register 0x30 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 0 16777215 EXMAXCH Extremes detector maximum data channel 0 3 0 7 EXMIN FLT0EXMIN Extremes detector minimum register 0x34 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 0 16777215 EXMINCH Extremes detector minimum data channel 0 3 0 7 CNVTIMR FLT0CNVTIMR conversion timer register 0x38 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 0 268435455 SEC_DFSDM1 0x50016000 DMAMUX1 Direct memory access Multiplexer DMAMUX 0x40020800 0x0 0x400 registers DMAMUX1_OVR DMAMUX overrun interrupt 27 DMAMUX1_OVR_S DMAMUX1 secure overRun interrupt 28 16 0x4 0-15 CCR%s C%sCR DMA Multiplexer Channel %s Control register 0x0 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 0 31 SPOL Sync polarity 17 2 SPOL NoEdge No event, i.e. no synchronization nor detection 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 SE Synchronization enable 16 1 SE Disabled Synchronization disabled 0 Enabled Synchronization enabled 1 EGE Event Generation Enable 9 1 EGE Disabled Event generation disabled 0 Enabled Event generation enabled 1 SOIE Synchronization Overrun Interrupt Enable 8 1 SOIE Disabled Synchronization overrun interrupt disabled 0 Enabled Synchronization overrun interrupt enabled 1 DMAREQ_ID DMA Request ID 0 7 CSR CSR DMA Multiplexer Channel Status register 0x80 0x20 read-write 0x00000000 16 0x1 0-15 SOF%s Synchronization Overrun Flag %s 0 1 SOF0 NoSyncEvent No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 0 SyncEvent Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 1 CCFR CCFR DMA Channel Clear Flag Register 0x84 0x20 read-write 0x00000000 16 0x1 0-15 CSOF%s Synchronization Clear Overrun Flag %s 0 1 oneToClear CSOF0W write Clear Clear synchronization flag 1 4 0x4 0-3 RGCR%s RG%sCR DMA Request Generator %s Control Register 0x100 0x20 read-write 0x00000000 GNBREQ Number of Request 19 5 0 31 GPOL Generation Polarity 17 2 GPOL NoEdge No event, i.e. no detection nor generation 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 GE Generation Enable 16 1 GE Disabled DMA request generation disabled 0 Enabled DMA request enabled 1 OIE Overrun Interrupt Enable 8 1 OIE Disabled Trigger overrun interrupt disabled 0 Enabled Trigger overrun interrupt enabled 1 SIG_ID Signal ID 0 5 RGSR RGSR DMA Request Generator Status Register 0x140 0x20 read-only 0x00000000 4 0x1 0-3 OF%s Generator Overrun Flag %s 0 1 OF0 NoTrigger No new trigger event occured on DMA request generator channel x, before the request counter underrun 0 Trigger New trigger event occured on DMA request generator channel x, before the request counter underrun 1 RGCFR RGCFR DMA Request Generator Clear Flag Register 0x144 0x20 read-write 0x00000000 4 0x1 0-3 COF%s Generator Clear Overrun Flag %s 0 1 oneToClear COF0W write Clear Clear overrun flag 1 SEC_DMAMUX1 0x50020800 EXTI External interrupt/event controller EXTI 0x4002F400 0x0 0x400 registers PVD_PVM PVD/PVM1/PVM2/PVM3/PVM4 through EXTI 1 TAMP TAMPTamper global interrupt (EXTI line 19) 4 TAMP_S Tamper secure global interrupt (EXTI line 20) 5 EXTI0 EXTI line0 interrupt 11 EXTI1 EXTI line1 interrupt 12 EXTI2 EXTI line2 interrupt 13 EXTI3 EXTI line3 interrupt 14 EXTI4 EXTI line4 interrupt 15 EXTI5 EXTI line5 interrupt 16 EXTI6 EXTI line6 interrupt 17 EXTI7 EXTI line7 interrupt 18 EXTI8 EXTI line8 interrupt 19 EXTI9 EXTI line9 interrupt 20 EXTI10 EXTI line10 interrupt 21 EXTI11 EXTI line11 interrupt 22 EXTI12 EXTI line12 interrupt 23 EXTI13 EXTI line13 interrupt 24 EXTI14 EXTI line14 interrupt 25 EXTI15 EXTI line15 interrupt 26 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 read-write 0x00000000 RT0 Rising trigger event configuration bit of configurable event input x 0 1 RT1 Rising trigger event configuration bit of configurable event input x 1 1 RT2 Rising trigger event configuration bit of configurable event input x 2 1 RT3 Rising trigger event configuration bit of configurable event input x 3 1 RT4 Rising trigger event configuration bit of configurable event input x 4 1 RT5 Rising trigger event configuration bit of configurable event input x 5 1 RT6 Rising trigger event configuration bit of configurable event input x 6 1 RT7 Rising trigger event configuration bit of configurable event input x 7 1 RT8 Rising trigger event configuration bit of configurable event input x 8 1 RT9 Rising trigger event configuration bit of configurable event input x 9 1 RT10 Rising trigger event configuration bit of configurable event input x 10 1 RT11 Rising trigger event configuration bit of configurable event input x 11 1 RT12 Rising trigger event configuration bit of configurable event input x 12 1 RT13 Rising trigger event configuration bit of configurable event input x 13 1 RT14 Rising trigger event configuration bit of configurable event input x 14 1 RT15 Rising trigger event configuration bit of configurable event input x 15 1 RT16 Rising trigger event configuration bit of configurable event input x 16 1 RT21 Rising trigger event configuration bit of configurable event input x 21 1 RT22 Rising trigger event configuration bit of configurable event input x 22 1 FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 read-write 0x00000000 FT0 Falling trigger event configuration bit of configurable event input x 0 1 FT1 Falling trigger event configuration bit of configurable event input x 1 1 FT2 Falling trigger event configuration bit of configurable event input x 2 1 FT3 Falling trigger event configuration bit of configurable event input x 3 1 FT4 Falling trigger event configuration bit of configurable event input x 4 1 FT5 Falling trigger event configuration bit of configurable event input x 5 1 FT6 Falling trigger event configuration bit of configurable event input x 6 1 FT7 Falling trigger event configuration bit of configurable event input x 7 1 FT8 Falling trigger event configuration bit of configurable event input x 8 1 FT9 Falling trigger event configuration bit of configurable event input x 9 1 FT10 Falling trigger event configuration bit of configurable event input x 10 1 FT11 Falling trigger event configuration bit of configurable event input x 11 1 FT12 Falling trigger event configuration bit of configurable event input x 12 1 FT13 Falling trigger event configuration bit of configurable event input x 13 1 FT14 Falling trigger event configuration bit of configurable event input x 14 1 FT15 Falling trigger event configuration bit of configurable event input x 15 1 FT16 Falling trigger event configuration bit of configurable event input x 16 1 FT21 Falling trigger event configuration bit of configurable event input x 21 1 FT22 Falling trigger event configuration bit of configurable event input x 22 1 SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 read-write 0x00000000 SWI0 Software interrupt on event x 0 1 SWI1 Software interrupt on event x 1 1 SWI2 Software interrupt on event x 2 1 SWI3 Software interrupt on event x 3 1 SWI4 Software interrupt on event x 4 1 SWI5 Software interrupt on event x 5 1 SWI6 Software interrupt on event x 6 1 SWI7 Software interrupt on event x 7 1 SWI8 Software interrupt on event x 8 1 SWI9 Software interrupt on event x 9 1 SWI10 Software interrupt on event x 10 1 SWI11 Software interrupt on event x 11 1 SWI12 Software interrupt on event x 12 1 SWI13 Software interrupt on event x 13 1 SWI14 Software interrupt on event x 14 1 SWI15 Software interrupt on event x 15 1 SWI16 Software interrupt on event x 16 1 SWI21 Software interrupt on event x 21 1 SWI22 Software interrupt on event x 22 1 RPR1 RPR1 EXTI rising edge pending register 0xC 0x20 read-write 0x00000000 RPIF0 configurable event inputs x rising edge pending bit 0 1 RPIF1 configurable event inputs x rising edge pending bit 1 1 RPIF2 configurable event inputs x rising edge pending bit 2 1 RPIF3 configurable event inputs x rising edge pending bit 3 1 RPIF4 configurable event inputs x rising edge pending bit 4 1 RPIF5 configurable event inputs x rising edge pending bit 5 1 RPIF6 configurable event inputs x rising edge pending bit 6 1 RPIF7 configurable event inputs x rising edge pending bit 7 1 RPIF8 configurable event inputs x rising edge pending bit 8 1 RPIF9 configurable event inputs x rising edge pending bit 9 1 RPIF10 configurable event inputs x rising edge pending bit 10 1 RPIF11 configurable event inputs x rising edge pending bit 11 1 RPIF12 configurable event inputs x rising edge pending bit 12 1 RPIF13 configurable event inputs x rising edge pending bit 13 1 RPIF14 configurable event inputs x rising edge pending bit 14 1 RPIF15 configurable event inputs x rising edge pending bit 15 1 RPIF16 configurable event inputs x rising edge pending bit 16 1 RPIF21 configurable event inputs x rising edge pending bit 21 1 RPIF22 configurable event inputs x rising edge pending bit 22 1 FPR1 FPR1 EXTI falling edge pending register 0x10 0x20 read-write 0x00000000 FPIF0 configurable event inputs x falling edge pending bit. 0 1 FPIF1 configurable event inputs x falling edge pending bit. 1 1 FPIF2 configurable event inputs x falling edge pending bit. 2 1 FPIF3 configurable event inputs x falling edge pending bit. 3 1 FPIF4 configurable event inputs x falling edge pending bit. 4 1 FPIF5 configurable event inputs x falling edge pending bit. 5 1 FPIF6 configurable event inputs x falling edge pending bit. 6 1 FPIF7 configurable event inputs x falling edge pending bit. 7 1 FPIF8 configurable event inputs x falling edge pending bit. 8 1 FPIF9 configurable event inputs x falling edge pending bit. 9 1 FPIF10 configurable event inputs x falling edge pending bit. 10 1 FPIF11 configurable event inputs x falling edge pending bit. 11 1 FPIF12 configurable event inputs x falling edge pending bit. 12 1 FPIF13 configurable event inputs x falling edge pending bit. 13 1 FPIF14 configurable event inputs x falling edge pending bit. 14 1 FPIF15 configurable event inputs x falling edge pending bit. 15 1 FPIF16 configurable event inputs x falling edge pending bit. 16 1 FPIF21 configurable event inputs x falling edge pending bit. 21 1 FPIF22 configurable event inputs x falling edge pending bit. 22 1 SECCFGR1 SECCFGR1 EXTI security configuration register 0x14 0x20 read-write 0x00000000 SEC0 Security enable on event input x 0 1 SEC1 Security enable on event input x 1 1 SEC2 Security enable on event input x 2 1 SEC3 Security enable on event input x 3 1 SEC4 Security enable on event input x 4 1 SEC5 Security enable on event input x 5 1 SEC6 Security enable on event input x 6 1 SEC7 Security enable on event input x 7 1 SEC8 Security enable on event input x 8 1 SEC9 Security enable on event input x 9 1 SEC10 Security enable on event input x 10 1 SEC11 Security enable on event input x 11 1 SEC12 Security enable on event input x 12 1 SEC13 Security enable on event input x 13 1 SEC14 Security enable on event input x 14 1 SEC15 Security enable on event input x 15 1 SEC16 Security enable on event input x 16 1 SEC17 Security enable on event input x 17 1 SEC18 Security enable on event input x 18 1 SEC19 Security enable on event input x 19 1 SEC20 Security enable on event input x 20 1 SEC21 Security enable on event input x 21 1 SEC22 Security enable on event input x 22 1 SEC23 Security enable on event input x 23 1 SEC24 Security enable on event input x 24 1 SEC25 Security enable on event input x 25 1 SEC26 Security enable on event input x 26 1 SEC27 Security enable on event input x 27 1 SEC28 Security enable on event input x 28 1 SEC29 Security enable on event input x 29 1 SEC30 Security enable on event input x 30 1 SEC31 Security enable on event input x 31 1 PRIVCFGR1 PRIVCFGR1 EXTI privilege configuration register 0x18 0x20 read-write 0x00000000 PRIV0 Security enable on event input x 0 1 PRIV1 Security enable on event input x 1 1 PRIV2 Security enable on event input x 2 1 PRIV3 Security enable on event input x 3 1 PRIV4 Security enable on event input x 4 1 PRIV5 Security enable on event input x 5 1 PRIV6 Security enable on event input x 6 1 PRIV7 Security enable on event input x 7 1 PRIV8 Security enable on event input x 8 1 PRIV9 Security enable on event input x 9 1 PRIV10 Security enable on event input x 10 1 PRIV11 Security enable on event input x 11 1 PRIV12 Security enable on event input x 12 1 PRIV13 Security enable on event input x 13 1 PRIV14 Security enable on event input x 14 1 PRIV15 Security enable on event input x 15 1 PRIV16 Security enable on event input x 16 1 PRIV17 Security enable on event input x 17 1 PRIV18 Security enable on event input x 18 1 PRIV19 Security enable on event input x 19 1 PRIV20 Security enable on event input x 20 1 PRIV21 Security enable on event input x 21 1 PRIV22 Security enable on event input x 22 1 PRIV23 Security enable on event input x 23 1 PRIV24 Security enable on event input x 24 1 PRIV25 Security enable on event input x 25 1 PRIV26 Security enable on event input x 26 1 PRIV27 Security enable on event input x 27 1 PRIV28 Security enable on event input x 28 1 PRIV29 Security enable on event input x 29 1 PRIV30 Security enable on event input x 30 1 PRIV31 Security enable on event input x 31 1 RTSR2 RTSR2 EXTI rising trigger selection register 0x20 0x20 read-write 0x00000000 RT35 Rising trigger event configuration bit of configurable event input x 3 1 RT36 Rising trigger event configuration bit of configurable event input x 4 1 RT37 Rising trigger event configuration bit of configurable event input x 5 1 RT38 Rising trigger event configuration bit of configurable event input x 6 1 FTSR2 FTSR2 EXTI falling trigger selection register 0x24 0x20 read-write 0x00000000 FT35 FT35 3 1 FT36 FT36 4 1 FT37 FT37 5 1 FT38 FT38 6 1 SWIER2 SWIER2 EXTI software interrupt event register 0x28 0x20 read-write 0x00000000 SWI35 SWI35 3 1 SWI36 SWI36 4 1 SWI37 SWI37 5 1 SWI38 SWI38 6 1 RPR2 RPR2 EXTI rising edge pending register 0x2C 0x20 read-write 0x00000000 RPIF35 RPIF35 3 1 RPIF36 RPIF36 4 1 RPIF37 RPIF37 5 1 RPIF38 RPIF38 6 1 FPR2 FPR2 EXTI falling edge pending register 0x30 0x20 read-write 0x00000000 FPIF35 FPIF35 3 1 FPIF36 FPIF36 4 1 FPIF37 FPIF37 5 1 FPIF38 FPIF38 6 1 SECCFGR2 SECCFGR2 EXTI security enable register 0x38 0x20 read-write 0x00000000 SEC32 SEC32 0 1 SEC33 SEC33 1 1 SEC34 SEC34 2 1 SEC35 SEC35 3 1 SEC36 SEC36 4 1 SEC37 SEC37 5 1 SEC38 SEC38 6 1 SEC39 SEC39 7 1 SEC40 SEC40 8 1 SEC41 SEC41 9 1 SEC42 SEC42 10 1 PRIVCFGR2 PRIVCFGR2 EXTI security enable register 0x34 0x20 read-write 0x00000000 PRIV32 PRIV32 0 1 PRIV33 PRIV33 1 1 PRIV34 PRIV34 2 1 PRIV35 PRIV35 3 1 PRIV36 PRIV36 4 1 PRIV37 PRIV37 5 1 PRIV38 PRIV38 6 1 PRIV39 PRIV39 7 1 PRIV40 PRIV40 8 1 PRIV41 PRIV41 9 1 PRIV42 PRIV42 10 1 EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 read-write 0x00000000 EXTI0 EXTIm GPIO port selection 0 8 EXTI1 EXTIm+1 GPIO port selection 8 8 EXTI2 EXTIm+2 GPIO port selection 16 8 EXTI3 EXTIm+3 GPIO port selection 24 8 EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 read-write 0x00000000 EXTI4 EXTIm GPIO port selection 0 8 EXTI5 EXTIm+1 GPIO port selection 8 8 EXTI6 EXTIm+2 GPIO port selection 16 8 EXTI7 EXTIm+3 GPIO port selection 24 8 EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 0x20 read-write 0x00000000 EXTI8 EXTIm GPIO port selection 0 8 EXTI9 EXTIm+1 GPIO port selection 8 8 EXTI10 EXTIm+2 GPIO port selection 16 8 EXTI11 EXTIm+3 GPIO port selection 24 8 EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 0x20 read-write 0x00000000 EXTI12 EXTIm GPIO port selection 0 8 EXTI13 EXTIm+1 GPIO port selection 8 8 EXTI14 EXTIm+2 GPIO port selection 16 8 EXTI15 EXTIm+3 GPIO port selection 24 8 LOCKRG LOCKRG EXTI lock register 0x70 0x20 read-write 0x00000000 LOCK LOCK 0 1 IMR1 IMR1 EXTI CPU wakeup with interrupt mask register 0x80 0x20 read-write 0xFF9E0000 IM0 CPU wakeup with interrupt mask on event input 0 1 IM1 CPU wakeup with interrupt mask on event input 1 1 IM2 CPU wakeup with interrupt mask on event input 2 1 IM3 CPU wakeup with interrupt mask on event input 3 1 IM4 CPU wakeup with interrupt mask on event input 4 1 IM5 CPU wakeup with interrupt mask on event input 5 1 IM6 CPU wakeup with interrupt mask on event input 6 1 IM7 CPU wakeup with interrupt mask on event input 7 1 IM8 CPU wakeup with interrupt mask on event input 8 1 IM9 CPU wakeup with interrupt mask on event input 9 1 IM10 CPU wakeup with interrupt mask on event input 10 1 IM11 CPU wakeup with interrupt mask on event input 11 1 IM12 CPU wakeup with interrupt mask on event input 12 1 IM13 CPU wakeup with interrupt mask on event input 13 1 IM14 CPU wakeup with interrupt mask on event input 14 1 IM15 CPU wakeup with interrupt mask on event input 15 1 IM16 CPU wakeup with interrupt mask on event input 16 1 IM17 CPU wakeup with interrupt mask on event input 17 1 IM18 CPU wakeup with interrupt mask on event input 18 1 IM19 CPU wakeup with interrupt mask on event input 19 1 IM20 CPU wakeup with interrupt mask on event input 20 1 IM21 CPU wakeup with interrupt mask on event input 21 1 IM22 CPU wakeup with interrupt mask on event input 22 1 IM23 CPU wakeup with interrupt mask on event input 23 1 IM24 CPU wakeup with interrupt mask on event input 24 1 IM25 CPU wakeup with interrupt mask on event input 25 1 IM26 CPU wakeup with interrupt mask on event input 26 1 IM27 CPU wakeup with interrupt mask on event input 27 1 IM28 CPU wakeup with interrupt mask on event input 28 1 IM29 CPU wakeup with interrupt mask on event input 29 1 IM30 CPU wakeup with interrupt mask on event input 30 1 IM31 CPU wakeup with interrupt mask on event input 31 1 EMR1 EMR1 EXTI CPU wakeup with event mask register 0x84 0x20 read-write 0x00000000 EM0 CPU wakeup with interrupt mask on event input 0 1 EM1 CPU wakeup with interrupt mask on event input 1 1 EM2 CPU wakeup with interrupt mask on event input 2 1 EM3 CPU wakeup with interrupt mask on event input 3 1 EM4 CPU wakeup with interrupt mask on event input 4 1 EM5 CPU wakeup with interrupt mask on event input 5 1 EM6 CPU wakeup with interrupt mask on event input 6 1 EM7 CPU wakeup with interrupt mask on event input 7 1 EM8 CPU wakeup with interrupt mask on event input 8 1 EM9 CPU wakeup with interrupt mask on event input 9 1 EM10 CPU wakeup with interrupt mask on event input 10 1 EM11 CPU wakeup with interrupt mask on event input 11 1 EM12 CPU wakeup with interrupt mask on event input 12 1 EM13 CPU wakeup with interrupt mask on event input 13 1 EM14 CPU wakeup with interrupt mask on event input 14 1 EM15 CPU wakeup with interrupt mask on event input 15 1 EM16 CPU wakeup with interrupt mask on event input 16 1 EM17 CPU wakeup with interrupt mask on event input 17 1 EM18 CPU wakeup with interrupt mask on event input 18 1 EM19 CPU wakeup with interrupt mask on event input 19 1 EM20 CPU wakeup with interrupt mask on event input 20 1 EM21 CPU wakeup with interrupt mask on event input 21 1 EM22 CPU wakeup with interrupt mask on event input 22 1 EM23 CPU wakeup with interrupt mask on event input 23 1 EM24 CPU wakeup with interrupt mask on event input 24 1 EM25 CPU wakeup with interrupt mask on event input 25 1 EM26 CPU wakeup with interrupt mask on event input 26 1 EM27 CPU wakeup with interrupt mask on event input 27 1 EM28 CPU wakeup with interrupt mask on event input 28 1 EM29 CPU wakeup with interrupt mask on event input 29 1 EM30 CPU wakeup with interrupt mask on event input 30 1 EM31 CPU wakeup with interrupt mask on event input 31 1 IMR2 IMR2 EXTI CPUm wakeup with interrupt mask register 0x90 0x20 read-write 0x00000787 IM32 CPU wakeup with interrupt mask on event input 0 1 IM33 CPU wakeup with interrupt mask on event input 1 1 IM34 CPU wakeup with interrupt mask on event input 2 1 IM35 CPU wakeup with interrupt mask on event input 3 1 IM36 CPU wakeup with interrupt mask on event input 4 1 IM37 CPU wakeup with interrupt mask on event input 5 1 IM38 CPU wakeup with interrupt mask on event input 6 1 IM40 CPU wakeup with interrupt mask on event input 8 1 IM41 CPU wakeup with interrupt mask on event input 9 1 IM42 CPU wakeup with interrupt mask on event input 10 1 EMR2 EMR2 EXTI CPU wakeup with event mask register 0x94 0x20 read-write 0x00000000 EM32 CPU wakeup with interrupt mask on event input 0 1 EM33 CPU wakeup with interrupt mask on event input 1 1 EM34 CPU wakeup with interrupt mask on event input 2 1 EM35 CPU wakeup with interrupt mask on event input 3 1 EM36 CPU wakeup with interrupt mask on event input 4 1 EM37 CPU wakeup with interrupt mask on event input 5 1 EM38 CPU wakeup with interrupt mask on event input 6 1 EM40 CPU wakeup with interrupt mask on event input 8 1 EM41 CPU wakeup with interrupt mask on event input 9 1 EM42 CPU wakeup with interrupt mask on event input 10 1 SEC_EXTI 0x5002F400 FDCAN1 FDCAN1 FDCAN 0x4000A400 0x0 0xC00 registers FDCAN1_IT0 FDCAN1 Interrupt 0 39 FDCAN1_IT1 FDCAN1 Interrupt 1 40 CREL CREL FDCAN Core Release Register 0x0 0x20 read-only 0x32141218 REL Core release 28 4 STEP Step of Core release 24 4 SUBSTEP Sub-step of Core release 20 4 YEAR Timestamp Year 16 4 MON Timestamp Month 8 8 DAY Timestamp Day 0 8 ENDN ENDN FDCAN Core Release Register 0x4 0x20 read-only 0x87654321 ETV Endiannes Test Value 0 32 DBTP DBTP FDCAN Data Bit Timing and Prescaler Register 0xC 0x20 read-write 0x00000A33 DSJW Synchronization Jump Width 0 4 DTSEG2 Data time segment after sample point 4 4 DTSEG1 Data time segment after sample point 8 5 DBRP Data BIt Rate Prescaler 16 5 TDC Transceiver Delay Compensation 23 1 TEST TEST FDCAN Test Register 0x10 0x20 0x00000010 LBCK Loop Back mode 4 1 read-write TX Loop Back mode 5 2 read-write RX Control of Transmit Pin 7 1 read-only RWD RWD FDCAN RAM Watchdog Register 0x14 0x20 0x00000000 WDV Watchdog value 8 8 read-only WDC Watchdog configuration 0 8 read-write CCCR CCCR FDCAN CC Control Register 0x18 0x20 read-write 0x00000001 INIT Initialization 0 1 CCE Configuration Change Enable 1 1 ASM ASM Restricted Operation Mode 2 1 CSA Clock Stop Acknowledge 3 1 CSR Clock Stop Request 4 1 MON Bus Monitoring Mode 5 1 DAR Disable Automatic Retransmission 6 1 TEST Test Mode Enable 7 1 FDOE FD Operation Enable 8 1 BSE FDCAN Bit Rate Switching 9 1 PXHD Protocol Exception Handling Disable 12 1 EFBI Edge Filtering during Bus Integration 13 1 TXP TXP 14 1 NISO Non ISO Operation 15 1 NBTP NBTP FDCAN Nominal Bit Timing and Prescaler Register 0x1C 0x20 read-write 0x06000A03 NSJW NSJW: Nominal (Re)Synchronization Jump Width 25 7 NBRP Bit Rate Prescaler 16 9 NTSEG1 Nominal Time segment before sample point 8 8 TSEG2 Nominal Time segment after sample point 0 7 TSCC TSCC FDCAN Timestamp Counter Configuration Register 0x20 0x20 read-write 0x00000000 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 TSCV TSCV FDCAN Timestamp Counter Value Register 0x24 0x20 read-write 0x00000000 TSC Timestamp Counter 0 16 TOCC TOCC FDCAN Timeout Counter Configuration Register 0x28 0x20 read-write 0xFFFF0000 ETOC Enable Timeout Counter 0 1 TOS Timeout Select 1 2 TOP Timeout Period 16 16 TOCV TOCV FDCAN Timeout Counter Value Register 0x2C 0x20 read-write 0x0000FFFF TOC Timeout Counter 0 16 ECR ECR FDCAN Error Counter Register 0x40 0x20 0x00000000 CEL AN Error Logging 16 8 read-write RP Receive Error Passive 15 1 read-write REC Receive Error Counter 8 7 read-only TEC Transmit Error Counter 0 8 read-only PSR PSR FDCAN Protocol Status Register 0x44 0x20 0x00000707 LEC Last Error Code 0 3 read-write ACT Activity 3 2 read-only EP Error Passive 5 1 read-only EW Warning Status 6 1 read-only BO Bus_Off Status 7 1 read-only DLEC Data Last Error Code 8 3 read-write RESI ESI flag of last received FDCAN Message 11 1 read-write RBRS BRS flag of last received FDCAN Message 12 1 read-write REDL Received FDCAN Message 13 1 read-write PXE Protocol Exception Event 14 1 read-write TDCV Transmitter Delay Compensation Value 16 7 read-only TDCR TDCR FDCAN Transmitter Delay Compensation Register 0x48 0x20 read-write 0x00000000 TDCF Transmitter Delay Compensation Filter Window Length 0 7 TDCO Transmitter Delay Compensation Offset 8 7 IR IR FDCAN Interrupt Register 0x50 0x20 read-write 0x00000000 RF0N RF0N 0 1 RF0F RF0F 1 1 RF0L RF0L 2 1 RF1N RF1N 3 1 RF1F RF1F 4 1 RF1L RF1L 5 1 HPM HPM 6 1 TC TC 7 1 TCF TCF 8 1 TFE TFE 9 1 TEFN TEFN 10 1 TEFF TEFF 11 1 TEFL TEFL 12 1 TSW TSW 13 1 MRAF MRAF 14 1 TOO TOO 15 1 ELO ELO 16 1 EP EP 17 1 EW EW 18 1 BO BO 19 1 WDI WDI 20 1 PEA PEA 21 1 PED PED 22 1 ARA ARA 23 1 IE IE FDCAN Interrupt Enable Register 0x54 0x20 read-write 0x00000000 RF0NE Rx FIFO 0 New Message Enable 0 1 RF0FE Rx FIFO 0 Full Enable 1 1 RF0LE Rx FIFO 0 Message Lost Enable 2 1 RF1NE Rx FIFO 1 New Message Enable 3 1 RF1FE Rx FIFO 1 Watermark Reached Enable 4 1 RF1LE Rx FIFO 1 Message Lost Enable 5 1 HPME High Priority Message Enable 6 1 TCE Transmission Completed Enable 7 1 TCFE Transmission Cancellation Finished Enable 8 1 TEFE Tx FIFO Empty Enable 9 1 TEFNE Tx Event FIFO New Entry Enable 10 1 TEFFE Tx Event FIFO Full Enable 11 1 TEFLE Tx Event FIFO Element Lost Enable 12 1 MRAFE Message RAM Access Failure Enable 13 1 TOOE Timeout Occurred Enable 14 1 ELOE Error Logging Overflow Enable 15 1 EPE Error Passive Enable 16 1 EWE Warning Status Enable 17 1 BOE Bus_Off Status Enable 18 1 WDIE Watchdog Interrupt Enable 19 1 PEAE Protocol Error in Arbitration Phase Enable 20 1 PEDE Protocol Error in Data Phase Enable 21 1 ARAE Access to Reserved Address Enable 22 1 ILS ILS FDCAN Interrupt Line Select Register 0x58 0x20 read-write 0x00000000 RxFIFO0 RxFIFO0 0 1 RxFIFO1 RxFIFO1 1 1 SMSG SMSG 2 1 TFERR TFERR 3 1 MISC MISC 4 1 BERR BERR 5 1 PERR PERR 6 1 ILE ILE FDCAN Interrupt Line Enable Register 0x5C 0x20 read-write 0x00000000 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 RXGFC RXGFC FDCAN Global Filter Configuration Register 0x80 0x20 read-write 0x00000000 RRFE Reject Remote Frames Extended 0 1 RRFS Reject Remote Frames Standard 1 1 ANFE Accept Non-matching Frames Extended 2 2 ANFS Accept Non-matching Frames Standard 4 2 F1OM F1OM 8 1 F0OM F0OM 9 1 LSS LSS 16 5 LSE LSE 24 4 XIDAM XIDAM FDCAN Extended ID and Mask Register 0x84 0x20 read-write 0x1FFFFFFF EIDM Extended ID Mask 0 29 HPMS HPMS FDCAN High Priority Message Status Register 0x88 0x20 read-only 0x00000000 BIDX Buffer Index 0 3 MSI Message Storage Indicator 6 2 FIDX Filter Index 8 5 FLST Filter List 15 1 RXF0S RXF0S FDCAN Rx FIFO 0 Status Register 0x90 0x20 read-write 0x00000000 F0FL Rx FIFO 0 Fill Level 0 4 F0GI Rx FIFO 0 Get Index 8 2 F0PI Rx FIFO 0 Put Index 16 2 F0F Rx FIFO 0 Full 24 1 RF0L Rx FIFO 0 Message Lost 25 1 RXF0A RXF0A CAN Rx FIFO 0 Acknowledge Register 0x94 0x20 read-write 0x00000000 F0AI Rx FIFO 0 Acknowledge Index 0 3 RXF1S RXF1S FDCAN Rx FIFO 1 Status Register 0x98 0x20 0x00000000 F1FL Rx FIFO 1 Fill Level 0 4 read-write F1GI Rx FIFO 1 Get Index 8 2 read-only F1PI Rx FIFO 1 Put Index 16 2 read-only F1F Rx FIFO 1 Full 24 1 read-only RF1L Rx FIFO 1 Message Lost 25 1 read-only RXF1A RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0x9C 0x20 read-write 0x00000000 F1AI Rx FIFO 1 Acknowledge Index 0 3 TXFQS TXFQS FDCAN Tx FIFO/Queue Status Register 0xC4 0x20 read-only 0x00000003 TFFL Tx FIFO Free Level 0 3 TFGI TFGI 8 2 TFQPI Tx FIFO/Queue Put Index 16 2 TFQF Tx FIFO/Queue Full 21 1 TXBRP TXBRP FDCAN Tx Buffer Request Pending Register 0xC8 0x20 read-only 0x00000000 TRP Transmission Request Pending 0 3 TXBAR TXBAR FDCAN Tx Buffer Add Request Register 0xCC 0x20 read-write 0x00000000 AR Add Request 0 3 TXBCR TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD0 0x20 read-write 0x00000000 CR Cancellation Request 0 3 TXBTO TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD4 0x20 read-only 0x00000000 TO Transmission Occurred. 0 3 TXBCF TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xD8 0x20 read-only 0x00000000 CF Cancellation Finished 0 3 TXBTIE TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xDC 0x20 read-write 0x00000000 TIE Transmission Interrupt Enable 0 3 TXBCIE TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE0 0x20 read-write 0x00000000 CF Cancellation Finished Interrupt Enable 0 3 TXEFS TXEFS FDCAN Tx Event FIFO Status Register 0xE4 0x20 read-only 0x00000000 EFFL Event FIFO Fill Level 0 3 EFGI Event FIFO Get Index. 8 2 EFF Event FIFO Full. 24 1 TEFL Tx Event FIFO Element Lost. 25 1 EFPI Event FIFO Put Index 16 2 TXEFA TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xE8 0x20 read-write 0x00000000 EFAI Event FIFO Acknowledge Index 0 2 CKDIV CKDIV FDCAN TT Trigger Memory Configuration Register 0x100 0x20 read-write 0x00000000 PDIV PDIV 0 4 TXBC TXBC FDCAN Tx buffer configuration register 0xC0 0x20 read-write 0x00000000 TFQM Tx FIFO/Queue Mode 24 1 SEC_FDCAN1 0x5000A400 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 6 FLASH_S Flash memory secure global interrupt 7 ACR ACR Access control register 0x0 0x20 read-write 0x00000000 LATENCY Latency 0 4 RUN_PD Flash Power-down mode during Low-power run mode 13 1 SLEEP_PD Flash Power-down mode during Low-power sleep mode 14 1 LVEN LVEN 15 1 PDKEYR PDKEYR Power down key register 0x4 0x20 write-only 0x00000000 PDKEYR RUN_PD in FLASH_ACR key 0 32 NSKEYR NSKEYR Flash non-secure key register 0x8 0x20 write-only 0x00000000 NSKEYR NSKEYR 0 32 SECKEYR SECKEYR Flash secure key register 0xC 0x20 write-only 0x00000000 SECKEYR SECKEYR 0 32 OPTKEYR OPTKEYR Flash option key register 0x10 0x20 write-only 0x00000000 OPTKEYR OPTKEYR 0 32 LVEKEYR LVEKEYR Flash low voltage key register 0x14 0x20 write-only 0x00000000 LVEKEYR LVEKEYR 0 32 NSSR NSSR Flash status register 0x20 0x20 0x00000000 NSEOP NSEOP 0 1 read-write NSOPERR NSOPERR 1 1 read-write NSPROGERR NSPROGERR 3 1 read-write NSWRPERR NSWRPERR 4 1 read-write NSPGAERR NSPGAERR 5 1 read-write NSSIZERR NSSIZERR 6 1 read-write NSPGSERR NSPGSERR 7 1 read-write OPTWERR OPTWERR 13 1 read-write OPTVERR OPTVERR 15 1 read-write NSBSY NSBusy 16 1 read-only SECSR SECSR Flash status register 0x24 0x20 0x00000000 SECEOP SECEOP 0 1 read-write SECOPERR SECOPERR 1 1 read-write SECPROGERR SECPROGERR 3 1 read-write SECWRPERR SECWRPERR 4 1 read-write SECPGAERR SECPGAERR 5 1 read-write SECSIZERR SECSIZERR 6 1 read-write SECPGSERR SECPGSERR 7 1 read-write SECRDERR Secure read protection error 14 1 read-write SECBSY SECBusy 16 1 read-only NSCR NSCR Flash non-secure control register 0x28 0x20 read-write 0xC0000000 NSPG NSPG 0 1 NSPER NSPER 1 1 NSMER1 NSMER1 2 1 NSPNB NSPNB 3 7 NSBKER NSBKER 11 1 NSMER2 NSMER2 15 1 NSSTRT Options modification start 16 1 OPTSTRT Options modification start 17 1 NSEOPIE NSEOPIE 24 1 NSERRIE NSERRIE 25 1 OBL_LAUNCH Force the option byte loading 27 1 OPTLOCK Options Lock 30 1 NSLOCK NSLOCK 31 1 SECCR SECCR Flash secure control register 0x2C 0x20 read-write 0x80000000 SECPG SECPG 0 1 SECPER SECPER 1 1 SECMER1 SECMER1 2 1 SECPNB SECPNB 3 7 SECBKER SECBKER 11 1 SECMER2 SECMER2 15 1 SECSTRT SECSTRT 16 1 SECEOPIE SECEOPIE 24 1 SECERRIE SECERRIE 25 1 SECRDERRIE SECRDERRIE 26 1 SECINV SECINV 29 1 SECLOCK SECLOCK 31 1 ECCR ECCR Flash ECC register 0x30 0x20 0x00000000 ADDR_ECC ECC fail address 0 19 read-only BK_ECC BK_ECC 21 1 read-only SYSF_ECC SYSF_ECC 22 1 read-only ECCIE ECC correction interrupt enable 24 1 read-write ECCC2 ECCC2 28 1 read-write ECCD2 ECCD2 29 1 read-write ECCC ECC correction 30 1 read-write ECCD ECC detection 31 1 read-write OPTR OPTR Flash option register 0x40 0x20 read-write 0x00000000 RDP Read protection level 0 8 BOR_LEV BOR reset Level 8 3 nRST_STOP nRST_STOP 12 1 nRST_STDBY nRST_STDBY 13 1 nRST_SHDW nRST_SHDW 14 1 IWDG_SW Independent watchdog selection 16 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 WWDG_SW Window watchdog selection 19 1 SWAP_BANK SWAP_BANK 20 1 DB256K DB256K 21 1 DBANK DBANK 22 1 SRAM2_PE SRAM2 parity check enable 24 1 SRAM2_RST SRAM2 Erase when system reset 25 1 nSWBOOT0 nSWBOOT0 26 1 nBOOT0 nBOOT0 27 1 PA15_PUPEN PA15_PUPEN 28 1 TZEN TZEN 31 1 NSBOOTADD0R NSBOOTADD0R Flash non-secure boot address 0 register 0x44 0x20 write-only 0x0000000F NSBOOTADD0 NSBOOTADD0 7 25 NSBOOTADD1R NSBOOTADD1R Flash non-secure boot address 1 register 0x48 0x20 write-only 0x0000000F NSBOOTADD1 NSBOOTADD1 7 25 SECBOOTADD0R SECBOOTADD0R FFlash secure boot address 0 register 0x4C 0x20 0x00000000 BOOT_LOCK BOOT_LOCK 0 1 read-write SECBOOTADD0 SECBOOTADD0 7 25 write-only SECWM1R1 SECWM1R1 Flash bank 1 secure watermak1 register 0x50 0x20 read-write 0xFF00FF00 SECWM1_PSTRT SECWM1_PSTRT 0 7 SECWM1_PEND SECWM1_PEND 16 7 SECWM1R2 SECWM1R2 Flash secure watermak1 register 2 0x54 0x20 read-write 0x0F000F00 PCROP1_PSTRT PCROP1_PSTRT 0 7 PCROP1EN PCROP1EN 15 1 HDP1_PEND HDP1_PEND 16 7 HDP1EN HDP1EN 31 1 WRP1AR WRP1AR Flash Bank 1 WRP area A address register 0x58 0x20 read-write 0xFF00FF00 WRP1A_PSTRT WRP1A_PSTRT 0 7 WRP1A_PEND WRP1A_PEND 16 7 WRP1BR WRP1BR Flash Bank 1 WRP area B address register 0x5C 0x20 read-write 0xFF00FF00 WRP1B_PSTRT WRP1B_PSTRT 0 7 WRP1B_PEND WRP1B_PEND 16 7 SECWM2R1 SECWM2R1 Flash secure watermak2 register 0x60 0x20 read-write 0xFF00FF00 SECWM2_PSTRT SECWM2_PSTRT 0 7 SECWM2_PEND SECWM2_PEND 16 7 SECWM2R2 SECWM2R2 Flash secure watermak2 register2 0x64 0x20 read-write 0x0F000F00 PCROP2_PSTRT PCROP2_PSTRT 0 7 PCROP2EN PCROP2EN 15 1 HDP2_PEND HDP2_PEND 16 7 HDP2EN HDP2EN 31 1 WRP2AR WRP2AR Flash WPR2 area A address register 0x68 0x20 read-write 0xFF00FF00 WRP2A_PSTRT WRP2A_PSTRT 0 7 WRP2A_PEND WRP2A_PEND 16 7 WRP2BR WRP2BR Flash WPR2 area B address register 0x6C 0x20 read-write 0xFF00FF00 WRP2B_PSTRT WRP2B_PSTRT 0 7 WRP2B_PEND WRP2B_PEND 16 7 4 0x4 1-4 SECBB1R%s SECBB1R%s FLASH secure block based bank 1 0x80 0x20 read-write 0x00000000 SECBB1 SECBB1 0 32 4 0x4 1-4 SECBB2R%s SECBB2R%s FLASH secure block based bank 2 0xA0 0x20 read-write 0x00000000 SECBB2 SECBB2 0 32 SECHDPCR SECHDPCR FLASH secure HDP control register 0xC0 0x20 read-write 0x00000000 HDP1_ACCDIS HDP1_ACCDIS 0 1 HDP2_ACCDIS HDP2_ACCDIS 1 1 PRIVCFGR PRIVCFGR Power privilege configuration register 0xC4 0x20 read-write 0x00000000 PRIV PRIV 0 1 SEC_FLASH 0x50022000 FMC FMC FMC 0x44020000 0x0 0x400 registers FMC FMC global interrupt 75 BCR1 BCR1 FMC_BCR1 0x0 0x20 read-write 0x000030DB MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MUXEN Disabled Address/Data non-multiplexed 0 Enabled Address/Data multiplexed on databus 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MTYP SRAM SRAM memory type 0 PSRAM PSRAM (CRAM) memory type 1 Flash NOR Flash/OneNAND Flash 2 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 FACCEN Disabled Corresponding NOR Flash memory access is disabled 0 Enabled Corresponding NOR Flash memory access is enabled 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 BURSTEN Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WAITPOL ActiveLow NWAIT active low 0 ActiveHigh NWAIT active high 1 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WAITCFG BeforeWaitState NWAIT signal is active one data cycle before wait state 0 DuringWaitState NWAIT signal is active during wait state 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 WREN Disabled Write operations disabled for the bank by the FMC 0 Enabled Write operations enabled for the bank by the FMC 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 WAITEN Disabled Values inside the FMC_BWTR are taken into account 0 Enabled NWAIT signal enabled 1 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 EXTMOD Disabled Values inside the FMC_BWTR are not taken into account 0 Enabled Values inside the FMC_BWTR are taken into account 1 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 ASYNCWAIT Disabled Wait signal not used in asynchronous mode 0 Enabled Wait signal used even in asynchronous mode 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 CPSIZE NoBurstSplit No burst split when crossing page boundary 0 Bytes128 128 bytes CRAM page size 1 Bytes256 256 bytes CRAM page size 2 Bytes512 512 bytes CRAM page size 3 Bytes1024 1024 bytes CRAM page size 4 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 CBURSTRW Disabled Write operations are always performed in asynchronous mode 0 Enabled Write operations are performed in synchronous mode 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 CCLKEN Disabled The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set 0 Enabled The FMC_CLK is only generated during the synchronous memory access (read/write transaction) 1 WFDIS Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 21 1 WFDIS Enabled Write FIFO enabled 0 Disabled Write FIFO disabled 1 NBLSET NBLSET 22 2 3 0x8 2-4 BCR%s BCR%s SRAM/NOR-Flash chip-select control register %s 0x8 0x20 read-write 0x000030D2 MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 NBLSET NBLSET 22 2 4 0x8 1-4 BTR%s BTR%s SRAM/NOR-flash chip-select timing registers for bank %s 0x4 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. 0 4 0 15 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 1 15 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 1 255 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ... 16 4 0 15 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 1 15 DATLAT Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles 24 4 0 15 ACCMOD Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATAHLD DATAHLD 30 2 PCR PCR NAND Flash control registers 0x80 0x20 read-write 0x00000018 PWAITEN Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank: 1 1 PWAITEN Disabled Wait feature disabled 0 Enabled Wait feature enabled 1 PBKEN NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus 2 1 PBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 PTYP Memory type 3 1 PTYP NANDFlash NAND Flash 1 PWID Data bus width. These bits define the external memory device width. 4 2 PWID Bits8 External memory device width 8 bits 0 Bits16 External memory device width 16 bits 1 ECCEN ECC computation logic enable bit 6 1 ECCEN Disabled ECC logic is disabled and reset 0 Enabled ECC logic is enabled 1 TCLR CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 9 4 0 15 TAR ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 13 4 0 15 ECCPS ECC page size. These bits define the page size for the extended ECC: 17 3 ECCPS Bytes256 ECC page size 256 bytes 0 Bytes512 ECC page size 512 bytes 1 Bytes1024 ECC page size 1024 bytes 2 Bytes2048 ECC page size 2048 bytes 3 Bytes4096 ECC page size 4096 bytes 4 Bytes8192 ECC page size 8192 bytes 5 SR SR This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty. 0x84 0x20 0x00000040 IRS Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 0 1 read-write IRS DidNotOccur Interrupt rising edge did not occur 0 Occurred Interrupt rising edge occurred 1 ILS Interrupt high-level status The flag is set by hardware and reset by software. 1 1 read-write ILS DidNotOccur Interrupt high-level did not occur 0 Occurred Interrupt high-level occurred 1 IFS Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 2 1 read-write IFS DidNotOccur Interrupt falling edge did not occur 0 Occurred Interrupt falling edge occurred 1 IREN Interrupt rising edge detection enable bit 3 1 read-write IREN Disabled Interrupt rising edge detection request disabled 0 Enabled Interrupt rising edge detection request enabled 1 ILEN Interrupt high-level detection enable bit 4 1 read-write ILEN Disabled Interrupt high-level detection request disabled 0 Enabled Interrupt high-level detection request enabled 1 IFEN Interrupt falling edge detection enable bit 5 1 read-write IFEN Disabled Interrupt falling edge detection request disabled 0 Enabled Interrupt falling edge detection request enabled 1 FEMPT FIFO empty. Read-only bit that provides the status of the FIFO 6 1 read-only FEMPT NotEmpty FIFO not empty 0 Empty FIFO empty 1 PMEM PMEM The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access. 0x88 0x20 read-write 0xFCFCFCFC MEMSET Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space: 0 8 0 254 MEMWAIT Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 1 254 MEMHOLD Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space: 16 8 1 254 MEMHIZ Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions: 24 8 0 254 PATT PATT The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature). 0x8C 0x20 read-write 0xFCFCFCFC ATTSET Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 0 8 0 254 ATTWAIT Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 1 254 ATTHOLD Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 16 8 1 254 ATTHIZ Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 24 8 0 254 ECCR ECCR This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. 0x94 0x20 read-only 0x00000000 ECC ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields. 0 32 0 4294967295 4 0x8 1-4 BWTR%s BWTR%s This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x104 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 0 15 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 4 4 1 15 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 8 8 1 255 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ... 16 4 0 15 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 PCSCNTR PCSCNTR PCSCNTR 0x20 0x20 read-write 0x00000000 CSCOUNT Chip select counter 0 16 4 0x1 1-4 CNTB%sEN Counter Bank %s enable 16 1 SEC_FMC 0x54020000 GPIOA General-purpose I/Os GPIO 0x42020000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xABFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 IDR%s Port input data pin %s 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 ODR%s Port output data pin %s 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 16 1 BitReset Reset Resets the corresponding ODx bit 1 16 0x1 0-15 BS%s Port x set pin %s 0 1 BitSet Set Sets the corresponding ODx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 8 0x4 EL0,EL1,EL2,EL3,EL4,EL5,EL6,EL7 AFR%s Alternate function selection for port x bit y (y = 0..7) 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 8 0x4 EL8,EL9,EL10,EL11,EL12,EL13,EL14,EL15 AFR%s Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 0 1 BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 write-only 0x00000000 SEC0 I/O pin of Port x secure bit enable 0 1 SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 SEC1 I/O pin of Port x secure bit enable 1 1 SEC2 I/O pin of Port x secure bit enable 2 1 SEC3 I/O pin of Port x secure bit enable 3 1 SEC4 I/O pin of Port x secure bit enable 4 1 SEC5 I/O pin of Port x secure bit enable 5 1 SEC6 I/O pin of Port x secure bit enable 6 1 SEC7 I/O pin of Port x secure bit enable 7 1 SEC8 I/O pin of Port x secure bit enable 8 1 SEC9 I/O pin of Port x secure bit enable 9 1 SEC10 I/O pin of Port x secure bit enable 10 1 SEC11 I/O pin of Port x secure bit enable 11 1 SEC12 I/O pin of Port x secure bit enable 12 1 SEC13 I/O pin of Port x secure bit enable 13 1 SEC14 I/O pin of Port x secure bit enable 14 1 SEC15 I/O pin of Port x secure bit enable 15 1 SEC_GPIOA 0x52020000 GPIOB General-purpose I/Os GPIO 0x42020400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFEBF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 write-only 0x00000000 SEC0 I/O pin of Port x secure bit enable 0 1 SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 SEC1 I/O pin of Port x secure bit enable 1 1 SEC2 I/O pin of Port x secure bit enable 2 1 SEC3 I/O pin of Port x secure bit enable 3 1 SEC4 I/O pin of Port x secure bit enable 4 1 SEC5 I/O pin of Port x secure bit enable 5 1 SEC6 I/O pin of Port x secure bit enable 6 1 SEC7 I/O pin of Port x secure bit enable 7 1 SEC8 I/O pin of Port x secure bit enable 8 1 SEC9 I/O pin of Port x secure bit enable 9 1 SEC10 I/O pin of Port x secure bit enable 10 1 SEC11 I/O pin of Port x secure bit enable 11 1 SEC12 I/O pin of Port x secure bit enable 12 1 SEC13 I/O pin of Port x secure bit enable 13 1 SEC14 I/O pin of Port x secure bit enable 14 1 SEC15 I/O pin of Port x secure bit enable 15 1 SEC_GPIOB 0x52020400 GPIOC General-purpose I/Os GPIO 0x42020800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 write-only 0x00000000 SEC0 I/O pin of Port x secure bit enable 0 1 SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 SEC1 I/O pin of Port x secure bit enable 1 1 SEC2 I/O pin of Port x secure bit enable 2 1 SEC3 I/O pin of Port x secure bit enable 3 1 SEC4 I/O pin of Port x secure bit enable 4 1 SEC5 I/O pin of Port x secure bit enable 5 1 SEC6 I/O pin of Port x secure bit enable 6 1 SEC7 I/O pin of Port x secure bit enable 7 1 SEC8 I/O pin of Port x secure bit enable 8 1 SEC9 I/O pin of Port x secure bit enable 9 1 SEC10 I/O pin of Port x secure bit enable 10 1 SEC11 I/O pin of Port x secure bit enable 11 1 SEC12 I/O pin of Port x secure bit enable 12 1 SEC13 I/O pin of Port x secure bit enable 13 1 SEC14 I/O pin of Port x secure bit enable 14 1 SEC15 I/O pin of Port x secure bit enable 15 1 GPIOD 0x42020C00 GPIOE 0x42021000 GPIOF 0x42021400 GPIOG 0x42021800 SEC_GPIOC 0x52020800 SEC_GPIOD 0x52020C00 SEC_GPIOE 0x52021000 SEC_GPIOF 0x52021400 SEC_GPIOG 0x52021800 GPIOH General-purpose I/Os GPIO 0x42021C00 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x0000000F 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 write-only 0x00000000 SEC0 I/O pin of Port x secure bit enable 0 1 SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 SEC1 I/O pin of Port x secure bit enable 1 1 SEC2 I/O pin of Port x secure bit enable 2 1 SEC3 I/O pin of Port x secure bit enable 3 1 SEC4 I/O pin of Port x secure bit enable 4 1 SEC5 I/O pin of Port x secure bit enable 5 1 SEC6 I/O pin of Port x secure bit enable 6 1 SEC7 I/O pin of Port x secure bit enable 7 1 SEC8 I/O pin of Port x secure bit enable 8 1 SEC9 I/O pin of Port x secure bit enable 9 1 SEC10 I/O pin of Port x secure bit enable 10 1 SEC11 I/O pin of Port x secure bit enable 11 1 SEC12 I/O pin of Port x secure bit enable 12 1 SEC13 I/O pin of Port x secure bit enable 13 1 SEC14 I/O pin of Port x secure bit enable 14 1 SEC15 I/O pin of Port x secure bit enable 15 1 SEC_GPIOH 0x52021C00 GTZC_MPCBB1 GTZC_MPCBB1 GTZC 0x40032C00 0x0 0x400 registers CR CR MPCBB control register 0x0 0x20 read-write 0x00000000 LCK LCK 0 1 INVSECSTATE INVSECSTATE 30 1 SRWILADIS SRWILADIS 31 1 LCKVTR1 LCKVTR1 MPCBB control register 0x10 0x20 read-write 0x00000000 LCKSB0 LCKSB0 0 1 LCKSB1 LCKSB1 1 1 LCKSB2 LCKSB2 2 1 LCKSB3 LCKSB3 3 1 LCKSB4 LCKSB4 4 1 LCKSB5 LCKSB5 5 1 LCKSB6 LCKSB6 6 1 LCKSB7 LCKSB7 7 1 LCKSB8 LCKSB8 8 1 LCKSB9 LCKSB9 9 1 LCKSB10 LCKSB10 10 1 LCKSB11 LCKSB11 11 1 LCKSB12 LCKSB12 12 1 LCKSB13 LCKSB13 13 1 LCKSB14 LCKSB14 14 1 LCKSB15 LCKSB15 15 1 LCKSB16 LCKSB16 16 1 LCKSB17 LCKSB17 17 1 LCKSB18 LCKSB18 18 1 LCKSB19 LCKSB19 19 1 LCKSB20 LCKSB20 20 1 LCKSB21 LCKSB21 21 1 LCKSB22 LCKSB22 22 1 LCKSB23 LCKSB23 23 1 LCKSB24 LCKSB24 24 1 LCKSB25 LCKSB25 25 1 LCKSB26 LCKSB26 26 1 LCKSB27 LCKSB27 27 1 LCKSB28 LCKSB28 28 1 LCKSB29 LCKSB29 29 1 LCKSB30 LCKSB30 30 1 LCKSB31 LCKSB31 31 1 LCKVTR2 LCKVTR2 MPCBB control register 0x14 0x20 read-write 0x00000000 LCKSB32 LCKSB32 0 1 LCKSB33 LCKSB33 1 1 LCKSB34 LCKSB34 2 1 LCKSB35 LCKSB35 3 1 LCKSB36 LCKSB36 4 1 LCKSB37 LCKSB37 5 1 LCKSB38 LCKSB38 6 1 LCKSB39 LCKSB39 7 1 LCKSB40 LCKSB40 8 1 LCKSB41 LCKSB41 9 1 LCKSB42 LCKSB42 10 1 LCKSB43 LCKSB43 11 1 LCKSB44 LCKSB44 12 1 LCKSB45 LCKSB45 13 1 LCKSB46 LCKSB46 14 1 LCKSB47 LCKSB47 15 1 LCKSB48 LCKSB48 16 1 LCKSB49 LCKSB49 17 1 LCKSB50 LCKSB50 18 1 LCKSB51 LCKSB51 19 1 LCKSB52 LCKSB52 20 1 LCKSB53 LCKSB53 21 1 LCKSB54 LCKSB54 22 1 LCKSB55 LCKSB55 23 1 LCKSB56 LCKSB56 24 1 LCKSB57 LCKSB57 25 1 LCKSB58 LCKSB58 26 1 LCKSB59 LCKSB59 27 1 LCKSB60 LCKSB60 28 1 LCKSB61 LCKSB61 29 1 LCKSB62 LCKSB62 30 1 LCKSB63 LCKSB63 31 1 64 0x4 0-63 VCTR%s VCTR%s MPCBBx vector register 0x100 0x20 read-write 0xFFFFFFFF B0 B0 0 1 B1 B1 1 1 B2 B2 2 1 B3 B3 3 1 B4 B4 4 1 B5 B5 5 1 B6 B6 6 1 B7 B7 7 1 B8 B8 8 1 B9 B9 9 1 B10 B10 10 1 B11 B11 11 1 B12 B12 12 1 B13 B13 13 1 B14 B14 14 1 B15 B15 15 1 B16 B16 16 1 B17 B17 17 1 B18 B18 18 1 B19 B19 19 1 B20 B20 20 1 B21 B21 21 1 B22 B22 22 1 B23 B23 23 1 B24 B24 24 1 B25 B25 25 1 B26 B26 26 1 B27 B27 27 1 B28 B28 28 1 B29 B29 29 1 B30 B30 30 1 B31 B31 31 1 SEC_GTZC_MPCBB1 SEC_GTZC_MPCBB1 SEC_GTZC 0x50032C00 GTZC_MPCBB2 GTZC_MPCBB2 GTZC 0x40033000 0x0 0x400 registers CR CR MPCBB control register 0x0 0x20 read-write 0x00000000 LCK LCK 0 1 INVSECSTATE INVSECSTATE 30 1 SRWILADIS SRWILADIS 31 1 LCKVTR1 LCKVTR1 MPCBB control register 0x10 0x20 read-write 0x00000000 LCKSB0 LCKSB0 0 1 LCKSB1 LCKSB1 1 1 LCKSB2 LCKSB2 2 1 LCKSB3 LCKSB3 3 1 LCKSB4 LCKSB4 4 1 LCKSB5 LCKSB5 5 1 LCKSB6 LCKSB6 6 1 LCKSB7 LCKSB7 7 1 LCKSB8 LCKSB8 8 1 LCKSB9 LCKSB9 9 1 LCKSB10 LCKSB10 10 1 LCKSB11 LCKSB11 11 1 LCKSB12 LCKSB12 12 1 LCKSB13 LCKSB13 13 1 LCKSB14 LCKSB14 14 1 LCKSB15 LCKSB15 15 1 LCKSB16 LCKSB16 16 1 LCKSB17 LCKSB17 17 1 LCKSB18 LCKSB18 18 1 LCKSB19 LCKSB19 19 1 LCKSB20 LCKSB20 20 1 LCKSB21 LCKSB21 21 1 LCKSB22 LCKSB22 22 1 LCKSB23 LCKSB23 23 1 LCKSB24 LCKSB24 24 1 LCKSB25 LCKSB25 25 1 LCKSB26 LCKSB26 26 1 LCKSB27 LCKSB27 27 1 LCKSB28 LCKSB28 28 1 LCKSB29 LCKSB29 29 1 LCKSB30 LCKSB30 30 1 LCKSB31 LCKSB31 31 1 LCKVTR2 LCKVTR2 MPCBB control register 0x14 0x20 read-write 0x00000000 LCKSB32 LCKSB32 0 1 LCKSB33 LCKSB33 1 1 LCKSB34 LCKSB34 2 1 LCKSB35 LCKSB35 3 1 LCKSB36 LCKSB36 4 1 LCKSB37 LCKSB37 5 1 LCKSB38 LCKSB38 6 1 LCKSB39 LCKSB39 7 1 LCKSB40 LCKSB40 8 1 LCKSB41 LCKSB41 9 1 LCKSB42 LCKSB42 10 1 LCKSB43 LCKSB43 11 1 LCKSB44 LCKSB44 12 1 LCKSB45 LCKSB45 13 1 LCKSB46 LCKSB46 14 1 LCKSB47 LCKSB47 15 1 LCKSB48 LCKSB48 16 1 LCKSB49 LCKSB49 17 1 LCKSB50 LCKSB50 18 1 LCKSB51 LCKSB51 19 1 LCKSB52 LCKSB52 20 1 LCKSB53 LCKSB53 21 1 LCKSB54 LCKSB54 22 1 LCKSB55 LCKSB55 23 1 LCKSB56 LCKSB56 24 1 LCKSB57 LCKSB57 25 1 LCKSB58 LCKSB58 26 1 LCKSB59 LCKSB59 27 1 LCKSB60 LCKSB60 28 1 LCKSB61 LCKSB61 29 1 LCKSB62 LCKSB62 30 1 LCKSB63 LCKSB63 31 1 64 0x4 0-63 VCTR%s VCTR%s MPCBBx vector register 0x100 0x20 read-write 0xFFFFFFFF B0 B0 0 1 B1 B1 1 1 B2 B2 2 1 B3 B3 3 1 B4 B4 4 1 B5 B5 5 1 B6 B6 6 1 B7 B7 7 1 B8 B8 8 1 B9 B9 9 1 B10 B10 10 1 B11 B11 11 1 B12 B12 12 1 B13 B13 13 1 B14 B14 14 1 B15 B15 15 1 B16 B16 16 1 B17 B17 17 1 B18 B18 18 1 B19 B19 19 1 B20 B20 20 1 B21 B21 21 1 B22 B22 22 1 B23 B23 23 1 B24 B24 24 1 B25 B25 25 1 B26 B26 26 1 B27 B27 27 1 B28 B28 28 1 B29 B29 29 1 B30 B30 30 1 B31 B31 31 1 SEC_GTZC_MPCBB2 SEC_GTZC_MPCBB2 SEC_GTZC 0x50033000 GTZC_TZIC GTZC_TZIC GTZC 0x40032800 0x0 0x400 registers GTZC TZIC secure global interrupt 8 IER1 IER1 TZIC interrupt enable register 1 0x0 0x20 read-write 0x00000000 TIM2IE TIM2IE 0 1 TIM3IE TIM3IE 1 1 TIM4IE TIM4IE 2 1 TIM5IE TIM5IE 3 1 TIM6IE TIM6IE 4 1 TIM7IE TIM7IE 5 1 WWDGIE WWDGIE 6 1 IWDGIE IWDGIE 7 1 SPI2IE SPI2IE 8 1 SPI3IE SPI3IE 9 1 USART2IE USART2IE 10 1 USART3IE USART3IE 11 1 UART4IE UART4IE 12 1 UART5IE UART5IE 13 1 I2C1IE I2C1IE 14 1 I2C2IE I2C2IE 15 1 I2C3IE I2C3IE 16 1 CRSIE CRSIE 17 1 DACIE DACIE 18 1 OPAMPIE OPAMPIE 19 1 LPTIM1IE LPTIM1IE 20 1 LPUART1IE LPUART1IE 21 1 I2C4IE I2C4IE 22 1 LPTIM2IE LPTIM2IE 23 1 LPTIM3IE LPTIM3IE 24 1 FDCAN1IE FDCAN1IE 25 1 USBFSIE USBFSIE 26 1 UCPD1IE UCPD1IE 27 1 VREFBUFIE VREFBUFIE 28 1 COMPIE COMPIE 29 1 TIM1IE TIM1IE 30 1 SPI1IE SPI1IE 31 1 IER2 IER2 TZIC interrupt enable register 2 0x4 0x20 read-write 0x00000000 TIM8IE TIM8IE 0 1 USART1IE USART1IE 1 1 TIM15IE TIM15IE 2 1 TIM16IE TIM16IE 3 1 TIM17IE TIM17IE 4 1 SAI1IE SAI1IE 5 1 SAI2IE SAI2IE 6 1 DFSDM1IE DFSDM1IE 7 1 CRCIE CRCIE 8 1 TSCIE TSCIE 9 1 ICACHEIE ICACHEIE 10 1 ADCIE ADCIE 11 1 AESIE AESIE 12 1 HASHIE HASHIE 13 1 RNGIE RNGIE 14 1 PKAIE PKAIE 15 1 SDMMC1IE SDMMC1IE 16 1 FMC_REGIE FMC_REGIE 17 1 OCTOSPI1_REGIE OCTOSPI1_REGIE 18 1 RTCIE RTCIE 19 1 PWRIE PWRIE 20 1 SYSCFGIE SYSCFGIE 21 1 DMA1IE DMA1IE 22 1 DMA2IE DMA2IE 23 1 DMAMUX1IE DMAMUX1IE 24 1 RCCIE RCCIE 25 1 FLASHIE FLASHIE 26 1 FLASH_REGIE FLASH_REGIE 27 1 EXTIIE EXTIIE 28 1 OTFDEC1IE OTFDEC1IE 29 1 IER3 IER3 TZIC interrupt enable register 3 0x8 0x20 read-write 0x00000000 TZSCIE TZSCIE 0 1 TZICIE TZICIE 1 1 MPCWM1IE MPCWM1IE 2 1 MPCWM2IE MPCWM2IE 3 1 MPCBB1IE MPCBB1IE 4 1 MPCBB1_REGIE MPCBB1_REGIE 5 1 MPCBB2IE MPCBB2IE 6 1 MPCBB2_REGIE MPCBB2_REGIE 7 1 SR1 SR1 TZIC interrupt status register 1 0x10 0x20 read-only 0x00000000 TIM2F TIM2F 0 1 TIM3F TIM3F 1 1 TIM4F TIM4F 2 1 TIM5F TIM5F 3 1 TIM6F TIM6F 4 1 TIM7F TIM7F 5 1 WWDGF WWDGF 6 1 IWDGF IWDGF 7 1 SPI2F SPI2F 8 1 SPI3F SPI3F 9 1 USART2F USART2F 10 1 USART3F USART3F 11 1 UART4F UART4F 12 1 UART5F UART5F 13 1 I2C1F I2C1F 14 1 I2C2F I2C2F 15 1 I2C3F I2C3F 16 1 CRSF CRSF 17 1 DACF DACF 18 1 OPAMPF OPAMPF 19 1 LPTIM1F LPTIM1F 20 1 LPUART1F LPUART1F 21 1 I2C4F I2C4F 22 1 LPTIM2F LPTIM2F 23 1 LPTIM3F LPTIM3F 24 1 FDCAN1F FDCAN1F 25 1 USBFSF USBFSF 26 1 UCPD1F UCPD1F 27 1 VREFBUFF VREFBUFF 28 1 COMPF COMPF 29 1 TIM1F TIM1F 30 1 SPI1F SPI1F 31 1 SR2 SR2 TZIC interrupt status register 2 0x14 0x20 read-write 0x00000000 TIM8F TIM8F 0 1 USART1F USART1F 1 1 TIM15F TIM15F 2 1 TIM16F TIM16F 3 1 TIM17F TIM17F 4 1 SAI1F SAI1F 5 1 SAI2F SAI2F 6 1 DFSDM1F DFSDM1F 7 1 CRCF CRCF 8 1 TSCF TSCF 9 1 ICACHEF ICACHEF 10 1 ADCF ADCF 11 1 AESF AESF 12 1 HASHF HASHF 13 1 RNGF RNGF 14 1 PKAF PKAF 15 1 SDMMC1F SDMMC1F 16 1 FMC_REGF FMC_REGF 17 1 OCTOSPI1_REGF OCTOSPI1_REGF 18 1 RTCF RTCF 19 1 PWRF PWRF 20 1 SYSCFGF SYSCFGF 21 1 DMA1F DMA1F 22 1 DMA2F DMA2F 23 1 DMAMUX1F DMAMUX1F 24 1 RCCF RCCF 25 1 FLASHF FLASHF 26 1 FLASH_REGF FLASH_REGF 27 1 EXTIF EXTIF 28 1 OTFDEC1F OTFDEC1F 29 1 SR3 SR3 TZIC interrupt status register 3 0x18 0x20 read-write 0x00000000 TZSCF TZSCF 0 1 TZICF TZICF 1 1 MPCWM1F MPCWM1F 2 1 MPCWM2F MPCWM2F 3 1 MPCBB1F MPCBB1F 4 1 MPCBB1_REGF MPCBB1_REGF 5 1 MPCBB2F MPCBB2F 6 1 MPCBB2_REGF MPCBB2_REGF 7 1 FCR1 FCR1 TZIC interrupt clear register 1 0x20 0x20 write-only 0x00000000 TIM2FC TIM2FC 0 1 TIM3FC TIM3FC 1 1 TIM4FC TIM4FC 2 1 TIM5FC TIM5FC 3 1 TIM6FC TIM6FC 4 1 TIM7FC TIM7FC 5 1 WWDGFC WWDGFC 6 1 IWDGFC IWDGFC 7 1 SPI2FC SPI2FC 8 1 SPI3FC SPI3FC 9 1 USART2FC USART2FC 10 1 USART3FC USART3FC 11 1 UART4FC UART4FC 12 1 UART5FC UART5FC 13 1 I2C1FC I2C1FC 14 1 I2C2FC I2C2FC 15 1 I2C3FC I2C3FC 16 1 CRSFC CRSFC 17 1 DACFC DACFC 18 1 OPAMPFC OPAMPFC 19 1 LPTIM1FC LPTIM1FC 20 1 LPUART1FC LPUART1FC 21 1 I2C4FC I2C4FC 22 1 LPTIM2FC LPTIM2FC 23 1 LPTIM3FC LPTIM3FC 24 1 FDCAN1FC FDCAN1FC 25 1 USBFSFC USBFSFC 26 1 UCPD1FC UCPD1FC 27 1 VREFBUFFC VREFBUFFC 28 1 COMPFC COMPFC 29 1 TIM1FC TIM1FC 30 1 SPI1FC SPI1FC 31 1 FCR2 ICR2 TZIC interrupt clear register 2 0x24 0x20 read-write 0x00000000 TIM8FC TIM8FC 0 1 USART1FC USART1FC 1 1 TIM15FC TIM15FC 2 1 TIM16FC TIM16FC 3 1 TIM17FC TIM17FC 4 1 SAI1FC SAI1FC 5 1 SAI2FC SAI2FC 6 1 DFSDM1FC DFSDM1FC 7 1 CRCFC CRCFC 8 1 TSCFC TSCFC 9 1 ICACHEFC ICACHEFC 10 1 ADCFC ADCFC 11 1 AESFC AESFC 12 1 HASHFC HASHFC 13 1 RNGFC RNGFC 14 1 PKAFC PKAFC 15 1 SDMMC1FC SDMMC1FC 16 1 FMC_REGFC FMC_REGFC 17 1 OCTOSPI1_REGFC OCTOSPI1_REGFC 18 1 RTCFC RTCFC 19 1 PWRFC PWRFC 20 1 SYSCFGFC SYSCFGFC 21 1 DMA1FC DMA1FC 22 1 DMA2FC DMA2FC 23 1 DMAMUX1FC DMAMUX1FC 24 1 RCCFC RCCFC 25 1 FLASHFC FLASHFC 26 1 FLASH_REGFC FLASH_REGFC 27 1 EXTIFC EXTIFC 28 1 OTFDEC1FC OTFDEC1FC 29 1 FCR3 FCR3 TZIC interrupt clear register 3 0x28 0x20 read-write 0x00000000 TZSCFC TZSCFC 0 1 TZICFC TZICFC 1 1 MPCWM1FC MPCWM1FC 2 1 MPCWM2FC MPCWM2FC 3 1 MPCBB1FC MPCBB1FC 4 1 MPCBB1_REGFC MPCBB1_REGFC 5 1 MPCBB2FC MPCBB2FC 6 1 MPCBB2_REGFC MPCBB2_REGFC 7 1 SEC_GTZC_TZIC 0x50032800 GTZC_TZSC GTZC_TZSC GTZC 0x40032400 0x0 0x400 registers CR CR TZSC control register 0x0 0x20 read-write 0x00000000 LCK LCK 0 1 SECCFGR1 SECCFGR1 TZSC secure configuration register 1 0x10 0x20 read-write 0x00000000 TIM2SEC TIM2SEC 0 1 TIM3SEC TIM3SEC 1 1 TIM4SEC TIM4SEC 2 1 TIM5SEC TIM5SEC 3 1 TIM6SEC TIM6SEC 4 1 TIM7SEC TIM7SEC 5 1 WWDGSEC WWDGSEC 6 1 IWDGSEC IWDGSEC 7 1 SPI2SEC SPI2SEC 8 1 SPI3SEC SPI3SEC 9 1 USART2SEC USART2SEC 10 1 USART3SEC USART3SEC 11 1 UART4SEC UART4SEC 12 1 UART5SEC UART5SEC 13 1 I2C1SEC I2C1SEC 14 1 I2C2SEC I2C2SEC 15 1 I2C3SEC I2C3SEC 16 1 CRSSEC CRSSEC 17 1 DACSEC DACSEC 18 1 OPAMPSEC OPAMPSEC 19 1 LPTIM1SEC LPTIM1SEC 20 1 LPUART1SEC LPUART1SEC 21 1 I2C4SEC I2C4SEC 22 1 LPTIM2SEC LPTIM2SEC 23 1 LPTIM3SEC LPTIM3SEC 24 1 FDCAN1SEC FDCAN1SEC 25 1 USBFSSEC USBFSSEC 26 1 UCPD1SEC UCPD1SEC 27 1 VREFBUFSEC VREFBUFSEC 28 1 COMPSEC COMPSEC 29 1 TIM1SEC TIM1SEC 30 1 SPI1SEC SPI1SEC 31 1 SECCFGR2 SECCFGR2 TZSC secure configuration register 2 0x14 0x20 read-write 0x00000000 TIM8SEC TIM8SEC 0 1 USART1SEC USART1SEC 1 1 TIM15SEC TIM15SEC 2 1 TIM16SEC TIM16SEC 3 1 TIM17SEC TIM17SEC 4 1 SAI1SEC SAI1SEC 5 1 SAI2SEC SAI2SEC 6 1 DFSDM1SEC DFSDM1SEC 7 1 CRCSEC CRCSEC 8 1 TSCSEC TSCSEC 9 1 ICACHESEC ICACHESEC 10 1 ADCSEC ADCSEC 11 1 AESSEC AESSEC 12 1 HASHSEC HASHSEC 13 1 RNGSEC RNGSEC 14 1 PKASEC PKASEC 15 1 SDMMC1SEC SDMMC1SEC 16 1 FSMC_REGSEC FSMC_REGSEC 17 1 OCTOSPI1_REGSEC OCTOSPI1_REGSEC 18 1 PRIVCFGR1 PRIVCFGR1 TZSC privilege configuration register 1 0x20 0x20 read-write 0x00000000 TIM2PRIV TIM2PRIV 0 1 TIM3PRIV TIM3PRIV 1 1 TIM4PRIV TIM4PRIV 2 1 TIM5PRIV TIM5PRIV 3 1 TIM6PRIV TIM6PRIV 4 1 TIM7PRIV TIM7PRIV 5 1 WWDGPRIV WWDGPRIV 6 1 IWDGPRIV IWDGPRIV 7 1 SPI2PRIV SPI2PRIV 8 1 SPI3PRIV SPI3PRIV 9 1 USART2PRIV USART2PRIV 10 1 USART3PRIV USART3PRIV 11 1 UART4PRIV UART4PRIV 12 1 UART5PRIV UART5PRIV 13 1 I2C1PRIV I2C1PRIV 14 1 I2C2PRIV I2C2PRIV 15 1 I2C3PRIV I2C3PRIV 16 1 CRSPRIV CRSPRIV 17 1 DACPRIV DACPRIV 18 1 OPAMPPRIV OPAMPPRIV 19 1 LPTIM1PRIV LPTIM1PRIV 20 1 LPUART1PRIV LPUART1PRIV 21 1 I2C4PRIV I2C4PRIV 22 1 LPTIM2PRIV LPTIM2PRIV 23 1 LPTIM3PRIV LPTIM3PRIV 24 1 FDCAN1PRIV FDCAN1PRIV 25 1 USBFSPRIV USBFSPRIV 26 1 UCPD1PRIV UCPD1PRIV 27 1 VREFBUFPRIV VREFBUFPRIV 28 1 COMPPRIV COMPPRIV 29 1 TIM1PRIV TIM1PRIV 30 1 SPI1PRIV SPI1PRIV 31 1 PRIVCFGR2 PRIVCFGR2 TZSC privilege configuration register 2 0x24 0x20 read-write 0x00000000 TIM8PRIV TIM8PRIV 0 1 USART1PRIV USART1PRIV 1 1 TIM15PRIV TIM15PRIV 2 1 TIM16PRIV TIM16PRIV 3 1 TIM17PRIV TIM17PRIV 4 1 SAI1PRIV SAI1PRIV 5 1 SAI2PRIV SAI2PRIV 6 1 DFSDM1PRIV DFSDM1PRIV 7 1 CRCPRIV CRCPRIV 8 1 TSCPRIV TSCPRIV 9 1 ICACHEPRIV ICACHEPRIV 10 1 ADCPRIV ADCPRIV 11 1 AESPRIV AESPRIV 12 1 HASHPRIV HASHPRIV 13 1 RNGPRIV RNGPRIV 14 1 PKAPRIV PKAPRIV 15 1 SDMMC1PRIV SDMMC1PRIV 16 1 FSMC_REGPRIV FSMC_REGPRIV 17 1 OCTOSPI1_REGPRIV OCTOSPI1_REGRIV 18 1 MPCWM1_NSWMR1 MPCWM1_NSWMR1 TZSC external memory non-secure watermark register 1 0x30 0x20 read-write 0x00000000 NSWM1STRT NSWM1STRT 0 11 NSWM1LGTH NSWM1LGTH 16 12 MPCWM1_NSWMR2 MPCWM1_NSWMR2 TZSC external memory non-secure watermark register 1 0x34 0x20 read-write 0x00000000 NSWM2STRT NSWM2STRT 0 11 NSWM2LGTH NSWM2LGTH 16 12 MPCWM2_NSWMR1 MPCWM2_NSWMR1 TZSC external memory non-secure watermark register 1 0x38 0x20 read-write 0x00000000 NSWM1STRT NSWM1STRT 0 11 NSWM1LGTH NSWM1LGTH 16 12 MPCWM3_NSWMR1 MPCWM3_NSWMR1 TZSC external memory non-secure watermark register 2 0x40 0x20 read-write 0x00000000 NSWM2STRT NSWM2STRT 0 11 NSWM2LGTH NSWM2LGTH 16 12 MPCWM2_NSWMR2 MPCWM2_NSWMR2 TZSC external memory non-secure watermark register 2 0x3C 0x20 read-write 0x00000000 NSWM2STRT NSWM2STRT 0 11 NSWM2LGTH NSWM2LGTH 16 12 SEC_GTZC_TZSC 0x50032400 HASH Hash processor HASH 0x420C0400 0x0 0x400 registers HASH HASH interrupt 96 CR CR control register 0x0 0x20 0x00000000 INIT Initialize message digest calculation 2 1 write-only DMAE DMA enable 3 1 read-write DATATYPE Data type selection 4 2 read-write MODE Mode selection 6 1 read-write ALGO0 Algorithm selection 7 1 read-write NBW Number of words already pushed 8 4 read-only DINNE DIN not empty 12 1 read-only MDMAT Multiple DMA Transfers 13 1 read-write LKEY Long key selection 16 1 read-write ALGO1 Algorithm selection 18 1 read-write DIN DIN data input register 0x4 0x20 read-write 0x00000000 DATAIN Data input 0 32 STR STR start register 0x8 0x20 0x00000000 DCAL Digest calculation 8 1 read-write NBLW Number of valid bits in the last word of the message 0 5 read-write HRA0 HRA0 HASH aliased digest register 0 0xC 0x20 read-only 0x00000000 H0 H0 0 32 HRA1 HRA1 HASH aliased digest register 1 0x10 0x20 read-only 0x00000000 H1 H1 0 32 HRA2 HRA2 HASH aliased digest register 2 0x14 0x20 read-only 0x00000000 H2 H2 0 32 HRA3 HRA3 HASH aliased digest register 3 0x18 0x20 read-only 0x00000000 H3 H3 0 32 HRA4 HRA4 HASH aliased digest register 4 0x1C 0x20 read-only 0x00000000 H4 H4 0 32 HR0 HR0 digest register 0 0x310 0x20 read-only 0x00000000 H0 H0 0 32 HR1 HR1 digest register 1 0x314 0x20 read-only 0x00000000 H1 H1 0 32 HR2 HR2 digest register 4 0x318 0x20 read-only 0x00000000 H2 H2 0 32 HR3 HR3 digest register 3 0x31C 0x20 read-only 0x00000000 H3 H3 0 32 HR4 HR4 digest register 4 0x320 0x20 read-only 0x00000000 H4 H4 0 32 HR5 HR5 supplementary digest register 5 0x324 0x20 read-only 0x00000000 H5 H5 0 32 HR6 HR6 supplementary digest register 6 0x328 0x20 read-only 0x00000000 H6 H6 0 32 HR7 HR7 supplementary digest register 7 0x32C 0x20 read-only 0x00000000 H7 H7 0 32 IMR IMR interrupt enable register 0x20 0x20 read-write 0x00000000 DCIE Digest calculation completion interrupt enable 1 1 DINIE Data input interrupt enable 0 1 SR SR status register 0x24 0x20 0x00000001 BUSY Busy bit 3 1 read-only DMAS DMA Status 2 1 read-only DCIS Digest calculation completion interrupt status 1 1 read-write DINIS Data input interrupt status 0 1 read-write CSR0 CSR0 context swap registers 0xF8 0x20 read-write 0x00000002 CSR0 CSR0 0 32 CSR1 CSR1 context swap registers 0xFC 0x20 read-write 0x00000000 CSR1 CSR1 0 32 CSR2 CSR2 context swap registers 0x100 0x20 read-write 0x00000000 CSR2 CSR2 0 32 CSR3 CSR3 context swap registers 0x104 0x20 read-write 0x00000000 CSR3 CSR3 0 32 CSR4 CSR4 context swap registers 0x108 0x20 read-write 0x00000000 CSR4 CSR4 0 32 CSR5 CSR5 context swap registers 0x10C 0x20 read-write 0x00000000 CSR5 CSR5 0 32 CSR6 CSR6 context swap registers 0x110 0x20 read-write 0x00000000 CSR6 CSR6 0 32 CSR7 CSR7 context swap registers 0x114 0x20 read-write 0x00000000 CSR7 CSR7 0 32 CSR8 CSR8 context swap registers 0x118 0x20 read-write 0x00000000 CSR8 CSR8 0 32 CSR9 CSR9 context swap registers 0x11C 0x20 read-write 0x00000000 CSR9 CSR9 0 32 CSR10 CSR10 context swap registers 0x120 0x20 read-write 0x00000000 CSR10 CSR10 0 32 CSR11 CSR11 context swap registers 0x124 0x20 read-write 0x00000000 CSR11 CSR11 0 32 CSR12 CSR12 context swap registers 0x128 0x20 read-write 0x00000000 CSR12 CSR12 0 32 CSR13 CSR13 context swap registers 0x12C 0x20 read-write 0x00000000 CSR13 CSR13 0 32 CSR14 CSR14 context swap registers 0x130 0x20 read-write 0x00000000 CSR14 CSR14 0 32 CSR15 CSR15 context swap registers 0x134 0x20 read-write 0x00000000 CSR15 CSR15 0 32 CSR16 CSR16 context swap registers 0x138 0x20 read-write 0x00000000 CSR16 CSR16 0 32 CSR17 CSR17 context swap registers 0x13C 0x20 read-write 0x00000000 CSR17 CSR17 0 32 CSR18 CSR18 context swap registers 0x140 0x20 read-write 0x00000000 CSR18 CSR18 0 32 CSR19 CSR19 context swap registers 0x144 0x20 read-write 0x00000000 CSR19 CSR19 0 32 CSR20 CSR20 context swap registers 0x148 0x20 read-write 0x00000000 CSR20 CSR20 0 32 CSR21 CSR21 context swap registers 0x14C 0x20 read-write 0x00000000 CSR21 CSR21 0 32 CSR22 CSR22 context swap registers 0x150 0x20 read-write 0x00000000 CSR22 CSR22 0 32 CSR23 CSR23 context swap registers 0x154 0x20 read-write 0x00000000 CSR23 CSR23 0 32 CSR24 CSR24 context swap registers 0x158 0x20 read-write 0x00000000 CSR24 CSR24 0 32 CSR25 CSR25 context swap registers 0x15C 0x20 read-write 0x00000000 CSR25 CSR25 0 32 CSR26 CSR26 context swap registers 0x160 0x20 read-write 0x00000000 CSR26 CSR26 0 32 CSR27 CSR27 context swap registers 0x164 0x20 read-write 0x00000000 CSR27 CSR27 0 32 CSR28 CSR28 context swap registers 0x168 0x20 read-write 0x00000000 CSR28 CSR28 0 32 CSR29 CSR29 context swap registers 0x16C 0x20 read-write 0x00000000 CSR29 CSR29 0 32 CSR30 CSR30 context swap registers 0x170 0x20 read-write 0x00000000 CSR30 CSR30 0 32 CSR31 CSR31 context swap registers 0x174 0x20 read-write 0x00000000 CSR31 CSR31 0 32 CSR32 CSR32 context swap registers 0x178 0x20 read-write 0x00000000 CSR32 CSR32 0 32 CSR33 CSR33 context swap registers 0x17C 0x20 read-write 0x00000000 CSR33 CSR33 0 32 CSR34 CSR34 context swap registers 0x180 0x20 read-write 0x00000000 CSR34 CSR34 0 32 CSR35 CSR35 context swap registers 0x184 0x20 read-write 0x00000000 CSR35 CSR35 0 32 CSR36 CSR36 context swap registers 0x188 0x20 read-write 0x00000000 CSR36 CSR36 0 32 CSR37 CSR37 context swap registers 0x18C 0x20 read-write 0x00000000 CSR37 CSR37 0 32 CSR38 CSR38 context swap registers 0x190 0x20 read-write 0x00000000 CSR38 CSR38 0 32 CSR39 CSR39 context swap registers 0x194 0x20 read-write 0x00000000 CSR39 CSR39 0 32 CSR40 CSR40 context swap registers 0x198 0x20 read-write 0x00000000 CSR40 CSR40 0 32 CSR41 CSR41 context swap registers 0x19C 0x20 read-write 0x00000000 CSR41 CSR41 0 32 CSR42 CSR42 context swap registers 0x1A0 0x20 read-write 0x00000000 CSR42 CSR42 0 32 CSR43 CSR43 context swap registers 0x1A4 0x20 read-write 0x00000000 CSR43 CSR43 0 32 CSR44 CSR44 context swap registers 0x1A8 0x20 read-write 0x00000000 CSR44 CSR44 0 32 CSR45 CSR45 context swap registers 0x1AC 0x20 read-write 0x00000000 CSR45 CSR45 0 32 CSR46 CSR46 context swap registers 0x1B0 0x20 read-write 0x00000000 CSR46 CSR46 0 32 CSR47 CSR47 context swap registers 0x1B4 0x20 read-write 0x00000000 CSR47 CSR47 0 32 CSR48 CSR48 context swap registers 0x1B8 0x20 read-write 0x00000000 CSR48 CSR48 0 32 CSR49 CSR49 context swap registers 0x1BC 0x20 read-write 0x00000000 CSR49 CSR49 0 32 CSR50 CSR50 context swap registers 0x1C0 0x20 read-write 0x00000000 CSR50 CSR50 0 32 CSR51 CSR51 context swap registers 0x1C4 0x20 read-write 0x00000000 CSR51 CSR51 0 32 CSR52 CSR52 context swap registers 0x1C8 0x20 read-write 0x00000000 CSR52 CSR52 0 32 CSR53 CSR53 context swap registers 0x1CC 0x20 read-write 0x00000000 CSR53 CSR53 0 32 SEC_HASH 0x520C0400 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 55 I2C1_ER I2C1 error interrupt 56 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 TXIE TX Interrupt enable 1 1 RXIE RX Interrupt enable 2 1 ADDRIE Address match interrupt enable (slave only) 3 1 NACKIE Not acknowledge received interrupt enable 4 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 ERRIE Error interrupts enable 7 1 DNF Digital noise filter 8 4 ANFOFF Analog noise filter OFF 12 1 TXDMAEN DMA transmission requests enable 14 1 RXDMAEN DMA reception requests enable 15 1 SBC Slave byte control 16 1 NOSTRETCH Clock stretching disable 17 1 WUPEN Wakeup from STOP enable 18 1 GCEN General call enable 19 1 SMBHEN SMBus Host address enable 20 1 SMBDEN SMBus Device Default address enable 21 1 ALERTEN SMBUS alert enable 22 1 PECEN PEC enable 23 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 AUTOEND Automatic end mode (master mode) 25 1 RELOAD NBYTES reload mode 24 1 NBYTES Number of bytes 16 8 NACK NACK generation (slave mode) 15 1 STOP Stop generation (master mode) 14 1 START Start generation 13 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 ADD10 10-bit addressing mode (master mode) 11 1 RD_WRN Transfer direction (master mode) 10 1 SADD Slave address bit (master mode) 0 10 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 OA1MODE Own Address 1 10-bit mode 10 1 OA1EN Own Address 1 enable 15 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 OA2MSK Own Address 2 masks 8 3 OA2EN Own Address 2 enable 15 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 SCLH SCL high period (master mode) 8 8 SDADEL Data hold time 16 4 SCLDEL Data setup time 20 4 PRESC Timing prescaler 28 4 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 TIDLE Idle clock timeout detection 12 1 TIMOUTEN Clock timeout enable 15 1 TIMEOUTB Bus timeout B 16 12 TEXTEN Extended clock timeout enable 31 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only DIR Transfer direction (Slave mode) 16 1 read-only BUSY Bus busy 15 1 read-only ALERT SMBus alert 13 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only PECERR PEC Error in reception 11 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only TCR Transfer Complete Reload 7 1 read-only TC Transfer Complete (master mode) 6 1 read-only STOPF Stop detection flag 5 1 read-only NACKF Not acknowledge received flag 4 1 read-only ADDR Address matched (slave mode) 3 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only TXIS Transmit interrupt status (transmitters) 1 1 read-write TXE Transmit data register empty (transmitters) 0 1 read-write ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 TIMOUTCF Timeout detection flag clear 12 1 PECCF PEC Error flag clear 11 1 OVRCF Overrun/Underrun flag clear 10 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 STOPCF Stop detection flag clear 5 1 NACKCF Not Acknowledge flag clear 4 1 ADDRCF Address Matched flag clear 3 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 57 I2C2_ER I2C2 error interrupt 58 I2C3 0x40005C00 I2C3_EV I2C3 event interrupt 88 I2C3_ER I2C3 error interrupt 89 I2C4 0x40008400 I2C4_ER I2C4 error interrupt 100 I2C4_EV I2C4 event interrupt 101 SEC_I2C1 0x50005400 SEC_I2C2 0x50005800 SEC_I2C3 0x50005C00 SEC_I2C4 0x50008400 ICACHE ICache ICache 0x40030400 0x0 0x400 registers ICACHE ICACHE 107 CR CR ICACHE control register 0x0 0x20 read-write 0x00000004 EN EN 0 1 CACHEINV CACHEINV 1 1 WAYSEL WAYSEL 2 1 HITMEN HITMEN 16 1 MISSMEN MISSMEN 17 1 HITMRST HITMRST 18 1 MISSMRST MISSMRST 19 1 SR SR ICACHE status register 0x4 0x20 read-only 0x00000001 BUSYF BUSYF 0 1 BSYENDF BSYENDF 1 1 ERRF ERRF 2 1 IER IER ICACHE interrupt enable register 0x8 0x20 read-write 0x00000000 BSYENDIE BSYENDIE 1 1 ERRIE ERRIE 2 1 FCR FCR ICACHE flag clear register 0xC 0x20 write-only 0x00000000 CBSYENDF CBSYENDF 1 1 CERRF CERRF 2 1 HMONR HMONR ICACHE hit monitor register 0x10 0x20 read-only 0x00000000 HITMON HITMON 0 32 MMONR MMONR ICACHE miss monitor register 0x14 0x20 read-only 0x00000000 MISSMON MISSMON 0 16 4 0x4 0-3 CRR%s CRR%s ICACHE region configuration register 0x20 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 SEC_ICache 0x50030400 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x10 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 0x10 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x10 read-only 0x00000000 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x10 read-write 0x00000FFF WIN Watchdog counter window value 0 12 SEC_IWDG 0x50003000 LPTIM1 Low power timer LPTIM 0x40007C00 0x0 0x400 registers LPTIM1 LP TIM1 interrupt 67 LPTIM2 LP TIM2 interrupt 68 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DOWN Counter direction change up to down 6 1 DOWNR Set Counter direction change up to down 1 UP Counter direction change down to up 5 1 UPR Set Counter direction change down to up 1 ARROK Autoreload register update OK 4 1 ARROKR Set Autoreload register update OK 1 CMPOK Compare register update OK 3 1 CMPOKR Set Compare register update OK 1 EXTTRIG External trigger edge event 2 1 EXTTRIGR Set External trigger edge event 1 ARRM Autoreload match 1 1 ARRMR Set Autoreload match 1 CMPM Compare match 0 1 CMPMR Set Compare match 1 UE LPTIM update event occurred 7 1 UER Set LPTIM update event occurred 1 REPOK Repetition register update Ok 8 1 REPOKR Set Repetition register update OK 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DOWNCF Direction change to down Clear Flag 6 1 DOWNCFW Clear Direction change to down Clear Flag 1 UPCF Direction change to UP Clear Flag 5 1 UPCFW Clear Direction change to up Clear Flag 1 ARROKCF Autoreload register update OK Clear Flag 4 1 ARROKCFW Clear Autoreload register update OK Clear Flag 1 CMPOKCF Compare register update OK Clear Flag 3 1 CMPOKCFW Clear Compare register update OK Clear Flag 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 EXTTRIGCFW Clear External trigger valid edge Clear Flag 1 ARRMCF Autoreload match Clear Flag 1 1 ARRMCFW Clear Autoreload match Clear Flag 1 CMPMCF compare match Clear Flag 0 1 CMPMCFW Clear Compare match Clear Flag 1 UECF Update event clear flag 7 1 UECFW Clear Clear update event flag 1 REPOKCF Repetition register update OK clear flag 8 1 REPOKCFW Clear Clear REPOK flag 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 DOWNIE Direction change to down Interrupt Enable 6 1 DOWNIE Disabled DOWN interrupt disabled 0 Enabled DOWN interrupt enabled 1 UPIE Direction change to UP Interrupt Enable 5 1 UPIE Disabled UP interrupt disabled 0 Enabled UP interrupt enabled 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 ARROKIE Disabled ARROK interrupt disabled 0 Enabled ARROK interrupt enabled 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 CMPOKIE Disabled CMPOK interrupt disabled 0 Enabled CMPOK interrupt enabled 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 EXTTRIGIE Disabled EXTTRIG interrupt disabled 0 Enabled EXTTRIG interrupt enabled 1 ARRMIE Autoreload match Interrupt Enable 1 1 ARRMIE Disabled ARRM interrupt disabled 0 Enabled ARRM interrupt enabled 1 CMPMIE Compare match Interrupt Enable 0 1 CMPMIE Disabled CMPM interrupt disabled 0 Enabled CMPM interrupt enabled 1 UEIE Update event interrupt enable 7 1 UEIE Disabled Update event interrupt disabled 0 Enabled Update event interrupt enabled 1 REPOKIE REPOKIE 8 1 REPOKIE Disabled Repetition register update OK interrupt disabled 0 Enabled Repetition register update OK interrupt enabled 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 ENC Disabled Encoder mode disabled 0 Enabled Encoder mode enabled 1 COUNTMODE counter mode enabled 23 1 COUNTMODE Internal The counter is incremented following each internal clock pulse 0 External The counter is incremented following each valid clock pulse on the LPTIM external Input1 1 PRELOAD Registers update mode 22 1 PRELOAD Immediate Registers are updated after each APB bus write access 0 EndOfPeriod Registers are updated at the end of the current LPTIM period 1 WAVPOL Waveform shape polarity 21 1 WAVPOL Positive The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 0 Negative The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 1 WAVE Waveform shape 20 1 WAVE Inactive Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit) 0 Active Activate the Set-once mode 1 TIMOUT Timeout enable 19 1 TIMOUT Disabled A trigger event arriving when the timer is already started will be ignored 0 Enabled A trigger event arriving when the timer is already started will reset and restart the counter 1 TRIGEN Trigger enable and polarity 17 2 TRIGEN SW Software trigger (counting start is initiated by software) 0 RisingEdge Rising edge is the active edge 1 FallingEdge Falling edge is the active edge 2 BothEdges Both edges are active edges 3 TRIGSEL Trigger selector 13 3 TRIGSEL Trig0 lptim_ext_trig0 0 Trig1 lptim_ext_trig1 1 Trig2 lptim_ext_trig2 2 Trig3 lptim_ext_trig3 3 Trig4 lptim_ext_trig4 4 Trig5 lptim_ext_trig5 5 Trig6 lptim_ext_trig6 6 Trig7 lptim_ext_trig7 7 PRESC Clock prescaler 9 3 PRESC Div1 /1 0 Div2 /2 1 Div4 /4 2 Div8 /8 3 Div16 /16 4 Div32 /32 5 Div64 /64 6 Div128 /128 7 TRGFLT Configurable digital filter for trigger 6 2 TRGFLT Immediate Any trigger active level change is considered as a valid trigger 0 Clocks2 Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger 1 Clocks4 Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger 2 Clocks8 Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger 3 CKFLT Configurable digital filter for external clock 3 2 CKFLT Immediate Any external clock signal level change is considered as a valid transition 0 Clocks2 External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition 1 Clocks4 External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition 2 Clocks8 External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition 3 CKPOL Clock Polarity 1 2 CKPOL RisingEdge The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active. 0 FallingEdge The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active. 1 BothEdges Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active. 2 CKSEL Clock selector 0 1 CKSEL Internal LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 0 External LPTIM is clocked by an external clock source through the LPTIM external Input1 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 CNTSTRT Timer start in continuous mode 2 1 CNTSTRTW write Start Timer start in Continuous mode 1 SNGSTRT LPTIM start in single mode 1 1 SNGSTRTW write Start LPTIM start in Single mode 1 ENABLE LPTIM Enable 0 1 ENABLE Disabled LPTIM is disabled 0 Enabled LPTIM is enabled 1 COUNTRST Counter reset 4 1 COUNTRSTR read Idle Triggering of reset is possible 0 Busy Reset in progress, do not write 1 to this field 1 COUNTRSTW write Reset Trigger synchronous reset of CNT (3 LPTimer core clock cycles) 1 RSTARE Reset after read enable 3 1 RSTARE Disabled CNT Register reads do not trigger reset 0 Enabled CNT Register reads trigger reset of LPTIM 1 CMP CMP Compare Register 0x14 0x20 read-write 0x00000000 CMP Compare value 0 16 0 65535 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 0 65535 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 0 65535 OR OR LPTIM option register 0x20 0x20 read-write 0x00000000 OR_0 Option register bit 0 0 1 OR_1 Option register bit 1 1 1 RCR RCR LPTIM repetition register 0x28 0x20 read-write 0x00000000 REP Repetition register value 0 8 0 255 LPTIM2 0x40009400 LPTIM3 0x40009800 LPTIM3 LPTIM3 98 SEC_LPTIM1 0x50007C00 SEC_LPTIM2 0x50009400 SEC_LPTIM3 0x50009800 LPUART1 Universal synchronous asynchronous receiver transmitter USART 0x40008000 0x0 0x400 registers LPUART1 LPUART1 global interrupt 66 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 M1 Word length 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 DEAT DEAT 21 5 0 31 DEDT DEDT 16 5 0 31 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 FIFOEN FIFOEN 29 1 FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFEIE 30 1 TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFFIE 31 1 RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop2 2 stop bit 2 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 TXFTIE TXFTIE 23 1 TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 RXFTCFG RXFTCFG 25 3 RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFTIE 28 1 RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFTCFG 29 3 TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR BRR 0 20 0 1048575 RQR RQR Request register 0x18 0x20 write-only 0x00000000 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 TXFRQ TXFRQ 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 TXE TXE 7 1 TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXNE RXNE 5 1 RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NF NF 2 1 NF NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 TXFE TXFE 23 1 TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFF 24 1 RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 RXFT RXFT 26 1 RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFT 27 1 TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 PRESC PRESC PRESC 0x2C 0x20 read-write 0x00000000 PRESCALER PRESCALER 0 4 PRESCALER Div1 /1 0 Div2 /2 1 Div4 /4 2 Div6 /6 3 Div8 /8 4 Div10 /10 5 Div12 /12 6 Div16 /16 7 Div32 /32 8 Div64 /64 9 Div128 /128 10 Div256 /256 11 SEC_LPUART1 0x50008000 OCTOSPI1 OctoSPI OctoSPI 0x44021000 0x0 0x400 registers OCTOSPI1 OCTOSPI1 global interrupt 76 CR CR control register 0x0 0x20 read-write 0x00000000 FMODE Functional mode 28 2 FMODE IndirectWrite Indirect-write mode 0 IndirectRead Indirect-read mode 1 AutomaticPolling Automatic status-polling mode 2 MemoryMapped Memory-mapped mode 3 PMM Polling match mode 23 1 PMM ANDMatchMode AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register 0 ORMatchmode OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register 1 APMS Automatic poll mode stop 22 1 APMS Running Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI 0 StopMatch Automatic status-polling mode stops as soon as there is a match 1 TEIE Transfer error interrupt enable 16 1 TEIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TOIE TimeOut interrupt enable 20 1 SMIE Status match interrupt enable 19 1 FTIE FIFO threshold interrupt enable 18 1 TCIE Transfer complete interrupt enable 17 1 FTHRES IFO threshold level 8 5 0 31 FSEL FLASH memory selection 7 1 FSEL FLASH1 FLASH 1 selected (data exchanged over IO[3:0]) 0 FLASH2 FLASH 2 selected (data exchanged over IO[7:4]) 1 DMM Dual-memory configuration 6 1 DMM Disabled Dual-quad configuration disabled 0 Enabled Dual-quad configuration enabled 1 TCEN Timeout counter enable 3 1 TCEN Disabled Timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in Memory-mapped mode 0 Enabled Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity 1 DMAEN DMA enable 2 1 DMAEN Disabled DMA disabled for Indirect mode 0 Enabled DMA enabled for Indirect mode 1 ABORT Abort request 1 1 ABORT NotRequested No abort requested 0 Requested Abort requested 1 EN Enable 0 1 EN Disabled OCTOSPI disabled 0 Enabled OCTOSPI enabled 1 DCR1 DCR1 device configuration register 0x8 0x20 read-write 0x00000000 CKMODE Mode 0 / mode 3 0 1 CKMODE Mode0 CLK must stay low while NCS is high (chip-select released). This is referred to as Mode 0 0 Mode3 CLK must stay high while NCS is high (chip-select released). This is referred to as Mode 3 1 FRCK Free running clock 1 1 FRCK Disabled CLK is not free running 0 Enabled CLK is free running (always provided) 1 DLYBYP Delay block bypass 3 1 DLYBYP DelayBlockEnabled The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral) 0 DelayBlockBypassed The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. The delay is shorter than when the delay block is not bypassed, even with the delay value set to minimum value in delay block 1 CSHT Chip-select high time 8 3 0 7 DEVSIZE Device size 16 5 0 31 MTYP Memory type 24 3 MTYP MicronMode Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes 0 MacronixMode Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes 1 StandardMode Standard Mode 2 MacronixRamMode Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping 3 HyperBusMemoryMode HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected 4 HyperBusMode HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used 5 DCR2 DCR2 device configuration register 2 0xC 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 8 0 255 WRAPSIZE Wrap size 16 3 WRAPSIZE NoWrappingSupport Wrapped reads are not supported by the memory 0 WrappingSize16 External memory supports wrap size of 16 bytes 2 WrappingSize32 External memory supports wrap size of 32 bytes 3 WrappingSize64 External memory supports wrap size of 64 bytes 4 WrappingSize128 External memory supports wrap size of 128 bytes 5 DCR3 DCR3 device configuration register 3 0x10 0x20 read-write 0x00000000 CSBOUND CS boundary 16 5 0 31 DCR4 DCR4 device configuration register 4 0x14 0x20 read-write 0x00000000 REFRESH REFRESH 0 32 0 4294967295 SR SR status register 0x20 0x20 read-write 0x00000000 TEF Transfer error flag 0 1 TEF Cleared This bit is cleared by writing 1 to CTEF 0 InvalidAddressAccessed This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode 1 TCF Transfer complete flag 1 1 TCF Cleared This bit is cleared by writing 1 to CTCF 0 TransferCompleted This bit is set when the programmed number of data has been transferred 1 FTF FIFO threshold flag 2 1 FTF Cleared It is cleared automatically as soon as the threshold condition is no longer true 0 ThresholdReached This bit is set when the FIFO threshold has been reached 1 SMF Status match flag 3 1 SMF Cleared It is cleared by writing 1 to CSMF 0 Matched This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (OCTOSPI_PSMAR) 1 TOF Timeout flag 4 1 TOF Cleared This bit is cleared by writing 1 to CTOF 0 Timeout This bit is set when timeout occurs 1 BUSY BUSY 5 1 BUSY Cleared This bit is cleared automatically when the operation with the external device is finished and the FIFO is empty 0 Busy This bit is set when an operation is ongoing 1 FLEVEL FIFO level 8 6 0 63 FCR FCR flag clear register 0x24 0x20 write-only 0x00000000 CTEF Clear transfer error flag 0 1 CTEF Clear Writing 1 clears the TEF flag in the OCTOSPI_SR register 1 CTCF Clear transfer complete flag 1 1 CTCF Clear Writing 1 clears the TCF flag in the OCTOSPI_SR register 1 CSMF Clear status match flag 3 1 CSMF Clear Writing 1 clears the SMF flag in the OCTOSPI_SR register 1 CTOF Clear timeout flag 4 1 CTOF Clear Writing 1 clears the TOF flag in the OCTOSPI_SR register 1 DLR DLR data length register 0x40 0x20 read-write 0x00000000 DL Data length 0 32 0 4294967295 AR AR address register 0x48 0x20 read-write 0x00000000 ADDRESS ADDRESS 0 32 0 4294967295 DR DR data register 0x50 0x20 read-write 0x00000000 DATA Data 0 32 0 4294967295 PSMKR PSMKR polling status mask register 0x80 0x20 read-write 0x00000000 MASK Status mask 0 32 0 4294967295 PSMAR PSMAR polling status match register 0x88 0x20 read-write 0x00000000 MATCH Status match 0 32 0 4294967295 PIR PIR polling interval register 0x90 0x20 read-write 0x00000000 INTERVAL Polling interval 0 16 0 65535 CCR CCR communication configuration 0x100 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR Instruction double transfer rate 3 1 IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE Instruction size 4 2 ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE Address mode 8 3 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR Address double transfer rate 11 1 ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE Address size 12 2 ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE Alternate byte mode 16 3 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR Alternate bytes double transfer rate 19 1 ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE Alternate bytes size 20 2 ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE Data mode 24 3 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR Alternate bytes double transfer rate 27 1 DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQS enable 29 1 DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 SIOO Send instruction only once mode 31 1 SIOO SendEveryTransaction Send instruction on every transaction 0 SendOnlyFirstCmd Send instruction only for the first command 1 TCR TCR timing configuration register 0x108 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 0 31 DHQC Delay hold quarter cycle 28 1 DHQC NoDelay No delay hold 0 QuarterCycleHold 1/4 cycle hold 1 SSHIFT Sample shift 30 1 SSHIFT NoShift No shift 0 HalfCycleShift 1/2 cycle shift 1 IR IR instruction register 0x110 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 0 4294967295 ABR ABR alternate bytes register 0x120 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 0 4294967295 LPTR LPTR low-power timeout register 0x130 0x20 read-write 0x00000000 TIMEOUT Timeout period 0 16 0 65535 WPCCR WPCCR wrap communication configuration register 0x140 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR Instruction double transfer rate 3 1 IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE Instruction size 4 2 ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE Address mode 8 3 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR Address double transfer rate 11 1 ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE Address size 12 2 ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE Alternate byte mode 16 3 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR Alternate bytes double transfer rate 19 1 ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE Alternate bytes size 20 2 ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE Data mode 24 3 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR alternate bytes double transfer rate 27 1 DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQS enable 29 1 DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 WPTCR WPTCR wrap timing configuration register 0x148 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 0 31 DHQC Delay hold quarter cycle 28 1 DHQC NoDelay No delay hold 0 QuarterCycleHold 1/4 cycle hold 1 SSHIFT Sample shift 30 1 SSHIFT NoShift No shift 0 HalfCycleShift 1/2 cycle shift 1 WPIR WPIR wrap instruction register 0x150 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 0 4294967295 WPABR WPABR wrap alternate bytes register 0x160 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 0 4294967295 HLCR HLCR HyperBus latency configuration register 0x200 0x20 read-write 0x00000000 LM Latency mode 0 1 LM Variable Variable initial latency 0 Fixed Fixed latency 1 WZL Write zero latency 1 1 WZL Disabled Latency on write accesses 0 Enabled No latency on write accesses 1 TACC Access time 8 8 0 255 TRWR Read write recovery time 16 8 0 255 WCCR WCCR WCCR 0x180 0x20 read-write 0x00000000 IMODE IMODE 0 3 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR IDTR 3 1 IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE ISIZE 4 2 ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE ADMODE 8 3 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR ADDTR 11 1 ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE ADSIZE 12 2 ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE ABMODE 16 3 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR ABDTR 19 1 ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE ABSIZE 20 2 ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE DMODE 24 3 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR DDTR 27 1 DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQSE 29 1 DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 WTCR WTCR WTCR 0x188 0x20 read-write 0x00000000 DCYC DCYC 0 5 0 31 WIR WIR WIR 0x190 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 0 4294967295 WABR WABR write alternate bytes register 0x1A0 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 0 4294967295 SEC_OCTOSPI1 0x54021000 OPAMP Operational amplifiers OPAMP 0x40007800 0x0 0x400 registers OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 OPALPM Operational amplifier Low Power Mode 1 1 OPAMODE Operational amplifier PGA mode 2 2 PGA_GAIN Operational amplifier Programmable amplifier gain value 4 2 VM_SEL inverting input selection 8 2 VP_SEL non inverted input selection 10 1 CALON calibration mode enable 12 1 CALSEL calibration selection 13 1 USERTRIM User trimming enable 14 1 CALOUT Operational amplifier calibration output 15 1 OPA_RANGE Operational amplifier power supply range for stability 31 1 OPAMP1_OTR OPAMP1_OTR OPAMP1 offset trimming register in normal mode 0x4 0x20 read-write 0x00000000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 TRIMOFFSETP Trim for PMOS differential pairs 8 5 OPAMP1_LPOTR OPAMP1_LPOTR OPAMP1 offset trimming register in low-powe mode 0x8 0x20 read-write 0x00000000 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 OPAMP2_CRS OPAMP2_CRS OPAMP2 control/status register 0x10 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 OPALPM Operational amplifier Low Power Mode 1 1 OPAMODE Operational amplifier PGA mode 2 2 PGA_GAIN Operational amplifier Programmable amplifier gain value 4 2 VM_SEL inverting input selection 8 2 VP_SEL non inverted input selection 10 1 CALON calibration mode enable 12 1 CALSEL calibration selection 13 1 USERTRIM User trimming enable 14 1 CALOUT Operational amplifier calibration output 15 1 OPAMP2_OTR OPAMP2_OTR OPAMP2 offset trimming register in normal mode 0x14 0x20 read-write 0x00000000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 TRIMOFFSETP Trim for PMOS differential pairs 8 5 OPAMP2_LPOTR OPAMP2_LPOTR OPAMP2 offset trimming register in low-power mode 0x18 0x20 read-write 0x00000000 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 SEC_OPAMP 0x50007800 OTFDEC1 On-The-Fly Decryption engine OTFDEC 0x420C5000 0x0 0x400 registers OTFDEC1 OTFDEC1 secure global interrupt 108 CR CR OTFDEC control register 0x0 0x20 read-write 0x00000000 ENC Encryption mode bit 0 1 R1CFGR R1CFGR OTFDEC region x configuration register 0x20 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REGx_VERSION region firmware version 16 16 read-write R2CFGR R2CFGR OTFDEC region x configuration register 0x50 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REGx_VERSION region firmware version 16 16 read-write R3CFGR R3CFGR OTFDEC region x configuration register 0x80 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REGx_VERSION region firmware version 16 16 read-write R4CFGR R4CFGR OTFDEC region x configuration register 0xB0 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REGx_VERSION region firmware version 16 16 read-write R1STARTADDR R1STARTADDR OTFDEC region x start address register 0x24 0x20 read-write 0x00000000 REGx_START_ADDR Region AXI start address 0 32 R2STARTADDR R2STARTADDR OTFDEC region x start address register 0x54 0x20 read-write 0x00000000 REGx_START_ADDR Region AXI start address 0 32 R3STARTADDR R3STARTADDR OTFDEC region x start address register 0x84 0x20 read-write 0x00000000 REGx_START_ADDR Region AXI start address 0 32 R4STARTADDR R4STARTADDR OTFDEC region x start address register 0xB4 0x20 read-write 0x00000000 REGx_START_ADDR Region AXI start address 0 32 R1ENDADDR R1ENDADDR OTFDEC region x end address register 0x28 0x20 read-write 0x00000FFF REGx_END_ADDR Region AXI end address 0 32 R2ENDADDR R2ENDADDR OTFDEC region x end address register 0x58 0x20 read-write 0x00000FFF REGx_END_ADDR Region AXI end address 0 32 R3ENDADDR R3ENDADDR OTFDEC region x end address register 0x88 0x20 read-write 0x00000FFF REGx_END_ADDR Region AXI end address 0 32 R4ENDADDR R4ENDADDR OTFDEC region x end address register 0xB8 0x20 read-write 0x00000FFF REGx_END_ADDR Region AXI end address 0 32 R1NONCER0 R1NONCER0 OTFDEC region x nonce register 0 0x2C 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R2NONCER0 R2NONCER0 OTFDEC region x nonce register 0 0x5C 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R3NONCER0 R3NONCER0 OTFDEC region x nonce register 0 R4ENDADDR 0x8C 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R4NONCER0 R4NONCER0 OTFDEC region x nonce register 0 0xBC 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R1NONCER1 R1NONCER1 OTFDEC region x nonce register 1 0x30 0x20 read-write 0x00000000 REGx_NONCE Region nonce 0 32 R2NONCER1 R2NONCER1 OTFDEC region x nonce register 1 0x60 0x20 read-write 0x00000000 REGx_NONCE Region nonce, bits [63:32]REGx_NONCE[63:32] 0 32 R3NONCER1 R3NONCER1 OTFDEC region x nonce register 1 0x90 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R4NONCER1 R4NONCER1 OTFDEC region x nonce register 1 0xC0 0x20 read-write 0x00000000 REGx_NONCE REGx_NONCE 0 32 R1KEYR0 R1KEYR0 OTFDEC region x key register 0 0x34 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R2KEYR0 R2KEYR0 OTFDEC region x key register 0 0x64 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R3KEYR0 R3KEYR0 OTFDEC region x key register 0 0x94 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R4KEYR0 R4KEYR0 OTFDEC region x key register 0 0xC4 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R1KEYR1 R1KEYR1 OTFDEC region x key register 1 0x38 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R2KEYR1 R2KEYR1 OTFDEC region x key register 1 0x68 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R3KEYR1 R3KEYR1 OTFDEC region x key register 1 0x98 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R4KEYR1 R4KEYR1 OTFDEC region x key register 1 0xC8 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R1KEYR2 R1KEYR2 OTFDEC region x key register 2 0x3C 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R2KEYR2 R2KEYR2 OTFDEC region x key register 2 0x6C 0x20 write-only 0x00000000 REGx_KEY_ REGx_KEY 0 32 R3KEYR2 R3KEYR2 OTFDEC region x key register 2 0x9C 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R4KEYR2 R4KEYR2 OTFDEC region x key register 2 0xCC 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R1KEYR3 R1KEYR3 OTFDEC region x key register 3 0x40 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R2KEYR3 R2KEYR3 OTFDEC region x key register 3 0x70 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R3KEYR3 R3KEYR3 OTFDEC region x key register 3 0xA0 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 R4KEYR3 R4KEYR3 OTFDEC region x key register 3 0xD0 0x20 write-only 0x00000000 REGx_KEY REGx_KEY 0 32 ISR ISR OTFDEC interrupt status register 0x300 0x20 read-only 0x00000000 SEIF Security Error Interrupt Flag status 0 1 XONEIF Execute-only execute-Never Error Interrupt Flag status 1 1 KEIF Key Error Interrupt Flag status 2 1 ICR ICR OTFDEC interrupt clear register 0x304 0x20 write-only 0x00000000 SEIF SEIF 0 1 XONEIF Execute-only execute-Never Error Interrupt Flag clear 1 1 KEIF KEIF 2 1 IER IER OTFDEC interrupt enable register 0x308 0x20 read-write 0x00000000 SEIE Security Error Interrupt Enable 0 1 XONEIE XONEIE 1 1 KEIE KEIE 2 1 SEC_OTFDEC1 0x520C5000 PKA PKA PKA 0x420C2000 0x0 0x400 registers PKA PKA global interrupts 97 CR CR PKA control register 0x0 0x20 read-write 0x00000000 EN PKA Enable 0 1 START Start the operation 1 1 MODE PKA operation code 8 6 PROCENDIE End of operation interrupt enable 17 1 RAMERRIE RAM error interrupt enable 19 1 ADDRERRIE Address error interrupt enable 20 1 SR SR PKA status register 0x4 0x20 read-only 0x00000000 BUSY PKA operation in progress 16 1 PROCENDF PKA end of operation flag 17 1 RAMERRF PKA ram error flag 19 1 ADDRERRF address er flag 20 1 CLRFR CLRFR PKA clear flag register 0x8 0x20 write-only 0x00000000 PROCENDFC clear PKA end of operation flag 17 1 RAMERRFC CLEAR PKA RAM ERROR FLAG 19 1 ADDRERRFC clear address error flag 20 1 SEC_PKA 0x520C2000 PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x20 read-write 0x00000400 LPR Low-power run 14 1 VOS Voltage scaling range selection 9 2 DBP Disable backup domain write protection 8 1 LPMS Low-power mode selection 0 3 CR2 CR2 Power control register 2 0x4 0x20 read-write 0x00000000 USV VDDUSB USB supply valid 10 1 IOSV VDDIO2 Independent I/Os supply valid 9 1 PVME4 Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V 7 1 PVME3 Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V 6 1 PVME2 Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V 5 1 PVME1 Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V 4 1 PLS Power voltage detector level selection 1 3 PVDE Power voltage detector enable 0 1 CR3 CR3 Power control register 3 0x8 0x20 read-write 0x00000000 UCPD_DBDIS UCPD_DBDIS 14 1 UCPD_STDBY UCPD_STDBY 13 1 ULPMEN ULPMEN 11 1 APC Apply pull-up and pull-down configuration 10 1 RRS SRAM2 retention in Standby mode 8 2 EWUP5 Enable Wakeup pin WKUP5 4 1 EWUP4 Enable Wakeup pin WKUP4 3 1 EWUP3 Enable Wakeup pin WKUP3 2 1 EWUP2 Enable Wakeup pin WKUP2 1 1 EWUP1 Enable Wakeup pin WKUP1 0 1 CR4 CR4 Power control register 4 0xC 0x20 read-write 0x00000000 SMPSLPEN SMPSLPEN 15 1 SMPSFSTEN SMPSFSTEN 14 1 EXTSMPSEN EXTSMPSEN 13 1 SMPSBYP SMPSBYP 12 1 VBRS VBAT battery charging resistor selection 9 1 VBE VBAT battery charging enable 8 1 WUPP5 Wakeup pin WKUP5 polarity 4 1 WUPP4 Wakeup pin WKUP4 polarity 3 1 WUPP3 Wakeup pin WKUP3 polarity 2 1 WUPP2 Wakeup pin WKUP2 polarity 1 1 WUPP1 Wakeup pin WKUP1 polarity 0 1 SR1 SR1 Power status register 1 0x10 0x20 read-only 0x00000000 SMPSHPRDY SMPSHPRDY 15 1 EXTSMPSRDY EXTSMPSRDY 13 1 SMPSBYPRDY SMPSBYPRDY 12 1 SBF Standby flag 8 1 WUF5 Wakeup flag 5 4 1 WUF4 Wakeup flag 4 3 1 WUF3 Wakeup flag 3 2 1 WUF2 Wakeup flag 2 1 1 WUF1 Wakeup flag 1 0 1 SR2 SR2 Power status register 2 0x14 0x20 read-only 0x00000000 PVMO4 Peripheral voltage monitoring output: VDDA vs. 2.2 V 15 1 PVMO3 Peripheral voltage monitoring output: VDDA vs. 1.62 V 14 1 PVMO2 Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V 13 1 PVMO1 Peripheral voltage monitoring output: VDDUSB vs. 1.2 V 12 1 PVDO Power voltage detector output 11 1 VOSF Voltage scaling flag 10 1 REGLPF Low-power regulator flag 9 1 REGLPS Low-power regulator started 8 1 SCR SCR Power status clear register 0x18 0x20 write-only 0x00000000 CSBF Clear standby flag 8 1 CWUF5 Clear wakeup flag 5 4 1 CWUF4 Clear wakeup flag 4 3 1 CWUF3 Clear wakeup flag 3 2 1 CWUF2 Clear wakeup flag 2 1 1 CWUF1 Clear wakeup flag 1 0 1 PUCRA PUCRA Power Port A pull-up control register 0x20 0x20 read-write 0x00000000 PU15 Port A pull-up bit y (y=0..15) 15 1 PU14 Port A pull-up bit y (y=0..15) 14 1 PU13 Port A pull-up bit y (y=0..15) 13 1 PU12 Port A pull-up bit y (y=0..15) 12 1 PU11 Port A pull-up bit y (y=0..15) 11 1 PU10 Port A pull-up bit y (y=0..15) 10 1 PU9 Port A pull-up bit y (y=0..15) 9 1 PU8 Port A pull-up bit y (y=0..15) 8 1 PU7 Port A pull-up bit y (y=0..15) 7 1 PU6 Port A pull-up bit y (y=0..15) 6 1 PU5 Port A pull-up bit y (y=0..15) 5 1 PU4 Port A pull-up bit y (y=0..15) 4 1 PU3 Port A pull-up bit y (y=0..15) 3 1 PU2 Port A pull-up bit y (y=0..15) 2 1 PU1 Port A pull-up bit y (y=0..15) 1 1 PU0 Port A pull-up bit y (y=0..15) 0 1 PDCRA PDCRA Power Port A pull-down control register 0x24 0x20 read-write 0x00000000 PD15 Port A pull-down bit y (y=0..15) 15 1 PD14 Port A pull-down bit y (y=0..15) 14 1 PD13 Port A pull-down bit y (y=0..15) 13 1 PD12 Port A pull-down bit y (y=0..15) 12 1 PD11 Port A pull-down bit y (y=0..15) 11 1 PD10 Port A pull-down bit y (y=0..15) 10 1 PD9 Port A pull-down bit y (y=0..15) 9 1 PD8 Port A pull-down bit y (y=0..15) 8 1 PD7 Port A pull-down bit y (y=0..15) 7 1 PD6 Port A pull-down bit y (y=0..15) 6 1 PD5 Port A pull-down bit y (y=0..15) 5 1 PD4 Port A pull-down bit y (y=0..15) 4 1 PD3 Port A pull-down bit y (y=0..15) 3 1 PD2 Port A pull-down bit y (y=0..15) 2 1 PD1 Port A pull-down bit y (y=0..15) 1 1 PD0 Port A pull-down bit y (y=0..15) 0 1 PUCRB PUCRB Power Port B pull-up control register 0x28 0x20 read-write 0x00000000 PU15 Port B pull-up bit y (y=0..15) 15 1 PU14 Port B pull-up bit y (y=0..15) 14 1 PU13 Port B pull-up bit y (y=0..15) 13 1 PU12 Port B pull-up bit y (y=0..15) 12 1 PU11 Port B pull-up bit y (y=0..15) 11 1 PU10 Port B pull-up bit y (y=0..15) 10 1 PU9 Port B pull-up bit y (y=0..15) 9 1 PU8 Port B pull-up bit y (y=0..15) 8 1 PU7 Port B pull-up bit y (y=0..15) 7 1 PU6 Port B pull-up bit y (y=0..15) 6 1 PU5 Port B pull-up bit y (y=0..15) 5 1 PU4 Port B pull-up bit y (y=0..15) 4 1 PU3 Port B pull-up bit y (y=0..15) 3 1 PU2 Port B pull-up bit y (y=0..15) 2 1 PU1 Port B pull-up bit y (y=0..15) 1 1 PU0 Port B pull-up bit y (y=0..15) 0 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 0x20 read-write 0x00000000 PD15 Port B pull-down bit y (y=0..15) 15 1 PD14 Port B pull-down bit y (y=0..15) 14 1 PD13 Port B pull-down bit y (y=0..15) 13 1 PD12 Port B pull-down bit y (y=0..15) 12 1 PD11 Port B pull-down bit y (y=0..15) 11 1 PD10 Port B pull-down bit y (y=0..15) 10 1 PD9 Port B pull-down bit y (y=0..15) 9 1 PD8 Port B pull-down bit y (y=0..15) 8 1 PD7 Port B pull-down bit y (y=0..15) 7 1 PD6 Port B pull-down bit y (y=0..15) 6 1 PD5 Port B pull-down bit y (y=0..15) 5 1 PD4 Port B pull-down bit y (y=0..15) 4 1 PD3 Port B pull-down bit y (y=0..15) 3 1 PD2 Port B pull-down bit y (y=0..15) 2 1 PD1 Port B pull-down bit y (y=0..15) 1 1 PD0 Port B pull-down bit y (y=0..15) 0 1 PUCRC PUCRC Power Port C pull-up control register 0x30 0x20 read-write 0x00000000 PU15 Port C pull-up bit y (y=0..15) 15 1 PU14 Port C pull-up bit y (y=0..15) 14 1 PU13 Port C pull-up bit y (y=0..15) 13 1 PU12 Port C pull-up bit y (y=0..15) 12 1 PU11 Port C pull-up bit y (y=0..15) 11 1 PU10 Port C pull-up bit y (y=0..15) 10 1 PU9 Port C pull-up bit y (y=0..15) 9 1 PU8 Port C pull-up bit y (y=0..15) 8 1 PU7 Port C pull-up bit y (y=0..15) 7 1 PU6 Port C pull-up bit y (y=0..15) 6 1 PU5 Port C pull-up bit y (y=0..15) 5 1 PU4 Port C pull-up bit y (y=0..15) 4 1 PU3 Port C pull-up bit y (y=0..15) 3 1 PU2 Port C pull-up bit y (y=0..15) 2 1 PU1 Port C pull-up bit y (y=0..15) 1 1 PU0 Port C pull-up bit y (y=0..15) 0 1 PDCRC PDCRC Power Port C pull-down control register 0x34 0x20 read-write 0x00000000 PD15 Port C pull-down bit y (y=0..15) 15 1 PD14 Port C pull-down bit y (y=0..15) 14 1 PD13 Port C pull-down bit y (y=0..15) 13 1 PD12 Port C pull-down bit y (y=0..15) 12 1 PD11 Port C pull-down bit y (y=0..15) 11 1 PD10 Port C pull-down bit y (y=0..15) 10 1 PD9 Port C pull-down bit y (y=0..15) 9 1 PD8 Port C pull-down bit y (y=0..15) 8 1 PD7 Port C pull-down bit y (y=0..15) 7 1 PD6 Port C pull-down bit y (y=0..15) 6 1 PD5 Port C pull-down bit y (y=0..15) 5 1 PD4 Port C pull-down bit y (y=0..15) 4 1 PD3 Port C pull-down bit y (y=0..15) 3 1 PD2 Port C pull-down bit y (y=0..15) 2 1 PD1 Port C pull-down bit y (y=0..15) 1 1 PD0 Port C pull-down bit y (y=0..15) 0 1 PUCRD PUCRD Power Port D pull-up control register 0x38 0x20 read-write 0x00000000 PU15 Port D pull-up bit y (y=0..15) 15 1 PU14 Port D pull-up bit y (y=0..15) 14 1 PU13 Port D pull-up bit y (y=0..15) 13 1 PU12 Port D pull-up bit y (y=0..15) 12 1 PU11 Port D pull-up bit y (y=0..15) 11 1 PU10 Port D pull-up bit y (y=0..15) 10 1 PU9 Port D pull-up bit y (y=0..15) 9 1 PU8 Port D pull-up bit y (y=0..15) 8 1 PU7 Port D pull-up bit y (y=0..15) 7 1 PU6 Port D pull-up bit y (y=0..15) 6 1 PU5 Port D pull-up bit y (y=0..15) 5 1 PU4 Port D pull-up bit y (y=0..15) 4 1 PU3 Port D pull-up bit y (y=0..15) 3 1 PU2 Port D pull-up bit y (y=0..15) 2 1 PU1 Port D pull-up bit y (y=0..15) 1 1 PU0 Port D pull-up bit y (y=0..15) 0 1 PDCRD PDCRD Power Port D pull-down control register 0x3C 0x20 read-write 0x00000000 PD15 Port D pull-down bit y (y=0..15) 15 1 PD14 Port D pull-down bit y (y=0..15) 14 1 PD13 Port D pull-down bit y (y=0..15) 13 1 PD12 Port D pull-down bit y (y=0..15) 12 1 PD11 Port D pull-down bit y (y=0..15) 11 1 PD10 Port D pull-down bit y (y=0..15) 10 1 PD9 Port D pull-down bit y (y=0..15) 9 1 PD8 Port D pull-down bit y (y=0..15) 8 1 PD7 Port D pull-down bit y (y=0..15) 7 1 PD6 Port D pull-down bit y (y=0..15) 6 1 PD5 Port D pull-down bit y (y=0..15) 5 1 PD4 Port D pull-down bit y (y=0..15) 4 1 PD3 Port D pull-down bit y (y=0..15) 3 1 PD2 Port D pull-down bit y (y=0..15) 2 1 PD1 Port D pull-down bit y (y=0..15) 1 1 PD0 Port D pull-down bit y (y=0..15) 0 1 PUCRE PUCRE Power Port E pull-up control register 0x40 0x20 read-write 0x00000000 PU15 Port E pull-up bit y (y=0..15) 15 1 PU14 Port E pull-up bit y (y=0..15) 14 1 PU13 Port E pull-up bit y (y=0..15) 13 1 PU12 Port E pull-up bit y (y=0..15) 12 1 PU11 Port E pull-up bit y (y=0..15) 11 1 PU10 Port E pull-up bit y (y=0..15) 10 1 PU9 Port E pull-up bit y (y=0..15) 9 1 PU8 Port E pull-up bit y (y=0..15) 8 1 PU7 Port E pull-up bit y (y=0..15) 7 1 PU6 Port E pull-up bit y (y=0..15) 6 1 PU5 Port E pull-up bit y (y=0..15) 5 1 PU4 Port E pull-up bit y (y=0..15) 4 1 PU3 Port E pull-up bit y (y=0..15) 3 1 PU2 Port E pull-up bit y (y=0..15) 2 1 PU1 Port E pull-up bit y (y=0..15) 1 1 PU0 Port E pull-up bit y (y=0..15) 0 1 PDCRE PDCRE Power Port E pull-down control register 0x44 0x20 read-write 0x00000000 PD15 Port E pull-down bit y (y=0..15) 15 1 PD14 Port E pull-down bit y (y=0..15) 14 1 PD13 Port E pull-down bit y (y=0..15) 13 1 PD12 Port E pull-down bit y (y=0..15) 12 1 PD11 Port E pull-down bit y (y=0..15) 11 1 PD10 Port E pull-down bit y (y=0..15) 10 1 PD9 Port E pull-down bit y (y=0..15) 9 1 PD8 Port E pull-down bit y (y=0..15) 8 1 PD7 Port E pull-down bit y (y=0..15) 7 1 PD6 Port E pull-down bit y (y=0..15) 6 1 PD5 Port E pull-down bit y (y=0..15) 5 1 PD4 Port E pull-down bit y (y=0..15) 4 1 PD3 Port E pull-down bit y (y=0..15) 3 1 PD2 Port E pull-down bit y (y=0..15) 2 1 PD1 Port E pull-down bit y (y=0..15) 1 1 PD0 Port E pull-down bit y (y=0..15) 0 1 PUCRF PUCRF Power Port F pull-up control register 0x48 0x20 read-write 0x00000000 PU15 Port F pull-up bit y (y=0..15) 15 1 PU14 Port F pull-up bit y (y=0..15) 14 1 PU13 Port F pull-up bit y (y=0..15) 13 1 PU12 Port F pull-up bit y (y=0..15) 12 1 PU11 Port F pull-up bit y (y=0..15) 11 1 PU10 Port F pull-up bit y (y=0..15) 10 1 PU9 Port F pull-up bit y (y=0..15) 9 1 PU8 Port F pull-up bit y (y=0..15) 8 1 PU7 Port F pull-up bit y (y=0..15) 7 1 PU6 Port F pull-up bit y (y=0..15) 6 1 PU5 Port F pull-up bit y (y=0..15) 5 1 PU4 Port F pull-up bit y (y=0..15) 4 1 PU3 Port F pull-up bit y (y=0..15) 3 1 PU2 Port F pull-up bit y (y=0..15) 2 1 PU1 Port F pull-up bit y (y=0..15) 1 1 PU0 Port F pull-up bit y (y=0..15) 0 1 PDCRF PDCRF Power Port F pull-down control register 0x4C 0x20 read-write 0x00000000 PD15 Port F pull-down bit y (y=0..15) 15 1 PD14 Port F pull-down bit y (y=0..15) 14 1 PD13 Port F pull-down bit y (y=0..15) 13 1 PD12 Port F pull-down bit y (y=0..15) 12 1 PD11 Port F pull-down bit y (y=0..15) 11 1 PD10 Port F pull-down bit y (y=0..15) 10 1 PD9 Port F pull-down bit y (y=0..15) 9 1 PD8 Port F pull-down bit y (y=0..15) 8 1 PD7 Port F pull-down bit y (y=0..15) 7 1 PD6 Port F pull-down bit y (y=0..15) 6 1 PD5 Port F pull-down bit y (y=0..15) 5 1 PD4 Port F pull-down bit y (y=0..15) 4 1 PD3 Port F pull-down bit y (y=0..15) 3 1 PD2 Port F pull-down bit y (y=0..15) 2 1 PD1 Port F pull-down bit y (y=0..15) 1 1 PD0 Port F pull-down bit y (y=0..15) 0 1 PUCRG PUCRG Power Port G pull-up control register 0x50 0x20 read-write 0x00000000 PU15 Port G pull-up bit y (y=0..15) 15 1 PU14 Port G pull-up bit y (y=0..15) 14 1 PU13 Port G pull-up bit y (y=0..15) 13 1 PU12 Port G pull-up bit y (y=0..15) 12 1 PU11 Port G pull-up bit y (y=0..15) 11 1 PU10 Port G pull-up bit y (y=0..15) 10 1 PU9 Port G pull-up bit y (y=0..15) 9 1 PU8 Port G pull-up bit y (y=0..15) 8 1 PU7 Port G pull-up bit y (y=0..15) 7 1 PU6 Port G pull-up bit y (y=0..15) 6 1 PU5 Port G pull-up bit y (y=0..15) 5 1 PU4 Port G pull-up bit y (y=0..15) 4 1 PU3 Port G pull-up bit y (y=0..15) 3 1 PU2 Port G pull-up bit y (y=0..15) 2 1 PU1 Port G pull-up bit y (y=0..15) 1 1 PU0 Port G pull-up bit y (y=0..15) 0 1 PDCRG PDCRG Power Port G pull-down control register 0x54 0x20 read-write 0x00000000 PD15 Port G pull-down bit y (y=0..15) 15 1 PD14 Port G pull-down bit y (y=0..15) 14 1 PD13 Port G pull-down bit y (y=0..15) 13 1 PD12 Port G pull-down bit y (y=0..15) 12 1 PD11 Port G pull-down bit y (y=0..15) 11 1 PD10 Port G pull-down bit y (y=0..15) 10 1 PD9 Port G pull-down bit y (y=0..15) 9 1 PD8 Port G pull-down bit y (y=0..15) 8 1 PD7 Port G pull-down bit y (y=0..15) 7 1 PD6 Port G pull-down bit y (y=0..15) 6 1 PD5 Port G pull-down bit y (y=0..15) 5 1 PD4 Port G pull-down bit y (y=0..15) 4 1 PD3 Port G pull-down bit y (y=0..15) 3 1 PD2 Port G pull-down bit y (y=0..15) 2 1 PD1 Port G pull-down bit y (y=0..15) 1 1 PD0 Port G pull-down bit y (y=0..15) 0 1 PUCRH PUCRH Power Port H pull-up control register 0x58 0x20 read-write 0x00000000 PU15 Port G pull-up bit y (y=0..15) 15 1 PU14 Port G pull-up bit y (y=0..15) 14 1 PU13 Port G pull-up bit y (y=0..15) 13 1 PU12 Port G pull-up bit y (y=0..15) 12 1 PU11 Port G pull-up bit y (y=0..15) 11 1 PU10 Port G pull-up bit y (y=0..15) 10 1 PU9 Port G pull-up bit y (y=0..15) 9 1 PU8 Port G pull-up bit y (y=0..15) 8 1 PU7 Port G pull-up bit y (y=0..15) 7 1 PU6 Port G pull-up bit y (y=0..15) 6 1 PU5 Port G pull-up bit y (y=0..15) 5 1 PU4 Port G pull-up bit y (y=0..15) 4 1 PU3 Port G pull-up bit y (y=0..15) 3 1 PU2 Port G pull-up bit y (y=0..15) 2 1 PU1 Port G pull-up bit y (y=0..15) 1 1 PU0 Port G pull-up bit y (y=0..15) 0 1 PDCRH PDCRH Power Port H pull-down control register 0x5C 0x20 read-write 0x00000000 PD15 Port G pull-down bit y (y=0..15) 15 1 PD14 Port G pull-down bit y (y=0..15) 14 1 PD13 Port G pull-down bit y (y=0..15) 13 1 PD12 Port G pull-down bit y (y=0..15) 12 1 PD11 Port G pull-down bit y (y=0..15) 11 1 PD10 Port G pull-down bit y (y=0..15) 10 1 PD9 Port G pull-down bit y (y=0..15) 9 1 PD8 Port G pull-down bit y (y=0..15) 8 1 PD7 Port G pull-down bit y (y=0..15) 7 1 PD6 Port G pull-down bit y (y=0..15) 6 1 PD5 Port G pull-down bit y (y=0..15) 5 1 PD4 Port G pull-down bit y (y=0..15) 4 1 PD3 Port G pull-down bit y (y=0..15) 3 1 PD2 Port G pull-down bit y (y=0..15) 2 1 PD1 Port G pull-down bit y (y=0..15) 1 1 PD0 Port G pull-down bit y (y=0..15) 0 1 SECCFGR SECCFGR Power secure configuration register 0x78 0x20 read-write 0x00000000 APCSEC APCSEC 11 1 VBSEC VBSEC 10 1 VDMSEC VDMSEC 9 1 LPMSEC LPMSEC 8 1 WUP5SEC WKUP5 pin security 4 1 WUP4SEC WKUP4 pin security 3 1 WUP3SEC WKUP3 pin security 2 1 WUP2SEC WKUP2 pin security 1 1 WUP1SEC WKUP1 pin security 0 1 PRIVCFGR PRIVCFGR Power privilege configuration register 0x80 0x20 read-write 0x00000000 PRIV PRIV 0 1 SEC_PWR 0x50007000 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 9 RCC_S RCC SECURE GLOBAL INTERRUPT 10 CR CR Clock control register 0x0 0x20 0x00000063 PRIV PRIV 31 1 read-write MSIRDY MSI clock ready flag 1 1 read-only MSIRDYR NotReady Clock not ready 0 Ready Clock ready 1 PLLSAI2RDY SAI2 PLL clock ready flag 29 1 read-only PLLSAI2ON SAI2 PLL enable 28 1 read-write PLLSAI1RDY SAI1 PLL clock ready flag 27 1 read-only PLLSAI1ON SAI1 PLL enable 26 1 read-write PLLRDY Main PLL clock ready flag 25 1 read-only HSION HSI clock enable 8 1 read-write HSION Off Clock Off 0 On Clock On 1 PLLON Main PLL enable 24 1 read-write CSSON Clock security system enable 19 1 write-only CSSON Off Clock security system disabled (clock detector OFF) 0 On Clock security system enable (clock detector ON if the HSE is ready, OFF if not) 1 HSEBYP HSE crystal oscillator bypass 18 1 read-write HSEBYP NotBypassed HSE crystal oscillator not bypassed 0 Bypassed HSE crystal oscillator bypassed with external clock 1 HSERDY HSE clock ready flag 17 1 read-only HSEON HSE clock enable 16 1 read-write HSIASFS HSI automatic start from Stop 11 1 read-write HSIRDY HSI clock ready flag 10 1 read-only HSIKERON HSI always enable for peripheral kernels 9 1 read-write MSIRANGE MSI clock ranges 4 4 read-write MSIRGSEL MSI clock range selection 3 1 write-only MSIPLLEN MSI clock PLL enable 2 1 read-write MSION MSI clock enable 0 1 read-write ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x40000000 HSITRIM HSI clock trimming 24 7 read-write HSICAL HSI clock calibration 16 8 read-only MSITRIM MSI clock trimming 8 8 read-write MSICAL MSI clock calibration 0 8 read-only CFGR CFGR Clock configuration register 0x8 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 3 read-only MCOPRE Div1 MCO divided by 1 0 Div2 MCO divided by 2 1 Div4 MCO divided by 4 2 Div8 MCO divided by 8 3 Div16 MCO divided by 16 4 MCOSEL Microcontroller clock output 24 4 read-write MCOSEL None MCO output disabled, no clock on MCO 0 SYSCLK SYSCLK system clock selected 1 MSI MSI clock selected 2 HSI HSI clock selected 3 HSE HSE clock selected 4 PLL Main PLL clock selected 5 LSI LSI clock selected 6 LSE LSE clock selected 7 HSI48 Internal HSI48 clock selected 8 STOPWUCK Wakeup from Stop and CSS backup clock selection 15 1 read-write STOPWUCK MSI MSI oscillator selected as wakeup from stop clock and CSS backup clock 0 HSI HSI oscillator selected as wakeup from stop clock and CSS backup clock 1 PPRE1 PB low-speed prescaler (APB1) 8 3 read-write PPRE1 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true PPRE2 APB high-speed prescaler (APB2) 11 3 read-write HPRE AHB prescaler 4 4 read-write HPRE Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 Div1 SYSCLK not divided true SWS System clock switch status 2 2 read-only SWSR MSI MSI oscillator used as system clock 0 HSI HSI oscillator used as system clock 1 HSE HSE used as system clock 2 PLL PLL used as system clock 3 SW System clock switch 0 2 read-write SW MSI MSI selected as system clock 0 HSI HSI selected as system clock 1 HSE HSE selected as system clock 2 PLL PLL selected as system clock 3 PLLCFGR PLLCFGR PLL configuration register 0xC 0x20 read-write 0x00001000 PLLPDIV Main PLL division factor for PLLSAI2CLK 27 5 PLLR Main PLL division factor for PLLCLK (system clock) 25 2 PLLREN Main PLL PLLCLK output enable 24 1 PLLQ Main PLL division factor for PLLUSB1CLK(48 MHz clock) 21 2 PLLQEN Main PLL PLLUSB1CLK output enable 20 1 PLLP Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) 17 1 PLLPEN Main PLL PLLSAI3CLK output enable 16 1 PLLN Main PLL multiplication factor for VCO 8 7 PLLM Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock 4 4 PLLSRC Main PLL, PLLSAI1 and PLLSAI2 entry clock source 0 2 PLLSAI1CFGR PLLSAI1CFGR PLLSAI1 configuration register 0x10 0x20 read-write 0x00001000 PLLSAI1PDIV PLLSAI1 division factor for PLLSAI1CLK 27 5 PLLSAI1R PLLSAI1 division factor for PLLADC1CLK (ADC clock) 25 2 PLLSAI1REN PLLSAI1 PLLADC1CLK output enable 24 1 PLLSAI1Q SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) 21 2 PLLSAI1QEN SAI1PLL PLLUSB2CLK output enable 20 1 PLLSAI1P SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) 17 1 PLLSAI1PEN SAI1PLL PLLSAI1CLK output enable 16 1 PLLSAI1N SAI1PLL multiplication factor for VCO 8 7 PLLSAI1M Division factor for PLLSAI1 input clock 4 4 PLLSAI1SRC PLLSAI1SRC 0 2 PLLSAI2CFGR PLLSAI2CFGR PLLSAI2 configuration register 0x14 0x20 read-write 0x00001000 PLLSAI2PDIV PLLSAI2 division factor for PLLSAI2CLK 27 5 PLLSAI2P SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) 17 1 PLLSAI2PEN SAI2PLL PLLSAI2CLK output enable 16 1 PLLSAI2N SAI2PLL multiplication factor for VCO 8 7 PLLSAI2M Division factor for PLLSAI2 input clock 4 4 PLLSAI2SRC PLLSAI2SRC 0 2 CIER CIER Clock interrupt enable register 0x18 0x20 read-write 0x00000000 LSIRDYIE LSI ready interrupt enable 0 1 LSERDYIE LSE ready interrupt enable 1 1 MSIRDYIE MSI ready interrupt enable 2 1 HSIRDYIE HSI ready interrupt enable 3 1 HSERDYIE HSE ready interrupt enable 4 1 PLLRDYIE PLL ready interrupt enable 5 1 PLLSAI1RDYIE PLLSAI1 ready interrupt enable 6 1 PLLSAI2RDYIE PLLSAI2 ready interrupt enable 7 1 LSECSSIE LSE clock security system interrupt enable 9 1 HSI48RDYIE HSI48 ready interrupt enable 10 1 CIFR CIFR Clock interrupt flag register 0x1C 0x20 read-only 0x00000000 LSIRDYF LSI ready interrupt flag 0 1 LSERDYF LSE ready interrupt flag 1 1 MSIRDYF MSI ready interrupt flag 2 1 HSIRDYF HSI ready interrupt flag 3 1 HSERDYF HSE ready interrupt flag 4 1 PLLRDYF PLL ready interrupt flag 5 1 PLLSAI1RDYF PLLSAI1 ready interrupt flag 6 1 PLLSAI2RDYF PLLSAI2 ready interrupt flag 7 1 CSSF Clock security system interrupt flag 8 1 LSECSSF LSE Clock security system interrupt flag 9 1 HSI48RDYF HSI48 ready interrupt flag 10 1 CICR CICR Clock interrupt clear register 0x20 0x20 write-only 0x00000000 LSIRDYC LSI ready interrupt clear 0 1 LSERDYC LSE ready interrupt clear 1 1 MSIRDYC MSI ready interrupt clear 2 1 HSIRDYC HSI ready interrupt clear 3 1 HSERDYC HSE ready interrupt clear 4 1 PLLRDYC PLL ready interrupt clear 5 1 PLLSAI1RDYC PLLSAI1 ready interrupt clear 6 1 PLLSAI2RDYC PLLSAI2 ready interrupt clear 7 1 CSSC Clock security system interrupt clear 8 1 LSECSSC LSE Clock security system interrupt clear 9 1 HSI48RDYC HSI48 oscillator ready interrupt clear 10 1 AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x28 0x20 read-write 0x00000000 DMA1RST DMA1 reset 0 1 DMA1RST Reset Reset the selected module 1 DMA2RST DMA2 reset 1 1 DMAMUX1RST DMAMUXRST 2 1 FLASHRST Flash memory interface reset 8 1 CRCRST CRC reset 12 1 TSCRST Touch Sensing Controller reset 16 1 GTZCRST GTZC reset 22 1 AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x2C 0x20 read-write 0x00000000 GPIOARST IO port A reset 0 1 GPIOARST Reset Reset the selected module 1 GPIOBRST IO port B reset 1 1 GPIOCRST IO port C reset 2 1 GPIODRST IO port D reset 3 1 GPIOERST IO port E reset 4 1 GPIOFRST IO port F reset 5 1 GPIOGRST IO port G reset 6 1 GPIOHRST IO port H reset 7 1 ADCRST ADC reset 13 1 AESRST AES hardware accelerator reset 16 1 HASHRST Hash reset 17 1 RNGRST Random number generator reset 18 1 PKARST PKARST 19 1 OTFDEC1RST OTFDEC1RST 21 1 SDMMC1RST SDMMC1 reset 22 1 AHB3RSTR AHB3RSTR AHB3 peripheral reset register 0x30 0x20 read-write 0x00000000 FMCRST Flexible memory controller reset 0 1 FMCRST Reset Reset the selected module 1 OSPI1RST OSPI1RST 8 1 APB1RSTR1 APB1RSTR1 APB1 peripheral reset register 1 0x38 0x20 read-write 0x00000000 TIM2RST TIM2 timer reset 0 1 TIM2RST Reset Reset the selected module 1 LPTIM1RST Low Power Timer 1 reset 31 1 OPAMPRST OPAMP interface reset 30 1 DAC1RST DAC1 interface reset 29 1 PWRRST Power interface reset 28 1 CRSRST CRS reset 24 1 I2C3RST I2C3 reset 23 1 I2C2RST I2C2 reset 22 1 I2C1RST I2C1 reset 21 1 UART5RST UART5 reset 20 1 UART4RST UART4 reset 19 1 USART3RST USART3 reset 18 1 USART2RST USART2 reset 17 1 SPI3RST SPI3 reset 15 1 SPI2RST SPI2 reset 14 1 TIM7RST TIM7 timer reset 5 1 TIM6RST TIM6 timer reset 4 1 TIM5RST TIM5 timer reset 3 1 TIM4RST TIM3 timer reset 2 1 TIM3RST TIM3 timer reset 1 1 APB1RSTR2 APB1RSTR2 APB1 peripheral reset register 2 0x3C 0x20 read-write 0x00000000 LPUART1RST Low-power UART 1 reset 0 1 LPUART1RST Reset Reset the selected module 1 I2C4RST I2C4 reset 1 1 LPTIM2RST Low-power timer 2 reset 5 1 LPTIM3RST LPTIM3RST 6 1 FDCAN1RST FDCAN1RST 9 1 USBFSRST USBFSRST 21 1 UCPD1RST UCPD1RST 23 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x40 0x20 read-write 0x00000000 SYSCFGRST System configuration (SYSCFG) reset 0 1 SYSCFGRST Reset Reset the selected module 1 TIM1RST TIM1 timer reset 11 1 SPI1RST SPI1 reset 12 1 TIM8RST TIM8 timer reset 13 1 USART1RST USART1 reset 14 1 TIM15RST TIM15 timer reset 16 1 TIM16RST TIM16 timer reset 17 1 TIM17RST TIM17 timer reset 18 1 SAI1RST Serial audio interface 1 (SAI1) reset 21 1 SAI2RST Serial audio interface 2 (SAI2) reset 22 1 DFSDM1RST Digital filters for sigma-delata modulators (DFSDM) reset 24 1 AHB1ENR AHB1ENR AHB1 peripheral clock enable register 0x48 0x20 read-write 0x00000100 DMA1EN DMA1 clock enable 0 1 DMA1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 DMA2EN DMA2 clock enable 1 1 DMAMUX1EN DMAMUX clock enable 2 1 FLASHEN Flash memory interface clock enable 8 1 CRCEN CRC clock enable 12 1 TSCEN Touch Sensing Controller clock enable 16 1 GTZCEN GTZCEN 22 1 AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x4C 0x20 read-write 0x00000000 GPIOAEN IO port A clock enable 0 1 GPIOAEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 GPIOBEN IO port B clock enable 1 1 GPIOCEN IO port C clock enable 2 1 GPIODEN IO port D clock enable 3 1 GPIOEEN IO port E clock enable 4 1 GPIOFEN IO port F clock enable 5 1 GPIOGEN IO port G clock enable 6 1 GPIOHEN IO port H clock enable 7 1 ADCEN ADC clock enable 13 1 AESEN AES accelerator clock enable 16 1 HASHEN HASH clock enable 17 1 RNGEN Random Number Generator clock enable 18 1 PKAEN PKAEN 19 1 OTFDEC1EN OTFDEC1EN 21 1 SDMMC1EN SDMMC1 clock enable 22 1 AHB3ENR AHB3ENR AHB3 peripheral clock enable register 0x50 0x20 read-write 0x00000000 FMCEN Flexible memory controller clock enable 0 1 FMCEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 OSPI1EN OSPI1EN 8 1 APB1ENR1 APB1ENR1 APB1ENR1 0x58 0x20 read-write 0x00000000 TIM2EN TIM2 timer clock enable 0 1 TIM2EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM3EN TIM3 timer clock enable 1 1 TIM4EN TIM4 timer clock enable 2 1 TIM5EN TIM5 timer clock enable 3 1 TIM6EN TIM6 timer clock enable 4 1 TIM7EN TIM7 timer clock enable 5 1 RTCAPBEN RTC APB clock enable 10 1 WWDGEN Window watchdog clock enable 11 1 SPI2EN SPI2 clock enable 14 1 SP3EN SPI3 clock enable 15 1 USART2EN USART2 clock enable 17 1 USART3EN USART3 clock enable 18 1 UART4EN UART4 clock enable 19 1 UART5EN UART5 clock enable 20 1 I2C1EN I2C1 clock enable 21 1 I2C2EN I2C2 clock enable 22 1 I2C3EN I2C3 clock enable 23 1 CRSEN Clock Recovery System clock enable 24 1 PWREN Power interface clock enable 28 1 DAC1EN DAC1 interface clock enable 29 1 OPAMPEN OPAMP interface clock enable 30 1 LPTIM1EN Low power timer 1 clock enable 31 1 APB1ENR2 APB1ENR2 APB1 peripheral clock enable register 2 0x5C 0x20 read-write 0x00000000 LPUART1EN Low power UART 1 clock enable 0 1 LPUART1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 I2C4EN I2C4 clock enable 1 1 LPTIM2EN LPTIM2EN 5 1 LPTIM3EN LPTIM3EN 6 1 FDCAN1EN FDCAN1EN 9 1 USBFSEN USBFSEN 21 1 UCPD1EN UCPD1EN 23 1 APB2ENR APB2ENR APB2ENR 0x60 0x20 read-write 0x00000000 SYSCFGEN SYSCFG clock enable 0 1 SYSCFGEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM1EN TIM1 timer clock enable 11 1 SPI1EN SPI1 clock enable 12 1 TIM8EN TIM8 timer clock enable 13 1 USART1EN USART1clock enable 14 1 TIM15EN TIM15 timer clock enable 16 1 TIM16EN TIM16 timer clock enable 17 1 TIM17EN TIM17 timer clock enable 18 1 SAI1EN SAI1 clock enable 21 1 SAI2EN SAI2 clock enable 22 1 DFSDM1EN DFSDM timer clock enable 24 1 AHB1SMENR AHB1SMENR AHB1 peripheral clocks enable in Sleep and Stop modes register 0x68 0x20 read-write 0x00C11307 DMA1SMEN DMA1 clocks enable during Sleep and Stop modes 0 1 DMA2SMEN DMA2 clocks enable during Sleep and Stop modes 1 1 DMAMUX1SMEN DMAMUX clock enable during Sleep and Stop modes 2 1 FLASHSMEN Flash memory interface clocks enable during Sleep and Stop modes 8 1 SRAM1SMEN SRAM1 interface clocks enable during Sleep and Stop modes 9 1 CRCSMEN CRCSMEN 12 1 TSCSMEN Touch Sensing Controller clocks enable during Sleep and Stop modes 16 1 GTZCSMEN GTZCSMEN 22 1 ICACHESMEN ICACHESMEN 23 1 AHB2SMENR AHB2SMENR AHB2 peripheral clocks enable in Sleep and Stop modes register 0x6C 0x20 read-write 0x006F22FF GPIOASMEN IO port A clocks enable during Sleep and Stop modes 0 1 GPIOBSMEN IO port B clocks enable during Sleep and Stop modes 1 1 GPIOCSMEN IO port C clocks enable during Sleep and Stop modes 2 1 GPIODSMEN IO port D clocks enable during Sleep and Stop modes 3 1 GPIOESMEN IO port E clocks enable during Sleep and Stop modes 4 1 GPIOFSMEN IO port F clocks enable during Sleep and Stop modes 5 1 GPIOGSMEN IO port G clocks enable during Sleep and Stop modes 6 1 GPIOHSMEN IO port H clocks enable during Sleep and Stop modes 7 1 SRAM2SMEN SRAM2 interface clocks enable during Sleep and Stop modes 9 1 ADCFSSMEN ADC clocks enable during Sleep and Stop modes 13 1 AESSMEN AES accelerator clocks enable during Sleep and Stop modes 16 1 HASHSMEN HASH clock enable during Sleep and Stop modes 17 1 RNGSMEN Random Number Generator clocks enable during Sleep and Stop modes 18 1 PKASMEN PKASMEN 19 1 OTFDEC1SMEN OTFDEC1SMEN 21 1 SDMMC1SMEN SDMMC1 clocks enable during Sleep and Stop modes 22 1 AHB3SMENR AHB3SMENR AHB3 peripheral clocks enable in Sleep and Stop modes register 0x70 0x20 read-write 0x00000101 FMCSMEN Flexible memory controller clocks enable during Sleep and Stop modes 0 1 OSPI1SMEN OSPI1SMEN 8 1 APB1SMENR1 APB1SMENR1 APB1SMENR1 0x78 0x20 read-write 0xF1FECC3F TIM2SMEN TIM2 timer clocks enable during Sleep and Stop modes 0 1 TIM3SMEN TIM3 timer clocks enable during Sleep and Stop modes 1 1 TIM4SMEN TIM4 timer clocks enable during Sleep and Stop modes 2 1 TIM5SMEN TIM5 timer clocks enable during Sleep and Stop modes 3 1 TIM6SMEN TIM6 timer clocks enable during Sleep and Stop modes 4 1 TIM7SMEN TIM7 timer clocks enable during Sleep and Stop modes 5 1 RTCAPBSMEN RTC APB clock enable during Sleep and Stop modes 10 1 WWDGSMEN Window watchdog clocks enable during Sleep and Stop modes 11 1 SPI2SMEN SPI2 clocks enable during Sleep and Stop modes 14 1 SP3SMEN SPI3 clocks enable during Sleep and Stop modes 15 1 USART2SMEN USART2 clocks enable during Sleep and Stop modes 17 1 USART3SMEN USART3 clocks enable during Sleep and Stop modes 18 1 UART4SMEN UART4 clocks enable during Sleep and Stop modes 19 1 UART5SMEN UART5 clocks enable during Sleep and Stop modes 20 1 I2C1SMEN I2C1 clocks enable during Sleep and Stop modes 21 1 I2C2SMEN I2C2 clocks enable during Sleep and Stop modes 22 1 I2C3SMEN I2C3 clocks enable during Sleep and Stop modes 23 1 CRSSMEN CRS clock enable during Sleep and Stop modes 24 1 PWRSMEN Power interface clocks enable during Sleep and Stop modes 28 1 DAC1SMEN DAC1 interface clocks enable during Sleep and Stop modes 29 1 OPAMPSMEN OPAMP interface clocks enable during Sleep and Stop modes 30 1 LPTIM1SMEN Low power timer 1 clocks enable during Sleep and Stop modes 31 1 APB1SMENR2 APB1SMENR2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x7C 0x20 read-write 0x00A00223 LPUART1SMEN Low power UART 1 clocks enable during Sleep and Stop modes 0 1 I2C4SMEN I2C4 clocks enable during Sleep and Stop modes 1 1 LPTIM2SMEN LPTIM2SMEN 5 1 LPTIM3SMEN LPTIM3SMEN 6 1 FDCAN1SMEN FDCAN1SMEN 9 1 USBFSSMEN USBFSSMEN 21 1 UCPD1SMEN UCPD1SMEN 23 1 APB2SMENR APB2SMENR APB2SMENR 0x80 0x20 read-write 0x01677801 SYSCFGSMEN SYSCFG clocks enable during Sleep and Stop modes 0 1 TIM1SMEN TIM1 timer clocks enable during Sleep and Stop modes 11 1 SPI1SMEN SPI1 clocks enable during Sleep and Stop modes 12 1 TIM8SMEN TIM8 timer clocks enable during Sleep and Stop modes 13 1 USART1SMEN USART1clocks enable during Sleep and Stop modes 14 1 TIM15SMEN TIM15 timer clocks enable during Sleep and Stop modes 16 1 TIM16SMEN TIM16 timer clocks enable during Sleep and Stop modes 17 1 TIM17SMEN TIM17 timer clocks enable during Sleep and Stop modes 18 1 SAI1SMEN SAI1 clocks enable during Sleep and Stop modes 21 1 SAI2SMEN SAI2 clocks enable during Sleep and Stop modes 22 1 DFSDM1SMEN DFSDM timer clocks enable during Sleep and Stop modes 24 1 CCIPR1 CCIPR1 CCIPR1 0x88 0x20 read-write 0x00000000 ADCSEL ADCs clock source selection 28 2 CLK48MSEL 48 MHz clock source selection 26 2 FDCANSEL FDCAN clock source selection 24 2 LPTIM3SEL Low-power timer 3 clock source selection 22 2 LPTIM2SEL Low power timer 2 clock source selection 20 2 LPTIM1SEL Low power timer 1 clock source selection 18 2 I2C3SEL I2C3 clock source selection 16 2 I2C2SEL I2C2 clock source selection 14 2 I2C1SEL I2C1 clock source selection 12 2 LPUART1SEL LPUART1 clock source selection 10 2 UART5SEL UART5 clock source selection 8 2 UART4SEL UART4 clock source selection 6 2 USART3SEL USART3 clock source selection 4 2 USART2SEL USART2 clock source selection 2 2 USART1SEL USART1 clock source selection 0 2 BDCR BDCR BDCR 0x90 0x20 0x00000000 LSCOSEL Low speed clock output selection 25 1 read-write LSCOSEL LSI LSI clock selected" 0 LSE LSE clock selected 1 LSCOEN Low speed clock output enable 24 1 read-write LSCOEN Disabled LSCO disabled 0 Enabled LSCO enabled 1 BDRST Backup domain software reset 16 1 read-write BDRST Disabled Reset not activated 0 Enabled Reset the entire RTC domain 1 RTCEN RTC clock enable 15 1 read-write RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 LSESYSRDY LSESYSRDY 11 1 read-write LSESYSRDYR read NotReady LSESYS clock not ready 0 Ready LSESYS clock ready 1 RTCSEL RTC clock source selection 8 2 read-write RTCSEL NoClock No clock 0 LSE LSE oscillator clock used as RTC clock 1 LSI LSI oscillator clock used as RTC clock 2 HSE HSE oscillator clock divided by a prescaler used as RTC clock 3 LSESYSEN LSESYSEN 7 1 read-write LSESYSEN Disabled LSESYS only enabled when requested by a peripheral or system function 0 Enabled LSESYS enabled always generated by RCC 1 LSECSSD LSECSSD 6 1 read-only LSECSSDR NoFailure No failure detected on LSE (32 kHz oscillator) 0 Failure Failure detected on LSE (32 kHz oscillator) 1 LSECSSON LSECSSON 5 1 read-write LSECSSON Off CSS on LSE (32 kHz external oscillator) OFF 0 On CSS on LSE (32 kHz external oscillator) ON 1 LSEDRV SE oscillator drive capability 3 2 read-write LSEDRV Lower 'Xtal mode' lower driving capability 0 MediumLow 'Xtal mode' medium low driving capability 1 MediumHigh 'Xtal mode' medium high driving capability 2 Higher 'Xtal mode' higher driving capability 3 LSEBYP LSE oscillator bypass 2 1 read-write LSEBYP NotBypassed LSE crystal oscillator not bypassed 0 Bypassed LSE crystal oscillator bypassed with external clock 1 LSERDY LSE oscillator ready 1 1 read-only LSERDYR NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEON LSE oscillator enable 0 1 read-write LSEON Off LSE oscillator Off 0 On LSE oscillator On 1 CSR CSR CSR 0x94 0x20 0x0C000600 OBLRSTF Option byte loader reset flag 25 1 read-only OBLRSTFR NoReset No reset has occured 0 Reset A reset has occured 1 LPWRSTF Low-power reset flag 31 1 read-only WWDGRSTF Window watchdog reset flag 30 1 read-only IWWDGRSTF Independent window watchdog reset flag 29 1 read-only SFTRSTF Software reset flag 28 1 read-only BORRSTF BOR flag 27 1 read-only PINRSTF Pin reset flag 26 1 read-only RMVF Remove reset flag 23 1 read-write RMVFW write Clear Clears the reset flag 1 MSISRANGE SI range after Standby mode 8 4 read-write LSIPREDIV LSIPREDIV 4 1 read-write LSIRDY LSI oscillator ready 1 1 read-only LSIRDYR NotReady LSI oscillator not ready 0 Ready LSI oscillator ready 1 LSION LSI oscillator enable 0 1 read-write LSION Off LSI oscillator Off 0 On LSI oscillator On 1 CRRCR CRRCR Clock recovery RC register 0x98 0x20 0x00000000 HSI48ON HSI48 clock enable 0 1 read-write HSI48RDY HSI48 clock ready flag 1 1 read-only HSI48CAL HSI48 clock calibration 7 9 read-only CCIPR2 CCIPR2 Peripherals independent clock configuration register 0x9C 0x20 read-write 0x00000000 I2C4SEL I2C4 clock source selection 0 2 DFSDMSEL Digital filter for sigma delta modulator kernel clock source selection 2 1 ADFSDMSEL Digital filter for sigma delta modulator audio clock source selection 3 2 SAI1SEL SAI1 clock source selection 5 3 SAI2SEL SAI2 clock source selection 8 3 SDMMCSEL SDMMC clock selection 14 1 OSPISEL Octospi clock source selection 20 2 SECCFGR SECCFGR RCC secure configuration register 0xB8 0x20 read-write 0x00000000 HSISEC HSISEC 0 1 HSESEC HSESEC 1 1 MSISEC MSISEC 2 1 LSISEC LSISEC 3 1 LSESEC LSESEC 4 1 SYSCLKSEC SYSCLKSEC 5 1 PRESCSEC PRESCSEC 6 1 PLLSEC PLLSEC 7 1 PLLSAI1SEC PLLSAI1SEC 8 1 PLLSAI2SEC PLLSAI2SEC 9 1 CLK48MSEC CLK48MSEC 10 1 HSI48SEC HSI48SEC 11 1 RMVFSEC RMVFSEC 12 1 SECSR SECSR RCC secure status register 0xBC 0x20 read-write 0x00000000 RMVFSECF RMVFSECF 12 1 HSI48SECF HSI48SECF 11 1 CLK48MSECF CLK48MSECF 10 1 PLLSAI2SECF PLLSAI2SECF 9 1 PLLSAI1SECF PLLSAI1SECF 8 1 PLLSECF PLLSECF 7 1 PRESCSECF PRESCSECF 6 1 SYSCLKSECF SYSCLKSECF 5 1 LSESECF LSESECF 4 1 LSISECF LSISECF 3 1 MSISECF MSISECF 2 1 HSESECF HSESECF 1 1 HSISECF HSISECF 0 1 AHB1SECSR AHB1SECSR RCC AHB1 security status register 0xE8 0x20 read-only 0x00400300 ICACHESECF ICACHESECF 23 1 GTZCSECF GTZCSECF 22 1 TSCSECF TSCSECF 16 1 CRCSECF CRCSECF 12 1 SRAM1SECF SRAM1SECF 9 1 FLASHSECF FLASHSECF 8 1 DMAMUX1SECF DMAMUX1SECF 2 1 DMA2SECF DMA2SECF 1 1 DMA1SECF DMA1SECF 0 1 AHB2SECSR AHB2SECSR RCC AHB2 security status register 0xEC 0x20 read-only 0x002002FF SDMMC1SECF SDMMC1SECF 22 1 OTFDEC1SECF OTFDEC1SECF 21 1 SRAM2SECF SRAM2SECF 9 1 GPIOHSECF GPIOHSECF 7 1 GPIOGSECF GPIOGSECF 6 1 GPIOFSECF GPIOFSECF 5 1 GPIOESECF GPIOESECF 4 1 GPIODSECF GPIODSECF 3 1 GPIOCSECF GPIOCSECF 2 1 GPIOBSECF GPIOBSECF 1 1 GPIOASECF GPIOASECF 0 1 AHB3SECSR AHB3SECSR RCC AHB3 security status register 0xF0 0x20 read-only 0x00000000 OSPI1SECF OSPI1SECF 8 1 FSMCSECF FSMCSECF 0 1 APB1SECSR1 APB1SECSR1 RCC APB1 security status register 1 0xF8 0x20 read-only 0x00000400 LPTIM1SECF LPTIM1SECF 31 1 OPAMPSECF OPAMPSECF 30 1 DACSECF DACSECF 29 1 PWRSECF PWRSECF 28 1 CRSSECF CRSSECF 24 1 I2C3SECF I2C3SECF 23 1 I2C2SECF I2C2SECF 22 1 I2C1SECF I2C1SECF 21 1 UART5SECF UART5SECF 20 1 UART4SECF UART4SECF 19 1 UART3SECF UART3SECF 18 1 UART2SECF UART2SECF 17 1 SPI3SECF SPI3SECF 15 1 SPI2SECF SPI2SECF 14 1 WWDGSECF WWDGSECF 11 1 RTCAPBSECF RTCAPBSECF 10 1 TIM7SECF TIM7SECF 5 1 TIM6SECF TIM6SECF 4 1 TIM5SECF TIM5SECF 3 1 TIM4SECF TIM4SECF 2 1 TIM3SECF TIM3SECF 1 1 TIM2SECF TIM2SECF 0 1 APB1SECSR2 APB1SECSR2 RCC APB1 security status register 2 0xFC 0x20 read-only 0x00000000 UCPD1SECF UCPD1SECF 23 1 USBFSSECF USBFSSECF 21 1 FDCAN1SECF FDCAN1SECF 9 1 LPTIM3SECF LPTIM3SECF 6 1 LPTIM2SECF LPTIM2SECF 5 1 I2C4SECF I2C4SECF 1 1 LPUART1SECF LPUART1SECF 0 1 APB2SECSR APB2SECSR RCC APB2 security status register 0x100 0x20 read-only 0x00000000 DFSDM1SECF DFSDM1SECF 24 1 SAI2SECF SAI2SECF 22 1 SAI1SECF SAI1SECF 21 1 TIM17SECF TIM17SECF 18 1 TIM16SECF TIM16SECF 17 1 TIM15SECF TIM15SECF 16 1 USART1SECF USART1SECF 14 1 TIM8SECF TIM8SECF 13 1 SPI1SECF SPI1SECF 12 1 TIM1SECF TIM1SECF 11 1 SYSCFGSECF SYSCFGSECF 0 1 SEC_RCC 0x50021000 RNG RNG RNG 0x420C0800 0x0 0x400 registers RNG RNG global interrupt 94 CR CR RNG control register 0x0 0x20 read-write 0x00000000 RNGEN Random number generator enable 2 1 RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 IE Interrupt enable 3 1 IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 CED Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled. 5 1 CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 RNG_CONFIG3 RNG configuration 3 8 4 RNG_CONFIG3 ConfigB Recommended value for config B (not NIST certifiable) 0 ConfigA Recommended value for config A (NIST certifiable) 13 NISTC Non NIST compliant 12 1 NISTC Default Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used 0 Custom Custom values for NIST compliant RNG 1 RNG_CONFIG2 RNG configuration 2 13 3 RNG_CONFIG2 ConfigA_B Recommended value for config A and B 0 CLKDIV Clock divider factor 16 4 CLKDIV Div1 Internal RNG clock after divider is similar to incoming RNG clock 0 Div2 Divide RNG clock by 2^1 1 Div4 Divide RNG clock by 2^2 2 Div8 Divide RNG clock by 2^3 3 Div16 Divide RNG clock by 2^4 4 Div32 Divide RNG clock by 2^5 5 Div64 Divide RNG clock by 2^6 6 Div128 Divide RNG clock by 2^7 7 Div256 Divide RNG clock by 2^8 8 Div512 Divide RNG clock by 2^9 9 Div1024 Divide RNG clock by 2^10 10 Div2048 Divide RNG clock by 2^11 11 Div4096 Divide RNG clock by 2^12 12 Div8192 Divide RNG clock by 2^13 13 Div16384 Divide RNG clock by 2^14 14 Div32768 Divide RNG clock by 2^15 15 RNG_CONFIG1 RNG configuration 1 20 6 RNG_CONFIG1 ConfigA Recommended value for config A (NIST certifiable) 15 ConfigB Recommended value for config B (not NIST certifiable) 24 CONDRST Conditioning soft reset 30 1 CONFIGLOCK RNG Config Lock 31 1 CONFIGLOCK Enabled Writes to the RNG_CR configuration bits [29:4] are allowed 0 Disabled Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset 1 SR SR RNG status register 0x4 0x20 0x00000000 DRDY Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated. 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 CECS Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1. 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 SECS Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CEIS Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1. 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register. 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 DR DR The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0. 0x8 0x20 read-only 0x00000000 RNDATA Random data 32-bit random data which are valid when DRDY=1. 0 32 0 4294967295 HTCR HTCR The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0. 0x10 0x20 read-write 0x000CAA74 HTCFG health test configuration 0 32 HTCFG Recommended Recommended value for RNG certification (0x0000_AA74) 43636 Magic Magic number to be written before any write (0x1759_0ABC) 391711420 SEC_RNG 0x520C0800 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC RTC global interrupts (EXTI line 17) 2 RTC_S RTC secure global interrupts (EXTI line 18) 3 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 0 15 YU Year units in BCD format 16 4 0 15 WDU Week day units 13 3 1 7 MT Month tens in BCD format 12 1 0 1 MU Month units in BCD format 8 4 0 15 DT Date tens in BCD format 4 2 0 3 DU Date units in BCD format 0 4 0 15 SSR SSR RTC sub second register 0x8 0x20 read-only 0x00000000 SS SS 0 16 0 65535 ICSR ICSR RTC initialization control and status register 0xC 0x20 0x00000007 2 0x1 A,B ALR%sWF Alarm %s write flag 0 1 read-only WUTWF Wakeup timer write flag 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending 3 1 read-write SHPFR read NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 RECALPF Recalibration pending Flag 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 0 127 PREDIV_S Synchronous prescaler factor 0 15 0 32767 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 0 65535 WUTOCLR WUTOCLR 16 16 CR CR RTC control register 0x18 0x20 read-write 0x00000000 WUCKSEL WUCKSEL 0 3 WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE TSEDGE 3 1 TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON REFCKON 4 1 REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD BYPSHAD 5 1 BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT FMT 6 1 FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 2 0x1 A,B ALR%sE Alarm %s enable 8 1 ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE WUTE 10 1 WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE TSE 11 1 TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE WUTIE 14 1 WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE TSIE 15 1 TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H ADD1H 16 1 ADD1HW write Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H SUB1H 17 1 SUB1HW write Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP BKP 18 1 BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 COSEL COSEL 19 1 COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL POL 20 1 POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL OSEL 21 2 OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE COE 23 1 COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ITSE ITSE 24 1 ITSE Disabled Internal event timestamp disabled 0 Enabled Internal event timestamp enabled 1 TAMPTS TAMPTS 25 1 TAMPTS Disabled Tamper detection event does not cause a RTC timestamp to be saved 0 Enabled Save RTC timestamp on tamper detection event 1 TAMPOE TAMPOE 26 1 TAMPOE Disabled The tamper flag is not routed on TAMPALRM 0 Enabled The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL 1 TAMPALRM_PU TAMPALRM_PU 29 1 TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPALRM_TYPE TAMPALRM_TYPE 30 1 TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 OUT2EN OUT2EN 31 1 OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 PRIVCR PRIVCR RTC privilege mode control register 0x1C 0x20 read-write 0x00000000 PRIV PRIV 15 1 INITPRIV INITPRIV 14 1 CALPRIV CALPRIV 13 1 TSPRIV TSPRIV 3 1 WUTPRIV WUTPRIV 2 1 ALRBPRIV ALRBPRIV 1 1 ALRAPRIV ALRAPRIV 0 1 SMCR SMCR RTC secure mode control register 0x20 0x20 read-write 0x0000E00F DECPROT DECPROT 15 1 INITDPROT INITDPROT 14 1 CALDPROT CALDPROT 13 1 TSDPROT TSDPROT 3 1 WUTDPROT WUTDPROT 2 1 ALRBDPROT ALRBDPROT 1 1 ALRADPROT ALRADPROT 0 1 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR calibration register 0x28 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW8 EightSeconds When CALW8 is set to â1â, the 8-second calibration cycle period is selected 1 CALW16 Use a 16-second calibration cycle period 13 1 CALW16 SixteenSeconds When CALW16 is set to â1â, the 16-second calibration cycle period is selected.This bit must not be set to â1â if CALW8=1 1 LPCAL LPCAL 12 1 CALM Calibration minus 0 9 0 511 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 SUBFS Subtract a fraction of a second 0 15 0 32767 TSTR TSTR time stamp time register 0x30 TSDR TSDR time stamp date register 0x34 TSSSR TSSSR timestamp sub second register 0x38 2 0x8 A,B ALRM%sR ALRM%sR Alarm %s register 0x40 0x20 read-write 0x00000000 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day donât care in Alarm comparison 1 MSK4 Alarm date mask 31 1 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is donât care. 1 DT Date tens in BCD format 28 2 0 3 DU Date units or day in BCD format 24 4 0 15 MSK3 Alarm hours mask 23 1 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MSK2 Alarm minutes mask 15 1 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 2 0x8 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 0 32767 SR SR RTC status register 0x50 0x20 read-only 0x00000000 2 0x1 A,B ALR%sF Alarm %s flag 0 1 ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 WUTF WUTF 2 1 WUTF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSF TSF 3 1 TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVF TSOVF 4 1 TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSF ITSF 5 1 ITSF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 MISR MISR RTC non-secure masked interrupt status register 0x54 0x20 read-only 0x00000000 2 0x1 A,B ALR%sMF Alarm %s masked flag 0 1 ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 WUTMF WUTMF 2 1 WUTMF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSMF TSMF 3 1 TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVMF TSOVMF 4 1 TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSMF ITSMF 5 1 ITSMF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SMISR SMISR RTC secure masked interrupt status register 0x58 0x20 read-only 0x00000000 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 WUTMF WUTMF 2 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 ITSMF ITSMF 5 1 SCR SCR RTC status clear register 0x5C 0x20 write-only 0x00000000 CALRAF CALRAF 0 1 CALRAF Clear Clear interrupt flag 1 CALRBF CALRBF 1 1 CWUTF CWUTF 2 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CITSF CITSF 5 1 SEC_RTC 0x50002800 SAI1 Serial audio interface SAI 0x40015400 0x0 0x400 registers SAI1 SAI1 global interrupt 90 2 0x20 A,B CH%s Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR 0x4 CR1 ACR1 AConfiguration register 1 0x0 0x20 read-write 0x00000040 MCKDIV Master clock divider 20 4 NODIV No divider 19 1 NODIV MasterClock MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value 0 NoDiv MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. 1 DMAEN DMA enable 17 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 SAIEN Audio block A enable 16 1 SAIEN Disabled SAI audio block disabled 0 Enabled SAI audio block enabled 1 OUTDRIV Output drive 13 1 OUTDRIV OnStart Audio block output driven when SAIEN is set 0 Immediately Audio block output driven immediately after the setting of this bit 1 MONO Mono mode 12 1 MONO Stereo Stereo mode 0 Mono Mono mode 1 SYNCEN Synchronization enable 10 2 SYNCEN Asynchronous audio sub-block in asynchronous mode 0 Internal audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode 1 External audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode 2 CKSTR Clock strobing edge 9 1 CKSTR FallingEdge Data strobing edge is falling edge of SCK 0 RisingEdge Data strobing edge is rising edge of SCK 1 LSBFIRST Least significant bit first 8 1 LSBFIRST MsbFirst Data are transferred with MSB first 0 LsbFirst Data are transferred with LSB first 1 DS Data size 5 3 DS Bit8 8 bits 2 Bit10 10 bits 3 Bit16 16 bits 4 Bit20 20 bits 5 Bit24 24 bits 6 Bit32 32 bits 7 PRTCFG Protocol configuration 2 2 PRTCFG Free Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol 0 Spdif SPDIF protocol 1 Ac97 ACâ97 protocol 2 MODE Audio block mode 0 2 MODE MasterTx Master transmitter 0 MasterRx Master receiver 1 SlaveTx Slave transmitter 2 SlaveRx Slave receiver 3 OSR OSR 26 1 CR2 ACR2 AConfiguration register 2 0x4 0x20 read-write 0x00000000 COMP Companding mode 14 2 read-write COMP NoCompanding No companding algorithm 0 MuLaw Î¼-Law algorithm 2 ALaw A-Law algorithm 3 CPL Complement bit 13 1 read-write CPL OnesComplement 1âs complement representation 0 TwosComplement 2âs complement representation 1 MUTECNT Mute counter 7 6 read-write MUTEVAL Mute value 6 1 read-write MUTEVAL SendZero Bit value 0 is sent during the mute mode 0 SendLast Last values are sent during the mute mode 1 MUTE Mute 5 1 read-write MUTE Disabled No mute mode 0 Enabled Mute mode enabled 1 TRIS Tristate management on data line 4 1 read-write FFLUSH FIFO flush 3 1 write-only FFLUSH NoFlush No FIFO flush 0 Flush FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared 1 FTH FIFO threshold 0 3 read-write FTH Empty FIFO empty 0 Quarter1 1â4 FIFO 1 Quarter2 1â2 FIFO 2 Quarter3 3â4 FIFO 3 Full FIFO full 4 FRCR AFRCR AFRCR 0x8 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 read-write FSOFF OnFirst FS is asserted on the first bit of the slot 0 0 BeforeFirst FS is asserted one bit before the first bit of the slot 0 1 FSPOL Frame synchronization polarity 17 1 read-write FSPOL FallingEdge FS is active low (falling edge) 0 RisingEdge FS is active high (rising edge) 1 FSDEF Frame synchronization definition 16 1 read-write FSALL Frame synchronization active level length 8 7 read-write FRL Frame length 0 8 read-write SLOTR ASLOTR ASlot register 0xC 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 SLOTEN Inactive Inactive slot 0 Active Active slot 1 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 SLOTSZ DataSize The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) 0 Bit16 16-bit 1 Bit32 32-bit 2 FBOFF First bit offset 0 5 IM AIM AInterrupt mask register2 0x10 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 LFSDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 AFSDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 CNRDYIE Codec not ready interrupt enable 4 1 CNRDYIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 FREQIE FIFO request interrupt enable 3 1 FREQIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 WCKCFGIE Wrong clock configuration interrupt enable 2 1 WCKCFGIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 MUTEDETIE Mute detection interrupt enable 1 1 MUTEDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 OVRUDRIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 SR ASR AStatus register 0x14 0x20 read-only 0x00000008 FLVL FIFO level threshold 16 3 FLVLR Empty FIFO empty 0 Quarter1 FIFO <= 1â4 but not empty 1 Quarter2 1â4 < FIFO <= 1â2 2 Quarter3 1â2 < FIFO <= 3â4 3 Quarter4 3â4 < FIFO but not full 4 Full FIFO full 5 LFSDET Late frame synchronization detection 6 1 LFSDETR NoError No error 0 NoSync Frame synchronization signal is not present at the right time 1 AFSDET Anticipated frame synchronization detection 5 1 AFSDETR NoError No error 0 EarlySync Frame synchronization signal is detected earlier than expected 1 CNRDY Codec not ready 4 1 CNRDYR Ready External ACâ97 Codec is ready 0 NotReady External ACâ97 Codec is not ready 1 FREQ FIFO request 3 1 FREQR NoRequest No FIFO request 0 Request FIFO request to read or to write the SAI_xDR 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 WCKCFGR Correct Clock configuration is correct 0 Wrong Clock configuration does not respect the rule concerning the frame length specification 1 MUTEDET Mute detection 1 1 MUTEDETR NoMute No MUTE detection on the SD input line 0 Mute MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame 1 OVRUDR Overrun / underrun 0 1 OVRUDRR NoError No overrun/underrun error 0 Overrun Overrun/underrun error detection 1 CLRFR ACLRFR AClear flag register 0x18 0x20 write-only 0x00000000 CLFSDET Clear late frame synchronization detection flag 6 1 CLFSDETW Clear Clears the LFSDET flag 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CAFSDETW Clear Clears the AFSDET flag 1 CCNRDY Clear codec not ready flag 4 1 CCNRDYW Clear Clears the CNRDY flag 1 CWCKCFG Clear wrong clock configuration flag 2 1 CWCKCFGW Clear Clears the WCKCFG flag 1 CMUTEDET Mute detection flag 1 1 CMUTEDETW Clear Clears the MUTEDET flag 1 COVRUDR Clear overrun / underrun 0 1 COVRUDRW Clear Clears the OVRUDR flag 1 DR ADR AData register 0x1C 0x20 read-write 0x00000000 DATA Data 0 32 GCR GCR Global configuration register 0x0 0x20 read-write 0x00000000 SYNCIN Synchronization inputs 0 2 SYNCOUT Synchronization outputs 4 2 PDMCR PDMCR PDM control register 0x44 0x20 read-write 0x00000000 PDMEN PDM enable 0 1 MICNBR MICNBR 4 2 2 0x1 1-2 CKEN%s Clock enable of bitstream clock number %s 8 1 PDMDLY PDMDLY PDM delay register 0x48 0x20 read-write 0x00000000 4 0x8 1-4 DLYM%sL Delay line adjust for first microphone of pair %s 0 3 4 0x8 1-4 DLYM%sR Delay line adjust for second microphone of pair %s 4 3 SAI2 0x40015800 SAI2 SAI2 global interrupt 91 SEC_SAI1 0x50015400 SEC_SAI2 0x50015800 SDMMC1 SDMMC1 SDMMC 0x420C8000 0x0 0x3FD registers SDMMC1 SDMMC1 global interrupt 78 POWER POWER SDMMC power control register 0x0 0x20 read-write 0x00000000 PWRCTRL SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11. 0 2 VSWITCH Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence: 2 1 VSWITCHEN Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response: 3 1 DIRPOL Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). 4 1 CLKCR CLKCR The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width. 0x4 0x20 read-write 0x00000000 CLKDIV Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.. 0 10 PWRSAV Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: 12 1 WIDBUS Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 14 2 NEGEDGE SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. 16 1 HWFC_EN Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11. 17 1 DDR Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0) 18 1 BUSSPEED Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 19 1 SELCLKRX Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 20 2 ARGR ARGR The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 0x8 0x20 read-write 0x00000000 CMDARG Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. 0 32 CMDR CMDR The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 0xC 0x20 read-write 0x00000000 CMDINDEX Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. 0 6 CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. 6 1 CMDSTOP The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent. 7 1 WAITRESP Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 8 2 WAITINT CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode. 10 1 WAITPEND CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. 11 1 CPSMEN Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0. 12 1 DTHOLD Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. 13 1 BOOTMODE Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) 14 1 BOOTEN Enable boot mode procedure. 15 1 CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. 16 1 4 0x4 1-4 RESP%sR RESP%sR SDMMC response %s register 0x14 0x20 read-only 0x00000000 CARDSTATUS Status of a card, which is part of the received response 0 32 DTIMER DTIMER The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 0x24 0x20 read-write 0x00000000 DATATIME Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. 0 32 DLENR DLENR The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0. 0 25 DCTRL DCTRL The SDMMC_DCTRL register control the data path state machine (DPSM). 0x2C 0x20 read-write 0x00000000 DTEN Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. 0 1 DTDIR Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 DTMODE Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 2 2 DBLOCKSIZE Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered) 4 4 RWSTART Read wait start. If this bit is set, read wait operation starts. 8 1 RWSTOP Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. 9 1 RWMOD Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 10 1 SDIOEN SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. 11 1 BOOTACKEN Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 12 1 FIFORST FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. 13 1 DCNTR DCNTR The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. 0 25 STAR STAR The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 0x34 0x20 read-only 0x00000000 CCRCFAIL Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 0 1 DCRCFAIL Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 1 1 CTIMEOUT Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. 2 1 DTIMEOUT Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 3 1 TXUNDERR Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 4 1 RXOVERR Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 5 1 CMDREND Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 6 1 CMDSENT Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 7 1 DATAEND Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 8 1 DHOLD Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 9 1 DBCKEND Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 10 1 DABORT Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 11 1 DPSMACT Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 12 1 CPSMACT Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 13 1 TXFIFOHE Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. 14 1 RXFIFOHF Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. 15 1 TXFIFOF Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. 16 1 RXFIFOF Receive FIFO full This bit is cleared when one FIFO location becomes empty. 17 1 TXFIFOE Transmit FIFO empty This bit is cleared when one FIFO location becomes full. 18 1 RXFIFOE Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. 19 1 BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. 20 1 BUSYD0END end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 21 1 SDIOIT SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 22 1 ACKFAIL Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 23 1 ACKTIMEOUT Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 24 1 VSWEND Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 25 1 CKSTOP SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 26 1 IDMATE IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 27 1 IDMABTC IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 28 1 ICR ICR The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 0x38 0x20 read-write 0x00000000 CCRCFAILC CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. 0 1 DCRCFAILC DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 1 1 CTIMEOUTC CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 2 1 DTIMEOUTC DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. 3 1 TXUNDERRC TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. 4 1 RXOVERRC RXOVERR flag clear bit Set by software to clear the RXOVERR flag. 5 1 CMDRENDC CMDREND flag clear bit Set by software to clear the CMDREND flag. 6 1 CMDSENTC CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 7 1 DATAENDC DATAEND flag clear bit Set by software to clear the DATAEND flag. 8 1 DHOLDC DHOLD flag clear bit Set by software to clear the DHOLD flag. 9 1 DBCKENDC DBCKEND flag clear bit Set by software to clear the DBCKEND flag. 10 1 DABORTC DABORT flag clear bit Set by software to clear the DABORT flag. 11 1 BUSYD0ENDC BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. 21 1 SDIOITC SDIOIT flag clear bit Set by software to clear the SDIOIT flag. 22 1 ACKFAILC ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. 23 1 ACKTIMEOUTC ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. 24 1 VSWENDC VSWEND flag clear bit Set by software to clear the VSWEND flag. 25 1 CKSTOPC CKSTOP flag clear bit Set by software to clear the CKSTOP flag. 26 1 IDMATEC IDMA transfer error clear bit Set by software to clear the IDMATE flag. 27 1 IDMABTCC IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. 28 1 MASKR MASKR The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x3C 0x20 read-write 0x00000000 CCRCFAILIE Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0 1 DCRCFAILIE Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 1 1 CTIMEOUTIE Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 2 1 DTIMEOUTIE Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 3 1 TXUNDERRIE Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 4 1 RXOVERRIE Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 5 1 CMDRENDIE Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 6 1 CMDSENTIE Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 7 1 DATAENDIE Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 8 1 DHOLDIE Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. 9 1 DBCKENDIE Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 10 1 DABORTIE Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. 11 1 TXFIFOHEIE Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 14 1 RXFIFOHFIE Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 15 1 RXFIFOFIE Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 17 1 TXFIFOEIE Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 18 1 BUSYD0ENDIE BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. 21 1 SDIOITIE SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 22 1 ACKFAILIE Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. 23 1 ACKTIMEOUTIE Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. 24 1 VSWENDIE Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. 25 1 CKSTOPIE Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. 26 1 IDMABTCIE IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. 28 1 ACKTIMER ACKTIMER The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 0x40 0x20 read-write 0x00000000 ACKTIME Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. 0 25 IDMACTRLR IDMACTRLR The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 0x50 0x20 read-write 0x00000000 IDMAEN IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 1 IDMABMODE Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 IDMABACT Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. 2 1 IDMABSIZER IDMABSIZER The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. 0x54 0x20 read-write 0x00000000 IDMABNDT Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). 5 8 IDMABASE0R IDMABASE0R The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. 0x58 0x20 read-write 0x00000000 IDMABASE0 Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1). 0 32 IDMABASE1R IDMABASE1R The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. 0x5C 0x20 read-write 0x00000000 IDMABASE1 Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0). 0 32 FIFOR FIFOR The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x80 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words. 0 32 RESPCMDR RESPCMDR SDMMC command response register 0x10 0x20 read-only 0xA3C5DD01 RESPCMD Response command index 0 6 SEC_SDMMC1 0x520C8000 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 59 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 CRCL CRC length 11 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 NSSP NSS pulse management 3 1 FRF Frame format 4 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 DS Data size 8 4 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 SR SR status register 0x8 0x10 0x00000002 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 TIFRFE TI frame format error 8 1 read-only FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 SPI2 0x40003800 SPI2 SPI2 global interrupt 60 SPI3 0x40003C00 SPI3 SPI3 99 SEC_SPI1 0x50013000 SEC_SPI2 0x50003800 SEC_SPI3 0x50003C00 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x30 registers SECCFGR SECCFGR SYSCFG secure configuration register 0x0 0x20 read-write 0x00000000 SRAM2SEC SRAM2 security 2 1 CLASSBSEC ClassB security 1 1 SYSCFGSEC SYSCFG clock control security 0 1 FPUSEC FPUSEC 3 1 CFGR1 CFGR1 configuration register 1 0x4 0x20 read-write 0x00000000 I2C4_FMP I2C4_FMP 23 1 I2C3_FMP I2C3 Fast-mode Plus driving capability activation 22 1 I2C2_FMP I2C2 Fast-mode Plus driving capability activation 21 1 I2C1_FMP I2C1 Fast-mode Plus driving capability activation 20 1 I2C_PB9_FMP Fast-mode Plus (Fm+) driving capability activation on PB9 19 1 I2C_PB8_FMP Fast-mode Plus (Fm+) driving capability activation on PB8 18 1 I2C_PB7_FMP Fast-mode Plus (Fm+) driving capability activation on PB7 17 1 I2C_PB6_FMP Fast-mode Plus (Fm+) driving capability activation on PB6 16 1 BOOSTEN I/O analog switch voltage booster enable 8 1 ANASWVDD GPIO analog switch control voltage selection 9 1 FPUIMR FPUIMR FPU interrupt mask register 0x8 0x20 read-write 0x0000001F FPU_IE Floating point unit interrupts enable bits 0 6 CNSLCKR CNSLCKR SYSCFG CPU non-secure lock register 0xC 0x20 read-write 0x00000000 LOCKNSVTOR VTOR_NS register lock 0 1 LOCKNSMPU Non-secure MPU registers lock 1 1 CSLOCKR CSLOCKR SYSCFG CPU secure lock register 0x10 0x20 read-write 0x00000000 LOCKSVTAIRCR LOCKSVTAIRCR 0 1 LOCKSMPU LOCKSMPU 1 1 LOCKSAU LOCKSAU 2 1 SCSR SCSR SCSR 0x18 0x20 0x00000000 SRAM2BSY SRAM2 busy by erase operation 1 1 read-only SRAM2ER SRAM2 Erase 0 1 read-write CFGR2 CFGR2 CFGR2 0x14 0x20 0x00000000 SPF SRAM2 parity error flag 8 1 read-write ECCL ECC Lock 3 1 write-only PVDL PVD lock enable bit 2 1 write-only SPL SRAM2 parity lock bit 1 1 write-only CLL LOCKUP (hardfault) output enable bit 0 1 write-only SWPR SWPR SWPR 0x20 0x20 write-only 0x00000000 P31WP SRAM2 page 31 write protection 31 1 P30WP P30WP 30 1 P29WP P29WP 29 1 P28WP P28WP 28 1 P27WP P27WP 27 1 P26WP P26WP 26 1 P25WP P25WP 25 1 P24WP P24WP 24 1 P23WP P23WP 23 1 P22WP P22WP 22 1 P21WP P21WP 21 1 P20WP P20WP 20 1 P19WP P19WP 19 1 P18WP P18WP 18 1 P17WP P17WP 17 1 P16WP P16WP 16 1 P15WP P15WP 15 1 P14WP P14WP 14 1 P13WP P13WP 13 1 P12WP P12WP 12 1 P11WP P11WP 11 1 P10WP P10WP 10 1 P9WP P9WP 9 1 P8WP P8WP 8 1 P7WP P7WP 7 1 P6WP P6WP 6 1 P5WP P5WP 5 1 P4WP P4WP 4 1 P3WP P3WP 3 1 P2WP P2WP 2 1 P1WP P1WP 1 1 P0WP P0WP 0 1 SKR SKR SKR 0x1C 0x20 write-only 0x00000000 KEY SRAM2 write protection key for software erase 0 8 SWPR2 SWPR2 SWPR2 0x24 0x20 write-only 0x00000000 P32WP P32WP 0 1 P33WP P33WP 1 1 P34WP P34WP 2 1 P35WP P35WP 3 1 P36WP P36WP 4 1 P37WP P37WP 5 1 P38WP P38WP 6 1 P39WP P39WP 7 1 P40WP P40WP 8 1 P41WP P41WP 9 1 P42WP P42WP 10 1 P43WP P43WP 11 1 P44WP P44WP 12 1 P45WP P45WP 13 1 P46WP P46WP 14 1 P47WP P47WP 15 1 P48WP P48WP 16 1 P49WP P49WP 17 1 P50WP P50WP 18 1 P51WP P51WP 19 1 P52WP P52WP 20 1 P53WP P53WP 21 1 P54WP P54WP 22 1 P55WP P55WP 23 1 P56WP P56WP 24 1 P57WP P57WP 25 1 P58WP P58WP 26 1 P59WP P59WP 27 1 P60WP P60WP 28 1 P61WP P61WP 29 1 P62WP P62WP 30 1 P63WP P63WP 31 1 RSSCMDR RSSCMDR RSSCMDR 0x2C 0x20 read-write 0x00000000 RSSCMD RSS commands 0 8 SEC_SYSCFG 0x50010000 TAMP Tamper and backup registers TAMP 0x40003400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0xFFFF0000 TAMP1E TAMP1E 0 1 TAMP2E TAMP2E 1 1 TAMP3E TAMP3E 2 1 TAMP4E TAMP4E 3 1 TAMP5E TAMP5E 4 1 TAMP6E TAMP6E 5 1 TAMP7E TAMP7E 6 1 TAMP8E TAMP8E 7 1 ITAMP1E ITAMP1E 16 1 ITAMP2E ITAMP2E 17 1 ITAMP3E ITAMP3E 18 1 ITAMP5E ITAMP5E 20 1 ITAMP8E ITAMP5E 23 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 TAMP1NOER TAMP1NOER 0 1 TAMP2NOER TAMP2NOER 1 1 TAMP3NOER TAMP3NOER 2 1 TAMP4NOER TAMP4NOER 3 1 TAMP5NOER TAMP5NOER 4 1 TAMP6NOER TAMP6NOER 5 1 TAMP7NOER TAMP7NOER 6 1 TAMP8NOER TAMP8NOER 7 1 TAMP1MSK TAMP1MSK 16 1 TAMP2MSK TAMP2MSK 17 1 TAMP3MSK TAMP3MSK 18 1 BKERASE BKERASE 23 1 TAMP1TRG TAMP1TRG 24 1 TAMP2TRG TAMP2TRG 25 1 TAMP3TRG TAMP3TRG 26 1 TAMP4TRG TAMP4TRG 27 1 TAMP5TRG TAMP5TRG 28 1 TAMP6TRG TAMP6TRG 29 1 TAMP7TRG TAMP7TRG 30 1 TAMP8TRG TAMP8TRG 31 1 CR3 CR3 control register 3 0x8 0x20 read-write 0x00000000 ITAMP1NOER ITAMP1NOER 0 1 ITAMP2NOER ITAMP2NOER 1 1 ITAMP3NOER ITAMP3NOER 2 1 ITAMP5NOER ITAMP5NOER 4 1 ITAMP8NOER ITAMP8NOER 7 1 FLTCR FLTCR TAMP filter control register 0xC 0x20 read-write 0x00000000 TAMPFREQ TAMPFREQ 0 3 TAMPFLT TAMPFLT 3 2 TAMPPRCH TAMPPRCH 5 2 TAMPPUDIS TAMPPUDIS 7 1 ATCR1 ATCR1 TAMP active tamper control register 1 0x10 0x20 read-write 0x00070000 TAMP1AM TAMP1AM 0 1 TAMP2AM TAMP2AM 1 1 TAMP3AM TAMP3AM 2 1 TAMP4AM TAMP4AM 3 1 TAMP5AM TAMP5AM 4 1 TAMP6AM TAMP6AM 5 1 TAMP7AM TAMP7AM 6 1 TAMP8AM TAMP8AM 7 1 ATOSEL1 ATOSEL1 8 2 ATOSEL2 ATOSEL2 10 2 ATOSEL3 ATOSEL3 12 2 ATOSEL4 ATOSEL4 14 2 ATCKSEL ATCKSEL 16 2 ATPER ATPER 24 2 ATOSHARE ATOSHARE 30 1 FLTEN FLTEN 31 1 ATSEEDR ATSEEDR TAMP active tamper seed register 0x14 0x20 write-only 0x00000000 SEED Pseudo-random generator seed value 0 32 ATOR ATOR TAMP active tamper output register 0x18 0x20 read-only 0x00000000 PRNG Pseudo-random generator value 0 8 SEEDF Seed running flag 14 1 INITS Active tamper initialization status 15 1 ATCR2 ATCR2 TAMP active tamper control register 2 0x1C 0x20 read-write 0x00000000 ATOSEL1 ATOSEL1 8 3 ATOSEL2 ATOSEL2 11 3 ATOSEL3 ATOSEL3 14 3 ATOSEL4 ATOSEL4 17 3 ATOSEL5 ATOSEL5 20 3 ATOSEL6 ATOSEL6 23 3 ATOSEL7 ATOSEL7 26 3 ATOSEL8 ATOSEL8 29 3 SMCR SMCR TAMP secure mode register 0x20 0x20 read-write 0x00000000 BKPRWDPROT Backup registers read/write protection offset 0 8 BKPWDPROT Backup registers write protection offset 16 8 TAMPDPROT Tamper protection 31 1 PRIVCR PRIVCR TAMP privilege mode control register 0x24 0x20 read-write 0x00000000 BKPRWPRIV Backup registers zone 1 privilege protection 29 1 BKPWPRIV Backup registers zone 2 privilege protection 30 1 TAMPPRIV Tamper privilege protection 31 1 IER IER TAMP interrupt enable register 0x2C 0x20 read-write 0x00000000 TAMP1IE TAMP1IE 0 1 TAMP2IE TAMP2IE 1 1 TAMP3IE TAMP3IE 2 1 TAMP4IE TAMP4IE 3 1 TAMP5IE TAMP5IE 4 1 TAMP6IE TAMP6IE 5 1 TAMP7IE TAMP7IE 6 1 TAMP8IE TAMP8IE 7 1 ITAMP1IE ITAMP1IE 16 1 ITAMP2IE ITAMP2IE 17 1 ITAMP3IE ITAMP3IE 18 1 ITAMP5IE ITAMP5IE 20 1 ITAMP8IE ITAMP8IE 23 1 SR SR TAMP status register 0x30 0x20 read-only 0x00000000 TAMP1F TAMP1F 0 1 TAMP2F TAMP2F 1 1 TAMP3F TAMP3F 2 1 TAMP4F TAMP4F 3 1 TAMP5F TAMP5F 4 1 TAMP6F TAMP6F 5 1 TAMP7F TAMP7F 6 1 TAMP8F TAMP8F 7 1 ITAMP1F ITAMP1F 16 1 ITAMP2F ITAMP2F 17 1 ITAMP3F ITAMP3F 18 1 ITAMP5F ITAMP5F 20 1 ITAMP8F ITAMP8F 23 1 MISR MISR TAMP masked interrupt status register 0x34 0x20 read-only 0x00000000 TAMP1MF TAMP1MF: 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 TAMP4MF TAMP4MF 3 1 TAMP5MF TAMP5MF 4 1 TAMP6MF TAMP6MF 5 1 TAMP7MF TAMP7MF: 6 1 TAMP8MF TAMP8MF 7 1 ITAMP1MF ITAMP1MF 16 1 ITAMP2MF ITAMP2MF 17 1 ITAMP3MF ITAMP3MF 18 1 ITAMP5MF ITAMP5MF 20 1 ITAMP8MF ITAMP8MF 23 1 SMISR SMISR TAMP secure masked interrupt status register 0x38 0x20 read-only 0x00000000 TAMP1MF TAMP1MF: 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 TAMP4MF TAMP4MF 3 1 TAMP5MF TAMP5MF 4 1 TAMP6MF TAMP6MF 5 1 TAMP7MF TAMP7MF: 6 1 TAMP8MF TAMP8MF 7 1 ITAMP1MF ITAMP1MF 16 1 ITAMP2MF ITAMP2MF 17 1 ITAMP3MF ITAMP3MF 18 1 ITAMP5MF ITAMP5MF 20 1 ITAMP8MF ITAMP8MF 23 1 SCR SCR TAMP status clear register 0x3C 0x20 write-only 0x00000000 CTAMP1F CTAMP1F 0 1 CTAMP2F CTAMP2F 1 1 CTAMP3F CTAMP3F 2 1 CTAMP4F CTAMP4F 3 1 CTAMP5F CTAMP5F 4 1 CTAMP6F CTAMP6F 5 1 CTAMP7F CTAMP7F 6 1 CTAMP8F CTAMP8F 7 1 CITAMP1F CITAMP1F 16 1 CITAMP2F CITAMP2F 17 1 CITAMP3F CITAMP3F 18 1 CITAMP5F CITAMP5F 20 1 CITAMP8F CITAMP8F 23 1 COUNTR COUNTR TAMP monotonic counter register 0x40 0x20 read-only 0x00000000 COUNT COUNT 0 32 CFGR CFGR TAMP configuration register 0x50 0x20 read-write 0x00000000 TMONEN TMONEN 1 1 VMONEN VMONEN 2 1 WUTMONEN WUTMONEN 3 1 32 0x4 0-31 BKP%sR BKP%sR TAMP backup register 0x100 0x20 read-write 0x00000000 BKP BKP 0 32 SEC_TAMP 0x50003400 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK TIM1 Break 41 TIM1_UP TIM1 Update 42 TIM1_TRG_COM TIM1 Trigger and Commutation 43 TIM1_CC TIM1 Capture Compare interrupt 44 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 3 0x2 1-3 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 MMS2 Master mode selection 2 20 4 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 SBIF System Break interrupt flag 13 1 zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 CC5IF Compare 5 interrupt flag 16 1 zeroToClear read write CC6IF Compare 6 interrupt flag 17 1 zeroToClear read write EGR EGR event generation register 0x14 0x20 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 B2G Break 2 generation 8 1 B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 3 0x4 1-3 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 DTG Dead-time generator setup 0 8 0 255 BKF Break filter 16 4 BK2F Break 2 filter 20 4 BK2E Break 2 enable 24 1 BK2P Break 2 polarity 25 1 BKDSRM Break Disarm 26 1 BK2DSRM Break2 Disarm 27 1 BKBID Break Bidirectional 28 1 BK2BID Break2 bidirectional 29 1 DCR DCR DMA control register 0x48 0x20 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 OR1 OR1 DMA address for full transfer 0x50 0x20 read-write 0x00000000 ETR_ADC1_RMP External trigger remap on ADC1 analog watchdog 0 2 TI1_RMP Input Capture 1 remap 4 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 0x20 read-write 0x00000000 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 2 0x8 5-6 OC%sM Output compare %s mode 4 3 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 CCR5 CCR5 capture/compare register 0x58 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 0x5C 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 OR2 OR2 DMA address for full transfer 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDFBK0E BRK DFSDM_BREAK0 enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 ETRSEL ETR source selection 14 3 OR3 OR3 DMA address for full transfer 0x64 0x20 read-write 0x00000001 BK2INE BRK2 BKIN input enable 0 1 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2DFBK0E BRK2 DFSDM_BREAK0 enable 8 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 SEC_TIM1 0x50012C00 TIM2 General-purpose-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 45 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Counter value 0 32 0 4294967295 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR Auto-reload value 0 32 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 32 0 4294967295 DCR DCR DMA control register 0x48 0x20 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB Low Capture/Compare 2 value 0 16 OR1 OR1 TIM2 option register 0x50 0x20 read-write 0x00000000 ITR1_RMP Internal trigger 1 remap 0 1 TI4_RMP Input Capture 4 remap 2 2 ETR1_RMP External trigger remap 1 1 OR2 OR2 TIM3 option register 2 0x60 0x20 read-write 0x00000000 ETRSEL ETR source selection 14 3 SEC_TIM2 0x50000000 TIM3 General-purpose-timers TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 global interrupt 46 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Counter value 0 16 0 65535 UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR Auto-reload value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 DCR DCR DMA control register 0x48 0x20 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB Low Capture/Compare 2 value 0 16 OR1 OR1 TIM2 option register 0x50 0x20 read-write 0x00000000 ITR1_RMP Internal trigger 1 remap 0 1 OR2 OR2 TIM3 option register 2 0x60 0x20 read-write 0x00000000 ETRSEL ETR source selection 14 3 SEC_TIM3 0x50000400 TIM4 General-purpose-timers TIM 0x40000800 TIM4 TIM4 global interrupt 47 SEC_TIM4 0x50000800 TIM5 0x40000C00 TIM5 TIM5 global interrupt 48 SEC_TIM5 0x50000C00 TIM6 General-purpose-timers TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 global interrupt 49 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UIFREMA UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS Master mode selection 4 3 MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT CNT 0 16 0 65535 UIFCPY UIFCPY or Res 31 1 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR ARR_bit0 0 16 0 65535 SEC_TIM6 0x50001000 TIM7 General-purpose-timers TIM 0x40001400 TIM7 TIM7 global interrupt 50 SEC_TIM7 0x50001400 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers TIM15 TIM15 global interrupt 69 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 2 0x2 1-2 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 MMS Master mode selection 4 2 TI1S TI1 selection 7 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 2 0x1 1-2 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 8 0 255 2 0xC 2,1 CCR%s CCR%s capture/compare register PSC 0x28 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 0 255 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 DCR DCR DMA control register 0x48 0x20 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 SMCR SMCR TIM15 slave mode control register 0x8 0x20 read-write 0x00000000 SMS Slave mode selection 0 3 TS Trigger selection 4 3 MSM Master/slave mode 7 1 SMS_3 Slave mode selection - bit 3 16 1 OR1 OR1 TIM15 option register 1 0x50 0x20 read-write 0x00000000 ENCODER_MODE Encoder mode 1 2 TI1_RMP Input capture 1 remap 0 1 OR2 OR2 TIM15 option register 2 0x60 0x20 read-write 0x00000000 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKDF1BK0E BRK dfsdm1_break[0] enable 8 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 SEC_TIM15 0x50014000 TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global interrupt 70 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 COMDE COM DMA request enable 13 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 1 0x0 1-1 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 8 0 255 1 0x4 1-1 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 0 255 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 DCR DCR DMA control register 0x48 0x20 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 OR1 OR1 TIM16 option register 1 0x50 0x20 read-write 0x00000000 TI1_RMP Input capture 1 remap 0 2 OR2 OR2 TIM17 option register 1 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDF1BK1E BRK dfsdm1_break[1] enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarit 11 1 SEC_TIM16 0x50014400 TIM17 General purpose timers TIM 0x40014800 0x0 0x400 registers TIM17 TIM17 global interrupt 71 CR1 CR1 control register 1 0x0 CR2 CR2 control register 2 0x4 DIER DIER DMA/Interrupt enable register 0xC SR SR status register 0x10 EGR EGR event generation register 0x14 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 CCER CCER capture/compare enable register 0x20 CNT CNT counter 0x24 PSC PSC prescaler 0x28 ARR ARR auto-reload register 0x2C RCR RCR repetition counter register 0x30 1 0x4 1-1 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR break and dead-time register 0x44 DCR DCR DMA control register 0x48 DMAR DMAR DMA address for full transfer 0x4C OR1 OR1 TIM16 option register 1 0x50 0x20 read-write 0x00000000 TI1_RMP Input capture 1 remap 0 2 OR2 OR2 TIM17 option register 1 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDF1BK2E BRK dfsdm1_break[2] enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarit 11 1 SEC_TIM17 0x50014800 TIM8 Advanced-timers TIM 0x40013400 0x0 0x400 registers TIM8_BRK TIM8 Break Interrupt 51 TIM8_UP TIM8 Update Interrupt 52 TIM8_TRG_COM TIM8 Trigger and Commutation Interrupt 53 TIM8_CC TIM8 Capture Compare Interrupt 54 CR1 CR1 control register 1 0x0 CR2 CR2 control register 2 0x4 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC SR SR status register 0x10 EGR EGR event generation register 0x14 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C CCER CCER capture/compare enable register 0x20 CNT CNT counter 0x24 PSC PSC prescaler 0x28 ARR ARR auto-reload register 0x2C RCR RCR repetition counter register 0x30 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR break and dead-time register 0x44 DCR DCR DMA control register 0x48 DMAR DMAR DMA address for full transfer 0x4C OR1 OR1 DMA address for full transfer 0x50 0x20 read-write 0x00000000 TI1_RMP Input Capture 1 remap 4 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 CCR5 CCR5 capture/compare register 0x58 CCR6 CCR6 capture/compare register 0x5C OR2 OR2 DMA address for full transfer 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDF1BK2E BRK dfsdm1_break[2] enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 ETRSEL ETR source selection 14 3 OR3 OR3 DMA address for full transfer 0x64 0x20 read-write 0x00000001 BK2INE BRK2 BKIN input enable 0 1 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2DFBK3E BRK2 DFSDM_BREAK0 enable 8 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 SEC_TIM8 0x50013400 TSC Touch sensing controller TSC 0x40024000 0x0 0x400 registers TSC TSC global interrupt 92 CR CR control register 0x0 0x20 read-write 0x00000000 CTPH Charge transfer pulse high 28 4 CTPL Charge transfer pulse low 24 4 SSD Spread spectrum deviation 17 7 SSE Spread spectrum enable 16 1 SSE Disabled Spread spectrum disabled 0 Enabled Spread spectrum enabled 1 SSPSC Spread spectrum prescaler 15 1 PGPSC pulse generator prescaler 12 3 MCV Max count value 5 3 IODEF I/O Default mode 4 1 IODEF PushPull I/Os are forced to output push-pull low 0 Floating I/Os are in input floating 1 SYNCPOL Synchronization pin polarity 3 1 SYNCPOL FallingEdge Falling edge only 0 RisingEdge Rising edge and high level 1 AM Acquisition mode 2 1 AM Normal Normal acquisition mode (acquisition starts as soon as START bit is set) 0 Synchronized Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) 1 START Start a new acquisition 1 1 START NoStarted Acquisition not started 0 Started Start a new acquisition 1 TSCE Touch sensing controller enable 0 1 TSCE Disabled Touch sensing controller disabled 0 Enabled Touch sensing controller enabled 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 MCEIE Max count error interrupt enable 1 1 MCEIE Disabled Max count error interrupt disabled 0 Enabled Max count error interrupt enabled 1 EOAIE End of acquisition interrupt enable 0 1 EOAIE Disabled End of acquisition interrupt disabled 0 Enabled End of acquisition interrupt enabled 1 ICR ICR interrupt clear register 0x8 0x20 read-write 0x00000000 MCEIC Max count error interrupt clear 1 1 EOAIC End of acquisition interrupt clear 0 1 ISR ISR interrupt status register 0xC 0x20 read-write 0x00000000 MCEF Max count error flag 1 1 EOAF End of acquisition flag 0 1 IOHCR IOHCR I/O hysteresis control register 0x10 0x20 read-write 0xFFFFFFFF 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy Schmitt trigger hysteresis disabled 0 Enabled Gx_IOy Schmitt trigger hysteresis enabled 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOASCR IOASCR I/O analog switch control register 0x18 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy analog switch disabled (opened) 0 Enabled Gx_IOy analog switch enabled (closed) 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOSCR IOSCR I/O sampling control register 0x20 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as sampling capacitor 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOCCR IOCCR I/O channel control register 0x28 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as channel 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOGCSR IOGCSR I/O group control status register 0x30 0x20 0x00000000 8 0x1 1-8 G%sS Analog I/O group x status 16 1 read-only G1S Ongoing Acquisition on analog I/O group x is ongoing or not started 0 Complete Acquisition on analog I/O group x is complete 1 8 0x1 1-8 G%sE Analog I/O group x enable 0 1 read-write G1E Disabled Acquisition on analog I/O group x disabled 0 Enabled Acquisition on analog I/O group x enabled 1 8 0x4 1-8 IOG%sCR IOG%sCR I/O group x counter register 0x34 0x20 read-only 0x00000000 CNT Counter value 0 14 SEC_TSC 0x50024000 USB Universal serial bus full-speed device interface USB 0x4000D400 0x0 0x800 registers USB_FS USB FS global interrupt 73 8 0x4 0-7 EP%sR EP%sR endpoint %s register 0x0 0x10 read-write 0x00000000 EA Endpoint address 0 4 0 15 STAT_TX Status bits, for transmission transfers 4 2 read-write oneToToggle STAT_TXR read Disabled all transmission requests addressed to this endpoint are ignored 0 Stall the endpoint is stalled and all transmission requests result in a STALL handshake 1 Nak the endpoint is naked and all transmission requests result in a NAK handshake 2 Valid this endpoint is enabled for transmission 3 DTOG_TX Data Toggle, for transmission transfers 6 1 oneToToggle CTR_TX Correct Transfer for transmission 7 1 zeroToClear EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 EP_TYPE Bulk Bulk endpoint 0 Control Control endpoint 1 Iso Iso endpoint 2 Interrupt Interrupt endpoint 3 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 read-write oneToToggle STAT_RXR read Disabled all reception requests addressed to this endpoint are ignored 0 Stall the endpoint is stalled and all reception requests result in a STALL handshake 1 Nak the endpoint is naked and all reception requests result in a NAK handshake 2 Valid this endpoint is enabled for reception 3 DTOG_RX Data Toggle, for reception transfers 14 1 oneToToggle CTR_RX Correct transfer for reception 15 1 zeroToClear CNTR CNTR control register 0x40 0x10 read-write 0x00000003 FRES Force USB Reset 0 1 FRES NoReset Clear USB reset 0 Reset Force a reset of the USB peripheral, exactly like a RESET signaling on the USB 1 PDWN Power down 1 1 PDWN Disabled No power down 0 Enabled Enter power down mode 1 LPMODE Low-power mode 2 1 LPMODE Disabled No low-power mode 0 Enabled Enter low-power mode 1 FSUSP Force suspend 3 1 FSUSP NoEffect No effect 0 Suspend Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected 1 RESUME Resume request 4 1 RESUME Requested Resume requested 1 L1RESUME LPM L1 Resume request 5 1 L1RESUME Requested LPM L1 request requested 1 L1REQM LPM L1 state request interrupt mask 7 1 L1REQM Disabled L1REQ Interrupt disabled 0 Enabled L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ESOFM Expected start of frame interrupt mask 8 1 ESOFM Disabled ESOF Interrupt disabled 0 Enabled ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 SOFM Start of frame interrupt mask 9 1 SOFM Disabled SOF Interrupt disabled 0 Enabled SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 RESETM USB reset interrupt mask 10 1 RESETM Disabled RESET Interrupt disabled 0 Enabled RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 SUSPM Suspend mode interrupt mask 11 1 SUSPM Disabled Suspend Mode Request SUSP Interrupt disabled 0 Enabled SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 WKUPM Wakeup interrupt mask 12 1 WKUPM Disabled WKUP Interrupt disabled 0 Enabled WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ERRM Error interrupt mask 13 1 ERRM Disabled ERR Interrupt disabled 0 Enabled ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 PMAOVRM Packet memory area over / underrun interrupt mask 14 1 PMAOVRM Disabled PMAOVR Interrupt disabled 0 Enabled PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 CTRM Correct transfer interrupt mask 15 1 CTRM Disabled Correct Transfer (CTR) Interrupt disabled 0 Enabled CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ISTR ISTR interrupt status register 0x44 0x10 0x00000000 EP_ID Endpoint Identifier 0 4 read-only 0 15 DIR Direction of transaction 4 1 read-only DIR To Data transmitted by the USB peripheral to the host PC 0 From Data received by the USB peripheral from the host PC 1 L1REQ LPM L1 state request 7 1 read-write zeroToClear L1REQR read NotReceived LPM command to enter the L1 state is not received 0 Received LPM command to enter the L1 state is successfully received and acknowledged 1 L1REQW write Clear Clear flag 0 ESOF Expected start frame 8 1 read-write zeroToClear ESOFR read NotExpectedStartOfFrame NotExpectedStartOfFrame 0 ExpectedStartOfFrame An SOF packet is expected but not received 1 ESOFW write Clear Clear flag 0 SOF start of frame 9 1 read-write zeroToClear SOFR read NotStartOfFrame NotStartOfFrame 0 StartOfFrame Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus 1 SOFW write Clear Clear flag 0 RESET reset request 10 1 read-write zeroToClear RESETR read NotReset NotReset 0 Reset Peripheral detects an active USB RESET signal at its inputs 1 RESETW write Clear Clear flag 0 SUSP Suspend mode request 11 1 read-write zeroToClear SUSPR read NotSuspend NotSuspend 0 Suspend No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus 1 SUSPW write Clear Clear flag 0 WKUP Wakeup 12 1 read-write zeroToClear WKUPR read NotWakeup NotWakeup 0 Wakeup Activity is detected that wakes up the USB peripheral 1 WKUPW write Clear Clear flag 0 ERR Error 13 1 read-write zeroToClear ERRR read NotOverrun Errors are not occurred 0 Error One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred 1 ERRW write Clear Clear flag 0 PMAOVR Packet memory area over / underrun 14 1 read-write zeroToClear PMAOVRR read NotOverrun Overrun is not occurred 0 Overrun Microcontroller has not been able to respond in time to an USB memory request 1 PMAOVRW write Clear Clear flag 0 CTR Correct transfer 15 1 read-only CTR Completed Endpoint has successfully completed a transaction 1 FNR FNR frame number register 0x48 0x10 read-only 0x00000000 FN Frame number 0 11 0 2047 LSOF Lost SOF 11 2 0 3 LCK Locked 13 1 LCK Locked the frame timer remains in this state until an USB reset or USB suspend event occurs 1 RXDM Receive data - line status 14 1 RXDM Received received data minus upstream port data line 1 RXDP Receive data + line status 15 1 RXDP Received received data plus upstream port data line 1 DADDR DADDR device address 0x4C 0x10 read-write 0x00000000 ADD Device address 0 7 0 127 EF Enable function 7 1 EF Disabled USB device disabled 0 Enabled USB device enabled 1 BTABLE BTABLE Buffer table address 0x50 0x10 read-write 0x00000000 BTABLE Buffer table 3 13 0 8191 LPMCSR LPMCSR LPM control and status register 0x54 0x10 read-write 0x00000000 LPMEN LPM support enable 0 1 LPMEN Disabled No LPM transactions are handled 0 Enabled Enable the LPM support within the USB device 1 LPMACK LPM Token acknowledge enable 1 1 LPMACK Nyet The valid LPM Token will be NYET 0 Ack The valid LPM Token will be ACK 1 REMWAKE RemoteWake value 3 1 BESL BESL value 4 4 0 15 BCDR BCDR Battery charging detector 0x58 0x10 read-write 0x00000000 BCDEN Battery charging detector (BCD) enable 0 1 BCDEN Disabled disable the BCD support 0 Enabled enable the BCD support within the USB device 1 DCDEN Data contact detection (DCD) mode enable 1 1 DCDEN Disabled Data contact detection (DCD) mode disabled 0 Enabled Data contact detection (DCD) mode enabled 1 PDEN Primary detection (PD) mode enable 2 1 PDEN Disabled Primary detection (PD) mode disabled 0 Enabled Primary detection (PD) mode enabled 1 SDEN Secondary detection (SD) mode enable 3 1 SDEN Disabled Secondary detection (SD) mode disabled 0 Enabled Secondary detection (SD) mode enabled 1 DCDET Data contact detection (DCD) status 4 1 DCDET NotDetected data lines contact not detected 0 Detected data lines contact detected 1 PDET Primary detection (PD) status 5 1 PDET NoBCD no BCD support detected 0 BCD BCD support detected 1 SDET Secondary detection (SD) status 6 1 SDET CDP CDP detected 0 DCP DCP detected 1 PS2DET DM pull-up detection status 7 1 PS2DET Normal Normal port detected 0 PS2 PS2 port or proprietary charger detected 1 DPPU DP pull-up control 15 1 DPPU Disabled signalize disconnect to the host when needed by the user software 0 Enabled enable the embedded pull-up on the DP line 1 SEC_USB 0x5000D400 UCPD1 USB Power Delivery interface UCPD 0x4000DC00 0x0 0x400 registers UCPD1 UCPD global interrupt 106 CFGR1 CFG1 UCPD configuration register 0x0 0x20 read-write 0x00000000 HBITCLKDIV HBITCLKDIV 0 6 0 63 IFRGAP IFRGAP 6 5 1 31 TRANSWIN TRANSWIN 11 5 1 31 PSC_USBPDCLK PSC_USBPDCLK 17 3 PSC_USBPDCLK Div1 Divide by 1 0 Div2 Divide by 2 1 Div4 Divide by 4 2 Div8 Divide by 8 3 Div16 Divide by 16 4 TXDMAEN TXDMAEN 29 1 TXDMAEN Disabled DMA mode for transmission disabled 0 Enabled DMA mode for transmission enabled 1 RXDMAEN RXDMAEN: 30 1 RXDMAEN Disabled DMA mode for reception disabled 0 Enabled DMA mode for reception enabled 1 UCPDEN UCPDEN 31 1 UCPDEN Disabled UCPD peripheral disabled 0 Enabled UCPD peripheral enabled 1 RXORDSETEN0 SOP detection 20 1 RXORDSETEN0 Disabled Flag disabled 0 Enabled Flag enabled 1 RXORDSETEN1 SOP' detection 21 1 RXORDSETEN2 SOP'' detection 22 1 RXORDSETEN3 Hard Reset detection 23 1 RXORDSETEN4 Cable Detect reset 24 1 RXORDSETEN5 SOP'_Debug 25 1 RXORDSETEN6 SOP'' Debug 26 1 RXORDSETEN7 SOP extension #1 27 1 RXORDSETEN8 SOP extension #2 28 1 CFGR2 CFG2 UCPD configuration register 2 0x4 0x20 read-write 0x00000000 RXFILTDIS RXFILTDIS 0 1 RXFILTDIS Enabled Rx pre-filter enabled 0 Disabled Rx pre-filter disabled 1 RXFILT2N3 RXFILT2N3 1 1 RXFILT2N3 Samp3 3 samples 0 Samp2 2 samples 1 FORCECLK FORCECLK 2 1 FORCECLK NoForce Do not force clock request 0 Force Force clock request 1 WUPEN WUPEN 3 1 WUPEN Disabled Disabled 0 Enabled Enabled 1 CFGR3 CFG3 UCPD configuration register 3 0x8 0x20 read-write 0x00000000 TRIM1_NG_CCRPD TRIM1_NG_CCRPD 0 4 0 15 TRIM1_NG_CC1A5 TRIM1_NG_CC1A5 4 5 0 15 TRIM1_NG_CC3A0 TRIM1_NG_CC3A0 9 4 0 15 TRIM2_NG_CCRPD TRIM2_NG_CCRPD 16 4 0 15 TRIM2_NG_CC1A5 TRIM2_NG_CC1A5 20 5 0 15 TRIM2_NG_CC3A0 TRIM2_NG_CC3A0 25 4 0 15 CR CR UCPD control register 0xC 0x20 read-write 0x00000000 TXMODE TXMODE 0 2 TXMODE RegisterSet Transmission of Tx packet previously defined in other registers 0 CableReset Cable Reset sequence 1 BISTTest BIST test sequence (BIST Carrier Mode 2) 2 TXSEND TXSEND 2 1 TXSEND NoEffect No effect 0 Start Start Tx packet transmission 1 TXHRST TXHRST 3 1 TXHRST NoEffect No effect 0 Start Start Tx Hard Reset message 1 RXMODE RXMODE 4 1 RXMODE Normal Normal receive mode 0 BIST BIST receive mode (BIST test data mode) 1 PHYRXEN PHYRXEN 5 1 PHYRXEN Disabled USB Power Delivery receiver disabled 0 Enabled USB Power Delivery receiver enabled 1 PHYCCSEL PHYCCSEL 6 1 PHYCCSEL CC1 Use CC1 IO for Power Delivery communication 0 CC2 Use CC2 IO for Power Delivery communication 1 ANASUBMODE ANASUBMODE 7 2 ANASUBMODE Disabled Disabled 0 Rp_DefaultUSB Default USB Rp 1 Rp_1_5A 1.5A Rp 2 Rp_3A 3A Rp 3 ANAMODE ANAMODE 9 1 ANAMODE Source Source 0 Sink Sink 1 CCENABLE CCENABLE 10 2 CCENABLE Disabled Both PHYs disabled 0 CC1Enabled CC1 PHY enabled 1 CC2Enabled CC2 PHY enabled 2 BothEnabled CC1 and CC2 PHYs enabled 3 FRSRXEN FRSRXEN 16 1 FRSRXEN Disabled FRS Rx event detection disabled 0 Enabled FRS Rx event detection enabled 1 FRSTX FRSTX 17 1 FRSTX NoEffect No effect 0 Enabled FRS Tx signaling enabled 1 RDCH RDCH 18 1 RDCH NoEffect No effect 0 ConditionDrive Rdch condition drive 1 CC1TCDIS CC1TCDIS 20 1 CC1TCDIS Enabled Type-C detector on the CCx line enabled 0 Disabled Type-C detector on the CCx line disabled 1 CC2TCDIS CC2TCDIS 21 1 IMR IMR UCPD Interrupt Mask Register 0x10 0x20 read-write 0x00000000 TXISIE TXISIE 0 1 TXISIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TXMSGDISCIE TXMSGDISCIE 1 1 TXMSGSENTIE TXMSGSENTIE 2 1 TXMSGABTIE TXMSGABTIE 3 1 HRSTDISCIE HRSTDISCIE 4 1 HRSTSENTIE HRSTSENTIE 5 1 TXUNDIE TXUNDIE 6 1 RXNEIE RXNEIE 8 1 RXORDDETIE RXORDDETIE 9 1 RXHRSTDETIE RXHRSTDETIE 10 1 RXOVRIE RXOVRIE 11 1 RXMSGENDIE RXMSGENDIE 12 1 TYPECEVT1IE TYPECEVT1IE 14 1 TYPECEVT2IE TYPECEVT2IE 15 1 FRSEVTIE FRSEVTIE 20 1 SR SR UCPD Status Register 0x14 0x20 read-only 0x00000000 TXIS TXIS 0 1 TXIS NotRequired New Tx data write not required 0 Required New Tx data write required 1 TXMSGDISC TXMSGDISC 1 1 TXMSGDISC NotDiscarded No Tx message discarded 0 Discarded Tx message discarded 1 TXMSGSENT TXMSGSENT 2 1 TXMSGSENT NotCompleted No Tx message completed 0 Completed Tx message completed 1 TXMSGABT TXMSGABT 3 1 TXMSGABT NoAbort No transmit message abort 0 Abort Transmit message abort 1 HRSTDISC HRSTDISC 4 1 HRSTDISC NotDiscarded No Hard Reset discarded 0 Discarded Hard Reset discarded 1 HRSTSENT HRSTSENT 5 1 HRSTSENT NotSent No Hard Reset message sent 0 Sent Hard Reset message sent 1 TXUND TXUND 6 1 TXUND NoUnderrun No Tx data underrun detected 0 Underrun Tx data underrun detected 1 RXNE RXNE 8 1 RXNE Empty Rx data register empty 0 NotEmpty Rx data register not empty 1 RXORDDET RXORDDET 9 1 RXORDDET NoOrderedSet No ordered set detected 0 OrderedSet Ordered set detected 1 RXHRSTDET RXHRSTDET 10 1 RXHRSTDET NoHardReset Hard Reset not received 0 HardReset Hard Reset received 1 RXOVR RXOVR 11 1 RXOVR NoOverflow No overflow 0 Overflow Overflow 1 RXMSGEND RXMSGEND 12 1 RXMSGEND NoNewMessage No new Rx message received 0 NewMessage A new Rx message received 1 RXERR RXERR 13 1 RXERR NoError No error detected 0 Error Error(s) detected 1 TYPECEVT1 TYPECEVT1 14 1 TYPECEVT1 NoNewEvent No new event 0 NewEvent A new Type-C event occurred 1 TYPECEVT2 TYPECEVT2 15 1 TYPEC_VSTATE_CC1 TYPEC_VSTATE_CC1 16 2 TYPEC_VSTATE_CC1 Lowest Lowest 0 Low Low 1 High High 2 Highest Highest 3 TYPEC_VSTATE_CC2 TYPEC_VSTATE_CC2 18 2 FRSEVT FRSEVT 20 1 FRSEVT NoNewEvent No new event 0 NewEvent New FRS receive event occurred 1 ICR ICR UCPD Interrupt Clear Register 0x18 0x20 read-write 0x00000000 TXMSGDISCCF TXMSGDISCCF 1 1 TXMSGDISCCFW write Clear Clear flag in UCPD_SR 1 TXMSGSENTCF TXMSGSENTCF 2 1 TXMSGABTCF TXMSGABTCF 3 1 HRSTDISCCF HRSTDISCCF 4 1 HRSTSENTCF HRSTSENTCF 5 1 TXUNDCF TXUNDCF 6 1 RXORDDETCF RXORDDETCF 9 1 RXHRSTDETCF RXHRSTDETCF 10 1 RXOVRCF RXOVRCF 11 1 RXMSGENDCF RXMSGENDCF 12 1 TYPECEVT1CF TYPECEVT1CF 14 1 TYPECEVT2CF TYPECEVT2CF 15 1 FRSEVTCF FRSEVTCF 20 1 TX_ORDSETR TX_ORDSET UCPD Tx Ordered Set Type Register 0x1C 0x20 read-write 0x00000000 TXORDSET TXORDSET 0 20 0 1048575 TX_PAYSZR TX_PAYSZ UCPD Tx Paysize Register 0x20 0x20 read-write 0x00000000 TXPAYSZ TXPAYSZ 0 10 0 1023 TXDR TXDR UCPD Tx Data Register 0x24 0x20 read-write 0x00000000 TXDATA TXDATA 0 8 0 255 RX_ORDSETR RX_ORDSET UCPD Rx Ordered Set Register 0x28 0x20 read-only 0x00000000 RXORDSET RXORDSET 0 3 RXORDSET SOP SOP code detected in receiver 0 SOPPrime SOP' code detected in receiver 1 SOPDoublePrime SOP'' code detected in receiver 2 SOPPrimeDebug SOP'_Debug detected in receiver 3 SOPDoublePrimeDebug SOP''_Debug detected in receiver 4 CableReset Cable Reset detected in receiver 5 SOPExtension1 SOP extension #1 detected in receiver 6 SOPExtension2 SOP extension #2 detected in receiver 7 RXSOP3OF4 RXSOP3OF4 3 1 RXSOP3OF4 AllCorrect 4 correct K-codes out of 4 0 OneIncorrect 3 correct K-codes out of 4 1 RXSOPKINVALID RXSOPKINVALID 4 3 RXSOPKINVALID Valid No K-code corrupted 0 FirstCorrupted First K-code corrupted 1 SecondCorrupted Second K-code corrupted 2 ThirdCorrupted Third K-code corrupted 3 FourthCorrupted Fourth K-code corrupted 4 RX_PAYSZR RX_PAYSZ UCPD Rx Paysize Register 0x2C 0x20 read-only 0x00000000 RXPAYSZ RXPAYSZ 0 10 0 1023 RXDR RXDR UCPD Receive Data Register 0x30 0x20 read-only 0x00000000 RXDATA RXDATA 0 8 0 255 RX_ORDEXTR1 RX_ORDEXT1 UCPD Rx Ordered Set Extension Register 0x34 0x20 read-write 0x00000000 RXSOPX1 RXSOPX1 0 20 0 1048575 RX_ORDEXTR2 RX_ORDEXT2 UCPD Rx Ordered Set Extension Register 0x38 0x20 read-write 0x00000000 RXSOPX2 RXSOPX2 0 20 0 1048575 SEC_UCPD1 0x5000DC00 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 61 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 M1 Word length 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 EOBIE End of Block interrupt enable 27 1 EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 RTOIE Receiver timeout interrupt enable 26 1 RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 DEAT Driver Enable assertion time 21 5 0 31 DEDT Driver Enable de-assertion time 16 5 0 31 OVER8 Oversampling mode 15 1 OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 FIFOEN FIFOEN 29 1 FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFEIE 30 1 TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFFIE 31 1 RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 RTOEN Receiver timeout enable 23 1 RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ABRMOD Auto baud rate mode 21 2 ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 ABREN Auto baud rate enable 20 1 ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 LINEN LIN mode enable 14 1 LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 CPOL Clock polarity 10 1 CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CPHA Clock phase 9 1 CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 LBCL Last bit clock pulse 8 1 LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 LBDIE LIN break detection interrupt enable 6 1 LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBDL LIN break detection length 5 1 LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 SLVEN SLVEN 0 1 SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 DIS_NSS DIS_NSS 3 1 DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 SCARCNT Smartcard auto-retry count 17 3 0 7 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 ONEBIT One sample bit method enable 11 1 ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 SCEN Smartcard mode enable 5 1 SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 NACK Smartcard NACK enable 4 1 NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 IRLP Ir low-power 2 1 IRLP Normal Normal mode 0 LowPower Low-power mode 1 IREN Ir mode enable 1 1 IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 TXFTIE TXFTIE 23 1 TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 TCBGTIE TCBGTIE 24 1 TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 RXFTCFG RXFTCFG 25 3 RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFTIE 28 1 RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFTCFG 29 3 TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR BRR 0 16 0 65535 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 0 255 PSC Prescaler value 0 8 0 255 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 0 255 RTO Receiver timeout value 0 24 0 16777215 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ABRRQ Auto baud rate request 0 1 ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 ABRF ABRF 15 1 ABRE ABRE 14 1 EOBF EOBF 12 1 EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 RTOF RTOF 11 1 RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 LBDF LBDF 8 1 LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 TXE TXE 7 1 TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXNE RXNE 5 1 RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NF NF 2 1 NF NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 TXFE TXFE 23 1 TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFF 24 1 RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TCBGT TCBGT 25 1 TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFT RXFT 26 1 RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFT 27 1 TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 UDR SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to . 13 1 read-only UDR NoUnderrun No underrun error 0 Underrun underrun error 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 EOBCF End of block clear flag 12 1 oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 RTOCF Receiver timeout clear flag 11 1 oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 LBDCF LIN break detection clear flag 8 1 oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 TXFECF TXFECF 5 1 oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 TCBGTCF TCBGTCF 7 1 oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 UDRCF UDRCF 13 1 oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 PRESC PRESC PRESC 0x2C 0x20 read-write 0x00000000 PRESCALER PRESCALER 0 4 PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 SEC_USART1 0x50013800 USART2 0x40004400 USART2 USART2 global interrupt 62 SEC_USART2 0x50004400 USART3 0x40004800 USART3 USART3 global interrupt 63 SEC_USART3 0x50004800 UART4 0x40004C00 UART4 UART4 global interrupt 64 UART5 0x40005000 UART5 UART5 global interrupt 65 SEC_UART4 0x50004C00 SEC_UART5 0x50005000 VREFBUF Voltage reference buffer VREF 0x40010030 0x0 0x1D0 registers CSR CSR VREF control and status register 0x0 0x20 0x00000002 ENVR Voltage reference buffer enable 0 1 read-write HIZ High impedance mode 1 1 read-write VRS Voltage reference scale 2 1 read-write VRR Voltage reference buffer ready 3 1 read-only CCR CCR calibration control register 0x4 0x20 read-write 0x00000000 TRIM Trimming code 0 6 SEC_VREFBUF 0x50010030 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR Control register 0x0 0x10 read-write 0x0000007F WDGA Activation bit 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 T 7-bit counter (MSB to LSB) 0 7 0 127 CFR CFR Configuration register 0x4 0x10 read-write 0x0000007F EWI Early wakeup interrupt 9 1 EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base 7 2 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 W 7-bit window value 0 7 0 127 SR SR Status register 0x8 0x10 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 SEC_WWDG 0x50002C00

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