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Showing content from https://stm32-rs.github.io/stm32-rs/stm32l4p5.svd.patched below:

STM32L4P5 1.6 STM32L4P5 CM4 r0p1 little true true 4 false 8 32 0x20 0x00000000 0xFFFFFFFF DAC Digital-to-analog converter DAC 0x40007400 0x0 0x400 registers CR CR DAC control register 0x0 0x20 read-write 0x00000000 2 0x10 1-2 EN%s DAC channel%s enable 0 1 EN1 Disabled DAC Channel X disabled 0 Enabled DAC Channel X enabled 1 2 0x10 1-2 TEN%s DAC channel%s trigger enable 1 1 TEN1 Disabled DAC Channel X trigger disabled 0 Enabled DAC Channel X trigger enabled 1 TSEL1 DAC channel1 trigger selection 2 4 TSEL1 Swtrig Software trigger 0 Tim1Trgo Timer 1 TRGO event 1 Tim2Trgo Timer 2 TRGO event 2 Tim4Trgo Timer 4 TRGO event 3 Tim5Trgo Timer 5 TRGO event 4 Tim6Trgo Timer 6 TRGO event 5 Tim7Trgo Timer 7 TRGO event 6 Tim8Trgo Timer 8 TRGO event 7 Tim15Trgo Timer 15 TRGO event 8 Lptim1Out LPTIM1 OUT event 11 Lptim2Out LPTIM2 OUT event 12 Exti9 External pin 13 2 0x10 1-2 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true 2 0x10 1-2 MAMP%s DAC channel%s mask/amplitude selector 8 4 MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 2 0x10 1-2 DMAEN%s DAC channel%s DMA enable 12 1 DMAEN1 Disabled DAC Channel X DMA mode disabled 0 Enabled DAC Channel X DMA mode enabled 1 2 0x10 1-2 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 2 0x10 1-2 CEN%s DAC channel%s calibration enable 14 1 CEN1 Normal DAC Channel X Normal operating mode 0 Calibration DAC Channel X calibration mode 1 TSEL2 DAC channel2 trigger selection 18 4 HFSEL High frequency interface mode enable 15 1 HFSEL Disabled High frequency interface mode disabled 0 Enabled High frequency interface mode enabled 1 SWTRIGR SWTRIGR software trigger register 0x4 0x20 write-only 0x00000000 2 0x1 1-2 SWTRIG%s DAC channel%s software trigger 0 1 SWTRIG1 NoTrigger No trigger 0 Trigger Trigger 1 2 0xC 1-2 DHR12R%s DHR12R%s channel%s 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit right-aligned data 0 12 0 4095 2 0xC 1-2 DHR12L%s DHR12L%s channel%s 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit left-aligned data 4 12 0 4095 2 0xC 1-2 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACCDHR DAC channel1 8-bit right-aligned data 0 8 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 0 4095 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 0 4095 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 2 0x8 1-2 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 0 255 2 0x4 1-2 DOR%s DOR%s channel%s data output register 0x2C 0x20 read-only 0x00000000 DACCDOR DAC channel1 data output 0 12 0 4095 SR SR status register 0x34 0x20 0x00000000 2 0x10 1-2 DMAUDR%s DAC channel%s DMA underrun flag 13 1 read-write DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 2 0x10 1-2 CAL_FLAG%s DAC channel%s calibration offset status 14 1 read-only CAL_FLAG1 Lower Calibration trimming value is lower than the offset correction value 0 Equal_Higher Calibration trimming value is equal or greater than the offset correction value 1 2 0x10 1-2 BWST%s DAC channel%s busy writing sample time flag 15 1 read-only BWST1 Idle There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written 0 Busy There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written 1 CCR CCR calibration control register 0x38 0x20 read-write 0x00000000 2 0x10 1-2 OTRIM%s DAC channel%s offset trimming value 0 5 0 31 MCR MCR mode control register 0x3C 0x20 read-write 0x00000000 2 0x10 1-2 MODE%s DAC channel%s mode 0 3 MODE1 NormalPinBuffer Normal mode - DAC channelx is connected to external pin with Buffer enabled 0 NormalPinChipBuffer Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 1 NormalPinNoBuffer Normal mode - DAC channelx is connected to external pin with Buffer disabled 2 NormalChipNoBuffer Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled 3 SHPinBuffer S&H mode - DAC channelx is connected to external pin with Buffer enabled 4 SHPinChipBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 5 SHPinNoBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled 6 SHChipNoBuffer S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled 7 2 0x4 1-2 SHSR%s SHSR%s DAC channel%s sample and hold sample time register 0x40 0x20 read-write 0x00000000 TSAMPLE DAC Channel 1 sample Time 0 10 0 1023 SHHR SHHR Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 2 0x10 1-2 THOLD%s DAC channel%s hold time (only valid in Sample and hold mode) 0 10 0 1023 SHRR SHRR Sample and Hold refresh time register 0x4C 0x20 read-write 0x00000001 2 0x10 1-2 TREFRESH%s DAC channel%s refresh time (only valid in Sample and hold mode) 0 8 0 255 DMA1 Direct memory access controller DMA 0x40020000 0x0 0x400 registers DMA1_CH1 DMA1 Channel1 global interrupt 11 DMA1_CH2 DMA1 Channel2 global interrupt 12 DMA1_CH3 DMA1 Channel3 interrupt 13 DMA1_CH4 DMA1 Channel4 interrupt 14 DMA1_CH5 DMA1 Channel5 interrupt 15 DMA1_CH6 DMA1 Channel6 interrupt 16 DMA1_CH7 DMA1 Channel 7 interrupt 17 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 7 0x4 1-7 TEIF%s Channel %s Transfer Error flag 3 1 TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 7 0x4 1-7 HTIF%s Channel %s Half Transfer Complete flag 2 1 HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 7 0x4 1-7 TCIF%s Channel %s Transfer Complete flag 1 1 TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 7 0x4 1-7 GIF%s Channel %s Global interrupt flag 0 1 GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 IFCR IFCR interrupt flag clear register 0x4 0x20 write-only 0x00000000 7 0x4 1-7 CTEIF%s Channel %s Transfer Error clear 3 1 CTEIF1 Clear Clears the TEIF flag in the ISR register 1 7 0x4 1-7 CHTIF%s Channel %s Half Transfer clear 2 1 CHTIF1 Clear Clears the HTIF flag in the ISR register 1 7 0x4 1-7 CTCIF%s Channel %s Transfer Complete clear 1 1 CTCIF1 Clear Clears the TCIF flag in the ISR register 1 7 0x4 1-7 CGIF%s Channel %s Global interrupt clear 0 1 CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 7 0x14 1-7 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8 CR CCR1 channel x configuration register 0x0 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 PL Channel priority level 12 2 PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 PSIZE Peripheral size 8 2 PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC Memory increment mode 7 1 CIRC Circular mode 5 1 CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 DIR Data transfer direction 4 1 DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 TEIE Transfer error interrupt enable 3 1 TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 HTIE Half transfer interrupt enable 2 1 HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TCIE Transfer complete interrupt enable 1 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 EN Channel enable 0 1 EN Disabled Channel disabled 0 Enabled Channel enabled 1 NDTR CNDTR1 channel x number of data register 0x4 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 0 65535 PAR CPAR1 channel x peripheral address register 0x8 0x20 read-write 0x00000000 PA Peripheral address 0 32 MAR CMAR1 channel x memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 DMAMUX DMA request multiplexer DMAMUX 0x40020800 0x0 0x400 registers DMAMUX1_OVR DMAMUX Overrun interrupt 94 14 0x4 0-13 CCR%s C%sCR DMA Multiplexer Channel %s Control register 0x0 0x20 read-write 0x00000000 SYNC_ID Synchronization identification 24 5 NBREQ Number of DMA requests minus 1 to forward 19 5 0 31 SPOL Synchronization polarity 17 2 SPOL NoEdge No event, i.e. no synchronization nor detection 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 SE Synchronization enable 16 1 SE Disabled Synchronization disabled 0 Enabled Synchronization enabled 1 EGE Event generation enable 9 1 EGE Disabled Event generation disabled 0 Enabled Event generation enabled 1 SOIE Synchronization overrun interrupt enable 8 1 SOIE Disabled Synchronization overrun interrupt disabled 0 Enabled Synchronization overrun interrupt enabled 1 DMAREQ_ID DMA request identification 0 7 CSR CSR channel status register 0x80 0x20 read-only 0x00000000 14 0x1 0-13 SOF%s Synchronization Overrun Flag %s 0 1 SOF0 NoSyncEvent No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 0 SyncEvent Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 1 CFR CFR clear flag register 0x84 0x20 write-only 0x00000000 14 0x1 0-13 CSOF%s Synchronization Clear Overrun Flag %s 0 1 oneToClear CSOF0W Clear Clear synchronization flag 1 4 0x4 0-3 RGCR%s RG%sCR request generator channel %s configuration register 0x100 0x20 read-write 0x00000000 GNBREQ Number of DMA requests to be generated minus 1 19 5 0 31 GPOL DMA request generator trigger polarity 17 2 GPOL NoEdge No event, i.e. no detection nor generation 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 GE DMA request generator channel 0 enable 16 1 GE Disabled DMA request generation disabled 0 Enabled DMA request enabled 1 OIE Trigger overrun interrupt enable 8 1 OIE Disabled Trigger overrun interrupt disabled 0 Enabled Trigger overrun interrupt enabled 1 SIG_ID Signal identification 0 5 RGSR RGSR request generator interrupt status register 0x140 0x20 read-only 0x00000000 4 0x1 0-3 OF%s Generator Overrun Flag %s 0 1 OF0 NoTrigger No new trigger event occured on DMA request generator channel x, before the request counter underrun 0 Trigger New trigger event occured on DMA request generator channel x, before the request counter underrun 1 RGCFR RGCFR request generator interrupt clear flag register 0x144 0x20 write-only 0x00000000 4 0x1 0-3 COF%s Generator Clear Overrun Flag %s 0 1 oneToClear COF0W Clear Clear overrun flag 1 DMA2 0x40020400 DMA2_CH1 DMA2 Channel 1 global Interrupt 56 DMA2_CH2 DMA2 Channel 2 global Interrupt 57 DMA2_CH3 DMA2 Channel 3 global Interrupt 58 DMA2_CH4 DMA2 Channel 4 global Interrupt 59 DMA2_CH5 DMA2 Channel 5 global Interrupt 60 DMA2_CH6 DMA2 Channel 6 global Interrupt 68 DMA2_CH7 DMA2 Channel 7 global Interrupt 69 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 8 0 255 CR CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 REV_IN Reverse input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 POLYSIZE Polynomial size 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 RESET RESET bit 0 1 write-only RESETW Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF INIT Programmable initial CRC value 0 32 0 4294967295 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 0 4294967295 LTDC LCD-TFT display controller LTDC 0x40016800 0x0 0x400 registers LCD_TFT LTDC global interrupt 91 LCD_TFT_ER LTDC global error interrupt 92 SSCR SSCR LTDC Synchronization Size Configuration Register 0x8 0x20 read-write 0x00000000 VSH Vertical Synchronization Height (in units of horizontal scan line) 0 11 0 2047 HSW Horizontal Synchronization Width (in units of pixel clock period) 16 12 0 4095 BPCR BPCR LTDC Back Porch Configuration Register 0xC 0x20 read-write 0x00000000 AVBP Accumulated Vertical back porch (in units of horizontal scan line) 0 11 0 2047 AHBP Accumulated Horizontal back porch (in units of pixel clock period) 16 12 0 4095 AWCR AWCR LTDC Active Width Configuration Register 0x10 0x20 read-write 0x00000000 AAH Accumulated Active Height (in units of horizontal scan line) 0 11 0 2047 AAW Accumulated Active Width (in units of pixel clock period) 16 12 0 4095 TWCR TWCR LTDC Total Width Configuration Register 0x14 0x20 read-write 0x00000000 TOTALH Total Height (in units of horizontal scan line) 0 11 0 2047 TOTALW Total Width (in units of pixel clock period) 16 12 0 4095 GCR GCR LTDC Global Control Register 0x18 0x20 0x00002220 LTDCEN LCD-TFT controller enable bit 0 1 read-write LTDCEN Disabled LCD-TFT controller disabled 0 Enabled LCD-TFT controller enabled 1 DBW Dither Blue Width 4 3 read-only DGW Dither Green Width 8 3 read-only DRW Dither Red Width 12 3 read-only DEN Dither Enable 16 1 read-write DEN Disabled Dither disabled 0 Enabled Dither enabled 1 PCPOL Pixel Clock Polarity 28 1 read-write PCPOL RisingEdge Pixel clock on rising edge 0 FallingEdge Pixel clock on falling edge 1 DEPOL Not Data Enable Polarity 29 1 read-write DEPOL ActiveLow Data enable polarity is active low 0 ActiveHigh Data enable polarity is active high 1 VSPOL Vertical Synchronization Polarity 30 1 read-write VSPOL ActiveLow Vertical synchronization polarity is active low 0 ActiveHigh Vertical synchronization polarity is active high 1 HSPOL Horizontal Synchronization Polarity 31 1 read-write HSPOL ActiveLow Horizontal synchronization polarity is active low 0 ActiveHigh Horizontal synchronization polarity is active high 1 SRCR SRCR LTDC Shadow Reload Configuration Register 0x24 0x20 read-write 0x00000000 IMR Immediate Reload 0 1 IMR NoEffect This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) 0 Reload The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload 1 VBR Vertical Blanking Reload 1 1 VBR NoEffect This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) 0 Reload The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). 1 BCCR BCCR LTDC Background Color Configuration Register 0x2C 0x20 read-write 0x00000000 BCBLUE Background Color Blue value 0 8 0 255 BCGREEN Background Color Green value 8 8 0 255 BCRED Background Color Red value 16 8 0 255 IER IER LTDC Interrupt Enable Register 0x34 0x20 read-write 0x00000000 LIE Line Interrupt Enable 0 1 LIE Disabled Line interrupt disabled 0 Enabled Line interrupt enabled 1 FUIE FIFO Underrun Interrupt Enable 1 1 FUIE Disabled FIFO underrun interrupt disabled 0 Enabled FIFO underrun interrupt enabled 1 TERRIE Transfer Error Interrupt Enable 2 1 TERRIE Disabled Transfer error interrupt disabled 0 Enabled Transfer error interrupt enabled 1 RRIE Register Reload interrupt enable 3 1 RRIE Disabled Register reload interrupt disabled 0 Enabled Register reload interrupt enabled 1 ISR ISR LTDC Interrupt Status Register 0x38 0x20 read-only 0x00000000 LIF Line Interrupt flag 0 1 LIF NotReached Programmed line not reached 0 Reached Line interrupt generated when a programmed line is reached 1 FUIF FIFO Underrun Interrupt flag 1 1 FUIF NoUnderrun No FIFO underrun 0 Underrun FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO 1 TERRIF Transfer Error interrupt flag 2 1 TERRIF NoError No transfer error 0 Error Transfer error interrupt generated when a bus error occurs 1 RRIF Register Reload Interrupt Flag 3 1 RRIF NoReload No register reload 0 Reload Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) 1 ICR ICR LTDC Interrupt Clear Register 0x3C 0x20 write-only 0x00000000 CLIF Clears the Line Interrupt Flag 0 1 oneToClear CLIFW Clear Clears the LIF flag in the ISR register 1 CFUIF Clears the FIFO Underrun Interrupt flag 1 1 oneToClear CFUIFW Clear Clears the FUIF flag in the ISR register 1 CTERRIF Clears the Transfer Error Interrupt Flag 2 1 oneToClear CTERRIFW Clear Clears the TERRIF flag in the ISR register 1 CRRIF Clears Register Reload Interrupt Flag 3 1 oneToClear CRRIFW Clear Clears the RRIF flag in the ISR register 1 LIPCR LIPCR LTDC Line Interrupt Position Configuration Register 0x40 0x20 read-write 0x00000000 LIPOS Line Interrupt Position 0 11 0 2047 CPSR CPSR LTDC Current Position Status Register 0x44 0x20 read-only 0x00000000 CYPOS Current Y Position 0 16 CXPOS Current X Position 16 16 CDSR CDSR LTDC Current Display Status Register 0x48 0x20 read-only 0x0000000F VDES Vertical Data Enable display Status 0 1 VDES NotActive Currently not in vertical Data Enable phase 0 Active Currently in vertical Data Enable phase 1 HDES Horizontal Data Enable display Status 1 1 HDES NotActive Currently not in horizontal Data Enable phase 0 Active Currently in horizontal Data Enable phase 1 VSYNCS Vertical Synchronization display Status 2 1 VSYNCS NotActive Currently not in VSYNC phase 0 Active Currently in VSYNC phase 1 HSYNCS Horizontal Synchronization display Status 3 1 HSYNCS NotActive Currently not in HSYNC phase 0 Active Currently in HSYNC phase 1 2 0x80 1-2 LAYER%s Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR 0x84 CR L1CR LTDC Layer Control Register 0x0 0x20 read-write 0x00000000 LEN Layer Enable 0 1 LEN Disabled Layer disabled 0 Enabled Layer enabled 1 COLKEN Color Keying Enable 1 1 COLKEN Disabled Color keying disabled 0 Enabled Color keying enabled 1 CLUTEN Color Look-Up Table Enable 4 1 CLUTEN Disabled Color look-up table disabled 0 Enabled Color look-up table enabled 1 WHPCR L1WHPCR LTDC Layer Window Horizontal Position Configuration Register 0x4 0x20 read-write 0x00000000 WHSTPOS Window Horizontal Start Position 0 12 0 4095 WHSPPOS Window Horizontal Stop Position 16 12 0 4095 WVPCR L1WVPCR LTDC Layer Window Vertical Position Configuration Register 0x8 0x20 read-write 0x00000000 WVSTPOS Window Vertical Start Position 0 11 0 2047 WVSPPOS Window Vertical Stop Position 16 11 0 2047 CKCR L1CKCR LTDC Layer Color Keying Configuration Register 0xC 0x20 read-write 0x00000000 CKBLUE Color Key Blue value 0 8 0 255 CKGREEN Color Key Green value 8 8 0 255 CKRED Color Key Red value 16 8 0 255 PFCR L1PFCR LTDC Layer Pixel Format Configuration Register 0x10 0x20 read-write 0x00000000 PF Pixel Format 0 3 PF ARGB8888 ARGB8888 0 RGB888 RGB888 1 RGB565 RGB565 2 ARGB1555 ARGB1555 3 ARGB4444 ARGB4444 4 L8 L8 (8-bit luminance) 5 AL44 AL44 (4-bit alpha, 4-bit luminance) 6 AL88 AL88 (8-bit alpha, 8-bit luminance) 7 CACR L1CACR LTDC Layer Constant Alpha Configuration Register 0x14 0x20 read-write 0x00000000 CONSTA Constant Alpha 0 8 0 255 DCCR L1DCCR LTDC Layer Default Color Configuration Register 0x18 0x20 read-write 0x00000000 DCBLUE Default Color Blue 0 8 0 255 DCGREEN Default Color Green 8 8 0 255 DCRED Default Color Red 16 8 0 255 DCALPHA Default Color Alpha 24 8 0 255 BFCR L1BFCR LTDC Layer Blending Factors Configuration Register 0x1C 0x20 read-write 0x00000000 BF2 Blending Factor 2 0 3 BF2 Constant BF2 = 1 - constant alpha 5 Pixel BF2 = 1 - pixel alpha * constant alpha 7 BF1 Blending Factor 1 8 3 BF1 Constant BF1 = constant alpha 4 Pixel BF1 = pixel alpha * constant alpha 6 CFBAR L1CFBAR LTDC Layer Color Frame Buffer Address Register 0x28 0x20 read-write 0x00000000 CFBADD Color Frame Buffer Start Address 0 32 0 4294967295 CFBLR L1CFBLR LTDC Layer Color Frame Buffer Length Register 0x2C 0x20 read-write 0x00000000 CFBLL Color Frame Buffer Line Length 0 13 0 8191 CFBP Color Frame Buffer Pitch in bytes 16 13 0 8191 CFBLNR L1CFBLNR LTDC Layer ColorFrame Buffer Line Number Register 0x30 0x20 read-write 0x00000000 CFBLNBR Frame Buffer Line Number 0 11 0 2047 CLUTWR L1CLUTWR LTDC Layerx CLUT Write Register 0x40 0x20 write-only 0x00000000 BLUE Blue value 0 8 0 255 GREEN Green value 8 8 0 255 RED Red value 16 8 0 255 CLUTADD CLUT Address 24 8 0 255 TSC Touch sensing controller TSC 0x40024000 0x0 0x400 registers TSC TSC global interrupt 77 CR CR control register 0x0 0x20 read-write 0x00000000 CTPH Charge transfer pulse high 28 4 CTPL Charge transfer pulse low 24 4 SSD Spread spectrum deviation 17 7 SSE Spread spectrum enable 16 1 SSE Disabled Spread spectrum disabled 0 Enabled Spread spectrum enabled 1 SSPSC Spread spectrum prescaler 15 1 PGPSC pulse generator prescaler 12 3 MCV Max count value 5 3 IODEF I/O Default mode 4 1 IODEF PushPull I/Os are forced to output push-pull low 0 Floating I/Os are in input floating 1 SYNCPOL Synchronization pin polarity 3 1 SYNCPOL FallingEdge Falling edge only 0 RisingEdge Rising edge and high level 1 AM Acquisition mode 2 1 AM Normal Normal acquisition mode (acquisition starts as soon as START bit is set) 0 Synchronized Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) 1 START Start a new acquisition 1 1 START NoStarted Acquisition not started 0 Started Start a new acquisition 1 TSCE Touch sensing controller enable 0 1 TSCE Disabled Touch sensing controller disabled 0 Enabled Touch sensing controller enabled 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 MCEIE Max count error interrupt enable 1 1 MCEIE Disabled Max count error interrupt disabled 0 Enabled Max count error interrupt enabled 1 EOAIE End of acquisition interrupt enable 0 1 EOAIE Disabled End of acquisition interrupt disabled 0 Enabled End of acquisition interrupt enabled 1 ICR ICR interrupt clear register 0x8 0x20 read-write 0x00000000 MCEIC Max count error interrupt clear 1 1 EOAIC End of acquisition interrupt clear 0 1 ISR ISR interrupt status register 0xC 0x20 read-write 0x00000000 MCEF Max count error flag 1 1 EOAF End of acquisition flag 0 1 IOHCR IOHCR I/O hysteresis control register 0x10 0x20 read-write 0xFFFFFFFF 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy Schmitt trigger hysteresis disabled 0 Enabled Gx_IOy Schmitt trigger hysteresis enabled 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOASCR IOASCR I/O analog switch control register 0x18 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy analog switch disabled (opened) 0 Enabled Gx_IOy analog switch enabled (closed) 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOSCR IOSCR I/O sampling control register 0x20 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as sampling capacitor 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOCCR IOCCR I/O channel control register 0x28 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as channel 1 8 0x4 1-8 G%s_IO4 G%s_IO4 3 1 8 0x4 1-8 G%s_IO3 G%s_IO3 2 1 8 0x4 1-8 G%s_IO2 G%s_IO2 1 1 IOGCSR IOGCSR I/O group control status register 0x30 0x20 0x00000000 8 0x1 1-8 G%sS Analog I/O group x status 16 1 read-only G1S Ongoing Acquisition on analog I/O group x is ongoing or not started 0 Complete Acquisition on analog I/O group x is complete 1 8 0x1 1-8 G%sE Analog I/O group x enable 0 1 read-write G1E Disabled Acquisition on analog I/O group x disabled 0 Enabled Acquisition on analog I/O group x enabled 1 8 0x4 1-8 IOG%sCR IOG%sCR I/O group x counter register 0x34 0x20 read-only 0x00000000 CNT Counter value 0 14 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x10 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR Prescaler register 0x4 0x10 read-write 0x00000000 PR Prescaler divider 0 3 PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 true RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value 0 12 0 4095 SR SR Status register 0xC 0x10 read-only 0x00000000 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x10 read-write 0x00000FFF WIN Watchdog counter window value 0 12 0 4095 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR Control register 0x0 0x10 read-write 0x0000007F WDGA Activation bit 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 T 7-bit counter (MSB to LSB) 0 7 0 127 CFR CFR Configuration register 0x4 0x10 read-write 0x0000007F EWI Early wakeup interrupt 9 1 EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base 7 2 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 W 7-bit window value 0 7 0 127 SR SR Status register 0x8 0x10 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 COMP Comparator COMP 0x40010200 0x0 0x200 registers COMP COMP1 and COMP2 interrupts 64 COMP1_CSR COMP1_CSR Comparator 1 control and status register 0x0 0x20 0x00000000 EN Comparator 1 enable bit 0 1 read-write EN Disabled Comparator X disabled 0 Enabled Comparator X enabled 1 PWRMODE Power Mode of the comparator 1 2 2 read-write PWRMODE High High speed 0 Medium Medium speed 1 Low Ultra low power 3 INMSEL Comparator 1 Input Minus connection configuration bit 4 3 read-write INPSEL Comparator1 input plus selection bit 7 1 read-write INPSEL External external IO - PC5 0 PB2 PB2 1 POLARITY Comparator 1 polarity selection bit 15 1 read-write POLARITY Normal Comparator X output value not inverted 0 Inverted Comparator X output value inverted 1 HYST Comparator 1 hysteresis selection bits 16 2 read-write HYST None No hysteresis 0 Low Low hysteresis 1 Medium Medium hysteresis 2 High High hysteresis 3 BLANKING Comparator 1 blanking source selection bits 18 3 read-write BLANKING Disabled No blanking 0 TIM1OC5 TIM1 OC5 selected as blanking source 1 TIM2OC3 TIM2 OC3 selected as blanking source 2 BRGEN Scaler bridge enable 22 1 read-write BRGEN Disabled Scaler resistor bridge disabled 0 Enabled Scaler resistor bridge enabled 1 SCALEN Voltage scaler enable bit 23 1 read-write SCALEN Disabled Voltage scaler disabled 0 Enabled Voltage scaler enabled 1 VALUE Comparator 1 output status bit 30 1 read-only VALUE Low Comparator output is low 0 High Comparator output is high 1 LOCK COMP1_CSR register lock bit 31 1 write-only LOCK Unlocked Comparator CSR bits are read-write 0 Locked Comparator CSR bits are read-only 1 COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x4 0x20 0x00000000 EN Comparator 2 enable bit 0 1 read-write EN Disabled Comparator X disabled 0 Enabled Comparator X enabled 1 PWRMODE Power Mode of the comparator 2 2 2 read-write PWRMODE High High speed 0 Medium Medium speed 1 Low Ultra low power 3 INMSEL Comparator 2 Input Minus connection configuration bit 4 3 read-write INPSEL Comparator 2 Input Plus connection configuration bit 7 1 read-write INPSEL PB4 PB4 0 PB6 PB6 1 WINMODE Windows mode selection bit 9 1 read-write WINMODE Disabled Input plus of Comparator 2 is not connected to Comparator 1 0 Enabled Input plus of Comparator 2 is connected with input plus of Comparator 1 1 POLARITY Comparator 2 polarity selection bit 15 1 read-write POLARITY Normal Comparator X output value not inverted 0 Inverted Comparator X output value inverted 1 HYST Comparator 2 hysteresis selection bits 16 2 read-write HYST None No hysteresis 0 Low Low hysteresis 1 Medium Medium hysteresis 2 High High hysteresis 3 BLANKING Comparator 2 blanking source selection bits 18 3 read-write BLANKING Disabled No blanking 0 TIM15OC1 TIM15 OC1 selected as blanking source 4 BRGEN Scaler bridge enable 22 1 read-write BRGEN Disabled Scaler resistor bridge disabled 0 Enabled Scaler resistor bridge enabled 1 SCALEN Voltage scaler enable bit 23 1 read-write SCALEN Disabled Voltage scaler disabled 0 Enabled Voltage scaler enabled 1 VALUE Comparator 2 output status bit 30 1 read-only VALUE Low Comparator output is low 0 High Comparator output is high 1 LOCK COMP2_CSR register lock bit 31 1 write-only LOCK Unlocked Comparator CSR bits are read-write 0 Locked Comparator CSR bits are read-only 1 FIREWALL Firewall Firewall 0x40011C00 0x0 0x400 registers CSSA CSSA Code segment start address 0x0 0x20 read-write 0x00000000 ADD code segment start address 8 16 0 65535 CSL CSL Code segment length 0x4 0x20 read-write 0x00000000 LENG code segment length 8 14 0 16383 NVDSSA NVDSSA Non-volatile data segment start address 0x8 0x20 read-write 0x00000000 ADD Non-volatile data segment start address 8 16 0 65535 NVDSL NVDSL Non-volatile data segment length 0xC 0x20 read-write 0x00000000 LENG Non-volatile data segment length 8 14 0 16383 VDSSA VDSSA Volatile data segment start address 0x10 0x20 read-write 0x00000000 ADD Volatile data segment start address 6 12 0 1023 VDSL VDSL Volatile data segment length 0x14 0x20 read-write 0x00000000 LENG Non-volatile data segment length 6 12 0 1023 CR CR Configuration register 0x20 0x20 read-write 0x00000000 VDE Volatile data execution 2 1 VDER read NotExecutable Volatile data segment cannot be executed if VDS = 0 0 Executable Volatile data segment is declared executable whatever VDS bit value 1 VDEW write Reset Resets volatile data execution bit 0 VDS Volatile data shared 1 1 VDSR read NotShared Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed 0 Shared Volatile data segment is shared with non protected application code 1 VDSW write Reset Resets volatile data shared bit 0 FPA Firewall pre alarm 0 1 FPAW write PreArmReset Any code executed outside the protected segment when the Firewall is opened will generate a system reset 0 PreArmSet Any code executed outside the protected segment will close the Firewall 1 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 31 I2C1_ER I2C1 error interrupt 32 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match interrupt enable (slave only) 3 1 ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received interrupt enable 4 1 NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE STOP detection Interrupt enable 5 1 STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable 6 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable 7 1 ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter 8 4 DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF 12 1 ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control 16 1 SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable 17 1 NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from STOP enable 18 1 WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus Host address enable 20 1 SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus Device Default address enable 21 1 SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBUS alert enable 22 1 ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable 23 1 PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 AUTOEND Automatic end mode (master mode) 25 1 AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 RELOAD NBYTES reload mode 24 1 RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 NBYTES Number of bytes 16 8 0 255 NACK NACK generation (slave mode) 15 1 oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 STOP Stop generation (master mode) 14 1 oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 START Start generation 13 1 oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 ADD10 10-bit addressing mode (master mode) 11 1 ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 RD_WRN Transfer direction (master mode) 10 1 RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 SADD Slave address bit (master mode) 0 10 0 1023 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 0 1023 OA1MODE Own Address 1 10-bit mode 10 1 OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 0 127 OA2MSK Own Address 2 masks 8 3 OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and donât care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and donât care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and donât care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and donât care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and donât care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and donât care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and donât care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 0 255 SCLH SCL high period (master mode) 8 8 0 255 SDADEL Data hold time 16 4 0 15 SCLDEL Data setup time 20 4 0 15 PRESC Timing prescaler 28 4 0 15 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 0 4095 TIDLE Idle clock timeout detection 12 1 TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B 16 12 0 4095 TEXTEN Extended clock timeout enable 31 1 TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only 0 127 DIR Transfer direction (Slave mode) 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 BUSY Bus busy 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 ALERT SMBus alert 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 TIMEOUT Timeout or t_low detection flag 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 PECERR PEC Error in reception 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 OVR Overrun/Underrun (slave mode) 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 ARLO Arbitration lost 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 BERR Bus error 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 TCR Transfer Complete Reload 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TC Transfer Complete (master mode) 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 STOPF Stop detection flag 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 NACKF Not acknowledge received flag 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 ADDR Address matched (slave mode) 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 RXNE Receive data register not empty (receivers) 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 TXIS Transmit interrupt status (transmitters) 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 TXE Transmit data register empty (transmitters) 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 TIMOUTCF Timeout detection flag clear 12 1 oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 PECCF PEC Error flag clear 11 1 oneToClear PECCF Clear Clears the PEC flag in ISR register 1 OVRCF Overrun/Underrun flag clear 10 1 oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 ARLOCF Arbitration lost flag clear 9 1 oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 BERRCF Bus error flag clear 8 1 oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 STOPCF Stop detection flag clear 5 1 oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 NACKCF Not Acknowledge flag clear 4 1 oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 ADDRCF Address Matched flag clear 3 1 oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 0 255 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 0 255 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 0 255 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 33 I2C2_ER I2C2 error interrupt 34 I2C3 0x40005C00 I2C3_EV I2C3 event interrupt 72 I2C3_ER I2C3 error interrupt 73 I2C4 0x40008400 I2C4_ER I2C4 error interrupt 83 I2C4_EV I2C4 event interrupt 84 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 4 ACR ACR Access control register 0x0 0x20 read-write 0x00000600 LATENCY Latency 0 4 LATENCY WS0 0 wait states 0 WS1 1 wait states 1 WS2 2 wait states 2 WS3 3 wait states 3 WS4 4 wait states 4 WS5 5 wait states 5 WS6 6 wait states 6 WS7 7 wait states 7 WS8 8 wait states 8 WS9 9 wait states 9 WS10 10 wait states 10 WS11 11 wait states 11 WS12 12 wait states 12 WS13 13 wait states 13 WS14 14 wait states 14 WS15 15 wait states 15 PRFTEN Prefetch enable 8 1 PRFTEN Disabled Prefetch is disabled 0 Enabled Prefetch is enabled 1 ICEN Instruction cache enable 9 1 ICEN Disabled Instruction cache is disabled 0 Enabled Instruction cache is enabled 1 DCEN Data cache enable 10 1 DCEN Disabled Data cache is disabled 0 Enabled Data cache is enabled 1 ICRST Instruction cache reset 11 1 ICRST NotReset Instruction cache is not reset 0 Reset Instruction cache is reset 1 DCRST Data cache reset 12 1 DCRST NotReset Data cache is not reset 0 Reset Data cache is reset 1 RUN_PD Flash Power-down mode during Low-power run mode 13 1 RUN_PD Idle Flash in idle mode 0 PowerDown Flash in Power-down mode 1 SLEEP_PD Flash Power-down mode during Low-power sleep mode 14 1 SLEEP_PD Idle Flash in idle mode during Sleep and Low-power sleep modes 0 PowerDown Flash in Power-down mode during Sleep and Low-power sleep modes 1 PDKEYR PDKEYR Power down key register 0x4 0x20 write-only 0x00000000 PDKEYR RUN_PD in FLASH_ACR key 0 32 0 4294967295 KEYR KEYR Flash key register 0x8 0x20 write-only 0x00000000 KEYR KEYR 0 32 0 4294967295 OPTKEYR OPTKEYR Option byte key register 0xC 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 0 4294967295 SR SR Status register 0x10 0x20 0x00000000 EOP End of operation 0 1 read-write EOPR read NoError No error 0 Error Set by hardware when one or more Flash memory operation (programming / erase) has been completed successfully 1 EOPW write Clear Cleared by writing 1 1 OPERR Operation error 1 1 read-write OPERRR read NoError No error 0 Error Set by hardware when a Flash memory operation (program / erase) completes unsuccessfully 1 OPERRW write Clear Cleared by writing 1 1 PROGERR Programming error 3 1 read-write PROGERRR read NoError No error 0 Error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000' 1 PROGERRW write Clear Cleared by writing 1 1 WRPERR Write protected error 4 1 read-write WRPERRR read NoError No error 0 Error Set by hardware when an address to be erased/programmed belongs to a writeprotected part (by WRP, PCROP or RDP level 1) of the Flash memory 1 WRPERRW write Clear Cleared by writing 1 1 PGAERR Programming alignment error 5 1 read-write PGAERRR read NoError No error 0 Error Set by hardware when the data to program cannot be contained in the same 64-bit Flash memory row in case of standard programming, or if there is a change of page during fast programming 1 PGAERRW write Clear Cleared by writing 1 1 SIZERR Size error 6 1 read-write SIZERRR read NoError No error 0 Error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access) 1 SIZERRW write Clear Cleared by writing 1 1 PGSERR Programming sequence error 7 1 read-write PGSERRR read NoError No error 0 Error Set by hardware when a write access to the Flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. Set also when trying to perform bank erase when DBANK=0 (or DB1M = 0) 1 PGSERRW write Clear Cleared by writing 1 1 MISERR Fast programming data miss error 8 1 read-write MISERRR read NoError No error 0 Error In fast programming mode, 32 double words must be sent to Flash successively, and the new data must be sent to the Flash logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time 1 MISERRW write Clear Cleared by writing 1 1 FASTERR Fast programming error 9 1 read-write FASTERRR read NoError No error 0 Error Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time 1 FASTERRW write Clear Cleared by writing 1 1 RDERR PCROP read error 14 1 read-write RDERRR read NoError No error 0 Error Set by hardware when an address to be read through the D-bus belongs to a read protected area of the Flash (PCROP protection) 1 RDERRW write Clear Cleared by writing 1 1 OPTVERR Option validity error 15 1 read-write OPTVERRR read NoError No error 0 Error Set by hardware when the options read may not be the one configured by the user. If option havenât been properly loaded, OPTVERR is set again after each system reset 1 OPTVERRW write Clear Cleared by writing 1 1 BSY Busy 16 1 read-only BSY NotBusy Not busy 0 Busy Busy 1 PEMPTY 17 1 PEMPTY Toggling The bit value is toggling 0 NoEffect No effect 1 CR CR Flash control register 0x14 0x20 read-write 0xC0000000 PG Programming 0 1 PG Disabled Flash programming disabled 0 Enabled Flash programming enabled 1 PER Page erase 1 1 PER Disabled Page erase disabled 0 Enabled Page erase enabled 1 MER1 Bank 1 Mass erase 2 1 MER1W write MassErase This bit triggers the bank 1 mass erase (all bank 1 user pages) when set 1 PNB Page number 3 8 0 255 BKER Bank erase 11 1 BKER Bank1 Bank 1 is selected for page erase 0 Bank2 Bank 2 is selected for page erase 1 MER2 Bank 2 Mass erase 15 1 MER2W write MassErase This bit triggers the bank 2 mass erase (all bank 2 user pages) when set 1 START Start 16 1 STARTR read Complete Cleared when BSY bit is cleared in SR 0 Requested Erase operation requested 1 STARTW write Start Trigger an erase operation 1 OPTSTRT Options modification start 17 1 OPTSTRTR read Complete Cleared when BSY bit is cleared in SR 0 Requested Options modification requested 1 OPTSTRTW write Set This bit triggers an options operation when set 1 FSTPG Fast programming 18 1 FSTPG Disabled Fast programming disabled 0 Enabled Fast programming enabled 1 EOPIE End of operation interrupt enable 24 1 EOPIE Disabled End of operation interrupt disabled 0 Enabled End of operation interrupt enabled 1 ERRIE Error interrupt enable 25 1 ERRIE Disabled Error interrupt generation disabled 0 Enabled Error interrupt generation enabled 1 RDERRIE PCROP read error interrupt enable 26 1 RDERRIE Disabled PCROP read error interrupt disabled 0 Enabled PCROP read error interrupt enabled 1 OBL_LAUNCH Force the option byte loading 27 1 OBL_LAUNCHR read Complete Option byte loading complete 0 Requested Option byte loading requested 1 OBL_LAUNCHW write Set Force option byte reloading 1 OPTLOCK Options Lock 30 1 OPTLOCKR read Unlocked Option page is unlocked 0 Locked All bits concerning user option in FLASH_CR register and so option page are locked 1 OPTLOCKW write Set This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked 1 LOCK FLASH_CR Lock 31 1 LOCKR read Unlocked FLASH_CR register is unlocked 0 Locked FLASH_CR register is locked 1 LOCKW write Set This bit is set only. When set, the FLASH_CR register is locked 1 ECCR ECCR Flash ECC register 0x18 0x20 0x00000000 ADDR_ECC ECC fail address 0 21 read-only 0 2097151 BK_ECC ECC fail bank 19 1 read-only BK_ECC Bank1 Bank 1 0 Bank2 Bank 2 1 SYSF_ECC System Flash ECC fail 20 1 read-only SYSF_ECC InSystemFlash This bit indicates that the ECC error correction or double ECC error detection is located in the System Flash 1 ECCIE ECC correction interrupt enable 24 1 read-write ECCIE Disabled ECCC interrupt disabled 0 Enabled ECCC interrupt enabled 1 ECCC ECC correction 30 1 read-write ECCCR read NoError No ECC error detected on LSB 0 Error Set by hardware when one ECC errors have been detected and corrected on LSB 1 ECCCW write Clear Cleared by writing 1 1 ECCD ECC detection 31 1 read-write ECCDR read NoError No double ECC errors detected on LSB 0 Error Set by hardware when two ECC errors have been detected on LSB 1 ECCDW write Clear Cleared by writing 1 1 ECCD2 ECC2 detection 29 1 ECCD2R read NoError No double ECC errors detected on MSB 0 Error Set by hardware when two ECC errors have been detected on MSB 1 ECCD2W write Clear Cleared by writing 1 1 ECCC2 ECC2 correction 28 1 ECCC2R read NoError No ECC error detected on MSB 0 Error Set by hardware when one ECC errors have been detected and corrected on MSB 1 ECCC2W write Clear Cleared by writing 1 1 OPTR OPTR Flash option register 0x20 0x20 read-write 0xFFEFF8AA RDP Read protection level 0 8 BOR_LEV BOR reset Level 8 3 nRST_STOP nRST_STOP 12 1 nRST_STDBY nRST_STDBY 13 1 IWDG_SW Independent watchdog selection 16 1 IWDG_SW Hardware Hardware independent watchdog 0 Software Software independent watchdog 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 IWDG_STOP Frozen Independent watchdog counter is frozen in Stop mode 0 Running Independent watchdog counter is running in Stop mode 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 IWDG_STDBY Frozen Independent watchdog counter is frozen in Standby mode 0 Running Independent watchdog counter is running in Standby mode 1 WWDG_SW Window watchdog selection 19 1 WWDG_SW Hardware Hardware window watchdog 0 Software Software window watchdog 1 BFB2 Dual-bank boot 20 1 BFB2 Disabled Dual-bank boot disabled 0 Enabled Dual-bank boot enabled 1 nBOOT1 Boot configuration 23 1 SRAM2_PE SRAM2 parity check enable 24 1 SRAM2_PE Enabled SRAM2 parity check enabled 0 Disabled SRAM2 parity check disabled 1 SRAM2_RST SRAM2 Erase when system reset 25 1 SRAM2_RST Enabled SRAM2 erased when a system reset occurs 0 Disabled SRAM2 is not erased when a system reset occurs 1 DBANK 22 1 DBANK SingleBankMode Single-bank mode with 128 bits data read width 0 DualBankMode Dual-bank mode with 64 bits data 1 DB1M 21 1 DB1M SingleBank Single Flash contiguous address in Bank 1 0 DualBank Dual-bank Flash with contiguous addresses 1 nSWBOOT0 Software BOOT0 26 1 nSWBOOT0 OptionBit BOOT0 taken from the option bit nBOOT0 0 Pin BOOT0 taken from PH3/BOOT0 pin 1 nBOOT0 nBOOT0 option bit 27 1 nBOOT0 Disabled nBOOT0 = 0 0 Enabled nBOOT0 = 1 1 PCROP1SR PCROP1SR Flash Bank 1 PCROP Start address register 0x24 0x20 read-write 0xFFFF0000 PCROP1_STRT Bank 1 PCROP area start offset 0 17 0 131071 PCROP1ER PCROP1ER Flash Bank 1 PCROP End address register 0x28 0x20 read-write 0x0FFF0000 PCROP1_END Bank 1 PCROP area end offset 0 17 0 131071 PCROP_RDP PCROP area preserved when RDP level decreased 31 1 PCROP_RDP Disabled PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0 0 Enabled PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 1 WRP1AR WRP1AR Flash Bank 1 WRP area A address register 0x2C 0x20 read-write 0xFF00FF00 WRP1A_STRT Bank 1 WRP first area start offset 0 8 WRP1A_END Bank 1 WRP first area A end offset 16 8 WRP1BR WRP1BR Flash Bank 1 WRP area B address register 0x4C 0x20 read-write 0xFF00FF00 WRP1B_END Bank 1 WRP second area B end offset 16 8 0 255 WRP1B_STRT Bank 1 WRP second area B start offset 0 8 0 255 PCROP2SR PCROP2SR Flash Bank 2 PCROP Start address register 0x44 0x20 read-write 0xFFFF0000 PCROP2_STRT Bank 2 PCROP area start offset 0 17 0 131071 PCROP2ER PCROP2ER Flash Bank 2 PCROP End address register 0x48 0x20 read-write 0xFFFF0000 PCROP2_END Bank 2 PCROP area end offset 0 17 0 131071 WRP2AR WRP2AR Flash Bank 2 WRP area A address register 0x30 0x20 read-write 0xFF00FF00 WRP2A_STRT Bank 2 WRP first area A start offset 0 8 WRP2A_END Bank 2 WRP first area A end offset 16 8 WRP2BR WRP2BR Flash Bank 2 WRP area B address register 0x50 0x20 read-write 0xFF00FF00 WRP2B_STRT Bank 2 WRP second area B start offset 0 8 0 255 WRP2B_END Bank 2 WRP second area B end offset 16 8 0 255 CFGR flash configuration register 0x130 0x00000000 LVEN Low voltage enable 0 1 LVEN Disabled Flash low voltage disabled 0 Enabled Flash low voltage enabled 1 DBGMCU Debug support DBGMCU 0xE0042000 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x00000000 DEV_ID Device Identifier 0 16 REV_ID Revision Identifier 16 16 CR CR Debug MCU Configuration Register 0x4 0x20 read-write 0x00000000 DBG_SLEEP Debug Sleep Mode 0 1 DBG_SLEEP Disabled Debug Sleep Mode Disabled 0 Enabled Debug Sleep Mode Enabled 1 DBG_STOP Debug Stop Mode 1 1 DBG_STOP Disabled Debug Stop Mode Disabled 0 Enabled Debug Stop Mode Enabled 1 DBG_STANDBY Debug Standby Mode 2 1 DBG_STANDBY Disabled Debug Standby Mode Disabled 0 Enabled Debug Standby Mode Enabled 1 TRACE_IOEN Trace pin assignment control 5 1 TRACE_IOEN Disabled Trace pins not assigned (default state) 0 Enabled Trace pins assigned 1 TRACE_MODE Trace pin assignment control 6 2 TRACE_MODE Asynchronous TRACE pin assignment for Asynchronous Mode 0 Size1 TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 1 Size2 TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 2 Size4 TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 3 APB1FZR1 APB1_FZR1 APB Low Freeze Register 1 0x8 0x20 read-write 0x00000000 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_TIMER2_STOP Continue The counter clock of TIMx is fed even if the core is halted 0 Stop The counter clock of TIMx is stopped when the core is halted 1 DBG_TIM3_STOP TIM3 counter stopped when core is halted 1 1 DBG_TIM4_STOP TIM4 counter stopped when core is halted 2 1 DBG_TIM5_STOP TIM5 counter stopped when core is halted 3 1 DBG_TIMER6_STOP Debug Timer 6 stopped when Core is halted 4 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_RTC_STOP Debug RTC stopped when Core is halted 10 1 DBG_RTC_STOP Continue The clock of the RTC counter is fed even if the core is halted 0 Stop The clock of the RTC counter is stopped when the core is halted 1 DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted 11 1 DBG_WWDG_STOP Continue The window watchdog counter clock continues even if the core is halted 0 Stop The window watchdog counter clock is stopped when the core is halted 1 DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted 12 1 DBG_IWDG_STOP Continue The independent watchdog counter clock continues even if the core is halted 0 Stop The independent watchdog counter clock is stopped when the core is halted 1 DBG_I2C1_STOP I2C1 SMBUS timeout mode stopped when core is halted 21 1 DBG_I2C1_STOP NormalMode Same behavior as in normal mode 0 SMBusTimeoutFrozen I2Cx SMBUS timeout is frozen 1 DBG_I2C2_STOP I2C2 SMBUS timeout mode stopped when core is halted 22 1 DBG_I2C3_STOP I2C3 SMBUS timeout counter stopped when core is halted 23 1 DBG_CAN1_STOP bxCAN stopped when core is halted 25 1 DBG_CAN1_STOP NormalMode Same behavior as in normal mode 0 ReceiveRegistersFrozen The bxCAN1 receive registers are frozen 1 DBG_LPTIM1_STOP LPTIM1 counter stopped when core is halted 31 1 DBG_LPTIM1_STOP Continue LPTIMx counter clock is fed even if the core is halted 0 Stop LPTIMx counter clock is stopped when the core is halted 1 APB1FZR2 APB1_FZR2 APB Low Freeze Register 2 0xC 0x20 read-write 0x00000000 DBG_LPTIM2_STOP LPTIM2 counter stopped when core is halted 5 1 DBG_LPTIM2_STOP Continue LPTIMx counter clock is fed even if the core is halted 0 Stop LPTIMx counter clock is stopped when the core is halted 1 DBG_I2C4_STOP I2C4 SMBUS timeout counter stopped when core is halted 1 1 DBG_I2C4_STOP NormalMode Same behavior as in normal mode 0 SMBusTimeoutFrozen I2Cx SMBUS timeout is frozen 1 APB2FZR APB2_FZR APB High Freeze Register 0x10 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM1_STOP Continue The counter clock of TIMx is fed even if the core is halted 0 Stop The counter clock of TIMx is stopped when the core is halted 1 DBG_TIM8_STOP TIM8 counter stopped when core is halted 13 1 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM17_STOP TIM17 counter stopped when core is halted 18 1 OCTOSPI1 OctoSPI OctoSPI 0xA0001000 0x0 0x400 registers OCTOSPI1 OCTOSPI1 global interrupt 71 CR CR control register 0x0 0x20 read-write 0x00000000 FMODE Functional mode 28 2 FMODE IndirectWrite Indirect-write mode 0 IndirectRead Indirect-read mode 1 AutomaticPolling Automatic status-polling mode 2 MemoryMapped Memory-mapped mode 3 PMM Polling match mode 23 1 PMM ANDMatchMode AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register 0 ORMatchmode OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register 1 APMS Automatic poll mode stop 22 1 APMS Running Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI 0 StopMatch Automatic status-polling mode stops as soon as there is a match 1 TEIE Transfer error interrupt enable 16 1 TEIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TOIE TimeOut interrupt enable 20 1 SMIE Status match interrupt enable 19 1 FTIE FIFO threshold interrupt enable 18 1 TCIE Transfer complete interrupt enable 17 1 FTHRES IFO threshold level 8 5 0 31 FSEL FLASH memory selection 7 1 FSEL FLASH1 FLASH 1 selected (data exchanged over IO[3:0]) 0 FLASH2 FLASH 2 selected (data exchanged over IO[7:4]) 1 DMM Dual-memory configuration 6 1 DMM Disabled Dual-quad configuration disabled 0 Enabled Dual-quad configuration enabled 1 TCEN Timeout counter enable 3 1 TCEN Disabled Timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in Memory-mapped mode 0 Enabled Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity 1 DMAEN DMA enable 2 1 DMAEN Disabled DMA disabled for Indirect mode 0 Enabled DMA enabled for Indirect mode 1 ABORT Abort request 1 1 ABORT NotRequested No abort requested 0 Requested Abort requested 1 EN Enable 0 1 EN Disabled OCTOSPI disabled 0 Enabled OCTOSPI enabled 1 DCR1 DCR1 device configuration register 0x8 0x20 read-write 0x00000000 CKMODE Mode 0 / mode 3 0 1 CKMODE Mode0 CLK must stay low while NCS is high (chip-select released). This is referred to as Mode 0 0 Mode3 CLK must stay high while NCS is high (chip-select released). This is referred to as Mode 3 1 FRCK Free running clock 1 1 FRCK Disabled CLK is not free running 0 Enabled CLK is free running (always provided) 1 CSHT Chip-select high time 8 6 0 63 DEVSIZE Device size 16 5 0 31 MTYP Memory type 24 3 MTYP MicronMode Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes 0 MacronixMode Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes 1 StandardMode Standard Mode 2 MacronixRamMode Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping 3 HyperBusMemoryMode HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected 4 HyperBusMode HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used 5 DLYBYP Delay block bypass 3 1 DLYBYP DelayBlockEnabled The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral) 0 DelayBlockBypassed The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. The delay is shorter than when the delay block is not bypassed, even with the delay value set to minimum value in delay block 1 DCR2 DCR2 device configuration register 2 0xC 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 8 0 255 WRAPSIZE Wrap size 16 3 WRAPSIZE NoWrappingSupport Wrapped reads are not supported by the memory 0 WrappingSize16 External memory supports wrap size of 16 bytes 2 WrappingSize32 External memory supports wrap size of 32 bytes 3 WrappingSize64 External memory supports wrap size of 64 bytes 4 WrappingSize128 External memory supports wrap size of 128 bytes 5 DCR3 DCR3 device configuration register 3 0x10 0x20 read-write 0x00000000 CSBOUND CS boundary 16 5 0 31 MAXTRAN Maximum transfer 0 8 0 255 DCR4 DCR4 device configuration register 4 0x14 read-write 0x00000000 REFRESH Refresh rate 0 32 0 4294967295 SR SR status register 0x20 0x20 read-only 0x00000000 TEF Transfer error flag 0 1 TEF Cleared This bit is cleared by writing 1 to CTEF 0 InvalidAddressAccessed This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode 1 TCF Transfer complete flag 1 1 TCF Cleared This bit is cleared by writing 1 to CTCF 0 TransferCompleted This bit is set when the programmed number of data has been transferred 1 FTF FIFO threshold flag 2 1 FTF Cleared It is cleared automatically as soon as the threshold condition is no longer true 0 ThresholdReached This bit is set when the FIFO threshold has been reached 1 SMF Status match flag 3 1 SMF Cleared It is cleared by writing 1 to CSMF 0 Matched This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (OCTOSPI_PSMAR) 1 TOF Timeout flag 4 1 TOF Cleared This bit is cleared by writing 1 to CTOF 0 Timeout This bit is set when timeout occurs 1 BUSY BUSY 5 1 BUSY Cleared This bit is cleared automatically when the operation with the external device is finished and the FIFO is empty 0 Busy This bit is set when an operation is ongoing 1 FLEVEL FIFO level 8 6 0 63 FCR FCR flag clear register 0x24 0x20 write-only 0x00000000 CTEF Clear transfer error flag 0 1 CTEF Clear Writing 1 clears the TEF flag in the OCTOSPI_SR register 1 CTCF Clear transfer complete flag 1 1 CTCF Clear Writing 1 clears the TCF flag in the OCTOSPI_SR register 1 CSMF Clear status match flag 3 1 CSMF Clear Writing 1 clears the SMF flag in the OCTOSPI_SR register 1 CTOF Clear timeout flag 4 1 CTOF Clear Writing 1 clears the TOF flag in the OCTOSPI_SR register 1 DLR DLR data length register 0x40 0x20 read-write 0x00000000 DL Data length 0 32 0 4294967295 AR AR address register 0x48 0x20 read-write 0x00000000 ADDRESS ADDRESS 0 32 0 4294967295 DR DR data register 0x50 0x20 read-write 0x00000000 DATA Data 0 32 0 4294967295 PSMKR PSMKR polling status mask register 0x80 0x20 read-write 0x00000000 MASK Status mask 0 32 0 4294967295 PSMAR PSMAR polling status match register 0x88 0x20 read-write 0x00000000 MATCH Status match 0 32 0 4294967295 PIR PIR polling interval register 0x90 0x20 read-write 0x00000000 INTERVAL Polling interval 0 16 0 65535 CCR CCR communication configuration register 0x100 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR Instruction double transfer rate 3 1 IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE Instruction size 4 2 ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE Address mode 8 3 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR Address double transfer rate 11 1 ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE Address size 12 2 ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE Alternate byte mode 16 3 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR Alternate bytes double transfer rate 19 1 ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE Alternate bytes size 20 2 ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE Data mode 24 3 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR Alternate bytes double transfer rate 27 1 DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQS enable 29 1 DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 SIOO Send instruction only once mode 31 1 SIOO SendEveryTransaction Send instruction on every transaction 0 SendOnlyFirstCmd Send instruction only for the first command 1 TCR TCR timing configuration register 0x108 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 0 31 DHQC Delay hold quarter cycle 28 1 DHQC NoDelay No delay hold 0 QuarterCycleHold 1/4 cycle hold 1 SSHIFT Sample shift 30 1 SSHIFT NoShift No shift 0 HalfCycleShift 1/2 cycle shift 1 IR IR instruction register 0x110 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 0 4294967295 ABR ABR alternate bytes register 0x120 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 0 4294967295 LPTR LPTR low-power timeout register 0x130 0x20 read-write 0x00000000 TIMEOUT Timeout period 0 16 0 65535 WPCCR wrap communication configuration register 0x140 0x00000000 DQSE DQS enable 29 1 DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 DDTR Data double transfer rate 27 1 DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DMODE Data mode 24 3 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 ABSIZE Alternate bytes size 20 2 ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 ABDTR Alternate bytes double transfer rate 19 1 ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABMODE Alternate-byte mode 16 3 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ADSIZE Address size 12 2 ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ADDTR Address double transfer rate 11 1 ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADMODE Address mode 8 3 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ISIZE Instruction size 4 2 ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 IDTR Instruction double transfer rate 3 1 IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 IMODE Instruction mode 0 3 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 WPTCR Wrap timing configuration register 0x148 0x00000000 SSHIFT Sample shift 30 1 SSHIFT NoShift No shift 0 HalfCycleShift 1/2 cycle shift 1 DHQC Delay hold quarter cycle 28 1 DHQC NoDelay No delay hold 0 QuarterCycleHold 1/4 cycle hold 1 DCYC Number of dummy cycles 0 5 0 31 WPIR Wrap instruction register 0x150 0x00000000 INSTRUCTION Instruction 0 32 0 4294967295 WPABR Wrap alternate bytes register 0x160 0x00000000 ALTERNATE Alternate bytes 0 32 0 4294967295 WCCR WCCR write communication configuration register 0x180 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR Instruction double transfer rate 3 1 IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE Instruction size 4 2 ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE Address mode 8 3 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR Address double transfer rate 11 1 ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE Address size 12 2 ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE Alternate byte mode 16 3 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR Alternate bytes double transfer rate 19 1 ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE Alternate bytes size 20 2 ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE Data mode 24 3 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR alternate bytes double transfer rate 27 1 DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQS enable 29 1 DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 WTCR WTCR write timing configuration register 0x188 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 0 31 WIR WIR write instruction register 0x190 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 0 4294967295 WABR WABR write alternate bytes register 0x1A0 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 0 4294967295 HLCR HLCR HyperBusTM latency configuration register 0x200 0x20 read-write 0x00000000 LM Latency mode 0 1 LM Variable Variable initial latency 0 Fixed Fixed latency 1 WZL Write zero latency 1 1 WZL Disabled Latency on write accesses 0 Enabled No latency on write accesses 1 TACC Access time 8 8 0 255 TRWR Read write recovery time 16 8 0 255 OCTOSPI2 0xA0001400 OCTOSPI2 OCTOSPI2 global interrupt 76 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 5 CR CR Clock control register 0x0 0x20 0x00000063 PLLSAI2RDY SAI2 PLL clock ready flag 29 1 read-only PLLSAI2RDY Unlocked PLLSAI2 unlocked 0 Locked PLLSAI2 locked 1 PLLSAI2ON SAI2 PLL enable 28 1 read-write PLLSAI2ON Disabled PLLSAI2 OFF 0 Enabled PLLSAI2 ON 1 PLLSAI1RDY SAI1 PLL clock ready flag 27 1 read-only PLLSAI1RDY Unlocked PLLSAI1 unlocked 0 Locked PLLSAI1 locked 1 PLLSAI1ON SAI1 PLL enable 26 1 read-write PLLSAI1ON Disabled PLLSAI1 OFF 0 Enabled PLLSAI1 ON 1 PLLRDY Main PLL clock ready flag 25 1 read-only PLLRDY Unlocked PLL unlocked 0 Locked PLL locked 1 PLLON Main PLL enable 24 1 read-write PLLON Disabled PLL OFF 0 Enabled PLL ON 1 CSSON Clock security system enable 19 1 write-only CSSON Disabled Clock security system OFF (clock detector OFF) 0 Enabled Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not) 1 HSEBYP HSE crystal oscillator bypass 18 1 read-write HSEBYP NotBypassed HSE crystal oscillator not bypassed 0 Bypassed HSE crystal oscillator bypassed with external clock 1 HSERDY HSE clock ready flag 17 1 read-only HSERDY NotReady HSE oscillator not ready 0 Ready HSE oscillator ready 1 HSEON HSE clock enable 16 1 read-write HSEON Disabled HSE oscillator OFF 0 Enabled HSE oscillator ON 1 HSIASFS HSI automatic start from Stop 11 1 read-write HSIASFS Disabled HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wakeup clock 0 Enabled HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wakeup clock 1 HSIRDY HSI clock ready flag 10 1 read-only HSIRDY NotReady HSI16 oscillator not ready 0 Ready HSI16 oscillator ready 1 HSIKERON HSI always enable for peripheral kernels 9 1 read-write HSIKERON Disabled No effect on HSI16 oscillator 0 Enabled HSI16 oscillator is forced ON even in Stop mode 1 HSION HSI clock enable 8 1 read-write HSION Disabled HSI16 oscillator OFF 0 Enabled HSI16 oscillator ON 1 MSIRANGE MSI clock ranges 4 4 read-write MSIRANGE Range100K range 0 around 100 kHz 0 Range200K range 1 around 200 kHz 1 Range400K range 2 around 400 kHz 2 Range800K range 3 around 800 kHz 3 Range1M range 4 around 1 MHz 4 Range2M range 5 around 2 MHz 5 Range4M range 6 around 4 MHz 6 Range8M range 7 around 8 MHz 7 Range16M range 8 around 16 MHz 8 Range24M range 9 around 24 MHz 9 Range32M range 10 around 32 MHz 10 Range48M range 11 around 48 MHz 11 MSIRGSEL MSI clock range selection 3 1 write-only MSIRGSEL CSR MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register 0 CR MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register 1 MSIPLLEN MSI clock PLL enable 2 1 read-write MSIPLLEN Disabled MSI PLL OFF 0 Enabled MSI PLL ON 1 MSIRDY MSI clock ready flag 1 1 read-only MSIRDY NotReady MSI oscillator not ready 0 Ready MSI oscillator ready 1 MSION MSI clock enable 0 1 read-write MSION Disabled MSI oscillator OFF 0 Enabled MSI oscillator ON 1 ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x10000000 HSITRIM HSI clock trimming 24 7 read-write 0 127 HSICAL HSI clock calibration 16 8 read-only 0 255 MSITRIM MSI clock trimming 8 8 read-write 0 255 MSICAL MSI clock calibration 0 8 read-only 0 255 CFGR CFGR Clock configuration register 0x8 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 3 read-only MCOPRE Divider1 MCO is divided by 1 0 Divider2 MCO is divided by 2 1 Divider4 MCO is divided by 4 2 Divider8 MCO is divided by 8 3 Divider16 MCO is divided by 16 4 MCOSEL Microcontroller clock output 24 4 read-write MCOSEL Disabled MCO output disabled, no clock on MCO 0 SYSCLK SYSCLK system clock selected 1 MSI MSI clock selected. 2 HSI16 HSI16 clock selected. 3 HSE HSE clock selected 4 MainPLL Main PLL clock selected 5 LSI LSI clock selected 6 LSE LSE clock selected 7 HSI48 Internal HSI48 clock selected 8 STOPWUCK Wakeup from Stop and CSS backup clock selection 15 1 read-write STOPWUCK MSI MSI oscillator selected as wakeup from stop clock and CSS backup clock 0 HSI16 HSI16 oscillator selected as wakeup from stop clock and CSS backup clock 1 PPRE1 PB low-speed prescaler (APB1) 8 3 read-write PPRE1 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true PPRE2 APB high-speed prescaler (APB2) 11 3 read-write HPRE AHB prescaler 4 4 read-write HPRE Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 Div1 SYSCLK not divided true SWS System clock switch status 2 2 read-only SWS MSI MSI oscillator used as system clock 0 HSI16 HSI16 oscillator used as system clock 1 HSE HSE used as system clock 2 PLL PLL used as system clock 3 SW System clock switch 0 2 read-write SW MSI MSI selected as system clock 0 HSI16 HSI16 selected as system clock 1 HSE HSE selected as system clock 2 PLL PLL selected as system clock 3 PLLCFGR PLLCFGR PLL configuration register 0xC 0x20 read-write 0x00001000 PLLPDIV Main PLL division factor for PLLSAI2CLK 27 5 PLLPDIV PLLP PLLSAI3CLK is controlled by the bit PLLP 0 Div2 PLLSAI3CLK = VCO / 2 2 Div3 PLLSAI3CLK = VCO / 3 3 Div4 PLLSAI3CLK = VCO / 4 4 Div5 PLLSAI3CLK = VCO / 5 5 Div6 PLLSAI3CLK = VCO / 6 6 Div7 PLLSAI3CLK = VCO / 7 7 Div8 PLLSAI3CLK = VCO / 8 8 Div9 PLLSAI3CLK = VCO / 9 9 Div10 PLLSAI3CLK = VCO / 10 10 Div11 PLLSAI3CLK = VCO / 11 11 Div12 PLLSAI3CLK = VCO / 12 12 Div13 PLLSAI3CLK = VCO / 13 13 Div14 PLLSAI3CLK = VCO / 14 14 Div15 PLLSAI3CLK = VCO / 15 15 Div16 PLLSAI3CLK = VCO / 16 16 Div17 PLLSAI3CLK = VCO / 17 17 Div18 PLLSAI3CLK = VCO / 18 18 Div19 PLLSAI3CLK = VCO / 19 19 Div20 PLLSAI3CLK = VCO / 20 20 Div21 PLLSAI3CLK = VCO / 21 21 Div22 PLLSAI3CLK = VCO / 22 22 Div23 PLLSAI3CLK = VCO / 23 23 Div24 PLLSAI3CLK = VCO / 24 24 Div25 PLLSAI3CLK = VCO / 25 25 Div26 PLLSAI3CLK = VCO / 26 26 Div27 PLLSAI3CLK = VCO / 27 27 Div28 PLLSAI3CLK = VCO / 28 28 Div29 PLLSAI3CLK = VCO / 29 29 Div30 PLLSAI3CLK = VCO / 30 30 Div31 PLLSAI3CLK = VCO / 31 31 PLLQ Main PLL division factor for PLLUSB1CLK(48 MHz clock) 21 2 PLLQ Div2 PLLx = 2 0 Div4 PLLx = 4 1 Div6 PLLx = 6 2 Div8 PLLx = 8 3 PLLR Main PLL division factor for PLLCLK (system clock) 25 2 PLLREN Main PLL PLLCLK output enable 24 1 PLLREN Disabled PLLCLK output disable 0 Enabled PLLCLK output enabled 1 PLLQEN Main PLL PLLUSB1CLK output enable 20 1 PLLQEN Disabled PLL48M1CLK output disable 0 Enabled PLL48M1CLK output enabled 1 PLLP Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) 17 1 PLLP Div7 PLLP = 7 0 Div17 PLLP = 17 1 PLLPEN Main PLL PLLSAI3CLK output enable 16 1 PLLPEN Disabled PLLSAI3CLK output disable 0 Enabled PLLSAI3CLK output enabled 1 PLLN Main PLL multiplication factor for VCO 8 7 8 127 PLLM Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock 4 4 PLLM Div1 PLLM = 1 0 Div2 PLLM = 2 1 Div3 PLLM = 3 2 Div4 PLLM = 4 3 Div5 PLLM = 5 4 Div6 PLLM = 6 5 Div7 PLLM = 7 6 Div8 PLLM = 8 7 Div9 PLLM = 9 8 Div10 PLLM = 11 9 Div11 PLLM = 12 10 Div12 PLLM = 13 11 Div13 PLLM = 13 12 Div14 PLLM = 14 13 Div15 PLLM = 15 14 Div16 PLLM = 16 15 PLLSRC Main PLL, PLLSAI1 and PLLSAI2 entry clock source 0 2 PLLSRC NoClock No clock sent to PLL 0 MSI MSI clock selected as PLL clock entry 1 HSI16 HSI16 clock selected as PLL clock entry 2 HSE HSE clock selected as PLL clock entry 3 PLLSAI1CFGR PLLSAI1CFGR PLLSAI1 configuration register 0x10 0x20 read-write 0x00001000 PLLSAI1PDIV PLLSAI1 division factor for PLLSAI1CLK 27 5 PLLSAI1PDIV PLLSAI1P PLLSAI1CLK is controlled by the bit PLLSAI1P 0 Div2 PLLSAI1CLK = VCOSAI / 2 2 Div3 PLLSAI1CLK = VCOSAI / 3 3 Div4 PLLSAI1CLK = VCOSAI / 4 4 Div5 PLLSAI1CLK = VCOSAI / 5 5 Div6 PLLSAI1CLK = VCOSAI / 6 6 Div7 PLLSAI1CLK = VCOSAI / 7 7 Div8 PLLSAI1CLK = VCOSAI / 8 8 Div9 PLLSAI1CLK = VCOSAI / 9 9 Div10 PLLSAI1CLK = VCOSAI / 10 10 Div11 PLLSAI1CLK = VCOSAI / 11 11 Div12 PLLSAI1CLK = VCOSAI / 12 12 Div13 PLLSAI1CLK = VCOSAI / 13 13 Div14 PLLSAI1CLK = VCOSAI / 14 14 Div15 PLLSAI1CLK = VCOSAI / 15 15 Div16 PLLSAI1CLK = VCOSAI / 16 16 Div17 PLLSAI1CLK = VCOSAI / 17 17 Div18 PLLSAI1CLK = VCOSAI / 18 18 Div19 PLLSAI1CLK = VCOSAI / 19 19 Div20 PLLSAI1CLK = VCOSAI / 20 20 Div21 PLLSAI1CLK = VCOSAI / 21 21 Div22 PLLSAI1CLK = VCOSAI / 22 22 Div23 PLLSAI1CLK = VCOSAI / 23 23 Div24 PLLSAI1CLK = VCOSAI / 24 24 Div25 PLLSAI1CLK = VCOSAI / 25 25 Div26 PLLSAI1CLK = VCOSAI / 26 26 Div27 PLLSAI1CLK = VCOSAI / 27 27 Div28 PLLSAI1CLK = VCOSAI / 28 28 Div29 PLLSAI1CLK = VCOSAI / 29 29 Div30 PLLSAI1CLK = VCOSAI / 30 30 Div31 PLLSAI1CLK = VCOSAI / 31 31 PLLSAI1Q SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) 21 2 PLLSAI1Q Div2 PLLSAI1x = 2 0 Div4 PLLSAI1x = 4 1 Div6 PLLSAI1x = 6 2 Div8 PLLSAI1x = 8 3 PLLSAI1R PLLSAI1 division factor for PLLADC1CLK (ADC clock) 25 2 PLLSAI1REN PLLSAI1 PLLADC1CLK output enable 24 1 PLLSAI1REN Disabled PLLADC1CLK output disable 0 Enabled PLLADC1CLK output enabled 1 PLLSAI1QEN SAI1PLL PLLUSB2CLK output enable 20 1 PLLSAI1QEN Disabled PLL48M2CLK output disable 0 Enabled PLL48M2CLK output enabled 1 PLLSAI1P SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) 17 1 PLLSAI1P Div7 PLLSAI1P = 7 0 Div17 PLLSAI1P = 17 1 PLLSAI1PEN SAI1PLL PLLSAI1CLK output enable 16 1 PLLSAI1PEN Disabled PLLSAI1CLK output disable 0 Enabled PLLSAI1CLK output enabled 1 PLLSAI1N SAI1PLL multiplication factor for VCO 8 7 8 127 PLLSAI1M Division factor for PLLSAI1 input clock 4 4 PLLSAI1M Div1 PLLSAI1M = 1 0 Div2 PLLSAI1M = 2 1 Div3 PLLSAI1M = 3 2 Div4 PLLSAI1M = 4 3 Div5 PLLSAI1M = 5 4 Div6 PLLSAI1M = 6 5 Div7 PLLSAI1M = 7 6 Div8 PLLSAI1M = 8 7 Div9 PLLSAI1M = 9 8 Div10 PLLSAI1M = 11 9 Div11 PLLSAI1M = 12 10 Div12 PLLSAI1M = 13 11 Div13 PLLSAI1M = 13 12 Div14 PLLSAI1M = 14 13 Div15 PLLSAI1M = 15 14 Div16 PLLSAI1M = 16 15 PLLSAI2CFGR PLLSAI2CFGR PLLSAI2 configuration register 0x14 0x20 read-write 0x00001000 PLLSAI2PDIV PLLSAI2 division factor for PLLSAI2CLK 27 5 PLLSAI2PDIV PLLSAI1P PLLSAI2CLK is controlled by the bit PLLSAI2P 0 Div2 PLLSAI2CLK = VCOSAI2 / 2 2 Div3 PLLSAI2CLK = VCOSAI2 / 3 3 Div4 PLLSAI2CLK = VCOSAI2 / 4 4 Div5 PLLSAI2CLK = VCOSAI2 / 5 5 Div6 PLLSAI2CLK = VCOSAI2 / 6 6 Div7 PLLSAI2CLK = VCOSAI2 / 7 7 Div8 PLLSAI2CLK = VCOSAI2 / 8 8 Div9 PLLSAI2CLK = VCOSAI2 / 9 9 Div10 PLLSAI2CLK = VCOSAI2 / 10 10 Div11 PLLSAI2CLK = VCOSAI2 / 11 11 Div12 PLLSAI2CLK = VCOSAI2 / 12 12 Div13 PLLSAI2CLK = VCOSAI2 / 13 13 Div14 PLLSAI2CLK = VCOSAI2 / 14 14 Div15 PLLSAI2CLK = VCOSAI2 / 15 15 Div16 PLLSAI2CLK = VCOSAI2 / 16 16 Div17 PLLSAI2CLK = VCOSAI2 / 17 17 Div18 PLLSAI2CLK = VCOSAI2 / 18 18 Div19 PLLSAI2CLK = VCOSAI2 / 19 19 Div20 PLLSAI2CLK = VCOSAI2 / 20 20 Div21 PLLSAI2CLK = VCOSAI2 / 21 21 Div22 PLLSAI2CLK = VCOSAI2 / 22 22 Div23 PLLSAI2CLK = VCOSAI2 / 23 23 Div24 PLLSAI2CLK = VCOSAI2 / 24 24 Div25 PLLSAI2CLK = VCOSAI2 / 25 25 Div26 PLLSAI2CLK = VCOSAI2 / 26 26 Div27 PLLSAI2CLK = VCOSAI2 / 27 27 Div28 PLLSAI2CLK = VCOSAI2 / 28 28 Div29 PLLSAI2CLK = VCOSAI2 / 29 29 Div30 PLLSAI2CLK = VCOSAI2 / 30 30 Div31 PLLSAI2CLK = VCOSAI2 / 31 31 PLLSAI2Q SAI2PLL PLLSAI2CLK output enable 21 2 PLLSAI2Q Div2 PLLSAI2x = 2 0 Div4 PLLSAI2x = 4 1 Div6 PLLSAI2x = 6 2 Div8 PLLSAI2x = 8 3 PLLSAI2R PLLSAI2 division factor for PLLADC2CLK (ADC clock) 25 2 PLLSAI2REN PLLSAI2 PLLADC2CLK output enable 24 1 PLLSAI2REN Disabled PLLLCDCLK output disable 0 Enabled PLLLCDCLK output enabled 1 PLLSAI2QEN PLLSAI2 division factor for PLLDISCLK 20 1 PLLSAI2QEN Disabled PLLDSICLK output disable 0 Enabled PLLDSICLK output enabled 1 PLLSAI2P SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) 17 1 PLLSAI2P Div7 PLLSAI2P = 7 0 Div17 PLLSAI2P = 17 1 PLLSAI2PEN SAI2PLL PLLSAI2CLK output enable 16 1 PLLSAI2PEN Disabled PLLSAI2CLK output disable 0 Enabled PLLSAI2CLK output enabled 1 PLLSAI2N SAI2PLL multiplication factor for VCO 8 7 8 127 PLLSAI2M Division factor for PLLSAI2 input clock 4 4 PLLSAI2M Div1 PLLSAI2M = 1 0 Div2 PLLSAI2M = 2 1 Div3 PLLSAI2M = 3 2 Div4 PLLSAI2M = 4 3 Div5 PLLSAI2M = 5 4 Div6 PLLSAI2M = 6 5 Div7 PLLSAI2M = 7 6 Div8 PLLSAI2M = 8 7 Div9 PLLSAI2M = 9 8 Div10 PLLSAI2M = 11 9 Div11 PLLSAI2M = 12 10 Div12 PLLSAI2M = 13 11 Div13 PLLSAI2M = 13 12 Div14 PLLSAI2M = 14 13 Div15 PLLSAI2M = 15 14 Div16 PLLSAI2M = 16 15 CIER CIER Clock interrupt enable register 0x18 0x20 read-write 0x00000000 LSIRDYIE LSI ready interrupt enable 0 1 LSIRDYIE Disabled LSI ready interrupt disabled 0 Enabled LSI ready interrupt enabled 1 LSERDYIE LSE ready interrupt enable 1 1 LSERDYIE Disabled LSE ready interrupt disabled 0 Enabled LSE ready interrupt enabled 1 MSIRDYIE MSI ready interrupt enable 2 1 MSIRDYIE Disabled MSI ready interrupt disabled 0 Enabled MSI ready interrupt enabled 1 HSIRDYIE HSI ready interrupt enable 3 1 HSIRDYIE Disabled HSI16 ready interrupt disabled 0 Enabled HSI16 ready interrupt enabled 1 HSERDYIE HSE ready interrupt enable 4 1 HSERDYIE Disabled HSE ready interrupt disabled 0 Enabled HSE ready interrupt enabled 1 PLLRDYIE PLL ready interrupt enable 5 1 PLLRDYIE Disabled PLL lock interrupt disabled 0 Enabled PLL lock interrupt enabled 1 PLLSAI1RDYIE PLLSAI1 ready interrupt enable 6 1 PLLSAI1RDYIE Disabled PLLSAI1 lock interrupt disabled 0 Enabled PLLSAI1 lock interrupt enabled 1 PLLSAI2RDYIE PLLSAI2 ready interrupt enable 7 1 PLLSAI2RDYIE Disabled PLLSAI2 lock interrupt disabled 0 Enabled PLLSAI2 lock interrupt enabled 1 LSECSSIE LSE clock security system interrupt enable 9 1 LSECSSIE Disabled Clock security interrupt caused by LSE clock failure disabled 0 Enabled Clock security interrupt caused by LSE clock failure enabled 1 HSI48RDYIE HSI48 ready interrupt enable 10 1 HSI48RDYIE Disabled HSI48 ready interrupt disabled 0 Enabled HSI48 ready interrupt enabled 1 CIFR CIFR Clock interrupt flag register 0x1C 0x20 read-only 0x00000000 LSIRDYF LSI ready interrupt flag 0 1 LSIRDYF NoInterrupt No clock ready interrupt caused by the LSI oscillator 0 Interrupt Clock ready interrupt caused by the LSI oscillator 1 LSERDYF LSE ready interrupt flag 1 1 LSERDYF NoInterrupt No clock ready interrupt caused by the LSE oscillator 0 Interrupt Clock ready interrupt caused by the LSE oscillator 1 MSIRDYF MSI ready interrupt flag 2 1 MSIRDYF NoInterrupt No clock ready interrupt caused by the MSI oscillator 0 Interrupt Clock ready interrupt caused by the MSI oscillator 1 HSIRDYF HSI ready interrupt flag 3 1 HSIRDYF NoInterrupt No clock ready interrupt caused by the HSI16 oscillator 0 Interrupt Clock ready interrupt caused by the HSI16 oscillator 1 HSERDYF HSE ready interrupt flag 4 1 HSERDYF NoInterrupt No clock ready interrupt caused by the HSE oscillator 0 Interrupt Clock ready interrupt caused by the HSE oscillator 1 PLLRDYF PLL ready interrupt flag 5 1 PLLRDYF NoInterrupt No clock ready interrupt caused by PLL lock 0 Interrupt Clock ready interrupt caused by PLL lock 1 PLLSAI1RDYF PLLSAI1 ready interrupt flag 6 1 PLLSAI1RDYF NoInterrupt No clock ready interrupt caused by PLLSAI1 lock 0 Interrupt Clock ready interrupt caused by PLLSAI1 lock 1 PLLSAI2RDYF PLLSAI2 ready interrupt flag 7 1 PLLSAI2RDYF NoInterrupt No clock ready interrupt caused by PLLSAI2 lock 0 Interrupt Clock ready interrupt caused by PLLSAI2 lock 1 CSSF Clock security system interrupt flag 8 1 CSSF NoInterrupt No clock security interrupt caused by HSE clock failure 0 Interrupt Clock security interrupt caused by HSE clock failure 1 LSECSSF LSE Clock security system interrupt flag 9 1 LSECSSF NoInterrupt No clock security interrupt caused by LSE clock failure 0 Interrupt Clock security interrupt caused by LSE clock failure 1 HSI48RDYF HSI48 ready interrupt flag 10 1 HSI48RDYF NoInterrupt No clock ready interrupt caused by the HSI48 oscillator 0 Interrupt Clock ready interrupt caused by the HSI48 oscillator 1 CICR CICR Clock interrupt clear register 0x20 0x20 write-only 0x00000000 LSIRDYC LSI ready interrupt clear 0 1 LSIRDYC Clear Clear the LSIRDYF flag 1 LSERDYC LSE ready interrupt clear 1 1 LSERDYC Clear Clear the LSERDYF flag 1 MSIRDYC MSI ready interrupt clear 2 1 MSIRDYC Clear Clear the MSIRDYF flag 1 HSIRDYC HSI ready interrupt clear 3 1 HSIRDYC Clear Clear HSIRDYF flag 1 HSERDYC HSE ready interrupt clear 4 1 HSERDYC Clear Clear HSERDYF flag 1 PLLRDYC PLL ready interrupt clear 5 1 PLLRDYC Clear Clear PLLRDYF flag 1 PLLSAI1RDYC PLLSAI1 ready interrupt clear 6 1 PLLSAI1RDYC Clear Clear PLLSAI1RDYF flag 1 PLLSAI2RDYC PLLSAI2 ready interrupt clear 7 1 PLLSAI2RDYC Clear Clear PLLSAI2RDYF flag 1 CSSC Clock security system interrupt clear 8 1 CSSC Clear Clear the CSSF flag 1 LSECSSC LSE Clock security system interrupt clear 9 1 LSECSSC Clear Clear the LSECSSF flag 1 HSI48RDYC HSI48 oscillator ready interrupt clear 10 1 HSI48RDYC Clear Clear the HSI48RDYC flag 1 AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x28 0x20 read-write 0x00000000 DMA1RST DMA1 reset 0 1 DMA1RST NoEffect No effect 0 Reset Reset DMA1 1 DMA2RST DMA2 reset 1 1 DMA2RST NoEffect No effect 0 Reset Reset DMA2 1 DMAMUX1RST DMAMUXRST 2 1 DMAMUX1RST NoEffect No effect 0 Reset Reset DMAMUX1 1 FLASHRST Flash memory interface reset 8 1 FLASHRST NoEffect No effect 0 Reset Reset Flash memory interface 1 CRCRST CRC reset 12 1 CRCRST NoEffect No effect 0 Reset Reset CRC 1 TSCRST Touch Sensing Controller reset 16 1 TSCRST NoEffect No effect 0 Reset Reset TSC 1 DMA2DRST DMA2D reset 17 1 DMA2DRST NoEffect No effect 0 Reset Reset DMA2D 1 GFXMMURST GFXMMU reset 18 1 GFXMMURST NoEffect No effect 0 Reset Reset GFXMMU 1 AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x2C 0x20 read-write 0x00000000 GPIOARST IO port A reset 0 1 GPIOARST NoEffect No effect 0 Reset Reset GPIO port x 1 GPIOBRST IO port B reset 1 1 GPIOCRST IO port C reset 2 1 GPIODRST IO port D reset 3 1 GPIOERST IO port E reset 4 1 GPIOFRST IO port F reset 5 1 GPIOGRST IO port G reset 6 1 GPIOHRST IO port H reset 7 1 GPIOIRST IO port I reset 8 1 OTGFSRST USB OTG FS reset 12 1 OTGFSRST NoEffect No effect 0 Reset Reset USB OTG FS 1 ADCRST ADC reset 13 1 ADCRST NoEffect No effect 0 Reset Reset ADC 1 DCMIRST Digital Camera Interface reset 14 1 DCMIRST NoEffect No effect 0 Reset Reset DCMI/PSSI interface 1 AESRST AES hardware accelerator reset 16 1 AESRST NoEffect No effect 0 Reset Reset AES 1 HASHRST Hash reset 17 1 HASHRST NoEffect No effect 0 Reset Reset HASH 1 RNGRST Random number generator reset 18 1 RNGRST NoEffect No effect 0 Reset Reset RNG 1 OSPIMRST OCTOSPI IO manager reset 20 1 OSPIMRST NoEffect No effect 0 Reset Reset OctoSPI IO manager 1 SDMMC1RST SDMMC1 reset 22 1 SDMMC1RST NoEffect No effect 0 Reset Reset SDMMC1 1 SDMMC2RST SDMMC2 reset 23 1 SDMMC2RST NoEffect No effect 0 Reset Reset SDMMC2 1 PKARST PKA reset 15 1 PKARST NoEffect No effect 0 Reset Reset PKA 1 AHB3RSTR AHB3RSTR AHB3 peripheral reset register 0x30 0x20 read-write 0x00000000 FMCRST Flexible memory controller reset 0 1 FMCRST NoEffect No effect 0 Reset Reset FMC 1 OSPI1RST OctoSPI1 memory interface reset 8 1 OSPI1RST NoEffect No effect 0 Reset Reset OctoSPIx 1 OSPI2RST OctOSPI2 memory interface reset 9 1 APB1RSTR1 APB1RSTR1 APB1 peripheral reset register 1 0x38 0x20 read-write 0x00000000 LPTIM1RST Low Power Timer 1 reset 31 1 LPTIM1RST NoEffect No effect 0 Reset Reset LPTIM1 1 OPAMPRST OPAMP interface reset 30 1 OPAMPRST NoEffect No effect 0 Reset Reset OPAMP 1 DAC1RST DAC1 interface reset 29 1 DAC1RST NoEffect No effect 0 Reset Reset DAC1 1 PWRRST Power interface reset 28 1 PWRRST NoEffect No effect 0 Reset Reset PWR 1 CAN1RST CAN1 reset 25 1 CAN1RST NoEffect No effect 0 Reset Reset CAN1 1 CRSRST CRS reset 24 1 CRSRST NoEffect No effect 0 Reset Reset CRS 1 I2C1RST I2C1 reset 21 1 I2C1RST NoEffect No effect 0 Reset Reset I2Cx 1 I2C3RST I2C3 reset 23 1 I2C2RST I2C2 reset 22 1 UART5RST UART5 reset 20 1 UART4RST UART4 reset 19 1 USART2RST USART2 reset 17 1 USART2RST NoEffect No effect 0 Reset Reset UARTx 1 USART3RST USART3 reset 18 1 SPI2RST SPI2 reset 14 1 SPI2RST NoEffect No effect 0 Reset Reset SPIx 1 SPI3RST SPI3 reset 15 1 TIM2RST TIM2 timer reset 0 1 TIM2RST NoEffect No effect 0 Reset Reset TIMx 1 TIM7RST TIM7 timer reset 5 1 TIM6RST TIM6 timer reset 4 1 TIM5RST TIM5 timer reset 3 1 TIM4RST TIM3 timer reset 2 1 TIM3RST TIM3 timer reset 1 1 APB1RSTR2 APB1RSTR2 APB1 peripheral reset register 2 0x3C 0x20 read-write 0x00000000 LPUART1RST Low-power UART 1 reset 0 1 LPUART1RST NoEffect No effect 0 Reset Reset LPUART1 1 I2C4RST I2C4 reset 1 1 I2C4RST NoEffect No effect 0 Reset Reset I2C4 1 LPTIM2RST Low-power timer 2 reset 5 1 LPTIM2RST NoEffect No effect 0 Reset Reset LPTIM2 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x40 0x20 read-write 0x00000000 SYSCFGRST System configuration (SYSCFG) reset 0 1 SYSCFGRST NoEffect No effect 0 Reset Reset SYSCFG + COMP + VREFBUF 1 TIM1RST TIM1 timer reset 11 1 TIM1RST NoEffect No effect 0 Reset Reset TIMx 1 SPI1RST SPI1 reset 12 1 SPI1RST NoEffect No effect 0 Reset Reset SPI1 1 TIM8RST TIM8 timer reset 13 1 USART1RST USART1 reset 14 1 USART1RST NoEffect No effect 0 Reset Reset UARTx 1 TIM15RST TIM15 timer reset 16 1 TIM16RST TIM16 timer reset 17 1 TIM17RST TIM17 timer reset 18 1 SAI1RST Serial audio interface 1 (SAI1) reset 21 1 SAI1RST NoEffect No effect 0 Reset Reset SAIx 1 SAI2RST Serial audio interface 2 (SAI2) reset 22 1 DFSDM1RST Digital filters for sigma-delata modulators (DFSDM) reset 24 1 DFSDM1RST NoEffect No effect 0 Reset Reset DFSDM1 1 LTDCRST LCD-TFT reset 26 1 LTDCRST NoEffect No effect 0 Reset Reset LCD-TFT 1 DSIRST DSI reset 27 1 DSIRST NoEffect No effect 0 Reset Reset DSI 1 AHB1ENR AHB1ENR AHB1 peripheral clock enable register 0x48 0x20 read-write 0x00000100 DMA1EN DMA1 clock enable 0 1 DMA1EN Disabled DMAx clock disabled 0 Enabled DMAx clock enabled 1 DMA2EN DMA2 clock enable 1 1 DMAMUX1EN DMAMUX clock enable 2 1 DMAMUX1EN Disabled DMAMUX1 clock disabled 0 Enabled DMAMUX1 clock enabled 1 FLASHEN Flash memory interface clock enable 8 1 FLASHEN Disabled Flash memory interface clock disabled 0 Enabled Flash memory interface clock enabled 1 CRCEN CRC clock enable 12 1 CRCEN Disabled CRC clock disabled 0 Enabled CRC clock enabled 1 TSCEN Touch Sensing Controller clock enable 16 1 TSCEN Disabled TSC clock disabled 0 Enabled TSC clock enabled 1 DMA2DEN DMA2D clock enable 17 1 DMA2DEN Disabled DMA2D clock disabled 0 Enabled DMA2D clock enabled 1 GFXMMUEN Graphic MMU clock enable 18 1 GFXMMUEN Disabled GFXMMU clock disabled 0 Enabled GFXMMU clock enabled 1 AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x4C 0x20 read-write 0x00000000 GPIOAEN IO port A clock enable 0 1 GPIOAEN Disabled IO port x clock disabled 0 Enabled IO port x clock enabled 1 GPIOBEN IO port B clock enable 1 1 GPIOCEN IO port C clock enable 2 1 GPIODEN IO port D clock enable 3 1 GPIOEEN IO port E clock enable 4 1 GPIOFEN IO port F clock enable 5 1 GPIOGEN IO port G clock enable 6 1 GPIOHEN IO port H clock enable 7 1 GPIOIEN IO port I clock enable 8 1 OTGFSEN OTG full speed clock enable 12 1 OTGFSEN Disabled USB OTG full speed clock disabled 0 Enabled USB OTG full speed clock enabled 1 ADCEN ADC clock enable 13 1 ADCEN Disabled ADC clock disabled 0 Enabled ADC clock enabled 1 DCMIEN DCMI clock enable 14 1 DCMIEN Disabled DCMI/PSSI clock disabled 0 Enabled DCMI/PSSI clock enabled 1 AESEN AES accelerator clock enable 16 1 AESEN Disabled AES clock disabled 0 Enabled AES clock enabled 1 HASHEN HASH clock enable 17 1 HASHEN Disabled HASH clock disabled 0 Enabled HASH clock enabled 1 RNGEN Random Number Generator clock enable 18 1 RNGEN Disabled Random Number Generator clock disabled 0 Enabled Random Number Generator clock enabled 1 OSPIMEN OctoSPI IO manager clock enable 20 1 OSPIMEN Disabled OctoSPI IO manager clock disabled 0 Enabled OctoSPI IO manager clock enabled 1 SDMMC1EN SDMMC1 clock enable 22 1 SDMMC1EN Disabled SDMMCx clock disabled 0 Enabled SDMMCx clock enabled 1 SDMMC2EN SDMMC2 clock enable 23 1 PKAEN PKA clock enable 15 1 PKAEN Disabled PKA clock disabled 0 Enabled PKA clock enabled 1 AHB3ENR AHB3ENR AHB3 peripheral clock enable register 0x50 0x20 read-write 0x00000000 FMCEN Flexible memory controller clock enable 0 1 FMCEN Disabled FMC clock disabled 0 Enabled FMC clock enabled 1 OSPI1EN OctoSPI1 memory interface clock enable 8 1 OSPI1EN Disabled OctoSPI x clock disabled 0 Enabled OctoSPI x clock enabled 1 OSPI2EN OSPI2EN memory interface clock enable 9 1 APB1ENR1 APB1ENR1 APB1ENR1 0x58 0x20 read-write 0x00000400 TIM2EN TIM2 timer clock enable 0 1 TIM2EN Disabled TIMx clock disabled 0 Enabled TIMx clock enabled 1 TIM3EN TIM3 timer clock enable 1 1 TIM4EN TIM4 timer clock enable 2 1 TIM5EN TIM5 timer clock enable 3 1 TIM6EN TIM6 timer clock enable 4 1 TIM7EN TIM7 timer clock enable 5 1 RTCAPBEN RTC APB clock enable 10 1 RTCAPBEN Disabled RTC APB clock disabled 0 Enabled RTC APB clock enabled 1 WWDGEN Window watchdog clock enable 11 1 WWDGEN Disabled Window watchdog clock disabled 0 Enabled Window watchdog clock enabled 1 SPI2EN SPI2 clock enable 14 1 SPI2EN Disabled SPIx clock disabled 0 Enabled SPIx clock enabled 1 SPI3EN SPI3 clock enable 15 1 USART2EN USART2 clock enable 17 1 USART2EN Disabled USARTx clock disabled 0 Enabled USARTx clock enabled 1 USART3EN USART3 clock enable 18 1 UART4EN UART4 clock enable 19 1 UART4EN Disabled UARTx clock disabled 0 Enabled UARTx clock enabled 1 UART5EN UART5 clock enable 20 1 I2C1EN I2C1 clock enable 21 1 I2C1EN Disabled I2C1 clock disabled 0 Enabled I2C1 clock enabled 1 I2C2EN I2C2 clock enable 22 1 I2C2EN Disabled I2C2 clock disabled 0 Enabled I2C2 clock enabled 1 I2C3EN I2C3 clock enable 23 1 I2C3EN Disabled I2C3 clock disabled 0 Enabled I2C3 clock enabled 1 CRSEN Clock Recovery System clock enable 24 1 CRSEN Disabled CRS clock disabled 0 Enabled CRS clock enabled 1 CAN1EN CAN1 clock enable 25 1 CAN1EN Disabled CAN1 clock disabled 0 Enabled CAN1 clock enabled 1 PWREN Power interface clock enable 28 1 PWREN Disabled Power interface clock disabled 0 Enabled Power interface clock enabled 1 DAC1EN DAC1 interface clock enable 29 1 DAC1EN Disabled DAC1 clock disabled 0 Enabled DAC1 clock enabled 1 OPAMPEN OPAMP interface clock enable 30 1 OPAMPEN Disabled OPAMP clock disabled 0 Enabled OPAMP clock enabled 1 LPTIM1EN Low power timer 1 clock enable 31 1 LPTIM1EN Disabled LPTIM1 clock disabled 0 Enabled LPTIM1 clock enabled 1 APB1ENR2 APB1ENR2 APB1 peripheral clock enable register 2 0x5C 0x20 read-write 0x00000000 LPUART1EN Low power UART 1 clock enable 0 1 LPUART1EN Disabled LPUART1 clock disabled 0 Enabled LPUART1 clock enabled 1 I2C4EN I2C4 clock enable 1 1 I2C4EN Disabled I2C4 clock disabled 0 Enabled I2C4 clock enabled 1 LPTIM2EN LPTIM2EN 5 1 LPTIM2EN Disabled LPTIM2 clock disabled 0 Enabled LPTIM2 clock enabled 1 APB2ENR APB2ENR APB2ENR 0x60 0x20 read-write 0x00000000 SYSCFGEN SYSCFG clock enable 0 1 SYSCFGEN Disabled SYSCFG + COMP + VREFBUF clock disabled 0 Enabled SYSCFG + COMP + VREFBUF clock enabled 1 FWEN Firewall clock enable 7 1 FWEN Disabled Firewall clock disabled 0 Enabled Firewall clock enabled 1 TIM1EN TIM1 timer clock enable 11 1 TIM1EN Disabled TIMx clock disabled 0 Enabled TIMx clock enabled 1 SPI1EN SPI1 clock enable 12 1 SPI1EN Disabled SPI1 clock disabled 0 Enabled SPI1 clock enabled 1 TIM8EN TIM8 timer clock enable 13 1 USART1EN USART1clock enable 14 1 USART1EN Disabled USART1 clock disabled 0 Enabled USART1 clock enabled 1 TIM15EN TIM15 timer clock enable 16 1 TIM16EN TIM16 timer clock enable 17 1 TIM17EN TIM17 timer clock enable 18 1 SAI1EN SAI1 clock enable 21 1 SAI1EN Disabled SAIx clock disabled 0 Enabled SAIx clock enabled 1 SAI2EN SAI2 clock enable 22 1 DFSDM1EN DFSDM timer clock enable 24 1 DFSDM1EN Disabled DFSDM1 clock disabled 0 Enabled DFSDM1 clock enabled 1 LTDCEN LCD-TFT clock enable 26 1 LTDCEN Disabled LTDC clock disabled 0 Enabled LTDC clock enabled 1 DSIEN DSI clock enable 27 1 DSIEN Disabled DSI clock disabled 0 Enabled DSI clock enabled 1 AHB1SMENR AHB1SMENR AHB1 peripheral clocks enable in Sleep and Stop modes register 0x68 0x20 read-write 0x00071307 DMA1SMEN DMA1 clocks enable during Sleep and Stop modes 0 1 DMA1SMEN Disabled DMAx clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled DMAx clocks enabled by the clock gating(1) during Sleep and Stop modes 1 DMA2SMEN DMA2 clocks enable during Sleep and Stop modes 1 1 DMAMUX1SMEN DMAMUX clock enable during Sleep and Stop modes 2 1 DMAMUX1SMEN Disabled DMAMUX1 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled DMAMUX1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 FLASHSMEN Flash memory interface clocks enable during Sleep and Stop modes 8 1 FLASHSMEN Disabled Flash memory interface clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Flash memory interface clocks enabled by the clock gating(1) during Sleep and Stop modes 1 SRAM1SMEN SRAM1 interface clocks enable during Sleep and Stop modes 9 1 SRAM1SMEN Disabled SRAM1 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled SRAM1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 CRCSMEN CRCSMEN 12 1 CRCSMEN Disabled CRC clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled CRC clocks enabled by the clock gating(1) during Sleep and Stop modes 1 TSCSMEN Touch Sensing Controller clocks enable during Sleep and Stop modes 16 1 TSCSMEN Disabled TSC clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled TSC clocks enabled by the clock gating(1) during Sleep and Stop modes 1 DMA2DSMEN DMA2D clock enable during Sleep and Stop modes 17 1 DMA2DSMEN Disabled DMA2D clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled DMA2D clocks enabled by the clock gating(1) during Sleep and Stop modes 1 GFXMMUSMEN GFXMMU clock enable during Sleep and Stop modes 18 1 GFXMMUSMEN Disabled GFXMMU clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled GFXMMU clocks enabled by the clock gating(1) during Sleep and Stop modes 1 AHB2SMENR AHB2SMENR AHB2 peripheral clocks enable in Sleep and Stop modes register 0x6C 0x20 read-write 0x005777FF GPIOASMEN IO port A clocks enable during Sleep and Stop modes 0 1 GPIOASMEN Disabled IO port x clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled IO port x clocks enabled by the clock gating(1) during Sleep and Stop modes 1 GPIOBSMEN IO port B clocks enable during Sleep and Stop modes 1 1 GPIOCSMEN IO port C clocks enable during Sleep and Stop modes 2 1 GPIODSMEN IO port D clocks enable during Sleep and Stop modes 3 1 GPIOESMEN IO port E clocks enable during Sleep and Stop modes 4 1 GPIOFSMEN IO port F clocks enable during Sleep and Stop modes 5 1 GPIOGSMEN IO port G clocks enable during Sleep and Stop modes 6 1 GPIOHSMEN IO port H clocks enable during Sleep and Stop modes 7 1 GPIOISMEN IO port I clocks enable during Sleep and Stop modes 8 1 SRAM2SMEN SRAM2 interface clocks enable during Sleep and Stop modes 9 1 SRAM2SMEN Disabled SRAMx clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled SRAMx clocks enabled by the clock gating(1) during Sleep and Stop modes 1 SRAM3SMEN SRAM2 interface clocks enable during Sleep and Stop modes 10 1 OTGFSSMEN OTG full speed clocks enable during Sleep and Stop modes 12 1 OTGFSSMEN Disabled USB OTG full speed clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled USB OTG full speed clocks enabled by the clock gating(1) during Sleep and Stop modes 1 ADCSMEN ADC clocks enable during Sleep and Stop modes 13 1 ADCSMEN Disabled ADC clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled ADC clocks enabled by the clock gating(1) during Sleep and Stop modes 1 DCMISMEN DCMI clock enable during Sleep and Stop modes 14 1 DCMISMEN Disabled DCMI/PSSI clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled DCMI/PSSI clocks enabled by the clock gating(1) during Sleep and Stop modes 1 AESSMEN AES accelerator clocks enable during Sleep and Stop modes 16 1 AESSMEN Disabled AES clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled AES clocks enabled by the clock gating(1) during Sleep and Stop modes 1 HASHSMEN HASH clock enable during Sleep and Stop modes 17 1 HASHSMEN Disabled HASH clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled HASH clocks enabled by the clock gating(1) during Sleep and Stop modes 1 RNGSMEN Random Number Generator clocks enable during Sleep and Stop modes 18 1 RNGSMEN Disabled Random Number Generator clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Random Number Generator clocks enabled by the clock gating(1) during Sleep and Stop modes 1 OSPIMSMEN OctoSPI IO manager clocks enable during Sleep and Stop modes 20 1 OSPIMSMEN Disabled OCTOSPIM clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled OCTOSPIM clocks enabled by the clock gating(1) during Sleep and Stop modes 1 SDMMC1SMEN SDMMC1 clocks enable during Sleep and Stop modes 22 1 SDMMC1SMEN Disabled SDMMCx clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled SDMMCx clocks enabled by the clock gating(1) during Sleep and Stop modes 1 SDMMC2SMEN SDMMC2 clocks enable during Sleep and Stop modes 23 1 PKASMEN PKA clocks enable during Sleep and Stop modes 15 1 PKASMEN Disabled PKA clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled PKA clocks enabled by the clock gating(1) during Sleep and Stop modes 1 AHB3SMENR AHB3SMENR AHB3 peripheral clocks enable in Sleep and Stop modes register 0x70 0x20 read-write 0x00000301 FMCSMEN Flexible memory controller clocks enable during Sleep and Stop modes 0 1 FMCSMEN Disabled FMC clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled FMC clocks enabled by the clock gating(1) during Sleep and Stop modes 1 OCTOSPI2 OctoSPI2 memory interface clocks enable during Sleep and Stop modes 9 1 OCTOSPI2 Disabled OctoSPI2 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled OctoSPI2 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 OSPI1SMEN OctoSPI1 memory interface clocks enable during Sleep and Stop modes 8 1 OSPI1SMEN Disabled OctoSPI1 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled OctoSPI1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 APB1SMENR1 APB1SMENR1 APB1SMENR1 0x78 0x20 read-write 0xF3FECC3F TIM2SMEN TIM2 timer clocks enable during Sleep and Stop modes 0 1 TIM2SMEN Disabled TIMx clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled TIMx clocks enabled by the clock gating(1) during Sleep and Stop modes 1 TIM3SMEN TIM3 timer clocks enable during Sleep and Stop modes 1 1 TIM4SMEN TIM4 timer clocks enable during Sleep and Stop modes 2 1 TIM5SMEN TIM5 timer clocks enable during Sleep and Stop modes 3 1 TIM6SMEN TIM6 timer clocks enable during Sleep and Stop modes 4 1 TIM7SMEN TIM7 timer clocks enable during Sleep and Stop modes 5 1 RTCAPBSMEN RTC APB clock enable during Sleep and Stop modes 10 1 RTCAPBSMEN Disabled RTC APB clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled RTC APB clocks enabled by the clock gating(1) during Sleep and Stop modes 1 WWDGSMEN Window watchdog clocks enable during Sleep and Stop modes 11 1 WWDGSMEN Disabled Window watchdog clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Window watchdog clocks enabled by the clock gating(1) during Sleep and Stop modes 1 SPI2SMEN SPI2 clocks enable during Sleep and Stop modes 14 1 SPI2SMEN Disabled SPIx clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled SPIx clocks enabled by the clock gating(1) during Sleep and Stop modes 1 SP3SMEN SPI3 clocks enable during Sleep and Stop modes 15 1 USART2SMEN USART2 clocks enable during Sleep and Stop modes 17 1 USART2SMEN Disabled USARTx clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled USARTx clocks enabled by the clock gating(1) during Sleep and Stop modes 1 USART3SMEN USART3 clocks enable during Sleep and Stop modes 18 1 UART4SMEN UART4 clocks enable during Sleep and Stop modes 19 1 UART4SMEN Disabled UARTx clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled UARTx clocks enabled by the clock gating(1) during Sleep and Stop modes 1 UART5SMEN UART5 clocks enable during Sleep and Stop modes 20 1 I2C1SMEN I2C1 clocks enable during Sleep and Stop modes 21 1 I2C1SMEN Disabled I2Cx clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled I2Cx clocks enabled by the clock gating(1) during Sleep and Stop modes 1 I2C2SMEN I2C2 clocks enable during Sleep and Stop modes 22 1 I2C3SMEN I2C3 clocks enable during Sleep and Stop modes 23 1 CRSSMEN CRS clock enable during Sleep and Stop modes 24 1 CRSSMEN Disabled CRS clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled CRS clocks enabled by the clock gating(1) during Sleep and Stop modes 1 CAN1SMEN CAN1 clocks enable during Sleep and Stop modes 25 1 CAN1SMEN Disabled CAN1 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled CAN1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 PWRSMEN Power interface clocks enable during Sleep and Stop modes 28 1 PWRSMEN Disabled Power interface clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled Power interface clocks enabled by the clock gating(1) during Sleep and Stop modes 1 DAC1SMEN DAC1 interface clocks enable during Sleep and Stop modes 29 1 DAC1SMEN Disabled DAC1 interface clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled DAC1 interface clocks enabled by the clock gating(1) during Sleep and Stop modes 1 OPAMPSMEN OPAMP interface clocks enable during Sleep and Stop modes 30 1 OPAMPSMEN Disabled OPAMP interface clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled OPAMP interface clocks enabled by the clock gating(1) during Sleep and Stop modes 1 LPTIM1SMEN Low power timer 1 clocks enable during Sleep and Stop modes 31 1 LPTIM1SMEN Disabled LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled LPTIM1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 APB1SMENR2 APB1SMENR2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x7C 0x20 read-write 0x00000023 LPUART1SMEN Low power UART 1 clocks enable during Sleep and Stop modes 0 1 LPUART1SMEN Disabled LPUART1 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled LPUART1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 I2C4SMEN I2C4 clocks enable during Sleep and Stop modes 1 1 I2C4SMEN Disabled I2C4 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled I2C4 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 LPTIM2SMEN LPTIM2SMEN 5 1 LPTIM2SMEN Disabled LPTIM2 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled LPTIM2 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 APB2SMENR APB2SMENR APB2SMENR 0x80 0x20 read-write 0x0D677801 SYSCFGSMEN SYSCFG clocks enable during Sleep and Stop modes 0 1 SYSCFGSMEN Disabled SYSCFG + COMP + VREFBUF clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled SYSCFG + COMP + VREFBUF clocks enabled by the clock gating(1) during Sleep and Stop modes 1 TIM1SMEN TIM1 timer clocks enable during Sleep and Stop modes 11 1 TIM1SMEN Disabled TIMx clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled TIMx clocks enabled by the clock gating(1) during Sleep and Stop modes 1 SPI1SMEN SPI1 clocks enable during Sleep and Stop modes 12 1 SPI1SMEN Disabled SPI1 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled SPI1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 TIM8SMEN TIM8 timer clocks enable during Sleep and Stop modes 13 1 USART1SMEN USART1clocks enable during Sleep and Stop modes 14 1 USART1SMEN Disabled USART1 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled USART1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 TIM15SMEN TIM15 timer clocks enable during Sleep and Stop modes 16 1 TIM16SMEN TIM16 timer clocks enable during Sleep and Stop modes 17 1 TIM17SMEN TIM17 timer clocks enable during Sleep and Stop modes 18 1 SAI1SMEN SAI1 clocks enable during Sleep and Stop modes 21 1 SAI1SMEN Disabled SAIx clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled SAIx clocks enabled by the clock gating(1) during Sleep and Stop modes 1 SAI2SMEN SAI2 clocks enable during Sleep and Stop modes 22 1 DFSDM1SMEN DFSDM timer clocks enable during Sleep and Stop modes 24 1 DFSDM1SMEN Disabled DFSDM1 clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled DFSDM1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1 LTDCSMEN LCD-TFT timer clocks enable during Sleep and Stop modes 26 1 LTDCSMEN Disabled LCD-TFT clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled LCD-TFT clocks enabled by the clock gating(1) during Sleep and Stop modes 1 DSISMEN DSI clocks enable during Sleep and Stop modes 27 1 DSISMEN Disabled DSI clocks disabled by the clock gating during Sleep and Stop modes 0 Enabled DSI clocks enabled by the clock gating(1) during Sleep and Stop modes 1 CCIPR CCIPR CCIPR 0x88 0x20 read-write 0x00000000 ADCSEL ADCs clock source selection 28 2 ADCSEL NoClock No clock selected 0 PLLADC1CLK PLLADC1CLK clock selected 1 SYSCLK SYSCLK clock selected 3 CLK48SEL 48 MHz clock source selection 26 2 CLK48SEL HSI48 HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected) 0 PLL48M2CLK PLL48M2CLK clock selected 1 PLL48M1CLK PLL48M1CLK clock selected 2 MSI MSI clock selected 3 SAI2SEL SAI2 clock source selection 24 2 SAI1SEL SAI1 clock source selection 22 2 LPTIM1SEL Low power timer 1 clock source selection 18 2 LPTIM1SEL PCLK PCLK clock selected 0 LSI LSI clock selected 1 HSI16 HSI16 clock selected 2 LSE LSE clock selected 3 LPTIM2SEL Low power timer 2 clock source selection 20 2 I2C1SEL I2C1 clock source selection 12 2 I2C1SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 I2C3SEL I2C3 clock source selection 16 2 I2C2SEL I2C2 clock source selection 14 2 LPUART1SEL LPUART1 clock source selection 10 2 LPUART1SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 LSE LSE clock selected 3 UART4SEL UART4 clock source selection 6 2 UART4SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 LSE LSE clock selected 3 UART5SEL UART5 clock source selection 8 2 USART1SEL USART1 clock source selection 0 2 USART1SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 LSE LSE clock selected 3 USART3SEL USART3 clock source selection 4 2 USART2SEL USART2 clock source selection 2 2 BDCR BDCR BDCR 0x90 0x20 0x00000000 LSCOSEL Low speed clock output selection 25 1 read-write LSCOSEL LSI LSI clock selected 0 LSE LSE clock selected 1 LSCOEN Low speed clock output enable 24 1 read-write LSCOEN Disabled Low speed clock output (LSCO) disabled 0 Enabled Low speed clock output (LSCO) enabled 1 BDRST Backup domain software reset 16 1 read-write BDRST NoReset Reset not activated 0 Reset Reset the entire Backup domain 1 RTCEN RTC clock enable 15 1 read-write RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 RTCSEL RTC clock source selection 8 2 read-write RTCSEL NoClock No clock 0 LSE LSE oscillator clock selected 1 LSI LSI oscillator clock selected 2 HSE HSE oscillator clock divided by 32 selected 3 LSECSSD LSECSSD 6 1 read-only LSECSSD NoFailure No failure detected on LSE (32 kHz oscillator) 0 FailureDetected Failure detected on LSE (32 kHz oscillator) 1 LSECSSON LSECSSON 5 1 read-write LSECSSON Disabled CSS on LSE (32 kHz external oscillator) OFF 0 Enabled CSS on LSE (32 kHz external oscillator) ON 1 LSEDRV SE oscillator drive capability 3 2 read-write LSEDRV Low âXtal modeâ lower driving capability 0 MediumLow âXtal modeâ medium low driving capability 1 MediumHigh âXtal modeâ medium high driving capability 2 High âXtal modeâ higher driving capability 3 LSEBYP LSE oscillator bypass 2 1 read-write LSEBYP NotBypassed LSE oscillator not bypassed 0 Bypassed LSE oscillator bypassed 1 LSERDY LSE oscillator ready 1 1 read-only LSERDY NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEON LSE oscillator enable 0 1 read-write LSEON Disabled LSE oscillator OFF 0 Enabled LSE oscillator ON 1 LSESYSDIS Disable the Clock LSE propagation to the system 7 1 LSESYSDIS Disabled No clock LSE propagation 0 Enabled Clock LSE propagation enabled 1 CSR CSR CSR 0x94 0x20 0x0C000600 LPWRRSTF Low-power reset flag 31 1 read-only LPWRRSTF NotOccured No illegal mode reset occurred 0 Occured Illegal mode reset occurred 1 WWDGRSTF Window watchdog reset flag 30 1 read-only WWDGRSTF NotOccured No window watchdog reset occurred 0 Occured Window watchdog reset occurred 1 IWDGRSTF Independent window watchdog reset flag 29 1 read-only IWDGRSTF NotOccured No independent watchdog reset occurred 0 Occured Independent watchdog reset occurred 1 SFTRSTF Software reset flag 28 1 read-only SFTRSTF NotOccured No software reset occurred 0 Occured Software reset occurred 1 BORRSTF BOR flag 27 1 read-only BORRSTF NotOccured No BOR occurred 0 Occured BOR occurred 1 PINRSTF Pin reset flag 26 1 read-only PINRSTF NotOccured No reset from NRST pin occurred 0 Occured Reset from NRST pin occurred 1 OBLRSTF Option byte loader reset flag 25 1 read-only OBLRSTF NotOccured No reset from Option Byte loading occurred 0 Occured Reset from Option Byte loading occurred 1 FWRSTF Firewall reset flag 24 1 read-only FWRSTF NotOccured No reset from the firewall occurred 0 Occured Reset from the firewall occurred 1 RMVF Remove reset flag 23 1 read-write RMVF NoEffect No effect 0 Clear Clear the reset flags 1 MSISRANGE SI range after Standby mode 8 4 read-write MSISRANGE Range1M range 4 around 1 MHz 4 Range2M range 5 around 2 MHz 5 Range4M range 6 around 4 MHz 6 Range8M range 7 around 8 MHz 7 LSIRDY LSI oscillator ready 1 1 read-only LSIRDY NotReady LSI oscillator not ready 0 Ready LSI oscillator ready 1 LSION LSI oscillator enable 0 1 read-write LSION Disabled LSI oscillator OFF 0 Enabled LSI oscillator ON 1 LSIPREDIV Internal low-speed oscillator predivided by 128 4 1 LSIPREDIV Disabled LSI PREDIV OFF 0 Enabled LSI PREDIV ON 1 CRRCR CRRCR Clock recovery RC register 0x98 0x20 0x00000000 HSI48ON HSI48 clock enable 0 1 read-write HSI48ON Disabled HSI48 oscillator OFF 0 Enabled HSI48 oscillator ON 1 HSI48RDY HSI48 clock ready flag 1 1 read-only HSI48RDY NotReady HSI48 oscillator not ready 0 Ready HSI48 oscillator ready 1 HSI48CAL HSI48 clock calibration 7 9 read-only 0 511 CCIPR2 CCIPR2 Peripherals independent clock configuration register 0x9C 0x20 read-write 0x00000000 I2C4SEL I2C4 clock source selection 0 2 I2C4SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 DFSDMSEL Digital filter for sigma delta modulator kernel clock source selection 2 1 DFSDMSEL PCLK2 APB2 clock (PCLK2) selected as DFSDM kernel clock 0 SYSCLK System clock selected as DFSDM kernel clock 1 ADFSDMSEL Digital filter for sigma delta modulator audio clock source selection 3 2 ADFSDMSEL SAI1 SAI1clock selected as DFSDM audio clock 0 HSI HSI clock selected as DFSDM audio clock 1 MSI MSI clock selected as DFSDM audio clock 2 SAI1SEL SAI1 clock source selection 5 3 SAI1SEL PLLSAI1CLK PLLSAI1CLK clock is selected as SAIx clock 0 PLLSAI2CLK PLLSAI2CLK clock is selected as SAIx clock 1 PLLSAI3CLK PLLSAI3CLK clock is selected as SAIx clock 2 SAI2_EXTCLK External clock SAIx_EXTCLK clock selected as SAIx clock 3 HSI HSI clock selected as SAIx clock 4 SAI2SEL SAI2 clock source selection 8 3 DSISEL clock selection 12 1 DSISEL DSIPHY DSI-PHY is selected as DSI byte lane clock source (usual case) 0 PLLDSICLK PLLDSICLK is selected as DSI byte lane clock source, used in case DSI PLL and DSIPHY are off (low-power mode) 1 SDMMCSEL SDMMC clock selection 14 1 SDMMCSEL HSI48 48 MHz clock is selected as SDMMC kernel clock 0 PLLSAI3CLK PLLSAI3CLK is selected as SDMMC kernel clock, used in case higher frequency than 48MHz is needed (for SDR50 mode) 1 PLLSAI2DIVR division factor for LTDC clock 16 2 PLLSAI2DIVR Div2 PLLSAI2DIVR = /2 0 Div4 PLLSAI2DIVR = /4 1 Div8 PLLSAI2DIVR = /8 2 Div16 PLLSAI2DIVR = /16 3 OSPISEL Octospi clock source selection 20 2 OSPISEL SYSCLK System clock selected as OctoSPI kernel clock 0 MSI MSI clock selected as OctoSPI kernel clock 1 PLL48M1CLK PLL48M1CLK clock selected as OctoSPI kernel clock 2 DLYCFGR delay configuration register 0xA4 0x00000000 OCTOSPI2_DLY Delay sampling configuration on OCTOSPI2 to be used for internal sampling clock (called feedback clock) or for DQS data strobe 4 4 0 15 OCTOSPI1_DLY Delay sampling configuration on OCTOSPI1 to be used for internal sampling clock (called feedback clock) or for DQS data strobe 0 4 0 15 PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x20 0x00000200 0xFFFFFFFF LPMS Low-power mode selection These bits select the low-power mode entered when CPU enters the Deepsleep mode. 1xx: Shutdown mode Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. 0 3 read-write LPMS Stop0 Stop 0 mode 0 Stop1 Stop 1 mode 1 Stop2 Stop 2 mode 2 Standby Standby mode 3 Shutdown Shutdown mode 4 RRSTP SRAM3 retention in Stop 2 mode 4 1 read-write RRSTP Disabled SRAM3 is powered off in Stop 2 mode (SRAM3 content is lost) 0 Enabled SRAM3 is powered in Stop 2 mode (RAM3 content is kept) 1 DBP Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 8 1 read-write DBP Disabled Access to RTC and Backup registers disabled 0 Enabled Access to RTC and Backup registers enabled 1 VOS Voltage scaling range selection 9 2 read-write VOS Range1 Range 1 1 Range2 Range 1 2 LPR Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. 14 1 read-write LPR MainMode Main Mode 0 LowPowerMode Low Power Mode 1 CR2 CR2 Power control register 2 0x4 0x20 0x00000000 0xFFFFFFFF PVDE Power voltage detector enable Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: This bit is reset only by a system reset. 0 1 read-write PVDE Disabled Power voltage detector disabled 0 Enabled Power voltage detector enabled 1 PLS Power voltage detector level selection. These bits select the voltage threshold detected by the power voltage detector: Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: These bits are reset only by a system reset. 1 3 read-write PLS VPVD0 VPVD0 around 2.0 V 0 VPVD1 VPVD1 around 2.2 V 1 VPVD2 VPVD2 around 2.4 V 2 VPVD3 VPVD3 around 2.5 V 3 VPVD4 VPVD4 around 2.6 V 4 VPVD5 VPVD5 around 2.8 V 5 VPVD6 VPVD6 around 2.9 V 6 PVDIN External input analog voltage PVD_IN (compared internally to VREFINT) 7 PVME1 Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V 4 1 read-write PVME1 Disabled PVM2 (VDDUSB monitoring vs. 1.2V threshold) disable 0 Enabled PVM2 (VDDUSB monitoring vs. 1.2V threshold) enable 1 PVME2 Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V 5 1 read-write PVME2 Disabled PVM2 (VDDIO2 monitoring vs. 0.9V threshold) disable 0 Enabled PVM2 (VDDIO2 monitoring vs. 0.9V threshold) enable 1 PVME3 Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V 6 1 read-write PVME3 Disabled PVM3 (VDDA monitoring vs. 1.62V threshold) disable 0 Enabled PVM3 (VDDA monitoring vs. 1.62V threshold) enable 1 PVME4 Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V 7 1 read-write PVME4 Disabled PVM4 (VDDA monitoring vs. 2.2V threshold) disable 0 Enabled PVM4 (VDDA monitoring vs. 2.2V threshold) enable 1 IOSV VDDIO2 Independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the PVM can be used to determine whether this supply is ready or not. 9 1 read-write IOSV NotPresent VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply 0 Valid VDDIO2 is valid 1 USV VDDUSB USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB OTG_FS peripheral. If VDDUSB is not always present in the application, the PVM can be used to determine whether this supply is ready or not. 10 1 read-write USV NotPresent VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply 0 Valid VDDUSB is valid 1 CR3 CR3 Power control register 3 0x8 0x20 0x00008000 0xFFFFFFFF EWUP1 Enable Wakeup pin WKUP1 When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. 0 1 read-write EWUP1 Disabled External Wakeup pin WKUPx is disabled 0 Enabled When this bit is set, the external wakeup pin WKUPx is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WPx bit in the PWR_CR4 register 1 EWUP2 Enable Wakeup pin WKUP2 When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. 1 1 read-write EWUP3 Enable Wakeup pin WKUP3 When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. 2 1 read-write EWUP4 Enable Wakeup pin WKUP4 When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. 3 1 read-write EWUP5 Enable Wakeup pin WKUP5 When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. 4 1 read-write RRS SRAM2 retention in Standby mode For STM32L4Rxxx and STM32L4Sxxx devices bit 9 is reserved For STM32L4P5xx and STM32L4Q5xx devices: 8 2 read-write RRS PoweredOff SRAM2 is powered off in Standby mode (SRAM2 content is lost) 0 PoweredOn Full SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 full content is kept) 1 PartialPoweredOn Only 4 Kbytes of SRAM2 is powered by the low-power regulator in Standby mode (4 Kbytes of SRAM2 content is kept) 2 APC Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os will be in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during Run mode. 10 1 read-write APC Disabled Configurations are not applied 0 Enabled When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os will be in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during Run mode 1 ENULP Enable ULP sampling When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes. Note: Available on STM32L4P5xx andSTM32L4Q5xx only. 11 1 read-write ENULP Disabled Sampling disabled 0 Enabled When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes 1 DSIPDEN Enable Pull-down activation on DSI pins 12 1 read-write DSIPDEN Disabled Pull-Down is disabled on DSI pins 0 Enabled Pull-Down is enabled on DSI pins 1 EIWUL Enable internal wakeup line 15 1 read-write EIWUL Disabled Internal wakeup line disable 0 Enabled Internal wakeup line enable 1 CR4 CR4 Power control register 4 0xC 0x20 0x00000000 0xFFFFFFFF WP1 Wakeup pin WKUP1 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 0 1 read-write WP1 RisingEdge Detection on high level (rising edge) 0 FallingEdge Detection on low level (falling edge) 1 WP2 Wakeup pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 1 1 read-write WP3 Wakeup pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 2 1 read-write WP4 Wakeup pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 3 1 read-write WP5 Wakeup pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 4 1 read-write VBE VBAT battery charging enable 8 1 read-write VBE Disabled VBAT battery charging disable 0 Enabled VBAT battery charging enable 1 VBRS VBAT battery charging resistor selection 9 1 read-write VBRS R5k Charge VBAT through a 5 kOhms resistor 0 R1k5 Charge VBAT through a 1.5 kOhms resistor 1 EXT_SMPS_ON external SMPS on. This bit informs the internal regulator about external SMPS switch status to decrease regulator output to 0.95 V in Range 2, allowing the external SMPS output down to 1.00 V. Note: This bit is only available on STM32L4P5xx and STM32L4Q5xx devices. 13 1 read-write EXT_SMPS_ON Disabled The external SMPS switch is open 0 Enabled The external SMPS switch is closed, internal regulator output is set to 0.95 V 1 SR1 SR1 Power status register 1 0x10 0x20 0x00000000 0xFFFFFFFF WUF1 Wakeup flag 1 This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register. 0 1 read-only WUF1 Set This bit is set when a wakeup event is detected on wakeup pin, WKUPx 0 Cleared No wakeup event detected on WKUPx 1 WUF2 Wakeup flag 2 This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register. 1 1 read-only WUF3 Wakeup flag 3 This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register. 2 1 read-only WUF4 Wakeup flag 4 This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register. 3 1 read-only WUF5 Wakeup flag 5 This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register. 4 1 read-only SBF Standby flag This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. 8 1 read-only SBF Set The device did not enter the Standby mode 0 Cleared The device entered the Standby mode 1 EXT_SMPS_RDY External SMPS ready This bit informs the state of regulator transition from Range 1 to Range 2 Note: This bit is only available on STM32L4P5xx and STM32L4Q5xx devices. 13 1 read-only EXT_SMPS_RDY NotReady Internal regulator not ready in Range 2, the external SMPS cannot be connected 0 Ready Internal regulator ready in Range 2, the external SMPS can be connected 1 WUFI Wakeup flag internal This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. 15 1 read-only WUFI Set This bit is set when a wakeup is detected on the internal wakeup line 0 Cleared It is cleared when all internal wakeup sources are cleared 1 SR2 SR2 Power status register 2 0x14 0x20 0x00000000 0xFFFFFFFF REGLPS Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased. 8 1 read-only REGLPS NotReady The low-power regulator is not ready 0 Ready The low-power regulator is ready 1 REGLPF Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready. 9 1 read-only REGLPF MR The regulator is ready in main mode (MR) 0 LPR The regulator is in low-power mode (LPR) 1 VOSF Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. 10 1 read-only VOSF Ready The regulator is ready in the selected voltage range 0 NotReady The regulator output voltage is changing to the required voltage level 1 PVDO Power voltage detector output 11 1 read-only PVDO Above VDD is above the selected PVD threshold 0 Below VDD is below the selected PVD threshold 1 PVMO1 Peripheral voltage monitoring output: VDDUSB vs. 1.2 V Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wakeup time. 12 1 read-only PVMO1 Above VDDUSB voltage is above PVM1 threshold (around 1.2 V) 0 Below VDDUSB voltage is below PVM1 threshold (around 1.2 V) 1 PVMO2 Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V Note: PVMO2 is cleared when PVM2 is disabled (PVME2 = 0). After enabling PVM2, the PVM2 output is valid after the PVM2 wakeup time. 13 1 read-only PVMO2 Above VDDIO2 voltage is above PVM2 threshold (around 0.9 V) 0 Below VDDIO2 voltage is below PVM2 threshold (around 0.9 V) 1 PVMO3 Peripheral voltage monitoring output: VDDA vs. 1.62 V Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wakeup time. 14 1 read-only PVMO3 Above VDDA voltage is above PVM3 threshold (around 1.62 V) 0 Below VDDA voltage is below PVM3 threshold (around 1.62 V) 1 PVMO4 Peripheral voltage monitoring output: VDDA vs. 2.2 V Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wakeup time. 15 1 read-only PVMO4 Above VDDA voltage is above PVM4 threshold (around 2.2 V) 0 Below VDDA voltage is below PVM4 threshold (around 2.2 V) 1 SCR SCR Power status clear register 0x18 0x20 0x00000000 0xFFFFFFFF CWUF1 Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register. 0 1 write-only CWUF1 Clear Setting this bit clears the WUFx flag in the PWR_SR1 register 1 CWUF2 Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register. 1 1 write-only CWUF3 Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register. 2 1 write-only CWUF4 Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register. 3 1 write-only CWUF5 Clear wakeup flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register. 4 1 write-only CSBF Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. 8 1 write-only CSBF Clear Setting this bit clears the SBF flag in the PWR_SR1 register 1 PUCRA PUCRA Power Port A pull-up control register 0x20 0x20 0x00000000 0xFFFFFFFF PU0 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU0 Disabled Pull-Up on Pxx is disabled 0 Enabled Pull-Up on Pxx is enabled 1 PU1 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU15 Port A pull-up bit 15 When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. If the corresponding PD15 bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. 15 1 read-write PDCRA PDCRA Power Port A pull-down control register 0x24 0x20 0x00000000 0xFFFFFFFF PD0 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD0 Disabled Pull-Down on Pxx is disabled 0 Enabled Pull-Down on Pxx is enabled 1 PD1 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD14 Port A pull-down bit 14 When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register. 14 1 read-write PUCRB PUCRB Power Port B pull-up control register 0x28 0x20 0x00000000 0xFFFFFFFF PU0 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU0 Disabled Pull-Up on Pxx is disabled 0 Enabled Pull-Up on Pxx is enabled 1 PU1 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRB PDCRB Power Port B pull-down control register 0x2C 0x20 0x00000000 0xFFFFFFFF PD0 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD0 Disabled Pull-Down on Pxx is disabled 0 Enabled Pull-Down on Pxx is enabled 1 PD1 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD5 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRC PUCRC Power Port C pull-up control register 0x30 0x20 0x00000000 0xFFFFFFFF PU0 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU0 Disabled Pull-Up on Pxx is disabled 0 Enabled Pull-Up on Pxx is enabled 1 PU1 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRC PDCRC Power Port C pull-down control register 0x34 0x20 0x00000000 0xFFFFFFFF PD0 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD0 Disabled Pull-Down on Pxx is disabled 0 Enabled Pull-Down on Pxx is enabled 1 PD1 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRD PUCRD Power Port D pull-up control register 0x38 0x20 0x00000000 0xFFFFFFFF PU0 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU0 Disabled Pull-Up on Pxx is disabled 0 Enabled Pull-Up on Pxx is enabled 1 PU1 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRD PDCRD Power Port D pull-down control register 0x3C 0x20 0x00000000 0xFFFFFFFF PD0 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD0 Disabled Pull-Down on Pxx is disabled 0 Enabled Pull-Down on Pxx is enabled 1 PD1 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PDCRE PDCRE Power Port E pull-down control register 0x44 0x20 0x00000000 0xFFFFFFFF PD0 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD0 Disabled Pull-Down on Pxx is disabled 0 Enabled Pull-Down on Pxx is enabled 1 PD1 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRF PUCRF Power Port F pull-up control register 0x48 0x20 0x00000000 0xFFFFFFFF PU0 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU0 Disabled Pull-Up on Pxx is disabled 0 Enabled Pull-Up on Pxx is enabled 1 PU1 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRF PDCRF Power Port F pull-down control register 0x4C 0x20 0x00000000 0xFFFFFFFF PD0 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD0 Disabled Pull-Down on Pxx is disabled 0 Enabled Pull-Down on Pxx is enabled 1 PD1 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRG PUCRG Power Port G pull-up control register 0x50 0x20 0x00000000 0xFFFFFFFF PU0 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU0 Disabled Pull-Up on Pxx is disabled 0 Enabled Pull-Up on Pxx is enabled 1 PU1 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRG PDCRG Power Port G pull-down control register 0x54 0x20 0x00000000 0xFFFFFFFF PD0 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD0 Disabled Pull-Down on Pxx is disabled 0 Enabled Pull-Down on Pxx is enabled 1 PD1 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRH PUCRH Power Port H pull-up control register 0x58 0x20 0x00000000 0xFFFFFFFF PU0 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU0 Disabled Pull-Up on Pxx is disabled 0 Enabled Pull-Up on Pxx is enabled 1 PU1 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRH PDCRH Power Port H pull-down control register 0x5C 0x20 0x00000000 0xFFFFFFFF PD0 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD0 Disabled Pull-Down on Pxx is disabled 0 Enabled Pull-Down on Pxx is enabled 1 PD1 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRI PUCRI Power Port I pull-up control register 0x60 0x20 0x00000000 0xFFFFFFFF PU0 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU0 Disabled Pull-Up on Pxx is disabled 0 Enabled Pull-Up on Pxx is enabled 1 PU1 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PDCRI PDCRI Power Port I pull-down control register 0x64 0x20 0x00000000 0xFFFFFFFF PD0 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD0 Disabled Pull-Down on Pxx is disabled 0 Enabled Pull-Down on Pxx is enabled 1 PD1 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register. 11 1 read-write CR5 CR5 PWR control register 0x80 0x20 0x00000100 0xFFFFFFFF R1MODE Main regulator Range 1 mode This bit is only valid for the main regulator in Range 1 and has no effect on Range 2. It is recommended to reset this bit when the system frequency is greater than 80 MHz. Refer to Table 28: Range 1 boost mode configuration. 8 1 read-write R1MODE BoostMode Main regulator in Range 1 boost mode 0 NormalMode Main regulator in Range 1 normal mode 1 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x30 registers MEMRMP MEMRMP memory remap register 0x0 0x20 read-write 0x00000000 FB_MODE Flash Bank mode selection 8 1 FB_MODE Normal Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000(1)) and Flash Bank 2 mapped at offset 0 Inverted Flash Bank 2 mapped at 0x0800 0000 (and aliased @0x0000 0000(1)) and Flash Bank 1 mapped at offset 1 MEM_MODE Memory mapping selection 0 3 MEM_MODE MainFlash Main Flash memory mapped at 0x00000000 0 SystemFlash System Flash memory mapped at 0x00000000 1 FMC FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 2 SRAM1 SRAM1 mapped at 0x00000000 3 OCTOSPI1 OCTOSPI1 memory mapped at 0x00000000 4 OCTOSPI2 OCTOSPI2 memory mapped at 0x00000000 5 CFGR1 CFGR1 configuration register 1 0x4 0x20 read-write 0x7C000001 I2C1_FMP I2C1 Fast-mode Plus driving capability activation 20 1 I2C1_FMP Disabled Fm+ mode is not enabled on I2Cx pins selected through AF selection bits 0 Enabled Fm+ mode is enabled on I2Cx pins selected through AF selection bits 1 I2C3_FMP I2C3 Fast-mode Plus driving capability activation 22 1 I2C2_FMP I2C2 Fast-mode Plus driving capability activation 21 1 I2C_PB6_FMP Fast-mode Plus (Fm+) driving capability activation on PB6 16 1 I2C_PB6_FMP Disabled PBx pin operates in standard mode 0 Enabled Fm+ mode enabled on PB7 pin, and the Speed control is bypassed 1 I2C_PB9_FMP Fast-mode Plus (Fm+) driving capability activation on PB9 19 1 I2C_PB8_FMP Fast-mode Plus (Fm+) driving capability activation on PB8 18 1 I2C_PB7_FMP Fast-mode Plus (Fm+) driving capability activation on PB7 17 1 BOOSTEN I/O analog switch voltage booster enable 8 1 BOOSTEN Disabled I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation 0 Enabled I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation 1 FWDIS Firewall disable 0 1 FWDIS Enabled Firewall protection enabled 0 Disabled Firewall protection disabled 1 FPU_IE0 Invalid operation interrupt enable 26 1 FPU_IE0 Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 FPU_IE5 Inexact interrupt enable 31 1 FPU_IE4 Input denormal interrupt enable 30 1 FPU_IE3 Overflow interrupt enable 29 1 FPU_IE2 Underflow interrupt enable 28 1 FPU_IE1 Divide-by-zero interrupt enable 27 1 ANASWVDD GPIO analog switch control voltage selection when at least one analog peripheral supplied by VDDA is enabled (COMP, OPAMP, VREFBUF, ADC,...) 9 1 ANASWVDD VDDA I/O analog switches supplied by VDDA or booster when booster is ON 0 VDD I/O analog switches supplied by VDD 1 I2C4_FMP I2C3 Fast-mode Plus driving capability activation 23 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x00000000 EXTI3 EXTI 3 configuration bits 12 4 EXTI2 EXTI 2 configuration bits 8 4 EXTI1 EXTI 1 configuration bits 4 4 EXTI0 EXTI 0 configuration bits 0 4 ExtiAbcdefgh PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 PE Select PEx as the source input for the EXTIx external interrupt 4 PF Select PFx as the source input for the EXTIx external interrupt 5 PG Select PGx as the source input for the EXTIx external interrupt 6 PH Select PHx as the source input for the EXTIx external interrupt 7 PI Select PIx as the source input for the EXTIx external interrupt 8 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x00000000 EXTI7 EXTI 7 configuration bits 12 4 EXTI6 EXTI 6 configuration bits 8 4 EXTI5 EXTI 5 configuration bits 4 4 EXTI4 EXTI 4 configuration bits 0 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x00000000 EXTI11 EXTI 11 configuration bits 12 4 EXTI10 EXTI 10 configuration bits 8 4 EXTI9 EXTI 9 configuration bits 4 4 EXTI8 EXTI 8 configuration bits 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x00000000 EXTI15 EXTI15 configuration bits 12 4 EXTI14 EXTI14 configuration bits 8 4 EXTI13 EXTI13 configuration bits 4 4 EXTI12 EXTI12 configuration bits 0 4 ExtiAbcdefgh PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 PE Select PEx as the source input for the EXTIx external interrupt 4 PF Select PFx as the source input for the EXTIx external interrupt 5 PG Select PGx as the source input for the EXTIx external interrupt 6 PH Select PHx as the source input for the EXTIx external interrupt 7 SCSR SCSR SCSR 0x18 0x20 0x00000000 SRAM2BS SRAM2 busy by erase operation 1 1 read-only SRAM2BS NotBusy No SRAM2 erase operation is on going 0 Busy SRAM2 erase operation is on going 1 SRAM2ER SRAM2 Erase 0 1 read-write SRAM2ER Erase Setting this bit starts a hardware SRAM2 erase operation 1 CFGR2 CFGR2 CFGR2 0x1C 0x20 0x00000000 SPF SRAM2 parity error flag 8 1 read-write SPF Cleared No SRAM2 parity error detected 0 Set SRAM2 parity error detected 1 ECCL ECC Lock 3 1 write-only ECCL Disconnected ECC error disconnected from TIM1/8/15/16/17 Break input 0 Connected ECC error connected to TIM1/8/15/16/17 Break input 1 PVDL PVD lock enable bit 2 1 write-only PVDL Disconnected PVD interrupt disconnected from TIM1/8/15/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application 0 Connected PVD interrupt connected to TIM1/8/15/16/17 Break input, PVDE and PLS[2:0] bits are read only 1 SPL SRAM2 parity lock bit 1 1 write-only SPL Disconnected SRAM2 parity error signal disconnected from TIM1/8/15/16/17 Break inputs 0 Connected SRAM2 parity error signal connected to TIM1/8/15/16/17 Break inputs 1 CLL Cortex-M4 LOCKUP (Hardfault) output enable bit 0 1 write-only CLL Disconnected CortexÂ®-M4 LOCKUP output disconnected from TIM1/8/15/16/17 Break inputs 0 Connected CortexÂ®-M4 LOCKUP output connected to TIM1/8/15/16/17 Break inputs 1 SWPR SWPR SWPR 0x20 0x20 write-only 0x00000000 P0WP P0WP 0 1 P0WP Disabled Write protection of SRAM2 page x is disabled 0 Enabled Write protection of SRAM2 page x is enabled 1 P31WP SRAM2 page 31 write protection 31 1 P30WP P30WP 30 1 P29WP P29WP 29 1 P28WP P28WP 28 1 P27WP P27WP 27 1 P26WP P26WP 26 1 P25WP P25WP 25 1 P24WP P24WP 24 1 P23WP P23WP 23 1 P22WP P22WP 22 1 P21WP P21WP 21 1 P20WP P20WP 20 1 P19WP P19WP 19 1 P18WP P18WP 18 1 P17WP P17WP 17 1 P16WP P16WP 16 1 P15WP P15WP 15 1 P14WP P14WP 14 1 P13WP P13WP 13 1 P12WP P12WP 12 1 P11WP P11WP 11 1 P10WP P10WP 10 1 P9WP P9WP 9 1 P8WP P8WP 8 1 P7WP P7WP 7 1 P6WP P6WP 6 1 P5WP P5WP 5 1 P4WP P4WP 4 1 P3WP P3WP 3 1 P2WP P2WP 2 1 P1WP P1WP 1 1 SKR SKR SKR 0x24 0x20 write-only 0x00000000 KEY SRAM2 write protection key for software erase 0 8 KEY Key2 2. Write 0x53 into Key[7:0] 83 Key1 1. Write 0xCA into Key[7:0] 202 SWPR2 write protection register 2 0x28 0x00000000 P32WP SRAM2 page x write protection 0 1 P32WP Disabled Write protection of SRAM2 page x is disabled 0 Enabled Write protection of SRAM2 page x is enabled 1 P63WP SRAM2 page x write protection 31 1 P62WP SRAM2 page x write protection 30 1 P61WP SRAM2 page x write protection 29 1 P60WP SRAM2 page x write protection 28 1 P59WP SRAM2 page x write protection 27 1 P58WP SRAM2 page x write protection 26 1 P57WP SRAM2 page x write protection 25 1 P56WP SRAM2 page x write protection 24 1 P55WP SRAM2 page x write protection 23 1 P54WP SRAM2 page x write protection 22 1 P53WP SRAM2 page x write protection 21 1 P52WP SRAM2 page x write protection 20 1 P51WP SRAM2 page x write protection 19 1 P50WP SRAM2 page x write protection 18 1 P49WP SRAM2 page x write protection 17 1 P48WP SRAM2 page x write protection 16 1 P47WP SRAM2 page x write protection 15 1 P46WP SRAM2 page x write protection 14 1 P45WP SRAM2 page x write protection 13 1 P44WP SRAM2 page x write protection 12 1 P43WP SRAM2 page x write protection 11 1 P42WP SRAM2 page x write protection 10 1 P41WP SRAM2 page x write protection 9 1 P40WP SRAM2 page x write protection 8 1 P39WP SRAM2 page x write protection 7 1 P38WP SRAM2 page x write protection 6 1 P37WP SRAM2 page x write protection 5 1 P36WP SRAM2 page x write protection 4 1 P35WP SRAM2 page x write protection 3 1 P34WP SRAM2 page x write protection 2 1 P33WP SRAM2 page x write protection 1 1 DFSDM1 Digital filter for sigma delta modulators DFSDM 0x40016000 0x0 0x500 registers DFSDM1_FLT3 DFSDM1_FLT3 global interrupt 42 DFSDM1_FLT0 DFSDM1_FLT0 global interrupt 61 DFSDM1_FLT1 DFSDM1_FLT1 global interrupt 62 DFSDM1_FLT2 DFSDM1_FLT2 global interrupt 63 8 0x20 0-7 CH%s DFSDM Channel cluster: contains CH?CFGR1, CH?CFGR2, CH?AWSCDR, CH?WDATR and CH?DATINR registers 0x0 CFGR1 CH0CFGR1 channel configuration y register 0x0 0x20 read-write 0x00000000 DFSDMEN DFSDMEN 31 1 DFSDMEN Disabled DFSDM interface disabled 0 Enabled DFSDM interface enabled 1 CKOUTSRC CKOUTSRC 30 1 CKOUTSRC SYSCLK Source for output clock is from system clock 0 AUDCLK Source for output clock is from audio clock 1 CKOUTDIV CKOUTDIV 16 8 0 255 DATPACK DATPACK 14 2 DATPACK Standard Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y 0 Interleaved : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: âfirst sample in INDAT0[15:0] (assigned to channel y) âsecond sample INDAT1[15:0] (assigned to channel y) 1 Dual Dual: input data in DFSDM_CHyDATINR register are stored as two samples: âfirst sample INDAT0[15:0] (assigned to channel y) âsecond sample INDAT1[15:0] (assigned to channel y+1) 2 DATMPX DATMPX 12 2 DATMPX External Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected 0 ADC Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register 1 Internal Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting 2 CHINSEL CHINSEL 8 1 CHINSEL SameChannel Channel inputs are taken from pins of the same channel y 0 FollowingChannel Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8) 1 CHEN CHEN 7 1 CHEN Disabled Channel y disabled 0 Enabled Channel y enabled 1 CKABEN CKABEN 6 1 CKABEN Disabled Clock absence detector disabled on channel y 0 Enabled Clock absence detector enabled on channel y 1 SCDEN SCDEN 5 1 SCDEN Disabled Input channel y will not be guarded by the short-circuit detector 0 Enabled Input channel y will be continuously guarded by the short-circuit detector 1 SPICKSEL SPICKSEL 2 2 SPICKSEL CKIN Clock coming from external CKINy input - sampling point according SITP[1:0] 0 CKOUT Clock coming from internal CKOUT output - sampling point according SITP[1:0] 1 CKOUTSecondFalling Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Î£â modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge) 2 CKOUTSecondRising Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Î£â modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge) 3 SITP SITP 0 2 SITP SPIRisingEdge SPI with rising edge to strobe data 0 SPIFallingEdge SPI with falling edge to strobe data 1 Manchester Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 2 ManchesterInverted Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 3 CFGR2 CH0CFGR2 channel configuration y register 0x4 0x20 read-write 0x00000000 OFFSET OFFSET 8 24 0 16777215 DTRBS DTRBS 3 5 0 31 AWSCDR CH0AWSCDR analog watchdog and short-circuit detector register 0x8 0x20 read-write 0x00000000 AWFORD AWFORD 22 2 AWFORD FastSinc FastSinc filter type 0 Sinc1 Sinc1 filter type 1 Sinc2 Sinc2 filter type 2 Sinc3 Sinc3 filter type 3 AWFOSR AWFOSR 16 5 0 31 BKSCD BKSCD 12 4 0 15 SCDT SCDT 0 8 0 255 WDATR CH0WDATR channel watchdog filter data register 0xC 0x20 read-write 0x00000000 WDATA WDATA 0 16 0 65535 DATINR CH0DATINR channel data input register 0x10 0x20 read-write 0x00000000 INDAT1 INDAT1 16 16 0 65535 INDAT0 INDAT0 0 16 0 65535 DLYR CH0DLYR channel y delay register 0x14 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 0 63 4 0x80 0-3 FLT%s Cluster FLT%s, containing FLT?CR1, FLT?CR2, FLT?ISR, FLT?ICR, FLT?JCHGR, FLT?FCR, FLT?JDATAR, FLT?RDATAR, FLT?AWHTR, FLT?AWLTR, FLT?AWSR, FLT?AWCFR, FLT?EXMAX, FLT?EXMIN, FLT?CNVTIMR 0x100 CR1 FLT0CR1 control register 1 0x0 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 AWFSEL Output Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 0 Transceiver Analog watchdog on channel transceivers value (after watchdog filter) 1 FAST Fast conversion mode selection for regular conversions 29 1 FAST Disabled Fast conversion mode disabled 0 Enabled Fast conversion mode enabled 1 RCH Regular channel selection 24 3 RCH Channel0 Channel 0 is selected as regular channel 0 Channel1 Channel 1 is selected as regular channel 1 Channel2 Channel 2 is selected as regular channel 2 Channel3 Channel 3 is selected as regular channel 3 Channel4 Channel 4 is selected as regular channel 4 Channel5 Channel 5 is selected as regular channel 5 Channel6 Channel 6 is selected as regular channel 6 Channel7 Channel 7 is selected as regular channel 7 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RDMAEN Disabled The DMA channel is not enabled to read regular data 0 Enabled The DMA channel is enabled to read regular data 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RSYNC NoLaunch Do not launch a regular conversion synchronously with DFSDM_FLT0 0 Launch Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 1 RCONT Continuous mode selection for regular conversions 18 1 RCONT Once The regular channel is converted just once for each conversion request 0 Continuous The regular channel is converted repeatedly after each conversion request 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSWSTARTW write Start Writing â1â makes a request to start a conversion on the regular channel and causes RCIP to become â1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing â1â has no effect if RSYNC=1 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTEN Disabled Trigger detection is disabled 0 RisingEdge Each rising edge on the selected trigger makes a request to launch an injected conversion 1 FallingEdge Each falling edge on the selected trigger makes a request to launch an injected conversion 2 BothEdges Both rising edges and falling edges on the selected trigger make requests to launch injected conversions 3 JEXTSEL Trigger signal selection for launching injected conversions 8 5 0 31 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JDMAEN Disabled The DMA channel is not enabled to read injected data 0 Enabled The DMA channel is enabled to read injected data 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSCAN Single One channel conversion is performed from the injected channel group and next the selected channel from this group is selected 0 Series The series of conversions for the injected group channels is executed, starting over with the lowest selected channel 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSYNC Disabled Do not launch an injected conversion synchronously with DFSDM_FLT0 0 Enabled Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSWSTARTW write Start Writing â1â makes a request to convert the channels in the injected conversion group, causing JCIP to become â1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing â1â has no effect if JSYNC=1 1 DFEN DFSDM enable 0 1 DFEN Disabled DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped 0 Enabled DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting 1 CR2 FLT0CR2 control register 2 0x4 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 AWDCH Disabled Analog watchdog is disabled on channel y 0 Enabled Analog watchdog is enabled on channel y 1 EXCH Extremes detector channel selection 8 8 EXCH Disabled Extremes detector does not accept data from channel y 0 Enabled Extremes detector accepts data from channel y 1 CKABIE Clock absence interrupt enable 6 1 CKABIE Disabled Detection of channel input clock absence interrupt is disabled 0 Enabled Detection of channel input clock absence interrupt is enabled 1 SCDIE Short-circuit detector interrupt enable 5 1 SCDIE Disabled Short-circuit detector interrupt is disabled 0 Enabled Short-circuit detector interrupt is enabled 1 AWDIE Analog watchdog interrupt enable 4 1 AWDIE Disabled Analog watchdog interrupt is disabled 0 Enabled Analog watchdog interrupt is enabled 1 ROVRIE Regular data overrun interrupt enable 3 1 ROVRIE Disabled Regular data overrun interrupt is disabled 0 Enabled Regular data overrun interrupt is enabled 1 JOVRIE Injected data overrun interrupt enable 2 1 JOVRIE Disabled Injected data overrun interrupt is disabled 0 Enabled Injected data overrun interrupt is enabled 1 REOCIE Regular end of conversion interrupt enable 1 1 REOCIE Disabled Regular end of conversion interrupt is disabled 0 Enabled Regular end of conversion interrupt is enabled 1 JEOCIE Injected end of conversion interrupt enable 0 1 JEOCIE Disabled Injected end of conversion interrupt is disabled 0 Enabled Injected end of conversion interrupt is enabled 1 ISR FLT0ISR interrupt and status register 0x8 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 SCDF Clear No short-circuit detector event occurred on channel y 0 Set The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers 1 CKABF Clock absence flag 16 8 CKABF Clear Clock signal on channel y is present. 0 Set Clock signal on channel y is not present 1 RCIP Regular conversion in progress status 14 1 RCIP NotInProgress No request to convert the regular channel has been issued 0 InProgress The conversion of the regular channel is in progress or a request for a regular conversion is pending 1 JCIP Injected conversion in progress status 13 1 JCIP NotInProgress No request to convert the injected channel group (neither by software nor by trigger) has been issued 0 InProgress The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to â1â being written to JSWSTART or to a trigger detection 1 AWDF Analog watchdog 4 1 AWDF Clear No Analog watchdog event occurred 0 Set The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers 1 ROVRF Regular conversion overrun flag 3 1 ROVRF Clear No regular conversion overrun has occurred 0 Set A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already â1â. RDATAR is not affected by overruns 1 JOVRF Injected conversion overrun flag 2 1 JOVRF Clear No injected conversion overrun has occurred 0 Set An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already â1â. JDATAR is not affected by overruns 1 REOCF End of regular conversion flag 1 1 REOCF Clear No regular conversion has completed 0 Set A regular conversion has completed and its data may be read 1 JEOCF End of injected conversion flag 0 1 JEOCF Clear No injected conversion has completed 0 Set An injected conversion has completed and its data may be read 1 ICR FLT0ICR interrupt flag clear register 0xC 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 0 255 CLRCKABF Clear the clock absence flag 16 8 0 255 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRROVRFW write Clear Writing â1â clears the ROVRF bit in the DFSDM_FLTxISR register 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRJOVRFW write Clear Writing â1â clears the JOVRF bit in the DFSDM_FLTxISR register 1 JCHGR FLT0JCHGR injected channel group selection register 0x10 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 0 255 FCR FLT0FCR filter control register 0x14 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FORD FastSinc FastSinc filter type 0 Sinc1 Sinc1 filter type 1 Sinc2 Sinc2 filter type 2 Sinc3 Sinc3 filter type 3 Sinc4 Sinc4 filter type 4 Sinc5 Sinc5 filter type 5 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 0 1023 IOSR Integrator oversampling ratio (averaging length) 0 8 0 255 JDATAR FLT0JDATAR data register for injected group 0x18 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 0 16777215 JDATACH Injected channel most recently converted 0 3 0 7 RDATAR FLT0RDATAR data register for the regular channel 0x1C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 0 16777215 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 0 7 AWHTR FLT0AWHTR analog watchdog high threshold register 0x20 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 0 16777215 4 0x1 0-3 BKAWH%s Break signal assignment to analog watchdog high threshold event 0 1 BKAWH0 NotAssigned Break i signal is not assigned to an analog watchdog high threshold event 0 Assigned Break i signal is assigned to an analog watchdog high threshold event 1 AWLTR FLT0AWLTR analog watchdog low threshold register 0x24 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 0 16777215 4 0x1 0-3 BKAWL%s Break signal assignment to analog watchdog low threshold event 0 1 BKAWL0 NotAssigned Break i signal is not assigned to an analog watchdog low threshold event 0 Assigned Break i signal is assigned to an analog watchdog low threshold event 1 AWSR FLT0AWSR analog watchdog status register 0x28 0x20 read-only 0x00000000 8 0x1 0-7 AWHTF%s Analog watchdog high threshold flag 8 1 AWHTF0 NoError No high threshold error 0 Error A high threshold error on channel y 1 8 0x1 0-7 AWLTF%s Analog watchdog low threshold flag 0 1 AWLTF0 NoError No low threshold error 0 Error A low threshold error on channel y 1 AWCFR FLT0AWCFR analog watchdog clear flag register 0x2C 0x20 read-write 0x00000000 8 0x1 0-7 CLRAWHTF%s Clear the analog watchdog high threshold flag 8 1 oneToClear CLRAWHTF0W write Clear Clear the corresponding AWHTF[y] bit 1 8 0x1 0-7 CLRAWLTF%s Clear the analog watchdog low threshold flag 0 1 oneToClear CLRAWLTF0W write Clear Clear the corresponding AWLTF[y] bit 1 EXMAX FLT0EXMAX Extremes detector maximum register 0x30 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 0 16777215 EXMAXCH Extremes detector maximum data channel 0 3 0 7 EXMIN FLT0EXMIN Extremes detector minimum register 0x34 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 0 16777215 EXMINCH Extremes detector minimum data channel 0 3 0 7 CNVTIMR FLT0CNVTIMR conversion timer register 0x38 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 0 268435455 RNG Random number generator RNG 0x50060800 0x0 0x400 registers RNG_HASH RNG and HASH global interrupt 80 CR CR control register 0x0 0x20 read-write 0x00000000 IE Interrupt enable 3 1 IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 RNGEN Random number generator enable 2 1 RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 CED Clock error detection 5 1 CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 CONFIGLOCK RNG Config lock 31 1 CONFIGLOCK Enabled Writes to the RNG_CR configuration bits [29:4] are allowed 0 Disabled Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset 1 CONDRST Conditioning soft reset 30 1 RNG_CONFIG1 RNG configuration 1 20 6 RNG_CONFIG1 ConfigA Recommended value for config A (NIST certifiable) 15 ConfigB Recommended value for config B (not NIST certifiable) 24 CLKDIV Clock divider factor 16 4 CLKDIV Div1 Internal RNG clock after divider is similar to incoming RNG clock 0 Div2 Divide RNG clock by 2^1 1 Div4 Divide RNG clock by 2^2 2 Div8 Divide RNG clock by 2^3 3 Div16 Divide RNG clock by 2^4 4 Div32 Divide RNG clock by 2^5 5 Div64 Divide RNG clock by 2^6 6 Div128 Divide RNG clock by 2^7 7 Div256 Divide RNG clock by 2^8 8 Div512 Divide RNG clock by 2^9 9 Div1024 Divide RNG clock by 2^10 10 Div2048 Divide RNG clock by 2^11 11 Div4096 Divide RNG clock by 2^12 12 Div8192 Divide RNG clock by 2^13 13 Div16384 Divide RNG clock by 2^14 14 Div32768 Divide RNG clock by 2^15 15 RNG_CONFIG2 RNG configuration 2 13 3 RNG_CONFIG2 ConfigA_B Recommended value for config A and B 0 NISTC Non NIST compliant 12 1 NISTC Default Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used 0 Custom Custom values for NIST compliant RNG 1 RNG_CONFIG3 RNG configuration 3 8 4 RNG_CONFIG3 ConfigB Recommended value for config B (not NIST certifiable) 0 ConfigA Recommended value for config A (NIST certifiable) 13 SR SR status register 0x4 0x20 0x00000000 CEIS Clock error interrupt status 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 SECS Seed error current status 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CECS Clock error current status 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 DRDY Data ready 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 DR DR data register 0x8 0x20 read-only 0x00000000 RNDATA Random data 0 32 0 4294967295 HTCR health test control register 0x10 0x00005A4E HTCFG health test configuration 0 32 HTCFG Recommended Recommended value for RNG certification (0x0000_AA74) 43636 Magic Magic number to be written before any write (0x1759_0ABC) 391711420 AES Advanced encryption standard hardware accelerator AES 0x50060000 0x0 0x400 registers AES AES global interrupt 79 CR CR control register 0x0 0x20 read-write 0x00000000 DMAOUTEN Enable DMA management of data output phase 12 1 DMAOUTEN Disabled Disable DMA Output 0 Enabled Enabled DMA Output 1 DMAINEN Enable DMA management of data input phase 11 1 DMAINEN Disabled Disable DMA Input 0 Enabled Enable DMA Input 1 ERRIE Error interrupt enable 10 1 ERRIE Disabled Disable (mask) error interrupt 0 Enabled Enable error interrupt 1 CCFIE CCF flag interrupt enable 9 1 CCFIE Disabled Disable (mask) CCF interrupt 0 Enabled Enable CCF interrupt 1 ERRC Error clear 8 1 ERRCW write Clear Clear RDERR and WRERR flags 1 CCFC Computation Complete Flag Clear 7 1 CCFCW write Clear Clear computation complete flag 1 CHMOD AES chaining mode 5 2 CHMOD ECB Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1 0 CBC Cipher-block chaining (CBC) 1 CTR Counter mode (CTR) 2 GCM Galois counter mode (GCM) and Galois message authentication code (GMAC) 3 MODE AES operating mode 3 2 MODE Mode1 Mode 1: encryption 0 Mode2 Mode 2: key derivation (or key preparation for ECB/CBC decryption) 1 Mode3 Mode 3: decryption 2 Mode4 Mode 4: key derivation then single decryption 3 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 DATATYPE None Word 0 HalfWord Half-word (16-bit) 1 Byte Byte (8-bit) 2 Bit Bit 3 EN AES enable 0 1 EN Disabled Disable AES 0 Enabled Enable AES 1 NPBLB Number of padding bytes in last block 20 4 0 15 KEYSIZE Key size selection 18 1 KEYSIZE AES128 128 0 AES256 256 1 CHMOD_2 Chaining mode selection, bit [2] 16 1 CHMOD_2 CHMOD Mode as per CHMOD (ECB, CBC, CTR, GCM) 0 CCM Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB) 1 GCMPH GCM or CCM phase selection 13 2 GCMPH Init Init phase 0 Header Header phase 1 Payload Payload phase 2 Final Final Phase 3 SR SR status register 0x4 0x20 read-only 0x00000000 WRERR Write error flag 2 1 WRERR NoError Write error not detected 0 Error Write error detected 1 RDERR Read error flag 1 1 RDERR NoError Read error not detected 0 Error Read error detected 1 CCF Computation complete flag 0 1 CCF Complete Computation complete 0 NotComplete Computation not complete 1 BUSY Busy 3 1 BUSY Idle Idle 0 Busy Busy 1 DINR DINR data input register 0x8 0x20 read-write 0x00000000 DIN Data Input Register 0 32 0 4294967295 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 DOUT Data output register 0 32 0 4294967295 KEYR0 KEYR0 key register 0 0x10 0x20 read-write 0x00000000 KEY Data Output Register (LSB key [31:0]) 0 32 0 4294967295 KEYR1 KEYR1 key register 1 0x14 0x20 read-write 0x00000000 KEY AES key register (key [63:32]) 0 32 0 4294967295 KEYR2 KEYR2 key register 2 0x18 0x20 read-write 0x00000000 KEY AES key register (key [95:64]) 0 32 0 4294967295 KEYR3 KEYR3 key register 3 0x1C 0x20 read-write 0x00000000 KEY AES key register (MSB key [127:96]) 0 32 0 4294967295 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 IVI initialization vector register (LSB IVR [31:0]) 0 32 0 4294967295 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [63:32]) 0 32 0 4294967295 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [95:64]) 0 32 0 4294967295 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization Vector Register (MSB IVR [127:96]) 0 32 0 4294967295 KEYR4 key register 4 0x30 0x20 read-write 0x00000000 KEY Cryptographic key, bits [159:128] 0 32 0 4294967295 KEYR5 key register 5 0x34 0x20 read-write 0x00000000 KEY Cryptographic key, bits [191:160] 0 32 0 4294967295 KEYR6 key register 6 0x38 0x20 read-write 0x00000000 KEY Cryptographic key, bits [223:192] 0 32 0 4294967295 KEYR7 key register 7 0x3C 0x20 read-write 0x00000000 KEY Cryptographic key, bits [255:224] 0 32 0 4294967295 SUSP0R suspend registers 0x40 0x20 read-write 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP1R suspend registers 0x44 0x20 read-write 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP2R suspend registers 0x48 0x20 read-write 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP3R suspend registers 0x4C 0x20 read-write 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP4R suspend registers 0x50 0x20 read-write 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP5R suspend registers 0x54 0x20 read-write 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP6R suspend registers 0x58 0x20 read-write 0x00000000 SUSP AES suspend 0 32 0 4294967295 SUSP7R suspend registers 0x5C 0x20 read-write 0x00000000 SUSP AES suspend 0 32 0 4294967295 ADC1 Analog-to-Digital Converter ADC 0x50040000 0x0 0xB9 registers ADC1_2 ADC1 and ADC2 global interrupt 18 ISR ISR interrupt and status register 0x0 0x20 read-write 0x00000000 JQOVF JQOVF 10 1 oneToClear JQOVFR read NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 JQOVFW write Clear Clear injected context queue overflow flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 oneToClear AWD1R read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD1W write Clear Clear analog watchdog event occurred flag 1 JEOS JEOS 6 1 oneToClear JEOSR read NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 JEOSW write Clear Clear Injected sequence complete flag 1 JEOC JEOC 5 1 oneToClear JEOCR read NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOCW write Clear Clear injected conversion complete flag 1 OVR OVR 4 1 oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear overrun occurred flag 1 EOS EOS 3 1 oneToClear EOSR read NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 EOSW write Clear Clear regular sequence complete flag 1 EOC EOC 2 1 oneToClear EOCR read NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOCW write Clear Clear regular conversion complete flag 1 EOSMP EOSMP 1 1 oneToClear EOSMPR read NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOSMPW write Clear Clear end of sampling phase reached flag 1 ADRDY ADRDY 0 1 oneToClear ADRDYR read NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 ADRDYW write Clear Clear ADC is ready to start conversion flag 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 JQOVFIE JQOVFIE 10 1 JQOVFIE Disabled Injected context queue overflow interrupt disabled 0 Enabled Injected context queue overflow interrupt enabled 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 AWD1IE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 JEOSIE JEOSIE 6 1 JEOSIE Disabled End of injected sequence interrupt disabled 0 Enabled End of injected sequence interrupt enabled 1 JEOCIE JEOCIE 5 1 JEOCIE Disabled End of injected conversion interrupt disabled 0 Enabled End of injected conversion interrupt enabled 1 OVRIE OVRIE 4 1 OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled 1 EOSIE EOSIE 3 1 EOSIE Disabled End of regular sequence interrupt disabled 0 Enabled End of regular sequence interrupt enabled 1 EOCIE EOCIE 2 1 EOCIE Disabled End of regular conversion interrupt disabled 0 Enabled End of regular conversion interrupt enabled 1 EOSMPIE EOSMPIE 1 1 EOSMPIE Disabled End of regular conversion sampling phase interrupt disabled 0 Enabled End of regular conversion sampling phase interrupt enabled 1 ADRDYIE ADRDYIE 0 1 ADRDYIE Disabled ADC ready interrupt disabled 0 Enabled ADC ready interrupt enabled 1 CR CR control register 0x8 0x20 read-write 0x00000000 ADCAL ADCAL 31 1 oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 ADCALDIF ADCALDIF 30 1 ADCALDIF SingleEnded Calibration for single-ended mode 0 Differential Calibration for differential mode 1 DEEPPWD DEEPPWD 29 1 DEEPPWD NotDeepPowerDown ADC not in Deep-power down 0 DeepPowerDown ADC in Deep-power-down (default reset state) 1 ADVREGEN ADVREGEN 28 1 ADVREGEN Disabled ADC Voltage regulator disabled 0 Enabled ADC Voltage regulator enabled 1 ADSTP ADSTP 4 1 oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 JADSTP JADSTP 5 1 oneToSet read write ADSTART ADSTART 2 1 oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 JADSTART JADSTART 3 1 oneToSet read write ADDIS ADDIS 1 1 oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADEN ADEN 0 1 oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 CFGR CFGR configuration register 0xC 0x20 read-write 0x00000000 JQDIS Injected Queue disable 31 1 AWD1CH AWDCH1CH 26 5 0 18 JAUTO JAUTO 25 1 JAUTO Disabled Automatic injected group conversion disabled 0 Enabled Automatic injected group conversion enabled 1 JAWD1EN JAWD1EN 24 1 JAWD1EN Disabled Analog watchdog 1 disabled on injected channels 0 Enabled Analog watchdog 1 enabled on injected channels 1 AWD1EN AWD1EN 23 1 AWD1EN Disabled Analog watchdog 1 disabled on regular channels 0 Enabled Analog watchdog 1 enabled on regular channels 1 AWD1SGL AWD1SGL 22 1 AWD1SGL All Analog watchdog 1 enabled on all channels 0 Single Analog watchdog 1 enabled on single channel selected in AWD1CH 1 JQM JQM 21 1 JQM Mode0 JSQR Mode 0: Queue maintains the last written configuration into JSQR 0 Mode1 JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence 1 JDISCEN JDISCEN 20 1 JDISCEN Disabled Discontinuous mode on injected channels disabled 0 Enabled Discontinuous mode on injected channels enabled 1 DISCNUM DISCNUM 17 3 0 7 DISCEN DISCEN 16 1 DISCEN Disabled Discontinuous mode on regular channels disabled 0 Enabled Discontinuous mode on regular channels enabled 1 AUTDLY AUTDLY 14 1 AUTDLY Off Auto delayed conversion mode off 0 On Auto delayed conversion mode on 1 CONT CONT 13 1 CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 OVRMOD OVRMOD 12 1 OVRMOD Preserve Preserve DR register when an overrun is detected 0 Overwrite Overwrite DR register when an overrun is detected 1 EXTEN EXTEN 10 2 EXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 EXTSEL EXTSEL3 6 4 EXTSEL TIM1_CC1 Timer 1 CC1 event 0 TIM1_CC2 Timer 1 CC2 event 1 TIM1_CC3 Timer 1 CC3 event 2 TIM2_CC2 Timer 2 CC2 event 3 TIM3_TRGO Timer 3 TRGO event 4 EXTI11 EXTI line 11 6 TIM1_TRGO Timer 1 TRGO event 9 TIM1_TRGO2 Timer 1 TRGO2 event 10 TIM2_TRGO Timer 2 TRGO event 11 TIM6_TRGO Timer 6 TRGO event 13 TIM15_TRGO Timer 15 TRGO event 14 TIM3_CC4 Timer 3 CC4 event 15 ALIGN ALIGN 5 1 ALIGN Right Right alignment 0 Left Left alignment 1 RES RES 3 2 RES Bits12 12-bit 0 Bits10 10-bit 1 Bits8 8-bit 2 Bits6 6-bit 3 DFSDMCFG DFSDM mode configuration 2 1 DMACFG DMACFG 1 1 DMACFG OneShot DMA One Shot mode selected 0 Circular DMA Circular mode selected 1 DMAEN DMAEN 0 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 CFGR2 CFGR2 configuration register 0x10 0x20 read-write 0x00000000 ROVSM Regular Oversampling mode 10 1 ROVSM ContinuedMode When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 0 ResumedMode When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) 1 TROVS Triggered Regular Oversampling 9 1 TROVS All All oversampled conversions for a channel are done consecutively following a trigger 0 Single Each oversampled conversion for a channel needs a new trigger 1 OVSS ALIGN 5 4 OVSS NoShift No Shift 0 Shift1Bit Shift 1-bit 1 Shift2Bit Shift 2-bit 2 Shift3Bit Shift 3-bit 3 Shift4Bit Shift 4-bit 4 Shift5Bit Shift 5-bit 5 Shift6Bit Shift 6-bit 6 Shift7Bit Shift 7-bit 7 Shift8Bit Shift 8-bit 8 OVSR RES 2 3 OVSR Ratio2 2x 0 Ratio4 4x 1 Ratio8 8x 2 Ratio16 16x 3 Ratio32 32x 4 Ratio64 64x 5 Ratio128 128x 6 Ratio256 256x 7 JOVSE DMACFG 1 1 JOVSE Disabled Injected Oversampling disabled 0 Enabled Injected Oversampling enabled 1 ROVSE DMAEN 0 1 ROVSE Disabled Regular Oversampling disabled 0 Enabled Regular Oversampling enabled 1 SMPR1 SMPR1 sample time register 1 0x14 0x20 read-write 0x00000000 10 0x3 0-9 SMP%s Channel %s sample time selection 0 3 SMP0 Cycles2_5 2.5 ADC clock cycles 0 Cycles6_5 6.5 ADC clock cycles 1 Cycles12_5 12.5 ADC clock cycles 2 Cycles24_5 24.5 ADC clock cycles 3 Cycles47_5 47.5 ADC clock cycles 4 Cycles92_5 92.5 ADC clock cycles 5 Cycles247_5 247.5 ADC clock cycles 6 Cycles640_5 640.5 ADC clock cycles 7 SMPPLUS Addition of one clock cycle to the sampling time 31 1 SMPPLUS KeepCycles The sampling time remains set to 2.5 ADC clock cycles remains 0 Add1Cycle 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers 1 SMPR2 SMPR2 sample time register 2 0x18 0x20 read-write 0x00000000 9 0x3 10-18 SMP%s Channel %s sample time selection 0 3 TR1 TR1 watchdog threshold register 1 0x20 0x20 read-write 0x0FFF0000 HT1 HT1 16 12 0 4095 LT1 LT1 0 12 0 4095 TR2 TR2 watchdog threshold register 0x24 0x20 read-write 0x0FFF0000 HT2 HT2 16 8 0 255 LT2 LT2 0 8 0 255 TR3 TR3 watchdog threshold register 3 0x28 0x20 read-write 0x0FFF0000 HT3 HT3 16 8 0 255 LT3 LT3 0 8 0 255 SQR1 SQR1 regular sequence register 1 0x30 0x20 read-write 0x00000000 4 0x6 1-4 SQ%s %s conversion in regular sequence 6 5 0 18 L Regular channel sequence length 0 4 0 15 SQR2 SQR2 regular sequence register 2 0x34 0x20 read-write 0x00000000 5 0x6 5-9 SQ%s %s conversion in regular sequence 0 5 SQR3 SQR3 regular sequence register 3 0x38 0x20 read-write 0x00000000 5 0x6 10-14 SQ%s %s conversion in regular sequence 0 5 SQR4 SQR4 regular sequence register 4 0x3C 0x20 read-write 0x00000000 2 0x6 15-16 SQ%s %s conversion in regular sequence 0 5 DR DR regular Data Register 0x40 0x20 read-only 0x00000000 RDATA Regular Data converted 0 16 0 65535 JSQR JSQR injected sequence register 0x4C 0x20 read-write 0x00000000 4 0x6 1-4 JSQ%s %s conversion in injected sequence 8 5 0 19 JEXTEN JEXTEN 6 2 JEXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 JEXTSEL JEXTSEL 2 4 JEXTSEL TIM1_TRGO Timer 1 TRGO event 0 TIM1_CC4 Timer 1 CC4 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM2_CC1 Timer 2 CC1 event 3 TIM3_CC4 Timer 3 CC4 event 4 EXTI15 EXTI line 15 6 TIM1_TRGO2 Timer 1 TRGO2 event 8 TIM3_CC3 Timer 3 CC3 event 11 TIM3_TRGO Timer 3 TRGO event 12 TIM3_CC1 Timer 3 CC1 event 13 TIM6_TRGO Timer 6 TRGO event 14 TIM15_TRGO Timer 15 TRGO event 15 JL JL 0 2 0 3 4 0x4 1-4 OFR%s OFR%s offset register %s 0x60 0x20 read-write 0x00000000 OFFSET_EN Offset X Enable 31 1 OFFSET_EN Disabled This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0] 0 Enabled This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0] 1 OFFSET_CH Channel selection for the data offset X 26 5 0 31 OFFSET Data offset X for the channel programmed into bits OFFSET_CH 0 12 0 4095 4 0x4 1-4 JDR%s JDR%s injected data register %s 0x80 0x20 read-only 0x00000000 JDATA Injected data 0 16 0 65535 AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 0x20 read-write 0x00000000 18 0x1 0-17 AWD2CH%s AWD2CH 0 1 AWD2CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 0x20 read-write 0x00000000 18 0x1 0-17 AWD3CH%s AWD3CH 0 1 AWD3CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 0x20 0x00000000 18 0x1 0-17 DIFSEL%s Differential mode for channel %s 1 1 DIFSEL0 SingleEnded Input channel is configured in single-ended mode 0 Differential Input channel is configured in differential mode 1 CALFACT CALFACT Calibration Factors 0xB4 0x20 read-write 0x00000000 CALFACT_D CALFACT_D 16 7 0 127 CALFACT_S CALFACT_S 0 7 0 127 ADC_Common Analog-to-Digital Converter ADC 0x50040300 0x0 0x11 registers CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 ADRDY_MST ADDRDY_MST 0 1 ADRDY_MST NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 EOSMP_MST EOSMP_MST 1 1 EOSMP_MST NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOC_MST EOC_MST 2 1 EOC_MST NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOS_MST EOS_MST 3 1 EOS_MST NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 OVR_MST OVR_MST 4 1 OVR_MST NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 JEOC_MST JEOC_MST 5 1 JEOC_MST NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOS_MST JEOS_MST 6 1 JEOS_MST NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 AWD1_MST AWD1_MST 7 1 AWD1_MST NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD2_MST AWD2_MST 8 1 AWD3_MST AWD3_MST 9 1 JQOVF_MST JQOVF_MST 10 1 JQOVF_MST NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 ADRDY_SLV ADRDY_SLV 16 1 EOSMP_SLV EOSMP_SLV 17 1 EOC_SLV End of regular conversion of the slave ADC 18 1 EOS_SLV End of regular sequence flag of the slave ADC 19 1 OVR_SLV Overrun flag of the slave ADC 20 1 JEOC_SLV End of injected conversion flag of the slave ADC 21 1 JEOS_SLV End of injected sequence flag of the slave ADC 22 1 AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC 26 1 CCR CCR ADC common control register 0x8 0x20 read-write 0x00000000 DUAL Dual ADC mode selection 0 5 DUAL Independent Independent mode 0 DualRJ Dual, combined regular simultaneous + injected simultaneous mode 1 DualRA Dual, combined regular simultaneous + alternate trigger mode 2 DualIJ Dual, combined interleaved mode + injected simultaneous mode 3 DualJ Dual, injected simultaneous mode only 5 DualR Dual, regular simultaneous mode only 6 DualI Dual, interleaved mode only 7 DualA Dual, alternate trigger mode only 9 DELAY Delay between 2 sampling phases 8 4 0 15 DMACFG DMA configuration (for multi-ADC mode) 13 1 DMACFG OneShotMode DMA One Shot mode selected 0 CircularMode DMA Circular mode selected 1 MDMA Direct memory access mode for multi ADC mode 14 2 MDMA Disabled MDMA mode disabled 0 Interleaved Enable dual interleaved mode to output to the master channel of DFSDM interface both Master and the Slave result (16-bit data width) 1 Bits12_10 MDMA mode enabled for 12 and 10-bit resolution 2 Bits8_6 MDMA mode enabled for 8 and 6-bit resolution 3 CKMODE ADC clock mode 16 2 CKMODE Asynchronous Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock 0 SyncDiv1 Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck 1 SyncDiv2 Use AHB clock rcc_hclk3 divided by 2 2 SyncDiv4 Use AHB clock rcc_hclk3 divided by 4 3 VREFEN VREFINT enable 22 1 VREFEN Disabled V_REFINT channel disabled 0 Enabled V_REFINT channel enabled 1 VSENSEEN Temperature sensor selection 23 1 VSENSEEN Disabled The selected ADC channel disabled 0 Enabled The selected ADC channel enabled 1 VBATEN VBAT selection 24 1 PRESC ADC prescaler 18 4 PRESC Div1 Input ADC clock not divided 0 Div2 Input ADC clock divided by 2 1 Div4 Input ADC clock divided by 4 2 Div6 Input ADC clock divided by 6 3 Div8 Input ADC clock divided by 8 4 Div10 Input ADC clock divided by 10 5 Div12 Input ADC clock divided by 12 6 Div16 Input ADC clock divided by 16 7 Div32 Input ADC clock divided by 32 8 Div64 Input ADC clock divided by 64 9 Div128 Input ADC clock divided by 128 10 Div256 Input ADC clock divided by 256 11 CDR CDR ADC common regular data register for dual and triple modes 0xC 0x20 read-only 0x00000000 RDATA_SLV Regular data of the slave ADC 16 16 0 65535 RDATA_MST Regular data of the master ADC 0 16 0 65535 GPIOA General-purpose I/Os GPIO 0x48000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xA8000000 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 IDR%s Port input data pin %s 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 ODR%s Port output data pin %s 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 16 1 BitReset Reset Resets the corresponding ODRx bit 1 16 0x1 0-15 BS%s Port x set pin %s 0 1 BitSet Set Sets the corresponding ODRx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 8 0x4 L0,L1,L2,L3,L4,L5,L6,L7 AFR%s Alternate function selection for port x bit y (y = 0..7) 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 8 0x4 H8,H9,H10,H11,H12,H13,H14,H15 AFR%s Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 0 1 BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 ASCR ASCR GPIO port analog switch control register 0x2C 0x20 read-write 0x00000000 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 GPIOB General-purpose I/Os GPIO 0x48000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000280 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 ASCR ASCR GPIO port analog switch control register 0x2C 0x20 read-write 0x00000000 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 GPIOC General-purpose I/Os GPIO 0x48000800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000000 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 ASCR ASCR GPIO port analog switch control register 0x2C 0x20 read-write 0x00000000 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 GPIOD 0x48000C00 GPIOE 0x48001000 GPIOF 0x48001400 GPIOG 0x48001800 GPIOH 0x48001C00 GPIOI General-purpose I/Os GPIO 0x48002000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000000 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 SAI1 Serial audio interface SAI 0x40015400 0x0 0x400 registers SAI1 SAI1 global interrupt 74 GCR Global configuration register 0x0 0x00000000 SYNCOUT Synchronization outputs 4 2 SYNCOUT Disabled No synchronization output signals. SYNCOUT[1:0] should be configured as âNo synchronization output signalsâ when audio block is configured as SPDIF 0 BlockA Block A used for further synchronization for others SAI 1 BlockB Block B used for further synchronization for others SAI 2 SYNCIN Synchronization inputs 0 2 2 0x20 A,B CH%s Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR 0x4 CR1 ACR1 AConfiguration register 1 0x0 0x20 read-write 0x00000040 MCKDIV Master clock divider 20 6 0 63 NOMCK No divider 19 1 NOMCK MasterClock MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value 0 NoDiv MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. 1 DMAEN DMA enable 17 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 SAIEN Audio block A enable 16 1 SAIEN Disabled SAI audio block disabled 0 Enabled SAI audio block enabled 1 OUTDRIV Output drive 13 1 OUTDRIV OnStart Audio block output driven when SAIEN is set 0 Immediately Audio block output driven immediately after the setting of this bit 1 MONO Mono mode 12 1 MONO Stereo Stereo mode 0 Mono Mono mode 1 SYNCEN Synchronization enable 10 2 SYNCEN Asynchronous audio sub-block in asynchronous mode 0 Internal audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode 1 External audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode 2 CKSTR Clock strobing edge 9 1 CKSTR FallingEdge Data strobing edge is falling edge of SCK 0 RisingEdge Data strobing edge is rising edge of SCK 1 LSBFIRST Least significant bit first 8 1 LSBFIRST MsbFirst Data are transferred with MSB first 0 LsbFirst Data are transferred with LSB first 1 DS Data size 5 3 DS Bit8 8 bits 2 Bit10 10 bits 3 Bit16 16 bits 4 Bit20 20 bits 5 Bit24 24 bits 6 Bit32 32 bits 7 PRTCFG Protocol configuration 2 2 PRTCFG Free Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol 0 Spdif SPDIF protocol 1 Ac97 ACâ97 protocol 2 MODE Audio block mode 0 2 MODE MasterTx Master transmitter 0 MasterRx Master receiver 1 SlaveTx Slave transmitter 2 SlaveRx Slave receiver 3 OSR Oversampling ratio for master clock 26 1 OSR Multiplier256 Master clock frequency = FFS x 256 0 Multiplier512 Master clock frequency = FFS x 512 1 CR2 ACR2 AConfiguration register 2 0x4 0x20 read-write 0x00000000 COMP Companding mode 14 2 read-write COMP NoCompanding No companding algorithm 0 MuLaw Î¼-Law algorithm 2 ALaw A-Law algorithm 3 CPL Complement bit 13 1 read-write CPL OnesComplement 1âs complement representation 0 TwosComplement 2âs complement representation 1 MUTECNT Mute counter 7 6 read-write 0 63 MUTEVAL Mute value 6 1 read-write MUTEVAL SendZero Bit value 0 is sent during the mute mode 0 SendLast Last values are sent during the mute mode 1 MUTE Mute 5 1 read-write MUTE Disabled No mute mode 0 Enabled Mute mode enabled 1 TRIS Tristate management on data line 4 1 read-write TRIS DrivenWhileInactive SD output line is still driven by the SAI when a slot is inactive 0 HighZ SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive 1 FFLUSH FIFO flush 3 1 write-only FFLUSH NoFlush No FIFO flush 0 Flush FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared 1 FTH FIFO threshold 0 3 read-write FTH Empty FIFO empty 0 Quarter1 1â4 FIFO 1 Quarter2 1â2 FIFO 2 Quarter3 3â4 FIFO 3 Full FIFO full 4 FRCR AFRCR AFRCR 0x8 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 read-write FSOFF OnFirst FS is asserted on the first bit of the slot 0 0 BeforeFirst FS is asserted one bit before the first bit of the slot 0 1 FSPOL Frame synchronization polarity 17 1 read-write FSPOL FallingEdge FS is active low (falling edge) 0 RisingEdge FS is active high (rising edge) 1 FSDEF Frame synchronization definition 16 1 read-write FSALL Frame synchronization active level length 8 7 read-write FRL Frame length 0 8 read-write SLOTR ASLOTR ASlot register 0xC 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 SLOTEN Inactive Inactive slot 0 Active Active slot 1 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 SLOTSZ DataSize The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) 0 Bit16 16-bit 1 Bit32 32-bit 2 FBOFF First bit offset 0 5 IM AIM AInterrupt mask register2 0x10 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 LFSDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 AFSDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 CNRDYIE Codec not ready interrupt enable 4 1 CNRDYIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 FREQIE FIFO request interrupt enable 3 1 FREQIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 WCKCFGIE Wrong clock configuration interrupt enable 2 1 WCKCFGIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 MUTEDETIE Mute detection interrupt enable 1 1 MUTEDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 OVRUDRIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 SR ASR AStatus register 0x14 0x20 read-only 0x00000008 FLVL FIFO level threshold 16 3 FLVLR Empty FIFO empty 0 Quarter1 FIFO <= 1â4 but not empty 1 Quarter2 1â4 < FIFO <= 1â2 2 Quarter3 1â2 < FIFO <= 3â4 3 Quarter4 3â4 < FIFO but not full 4 Full FIFO full 5 LFSDET Late frame synchronization detection 6 1 LFSDETR NoError No error 0 NoSync Frame synchronization signal is not present at the right time 1 AFSDET Anticipated frame synchronization detection 5 1 AFSDETR NoError No error 0 EarlySync Frame synchronization signal is detected earlier than expected 1 CNRDY Codec not ready 4 1 CNRDYR Ready External ACâ97 Codec is ready 0 NotReady External ACâ97 Codec is not ready 1 FREQ FIFO request 3 1 FREQR NoRequest No FIFO request 0 Request FIFO request to read or to write the SAI_xDR 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 WCKCFGR Correct Clock configuration is correct 0 Wrong Clock configuration does not respect the rule concerning the frame length specification 1 MUTEDET Mute detection 1 1 MUTEDETR NoMute No MUTE detection on the SD input line 0 Mute MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame 1 OVRUDR Overrun / underrun 0 1 OVRUDRR NoError No overrun/underrun error 0 Overrun Overrun/underrun error detection 1 CLRFR ACLRFR AClear flag register 0x18 0x20 write-only 0x00000000 CLFSDET Clear late frame synchronization detection flag 6 1 CLFSDETW Clear Clears the LFSDET flag 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CAFSDETW Clear Clears the AFSDET flag 1 CCNRDY Clear codec not ready flag 4 1 CCNRDYW Clear Clears the CNRDY flag 1 CWCKCFG Clear wrong clock configuration flag 2 1 CWCKCFGW Clear Clears the WCKCFG flag 1 CMUTEDET Mute detection flag 1 1 CMUTEDETW Clear Clears the MUTEDET flag 1 COVRUDR Clear overrun / underrun 0 1 COVRUDRW Clear Clears the OVRUDR flag 1 DR ADR AData register 0x1C 0x20 read-write 0x00000000 DATA Data 0 32 SAI2 0x40015800 SAI2 SAI2 global interrupt 75 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_TIM15 TIM1 Break/TIM15 global interrupts 24 TIM1_UP_TIM16 TIM1 Update/TIM16 global interrupts 25 TIM1_TRG_COM_TIM17 TIM1 Trigger and Commutation interrupts and TIM17 global interrupt 26 TIM1_CC TIM1 Capture Compare interrupt 27 CR1 CR1 TIM1 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT. 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CR2 CR2 TIM1 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 TI1S TI1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 3 0x2 1-3 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 MMS2 Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 20 4 read-write SMCR SMCR TIM1 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Codes above 1000: Reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write SMS Disabled Slave mode disabled - if CEN = â1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 TS TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 167: TIMxTIM1 internal trigger connection on page 777 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write DIER DIER TIM1 DMA/interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 read-write COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR TIM1 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to Section 24.4.3: TIMx slave mode control register (TIM1_SMCRTIMx_SMCR)(x = 1, 8)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 B2IF Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 8 1 read-write zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 SBIF System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 13 1 read-write zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 CC5IF Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output) 16 1 read-write zeroToClear read write CC6IF Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output) 17 1 read-write zeroToClear read write EGR EGR TIM1 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 B2G Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 8 1 write-only B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Input CCMR1_Input TIM1 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM1 capture/compare mode register 1 CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM1 capture/compare mode register 2 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM1 capture/compare mode register 2 CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM1 capture/compare enable register 0x20 0x20 0x00000000 0xFFFFFFFF 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 3 0x4 1-3 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM1 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. 31 1 read-only PSC PSC TIM1 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). 0 16 read-write 0 65535 ARR ARR TIM1 auto-reload register 0x2C 0x10 0x0000FFFF 0x0000FFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 24.3.1: Time-base unit on page 691 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 RCR RCR TIM1 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode. 0 16 read-write 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 0x00000000 0x0000FFFF CCR Capture/Compare value 0 16 read-write 0 65535 BDTR BDTR TIM1 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 24.4.11: TIMx capture/compare enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 24.4.11: TIMx capture/compare enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per Figure 189: Break and Break2 circuitry overview). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (Section 24.4.11: TIMx capture/compare enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write BK2F Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 20 4 read-write BK2E Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per Figure 189: Break and Break2 circuitry overview). Note: The BKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 24 1 read-write BK2P Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 25 1 read-write DCR DCR TIM1 DMA control register 0x48 0x10 0x00000000 0x0000FFFF DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write 0 18 DMAR DMAR TIM1 DMA address for full transfer 0x4C 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write CCMR3_Output CCMR3_Output TIM1 capture/compare mode register 3 0x54 0x20 0x00000000 0xFFFFFFFF 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 5-6 OC%sM Output compare %s mode 4 3 read-write 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCR5 CCR5 capture/compare register 0x58 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 16 read-write 0 65535 GC5C1 Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 29 1 read-write GC5C2 Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 30 1 read-write GC5C3 Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. 31 1 read-write CCR6 CCR6 capture/compare register 0x5C 0x10 0x00000000 0x0000FFFF CCR Capture/Compare value 0 16 read-write 0 65535 AF1 AF1 TIM1 alternate function option register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKCMP1E BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input. COMP1 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP2E BRK COMP2 enable This bit enables the COMP2 for the timer s BRK input. COMP2 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKDF1BK0E BRK dfsdm1_break[0] enable This bit enables the dfsdm1_break[0] for the timer s BRK input. dfsdm1_break[0] output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKCMP1P BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP2P BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write ETRSEL ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 4 read-write AF2 AF2 TIM1 Alternate function register 2 0x64 0x20 0x00000001 0xFFFFFFFF BK2INE BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer s BRK2 input. BKIN2 input is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BK2CMP1E BRK2 COMP1 enable This bit enables the COMP1 for the timer s BRK2 input. COMP1 output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BK2CMP2E BRK2 COMP2 enable This bit enables the COMP2 for the timer s BRK2 input. COMP2 output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BK2DF1BK1E BRK2 dfsdm1_break[1] enable This bit enables the dfsdm1_break[1] for the timer s BRK2 input. dfsdm1_break[1] output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BK2INP BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BK2CMP1P BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BK2CMP2P BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write TISEL TISEL TIM1 timer input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write TI2SEL selects TI2[0] to TI2[15] input Others: Reserved 8 4 read-write TI3SEL selects TI3[0] to TI3[15] input Others: Reserved 16 4 read-write TI4SEL selects TI4[0] to TI4[15] input Others: Reserved 24 4 read-write TIM2 General-purpose-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 CR1 CR1 TIM2 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CR2 CR2 TIM2 control register 2 0x4 0x10 0x00000000 0x0000FFFF CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 TI1S TI1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 SMCR SMCR TIM2 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write SMS Disabled Slave mode disabled - if CEN = â1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 TS TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 179: TIMx internal trigger connection on page 846 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/Slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). Note: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write DIER DIER TIM2 DMA/Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR TIM2 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow (for TIM2 to TIM4) and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM2 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM2 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM2 capture/compare mode register 1 CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM2 capture/compare mode register 2 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM2 capture/compare mode register 2 CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM2 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM2 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value 0 32 read-write 0 4294967295 CNT_ALTERNATE CNT_ALTERNATE TIM2 counter CNT 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value 0 31 read-write UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register 31 1 read-write PSC PSC TIM2 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). 0 16 read-write 0 65535 ARR ARR TIM2 auto-reload register 0x2C 0x20 0xFFFFFFFF 0xFFFFFFFF ARR Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 25.3.1: Time-base unit on page 786 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 32 read-write 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 32 read-write 0 4294967295 DCR DCR TIM2 DMA control register 0x48 0x10 0x00000000 0x0000FFFF DBA DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ... 8 5 read-write 0 18 DMAR DMAR TIM2 DMA address for full transfer 0x4C 0x10 0x00000000 0x0000FFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 16 read-write AF1 AF1 TIM2 alternate function option register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL ETR source selection These bits select the ETR input source. Others: Reserved 14 4 read-write TISEL TISEL TIM2 timer input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved 0 4 read-write TI2SEL TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved 8 4 read-write TI3SEL TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved 16 4 read-write TI4SEL TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. Others: Reserved 24 4 read-write TIM3 General-purpose-timers TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 global interrupt 29 CR1 CR1 TIM3 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CR2 CR2 TIM3 control register 2 0x4 0x10 0x00000000 0x0000FFFF CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 TI1S TI1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 SMCR SMCR TIM3 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write SMS Disabled Slave mode disabled - if CEN = â1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 TS TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 179: TIMx internal trigger connection on page 846 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/Slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). Note: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write DIER DIER TIM3 DMA/Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR TIM3 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow (for TIM2 to TIM4) and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM3 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM3 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM3 capture/compare mode register 1 CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM3 capture/compare mode register 2 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM3 capture/compare mode register 2 CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM3 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM3 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value 0 16 read-write 0 65535 CNT_ALTERNATE CNT_ALTERNATE TIM3 counter CNT 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value 0 31 read-write UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register 31 1 read-write PSC PSC TIM3 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). 0 16 read-write 0 65535 ARR ARR TIM3 auto-reload register 0x2C 0x20 0xFFFFFFFF 0xFFFFFFFF ARR Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 25.3.1: Time-base unit on page 786 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 32 read-write 0 65535 DCR DCR TIM3 DMA control register 0x48 0x10 0x00000000 0x0000FFFF DBA DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ... 8 5 read-write 0 18 DMAR DMAR TIM3 DMA address for full transfer 0x4C 0x10 0x00000000 0x0000FFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 16 read-write AF1 AF1 TIM3 alternate function option register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL ETR source selection These bits select the ETR input source. Others: Reserved 14 4 read-write TISEL TISEL TIM3 timer input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved 0 4 read-write TI2SEL TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved 8 4 read-write TI3SEL TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved 16 4 read-write TI4SEL TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. Others: Reserved 24 4 read-write TIM4 General-purpose-timers TIM 0x40000800 0x0 0x400 registers TIM4 TIM4 global interrupt 30 CR1 CR1 TIM4 control register 1 0x0 CR2 CR2 TIM4 control register 2 0x4 SMCR SMCR TIM4 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write TS TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 179: TIMx internal trigger connection on page 846 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/Slave mode 7 1 read-write ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 12 2 read-write ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). Note: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 15 1 read-write SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write DIER DIER TIM4 DMA/Interrupt enable register 0xC SR SR TIM4 status register 0x10 EGR EGR TIM4 event generation register 0x14 CCMR1_Input CCMR1_Input TIM4 capture/compare mode register 1 0x18 CCMR1_Output CCMR1_Output TIM4 capture/compare mode register 1 CCMR1_Input 0x18 CCMR2_Input CCMR2_Input TIM4 capture/compare mode register 2 0x1C CCMR2_Output CCMR2_Output TIM4 capture/compare mode register 2 CCMR2_Input 0x1C CCER CCER TIM4 capture/compare enable register 0x20 CNT CNT TIM4 counter 0x24 CNT_ALTERNATE CNT_ALTERNATE TIM4 counter CNT 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value 0 31 read-write UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register 31 1 read-write PSC PSC TIM4 prescaler 0x28 ARR ARR TIM4 auto-reload register 0x2C 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 DCR DCR TIM4 DMA control register 0x48 DMAR DMAR TIM4 DMA address for full transfer 0x4C AF1 AF1 TIM4 alternate function option register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL ETR source selection These bits select the ETR input source. Others: Reserved 14 4 read-write TISEL TISEL TIM4 timer input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved 0 4 read-write TI2SEL TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved 8 4 read-write TI3SEL TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved 16 4 read-write TI4SEL TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. Others: Reserved 24 4 read-write TIM5 General-purpose-timers TIM 0x40000C00 0x0 0x400 registers TIM5 TIM5 global Interrupt 50 CR1 CR1 TIM5 control register 1 0x0 CR2 CR2 TIM5 control register 2 0x4 SMCR SMCR TIM5 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write TS TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 179: TIMx internal trigger connection on page 846 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/Slave mode 7 1 read-write ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 12 2 read-write ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). Note: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 15 1 read-write SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write DIER DIER TIM5 DMA/Interrupt enable register 0xC SR SR TIM5 status register 0x10 EGR EGR TIM5 event generation register 0x14 CCMR1_Input CCMR1_Input TIM5 capture/compare mode register 1 0x18 CCMR1_Output CCMR1_Output TIM5 capture/compare mode register 1 CCMR1_Input 0x18 CCMR2_Input CCMR2_Input TIM5 capture/compare mode register 2 0x1C CCMR2_Output CCMR2_Output TIM5 capture/compare mode register 2 CCMR2_Input 0x1C CCER CCER TIM5 capture/compare enable register 0x20 CNT CNT TIM5 counter 0x24 CNT_ALTERNATE CNT_ALTERNATE TIM5 counter CNT 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value 0 31 read-write UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register 31 1 read-write PSC PSC TIM5 prescaler 0x28 ARR ARR TIM5 auto-reload register 0x2C 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 DCR DCR TIM5 DMA control register 0x48 DMAR DMAR TIM5 DMA address for full transfer 0x4C AF1 AF1 TIM5 alternate function option register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL ETR source selection These bits select the ETR input source. Others: Reserved 14 4 read-write TISEL TISEL TIM5 timer input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved 0 4 read-write TI2SEL TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved 8 4 read-write TI3SEL TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved 16 4 read-write TI4SEL TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. Others: Reserved 24 4 read-write TIM6 TIM6 address block description TIM 0x40001000 0x0 0x400 registers TIM6_DACUNDER TIM6 global and DAC1 and 2 underrun error interrupts 54 CR1 CR1 TIM6 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CR2 CR2 TIM6 control register 2 0x4 0x10 0x00000000 0x0000FFFF MMS Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER TIM6 DMA/Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 SR SR TIM6 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR TIM6 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT TIM6 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM6 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). 0 16 read-write 0 65535 ARR ARR TIM6 auto-reload register 0x2C 0x10 0x0000FFFF 0x0000FFFF ARR Prescaler value ARR is the value to be loaded into the actual auto-reload register. Refer to Section 46.3.1: Time-base unit on page 1760 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 TIM7 TIM7 address block description TIM 0x40001400 TIM7 TIM7 global interrupt 55 TIM8 Advanced-timers TIM 0x40013400 0x0 0x400 registers TIM8_BRK TIM8 Break Interrupt 43 TIM8_UP TIM8 Update Interrupt 44 TIM8_TRG_COM TIM8 Trigger and Commutation Interrupt 45 TIM8_CC TIM8 Capture Compare Interrupt 46 CR1 CR1 TIM8 control register 1 0x0 CR2 CR2 TIM8 control register 2 0x4 SMCR SMCR TIM8 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Codes above 1000: Reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write TS TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 167: TIMxTIM1 internal trigger connection on page 777 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/slave mode 7 1 read-write ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 12 2 read-write ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 15 1 read-write SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write DIER DIER TIM8 DMA/interrupt enable register 0xC SR SR TIM8 status register 0x10 EGR EGR TIM8 event generation register 0x14 CCMR1_Input CCMR1_Input TIM8 capture/compare mode register 1 0x18 CCMR1_Output CCMR1_Output TIM8 capture/compare mode register 1 CCMR1_Input 0x18 CCMR2_Input CCMR2_Input TIM8 capture/compare mode register 2 0x1C CCMR2_Output CCMR2_Output TIM8 capture/compare mode register 2 CCMR2_Input 0x1C CCER CCER TIM8 capture/compare enable register 0x20 CNT CNT TIM8 counter 0x24 PSC PSC TIM8 prescaler 0x28 ARR ARR TIM8 auto-reload register 0x2C RCR RCR TIM8 repetition counter register 0x30 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR TIM8 break and dead-time register 0x44 DCR DCR TIM8 DMA control register 0x48 DMAR DMAR TIM8 DMA address for full transfer 0x4C CCMR3_Output CCMR3_Output TIM8 capture/compare mode register 3 0x54 CCR5 CCR5 capture/compare register 0x58 CCR6 CCR6 capture/compare register 0x5C AF1 AF1 TIM8 Alternate function option register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKCMP1E BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input. COMP1 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP2E BRK COMP2 enable This bit enables the COMP2 for the timer s BRK input. COMP2 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKDF1BK2E BRK dfsdm1_break[2] enable This bit enables the dfsdm1_break[2] for the timer s BRK input. dfsdm1_break[2] output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKCMP1P BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP2P BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write ETRSEL ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 4 read-write AF2 AF2 TIM8 Alternate function option register 2 0x64 0x20 0x00000001 0xFFFFFFFF BK2INE BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer s BRK2 input. BKIN2 input is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BK2CMP1E BRK2 COMP1 enable This bit enables the COMP1 for the timer s BRK2 input. COMP1 output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BK2CMP2E BRK2 COMP2 enable This bit enables the COMP2 for the timer s BRK2 input. COMP2 output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BK2DF1BK3E BRK2 dfsdm1_break[3] enable This bit enables the dfsdm1_break[3] for the timer s BRK2 input. dfsdm1_break[3] output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BK2INP BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BK2CMP1P BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BK2CMP2P BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write TISEL TISEL TIM8 timer input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write TI2SEL selects TI2[0] to TI2[15] input Others: Reserved 8 4 read-write TI3SEL selects TI3[0] to TI3[15] input Others: Reserved 16 4 read-write TI4SEL selects TI4[0] to TI4[15] input Others: Reserved 24 4 read-write TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers CR1 CR1 TIM15 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx) 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write CR2 CR2 TIM15 control register 2 0x4 0x10 0x00000000 0x0000FFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 4 3 read-write TI1S TI1 selection 7 1 read-write 2 0x2 1-2 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 SMCR SMCR TIM15 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS= 00100 ). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write TS TS[0]: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See Table 181: TIMx Internal trigger connection on page 910 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write MSM Master/slave mode 7 1 read-write SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write DIER DIER TIM15 DMA/interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 read-write COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR TIM15 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to Section 26.6.3: TIM15 slave mode control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM15 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 5 1 read-write COMGW write Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 CCMR1_Input CCMR1_Input TIM15 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM15 capture/compare mode register 1 CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCER CCER TIM15 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM15 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register. 31 1 read-only PSC PSC TIM15 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). 0 16 read-write 0 65535 ARR ARR TIM15 auto-reload register 0x2C 0x10 0x0000FFFF 0x0000FFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 26.5.1: Time-base unit on page 862 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 RCR RCR TIM15 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. 0 8 read-write 0 255 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x10 0x00000000 0x0000FFFF CCR Capture/Compare value 0 16 read-write 0 65535 BDTR BDTR TIM15 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 26.6.9: TIM15 capture/compare enable register (TIM15_CCER) on page 918). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 26.6.9: TIM15 capture/compare enable register (TIM15_CCER) on page 918). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (Section 26.6.9: TIM15 capture/compare enable register (TIM15_CCER) on page 918). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write DCR DCR TIM15 DMA control register 0x48 0x10 0x00000000 0x0000FFFF DBA DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write DBL DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ... 8 5 read-write DMAR DMAR TIM15 DMA address for full transfer 0x4C 0x10 0x00000000 0x0000FFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 16 read-write AF1 AF1 TIM15 alternate register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKCMP1E BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input. COMP1 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP2E BRK COMP2 enable This bit enables the COMP2 for the timer s BRK input. COMP2 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKDF1BK0E BRK dfsdm1_break[0] enable This bit enables the dfsdm1_break[0] for the timer s BRK input. dfsdm1_break[0] output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKCMP1P BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP2P BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write TISEL TISEL TIM15 input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL selects TI1[0] to TI1[15] input Other: Reserved 0 4 read-write TI2SEL selects TI2[0] to TI2[15] input Others: Reserved 8 4 read-write TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers CR1 CR1 TIM16 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write CR2 CR2 TIM16 control register 2 0x4 0x10 0x00000000 0x0000FFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 DIER DIER TIM16 DMA/interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 SR SR TIM16 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM16 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 CCMR1_Input CCMR1_Input TIM16 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 1 0x0 1-1 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CCMR1_Output CCMR1_Output TIM16 capture/compare mode register 1 CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM16 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM16 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. 31 1 read-only PSC PSC TIM16 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). 0 16 read-write 0 65535 ARR ARR TIM16 auto-reload register 0x2C 0x10 0x0000FFFF 0x0000FFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 26.5.1: Time-base unit on page 862 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 RCR RCR TIM16 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. 0 8 read-write 0 255 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 0x10 0x00000000 0x0000FFFF CCR Capture/Compare value 0 16 read-write 0 65535 BDTR BDTR TIM16 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 26.7.8: TIMx capture/compare enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 946). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 26.7.8: TIMx capture/compare enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 946). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (Section 26.7.8: TIMx capture/compare enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 946). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write DCR DCR TIM16 DMA control register 0x48 0x10 0x00000000 0x0000FFFF DBA DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write DBL DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... 8 5 read-write DMAR DMAR TIM16 DMA address for full transfer 0x4C 0x10 0x00000000 0x0000FFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 16 read-write AF1 AF1 TIM16 alternate function register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKCMP1E BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input. COMP1 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP2E BRK COMP2 enable This bit enables the COMP2 for the timer s BRK input. COMP2 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKDF1BK1E BRK dfsdm1_break[1] enable This bit enables the dfsdm1_break[1] for the timer s BRK input. dfsdm1_break[1] output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKCMP1P BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP2P BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write TISEL TISEL TIM16 input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL selects TI1[0] to TI1[15] input Other: Reserved 0 4 read-write TIM17 General purpose timers TIM 0x40014800 0x0 0x400 registers CR1 CR1 TIM17 control register 1 0x0 CR2 CR2 TIM17 control register 2 0x4 DIER DIER TIM17 DMA/interrupt enable register 0xC SR SR TIM17 status register 0x10 EGR EGR TIM17 event generation register 0x14 CCMR1_Input CCMR1_Input TIM17 capture/compare mode register 1 0x18 CCMR1_Output CCMR1_Output TIM17 capture/compare mode register 1 CCMR1_Input 0x18 CCER CCER TIM17 capture/compare enable register 0x20 CNT CNT TIM17 counter 0x24 PSC PSC TIM17 prescaler 0x28 ARR ARR TIM17 auto-reload register 0x2C RCR RCR TIM17 repetition counter register 0x30 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR TIM17 break and dead-time register 0x44 DCR DCR TIM17 DMA control register 0x48 DMAR DMAR TIM17 DMA address for full transfer 0x4C AF1 AF1 TIM17 alternate function register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKCMP1E BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input. COMP1 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP2E BRK COMP2 enable This bit enables the COMP2 for the timer s BRK input. COMP2 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKDF1BK2E BRK dfsdm1_break[2] enable This bit enables the dfsdm1_break[2] for the timer s BRK input. dfsdm1_break[2] output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKCMP1P BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP2P BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write TISEL TISEL TIM17 input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write LPTIM1 Low power timer LPTIM 0x40007C00 0x0 0x400 registers LPTIM1 LP TIM1 interrupt 65 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DOWN Counter direction change up to down 6 1 DOWNR Set Counter direction change up to down 1 UP Counter direction change down to up 5 1 UPR Set Counter direction change down to up 1 ARROK Autoreload register update OK 4 1 ARROKR Set Autoreload register update OK 1 CMPOK Compare register update OK 3 1 CMPOKR Set Compare register update OK 1 EXTTRIG External trigger edge event 2 1 EXTTRIGR Set External trigger edge event 1 ARRM Autoreload match 1 1 ARRMR Set Autoreload match 1 CMPM Compare match 0 1 CMPMR Set Compare match 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DOWNCF Direction change to down Clear Flag 6 1 DOWNCFW Clear Direction change to down Clear Flag 1 UPCF Direction change to UP Clear Flag 5 1 UPCFW Clear Direction change to up Clear Flag 1 ARROKCF Autoreload register update OK Clear Flag 4 1 ARROKCFW Clear Autoreload register update OK Clear Flag 1 CMPOKCF Compare register update OK Clear Flag 3 1 CMPOKCFW Clear Compare register update OK Clear Flag 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 EXTTRIGCFW Clear External trigger valid edge Clear Flag 1 ARRMCF Autoreload match Clear Flag 1 1 ARRMCFW Clear Autoreload match Clear Flag 1 CMPMCF compare match Clear Flag 0 1 CMPMCFW Clear Compare match Clear Flag 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 DOWNIE Direction change to down Interrupt Enable 6 1 DOWNIE Disabled DOWN interrupt disabled 0 Enabled DOWN interrupt enabled 1 UPIE Direction change to UP Interrupt Enable 5 1 UPIE Disabled UP interrupt disabled 0 Enabled UP interrupt enabled 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 ARROKIE Disabled ARROK interrupt disabled 0 Enabled ARROK interrupt enabled 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 CMPOKIE Disabled CMPOK interrupt disabled 0 Enabled CMPOK interrupt enabled 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 EXTTRIGIE Disabled EXTTRIG interrupt disabled 0 Enabled EXTTRIG interrupt enabled 1 ARRMIE Autoreload match Interrupt Enable 1 1 ARRMIE Disabled ARRM interrupt disabled 0 Enabled ARRM interrupt enabled 1 CMPMIE Compare match Interrupt Enable 0 1 CMPMIE Disabled CMPM interrupt disabled 0 Enabled CMPM interrupt enabled 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 ENC Disabled Encoder mode disabled 0 Enabled Encoder mode enabled 1 COUNTMODE counter mode enabled 23 1 COUNTMODE Internal The counter is incremented following each internal clock pulse 0 External The counter is incremented following each valid clock pulse on the LPTIM external Input1 1 PRELOAD Registers update mode 22 1 PRELOAD Immediate Registers are updated after each APB bus write access 0 EndOfPeriod Registers are updated at the end of the current LPTIM period 1 WAVPOL Waveform shape polarity 21 1 WAVPOL Positive The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 0 Negative The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 1 WAVE Waveform shape 20 1 WAVE Inactive Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit) 0 Active Activate the Set-once mode 1 TIMOUT Timeout enable 19 1 TIMOUT Disabled A trigger event arriving when the timer is already started will be ignored 0 Enabled A trigger event arriving when the timer is already started will reset and restart the counter 1 TRIGEN Trigger enable and polarity 17 2 TRIGEN SW Software trigger (counting start is initiated by software) 0 RisingEdge Rising edge is the active edge 1 FallingEdge Falling edge is the active edge 2 BothEdges Both edges are active edges 3 TRIGSEL Trigger selector 13 3 TRIGSEL Trig0 lptim_ext_trig0 0 Trig1 lptim_ext_trig1 1 Trig2 lptim_ext_trig2 2 Trig3 lptim_ext_trig3 3 Trig4 lptim_ext_trig4 4 Trig5 lptim_ext_trig5 5 Trig6 lptim_ext_trig6 6 Trig7 lptim_ext_trig7 7 PRESC Clock prescaler 9 3 PRESC Div1 /1 0 Div2 /2 1 Div4 /4 2 Div8 /8 3 Div16 /16 4 Div32 /32 5 Div64 /64 6 Div128 /128 7 TRGFLT Configurable digital filter for trigger 6 2 TRGFLT Immediate Any trigger active level change is considered as a valid trigger 0 Clocks2 Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger 1 Clocks4 Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger 2 Clocks8 Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger 3 CKFLT Configurable digital filter for external clock 3 2 CKFLT Immediate Any external clock signal level change is considered as a valid transition 0 Clocks2 External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition 1 Clocks4 External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition 2 Clocks8 External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition 3 CKPOL Clock Polarity 1 2 CKPOL RisingEdge The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active. 0 FallingEdge The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active. 1 BothEdges Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active. 2 CKSEL Clock selector 0 1 CKSEL Internal LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 0 External LPTIM is clocked by an external clock source through the LPTIM external Input1 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 CNTSTRT Timer start in continuous mode 2 1 CNTSTRTW write Start Timer start in Continuous mode 1 SNGSTRT LPTIM start in single mode 1 1 SNGSTRTW write Start LPTIM start in Single mode 1 ENABLE LPTIM Enable 0 1 ENABLE Disabled LPTIM is disabled 0 Enabled LPTIM is enabled 1 COUNTRST Counter reset 3 1 RSTARE Reset after read enable 4 1 CMP CMP Compare Register 0x14 0x20 read-write 0x00000000 CMP Compare value 0 16 0 65535 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 0 65535 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 0 65535 OR ?? 0x20 0x00000000 OR_0 Option register bit 0 0 1 OR_1 Option register bit 1 1 1 LPTIM2 0x40009400 LPTIM2 LP TIM2 interrupt 66 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 37 CR1 CR1 USART control register 1 0x0 0x20 0x00000000 0xFFFFFFFF UE USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 1 1 read-write UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1 . To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable This bit is set and cleared by software. 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not-full interrupt enable This bit is set and cleared by software. 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 OVER8 Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. 15 1 read-write OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 DEDT Driver enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 16 5 read-write 0 31 DEAT Driver enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 21 5 read-write 0 31 RTOIE Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038. 26 1 read-write RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 EOBIE End-of-block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 27 1 read-write EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00 : 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01 : 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10 : 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable This bit is set and cleared by software. 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO full interrupt enable This bit is set and cleared by software. 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 USART control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SLVEN Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 0 1 read-write SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 DIS_NSS NSS pin enable When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 3 1 read-write DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 ADDM7 7-bit address detection/4-bit address detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 LBDL LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 5 1 read-write LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 LBDIE LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 6 1 read-write LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBCL Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 8 1 read-write LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 CPHA Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 326 and Figure 327) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 9 1 read-write CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 CPOL Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 10 1 read-write CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CLKEN Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1 11 1 read-write CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 STOP Stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 LINEN LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 14 1 read-write LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 SWAP Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ABREN Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 20 1 read-write ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 ABRMOD Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 21 2 read-write ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 RTOEN Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 23 1 read-write RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ADD Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0). 24 8 read-write 0 255 CR3 CR3 USART control register 3 0x8 0x20 0x00000000 0xFFFFFFFF EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register). 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 IREN IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 1 1 read-write IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 IRLP IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 2 1 read-write IRLP Normal Normal mode 0 LowPower Low-power mode 1 HDSEL Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 NACK Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 4 1 read-write NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 SCEN Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 5 1 read-write SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 DMAR DMA enable receiver This bit is set/reset by software 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter This bit is set/reset by software 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 ONEBIT One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0). 11 1 read-write ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 OVRDIS Overrun disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA Disable on reception error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038. 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 SCARCNT Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 17 3 read-write 0 7 WUS Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 20 2 read-write WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 WUFIE Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 22 1 read-write WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 TXFTIE TXFIFO threshold interrupt enable This bit is set and cleared by software. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 TCBGTIE Transmission complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 24 1 read-write TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 RXFTCFG Receive FIFO threshold configuration Remaining combinations: Reserved 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration Remaining combinations: Reserved 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR USART baud rate register 0xC 0x20 0x00000000 0xFFFFFFFF BRR USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared. 0 16 read-write 0 65535 GTPR GTPR USART guard time and prescaler register 0x10 0x20 0x00000000 0xFFFFFFFF PSC Prescaler value 0 8 read-write 0 255 GT Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 8 8 read-write 0 255 RTOR RTOR USART receiver timeout register 0x14 0x20 0x00000000 0xFFFFFFFF RTO Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character. 0 24 read-write 0 16777215 BLEN Block length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. 24 8 read-write 0 255 RQR RQR USART request register 0x18 0x20 0x00000000 0xFFFFFFFF ABRRQ Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 0 1 write-only ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR USART interrupt and status register 0x1C 0x20 0x008000C0 0xF0FFFFFF PE Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR. 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR3 register. Note: This error is associated with the character in the USART_RDR. 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 33.5.8: Tolerance of the USART receiver to clock deviation on page 1055). Note: This error is associated with the character in the USART_RDR. 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set. 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register. 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set. 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). Note: This bit is used during single buffer transmission. 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 LBDF LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 8 1 read-only LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 CTSIF CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 RTOF Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. 11 1 read-only RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 EOBF End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 12 1 read-only EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 UDR SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 13 1 read-only UDR NoUnderrun No underrun error 0 Underrun underrun error 1 ABRE Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 14 1 read-only ABRF Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 15 1 read-only BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register. 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 19 1 read-only RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 WUF Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 20 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 22 1 read-only TXFE TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TCBGT Transmission complete before guard time flag 25 1 read-only TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFT RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101 , RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register. 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR USART interrupt flag clear register 0x20 0x20 0x00000000 0xFFFFFFFF PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register. 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TXFECF TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register. 5 1 write-only oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 TCCF Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register. 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TCBGTCF Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. 7 1 write-only oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 LBDCF LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 8 1 write-only oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 CTSCF CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 RTOCF Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 11 1 write-only oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 EOBCF End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 12 1 write-only oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 UDRCF SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038 13 1 write-only oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 CMCF Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register. 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 WUCF Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. 20 1 write-only oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 RDR RDR USART receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RDR Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 320). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR USART transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TDR Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 320). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1. 0 9 read-write 0 511 PRESC PRESC USART prescaler register 0x2C 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256. 0 4 read-write PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 USART2 0x40004400 USART2 USART2 global interrupt 38 USART3 0x40004800 USART3 USART3 global interrupt 39 UART4 0x40004C00 UART4 UART4 global Interrupt 52 UART5 0x40005000 UART5 UART5 global Interrupt 53 LPUART1 Universal synchronous asynchronous receiver transmitter USART 0x40008000 0x0 0x400 registers LPUART1 LPUART1 global interrupt 70 CR1 CR1 LPUART control register 1 0x0 0x20 0x00000000 0xFFFFFFFF UE LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from low-power mode. When this bit is set, the LPUART is able to wake up the MCU from low-power mode, provided that the LPUART clock selection is HSI or LSE in the RCC. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it on exit from low-power mode. 1 1 read-write UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word. In order to generate an idle character, the TE must not be immediately written to 1. In order to ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. Note: When TE is set there is a 1 bit-time delay before the transmission starts. 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable This bit is set and cleared by software. 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable This bit is set and cleared by software. 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the LPUART is disabled (UE = 0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the LPUART is disabled (UE = 0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wakeup method This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the LPUART is disabled (UE = 0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). This bit can only be written when the LPUART is disabled (UE = 0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 DEDT Driver enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 34.4.13: RS232 Hardware flow control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UE = 0). 16 5 read-write 0 31 DEAT Driver enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 33.5.20: RS232 Hardware flow control and RS485 Driver Enable. This bitfield can only be written when the LPUART is disabled (UE = 0). 21 5 read-write 0 31 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00 : 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01 : 1 Start bit, 9 Data bits, n Stop bit M[1:0] = 10 : 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UE = 0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable This bit is set and cleared by software. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable This bit is set and cleared by software. 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO full interrupt enable This bit is set and cleared by software. 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 LPUART control register 2 0x4 0x20 0x00000000 0xFFFFFFFF ADDM7 7-bit address detection/4-bit address detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the LPUART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 STOP STOP bits These bits are used for programming the stop bits. This bitfield can only be written when the LPUART is disabled (UE = 0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop2 2 stop bit 2 SWAP Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE = 0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the LPUART is disabled (UE = 0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the LPUART is disabled (UE = 0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE = 0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE = 0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ADD Address of the LPUART node These bits give the address of the LPUART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0). 24 8 read-write 0 255 CR3 CR3 LPUART control register 3 0x8 0x20 0x00000000 0xFFFFFFFF EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE = 1 or ORE = 1 or NE = 1 in the LPUART_ISR register). 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 HDSEL Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the LPUART is disabled (UE = 0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 DMAR DMA enable receiver This bit is set/reset by software 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter This bit is set/reset by software 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable This bit can only be written when the LPUART is disabled (UE = 0). 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable This bit can only be written when the LPUART is disabled (UE = 0) 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 OVRDIS Overrun disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data. 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA disable on reception error This bit can only be written when the LPUART is disabled (UE = 0). Note: The reception errors are: parity error, framing error or noise error. 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the LPUART is disabled (UE = 0). 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection This bit can only be written when the LPUART is disabled (UE = 0). 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 WUS Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the LPUART is disabled (UE = 0). Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation. 20 2 read-write WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 WUFIE Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation. 22 1 read-write WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 TXFTIE TXFIFO threshold interrupt enable This bit is set and cleared by software. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 RXFTCFG Receive FIFO threshold configuration Remaining combinations: Reserved. 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration Remaining combinations: Reserved. 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR LPUART baud rate register 0xC 0x20 0x00000000 0xFFFFFFFF BRR LPUART baud rate 0 20 read-write 0 1048575 RQR RQR LPUART request register 0x18 0x20 0x00000000 0xFFFFFFFF SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request Writing 1 to this bit clears the RXNE flag. This enables discarding the received data without reading it, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR LPUART interrupt and status register 0x1C 0x20 0x008000C0 0xFFFFFFFF PE Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR. 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the LPUART_CR3 register. Note: This error is associated with the character in the LPUART_RDR. 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Start bit noise detection flag This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NECF bit in the LPUART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: This error is associated with the character in the LPUART_RDR. 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the LPUART_CR1 register, or EIE = 1 in the LPUART_CR3 register. Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIE = 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME = 1), IDLE is set if the LPUART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set. 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXFNEIE = 1 in the LPUART_CR1 register. 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXFF is set. An interrupt is generated if TCIE = 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the TCCF in the LPUART_ICR register or by a write to the LPUART_TDR register. An interrupt is generated if TCIE = 1 in the LPUART_CR1 register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately. 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). An interrupt is generated if the TXFNFIE bit = 1 in the LPUART_CR1 register. Note: This bit is used during single buffer transmission. 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 CTSIF CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIE = 1 in the LPUART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIE = 1in the LPUART_CR1 register. 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wakeup from Mute mode This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. 19 1 read-only RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 WUF Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIE = 1 in the LPUART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value 20 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the LPUART_CR1 register, in order to respect the TE = 0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. 22 1 read-only TXFE TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the LPUART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the LPUART_CR1 register. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the LPUART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the LPUART_CR1 register. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 RXFT RXFIFO threshold flag This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the LPUART_CR3 register. 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the LPUART_CR3 register. 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR LPUART interrupt flag clear register 0x20 0x20 0x00000000 0xFFFFFFFF PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the LPUART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the LPUART_ISR register. 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag Writing 1 to this bit clears the NE flag in the LPUART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag Writing 1 to this bit clears the ORE flag in the LPUART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TCCF Transmission complete clear flag Writing 1 to this bit clears the TC flag in the LPUART_ISR register. 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 CTSCF CTS clear flag Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register. 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 CMCF Character match clear flag Writing 1 to this bit clears the CMF flag in the LPUART_ISR register. 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 WUCF Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the LPUART_ISR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation. 20 1 write-only oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 RDR RDR LPUART receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RDR Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 347). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR LPUART transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TDR Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 347). When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1. 0 9 read-write 0 511 PRESC PRESC LPUART prescaler register 0x2C 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler The LPUART input clock can be divided by a prescaler: Remaining combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256. 0 4 read-write PRESCALER Div1 /1 0 Div2 /2 1 Div4 /4 2 Div6 /6 3 Div8 /8 4 Div10 /10 5 Div12 /12 6 Div16 /16 7 Div32 /32 8 Div64 /64 9 Div128 /128 10 Div256 /256 11 SPI1 Serial peripheral interface/Inter-IC sound SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 CRCL CRC length 11 1 CRCL EightBit 8-bit CRC length 0 SixteenBit 16-bit CRC length 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 NSSP NSS pulse management 3 1 NSSP NoPulse No NSS pulse 0 PulseGenerated NSS pulse generated 1 FRF Frame format 4 1 FRF Motorola SPI Motorola mode 0 TI SPI TI mode 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 DS Data size 8 4 DS FourBit 4-bit 3 FiveBit 5-bit 4 SixBit 6-bit 5 SevenBit 7-bit 6 EightBit 8-bit 7 NineBit 9-bit 8 TenBit 10-bit 9 ElevenBit 11-bit 10 TwelveBit 12-bit 11 ThirteenBit 13-bit 12 FourteenBit 14-bit 13 FifteenBit 15-bit 14 SixteenBit 16-bit 15 FRXTH FIFO reception threshold 12 1 FRXTH Half RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 0 Quarter RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_RX Even Number of data to transfer for receive is even 0 Odd Number of data to transfer for receive is odd 1 LDMA_TX Last DMA transfer for transmission 14 1 LDMA_TX Even Number of data to transfer for transmit is even 0 Odd Number of data to transfer for transmit is odd 1 SR SR status register 0x8 0x10 0x00000002 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 FRE Frame format error 8 1 read-only FRER NoError No frame format error 0 Error A frame format error occurred 1 FRLVL FIFO reception level 9 2 read-only FRLVLR Empty Rx FIFO Empty 0 Quarter Rx 1/4 FIFO 1 Half Rx 1/2 FIFO 2 Full Rx FIFO full 3 FTLVL FIFO transmission level 11 2 read-only FTLVLR Empty Tx FIFO Empty 0 Quarter Tx 1/4 FIFO 1 Half Tx 1/2 FIFO 2 Full Tx FIFO full 3 DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 SPI2 0x40003800 SPI2 SPI2 global interrupt 36 SPI3 0x40003C00 SPI3 SPI3 global Interrupt 51 SDMMC1 Secure digital input/output interface 1 SDIO 0x50062400 0x0 0x400 registers SDMMC1 SDMMC1 global Interrupt 49 POWER POWER power control register 0x0 0x20 read-write 0x00000000 PWRCTRL SDMMC state control bits 0 2 VSWITCH Voltage switch sequence start 2 1 VSWITCHEN Voltage switch procedure enable 3 1 DIRPOL Data and command direction signals polarity selection 4 1 CLKCR CLKCR SDI clock control register 0x4 0x20 read-write 0x00000000 SELCLKRX Receive clock selection 20 2 BUSSPEED Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50 19 1 DDR Data rate signaling selection 18 1 HWFC_EN Hardware flow control enable 17 1 NEGEDGE SDMMC_CK dephasing selection bit for data and command 16 1 WIDBUS Wide bus mode enable bit 14 2 PWRSAV Power saving configuration bit 12 1 CLKDIV Clock divide factor 0 10 ARGR ARGR argument register 0x8 0x20 read-write 0x00000000 CMDARG Command argument 0 32 CMDR CMDR command register 0xC 0x20 read-write 0x00000000 CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end 16 1 BOOTEN Enable boot mode procedure 15 1 BOOTMODE Select the boot mode procedure to be used 14 1 DTHOLD Hold new data block transmission and reception in the DPSM 13 1 CPSMEN Command path state machine (CPSM) Enable bit 12 1 WAITPEND CPSM Waits for ends of data transfer (CmdPend internal signal) 11 1 WAITINT CPSM waits for interrupt request 10 1 WAITRESP Wait for response bits 8 2 CMDSTOP The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM 7 1 CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM 6 1 CMDINDEX Command index 0 6 RESPCMDR RESPCMDR command response register 0x10 0x20 read-only 0x00000000 RESPCMD Response command index 0 6 4 0x4 1-4 RESP%sR RESP%sR SDMMC response %s register 0x14 0x20 read-only 0x00000000 CARDSTATUS Status of a card, which is part of the received response 0 32 DTIMER DTIMER data timer register 0x24 0x20 read-write 0x00000000 DATATIME Data timeout period 0 32 DLENR DLENR data length register 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value 0 25 DCTRL DCTRL data control register 0x2C 0x20 read-write 0x00000000 FIFORST FIFO reset, will flush any remaining data 13 1 BOOTACKEN Enable the reception of the boot acknowledgment 12 1 SDIOEN SD I/O enable functions 11 1 RWMOD Read wait mode 10 1 RWSTOP Read wait stop 9 1 RWSTART Read wait start 8 1 DBLOCKSIZE Data block size 4 4 DTMODE Data transfer mode selection 1: Stream or SDIO multibyte data transfer 2 2 DTDIR Data transfer direction selection 1 1 DTEN DTEN 0 1 DCNTR DCNTR data counter register 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value 0 25 STAR STAR status register 0x34 0x20 read-only 0x00000000 IDMABTC IDMA buffer transfer complete 28 1 IDMATE IDMA transfer error 27 1 CKSTOP SDMMC_CK stopped in Voltage switch procedure 26 1 VSWEND Voltage switch critical timing section completion 25 1 ACKTIMEOUT Boot acknowledgment timeout 24 1 ACKFAIL Boot acknowledgment received (boot acknowledgment check fail) 23 1 SDIOIT SDIO interrupt received 22 1 BUSYD0END end of SDMMC_D0 Busy following a CMD response detected 21 1 BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response 20 1 RXFIFOE Receive FIFO empty 19 1 TXFIFOE Transmit FIFO empty 18 1 RXFIFOF Receive FIFO full 17 1 TXFIFOF Transmit FIFO full 16 1 RXFIFOHF Receive FIFO half full: there are at least 8 words in the FIFO 15 1 TXFIFOHE Transmit FIFO half empty: at least 8 words can be written into the FIFO 14 1 CPSMACT Command path state machine active, i.e. not in Idle state 13 1 DPSMACT Data path state machine active, i.e. not in Idle state 12 1 DABORT Data transfer aborted by CMD12 11 1 DBCKEND Data block sent/received 10 1 DHOLD Data transfer Hold 9 1 DATAEND Data end (data counter, SDIDCOUNT, is zero) 8 1 CMDSENT Command sent (no response required) 7 1 CMDREND Command response received (CRC check passed) 6 1 RXOVERR Received FIFO overrun error 5 1 TXUNDERR Transmit FIFO underrun error 4 1 DTIMEOUT Data timeout 3 1 CTIMEOUT Command response timeout 2 1 DCRCFAIL Data block sent/received (CRC check failed) 1 1 CCRCFAIL Command response received (CRC check failed) 0 1 ICR ICR interrupt clear register 0x38 0x20 read-write 0x00000000 IDMABTCC IDMA buffer transfer complete clear bit 28 1 IDMATEC IDMA transfer error clear bit 27 1 CKSTOPC CKSTOP flag clear bit 26 1 VSWENDC VSWEND flag clear bit 25 1 ACKTIMEOUTC ACKTIMEOUT flag clear bit 24 1 ACKFAILC ACKFAIL flag clear bit 23 1 SDIOITC SDIOIT flag clear bit 22 1 BUSYD0ENDC BUSYD0END flag clear bit 21 1 DABORTC DABORT flag clear bit 11 1 DBCKENDC DBCKEND flag clear bit 10 1 DHOLDC DHOLD flag clear bit 9 1 DATAENDC DATAEND flag clear bit 8 1 CMDSENTC CMDSENT flag clear bit 7 1 CMDRENDC CMDREND flag clear bit 6 1 RXOVERRC RXOVERR flag clear bit 5 1 TXUNDERRC TXUNDERR flag clear bit 4 1 DTIMEOUTC DTIMEOUT flag clear bit 3 1 CTIMEOUTC CTIMEOUT flag clear bit 2 1 DCRCFAILC DCRCFAIL flag clear bit 1 1 CCRCFAILC CCRCFAIL flag clear bit 0 1 MASKR MASKR mask register 0x3C 0x20 read-write 0x00000000 IDMABTCIE IDMABTCIE 28 1 CKSTOPIE CKSTOPIE 26 1 VSWENDIE Voltage switch critical timing section completion interrupt enable 25 1 ACKTIMEOUTIE Acknowledgment timeout interrupt enable 24 1 ACKFAILIE Acknowledgment Fail interrupt enable 23 1 SDIOITIE SDIO mode interrupt received interrupt enable 22 1 BUSYD0ENDIE BUSYD0END interrupt enable 21 1 TXFIFOEIE Tx FIFO empty interrupt enable 18 1 RXFIFOFIE Rx FIFO full interrupt enable 17 1 RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 DABORTIE Data transfer aborted interrupt enable 11 1 DBCKENDIE Data block end interrupt enable 10 1 DHOLDIE Data hold interrupt enable 9 1 DATAENDIE Data end interrupt enable 8 1 CMDSENTIE Command sent interrupt enable 7 1 CMDRENDIE Command response received interrupt enable 6 1 RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 DTIMEOUTIE Data timeout interrupt enable 3 1 CTIMEOUTIE Command timeout interrupt enable 2 1 DCRCFAILIE Data CRC fail interrupt enable 1 1 CCRCFAILIE Command CRC fail interrupt enable 0 1 ACKTIMER ACKTIMER acknowledgment timer register 0x40 0x20 read-write 0x00000000 ACKTIME Boot acknowledgment timeout period 0 25 16 0x4 0-15 FIFOR%s FIFOR%s data FIFO register %s 0x80 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 IDMACTRLR IDMACTRLR DMA control register 0x50 0x20 read-write 0x00000000 IDMAEN IDMA enable 0 1 IDMABMODE Buffer mode selection 1 1 IDMABACT Double buffer mode active buffer indication 2 1 IDMABSIZER IDMABSIZER IDMA buffer size register 0x54 0x20 read-write 0x00000000 IDMABNDT Number of bytes per buffer 5 8 IDMABASE0R IDMABASE0R IDMA buffer 0 base address register 0x58 0x20 read-write 0x00000000 IDMABASE0 Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only) 0 32 IDMABASE1R IDMABASE1R IDMA buffer 0 base address register 0x5C 0x20 read-write 0x00000000 IDMABASE1 Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only) 0 32 SDMMC2 Secure digital input/output interface 2 SDIO 0x50062800 SDMMC2 SDMMC2 global Interrupt 47 EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers PVD_PVM PVD through EXTI line detection 1 EXTI0 EXTI Line 0 interrupt 6 EXTI1 EXTI Line 1 interrupt 7 EXTI2 EXTI Line 2 interrupt 8 EXTI3 EXTI Line 3 interrupt 9 EXTI4 EXTI Line 4 interrupt 10 EXTI9_5 EXTI Line5 to Line9 interrupts 23 EXTI15_10 EXTI Lines 10 to 15 interrupts 40 IMR1 IMR1 Interrupt mask register 0x0 0x20 read-write 0xFF820000 MR0 Interrupt Mask on line 0 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 MR1 Interrupt Mask on line 1 1 1 MR2 Interrupt Mask on line 2 2 1 MR3 Interrupt Mask on line 3 3 1 MR4 Interrupt Mask on line 4 4 1 MR5 Interrupt Mask on line 5 5 1 MR6 Interrupt Mask on line 6 6 1 MR7 Interrupt Mask on line 7 7 1 MR8 Interrupt Mask on line 8 8 1 MR9 Interrupt Mask on line 9 9 1 MR10 Interrupt Mask on line 10 10 1 MR11 Interrupt Mask on line 11 11 1 MR12 Interrupt Mask on line 12 12 1 MR13 Interrupt Mask on line 13 13 1 MR14 Interrupt Mask on line 14 14 1 MR15 Interrupt Mask on line 15 15 1 MR16 Interrupt Mask on line 16 16 1 MR17 Interrupt Mask on line 17 17 1 MR18 Interrupt Mask on line 18 18 1 MR19 Interrupt Mask on line 19 19 1 MR20 Interrupt Mask on line 20 20 1 MR21 Interrupt Mask on line 21 21 1 MR22 Interrupt Mask on line 22 22 1 MR23 Interrupt Mask on line 23 23 1 MR24 Interrupt Mask on line 24 24 1 MR25 Interrupt Mask on line 25 25 1 MR26 Interrupt Mask on line 26 26 1 MR27 Interrupt Mask on line 27 27 1 MR28 Interrupt Mask on line 28 28 1 MR29 Interrupt Mask on line 29 29 1 MR30 Interrupt Mask on line 30 30 1 MR31 Interrupt Mask on line 31 31 1 EMR1 EMR1 Event mask register 0x4 0x20 read-write 0x00000000 MR0 Event Mask on line 0 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 MR1 Event Mask on line 1 1 1 MR2 Event Mask on line 2 2 1 MR3 Event Mask on line 3 3 1 MR4 Event Mask on line 4 4 1 MR5 Event Mask on line 5 5 1 MR6 Event Mask on line 6 6 1 MR7 Event Mask on line 7 7 1 MR8 Event Mask on line 8 8 1 MR9 Event Mask on line 9 9 1 MR10 Event Mask on line 10 10 1 MR11 Event Mask on line 11 11 1 MR12 Event Mask on line 12 12 1 MR13 Event Mask on line 13 13 1 MR14 Event Mask on line 14 14 1 MR15 Event Mask on line 15 15 1 MR16 Event Mask on line 16 16 1 MR17 Event Mask on line 17 17 1 MR18 Event Mask on line 18 18 1 MR19 Event Mask on line 19 19 1 MR20 Event Mask on line 20 20 1 MR21 Event Mask on line 21 21 1 MR22 Event Mask on line 22 22 1 MR23 Event Mask on line 23 23 1 MR24 Event Mask on line 24 24 1 MR25 Event Mask on line 25 25 1 MR26 Event Mask on line 26 26 1 MR27 Event Mask on line 27 27 1 MR28 Event Mask on line 28 28 1 MR29 Event Mask on line 29 29 1 MR30 Event Mask on line 30 30 1 MR31 Event Mask on line 31 31 1 RTSR1 RTSR1 Rising Trigger selection register 0x8 0x20 read-write 0x00000000 TR0 Rising trigger event configuration of line 0 0 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 TR1 Rising trigger event configuration of line 1 1 1 TR2 Rising trigger event configuration of line 2 2 1 TR3 Rising trigger event configuration of line 3 3 1 TR4 Rising trigger event configuration of line 4 4 1 TR5 Rising trigger event configuration of line 5 5 1 TR6 Rising trigger event configuration of line 6 6 1 TR7 Rising trigger event configuration of line 7 7 1 TR8 Rising trigger event configuration of line 8 8 1 TR9 Rising trigger event configuration of line 9 9 1 TR10 Rising trigger event configuration of line 10 10 1 TR11 Rising trigger event configuration of line 11 11 1 TR12 Rising trigger event configuration of line 12 12 1 TR13 Rising trigger event configuration of line 13 13 1 TR14 Rising trigger event configuration of line 14 14 1 TR15 Rising trigger event configuration of line 15 15 1 TR16 Rising trigger event configuration of line 16 16 1 TR18 Rising trigger event configuration of line 18 18 1 TR19 Rising trigger event configuration of line 19 19 1 TR20 Rising trigger event configuration of line 20 20 1 TR21 Rising trigger event configuration of line 21 21 1 TR22 Rising trigger event configuration of line 22 22 1 FTSR1 FTSR1 Falling Trigger selection register 0xC 0x20 read-write 0x00000000 TR0 Falling trigger event configuration of line 0 0 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 TR1 Falling trigger event configuration of line 1 1 1 TR2 Falling trigger event configuration of line 2 2 1 TR3 Falling trigger event configuration of line 3 3 1 TR4 Falling trigger event configuration of line 4 4 1 TR5 Falling trigger event configuration of line 5 5 1 TR6 Falling trigger event configuration of line 6 6 1 TR7 Falling trigger event configuration of line 7 7 1 TR8 Falling trigger event configuration of line 8 8 1 TR9 Falling trigger event configuration of line 9 9 1 TR10 Falling trigger event configuration of line 10 10 1 TR11 Falling trigger event configuration of line 11 11 1 TR12 Falling trigger event configuration of line 12 12 1 TR13 Falling trigger event configuration of line 13 13 1 TR14 Falling trigger event configuration of line 14 14 1 TR15 Falling trigger event configuration of line 15 15 1 TR16 Falling trigger event configuration of line 16 16 1 TR18 Falling trigger event configuration of line 18 18 1 TR19 Falling trigger event configuration of line 19 19 1 TR20 Falling trigger event configuration of line 20 20 1 TR21 Falling trigger event configuration of line 21 21 1 TR22 Falling trigger event configuration of line 22 22 1 SWIER1 SWIER1 Software interrupt event register 0x10 0x20 read-write 0x00000000 SWIER0 Software Interrupt on line 0 0 1 SoftwareInterrupt write Pend Generates an interrupt request 1 SWIER1 Software Interrupt on line 1 1 1 SWIER2 Software Interrupt on line 2 2 1 SWIER3 Software Interrupt on line 3 3 1 SWIER4 Software Interrupt on line 4 4 1 SWIER5 Software Interrupt on line 5 5 1 SWIER6 Software Interrupt on line 6 6 1 SWIER7 Software Interrupt on line 7 7 1 SWIER8 Software Interrupt on line 8 8 1 SWIER9 Software Interrupt on line 9 9 1 SWIER10 Software Interrupt on line 10 10 1 SWIER11 Software Interrupt on line 11 11 1 SWIER12 Software Interrupt on line 12 12 1 SWIER13 Software Interrupt on line 13 13 1 SWIER14 Software Interrupt on line 14 14 1 SWIER15 Software Interrupt on line 15 15 1 SWIER16 Software Interrupt on line 16 16 1 SWIER18 Software Interrupt on line 18 18 1 SWIER19 Software Interrupt on line 19 19 1 SWIER20 Software Interrupt on line 20 20 1 SWIER21 Software Interrupt on line 21 21 1 SWIER22 Software Interrupt on line 22 22 1 PR1 PR1 Pending register 0x14 0x20 read-write 0x00000000 PR0 Pending bit 0 0 1 oneToClear PR0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PR0W write Clear Clears pending bit 1 PR1 Pending bit 1 1 1 oneToClear read write PR2 Pending bit 2 2 1 oneToClear read write PR3 Pending bit 3 3 1 oneToClear read write PR4 Pending bit 4 4 1 oneToClear read write PR5 Pending bit 5 5 1 oneToClear read write PR6 Pending bit 6 6 1 oneToClear read write PR7 Pending bit 7 7 1 oneToClear read write PR8 Pending bit 8 8 1 oneToClear read write PR9 Pending bit 9 9 1 oneToClear read write PR10 Pending bit 10 10 1 oneToClear read write PR11 Pending bit 11 11 1 oneToClear read write PR12 Pending bit 12 12 1 oneToClear read write PR13 Pending bit 13 13 1 oneToClear read write PR14 Pending bit 14 14 1 oneToClear read write PR15 Pending bit 15 15 1 oneToClear read write PR16 Pending bit 16 16 1 oneToClear read write PR18 Pending bit 18 18 1 oneToClear read write PR19 Pending bit 19 19 1 oneToClear read write PR20 Pending bit 20 20 1 oneToClear read write PR21 Pending bit 21 21 1 oneToClear read write PR22 Pending bit 22 22 1 oneToClear read write IMR2 IMR2 Interrupt mask register 0x20 0x20 read-write 0xFFFFFF87 MR32 Interrupt Mask on external/internal line 32 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 MR33 Interrupt Mask on external/internal line 33 1 1 MR34 Interrupt Mask on external/internal line 34 2 1 MR35 Interrupt Mask on external/internal line 35 3 1 MR36 Interrupt Mask on external/internal line 36 4 1 MR37 Interrupt Mask on external/internal line 37 5 1 MR38 Interrupt Mask on external/internal line 38 6 1 MR39 Interrupt Mask on external/internal line 39 7 1 MR40 Interrupt Mask on external/internal line 40 8 1 EMR2 EMR2 Event mask register 0x24 0x20 read-write 0x00000000 MR32 Event mask on external/internal line 32 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 MR33 Event mask on external/internal line 33 1 1 MR34 Event mask on external/internal line 34 2 1 MR35 Event mask on external/internal line 35 3 1 MR36 Event mask on external/internal line 36 4 1 MR37 Event mask on external/internal line 37 5 1 MR38 Event mask on external/internal line 38 6 1 MR39 Event mask on external/internal line 39 7 1 MR40 Event mask on external/internal line 40 8 1 RTSR2 RTSR2 Rising Trigger selection register 0x28 0x20 read-write 0x00000000 RT35 Rising trigger event configuration bit of line 35 3 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT36 Rising trigger event configuration bit of line 36 4 1 RT37 Rising trigger event configuration bit of line 37 5 1 RT38 Rising trigger event configuration bit of line 38 6 1 FTSR2 FTSR2 Falling Trigger selection register 0x2C 0x20 read-write 0x00000000 FT35 Falling trigger event configuration bit of line 35 3 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT36 Falling trigger event configuration bit of line 36 4 1 FT37 Falling trigger event configuration bit of line 37 5 1 FT38 Falling trigger event configuration bit of line 38 6 1 SWIER2 SWIER2 Software interrupt event register 0x30 0x20 read-write 0x00000000 SWI35 Software interrupt on line 35 3 1 SoftwareInterrupt write Pend Generates an interrupt request 1 SWI36 Software interrupt on line 36 4 1 SWI37 Software interrupt on line 37 5 1 SWI38 Software interrupt on line 38 6 1 PR2 PR2 Pending register 0x34 0x20 read-write 0x00000000 PIF35 Pending interrupt flag on line 35 3 1 oneToClear PIF35R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PIF35W write Clear Clears pending bit 1 PIF36 Pending interrupt flag on line 36 4 1 oneToClear read write PIF37 Pending interrupt flag on line 37 5 1 oneToClear read write PIF38 Pending interrupt flag on line 38 6 1 oneToClear read write VREFBUF Voltage reference buffer VREF 0x40010030 0x0 0x1D0 registers CSR CSR VREF control and status register 0x0 0x20 0x00000002 ENVR Voltage reference buffer enable 0 1 read-write HIZ High impedance mode 1 1 read-write VRS Voltage reference scale 2 1 read-write VRR Voltage reference buffer ready 3 1 read-only CCR CCR calibration control register 0x4 0x20 read-write 0x00000000 TRIM Trimming code 0 6 CAN1 Controller area network CAN 0x40006400 0x0 0x400 registers CAN1_TX CAN1 TX interrupts 19 CAN1_RX0 CAN1 RX0 interrupts 20 CAN1_RX1 CAN1 RX1 interrupts 21 CAN1_SCE CAN1 SCE interrupt 22 MCR MCR master control register 0x0 0x20 read-write 0x00010002 DBF DBF 16 1 RESET RESET 15 1 TTCM TTCM 7 1 ABOM ABOM 6 1 AWUM AWUM 5 1 NART NART 4 1 RFLM RFLM 3 1 TXFP TXFP 2 1 SLEEP SLEEP 1 1 INRQ INRQ 0 1 MSR MSR master status register 0x4 0x20 0x00000C02 RX RX 11 1 read-only SAMP SAMP 10 1 read-only RXM RXM 9 1 read-only TXM TXM 8 1 read-only SLAKI SLAKI 4 1 read-write WKUI WKUI 3 1 read-write ERRI ERRI 2 1 read-write SLAK SLAK 1 1 read-only INAK INAK 0 1 read-only TSR TSR transmit status register 0x8 0x20 0x1C000000 3 0x1 0-2 LOW%s Lowest priority flag for mailbox %s 29 1 read-only 3 0x1 0-2 TME%s Lowest priority flag for mailbox %s 26 1 read-only CODE CODE 24 2 read-only 3 0x8 0-2 ABRQ%s ABRQ%s 7 1 read-write 3 0x8 0-2 TERR%s TERR%s 3 1 read-write 3 0x8 0-2 ALST%s ALST%s 2 1 read-write 3 0x8 0-2 TXOK%s TXOK%s 1 1 read-write 3 0x8 0-2 RQCP%s RQCP%s 0 1 read-write 2 0x4 0-1 RF%sR RF%sR receive FIFO %s register 0xC 0x20 0x00000000 RFOM RFOM0 5 1 read-write RFOM0W write Release Set by software to release the output mailbox of the FIFO 1 FOVR FOVR0 4 1 read-write FOVR0R read NoOverrun No FIFO x overrun 0 Overrun FIFO x overrun 1 FOVR0W write Clear Clear flag 1 FULL FULL0 3 1 read-write FULL0R read NotFull FIFO x is not full 0 Full FIFO x is full 1 FULL0W write Clear Clear flag 1 FMP FMP0 0 2 read-only IER IER interrupt enable register 0x14 0x20 read-write 0x00000000 SLKIE SLKIE 17 1 SLKIE Disabled No interrupt when SLAKI bit is set 0 Enabled Interrupt generated when SLAKI bit is set 1 WKUIE WKUIE 16 1 WKUIE Disabled No interrupt when WKUI is set 0 Enabled Interrupt generated when WKUI bit is set 1 ERRIE ERRIE 15 1 ERRIE Disabled No interrupt will be generated when an error condition is pending in the CAN_ESR 0 Enabled An interrupt will be generation when an error condition is pending in the CAN_ESR 1 LECIE LECIE 11 1 LECIE Disabled ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection 0 Enabled ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection 1 BOFIE BOFIE 10 1 BOFIE Disabled ERRI bit will not be set when BOFF is set 0 Enabled ERRI bit will be set when BOFF is set 1 EPVIE EPVIE 9 1 EPVIE Disabled ERRI bit will not be set when EPVF is set 0 Enabled ERRI bit will be set when EPVF is set 1 EWGIE EWGIE 8 1 EWGIE Disabled ERRI bit will not be set when EWGF is set 0 Enabled ERRI bit will be set when EWGF is set 1 FOVIE1 FOVIE1 6 1 FOVIE1 Disabled No interrupt when FOVR is set 0 Enabled Interrupt generation when FOVR is set 1 FFIE1 FFIE1 5 1 FFIE1 Disabled No interrupt when FULL bit is set 0 Enabled Interrupt generated when FULL bit is set 1 FMPIE1 FMPIE1 4 1 FMPIE1 Disabled No interrupt generated when state of FMP[1:0] bits are not 00b 0 Enabled Interrupt generated when state of FMP[1:0] bits are not 00b 1 FOVIE0 FOVIE0 3 1 FOVIE0 Disabled No interrupt when FOVR bit is set 0 Enabled Interrupt generated when FOVR bit is set 1 FFIE0 FFIE0 2 1 FFIE0 Disabled No interrupt when FULL bit is set 0 Enabled Interrupt generated when FULL bit is set 1 FMPIE0 FMPIE0 1 1 FMPIE0 Disabled No interrupt generated when state of FMP[1:0] bits are not 00 0 Enabled Interrupt generated when state of FMP[1:0] bits are not 00b 1 TMEIE TMEIE 0 1 TMEIE Disabled No interrupt when RQCPx bit is set 0 Enabled Interrupt generated when RQCPx bit is set 1 ESR ESR interrupt enable register 0x18 0x20 0x00000000 REC REC 24 8 read-only TEC TEC 16 8 read-only LEC LEC 4 3 read-write LEC NoError No Error 0 Stuff Stuff Error 1 Form Form Error 2 Ack Acknowledgment Error 3 BitRecessive Bit recessive Error 4 BitDominant Bit dominant Error 5 Crc CRC Error 6 Custom Set by software 7 BOFF BOFF 2 1 read-only EPVF EPVF 1 1 read-only EWGF EWGF 0 1 read-only BTR BTR bit timing register 0x1C 0x20 read-write 0x00000000 SILM SILM 31 1 SILM Normal Normal operation 0 Silent Silent Mode 1 LBKM LBKM 30 1 LBKM Disabled Loop Back Mode disabled 0 Enabled Loop Back Mode enabled 1 SJW SJW 24 2 TS2 TS2 20 3 TS1 TS1 16 4 BRP BRP 0 10 3 0x10 0-2 TX%s CAN Transmit cluster 0x180 TIR TI0R TX mailbox identifier register 0x0 0x20 read-write 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 IDE Standard Standard identifier 0 Extended Extended identifier 1 RTR RTR 1 1 RTR Data Data frame 0 Remote Remote frame 1 TXRQ TXRQ 0 1 TDTR TDT0R mailbox data length control and time stamp register 0x4 0x20 read-write 0x00000000 TIME TIME 16 16 TGT TGT 8 1 DLC DLC 0 4 0 8 TDLR TDL0R mailbox data low register 0x8 0x20 read-write 0x00000000 4 0x8 0-3 DATA%s DATA%s 0 8 TDHR TDH0R mailbox data high register 0xC 0x20 read-write 0x00000000 4 0x8 4-7 DATA%s DATA%s 0 8 2 0x10 0-1 RX%s CAN Receive cluster 0x1B0 RIR RI0R receive FIFO mailbox identifier register 0x0 0x20 read-only 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 IDE Standard Standard identifier 0 Extended Extended identifier 1 RTR RTR 1 1 RTR Data Data frame 0 Remote Remote frame 1 RDTR RDT0R mailbox data high register 0x4 0x20 read-only 0x00000000 TIME TIME 16 16 FMI FMI 8 8 DLC DLC 0 4 0 8 RDLR RDL0R mailbox data high register 0x8 0x20 read-only 0x00000000 4 0x8 0-3 DATA%s DATA%s 0 8 RDHR RDH0R receive FIFO mailbox data high register 0xC 0x20 read-only 0x00000000 4 0x8 4-7 DATA%s DATA%s 0 8 FMR FMR filter master register 0x200 0x20 read-write 0x2A1C0E01 FINIT Filter initialization mode 0 1 CANSB CAN start bank 8 6 FM1R FM1R filter mode register 0x204 0x20 read-write 0x00000000 28 0x1 0-27 FBM%s Filter mode 0 1 FS1R FS1R filter scale register 0x20C 0x20 read-write 0x00000000 28 0x1 0-27 FSC%s Filter scale configuration 0 1 FFA1R FFA1R filter FIFO assignment register 0x214 0x20 read-write 0x00000000 28 0x1 0-27 FFA%s Filter FIFO assignment for filter %s 0 1 FA1R FA1R filter activation register 0x21C 0x20 read-write 0x00000000 28 0x1 0-27 FACT%s Filter active 0 1 28 0x8 0-27 FB%s CAN Filter Bank cluster 0x240 FR1 F0R1 Filter bank x register 1 0x0 0x20 read-write 0x00000000 FB Filter bits 0 32 FR2 F0R2 Filter bank x register 2 0x4 0x20 read-write 0x00000000 FB Filter bits 0 32 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC_TAMP_STAMP_CSS_LSE RTC Tamper or TimeStamp /CSS on LSE through EXTI line 19 interrupts 2 RTC_WKUP RTC Wakeup timer through EXTI line 20 interrupt 3 RTC_ALARM RTC alarms through EXTI line 18 interrupts 41 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 0 15 YU Year units in BCD format 16 4 0 15 WDU Week day units 13 3 1 7 MT Month tens in BCD format 12 1 0 1 MU Month units in BCD format 8 4 0 15 DT Date tens in BCD format 4 2 0 3 DU Date units in BCD format 0 4 0 15 SSR SSR sub second register 0x8 0x20 read-only 0x00000000 SS Synchronous binary counter 0 32 0 65535 ICSR ICSR initialization control and status register 0xC 0x20 0x00000007 WUTWF Wakeup timer write flag 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 BIN Binary mode 8 2 read-write BCDU BCD update 10 3 read-write RECALPF Recalibration pending Flag 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 0 127 PREDIV_S Synchronous prescaler factor 0 15 0 32767 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 0 65535 CR CR control register 0x18 0x20 read-write 0x00000000 WUCKSEL Wakeup clock selection 0 3 WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE Time-stamp event active edge 3 1 TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON Reference clock detection enable (50 or 60 Hz) 4 1 REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD Bypass the shadow registers 5 1 BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT Hour format 6 1 FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 SSRUIE SSR underflow interrupt enable 7 1 ALRAE Alarm A enable 8 1 ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 ALRBE Alarm B enable 9 1 WUTE Wakeup timer enable 10 1 WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE Time stamp enable 11 1 TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 ALRAIE Alarm A interrupt enable 12 1 ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 ALRBIE Alarm B interrupt enable 13 1 WUTIE Wakeup timer interrupt enable 14 1 WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE Time-stamp interrupt enable 15 1 TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H Add 1 hour (summer time change) 16 1 ADD1HW write Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H Subtract 1 hour (winter time change) 17 1 SUB1HW write Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP Backup 18 1 BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 COSEL Calibration output selection 19 1 COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL Output polarity 20 1 POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL Output selection 21 2 OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE Calibration output enable 23 1 COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ITSE timestamp on internal event enable 24 1 ITSE Disabled Internal event timestamp disabled 0 Enabled Internal event timestamp enabled 1 TAMPTS Activate timestamp on tamper detection event 25 1 TAMPTS Disabled Tamper detection event does not cause a RTC timestamp to be saved 0 Enabled Save RTC timestamp on tamper detection event 1 TAMPOE Tamper detection output enable on TAMPALRM 26 1 TAMPOE Disabled The tamper flag is not routed on TAMPALRM 0 Enabled The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL 1 TAMPALRM_PU TAMPALRM pull-up enable 29 1 TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPALRM_TYPE TAMPALRM output type 30 1 TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 OUT2EN RTC_OUT2 output enable 31 1 OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR calibration register 0x28 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW8 EightSeconds When CALW8 is set to â1â, the 8-second calibration cycle period is selected 1 CALW16 Use a 16-second calibration cycle period 13 1 CALW16 SixteenSeconds When CALW16 is set to â1â, the 16-second calibration cycle period is selected.This bit must not be set to â1â if CALW8=1 1 LPCAL Calibration low-power mode 12 1 CALM Calibration minus 0 9 0 511 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 SUBFS Subtract a fraction of a second 0 15 0 32767 TSTR TSTR time stamp time register 0x30 TSDR TSDR time stamp date register 0x34 TSSSR TSSSR timestamp sub second register 0x38 ALRMAR ALRMAR Alarm register 0x40 0x20 read-write 0x00000000 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day donât care in Alarm comparison 1 MSK4 Alarm date mask 31 1 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is donât care. 1 DT Date tens in BCD format 28 2 0 3 DU Date units or day in BCD format 24 4 0 15 MSK3 Alarm hours mask 23 1 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MSK2 Alarm minutes mask 15 1 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 ALRMASSR ALRMASSR Alarm sub-second register 0x44 0x20 read-write 0x00000000 SSCLR Clear synchronous counter on alarm 31 1 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 0 32767 ALRMBR ALRMBR Alarm register 0x48 0x20 read-write 0x00000000 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day donât care in Alarm comparison 1 MSK4 Alarm date mask 31 1 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is donât care. 1 DT Date tens in BCD format 28 2 0 3 DU Date units or day in BCD format 24 4 0 15 MSK3 Alarm hours mask 23 1 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MSK2 Alarm minutes mask 15 1 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 ALRMBSSR ALRMBSSR Alarm sub-second register 0x4C 0x20 read-write 0x00000000 SSCLR Clear synchronous counter on alarm 31 1 MASKSS Mask the most-significant bits starting at this bit 24 6 SS Sub seconds value 0 15 0 32767 SR SR status register 0x50 0x20 read-only 0x00000000 ALRAF ALRAF 0 1 ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 ALRBF ALRBF 1 1 WUTF WUTF 2 1 WUTF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSF TSF 3 1 TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVF TSOVF 4 1 TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSF ITSF 5 1 ITSF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SSRUF SSRUF 6 1 MISR MISR masked interrupt status register 0x54 0x20 read-only 0x00000000 ALRAMF ALRMF 0 1 ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 ALRBMF ALRBMF 1 1 WUTMF WUTMF 2 1 WUTMF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSMF TSMF 3 1 TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVMF TSOVMF 4 1 TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSMF ITSMF 5 1 ITSMF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SSRUMF SSRUMF 6 1 SCR SCR status clear register 0x5C 0x20 read-only 0x00000000 CALRAF CALRAF 0 1 CALRAF Clear Clear interrupt flag 1 CALRBF CALRBF 1 1 CWUTF CWUTF 2 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CITSF CITSF 5 1 CSSRUF CSSRUF 6 1 ALRABINR ALRABINR alarm A binary mode register 0x70 0x20 read-write 0x00000000 SS Synchronous counter alarm value in Binary mode 0 32 ALRBBINR ALRBBINR alarm B binary mode register 0x74 0x20 read-write 0x00000000 SS Synchronous counter alarm value in Binary mode 0 32 OTG_FS_GLOBAL USB on the go full speed USB_OTG_FS 0x50000000 0x0 0x400 registers OTG_FS USB OTG FS global Interrupt 67 GOTGCTL GOTGCTL OTG_FS control and status register (OTG_FS_GOTGCTL) 0x0 0x20 0x00000800 SRQSCS Session request success 0 1 read-only SRQ Session request 1 1 read-write HNGSCS Host negotiation success 8 1 read-only HNPRQ HNP request 9 1 read-write HSHNPEN Host set HNP enable 10 1 read-write DHNPEN Device HNP enabled 11 1 read-write CIDSTS Connector ID status 16 1 read-only DBCT Long/short debounce time 17 1 read-only ASVLD A-session valid 18 1 read-only BSVLD B-session valid 19 1 read-only VBVALOEN VBUS valid override enable 2 1 read-write VBVALOVAL VBUS valid override value 3 1 read-write AVALOEN A-peripheral session valid override enable 4 1 read-write AVALOVAL A-peripheral session valid override value 5 1 read-write BVALOEN B-peripheral session valid override enable 6 1 read-write BVALOVAL B-peripheral session valid override value 7 1 read-write EHEN Embedded host enable 12 1 read-write OTGVER OTG version 20 1 read-write CURMOD Current mode of operation 21 1 read-only GOTGINT GOTGINT OTG_FS interrupt register (OTG_FS_GOTGINT) 0x4 0x20 read-write 0x00000000 SEDET Session end detected 2 1 SRSSCHG Session request success status change 8 1 HNSSCHG Host negotiation success status change 9 1 HNGDET Host negotiation detected 17 1 ADTOCHG A-device timeout change 18 1 DBCDNE Debounce done 19 1 GAHBCFG GAHBCFG OTG_FS AHB configuration register (OTG_FS_GAHBCFG) 0x8 0x20 read-write 0x00000000 GINTMSK Global interrupt mask 0 1 TXFELVL TxFIFO empty level 7 1 PTXFELVL Periodic TxFIFO empty level 8 1 GUSBCFG GUSBCFG OTG_FS USB configuration register (OTG_FS_GUSBCFG) 0xC 0x20 0x00000A00 TOCAL FS timeout calibration 0 3 read-write PHYSEL Full Speed serial transceiver select 6 1 write-only SRPCAP SRP-capable 8 1 read-write HNPCAP HNP-capable 9 1 read-write TRDT USB turnaround time 10 4 read-write FHMOD Force host mode 29 1 read-write FDMOD Force device mode 30 1 read-write GRSTCTL GRSTCTL OTG_FS reset register (OTG_FS_GRSTCTL) 0x10 0x20 0x20000000 CSRST Core soft reset 0 1 read-write HSRST HCLK soft reset 1 1 read-write FCRST Host frame counter reset 2 1 read-write RXFFLSH RxFIFO flush 4 1 read-write TXFFLSH TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write AHBIDL AHB master idle 31 1 read-only GINTSTS GINTSTS OTG_FS core interrupt register (OTG_FS_GINTSTS) 0x14 0x20 0x04000020 CMOD Current mode of operation 0 1 read-only MMIS Mode mismatch interrupt 1 1 read-write OTGINT OTG interrupt 2 1 read-only SOF Start of frame 3 1 read-write RXFLVL RxFIFO non-empty 4 1 read-only NPTXFE Non-periodic TxFIFO empty 5 1 read-only GINAKEFF Global IN non-periodic NAK effective 6 1 read-only GOUTNAKEFF Global OUT NAK effective 7 1 read-only ESUSP Early suspend 10 1 read-write USBSUSP USB suspend 11 1 read-write USBRST USB reset 12 1 read-write ENUMDNE Enumeration done 13 1 read-write ISOODRP Isochronous OUT packet dropped interrupt 14 1 read-write EOPF End of periodic frame interrupt 15 1 read-write IEPINT IN endpoint interrupt 18 1 read-only OEPINT OUT endpoint interrupt 19 1 read-only IISOIXFR Incomplete isochronous IN transfer 20 1 read-write IPXFR_INCOMPISOOUT Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) 21 1 read-write HPRTINT Host port interrupt 24 1 read-only HCINT Host channels interrupt 25 1 read-only PTXFE Periodic TxFIFO empty 26 1 read-only CIDSCHG Connector ID status change 28 1 read-write DISCINT Disconnect detected interrupt 29 1 read-write SRQINT Session request/new session detected interrupt 30 1 read-write WKUPINT Resume/remote wakeup detected interrupt 31 1 read-write RSTDET Reset detected interrupt 23 1 LPMINT LPM interrupt 27 1 GINTMSK GINTMSK OTG_FS interrupt mask register (OTG_FS_GINTMSK) 0x18 0x20 0x00000000 MMISM Mode mismatch interrupt mask 1 1 read-write OTGINT OTG interrupt mask 2 1 read-write SOFM Start of frame mask 3 1 read-write RXFLVLM Receive FIFO non-empty mask 4 1 read-write NPTXFEM Non-periodic TxFIFO empty mask 5 1 read-write GINAKEFFM Global non-periodic IN NAK effective mask 6 1 read-write GONAKEFFM Global OUT NAK effective mask 7 1 read-write ESUSPM Early suspend mask 10 1 read-write USBSUSPM USB suspend mask 11 1 read-write USBRST USB reset mask 12 1 read-write ENUMDNEM Enumeration done mask 13 1 read-write ISOODRPM Isochronous OUT packet dropped interrupt mask 14 1 read-write EOPFM End of periodic frame interrupt mask 15 1 read-write EPMISM Endpoint mismatch interrupt mask 17 1 read-write IEPINT IN endpoints interrupt mask 18 1 read-write OEPINT OUT endpoints interrupt mask 19 1 read-write IISOIXFRM Incomplete isochronous IN transfer mask 20 1 read-write IPXFRM_IISOOXFRM Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) 21 1 read-write PRTIM Host port interrupt mask 24 1 read-write HCIM Host channels interrupt mask 25 1 read-write PTXFEM Periodic TxFIFO empty mask 26 1 read-write CIDSCHGM Connector ID status change mask 28 1 read-write DISCINT Disconnect detected interrupt mask 29 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write WUIM Resume/remote wakeup detected interrupt mask 31 1 read-write RSTDETM Reset detected interrupt mask 23 1 LPMINTM LPM interrupt mask 27 1 GRXSTSR_Device GRXSTSR_Device OTG_FS Receive status debug read(Device mode) 0x1C 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FRMNUM Frame number 21 4 STSPHST Status phase start 27 1 GRXSTSR_Host GRXSTSR_Host OTG status debug read (host mode) GRXSTSR_Device 0x1C 0x20 read-only 0x00000000 CHNUM Channel number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 GRXSTSP_Device OTG status read and pop (device mode) 0x20 0x20 read-only 0x00000000 FRMNUM Frame number 21 4 PKTSTS Packet status 17 4 DPID Data PID 15 2 BCNT Byte count 4 11 EPNUM Endpoint number 0 4 STSPHST ?? 27 1 GRXSTSP_Host OTG status read and pop (host mode) GRXSTSP_Device 0x20 0x20 read-only 0x00000000 PKTSTS Packet status 17 4 DPID Data PID 15 2 BCNT Byte count 4 11 CHNUM Channel number 0 4 GRXFSIZ GRXFSIZ OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) 0x24 0x20 read-write 0x00000200 RXFD RxFIFO depth 0 16 DIEPTXF0 DIEPTXF0 OTG_FS non-periodic transmit FIFO size register (Device mode) 0x28 0x20 read-write 0x00000200 TX0FSA Endpoint 0 transmit RAM start address 0 16 TX0FD Endpoint 0 TxFIFO depth 16 16 HNPTXFSIZ HNPTXFSIZ OTG_FS non-periodic transmit FIFO size register (Host mode) DIEPTXF0 0x28 0x20 read-write 0x00000200 NPTXFSA Non-periodic transmit RAM start address 0 16 NPTXFD Non-periodic TxFIFO depth 16 16 GNPTXSTS GNPTXSTS OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) 0x2C 0x20 read-only 0x00080200 NPTXFSAV Non-periodic TxFIFO space available 0 16 NPTQXSAV Non-periodic transmit request queue space available 16 8 NPTXQTOP Top of the non-periodic transmit request queue 24 7 GCCFG GCCFG OTG_FS general core configuration register (OTG_FS_GCCFG) 0x38 0x20 read-write 0x00000000 PWRDWN Power down 16 1 DCDET Data contact detection (DCD) status 0 1 read-only PDET Primary detection (PD) status 1 1 read-only SDET Secondary detection (SD) status 2 1 read-only PS2DET DM pull-up detection status 3 1 read-only BCDEN Battery charging detector (BCD) enable 17 1 read-write DCDEN Data contact detection (DCD) mode enable 18 1 read-write PDEN Primary detection (PD) mode enable 19 1 read-write SDEN Secondary detection (SD) mode enable 20 1 read-write VBDEN USB VBUS detection enable 21 1 read-write CID CID core ID register 0x3C 0x20 read-write 0x00001000 PRODUCT_ID Product ID field 0 32 GLPMCFG OTG core LPM configuration register 0x54 0x00000000 LPMEN LPM support enable 0 1 read-write LPMACK LPM token acknowledge enable 1 1 read-write BESL Best effort service latency 2 4 read-write REMWAKE bRemoteWake value 6 1 read-write L1SSEN L1 Shallow Sleep enable 7 1 read-write BESLTHRS BESL threshold 8 4 read-write L1DSEN L1 deep sleep enable 12 1 read-write LPMRSP LPM response 13 2 read-only SLPSTS Port sleep status 15 1 read-only L1RSMOK Sleep state resume OK 16 1 read-only LPMCHIDX LPM Channel Index 17 4 read-write LPMRCNT LPM retry count 21 3 SNDLPM Send LPM transaction 24 1 read-write LPMRCNTSTS LPM retry count status 25 3 read-only ENBESL Enable best effort service latency 28 1 read-write GPWRDN OTG power down register 0x58 read-write 0x00000000 ADPMEN ADP module enable 0 1 ADPIF ADP interrupt flag 23 1 GADPCTL OTG ADP timer, control and status register 0x60 0x00000000 PRBDSCHG Probe discharge 0 2 read-write PRBDELTA Probe delta 2 2 read-write PRBPER Probe period 0 4 read-write RTIM Ramp time 6 11 read-only ENAPRB Enable probe 17 1 read-write ENASNS Enable sense 18 1 read-write ADPRST ADP reset 19 1 read-write ADPEN ADP enable 20 1 read-write ADPPRBIF ADP probe interrupt flag 21 1 read-write ADPSNSIF ADP sense interrupt flag 22 1 read-write ADPTOIF ADP timeout interrupt flag 23 1 read-write ADPPRBIM ADP probe interrupt mask 24 1 read-write ADPSNSIM ADP sense interrupt mask 25 1 read-write ADPTOIM ADP timeout interrupt mask 26 1 read-write AR Access request 27 2 read-write HPTXFSIZ HPTXFSIZ OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) 0x100 0x20 read-write 0x02000600 PTXSA Host periodic TxFIFO start address 0 16 PTXFSIZ Host periodic TxFIFO depth 16 16 5 0x4 1-5 DIEPTXF%s DIEPTXF%s OTG_FS device IN endpoint transmit FIFO size register 0x104 0x20 read-write 0x02000400 INEPTXSA IN endpoint FIFO2 transmit RAM start address 0 16 INEPTXFD IN endpoint TxFIFO depth 16 16 OTG_FS_HOST USB on the go full speed USB_OTG_FS 0x50000400 0x0 0x400 registers HCFG HCFG OTG_FS host configuration register (OTG_FS_HCFG) 0x0 0x20 0x00000000 FSLSPCS FS/LS PHY clock select 0 2 read-write FSLSS FS- and LS-only support 2 1 read-write HFIR HFIR OTG_FS Host frame interval register 0x4 0x20 read-write 0x0000EA60 FRIVL Frame interval 0 16 RLDCTRL Reload control 16 1 HFNUM HFNUM OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) 0x8 0x20 read-only 0x00003FFF FRNUM Frame number 0 16 FTREM Frame time remaining 16 16 HPTXSTS HPTXSTS OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) 0x10 0x20 0x00080100 PTXFSAVL Periodic transmit data FIFO space available 0 16 read-write PTXQSAV Periodic transmit request queue space available 16 8 read-only PTXQTOP Top of the periodic transmit request queue 24 8 read-only HAINT HAINT OTG_FS Host all channels interrupt register 0x14 0x20 read-only 0x00000000 HAINT Channel interrupts 0 16 HAINTMSK HAINTMSK OTG_FS host all channels interrupt mask register 0x18 0x20 read-write 0x00000000 HAINTM Channel interrupt mask 0 16 HPRT HPRT OTG_FS host port control and status register (OTG_FS_HPRT) 0x40 0x20 0x00000000 PCSTS Port connect status 0 1 read-only PCDET Port connect detected 1 1 read-write PENA Port enable 2 1 read-write PENCHNG Port enable/disable change 3 1 read-write POCA Port overcurrent active 4 1 read-only POCCHNG Port overcurrent change 5 1 read-write PRES Port resume 6 1 read-write PSUSP Port suspend 7 1 read-write PRST Port reset 8 1 read-write PLSTS Port line status 10 2 read-only PPWR Port power 12 1 read-write PTCTL Port test control 13 4 read-write PSPD Port speed 17 2 read-only 12 0x20 0-11 HC%s Host channel 0x100 CHAR HCCHAR0 OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) 0x0 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 INT HCINT0 OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) 0x8 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 INTMSK HCINTMSK0 OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) 0xC 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 TSIZ HCTSIZ0 OTG_FS host channel-0 transfer size register 0x10 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 DOPNG Do Ping 31 1 OTG_FS_DEVICE USB on the go full speed USB_OTG_FS 0x50000800 0x0 0x400 registers DCFG DCFG OTG_FS device configuration register (OTG_FS_DCFG) 0x0 0x20 read-write 0x02200000 DSPD Device speed 0 2 NZLSOHSK Non-zero-length status OUT handshake 2 1 DAD Device address 4 7 PFIVL Periodic frame interval 11 2 ERRATIM Erratic error interrupt mask 15 1 DCTL DCTL OTG_FS device control register (OTG_FS_DCTL) 0x4 0x20 0x00000000 RWUSIG Remote wakeup signaling 0 1 read-write SDIS Soft disconnect 1 1 read-write GINSTS Global IN NAK status 2 1 read-only GONSTS Global OUT NAK status 3 1 read-only TCTL Test control 4 3 read-write SGINAK Set global IN NAK 7 1 read-write CGINAK Clear global IN NAK 8 1 read-write SGONAK Set global OUT NAK 9 1 read-write CGONAK Clear global OUT NAK 10 1 read-write POPRGDNE Power-on programming done 11 1 read-write DSBESLRJCT Deep sleep BESL reject 18 1 read-write DSTS DSTS OTG_FS device status register (OTG_FS_DSTS) 0x8 0x20 read-only 0x00000010 SUSPSTS Suspend status 0 1 ENUMSPD Enumerated speed 1 2 EERR Erratic error 3 1 FNSOF Frame number of the received SOF 8 14 DEVLNSTS Device line status 22 2 DIEPMSK DIEPMSK OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) 0x10 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 TOM Timeout condition mask (Non-isochronous endpoints) 3 1 ITTXFEMSK IN token received when TxFIFO empty mask 4 1 INEPNMM IN token received with EP mismatch mask 5 1 INEPNEM IN endpoint NAK effective mask 6 1 NAKM NAK interrupt mask 13 1 DOEPMSK DOEPMSK OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) 0x14 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 STUPM SETUP phase done mask 3 1 OTEPDM OUT token received when endpoint disabled mask 4 1 OUTPKTERRM Out packet error mask 8 1 BERRM Babble error interrupt mask 12 1 NAKMSK NAK interrupt mask 13 1 DAINT DAINT OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) 0x18 0x20 read-only 0x00000000 IEPINT IN endpoint interrupt bits 0 16 OEPINT OUT endpoint interrupt bits 16 16 DAINTMSK DAINTMSK OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) 0x1C 0x20 read-write 0x00000000 IEPM IN EP interrupt mask bits 0 16 OEPM OUT EP interrupt mask bits 16 16 DVBUSDIS DVBUSDIS OTG_FS device VBUS discharge time register 0x28 0x20 read-write 0x000017D7 VBUSDT Device VBUS discharge time 0 16 DVBUSPULSE DVBUSPULSE OTG_FS device VBUS pulsing time register 0x2C 0x20 read-write 0x000005B8 DVBUSP Device VBUS pulsing time 0 12 DIEPEMPMSK DIEPEMPMSK OTG_FS device IN endpoint FIFO empty interrupt mask register 0x34 0x20 read-write 0x00000000 INEPTXFEM IN EP Tx FIFO empty interrupt mask bits 0 16 DIEP0 Device IN endpoint 0 0x100 CTL DIEPCTL0 OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) 0x0 0x20 0x00000000 MPSIZ Maximum packet size 0 2 read-write USBAEP USB active endpoint 15 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-only STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPDIS Endpoint disable 30 1 read-only EPENA Endpoint enable 31 1 read-write INT DIEPINT0 device endpoint-x interrupt register 0x8 0x20 0x00000080 TXFE TXFE 7 1 read-only INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write EPDISD EPDISD 1 1 read-write XFRC XFRC 0 1 read-write INEPNM IN token received with EP mismatch 5 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write NAK NAK input 13 1 read-write TSIZ DIEPTSIZ0 device endpoint-0 transfer size register 0x10 0x20 read-write 0x00000000 PKTCNT Packet count 19 2 XFRSIZ Transfer size 0 7 TXFSTS DTXFSTS0 OTG_FS device IN endpoint transmit FIFO status register 0x18 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space available 0 16 5 0x20 1-5 DIEP%s Device IN endpoint X 0x120 CTL DIEPCTL1 OTG device endpoint-1 control register 0x0 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM_SD1PID SODDFRM/SD1PID 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only TXFNUM TXFNUM 22 4 read-write STALL STALL handshake 21 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write INT DIEPINT1 device endpoint-1 interrupt register 0x8 TSIZ DIEPTSIZ1 device endpoint-1 transfer size register 0x10 0x20 read-write 0x00000000 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 TXFSTS DTXFSTS1 OTG_FS device IN endpoint transmit FIFO status register 0x18 DOEP0 Device OUT endpoint 0 0x300 CTL DOEPCTL0 device endpoint-0 control register 0x0 0x20 0x00008000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only STALL STALL handshake 21 1 read-write SNPM SNPM 20 1 read-write EPTYP EPTYP 18 2 read-only NAKSTS NAKSTS 17 1 read-only USBAEP USBAEP 15 1 read-only MPSIZ MPSIZ 0 2 read-only INT DOEPINT0 device endpoint-0 interrupt register 0x8 0x20 read-write 0x00000080 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 EPDISD EPDISD 1 1 XFRC XFRC 0 1 STSPHSRX Status phase received for control write 5 1 BERR Babble error interrupt 12 1 NAK NAK input 13 1 TSIZ DOEPTSIZ0 device OUT endpoint-0 transfer size register 0x10 0x20 read-write 0x00000000 STUPCNT SETUP packet count 29 2 PKTCNT Packet count 19 1 XFRSIZ Transfer size 0 7 5 0x20 1-5 DOEP%s Device IN endpoint X 0x320 CTL DOEPCTL1 device endpoint-1 control register 0x0 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM SODDFRM 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only STALL STALL handshake 21 1 read-write SNPM SNPM 20 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write INT DOEPINT1 device endpoint-1 interrupt register 0x8 TSIZ DOEPTSIZ1 device OUT endpoint-1 transfer size register 0x10 0x20 read-write 0x00000000 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 OTG_FS_PWRCLK USB on the go full speed USB_OTG_FS 0x50000E00 0x0 0x400 registers PCGCCTL PCGCCTL OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) 0x0 0x20 read-write 0x00000000 STPPCLK Stop PHY clock 0 1 GATEHCLK Gate HCLK 1 1 PHYSUSP PHY Suspended 4 1 OPAMP Operational amplifiers OPAMP 0x40007800 0x0 0x400 registers OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 OPAEN Disabled OpAmp disabled 0 Enabled OpAmp enabled 1 OPALPM Operational amplifier Low Power Mode 1 1 OPALPM NORMAL OpAmp in normal mode 0 LOW OpAmp in low power mode 1 OPAMODE Operational amplifier PGA mode 2 2 OPAMODE PGA_DISABLED internal PGA diabled 0 PGA_ENABLED internal PGA enabled, gain programmed in PGA_GAIN 2 FOLLOWER internal follower 3 PGA_GAIN Operational amplifier Programmable amplifier gain value 4 2 PGA_GAIN Gain2 Gain 2 0 Gain4 Gain 4 1 Gain8 Gain 8 2 Gain16 Gain 16 3 VM_SEL Inverting input selection 8 2 VM_SEL GPIO GPIO connectet to VINM 0 LOW_LEAKAGE Low leakage inputs connected (only available in certein BGA cases 1 PGA_MODE OPAMP in PGA mode 2 VP_SEL Non inverted input selection 10 1 VP_SEL GPIO GPIO connected to VINP 0 DAC DAC connected to VPINP 1 CALON Calibration mode enabled 12 1 CALON Disabled Normal mode 0 Enabled Calibration mode 1 CALSEL Calibration selection 13 1 CALSEL NMOS 0.2V applied to OPAMP inputs during calibration 0 PMOS VDDA-0.2V applied to OPAMP inputs during calibration" 1 USERTRIM allows to switch from AOP offset trimmed values to AOP offset 14 1 USERTRIM Factory Factory trim used 0 User User trim used 1 CALOUT Operational amplifier calibration output 15 1 0 1 OPA_RANGE Operational amplifier power supply range for stability 31 1 OPA_RANGE LOW low range (VDDA < 2.4V 0 HIGH low range (VDDA >2.4V 1 OPAMP1_OTR OPAMP1_OTR OPAMP1 offset trimming register in normal mode 0x4 0x20 read-write 0x00000000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 0 31 TRIMOFFSETP Trim for PMOS differential pairs 8 5 0 31 OPAMP1_LPOTR OPAMP1_LPOTR OPAMP1 offset trimming register in low-power mode 0x8 0x20 read-write 0x00000000 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 0 31 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 0 31 OPAMP2_CSR OPAMP2_CSR OPAMP2 control/status register 0x10 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 OPALPM Operational amplifier Low Power Mode 1 1 OPAMODE Operational amplifier PGA mode 2 2 PGA_GAIN Operational amplifier Programmable amplifier gain value 4 2 PGA_GAIN Gain2 Gain 2 0 Gain4 Gain 4 1 Gain8 Gain 8 2 Gain16 Gain 16 3 VM_SEL Inverting input selection 8 2 VP_SEL Non inverted input selection 10 1 CALON Calibration mode enabled 12 1 CALSEL Calibration selection 13 1 USERTRIM allows to switch from AOP offset trimmed values to AOP offset 14 1 CALOUT Operational amplifier calibration output 15 1 OPAMP2_OTR OPAMP2_OTR OPAMP2 offset trimming register in normal mode 0x14 0x20 read-write 0x00000000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 0 31 TRIMOFFSETP Trim for PMOS differential pairs 8 5 0 31 OPAMP2_LPOTR OPAMP2_LPOTR OPAMP2 offset trimming register in low-power mode 0x18 0x20 read-write 0x00000000 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 0 31 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 0 31 FMC Flexible memory controller FMC 0xA0000000 0x0 0x400 registers FMC FMC global Interrupt 48 FPU Floating point interrupt 81 BCR1 BCR1 SRAM/NOR-Flash chip-select control register 1 0x0 0x20 read-write 0x000030D0 MBKEN MBKEN 0 1 MBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 MUXEN MUXEN 1 1 MUXEN Disabled Address/Data non-multiplexed 0 Enabled Address/Data multiplexed on databus 1 MTYP MTYP 2 2 MTYP SRAM SRAM memory type 0 PSRAM PSRAM (CRAM) memory type 1 Flash NOR Flash/OneNAND Flash 2 MWID MWID 4 2 MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 FACCEN FACCEN 6 1 FACCEN Disabled Corresponding NOR Flash memory access is disabled 0 Enabled Corresponding NOR Flash memory access is enabled 1 BURSTEN BURSTEN 8 1 BURSTEN Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 WAITPOL WAITPOL 9 1 WAITPOL ActiveLow NWAIT active low 0 ActiveHigh NWAIT active high 1 WAITCFG WAITCFG 11 1 WAITCFG BeforeWaitState NWAIT signal is active one data cycle before wait state 0 DuringWaitState NWAIT signal is active during wait state 1 WREN WREN 12 1 WREN Disabled Write operations disabled for the bank by the FMC 0 Enabled Write operations enabled for the bank by the FMC 1 WAITEN WAITEN 13 1 WAITEN Disabled Values inside the FMC_BWTR are taken into account 0 Enabled NWAIT signal enabled 1 EXTMOD EXTMOD 14 1 EXTMOD Disabled Values inside the FMC_BWTR are not taken into account 0 Enabled Values inside the FMC_BWTR are taken into account 1 ASYNCWAIT ASYNCWAIT 15 1 ASYNCWAIT Disabled Wait signal not used in asynchronous mode 0 Enabled Wait signal used even in asynchronous mode 1 CBURSTRW CBURSTRW 19 1 CBURSTRW Disabled Write operations are always performed in asynchronous mode 0 Enabled Write operations are performed in synchronous mode 1 CCLKEN CCLKEN 20 1 CCLKEN Disabled The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set 0 Enabled The FMC_CLK is only generated during the synchronous memory access (read/write transaction) 1 WFDIS Write FIFO Disable 21 1 WFDIS Enabled Write FIFO enabled 0 Disabled Write FIFO disabled 1 CPSIZE CRAM page size 16 3 CPSIZE NoBurstSplit No burst split when crossing page boundary 0 Bytes128 128 bytes CRAM page size 1 Bytes256 256 bytes CRAM page size 2 Bytes512 512 bytes CRAM page size 3 Bytes1024 1024 bytes CRAM page size 4 NBLSET Byte lane (NBL) setup 22 2 4 0x8 1-4 BTR%s BTR%s SRAM/NOR-Flash chip-select timing register %s 0x4 0x20 read-write 0xFFFFFFFF ACCMOD ACCMOD 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATLAT DATLAT 24 4 0 15 CLKDIV CLKDIV 20 4 1 15 BUSTURN BUSTURN 16 4 0 15 DATAST DATAST 8 8 1 255 ADDHLD ADDHLD 4 4 1 15 ADDSET ADDSET 0 4 0 15 DATAHLD Data hold phase duration 30 2 3 0x8 2-4 BCR%s BCR%s SRAM/NOR-Flash chip-select control register %s 0x8 0x20 read-write 0x000030D0 CBURSTRW CBURSTRW 19 1 ASYNCWAIT ASYNCWAIT 15 1 EXTMOD EXTMOD 14 1 WAITEN WAITEN 13 1 WREN WREN 12 1 WAITCFG WAITCFG 11 1 WAITPOL WAITPOL 9 1 BURSTEN BURSTEN 8 1 FACCEN FACCEN 6 1 MWID MWID 4 2 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MBKEN MBKEN 0 1 CPSIZE CRAM page size 16 3 NBLSET Byte lane (NBL) setup 22 2 PCSCNTR PSRAM chip select counter register 0x20 0x00000000 CSCOUNT Chip select counter 0 16 4 0x1 1-4 CNTB%sEN Counter Bank %s enable 16 1 PCR PCR PC Card/NAND Flash control register 3 0x80 0x20 read-write 0x00000018 ECCPS ECCPS 17 3 ECCPS Bytes256 ECC page size 256 bytes 0 Bytes512 ECC page size 512 bytes 1 Bytes1024 ECC page size 1024 bytes 2 Bytes2048 ECC page size 2048 bytes 3 Bytes4096 ECC page size 4096 bytes 4 Bytes8192 ECC page size 8192 bytes 5 TAR TAR 13 4 0 15 TCLR TCLR 9 4 0 15 ECCEN ECCEN 6 1 ECCEN Disabled ECC logic is disabled and reset 0 Enabled ECC logic is enabled 1 PWID PWID 4 2 PWID Bits8 External memory device width 8 bits 0 Bits16 External memory device width 16 bits 1 PTYP PTYP 3 1 PTYP NANDFlash NAND Flash 1 PBKEN PBKEN 2 1 PBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 PWAITEN PWAITEN 1 1 PWAITEN Disabled Wait feature disabled 0 Enabled Wait feature enabled 1 SR SR FIFO status and interrupt register 3 0x84 0x20 0x00000040 FEMPT FEMPT 6 1 read-only FEMPT NotEmpty FIFO not empty 0 Empty FIFO empty 1 IFEN IFEN 5 1 read-write IFEN Disabled Interrupt falling edge detection request disabled 0 Enabled Interrupt falling edge detection request enabled 1 ILEN ILEN 4 1 read-write ILEN Disabled Interrupt high-level detection request disabled 0 Enabled Interrupt high-level detection request enabled 1 IREN IREN 3 1 read-write IREN Disabled Interrupt rising edge detection request disabled 0 Enabled Interrupt rising edge detection request enabled 1 IFS IFS 2 1 read-write IFS DidNotOccur Interrupt falling edge did not occur 0 Occurred Interrupt falling edge occurred 1 ILS ILS 1 1 read-write ILS DidNotOccur Interrupt high-level did not occur 0 Occurred Interrupt high-level occurred 1 IRS IRS 0 1 read-write IRS DidNotOccur Interrupt rising edge did not occur 0 Occurred Interrupt rising edge occurred 1 PMEM PMEM Common memory space timing register 3 0x88 0x20 read-write 0xFCFCFCFC MEMHIZ MEMHIZx 24 8 0 254 MEMHOLD MEMHOLDx 16 8 1 254 MEMWAIT MEMWAITx 8 8 1 254 MEMSET MEMSETx 0 8 0 254 PATT PATT Attribute memory space timing register 3 0x8C 0x20 read-write 0xFCFCFCFC ATTHIZ ATTHIZx 24 8 0 254 ATTHOLD ATTHOLDx 16 8 1 254 ATTWAIT ATTWAITx 8 8 1 254 ATTSET ATTSETx 0 8 0 254 ECCR ECCR ECC result register 3 0x94 0x20 read-only 0x00000000 ECC ECCx 0 32 0 4294967295 4 0x8 1-4 BWTR%s BWTR%s SRAM/NOR-Flash write timing registers %s 0x104 0x20 read-write 0x0FFFFFFF ACCMOD ACCMOD 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATAST DATAST 8 8 1 255 ADDHLD ADDHLD 4 4 1 15 ADDSET ADDSET 0 4 0 15 BUSTURN Bus turnaround phase duration 16 4 0 15 DATAHLD Data hold phase duration 30 2 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0x368 registers ISER0 ISER0 Interrupt Set-Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER2 ISER2 Interrupt Set-Enable Register 0x8 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER2 ICER2 Interrupt Clear-Enable Register 0x88 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR2 ISPR2 Interrupt Set-Pending Register 0x108 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR2 ICPR2 Interrupt Clear-Pending Register 0x188 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x200 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR2 IABR2 Interrupt Active Bit Register 0x208 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x300 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x30C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR15 IPR15 Interrupt Priority Register 0x33C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR16 IPR16 Interrupt Priority Register 0x340 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR17 IPR17 Interrupt Priority Register 0x344 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR18 IPR18 Interrupt Priority Register 0x348 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR19 IPR19 Interrupt Priority Register 0x34C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR20 IPR20 Interrupt Priority Register 0x350 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR21 IPR21 Interrupt Priority Register 0x354 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR22 IPR22 Interrupt Priority Register 0x358 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR23 IPR23 Interrupt Priority Register 0x35C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR24 IPR24 Interrupt Priority Register 0x360 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR25 IPR25 Interrupt Priority Register 0x364 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 CRS Clock recovery system CRS 0x40006000 0x0 0x400 registers CRS CRS global interrupt 82 CR CR control register 0x0 0x20 read-write 0x00002000 TRIM HSI48 oscillator smooth trimming 8 6 0 63 SWSYNC Generate software SYNC event 7 1 SWSYNC Sync A software sync is generated 1 AUTOTRIMEN Automatic trimming enable 6 1 AUTOTRIMEN Disabled Automatic trimming disabled 0 Enabled Automatic trimming enabled 1 CEN Frequency error counter enable 5 1 CEN Disabled Frequency error counter disabled 0 Enabled Frequency error counter enabled 1 SYNCOKIE SYNC event OK interrupt enable 0 1 SYNCOKIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 ESYNCIE Expected SYNC interrupt enable 3 1 ERRIE Synchronization or trimming error interrupt enable 2 1 SYNCWARNIE SYNC warning interrupt enable 1 1 CFGR CFGR configuration register 0x4 0x20 read-write 0x2022BB7F SYNCPOL SYNC polarity selection 31 1 SYNCPOL RisingEdge SYNC active on rising edge 0 FallingEdge SYNC active on falling edge 1 SYNCSRC SYNC signal source selection 28 2 SYNCSRC GPIO_AF GPIO AF (crs_sync_in_1) selected as SYNC signal source 0 LSE LSE (crs_sync_in_2) selected as SYNC signal source 1 USB_SOF USB SOF (crs_sync_in_3) selected as SYNC signal source 2 SYNCDIV SYNC divider 24 3 SYNCDIV Div1 SYNC not divided 0 Div2 SYNC divided by 2 1 Div4 SYNC divided by 4 2 Div8 SYNC divided by 8 3 Div16 SYNC divided by 16 4 Div32 SYNC divided by 32 5 Div64 SYNC divided by 64 6 Div128 SYNC divided by 128 7 FELIM Frequency error limit 16 8 0 255 RELOAD Counter reload value 0 16 0 65535 ISR ISR interrupt and status register 0x8 0x20 read-only 0x00000000 FECAP Frequency error capture 16 16 0 65535 FEDIR Frequency error direction 15 1 FEDIR UpCounting Error in up-counting direction 0 DownCounting Error in down-counting direction 1 SYNCOKF SYNC event OK flag 0 1 SYNCOKF NotSignaled Signal not set 0 Signaled Signal set 1 TRIMOVF Trimming overflow or underflow 10 1 SYNCMISS SYNC missed 9 1 SYNCERR SYNC error 8 1 ESYNCF Expected SYNC flag 3 1 ERRF Error flag 2 1 SYNCWARNF SYNC warning flag 1 1 ICR ICR interrupt flag clear register 0xC 0x20 read-write 0x00000000 SYNCOKC SYNC event OK clear flag 0 1 SYNCOKC Clear Clear flag 1 ESYNCC Expected SYNC clear flag 3 1 ERRC Error clear flag 2 1 SYNCWARNC SYNC warning clear flag 1 1 DCMI Digital camera interface DCMI 0x50050000 0x0 0x400 registers DCMI_PSSI DCMI/PSSI global interrupt 85 CR CR control register 1 0x0 0x20 read-write 0x00000000 ENABLE DCMI enable 14 1 ENABLE Disabled DCMI disabled 0 Enabled DCMI enabled 1 EDM Extended data mode 10 2 EDM BitWidth8 Interface captures 8-bit data on every pixel clock 0 BitWidth10 Interface captures 10-bit data on every pixel clock 1 BitWidth12 Interface captures 12-bit data on every pixel clock 2 BitWidth14 Interface captures 14-bit data on every pixel clock 3 FCRC Frame capture rate control 8 2 FCRC All All frames are captured 0 Alternate Every alternate frame captured (50% bandwidth reduction) 1 OneOfFour One frame out of four captured (75% bandwidth reduction) 2 VSPOL Vertical synchronization polarity 7 1 VSPOL ActiveLow DCMI_VSYNC active low 0 ActiveHigh DCMI_VSYNC active high 1 HSPOL Horizontal synchronization polarity 6 1 HSPOL ActiveLow DCMI_HSYNC active low 0 ActiveHigh DCMI_HSYNC active high 1 PCKPOL Pixel clock polarity 5 1 PCKPOL FallingEdge Falling edge active 0 RisingEdge Rising edge active 1 ESS Embedded synchronization select 4 1 ESS Hardware Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals 0 Embedded Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow 1 JPEG JPEG format 3 1 JPEG Uncompressed Uncompressed video format 0 JPEG This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode 1 CROP Crop feature 2 1 CROP Full The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four 0 Cropped Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured 1 CM Capture mode 1 1 CM Continuous Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA 0 Snapshot Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset 1 CAPTURE Capture enable 0 1 CAPTURE Disabled Capture disabled 0 Enabled Capture enabled 1 OELS Odd/Even Line Select (Line Select Start) 20 1 OELS Odd Interface captures first line after the frame start, second one being dropped 0 Even Interface captures second line from the frame start, first one being dropped 1 LSM Line Select mode 19 1 LSM All Interface captures all received lines 0 Half Interface captures one line out of two 1 OEBS Odd/Even Byte Select (Byte Select Start) 18 1 OEBS Odd Interface captures first data (byte or double byte) from the frame/line start, second one being dropped 0 Even Interface captures second data (byte or double byte) from the frame/line start, first one being dropped 1 BSM Byte Select mode 16 2 BSM All Interface captures all received data 0 EveryOther Interface captures every other byte from the received data 1 Fourth Interface captures one byte out of four 2 TwoOfFour Interface captures two bytes out of four 3 SR SR status register 0x4 0x20 read-only 0x00000000 FNE FIFO not empty 2 1 FNE NotEmpty FIFO contains valid data 0 Empty FIFO empty 1 VSYNC VSYNC 1 1 VSYNC ActiveFrame Active frame 0 BetweenFrames Synchronization between frames 1 HSYNC HSYNC 0 1 HSYNC ActiveLine Active line 0 BetweenLines Synchronization between lines 1 RIS RIS raw interrupt status register 0x8 0x20 read-only 0x00000000 LINE_RIS Line raw interrupt status 4 1 LINE_RIS Cleared Interrupt cleared 0 Set Interrupt set 1 VSYNC_RIS VSYNC raw interrupt status 3 1 VSYNC_RIS Cleared Interrupt cleared 0 Set Interrupt set 1 ERR_RIS Synchronization error raw interrupt status 2 1 ERR_RIS NoError No synchronization error detected 0 SynchronizationError Embedded synchronization characters are not received in the correct order 1 OVR_RIS Overrun raw interrupt status 1 1 OVR_RIS NoOverrun No data buffer overrun occurred 0 OverrunOccured A data buffer overrun occurred and the data FIFO is corrupted. The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register 1 FRAME_RIS Capture complete raw interrupt status 0 1 FRAME_RIS NoNewCapture No new capture 0 FrameCaptured A frame has been captured 1 IER IER interrupt enable register 0xC 0x20 read-write 0x00000000 LINE_IE Line interrupt enable 4 1 LINE_IE Disabled No interrupt generation when the line is received 0 Enabled An Interrupt is generated when a line has been completely received 1 VSYNC_IE VSYNC interrupt enable 3 1 VSYNC_IE Disabled No interrupt generation 0 Enabled An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state 1 ERR_IE Synchronization error interrupt enable 2 1 ERR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if the embedded synchronization codes are not received in the correct order 1 OVR_IE Overrun interrupt enable 1 1 OVR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received 1 FRAME_IE Capture complete interrupt enable 0 1 FRAME_IE Disabled No interrupt generation 0 Enabled An interrupt is generated at the end of each received frame/crop window (in crop mode) 1 MIS MIS masked interrupt status register 0x10 0x20 read-only 0x00000000 LINE_MIS Line masked interrupt status 4 1 LINE_MIS Disabled No interrupt generation when the line is received 0 Enabled An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER 1 VSYNC_MIS VSYNC masked interrupt status 3 1 VSYNC_MIS Disabled No interrupt is generated on DCMI_VSYNC transitions 0 Enabled An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER 1 ERR_MIS Synchronization error masked interrupt status 2 1 ERR_MIS Disabled No interrupt is generated on a synchronization error 0 Enabled An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set 1 OVR_MIS Overrun masked interrupt status 1 1 OVR_MIS Disabled No interrupt is generated on overrun 0 Enabled An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER 1 FRAME_MIS Capture complete masked interrupt status 0 1 FRAME_MIS Disabled No interrupt is generated after a complete capture 0 Enabled An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER 1 ICR ICR interrupt clear register 0x14 0x20 write-only 0x00000000 LINE_ISC line interrupt status clear 4 1 LINE_ISC Clear Setting this bit clears the LINE_RIS flag in the DCMI_RIS register 1 VSYNC_ISC Vertical synch interrupt status clear 3 1 VSYNC_ISC Clear Setting this bit clears the VSYNC_RIS flag in the DCMI_RIS register 1 ERR_ISC Synchronization error interrupt status clear 2 1 ERR_ISC Clear Setting this bit clears the ERR_RIS flag in the DCMI_RIS register 1 OVR_ISC Overrun interrupt status clear 1 1 OVR_ISC Clear Setting this bit clears the OVR_RIS flag in the DCMI_RIS register 1 FRAME_ISC Capture complete interrupt status clear 0 1 FRAME_ISC Clear Setting this bit clears the FRAME_RIS flag in the DCMI_RIS register 1 ESCR ESCR embedded synchronization code register 0x18 0x20 read-write 0x00000000 FEC Frame end delimiter code 24 8 LEC Line end delimiter code 16 8 LSC Line start delimiter code 8 8 FSC Frame start delimiter code 0 8 ESUR ESUR embedded synchronization unmask register 0x1C 0x20 read-write 0x00000000 FEU Frame end delimiter unmask 24 8 LEU Line end delimiter unmask 16 8 LSU Line start delimiter unmask 8 8 FSU Frame start delimiter unmask 0 8 CWSTRT CWSTRT crop window start 0x20 0x20 read-write 0x00000000 VST Vertical start line count 16 13 0 8191 HOFFCNT Horizontal offset count 0 14 0 16383 CWSIZE CWSIZE crop window size 0x24 0x20 read-write 0x00000000 VLINE Vertical line count 16 14 0 16383 CAPCNT Capture count 0 14 0 16383 DR DR data register 0x28 0x20 read-only 0x00000000 4 0x8 0-3 BYTE%s Data byte %s 0 8 0 255 PSSI Parallel synchronous slave interface PSSI 0x50050400 0x0 0x400 registers CR PSSI control register 0x0 0x20 read-write 0x40000000 OUTEN Data direction selection bit 31 1 OUTEN ReceiveMode Data is input synchronously with PSSI_PDCK 0 TransmitMode Data is output synchronously with PSSI_PDCK 1 DMAEN DMA enable bit 30 1 DMAEN Disabled DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled. 0 Enabled DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR 1 DERDYCFG Data enable and ready configuration 18 3 DERDYCFG Disabled PSSI_DE and PSSI_RDY both disabled 0 Rdy Only PSSI_RDY enabled 1 De Only PSSI_DE enabled 2 RdyDeAlt Both PSSI_RDY and PSSI_DE alternate functions enabled 3 RdyDe Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin 4 RdyRemapped Only PSSI_RDY function enabled, but mapped to PSSI_DE pin 5 DeRemapped Only PSSI_DE function enabled, but mapped to PSSI_RDY pin 6 RdyDeBidi Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin 7 ENABLE PSSI enable 14 1 ENABLE Disabled PSSI disabled 0 Enabled PSSI enabled 1 EDM Extended data mode 10 2 EDM BitWidth8 Interface captures 8-bit data on every parallel data clock 0 BitWidth16 The interface captures 16-bit data on every parallel data clock 3 RDYPOL Ready (PSSI_RDY) polarity 8 1 RDYPOL ActiveLow PSSI_RDY active low (0 indicates that the receiver is ready to receive) 0 ActiveHigh PSSI_RDY active high (1 indicates that the receiver is ready to receive) 1 DEPOL Data enable (PSSI_DE) polarity 6 1 DEPOL ActiveLow PSSI_DE active low (0 indicates that data is valid) 0 ActiveHigh PSSI_DE active high (1 indicates that data is valid) 1 CKPOL Parallel data clock polarity 5 1 CKPOL FallingEdge Falling edge active for inputs or rising edge active for outputs 0 RisingEdge Rising edge active for inputs or falling edge active for outputs 1 SR PSSI status register 0x4 0x20 read-only 0x00000000 RTT1B FIFO is ready to transfer one byte 3 1 RTT1B NotReady FIFO is not ready for a 1-byte transfer 0 Ready FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO 1 RTT4B FIFO is ready to transfer four bytes 2 1 RTT4B NotReady FIFO is not ready for a four-byte transfer 0 Ready FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO 1 RIS PSSI raw interrupt status register 0x8 0x20 read-only 0x00000000 OVR_RIS Data buffer overrun/underrun raw interrupt status 1 1 OVR_RIS Cleared No overrun/underrun occurred 0 Occurred An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR 1 IER PSSI interrupt enable register 0xC 0x20 read-write 0x00000000 OVR_IE Data buffer overrun/underrun interrupt enable 1 1 OVR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if either an overrun or an underrun error occurred 1 MIS PSSI masked interrupt status register 0x10 0x20 read-only 0x00000000 OVR_MIS Data buffer overrun/underrun masked interrupt status 1 1 OVR_MIS Disabled No interrupt is generated when an overrun/underrun error occurs 0 Enabled An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER 1 ICR PSSI interrupt clear register 0x14 0x20 write-only 0x00000000 OVR_ISC Data buffer overrun/underrun interrupt status clear 1 1 OVR_ISC Clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS 1 DR PSSI data register 0x28 0x20 read-write 0x00000000 BYTE3 24 8 0 255 BYTE2 16 8 0 255 BYTE1 8 8 0 255 BYTE0 0 8 0 255 HASH Hash processor HASH 0x50060400 0x0 0x400 registers CR CR control register 0x0 0x20 0x00000000 INIT Initialize message digest calculation 2 1 write-only DMAE DMA enable 3 1 read-write DATATYPE Data type selection 4 2 read-write MODE Mode selection 6 1 read-write ALGO0 Algorithm selection 7 1 read-write NBW Number of words already pushed 8 4 read-only DINNE DIN not empty 12 1 read-only MDMAT Multiple DMA Transfers 13 1 read-write LKEY Long key selection 16 1 read-write ALGO1 ALGO 18 1 read-write DIN DIN data input register 0x4 0x20 read-write 0x00000000 DATAIN Data input 0 32 STR STR start register 0x8 0x20 0x00000000 DCAL Digest calculation 8 1 write-only NBLW Number of valid bits in the last word of the message 0 5 read-write 5 0x4 0-4 HRA%s HRA%s HASH digest register alias %s 0xC 0x20 read-only 0x00000000 H H0 0 32 IMR IMR interrupt enable register 0x20 0x20 read-write 0x00000000 DCIE Digest calculation completion interrupt enable 1 1 DINIE Data input interrupt enable 0 1 SR SR status register 0x24 0x20 0x00000001 BUSY Busy bit 3 1 read-only DMAS DMA Status 2 1 read-only DCIS Digest calculation completion interrupt status 1 1 read-write DINIS Data input interrupt status 0 1 read-write 54 0x4 0-53 CSR%s CSR%s HASH context swap register %s 0xF8 0x20 read-write 0x00000000 CS CSR0 0 32 8 0x4 0-7 HR%s HASH_HR%s HASH digest register %s 0x310 0x20 read-only 0x00000000 H H0 0 32 DMA2D DMA2D controller DMA2D 0x4002B000 0x0 0xC00 registers DMA2D DMA2D global interrupt 90 CR CR control register 0x0 0x20 read-write 0x00000000 MODE DMA2D mode 16 3 MODE MemoryToMemory Memory-to-memory (FG fetch only) 0 MemoryToMemoryPFC Memory-to-memory with PFC (FG fetch only with FG PFC active) 1 MemoryToMemoryPFCBlending Memory-to-memory with blending (FG and BG fetch with PFC and blending) 2 RegisterToMemory Register-to-memory 3 CEIE Configuration Error Interrupt Enable 13 1 CEIE Disabled CE interrupt disabled 0 Enabled CE interrupt enabled 1 CTCIE CLUT transfer complete interrupt enable 12 1 CTCIE Disabled CTC interrupt disabled 0 Enabled CTC interrupt enabled 1 CAEIE CLUT access error interrupt enable 11 1 CAEIE Disabled CAE interrupt disabled 0 Enabled CAE interrupt enabled 1 TWIE Transfer watermark interrupt enable 10 1 TWIE Disabled TW interrupt disabled 0 Enabled TW interrupt enabled 1 TCIE Transfer complete interrupt enable 9 1 TCIE Disabled TC interrupt disabled 0 Enabled TC interrupt enabled 1 TEIE Transfer error interrupt enable 8 1 TEIE Disabled TE interrupt disabled 0 Enabled TE interrupt enabled 1 ABORT Abort 2 1 ABORT AbortRequest Transfer abort requested 1 SUSP Suspend 1 1 SUSP NotSuspended Transfer not suspended 0 Suspended Transfer suspended 1 START Start 0 1 START Start Launch the DMA2D 1 LOM Line Offset Mode 6 1 ISR ISR Interrupt Status Register 0x4 0x20 read-only 0x00000000 CEIF Configuration error interrupt flag 5 1 CTCIF CLUT transfer complete interrupt flag 4 1 CAEIF CLUT access error interrupt flag 3 1 TWIF Transfer watermark interrupt flag 2 1 TCIF Transfer complete interrupt flag 1 1 TEIF Transfer error interrupt flag 0 1 IFCR IFCR interrupt flag clear register 0x8 0x20 read-write 0x00000000 CCEIF Clear configuration error interrupt flag 5 1 CCEIF Clear Clear the CEIF flag in the ISR register 1 CCTCIF Clear CLUT transfer complete interrupt flag 4 1 CCTCIF Clear Clear the CTCIF flag in the ISR register 1 CAECIF Clear CLUT access error interrupt flag 3 1 CAECIF Clear Clear the CAEIF flag in the ISR register 1 CTWIF Clear transfer watermark interrupt flag 2 1 CTWIF Clear Clear the TWIF flag in the ISR register 1 CTCIF Clear transfer complete interrupt flag 1 1 CTCIF Clear Clear the TCIF flag in the ISR register 1 CTEIF Clear Transfer error interrupt flag 0 1 CTEIF Clear Clear the TEIF flag in the ISR register 1 FGMAR FGMAR foreground memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 FGOR FGOR foreground offset register 0x10 0x20 read-write 0x00000000 LO Line offset 0 16 0 16383 BGMAR BGMAR background memory address register 0x14 0x20 read-write 0x00000000 MA Memory address 0 32 BGOR BGOR background offset register 0x18 0x20 read-write 0x00000000 LO Line offset 0 16 0 16383 FGPFCCR FGPFCCR foreground PFC control register 0x1C 0x20 read-write 0x00000000 ALPHA Alpha value 24 8 0 255 AM Alpha mode 16 2 AM NoModify No modification of alpha channel 0 Replace Replace with value in ALPHA[7:0] 1 Multiply Multiply with value in ALPHA[7:0] 2 CS CLUT size 8 8 0 255 START Start 5 1 START Start Start the automatic loading of the CLUT 1 CCM CLUT color mode 4 1 CCM ARGB8888 CLUT color format ARGB8888 0 RGB888 CLUT color format RGB888 1 CM Color mode 0 4 CM ARGB8888 Color mode ARGB8888 0 RGB888 Color mode RGB888 1 RGB565 Color mode RGB565 2 ARGB1555 Color mode ARGB1555 3 ARGB4444 Color mode ARGB4444 4 L8 Color mode L8 5 AL44 Color mode AL44 6 AL88 Color mode AL88 7 L4 Color mode L4 8 A8 Color mode A8 9 A4 Color mode A4 10 RBS Red Blue Swap 21 1 AI Alpha Inverted 20 1 FGCOLR FGCOLR foreground color register 0x20 0x20 read-write 0x00000000 RED Red Value 16 8 0 255 GREEN Green Value 8 8 0 255 BLUE Blue Value 0 8 0 255 BGPFCCR BGPFCCR background PFC control register 0x24 0x20 read-write 0x00000000 ALPHA Alpha value 24 8 0 255 AM Alpha mode 16 2 AM NoModify No modification of alpha channel 0 Replace Replace with value in ALPHA[7:0] 1 Multiply Multiply with value in ALPHA[7:0] 2 CS CLUT size 8 8 0 255 START Start 5 1 START Start Start the automatic loading of the CLUT 1 CCM CLUT Color mode 4 1 CCM ARGB8888 CLUT color format ARGB8888 0 RGB888 CLUT color format RGB888 1 CM Color mode 0 4 CM ARGB8888 Color mode ARGB8888 0 RGB888 Color mode RGB888 1 RGB565 Color mode RGB565 2 ARGB1555 Color mode ARGB1555 3 ARGB4444 Color mode ARGB4444 4 L8 Color mode L8 5 AL44 Color mode AL44 6 AL88 Color mode AL88 7 L4 Color mode L4 8 A8 Color mode A8 9 A4 Color mode A4 10 RBS Red Blue Swap 21 1 AI Alpha Inverted 20 1 BGCOLR BGCOLR background color register 0x28 0x20 read-write 0x00000000 RED Red Value 16 8 0 255 GREEN Green Value 8 8 0 255 BLUE Blue Value 0 8 0 255 FGCMAR FGCMAR foreground CLUT memory address register 0x2C 0x20 read-write 0x00000000 MA Memory Address 0 32 BGCMAR BGCMAR background CLUT memory address register 0x30 0x20 read-write 0x00000000 MA Memory address 0 32 OPFCCR OPFCCR output PFC control register 0x34 0x20 read-write 0x00000000 CM Color mode 0 3 CM ARGB8888 ARGB8888 0 RGB888 RGB888 1 RGB565 RGB565 2 ARGB1555 ARGB1555 3 ARGB4444 ARGB4444 4 RBS Red Blue Swap 21 1 AI Alpha Inverted 20 1 SB Swap Bytes 9 1 OCOLR OCOLR output color register 0x38 0x20 read-write 0x00000000 APLHA Alpha Channel Value 24 8 RED Red Value 16 8 GREEN Green Value 8 8 BLUE Blue Value 0 8 OMAR OMAR output memory address register 0x3C 0x20 read-write 0x00000000 MA Memory Address 0 32 OOR OOR output offset register 0x40 0x20 read-write 0x00000000 LO Line Offset 0 14 0 16383 NLR NLR number of line register 0x44 0x20 read-write 0x00000000 PL Pixel per lines 16 14 0 16383 NL Number of lines 0 16 0 65535 LWR LWR line watermark register 0x48 0x20 read-write 0x00000000 LW Line watermark 0 16 AMTCR AMTCR AHB master timer configuration register 0x4C 0x20 read-write 0x00000000 DT Dead Time 8 8 0 255 EN Enable 0 1 EN Disabled Disabled AHB/AXI dead-time functionality 0 Enabled Enabled AHB/AXI dead-time functionality 1 FGCLUT FGCLUT FGCLUT 0x400 0x20 read-write 0x00000000 APLHA APLHA 24 8 RED RED 16 8 GREEN GREEN 8 8 BLUE BLUE 0 8 BGCLUT BGCLUT BGCLUT 0x800 0x20 read-write 0x00000000 APLHA APLHA 24 8 RED RED 16 8 GREEN GREEN 8 8 BLUE BLUE 0 8 OCTOSPIM OctoSPI IO Manager OCTOSPIM 0x50061C00 0x0 0x400 registers CR configuration register 0x0 0x00000000 MUXEN Multiplexed mode enable 0 1 REQ2ACK_TIME REQ to ACK time 16 8 P1CR P1CR OctoSPI IO Manager Port 1 Configuration Register 0x4 0x20 read-write 0x03010111 CLKEN CLK/CLK Enable for Port 0 1 CLKSRC CLK/CLK Source for Port 1 1 DQSEN DQS Enable for Port 4 1 DQSSRC DQS Source for Port 5 1 NCSEN CS Enable for Port 8 1 NCSSRC CS Source for Port 9 1 IOLEN Enable for Port 16 1 IOLSRC Source for Port 17 2 IOHEN Enable for Port n 24 1 IOHSRC Source for Port 25 2 P2CR P2CR OctoSPI IO Manager Port 2 Configuration Register 0x8 0x20 read-write 0x07050333 CLKEN CLK/CLK Enable for Port 0 1 CLKSRC CLK/CLK Source for Port 1 1 DQSEN DQS Enable for Port 4 1 DQSSRC DQS Source for Port 5 1 NCSEN CS Enable for Port 8 1 NCSSRC CS Source for Port 9 1 IOLEN Enable for Port 16 1 IOLSRC Source for Port 17 2 IOHEN Enable for Port n 24 1 IOHSRC Source for Port 25 2 FPU Floting point unit FPU 0xE000EF34 0x0 0xD registers FPU Floating point unit interrupt 81 FPU Floating point interrupt 81 FPCCR FPCCR Floating-point context control register 0x0 0x20 read-write 0x00000000 LSPACT LSPACT 0 1 USER USER 1 1 THREAD THREAD 3 1 HFRDY HFRDY 4 1 MMRDY MMRDY 5 1 BFRDY BFRDY 6 1 MONRDY MONRDY 8 1 LSPEN LSPEN 30 1 ASPEN ASPEN 31 1 FPCAR FPCAR Floating-point context address register 0x4 0x20 read-write 0x00000000 ADDRESS Location of unpopulated floating-point 3 29 FPSCR FPSCR Floating-point status control register 0x8 0x20 read-write 0x00000000 IOC Invalid operation cumulative exception bit 0 1 DZC Division by zero cumulative exception bit. 1 1 OFC Overflow cumulative exception bit 2 1 UFC Underflow cumulative exception bit 3 1 IXC Inexact cumulative exception bit 4 1 IDC Input denormal cumulative exception bit. 7 1 RMode Rounding Mode control field 22 2 FZ Flush-to-zero mode control bit: 24 1 DN Default NaN mode control bit 25 1 AHP Alternative half-precision control bit 26 1 V Overflow condition code flag 28 1 C Carry condition code flag 29 1 Z Zero condition code flag 30 1 N Negative condition code flag 31 1 MPU Memory protection unit MPU 0xE000ED90 0x0 0x15 registers TYPER TYPER MPU type register 0x0 0x20 read-only 0x00000800 SEPARATE Separate flag 0 1 DREGION Number of MPU data regions 8 8 IREGION Number of MPU instruction regions 16 8 CTRL CTRL MPU control register 0x4 0x20 read-write 0x00000000 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault 1 1 PRIVDEFENA Enable priviliged software access to default memory map 2 1 RNR RNR MPU region number register 0x8 0x20 read-write 0x00000000 REGION MPU region 0 8 RBAR RBAR MPU region base address register 0xC 0x20 read-write 0x00000000 REGION MPU region field 0 4 VALID MPU region number valid 4 1 ADDR Region base address field 5 27 RASR RASR MPU region attribute and size register 0x10 0x20 read-write 0x00000000 ENABLE Region enable bit. 0 1 SIZE Size of the MPU protection region 1 5 SRD Subregion disable bits 8 8 B memory attribute 16 1 C memory attribute 17 1 S Shareable memory attribute 18 1 TEX memory attribute 19 3 AP Access permission 24 3 XN Instruction access disable bit 28 1 STK SysTick timer STK 0xE000E010 0x0 0x11 registers CTRL CTRL SysTick control and status register 0x0 0x20 read-write 0x00000000 ENABLE Counter enable 0 1 TICKINT SysTick exception request enable 1 1 CLKSOURCE Clock source selection 2 1 COUNTFLAG COUNTFLAG 16 1 LOAD LOAD SysTick reload value register 0x4 0x20 read-write 0x00000000 RELOAD RELOAD value 0 24 VAL VAL SysTick current value register 0x8 0x20 read-write 0x00000000 CURRENT Current counter value 0 24 CALIB CALIB SysTick calibration value register 0xC 0x20 read-write 0x00000000 TENMS Calibration value 0 24 SKEW SKEW flag: Indicates whether the TENMS value is exact 30 1 NOREF NOREF flag. Reads as zero 31 1 SCB System control block SCB 0xE000ED00 0x0 0x41 registers CPUID CPUID CPUID base register 0x0 0x20 read-only 0x410FC241 Revision Revision number 0 4 PartNo Part number of the processor 4 12 Constant Reads as 0xF 16 4 Variant Variant number 20 4 Implementer Implementer code 24 8 ICSR ICSR Interrupt control and state register 0x4 0x20 read-write 0x00000000 VECTACTIVE Active vector 0 9 RETTOBASE Return to base level 11 1 VECTPENDING Pending vector 12 7 ISRPENDING Interrupt pending flag 22 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVSET PendSV set-pending bit 28 1 NMIPENDSET NMI set-pending bit. 31 1 VTOR VTOR Vector table offset register 0x8 0x20 read-write 0x00000000 TBLOFF Vector table base offset field 9 21 AIRCR AIRCR Application interrupt and reset control register 0xC 0x20 read-write 0x00000000 VECTRESET VECTRESET 0 1 VECTCLRACTIVE VECTCLRACTIVE 1 1 SYSRESETREQ SYSRESETREQ 2 1 PRIGROUP PRIGROUP 8 3 ENDIANESS ENDIANESS 15 1 VECTKEYSTAT Register key 16 16 SCR SCR System control register 0x10 0x20 read-write 0x00000000 SLEEPONEXIT SLEEPONEXIT 1 1 SLEEPDEEP SLEEPDEEP 2 1 SEVEONPEND Send Event on Pending bit 4 1 CCR CCR Configuration and control register 0x14 0x20 read-write 0x00000000 NONBASETHRDENA Configures how the processor enters Thread mode 0 1 USERSETMPEND USERSETMPEND 1 1 UNALIGN__TRP UNALIGN_ TRP 3 1 DIV_0_TRP DIV_0_TRP 4 1 BFHFNMIGN BFHFNMIGN 8 1 STKALIGN STKALIGN 9 1 SHPR1 SHPR1 System handler priority registers 0x18 0x20 read-write 0x00000000 PRI_4 Priority of system handler 4 0 8 PRI_5 Priority of system handler 5 8 8 PRI_6 Priority of system handler 6 16 8 SHPR2 SHPR2 System handler priority registers 0x1C 0x20 read-write 0x00000000 PRI_11 Priority of system handler 11 24 8 SHPR3 SHPR3 System handler priority registers 0x20 0x20 read-write 0x00000000 PRI_14 Priority of system handler 14 16 8 PRI_15 Priority of system handler 15 24 8 SHCSR SHCSR System handler control and state register 0x24 0x20 read-write 0x00000000 MEMFAULTACT Memory management fault exception active bit 0 1 BUSFAULTACT Bus fault exception active bit 1 1 USGFAULTACT Usage fault exception active bit 3 1 SVCALLACT SVC call active bit 7 1 MONITORACT Debug monitor active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTPENDED Usage fault exception pending bit 12 1 MEMFAULTPENDED Memory management fault exception pending bit 13 1 BUSFAULTPENDED Bus fault exception pending bit 14 1 SVCALLPENDED SVC call pending bit 15 1 MEMFAULTENA Memory management fault enable bit 16 1 BUSFAULTENA Bus fault enable bit 17 1 USGFAULTENA Usage fault enable bit 18 1 CFSR_UFSR_BFSR_MMFSR CFSR_UFSR_BFSR_MMFSR Configurable fault status register 0x28 0x20 read-write 0x00000000 IACCVIOL Instruction access violation flag 1 1 MUNSTKERR Memory manager fault on unstacking for a return from exception 3 1 MSTKERR Memory manager fault on stacking for exception entry. 4 1 MLSPERR MLSPERR 5 1 MMARVALID Memory Management Fault Address Register (MMAR) valid flag 7 1 IBUSERR Instruction bus error 8 1 PRECISERR Precise data bus error 9 1 IMPRECISERR Imprecise data bus error 10 1 UNSTKERR Bus fault on unstacking for a return from exception 11 1 STKERR Bus fault on stacking for exception entry 12 1 LSPERR Bus fault on floating-point lazy state preservation 13 1 BFARVALID Bus Fault Address Register (BFAR) valid flag 15 1 UNDEFINSTR Undefined instruction usage fault 16 1 INVSTATE Invalid state usage fault 17 1 INVPC Invalid PC load usage fault 18 1 NOCP No coprocessor usage fault. 19 1 UNALIGNED Unaligned access usage fault 24 1 DIVBYZERO Divide by zero usage fault 25 1 HFSR HFSR Hard fault status register 0x2C 0x20 read-write 0x00000000 VECTTBL Vector table hard fault 1 1 FORCED Forced hard fault 30 1 DEBUG_VT Reserved for Debug use 31 1 MMFAR MMFAR Memory management fault address register 0x34 0x20 read-write 0x00000000 MMFAR Memory management fault address 0 32 BFAR BFAR Bus fault address register 0x38 0x20 read-write 0x00000000 BFAR Bus fault address 0 32 AFSR AFSR Auxiliary fault status register 0x3C 0x20 read-write 0x00000000 IMPDEF Implementation defined 0 32 NVIC_STIR Nested vectored interrupt controller NVIC 0xE000EF00 0x0 0x5 registers STIR STIR Software trigger interrupt register 0x0 0x20 read-write 0x00000000 INTID Software generated interrupt ID 0 9 FPU_CPACR Floating point unit CPACR FPU 0xE000ED88 0x0 0x5 registers CPACR CPACR Coprocessor access control register 0x0 0x20 read-write 0x00000000 CP CP 20 4 SCB_ACTRL System control block ACTLR SCB 0xE000E008 0x0 0x5 registers ACTRL ACTRL Auxiliary control register 0x0 0x20 read-write 0x00000000 DISMCYCINT DISMCYCINT 0 1 DISDEFWBUF DISDEFWBUF 1 1 DISFOLD DISFOLD 2 1 DISFPCA DISFPCA 8 1 DISOOFP DISOOFP 9 1

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