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Showing content from https://stm32-rs.github.io/stm32-rs/stm32h7s.svd.patched below:

STM32H7S 1.0 STM32H7S CM7 r0p1 little true true 4 false 8 32 0x20 0x00000000 0xFFFFFFFF ADC1 ADC register block ADC 0x40022000 0x0 0x400 registers ISR ISR ADC interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF ADRDY ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0 1 read-write EOSMP End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase. 1 1 read-write EOC End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register 2 1 read-write EOS End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it. 3 1 read-write OVR ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it. 4 1 read-write JEOC Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register 5 1 read-write JEOS Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it. 6 1 read-write AWD1 Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it. 7 1 read-write AWD2 Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it. 8 1 read-write AWD3 Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it. 9 1 read-write JQOVF Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to Section 25.4.21: Queue of context for injected conversions for more information. 10 1 read-write IER IER ADC interrupt enable register 0x4 0x20 0x00000000 0xFFFFFFFF ADRDYIE ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 1 read-write EOSMPIE End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 1 1 read-write EOCIE End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 2 1 read-write EOSIE End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 3 1 read-write OVRIE Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 4 1 read-write JEOCIE End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 5 1 read-write JEOSIE End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 6 1 read-write AWD1IE Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 7 1 read-write AWD2IE Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 8 1 read-write AWD3IE Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 9 1 read-write JQOVFIE Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 10 1 read-write CR CR ADC control register 0x8 0x20 0x20000000 0xFFFFFFFF ADEN ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator) 0 1 read-write ADDIS ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 1 1 read-write ADSTART ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion immediately starts (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) Note: In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) 2 1 read-write JADSTART ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion immediately starts (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). Note: In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) 3 1 read-write ADSTP ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). 4 1 read-write JADSTP ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) Note: In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP) 5 1 read-write ADVREGEN ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to Section 25.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 28 1 read-write DEEPPWD Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 29 1 read-write ADCALDIF Differential mode for calibration This bit is set and cleared by software to configure the Single-ended or Differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 30 1 read-write ADCAL ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for Single-ended or Differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. Note: The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing) 31 1 read-write CFGR CFGR ADC configuration register 0xC 0x20 0x80000000 0xFFFFFFFF DMAEN Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to Section : Managing conversions using the DMA. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the ADC_CCR register. 0 1 read-write DMACFG Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Section : Managing conversions using the DMA Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the ADC_CCR register. 1 1 read-write ADFCFG ADF mode configuration This bit is set and cleared by software to enable the ADF mode. It is effective only when DMAEN = 0. Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0. 2 1 read-write RES Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 3 2 read-write EXTSEL External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 5 5 EXTEN External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 10 2 read-write OVRMOD Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 12 1 read-write CONT Single / Continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADC_CCR register are not equal to zero), the bit CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the master ADC. 13 1 read-write AUTDLY Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADC_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC. 14 1 read-write ALIGN Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Section : Data register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 15 1 read-write DISCEN Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. Note: It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADC_CCR register are not equal to zero), the bit DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC. 16 1 read-write DISCNUM Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in Discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADC_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC. 17 3 read-write JDISCEN Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable Discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). Note: It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. Note: When dual mode is enabled (bits DUAL of ADC_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC. 20 1 read-write JQM JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to Section 25.4.21: Queue of context for injected conversions for more information. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADC_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master ADC. 21 1 read-write AWD1SGL Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 22 1 read-write AWD1EN Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 23 1 read-write JAWD1EN Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 24 1 read-write JAUTO Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADC_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC. 25 1 read-write AWD1CH Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: reserved, must not be used Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 26 5 read-write JQDIS Injected queue disable This bit is set and cleared by software to disable the injected queue mechanism: Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). Note: A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared. 31 1 read-write CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 0x00000000 0xFFFFFFFF ROVSE Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 0 1 read-write JOVSE Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 1 1 read-write OVSR Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). 2 3 read-write OVSS Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). 5 4 read-write TROVS Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 9 1 read-write ROVSM Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 10 1 read-write SWTRIG Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 25 1 read-write BULB Bulb sampling mode This bit is set and cleared by software to enable the bulb sampling mode. SAMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 26 1 read-write SMPTRIG Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 27 1 read-write SMPR1 SMPR1 ADC sample time register 1 0x14 0x20 0x00000000 0xFFFFFFFF SMP0 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 3 read-write SMP1 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 3 3 read-write SMP2 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 6 3 read-write SMP3 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 9 3 read-write SMP4 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 12 3 read-write SMP5 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 15 3 read-write SMP6 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 18 3 read-write SMP7 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 21 3 read-write SMP8 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 24 3 read-write SMP9 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 27 3 read-write SMPPLUS Addition of one clock cycle to the sampling time. To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0. 31 1 read-write SMPR2 SMPR2 ADC sample time register 2 0x18 0x20 0x00000000 0xFFFFFFFF SMP10 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 3 read-write SMP11 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 3 3 read-write SMP12 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 6 3 read-write SMP13 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 9 3 read-write SMP14 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 12 3 read-write SMP15 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 15 3 read-write SMP16 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 18 3 read-write SMP17 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 21 3 read-write SMP18 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 24 3 read-write TR1 TR1 ADC watchdog threshold register 1 0x20 0x20 0x0FFF0000 0xFFFFFFFF LT1 Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to Section 25.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 12 read-write AWDFILT Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 12 3 read-write HT1 Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to Section 25.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 16 12 read-write TR2 TR2 ADC watchdog threshold register 2 0x24 0x20 0x00FF0000 0xFFFFFFFF LT2 Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to Section 25.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 8 read-write HT2 Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to Section 25.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 16 8 read-write TR3 TR3 ADC watchdog threshold register 3 0x28 0x20 0x00FF0000 0xFFFFFFFF LT3 Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 8 read-write HT3 Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to Section 25.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 16 8 read-write SQR1 SQR1 ADC regular sequence register 1 0x30 0x20 0x00000000 0xFFFFFFFF L Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 0 4 read-write SQ1 1st conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 1st in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 6 5 read-write SQ2 2nd conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 12 5 read-write SQ3 3rd conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 18 5 read-write SQ4 4th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 24 5 read-write SQR2 SQR2 ADC regular sequence register 2 0x34 0x20 0x00000000 0xFFFFFFFF SQ5 5th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 5th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 0 5 read-write SQ6 6th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 6th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 6 5 read-write SQ7 7th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 7th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 12 5 read-write SQ8 8th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 8th in the regular conversion sequence Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 18 5 read-write SQ9 9th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 24 5 read-write SQR3 SQR3 ADC regular sequence register 3 0x38 0x20 0x00000000 0xFFFFFFFF SQ10 10th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 10th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 0 5 read-write SQ11 11th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 11th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 6 5 read-write SQ12 12th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 12th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 12 5 read-write SQ13 13th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 13th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 18 5 read-write SQ14 14th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 24 5 read-write SQR4 SQR4 ADC regular sequence register 4 0x3C 0x20 0x00000000 0xFFFFFFFF SQ15 15th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 15th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 0 5 read-write SQ16 16th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 6 5 read-write DR DR ADC regular data register 0x40 0x20 0x00000000 0xFFFFFFFF RDATA Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in Section 25.4.26: Data management. 0 16 read-only JSQR JSQR ADC injected sequence register 0x4C 0x20 0x00000000 0xFFFFFFFF JL Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 0 2 read-write JEXTSEL External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 2 5 read-write JEXTEN External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). Note: If JQM = 1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Section 25.4.21: Queue of context for injected conversions) 7 2 read-write JSQ1 1st conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 1st in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 9 5 read-write JSQ2 2nd conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 15 5 read-write JSQ3 3rd conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 21 5 read-write JSQ4 4th conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 27 5 read-write OFR1 OFR1 ADC offset 1 register 0x60 0x20 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Note: Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. 0 12 read-write OFFSETPOS Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 24 1 read-write SATEN Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 25 1 read-write OFFSET_CH Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the data offset y. Note: If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. 26 5 read-write OFFSET_EN Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 31 1 read-write OFR2 OFR2 ADC offset 2 register 0x64 0x20 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Note: Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. 0 12 read-write OFFSETPOS Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 24 1 read-write SATEN Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 25 1 read-write OFFSET_CH Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the data offset y. Note: If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. 26 5 read-write OFFSET_EN Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 31 1 read-write OFR3 OFR3 ADC offset 3 register 0x68 0x20 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Note: Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. 0 12 read-write OFFSETPOS Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 24 1 read-write SATEN Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 25 1 read-write OFFSET_CH Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the data offset y. Note: If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. 26 5 read-write OFFSET_EN Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 31 1 read-write OFR4 OFR4 ADC offset 4 register 0x6C 0x20 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Note: Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. 0 12 read-write OFFSETPOS Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 24 1 read-write SATEN Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 25 1 read-write OFFSET_CH Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the data offset y. Note: If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. 26 5 read-write OFFSET_EN Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 31 1 read-write JDR1 JDR1 ADC injected channel 1 data register 0x80 0x20 0x00000000 0xFFFFFFFF JDATA Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 25.4.26: Data management. 0 16 read-only JDR2 JDR2 ADC injected channel 2 data register 0x84 0x20 0x00000000 0xFFFFFFFF JDATA Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 25.4.26: Data management. 0 16 read-only JDR3 JDR3 ADC injected channel 3 data register 0x88 0x20 0x00000000 0xFFFFFFFF JDATA Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 25.4.26: Data management. 0 16 read-only JDR4 JDR4 ADC injected channel 4 data register 0x8C 0x20 0x00000000 0xFFFFFFFF JDATA Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 25.4.26: Data management. 0 16 read-only AWD2CR AWD2CR ADC Analog Watchdog 2 Configuration Register 0xA0 0x20 0x00000000 0xFFFFFFFF AWD2CH Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog. 0 19 read-write AWD3CR AWD3CR ADC Analog Watchdog 3 Configuration Register 0xA4 0x20 0x00000000 0xFFFFFFFF AWD3CH Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog. 0 19 read-write DIFSEL DIFSEL ADC Differential mode Selection Register 0xB0 0x20 0x00000000 0xFFFFFFFF DIFSEL Differential mode for channels 18 to 0. These bits are set and cleared by software. They allow to select if a channel is configured as Single-ended or Differential mode. DIFSEL[i] = 0: ADC analog input channel is configured in Single-ended mode DIFSEL[i] = 1: ADC analog input channel i is configured in Differential mode Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (Single-ended input mode). Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 0 19 read-write CALFACT CALFACT ADC Calibration Factors 0xB4 0x20 0x00000000 0xFFFFFFFF CALFACT_S Calibration Factors In Single-ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). 0 7 read-write CALFACT_D Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new differential calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). 16 7 read-write OR OR ADC option register 0xC8 0x20 0x00000000 0xFFFFFFFF OP0 Option bit 0 0 1 read-write ADC2 0x40022100 ADC12_common master and slave ADC common ADC 0x40022300 0x0 0x400 registers ADC1_2 ADC1/2 global interrupt 38 CSR CSR ADC common status register 0x300 0x20 0x00000000 0xFFFFFFFF ADRDY_MST Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. 0 1 read-only EOSMP_MST End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register. 1 1 read-only EOC_MST End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register. 2 1 read-only EOS_MST End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register. 3 1 read-only OVR_MST Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register. 4 1 read-only JEOC_MST End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. 5 1 read-only JEOS_MST End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. 6 1 read-only AWD1_MST Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. 7 1 read-only AWD2_MST Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register. 8 1 read-only AWD3_MST Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register. 9 1 read-only JQOVF_MST Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. 10 1 read-only ADRDY_SLV Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. 16 1 read-only EOSMP_SLV End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register. 17 1 read-only EOC_SLV End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register. 18 1 read-only EOS_SLV End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register. 19 1 read-only OVR_SLV Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register. 20 1 read-only JEOC_SLV End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. 21 1 read-only JEOS_SLV End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. 22 1 read-only AWD1_SLV Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. 23 1 read-only AWD2_SLV Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register. 24 1 read-only AWD3_SLV Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register. 25 1 read-only JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. 26 1 read-only CCR CCR ADC common control register 0x308 0x20 0x00000000 0xFFFFFFFF DUAL Dual ADC mode selection These bits are written by software to select the operating mode. 00000 corresponds to Independent mode. Values 00001 to 01001 correspond to Dual mode, master and slave ADCs working together. Others: Reserved, must not be used Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 0 5 read-write DELAY Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to Table 198 for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 8 4 read-write DMACFG DMA configuration (for dual ADC mode) This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Section : Managing conversions using the DMA Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 13 1 read-write MDMA Direct memory access mode for dual ADC mode This bitfield is set and cleared by software. Refer to the DMA controller section for more details. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 14 2 read-write CKMODE ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 16 2 read-write PRESC ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00. 18 4 read-write VREFEN VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel. 22 1 read-write TSEN VSENSE enable This bit is set and cleared by software to control VSENSE. 23 1 read-write VBATEN VBAT enable This bit is set and cleared by software to control. 24 1 read-write CDR CDR ADC common regular data register for dual mode 0x30C 0x20 0x00000000 0xFFFFFFFF RDATA_MST Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to Section 25.4.31: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)) In MDMA = 0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0]. 0 16 read-only RDATA_SLV Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 25.4.31: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)) 16 16 read-only HWCFGR0 HWCFGR0 ADC hardware configuration register 0x3F0 0x20 0x00001112 0xFFFFFFFF ADCNUM Number of ADCs implemented 0 4 read-only MULPIPE Number of pipeline stages 4 4 read-only OPBITS Number of option bits 8 4 read-only IDLEVALUE Idle value for non-selected channels 12 4 read-only VERR VERR ADC version register 0x3F4 0x20 0x00000012 0xFFFFFFFF MINREV Minor revision These bits returns the ADC IP minor revision 0 4 read-only MAJREV Major revision These bits returns the ADC IP major revision 4 4 read-only IPDR IPDR ADC identification register 0x3F8 0x20 0x00110006 0xFFFFFFFF ID Peripheral identifier These bits returns the ADC identifier. ID[31:0] = 0x0011 0006: c7amba_aditf5_90_v1 0 32 read-only SIDR SIDR ADC size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size Identification SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address: 0 32 read-only ADF Audio digital filter ADF 0x4002F000 0x0 0xF4 registers ADF1_FLT0 ADF1 filter 0 global interrupt 126 GCR GCR ADF global control register 0x0 0x20 0x00000000 0xFFFFFFFF TRGO Trigger output control This bit is set by software and reset by hardware. It is used to start the acquisition of several filters synchronously. It is also used to synchronize several ADF together by controlling the adf_trgo signal. 0 1 read-write CKGCR CKGCR ADF clock generator control register 0x4 0x20 0x00000000 0xFFFFFFFF CKGDEN CKGEN dividers enable This bit is set and reset by software. It is used to enable/disable the clock dividers of the CKGEN: PROCDIV and CCKDIV. 0 1 read-write CCK0EN ADF_CCK0 clock enable This bit is set and reset by software. It is used to control the generation of the bitstream clock on the ADF_CCK0 pin. 1 1 read-write CCK1EN ADF_CCK1 clock enable This bit is set and reset by software. It is used to control the generation of the bitstream clock on the ADF_CCK1 pin. 2 1 read-write CKGMOD Clock generator mode This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1). Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 4 1 read-write CCK0DIR ADF_CCK0 direction This bit is set and reset by software. It is used to control the direction of the ADF_CCK0 pin. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 5 1 read-write CCK1DIR ADF_CCK1 direction This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 6 1 read-write TRGSENS CKGEN trigger sensitivity selection This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0. Note: When the trigger source is TRGO, the sensitivity is forced to falling edge, thus TRGSENS value is not taken into account. This bit can be write-protected (see Section 46.4.13: Register protection for details). 8 1 read-write TRGSRC Digital filter trigger signal selection This field is set and cleared by software. It is used to select which external signals trigger the corresponding filter. This field is not significant if the CKGMOD = 0. 000x: TRGO selected others: reserved Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 12 4 read-write CCKDIV Divider to control the ADF_CCK clock This field is set and reset by software. It is used to adjust the frequency of the ADF_CCK clock. The input clock of this divider is the clock provided to the SITF. More globally, the frequency of the ADF_CCK is given by the following formula: This field must not be changed if the filter is enabled (DFTEN = 1). ... Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 16 4 read-write PROCDIV Divider to control the serial interface clock this field is set and reset by software. It is used to adjust the frequency of the clock provided to the SITF. This field must not be changed if the filter is enabled (DFTEN = 1). ... Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 24 7 read-write CKGACTIVE Clock generator active flag This bit is set and cleared by hardware. Ii is used by the application to check if the clock generator is effectively enabled (active) or not. The protected fields of this function can only be updated when CKGACTIVE = 0 (see Section 46.4.13: Register protection for details). The delay between a transition on CKGDEN and a transition on CKGACTIVE is two periods of AHB clock and two 2 periods of adf_proc_ck. 31 1 read-only SITF0CR SITF0CR ADF serial interface control register 0 0x80 0x20 0x00001F00 0xFFFFFFFF SITFEN Serial interface enable This bit is set and cleared by software. It is used to enable/disable the serial interface. 0 1 read-write SCKSRC Serial clock source This field is set and cleared by software. It is used to select the clock source of the serial interface. others: reserved Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 1 2 read-write SITFMOD Serial interface type This field is set and cleared by software. It is used to define the serial interface type. Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 4 2 read-write STH Manchester symbol threshold/SPI threshold This field is set and cleared by software. It is used for Manchester mode to define the expected symbol threshold levels (seer to Manchester mode for details on computation). In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. STH[4:0] values lower than four are invalid. Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 8 5 read-write SITFACTIVE Serial interface active flag This bit is set and cleared by hardware. It is used by the application to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when SITFACTIVE is set to 0 (see Section 46.4.13: Register protection for details). The delay between a transition on SITFEN and a transition on SITFACTIVE is two periods of AHB clock and two periods of adf_proc_ck. 31 1 read-only BSMX0CR BSMX0CR ADF bitstream matrix control register 0 0x84 0x20 0x00000000 0xFFFFFFFF BSSEL Bitstream selection This field is set and cleared by software. It is used to select the bitstream to be processed for DFLT0. others: reserved Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 0 5 read-write BSMXACTIVE BSMX active flag This bit is set and cleared by hardware. It is used by the application to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when BSMXACTIVE is set to 0. This BSMXACTIVE flag cannot go to 0 if DFLT0 is enabled. 31 1 read-only DFLT0CR DFLT0CR ADF digital filter control register 0 0x88 0x20 0x00000000 0xFFFFFFFF DFLTEN DFLT0 enable This bit is set and cleared by software. It is used to control the start of acquisition of the DFLT0 path. This bit behavior depends on ACQMOD[2:0] and external events. The serial or parallel interface delivering the samples must be enabled as well. 0 1 write-only DMAEN DMA requests enable This bit is set and cleared by software. It is used to control the generation of DMA request to transfer the processed samples into the memory. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 1 1 read-write FTH RXFIFO threshold selection This bit is set and cleared by software. It is used to select the RXFIFO threshold. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 2 1 read-write ACQMOD DFLT0 trigger mode This field is set and cleared by software. It is used to select the filter trigger mode. others: same as 000 Note: This field can be write-protected (see Section 46.4.13: Register protection for details).. 4 3 read-write TRGSENS DFLT0 trigger sensitivity selection This field is set and cleared by software. It is used to select the trigger sensitivity of the external signals When the trigger source is TRGO, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 8 1 read-write TRGSRC DFLT0 trigger signal selection This field is set and cleared by software. It is used to select which external signals trigger DFLT0. others: Reserved Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 12 4 read-write NBDIS Number of samples to be discarded This field is set and cleared by software. It is used to define the number of samples to be discarded every time DFLT0 is re-started. ... Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 20 8 read-write DFLTRUN DFLT0 run status flag This bit is set and cleared by hardware. It indicates if DFLT0 is running or not. 30 1 read-only DFLTACTIVE DFLT0 active flag This bit is set and cleared by hardware. It indicates if DFLT0 is active: can be running or waiting for events. 31 1 read-only DFLT0CICR DFLT0CICR ADF digital filer configuration register 0 0x8C 0x20 0x00000000 0xFFFFFFFF DATSRC Source data for the digital filter This field is set and cleared by software. 0x: Stream coming from the BSMX selected Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 0 2 read-write CICMOD Select the CIC order This field is set and cleared by software. It is used to select the order of the MCIC. others: reserved Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 4 3 read-write MCICD CIC decimation ratio selection This field is set and cleared by software.It is used to select the CIC decimation ratio. A decimation ratio smaller than two is not allowed. The decimation ratio is given by (CICDEC+1). ... Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 8 8 read-write MCICD8 CIC decimation ratio selection This field is set and cleared by software.It is used to select the CIC decimation ratio. A decimation ratio smaller than two is not allowed. The decimation ratio is given by (CICDEC+1). ... Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 16 1 read-write SCALE Scaling factor selection This field is set and cleared by software. It is used to select the gain to be applied at CIC output (see Table 419 for details). If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this field informs the application on the current gain value. ... ... others: Reserved 20 6 read-write DFLT0RSFR DFLT0RSFR ADF reshape filter configuration register 0 0x90 0x20 0x00000000 0xFFFFFFFF RSFLTBYP Reshaper filter bypass This bit is set and cleared by software. It is used to bypass the reshape filter and its decimation block. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 0 1 read-write RSFLTD Reshaper filter decimation ratio This bit is set and cleared by software. It is used to select the decimation ratio for the reshape filter Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 4 1 read-write HPFBYP High-pass filter bypass This bit is set and cleared by software. It is used to bypass the high-pass filter. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 7 1 read-write HPFC High-pass filter cut-off frequency This field is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 8 2 read-write DLY0CR DLY0CR ADF delay control register 0 0xA4 0x20 0x00000000 0xFFFFFFFF SKPDLY Delay to apply to a bitstream This field is set and cleared by software. It defines the number of input samples that are skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 and DFLTEN = 1. If SKPBF = 1, the value written into the register is ignored by the delay state machine. ... 0 7 read-write SKPBF Skip busy flag This bit is set and cleared by hardware. It is used to control if the delay sequence is completed. 31 1 read-only DFLT0IER DFLT0IER ADF DFLT0 interrupt enable register 0xAC 0x20 0x00000000 0xFFFFFFFF FTHIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 0 1 read-write DOVRIE Data overflow interrupt enable This bit is set and cleared by software. 1 1 read-write SATIE Saturation detection interrupt enable This bit is set and cleared by software. 9 1 read-write CKABIE Clock absence detection interrupt enable This bit is set and cleared by software. 10 1 read-write RFOVRIE Reshape filter overrun interrupt enable This bit is set and cleared by software. 11 1 read-write SDDETIE Sound activity detection interrupt enable This bit is set and cleared by software. 12 1 read-write SDLVLIE SAD sound-level value ready enable This bit is set and cleared by software. 13 1 read-write DFLT0ISR DFLT0ISR ADF DFLT0 interrupt status register 0 0xB0 0x20 0x00000000 0xFFFFFFFF FTHF RXFIFO threshold flag This bit is set by hardware, and cleared by the hardware when the RXFIFO level is lower than the threshold. 0 1 read-only DOVRF Data overflow flag This bit is set by hardware and cleared by software by writing this bit to 1. 1 1 read-write RXNEF RXFIFO not empty flag This bit is set and cleared by hardware according to the RXFIFO level. 3 1 read-only SATF Saturation detection flag This bit is set by hardware and cleared by software by writing this bit to 1. 9 1 read-write CKABF Clock absence detection flag This bit is set by hardware and cleared by software by writing this bit to 1. 10 1 read-write RFOVRF Reshape filter overrun detection flag This bit is set by hardware and cleared by software by writing this bit to 1. 11 1 read-write SDDETF Sound activity detection flag This bit is set by hardware and cleared by software by writing this bit to 1. 12 1 read-write SDLVLF Sound level value ready flag This bit is set by hardware and cleared by software by writing this bit to 1. 13 1 read-write SADCR SADCR ADF SAD control register 0xB8 0x20 0x00000000 0xFFFFFFFF SADEN Sound activity detector enable This bit is set and cleared by software. It is used to enable/disable the SAD. 0 1 read-write DATCAP Data capture mode This field is set and cleared by software. It is used to define in which conditions, the samples provided by DLFT0 are stored into the memory. 1x: Samples from DFLT0 transfered into memory when SAD and DFLT0 are enabled Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 1 2 read-write DETCFG Sound trigger event configuration This bit is set and cleared by software. It is used to define if the sddet_evt event is generated only when the SAD enters to MONITOR state or when the SAD enters or exits the DETECT state. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 3 1 read-write SADST SAD state This field is set and cleared by hardware. It indicates the SAD state and is meaningful only when SADEN = 1. The SAD state can be: - LEARN when the SAD is in learning phase or in SDLVL computation mode - MONITOR when the SAD is in monitoring phase - DETECT when the SAD detects a sound 4 2 read-only HYSTEN Hysteresis enable This bit is set and cleared by software. It is used to enable/disable the hysteresis function (see Table 419 for details). This bit must be kept to 0 when SADMOD[1:0] = 1x. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 7 1 read-write FRSIZE Frame size This field is set and cleared by software. it is used to define the size of one frame and also to define how many samples are taken into account to compute the short-term signal level. 11x: 512 PCM samples used to compute the short-term signal level Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 8 3 read-write SADMOD SAD working mode This field is set and cleared by software. It is used to define the way the SAD works. The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a voice activity detector. The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a sound detector. 1x: Threshold value given by 4 x ANMIN[12:0] The SAD triggers when the estimated ambient noise (ANLVL), multiplied by the gain selected by SNTHR[3:0] is bigger than the defined threshold. In this mode, the SAD is working like an ambient noise estimator. Hysteresis function cannot be used in this mode. Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 12 2 read-write SADACTIVE SAD Active flag This bit is set and cleared by hardware. It is used to check if the SAD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the SADACTIVE is set to 0 (see Section 46.4.13: Register protection for details). The delay between a transition on SADEN and a transition on SADACTIVE is two periods of AHB clock and two periods of adf_proc_ck. 31 1 read-only SADCFGR SADCFGR ADF SAD configuration register 0xBC 0x20 0x00000000 0xFFFFFFFF SNTHR Signal to noise threshold This field is set and cleared by software. It is used to define THRH (and THRL if hysteresis is enabled). See Table 419 for details. others: Reserved Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 0 4 read-write ANSLP Ambient noise slope control This field is set and cleared by software. It is used to define the positive and negative slope of the noise estimator, in charge of updating the ANLVL (see Ambient noise estimation (ANLVL) for information about programming this field). Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 4 3 read-write LFRNB Number of learning frames This field is set and cleared by software. It is used to define the number of learning frames to perform the first estimate of the noise level. 1xx: 32 frames used to compute the initial noise level Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 8 3 read-write HGOVR Hangover time window This field is set and cleared by software. Once the SAD state is DETECT, this parameter is used to define the amount of time the sound is allowed to remain below the threshold, before switching the SAD to MONITOR state (see FRSIZE field for the description of a frame). Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 12 3 read-write ANMIN Minimum noise level This field is set and cleared by software. It is used to define the minimum noise level and then the sensitivity. It represents a positive number. Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 16 13 read-write SADSDLVR SADSDLVR ADF SAD sound level register 0xC0 0x20 0x00000000 0xFFFFFFFF SDLVL Short term sound level This field is set by hardware. It contains the latest sound level computed by the SAD. To refresh this value, SDLVLF must be cleared. 0 15 read-only SADANLVR SADANLVR ADF SAD ambient noise level register 0xC4 0x20 0x00000000 0xFFFFFFFF ANLVL Ambient noise level estimation This field is set by hardware. It contains the latest ambient noise level computed by the SAD. To refresh this field, the SDLVLF flag must be cleared. 0 15 read-only DFLT0DR DFLT0DR ADF digital filter data register 0 0xF0 0x20 0x00000000 0xFFFFFFFF DR Data processed by DFT0 8 24 read-only CEC HDMI-CEC controller CEC 0x40006C00 0x0 0x18 registers CEC CEC global interrupt 129 CR CR CEC control register 0x0 0x20 0x00000000 0xFFFFFFFF CECEN CEC enable The CECEN bit is set and cleared by software. CECEN = 1 starts message reception and enables the TXSOM control. CECEN = 0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission. 0 1 read-write TXSOM Tx start of message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission starts after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND = 1), in case of transmission underrun (TXUDR = 1), negative acknowledge (TXACKE = 1), and transmission error (TXERR = 1). It is also cleared by CECEN = 0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST = 1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN = 1. Note: TXSOM must be set when transmission data is available into TXDR. Note: HEADER first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR that is used only for reception. 1 1 read-write TXEOM Tx end of message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN = 1. Note: TXEOM must be set before writing transmission data to TXDR. Note: If TXEOM is set when TXSOM = 0, transmitted message consists of 1 byte (HEADER) only (PING message). 2 1 read-write CFGR CFGR CEC configuration register 0x4 0x20 0x00000000 0xFFFFFFFF SFT Signal free time SFT bits are set by software. In the SFT = 0x0 configuration, the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. 0x0 2.5 data-bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST = 1, TXERR = 1, TXUDR = 1 or TXACKE = 1) 4 data-bit periods if CEC is the new bus initiator 6 data-bit periods if CEC is the last bus initiator with successful transmission (TXEOM = 1) 0 3 read-write RXTOL Rx-tolerance The RXTOL bit is set and cleared by software. Start-bit, +/- 200 s rise, +/- 200 s fall Data-bit: +/- 200 s rise. +/- 350 s fall Start-bit: +/- 400 s rise, +/- 400 s fall Data-bit: +/-300 s rise, +/- 500 s fall 3 1 read-write BRESTP Rx-stop on bit rising error The BRESTP bit is set and cleared by software. 4 1 read-write BREGEN Generate error-bit on bit rising error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN = 0, an error-bit is generated upon BRE detection with BRESTP = 1 in broadcast even if BREGEN = 0. 5 1 read-write LBPEGEN Generate error-bit on long bit period error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN = 0, an error-bit is generated upon LBPE detection in broadcast even if LBPEGEN = 0. 6 1 read-write BRDNOGEN Avoid error-bit generation in broadcast The BRDNOGEN bit is set and cleared by software. error-bit on the CEC line. LBPE detection with LBPEGEN = 0 on a broadcast message generates an error-bit on the CEC line. 7 1 read-write SFTOP SFT option bit The SFTOPT bit is set and cleared by software. 8 1 read-write OAR Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN = 1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received. 16 15 read-write LSTN Listen mode LSTN bit is set and cleared by software. 31 1 read-write TXDR TXDR CEC Tx data register 0x8 0x20 0x00000000 0xFFFFFFFF TXD Tx data TXD is a write-only register containing the data byte to be transmitted. 0 8 write-only RXDR RXDR CEC Rx data register 0xC 0x20 0x00000000 0xFFFFFFFF RXD Rx data RXD is read-only and contains the last data byte that has been received from the CEC line. 0 8 read-only ISR ISR CEC interrupt and status register 0x10 0x20 0x00000000 0xFFFFFFFF RXBR Rx-byte received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1. 0 1 read-write RXEND End of reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1. 1 1 read-write RXOVR Rx-overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1. 2 1 read-write BRE Rx-bit rising error BRE is set by hardware in case a data-bit waveform is detected with bit rising error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP = 1. BRE generates an error-bit on the CEC line if BREGEN = 1. BRE is cleared by software write at 1. 3 1 read-write SBPE Rx-short bit period error SBPE is set by hardware in case a data-bit waveform is detected with short bit period error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an error-bit on the CEC line. SBPE is cleared by software write at 1. 4 1 read-write LBPE Rx-long bit period error LBPE is set by hardware in case a data-bit waveform is detected with long bit period error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an error-bit on the CEC line if LBPEGEN = 1. In case of broadcast, error-bit is generated even in case of LBPEGEN = 0. LBPE is cleared by software write at 1. 5 1 read-write RXACKE Rx-missing acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1. 6 1 read-write ARBLST Arbitration lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1. 7 1 read-write TXBR Tx-byte request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within six nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1. 8 1 read-write TXEND End of transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1. 9 1 read-write TXUDR Tx-buffer underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1 10 1 read-write TXERR Tx-error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1. 11 1 read-write TXACKE Tx-missing acknowledge error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1. 12 1 read-write IER IER CEC interrupt enable register 0x14 0x20 0x00000000 0xFFFFFFFF RXBRIE Rx-byte received interrupt enable The RXBRIE bit is set and cleared by software. 0 1 read-write RXENDIE End of reception interrupt enable The RXENDIE bit is set and cleared by software. 1 1 read-write RXOVRIE Rx-buffer overrun interrupt enable The RXOVRIE bit is set and cleared by software. 2 1 read-write BREIE Bit rising error interrupt enable The BREIE bit is set and cleared by software. 3 1 read-write SBPEIE Short bit period error interrupt enable The SBPEIE bit is set and cleared by software. 4 1 read-write LBPEIE Long bit period error interrupt enable The LBPEIE bit is set and cleared by software. 5 1 read-write RXACKIE Rx-missing acknowledge error interrupt enable The RXACKIE bit is set and cleared by software. 6 1 read-write ARBLSTIE Arbitration lost interrupt enable The ARBLSTIE bit is set and cleared by software. 7 1 read-write TXBRIE Tx-byte request interrupt enable The TXBRIE bit is set and cleared by software. 8 1 read-write TXENDIE Tx-end of message interrupt enable The TXENDIE bit is set and cleared by software. 9 1 read-write TXUDRIE Tx-underrun interrupt enable The TXUDRIE bit is set and cleared by software. 10 1 read-write TXERRIE Tx-error interrupt enable The TXERRIE bit is set and cleared by software. 11 1 read-write TXACKIE Tx-missing acknowledge error interrupt enable The TXACKEIE bit is set and cleared by software. 12 1 read-write CORDIC CORDIC register block CORDIC 0x48004400 0x0 0x100 registers CORDIC CORDIC interrupt 93 CSR CSR CORDIC control/status register 0x0 0x20 0x00000050 0xFFFFFFFF FUNC Function 10 to 15: reserved 0 4 read-write PRECISION Precision required (number of iterations) 1 to 15: (Number of iterations)/4 To determine the number of iterations needed for a given accuracy refer to Table 193. Note that for most functions, the recommended range for this field is 3 to 6. 4 4 read-write SCALE Scaling factor The value of this field indicates the scaling factor applied to the arguments and/or results. A value n implies that the arguments have been multiplied by a factor 2-n, and/or the results need to be multiplied by 2n. Refer to Section 24.3.2 for the applicability of the scaling factor for each function and the appropriate range. 8 3 read-write IEN Enable interrupt. This bit is set and cleared by software. A read returns the current state of the bit. 16 1 read-write DMAREN Enable DMA read channel This bit is set and cleared by software. A read returns the current state of the bit. 17 1 read-write DMAWEN Enable DMA write channel This bit is set and cleared by software. A read returns the current state of the bit. 18 1 read-write NRES Number of results in the CORDIC_RDATA register Reads return the current state of the bit. 19 1 read-write NARGS Number of arguments expected by the CORDIC_WDATA register Reads return the current state of the bit. 20 1 read-write RESSIZE Width of output data RESSIZE selects the number of bits used to represent output data. If 32-bit data is selected, the CORDIC_RDATA register contains results in q1.31 format. If 16-bit data is selected, the least significant half-word of CORDIC_RDATA contains the primary result (RES1) in q1.15 format, and the most significant half-word contains the secondary result (RES2), also in q1.15 format. 21 1 read-write ARGSIZE Width of input data ARGSIZE selects the number of bits used to represent input data. If 32-bit data is selected, the CORDIC_WDATA register expects arguments in q1.31 format. If 16-bit data is selected, the CORDIC_WDATA register expects arguments in q1.15 format. The primary argument (ARG1) is written to the least significant half-word, and the secondary argument (ARG2) to the most significant half-word. 22 1 read-write RRDY Result ready flag This bit is set by hardware when a CORDIC operation completes. It is reset by hardware when the CORDIC_RDATA register is read (NRES+1) times. When this bit is set, if the IEN bit is also set, the CORDIC interrupt is asserted. If the DMAREN bit is set, a DMA read channel request is generated. While this bit is set, no new calculation is started. 31 1 read-only WDATA WDATA CORDIC argument register 0x4 0x20 0x00000000 0x00000000 ARG Function input arguments This register is programmed with the input arguments for the function selected in the CORDIC_CSR register FUNC field. If 32-bit format is selected (CORDIC_CSR.ARGSIZE = 0) and two input arguments are required (CORDIC_CSR.NARGS = 1), two successive writes are required to this register. The first writes the primary argument (ARG1), the second writes the secondary argument (ARG2). If 32-bit format is selected and only one input argument is required (NARGS = 0), only one write is required to this register, containing the primary argument (ARG1). If 16-bit format is selected (CORDIC_CSR.ARGSIZE = 1), one write to this register contains both arguments. The primary argument (ARG1) is in the lower half, ARG[15:0], and the secondary argument (ARG2) is in the upper half, ARG[31:16]. In this case, NARGS must be set to 0. Refer to Section 24.3.2 for the arguments required by each function, and their permitted range. When the required number of arguments has been written, the CORDIC evaluates the function designated by CORDIC_CSR.FUNC using the supplied input arguments, provided any previous calculation has completed. If a calculation is ongoing, the ARG1 and ARG 2 values are held pending until the calculation is completed and the results read. During this time, a write to the register cancels the pending operation and overwrite the argument data. 0 32 write-only RDATA RDATA CORDIC result register 0x8 0x20 0x00000000 0xFFFFFFFF RES Function result If 32-bit format is selected (CORDIC_CSR.RESSIZE = 0) and two output values are expected (CORDIC_CSR.NRES = 1), this register must be read twice when the RRDY flag is set. The first read fetches the primary result (RES1). The second read fetches the secondary result (RES2) and resets RRDY. If 32-bit format is selected and only one output value is expected (NRES = 0), only one read of this register is required to fetch the primary result (RES1) and reset the RRDY flag. If 16-bit format is selected (CORDIC_CSR.RESSIZE = 1), this register contains the primary result (RES1) in the lower half, RES[15:0], and the secondary result (RES2) in the upper half, RES[31:16]. In this case, NRES must be set to 0, and only one read performed. A read from this register resets the RRDY flag in the CORDIC_CSR register. 0 32 read-only CRC Cyclic redundancy check calculation unit CRC 0x58024C00 0x0 0x18 registers DR DR CRC data register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF DR Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. 0 32 read-write 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR CRC independent data register 0x4 0x20 0x00000000 0xFFFFFFFF IDR General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register 0 32 read-write 0 4294967295 CR CR CRC control register 0x8 0x20 0x00000000 0xFFFFFFFF RESET RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 0 1 read-write RESETW write Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 POLYSIZE Polynomial size These bits control the size of the polynomial. 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 REV_IN Reverse input data This bitfield controls the reversal of the bit order of the input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 REV_OUT Reverse output data This bit controls the reversal of the bit order of the output data. 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 INIT INIT CRC initial value 0x10 0x20 0xFFFFFFFF 0xFFFFFFFF INIT Programmable initial CRC value This register is used to write the CRC initial value. 0 32 read-write 0 4294967295 POL POL CRC polynomial 0x14 0x20 0x04C11DB7 0xFFFFFFFF POL Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. 0 32 read-write 0 4294967295 CRS Clock Recovery System CRS 0x40008400 0x0 0x400 registers CRS CRS global interrupt 127 CR CR CRS control register 0x0 0x20 0x00002000 0xFFFFFFFF SYNCOKIE SYNC event OK interrupt enable 0 1 read-write SYNCOKIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 SYNCWARNIE SYNC warning interrupt enable 1 1 read-write ERRIE Synchronization or trimming error interrupt enable 2 1 read-write ESYNCIE Expected SYNC interrupt enable 3 1 read-write CEN Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. 5 1 read-write CEN Disabled Frequency error counter disabled 0 Enabled Frequency error counter enabled 1 AUTOTRIMEN Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section 7.5.3 for more details. 6 1 read-write AUTOTRIMEN Disabled Automatic trimming disabled 0 Enabled Automatic trimming enabled 1 SWSYNC Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. 7 1 read-write SWSYNC Sync A software sync is generated 1 TRIM HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48 oscillator. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is specified in the product datasheet. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. 8 6 read-write 0 63 CFGR CFGR CRS configuration register 0x4 0x20 0x2022BB7F 0xFFFFFFFF RELOAD Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section 7.5.2 for more details about counter behavior. 0 16 read-write 0 65535 FELIM Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 7.5.3 for more details about FECAP evaluation. 16 8 read-write 0 255 SYNCDIV SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 24 3 read-write SYNCDIV Div1 SYNC not divided 0 Div2 SYNC divided by 2 1 Div4 SYNC divided by 4 2 Div8 SYNC divided by 8 3 Div16 SYNC divided by 16 4 Div32 SYNC divided by 32 5 Div64 SYNC divided by 64 6 Div128 SYNC divided by 128 7 SYNCSRC SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE clock or the SYNC pin must be used as SYNC signal. 28 2 read-write SYNCSRC GPIO_AF GPIO AF (crs_sync_in_1) selected as SYNC signal source 0 LSE LSE (crs_sync_in_2) selected as SYNC signal source 1 USB_SOF USB SOF (crs_sync_in_3) selected as SYNC signal source 2 SYNCPOL SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. 31 1 read-write SYNCPOL RisingEdge SYNC active on rising edge 0 FallingEdge SYNC active on falling edge 1 ISR ISR CRS interrupt and status register 0x8 0x20 0x00000000 0xFFFFFFFF SYNCOKF SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. 0 1 read-only SYNCOKF NotSignaled Signal not set 0 Signaled Signal set 1 SYNCWARNF SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. 1 1 read-only ERRF Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. 2 1 read-only ESYNCF Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. 3 1 read-only SYNCERR SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action has to be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 8 1 read-only SYNCMISS SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action has to be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 9 1 read-only TRIMOVF Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 10 1 read-only FEDIR Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. 15 1 read-only FEDIR UpCounting Error in up-counting direction 0 DownCounting Error in down-counting direction 1 FECAP Frequency error capture FECAP is the frequency error counter value latched in the time of the last SYNC event. Refer to Section 7.5.3 for more details about FECAP usage. 16 16 read-only 0 65535 ICR ICR CRS interrupt flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF SYNCOKC SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. 0 1 read-write SYNCOKC Clear Clear flag 1 SYNCWARNC SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. 1 1 read-write ERRC Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. 2 1 read-write ESYNCC Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. 3 1 read-write CRYP Cryptographic processor CRYP 0x48020800 0x0 0x400 registers CR CR CRYP control register 0x0 0x20 0x00000000 0xFFFFFFFF ALGODIR Algorithm direction This bit selects the algorithm direction. Attempts to write the bitfield are ignored when BUSY is set. 2 1 read-write ALGOMODE ALGOMODE[2:0]: Algorithm mode This bitfield selects the AES algorithm/chaining mode. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set. 3 3 read-write DATATYPE Data type This bitfield defines the format of data written in the CRYP_DINR register or read from the CRYP_DOUTR register, through selecting the mode of data swapping. This swapping is defined in Section 60.4.15: CRYP data registers and data swapping. Attempts to write the bitfield are ignored when BUSY is set. 6 2 read-write KEYSIZE Key size selection This bitfield defines the key length in bits of the key used by CRYP. When KEYSIZE is changed, KEYVALID bit is cleared. Attempts to write the bitfield are ignored when BUSY is set. 8 2 read-write FFLUSH FIFO flush This bit enables/disables the flushing of CRYP input and output FIFOs. Reading this bit always returns 0. When CRYPEN is cleared, writing this bit to 1 flushes both input and output FIFOs (that is read and write pointers of the FIFOs are reset). FFLUSH bit must be set when BUSY is cleared, otherwise the FIFO is flushed, but the block being processed may be pushed into the output FIFO just after the flush operation, resulting in a non-empty FIFO condition. Attempts to write FFLUSH are ignored when CRYPEN is set. 14 1 read-write CRYPEN CRYP enable This bit enables/disables the CRYP peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (ALGOMODE[3:0] at 0x7) and upon the completion of GCM/GMAC/CCM initialization phase. The bit cannot be set as long as KEYVALID is cleared. 15 1 read-write GCM_CCMPH GCM or CCM phase selection This bitfield selects the phase, applicable only with GCM, GMAC or CCM chaining modes. Attempts to write the bitfield are ignored when BUSY is set. 16 2 read-write ALGOMODE_1 ALGOMODE[3] 19 1 read-write NPBLB Number of padding bytes in last block This padding information must be filled by software before processing the last block of GCM payload encryption or CCM payload decryption, otherwise authentication tag computation is incorrect. ... Attempts to write the bitfield are ignored when BUSY is set. 20 4 read-write KMOD Key mode selection This bitfield defines how the CRYP key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set. 24 2 read-write IPRST CRYP peripheral software reset Setting the bit resets the CRYP peripheral, putting all registers to their default values, except the IPRST bit itself. This bit must be kept cleared while writing any configuration registers. 31 1 read-write SR SR CRYP status register 0x4 0x20 0x00000003 0xFFFFFFFF IFEM Input FIFO empty flag 0 1 read-only IFNF Input FIFO not full flag 1 1 read-only OFNE Output FIFO not empty flag 2 1 read-only OFFU Output FIFO full flag 3 1 read-only BUSY Busy bit This flag indicates whether CRYP is idle or busy. CRYP is flagged as idle when disabled (CRYPEN = 0) or when the AES core is not processing any data. It happens when the last processing has completed, or CRYP is waiting for enough data in the input FIFO or enough free space in the output FIFO (that is in each case at least 4 words). CRYP is flagged as busy when processing a block data, preparing a key (ECB or CBC decryption only), or transferring a shared key from SAES peripheral. 4 1 read-only KERF Key error flag This read-only bit is set by hardware when key information failed to load into key registers. KERF is triggered upon any of the following errors: CRYP_KxR/LR register write does not respect the correct order (refer to Section 60.4.16: CRYP key registers for details). CRYP fails to load the key shared by SAES peripheral (KMOD = 0x2). KERF must be cleared by the application software, otherwise KEYVALID cannot be set. It can be done through IPRST bit of CRYP_CR, or when a correct key writing sequence starts. 6 1 read-only KEYVALID Key valid flag This read-only bit is set by hardware when the key of size defined by KEYSIZE is loaded in CRYP_KxR/LR key registers. The CRYPEN bit can only be set when KEYVALID is set. In normal mode when KMOD[1:0] is at zero, the key must be written in the key registers in the correct sequence, otherwise the KERF flag is set and KEYVALID remains cleared. When KMOD[1:0] is different from zero, the BUSY flag is automatically set by CRYP. When the key is loaded successfully, BUSY is cleared and KEYVALID set. Upon an error, KERF is set, BUSY cleared and KEYVALID remains cleared. If set, KERF must be cleared, otherwise KEYVALID cannot be set. For further information on key loading, refer to Section 60.4.16: CRYP key registers. 7 1 read-only DINR DINR CRYP data input register 0x8 0x20 0x00000000 0xFFFFFFFF DIN Data input A four-fold sequential write to this bitfield during the Input phase results in pushing a complete 16-byte block into the CRYP input FIFO. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Input FIFO can receive up to two 16-byte blocks of plaintext (when encrypting) or ciphertext (when decrypting). If EN bit is set in CRYP_CR register, when at least four 32-bit words have been pushed into the input FIFO, and when at least four 32-bit words are free in the output FIFO, the CRYP automatically starts an encryption or decryption process, setting the BUSY bit. Reading this register pops data off the input FIFO (oldest value is returned). The data present in the input FIFO are returned only if CRYPEN is cleared (undefined value is returned otherwise). Following one or more reads the FIFO must be flushed (setting the FFLUSH bit) prior to processing new data. 0 32 read-write DOUTR DOUTR CRYP data output register 0xC 0x20 0x00000000 0xFFFFFFFF DOUT Data output A four-fold sequential read to this bitfield during the output phase results in retrieving a complete 16-byte block from the CRYP output FIFO. From the first to the fourth read, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Output FIFO can store up to two 16-byte blocks of plaintext (when decrypting) or ciphertext (when encrypting). When the output FIFO is empty a read returns an undefined value. Writes are ignored. 0 32 read-only DMACR DMACR CRYP DMA control register 0x10 0x20 0x00000000 0xFFFFFFFF DIEN DMA input enable When this bit is set, DMA requests are automatically generated by the peripheral during the input data phase. 0 1 read-write DOEN DMA output enable When this bit is set, DMA requests are automatically generated by the peripheral during the output data phase. 1 1 read-write IMSCR IMSCR CRYP interrupt mask set/clear register 0x14 0x20 0x00000000 0xFFFFFFFF INIM Input FIFO service interrupt mask This bit enables or disables (masks) the CRYP input FIFO service interrupt generation when INRIS is set. 0 1 read-write OUTIM Output FIFO service interrupt mask This bit enables or disables (masks) the CRYP output FIFO service interrupt generation when OUTRIS is set. 1 1 read-write RISR RISR CRYP raw interrupt status register 0x18 0x20 0x00000001 0xFFFFFFFF INRIS Input FIFO service raw interrupt status This read-only bit is set by hardware when an input FIFO flag (IFNF or IFEM) is set in CRYP_SR register, regardless of the INIM mask bit value in CRYP_IMSCR register. 0 1 read-only OUTRIS Output FIFO service raw interrupt status This read-only bit is set by hardware when an output FIFO flag (OFFU or OFNE) is set in CRYP_SR register, regardless of the OUTIM mask bit value in CRYP_IMSCR register. 1 1 read-only MISR MISR CRYP masked interrupt status register 0x1C 0x20 0x00000000 0xFFFFFFFF INMIS Input FIFO service masked interrupt status This read-only bit is set by hardware when an input FIFO flag (IFNF or IFEM) is set in CRYP_SR register. If the INIM mask bit is cleared in CRYP_IMSCR register, the INMIS bit stays cleared (masked). The INMIS bit is cleared by writing data to the input FIFO until IFEM flag is cleared (there is at least one word in input FIFO), or by clearing CRYPEN, When CRYP is disabled, INMIS bit stays low even if the input FIFO is empty. 0 1 read-only OUTMIS Output FIFO service masked interrupt status This read-only bit is set by hardware when an output FIFO flag (OFFU or OFNE) is set in CRYP_SR register. If the OUTIM mask bit is cleared in CRYP_IMSCR register, the OUTMIS bit stays cleared (masked). The OUTMIS bit is cleared by reading data from the output FIFO until OFNE flag is cleared (output FIFO empty). It is not cleared by disabling CRYP with CRYPEN bit. 1 1 read-only 4 0x8 0-3 KEY%s Cluster KEY%s, containing K?LR, K?RR 0x20 KLR K0LR CRYP key register 0L 0x0 0x20 0x00000000 0xFFFFFFFF K Key bit x This write-only bitfield contains the bits [255:224] of the AES encryption or decryption key, depending on the operating mode. Write to CRYP_KxR/LR registers is ignored when CRYP is busy (BUSY bit set). When key is coming from the SAES peripheral (KMOD[1:0] = 0x2), write is also ignored. With KMOD[1:0] at 0x0, a special writing sequence is required. In this sequence, any valid write to CRYP_KxR/LR register clears the KEYVALID flag except for the sequence-completing write that sets it. Also refer to the description of the KEYVALID flag in the CRYP_SR register. 0 32 write-only KRR K0RR CRYP key register 0R 0x4 0x20 0x00000000 0xFFFFFFFF K Key bit x This write-only bitfield contains the bits [223:192] of the AES encryption or decryption key, depending on the operating mode. Refer to the CRYP_K0LR register for information relative to writing CRYP_KxR/LR registers. 0 32 write-only 2 0x8 0-1 INIT%s Cluster INIT%s, containing IV?LR, IV?RR 0x40 IVLR IV0LR CRYP initialization vector register 0L 0x0 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector bit x This bitfield stores the initialization vector bits [127:96] for AES chaining modes other than ECB. The value stored in CRYP_IVxR/LR registers is updated by hardware after each computation round (when applicable). Write to this register is ignored when CRYP is busy (BUSY bit set). 0 32 read-write IVRR IV0RR CRYP initialization vector register 0R 0x4 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector bit x This bitfield stores the initialization vector bits [95:64] for AES chaining modes other than ECB. The value stored in CRYP_IVxR/LR registers is updated by hardware after each computation round (when applicable). Write to this register is ignored when CRYP is busy (BUSY bit set). 0 32 read-write 8 0x4 0-7 CSGCMCCM%sR CSGCMCCM%sR CRYP context swap GCM-CCM registers 0x50 0x20 0x00000000 0xFFFFFFFF CSGCMCCM Context swap for GCM/GMAC and CCM modes CRYP_CSGCMCCMxR registers contain the complete internal register states of the CRYP when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section 60.4.8: CRYP suspend and resume operations for more details. CRYP_CSGCMCCMxR registers are not used in other chaining modes than GCM, GMAC or CCM. 0 32 read-write 8 0x4 0-7 CSGCM%sR CSGCM%sR CRYP context swap GCM registers 0x70 0x20 0x00000000 0xFFFFFFFF CSGCM Context swap for GCM/GMAC modes CRYP_CSGCMxR registers contain the complete internal register states of the CRYP when the GCM or GMAC processing of the current task is suspended to process a higher-priority task. Refer to Section 60.4.8: CRYP suspend and resume operations for more details. CRYP_CSGCMxR registers are not used in other chaining modes than GCM or GMAC. 0 32 read-write DBGMCU Microcontroller debug unit DBGMCU 0x5C001000 0x0 0x1000 registers IDC IDC DBGMCU identity code register 0x0 0x20 0x00006485 0x0000FFFF DEV_ID Device ID 0 12 read-only REV_ID Revision 16 16 read-only CR CR DBGMCU configuration register 0x4 0x20 0x00000000 0xFFFFFFFF DBGSLEEP Debug in Sleep mode enable 0 1 read-write DBGSTOP Debug in Stop mode enable 1 1 read-write DBGSTBY Debug in Standby mode enable 2 1 read-write DCRT Debug credentials reset type This bit selects which type of reset is used to revoke the debug authentication credentials 16 1 read-write TRACECLKEN Trace port clock enable. This bit enables the trace port clock, TRACECLK. 20 1 read-write D1DBGCKEN D1 debug clock enable This bit allows the debug components in the D1 clock domain (excluding those in the processor core) to be switched off if they are not needed. 21 1 read-write TRGOEN External trigger output enable This bit controls the direction of the bi-directional trigger pin, TRGIO. 28 1 read-write AHB5FZR AHB5FZR DBGMCU AHB5 peripheral freeze register 0x20 0x20 0x00000000 0xFFFFFFFF DBG_HPDMA_0_STOP HPDMA channel 0 stop in debug 0 1 read-write DBG_HPDMA_1_STOP HPDMA channel 1 stop in debug 1 1 read-write DBG_HPDMA_2_STOP HPDMA channel 2 stop in debug 2 1 read-write DBG_HPDMA_3_STOP HPDMA channel 3 stop in debug 3 1 read-write DBG_HPDMA_4_STOP HPDMA channel 4 stop in debug 4 1 read-write DBG_HPDMA_5_STOP HPDMA channel 5 stop in debug 5 1 read-write DBG_HPDMA_6_STOP HPDMA channel 6 stop in debug 6 1 read-write DBG_HPDMA_7_STOP HPDMA channel 7 stop in debug 7 1 read-write DBG_HPDMA_8_STOP HPDMA channel 8 stop in debug 8 1 read-write DBG_HPDMA_9_STOP HPDMA channel 9 stop in debug 9 1 read-write DBG_HPDMA_10_STOP HPDMA channel 10 stop in debug 10 1 read-write DBG_HPDMA_11_STOP HPDMA channel 11 stop in debug 11 1 read-write DBG_HPDMA_12_STOP HPDMA channel 12 stop in debug 12 1 read-write DBG_HPDMA_13_STOP HPDMA channel 13 stop in debug 13 1 read-write DBG_HPDMA_14_STOP HPDMA channel 14 stop in debug 14 1 read-write DBG_HPDMA_15_STOP HPDMA channel 15 stop in debug 15 1 read-write AHB1FZR AHB1FZR DBGMCU AHB1 peripheral freeze register 0x24 0x20 0x00000000 0xFFFFFFFF DBG_GPDMA_0_STOP GPDMA channel 0 stop in debug 0 1 read-write DBG_GPDMA_1_STOP GPDMA channel 1 stop in debug 1 1 read-write DBG_GPDMA_2_STOP GPDMA channel 2 stop in debug 2 1 read-write DBG_GPDMA_3_STOP GPDMA channel 3 stop in debug 3 1 read-write DBG_GPDMA_4_STOP GPDMA channel 4 stop in debug 4 1 read-write DBG_GPDMA_5_STOP GPDMA channel 5 stop in debug 5 1 read-write DBG_GPDMA_6_STOP GPDMA channel 6 stop in debug 6 1 read-write DBG_GPDMA_7_STOP GPDMA channel 7 stop in debug 7 1 read-write DBG_GPDMA_8_STOP GPDMA channel 8 stop in debug 8 1 read-write DBG_GPDMA_9_STOP GPDMA channel 9 stop in debug 9 1 read-write DBG_GPDMA_10_STOP GPDMA channel 10 stop in debug 10 1 read-write DBG_GPDMA_11_STOP GPDMA channel 11 stop in debug 11 1 read-write DBG_GPDMA_12_STOP GPDMA channel 12 stop in debug 12 1 read-write DBG_GPDMA_13_STOP GPDMA channel 13 stop in debug 13 1 read-write DBG_GPDMA_14_STOP GPDMA channel 14 stop in debug 14 1 read-write DBG_GPDMA_15_STOP GPDMA channel 15 stop in debug 15 1 read-write APB1FZR APB1FZR DBGMCU APB1 peripheral freeze register 0x3C 0x20 0x00000000 0xFFFFFFFF TIM2 TIM2 stop in debug 0 1 read-write TIM3 TIM3 stop in debug 1 1 read-write TIM4 TIM4 stop in debug 2 1 read-write TIM5 TIM5 stop in debug 3 1 read-write TIM6 TIM6 stop in debug 4 1 read-write TIM7 TIM7 stop in debug 5 1 read-write TIM12 TIM12 stop in debug 6 1 read-write TIM13 TIM13 stop in debug 7 1 read-write TIM14 TIM14 stop in debug 8 1 read-write LPTIM1 LPTIM1 stop in debug 9 1 read-write WWDG WWDG stop in debug 11 1 read-write I2C1 I2C1 SMBUS timeout stop in debug 21 1 read-write I2C2 I2C2 SMBUS timeout stop in debug 22 1 read-write I2C3 I2C3 SMBUS timeout stop in debug 23 1 read-write APB2FZ APB2FZ DBGMCU APB2 peripheral freeze register 0x4C 0x20 0x00000000 0xFFFFFFFF TIM1 TIM1 stop in debug 0 1 read-write TIM15 TIM15 stop in debug 16 1 read-write TIM16 TIM16 stop in debug 17 1 read-write TIM17 TIM17 stop in debug 18 1 read-write TIM9 TIM9 stop in debug 19 1 read-write APB4FZR APB4FZR DBGMCU APB4 peripheral freeze register 0x54 0x20 0x00000000 0xFFFFFFFF LPTIM2 LPTIM2 stop in debug 9 1 read-write LPTIM3 LPTIM2 stop in debug 10 1 read-write LPTIM4 LPTIM4 stop in debug 11 1 read-write LPTIM5 LPTIM5 stop in debug 12 1 read-write RTC RTC stop in debug 16 1 read-write IWDG Independent watchdog for stop in debug 18 1 read-write SR SR DBGMCU status register 0xFC 0x20 0x00010003 0xFFFFFFFF AP_PRESENT Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) Bit n = 0: APn absent Bit n = 1: APn present 0 16 read-only AP_ENABLED Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) Bit n = 0: APn locked Bit n = 1: APn enabled 16 16 read-only DBG_AUTH_HOST DBG_AUTH_HOST DBGMCU debug authentication mailbox host register 0x100 0x20 0x00000000 0x00000000 MESSAGE Debug host to device mailbox message. During debug authentication the debug host communicates with the device via this register. 0 32 read-write DBG_AUTH_DEVICE DBG_AUTH_DEVICE DBGMCU debug authentication mailbox device register 0x104 0x20 0x00000000 0x00000000 MESSAGE Device to debug host mailbox message. During debug authentication the device communicates with the debug host via this register. 0 32 read-write DBG_AUTH_ACK DBG_AUTH_ACK DBGMCU debug authentication mailbox acknowledge register 0x108 0x20 0x00000000 0xFFFFFFFF HOST_ACK Host to device acknowledge. The device sets this bit to indicate that it has placed a message in the DBGMCU_DBG_AUTH_DEVICE register. It should be reset by the host after reading the message 0 1 read-write DEV_ACK Device to device acknowledge. The host sets this bit to indicate that it has placed a message in the DBGMCU_DBG_AUTH_HOST register. It is reset by the device after reading the message 1 1 read-write PIDR4 PIDR4 DBGMCU peripheral identity register 4 0xFD0 0x20 0x00000000 0xFFFFFFFF JEP106CON JEP106 continuation code 0 4 read-only SIZE Register file size 4 4 read-only PIDR0 PIDR0 DBGMCU peripheral identity register 0 0xFE0 0x20 0x00000000 0xFFFFFFFF PARTNUM Part number field, bits [7:0] 0 8 read-only PIDR1 PIDR1 DBGMCU peripheral identity register 1 0xFE4 0x20 0x00000000 0xFFFFFFFF PARTNUM Part number field, bits [11:8] 0 4 read-only JEP106ID JEP106 identity code field, bits [3:0] 4 4 read-only PIDR2 PIDR2 DBGMCU peripheral identity register 2 0xFE8 0x20 0x0000000A 0xFFFFFFFF JEP106ID JEP106 identity code field, bits [6:4] 0 3 read-only JEDEC JEDEC assigned value 3 1 read-only REVISION Component revision number 4 4 read-only PIDR3 PIDR3 DBGMCU peripheral identity register 3 0xFEC 0x20 0x00000000 0xFFFFFFFF CMOD Customer modified 0 4 read-only REVAND Metal fix version 4 4 read-only CIDR0 CIDR0 DBGMCU component identity register 0xFF0 0x20 0x0000000D 0xFFFFFFFF PREAMBLE Component ID field, bits [7:0] 0 8 read-only CIDR1 CIDR1 DBGMCU component identity register 0xFF4 0x20 0x000000F0 0xFFFFFFFF PREAMBLE Component ID field, bits [11:8] 0 4 read-only CLASS Component ID field, bits [15:12] - component class 4 4 read-only CIDR2 CIDR2 DBGMCU component identity register 0xFF8 0x20 0x00000005 0xFFFFFFFF PREAMBLE Component ID field, bits [23:16] 0 8 read-only CIDR3 CIDR3 DBGMCU component identity register 0xFFC 0x20 0x000000B1 0xFFFFFFFF PREAMBLE Component ID field, bits [31:24] 0 8 read-only DCMIPP Digital camera interface pixel pipeline 0x50002000 0x0 0x1000 registers DCMIPP DCMIPP global interrupt 95 IPGR1 IPGR1 DCMIPP IP-Plug global register 1 0x0 0x20 0x00000002 0xFFFFFFFF MEMORYPAGE Memory page size, as power of 2 of 64-byte units: 0 3 read-write QOS_MODE Quality of service Set of functions enabling to build and configure an architecture able to meet bandwidth and latency requirements. 24 1 read-write IPGR2 IPGR2 DCMIPP IP-Plug global register 2 0x4 0x20 0x00000000 0xFFFFFFFF PSTART Request to lock the IP-Plug, to allow reconfiguration. PSTART must be reset to 0 after configuration is completed, to restart the IP-Plug. 0 1 read-write IPGR3 IPGR3 DCMIPP IP-Plug global register 3 0x8 0x20 0x00000001 0xFFFFFFFF IDLE Status of IP-Plug IDLE is set some time after a request by setting PSTART at 1, and reset by resetting PSTART at 0. 0 1 read-only IPGR8 IPGR8 DCMIPP IP-Plug identification register 0x1C 0x20 0xAA040314 0xFFFFFFFF DID Division identifier (0x14) 0 6 read-only REVID Revision identifier (0x03) 8 5 read-only ARCHIID Architecture identifier (0x04) 16 5 read-only IPPID IP identifier (0xAA) 24 8 read-only IPC1R1 IPC1R1 DCMIPP IP-Plug Clientx register 1 0x20 0x20 0x00000003 0xFFFFFFFF TRAFFIC Burst size as power of 2 of 8-byte units Other values: Reserved 0 3 read-write OTR Maximum outstanding transactions ... Other values are not allowed. 8 2 read-write IPC1R2 IPC1R2 DCMIPP IP-Plug Clientx register 2 0x24 0x20 0x00010000 0xFFFFFFFF SVCMAPPING Non-user, must be kept at reset value. 8 4 read-write WLRU Ratio for WLRU[3:0] arbitration A client gets a portion of the total bandwidth = Ratio(client) / Sum(all ratio) ... 16 4 read-write IPC1R3 IPC1R3 DCMIPP IP-Plug Clientx register 3 0x28 0x20 0x001F0000 0xFFFFFFFF DPREGSTART Start word (AXI width = 64 bits) of the FIFO of Clientx. 0 5 read-write DPREGEND End word (AXI width = 64 bits) of the FIFO of Clientx. The addressed word is included in the FIFO, so that next DPREGSTART is DPREGEND + 1. 16 5 read-write PRCR PRCR DCMIPP parallel interface control register 0x104 0x20 0x00000000 0xFFFFFFFF ESS Embedded synchronization select Valid only for 8-bit parallel data. HSPOL/VSPOL are ignored when this bit is set. 4 1 read-write PCKPOL Pixel clock polarity This bit configures the capture edge of the pixel clock 5 1 read-write HSPOL Horizontal synchronization polarity This bit indicates the level on the HSYNC pin when the data are not valid on the parallel interface. 6 1 read-write VSPOL Vertical synchronization polarity This bit indicates the level on the VSYNC pin when the data are not valid on the parallel interface. 7 1 read-write EDM Extended data mode Other values: Reserved. 10 3 read-write ENABLE Parallel interface enable The parallel interface configuration registers must be correctly programmed before enabling this bit. 14 1 read-write FORMAT Other values: data are captured and output as-is only through the data/dump pipeline (for example JPEG or byte input format). The monochrome Y input is inserted in the pipe as YUV pixels, with the U and V components set to neutral, to represent a grey color. 16 8 read-write SWAPCYCLES Swap data (cycle 0 vs. cycle 1) for pixels received on two cycles The swap must not be activated by software for pixels received in one or three cycles. 25 1 read-write SWAPBITS Swap LSB vs. MSB within each received component 26 1 read-write PRESCR PRESCR DCMIPP parallel interface embedded synchronization code register 0x108 0x20 0x00000000 0xFFFFFFFF FSC Frame start delimiter code This byte specifies the code of the frame start delimiter. The code consists of four bytes in the form of 0xFF, 0x00, 0x00, FSC. If FSC is programmed to 0xFF, no frame start delimiter is detected, but the first occurrence of LSC after an FEC code is interpreted as the start of frame delimiter. 0 8 read-write LSC Line start delimiter code This byte specifies the code of the line start delimiter. The code consists of four bytes in the form of 0xFF, 0x00, 0x00, LSC. 8 8 read-write LEC Line end delimiter code This byte specifies the code of the line end delimiter. The code consists of four bytes in the form of 0xFF, 0x00, 0x00, LEC. 16 8 read-write FEC Frame end delimiter code This byte specifies the code of the frame end delimiter. The code consists of four bytes in the form of 0xFF, 0x00, 0x00, FEC. If FEC is programmed to 0xFF, all the unused codes (0xFF00 00XY) are interpreted as frame end delimiters. 24 8 read-write PRESUR PRESUR DCMIPP parallel interface embedded synchronization unmask register 0x10C 0x20 0x00000000 0xFFFFFFFF FSU Frame start delimiter unmask This byte specifies the mask to be applied to the code of the frame start delimiter. 0 8 read-write LSU Line start delimiter unmask This byte specifies the mask to be applied to the code of the line start delimiter. 8 8 read-write LEU Line end delimiter unmask This byte specifies the mask to be applied to the code of the line end delimiter. 16 8 read-write FEU Frame end delimiter unmask This byte specifies the mask to be applied to the code of the frame end delimiter. 24 8 read-write PRIER PRIER DCMIPP parallel interface interrupt enable register 0x1F4 0x20 0x00000000 0xFFFFFFFF ERRIE Synchronization error interrupt enable This bit is available only in embedded synchronization mode. 6 1 read-write PRSR PRSR DCMIPP parallel interface status register 0x1F8 0x20 0x00030000 0xFFFFFFFF ERRF Synchronization error raw interrupt status This bit is valid only in the embedded synchronization mode. It is cleared by writing a 1 to the CERRF bit in DCMIPP_PRFCR. This bit is available only in embedded synchronization mode. 6 1 read-only HSYNC This bit gives the state of the HSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit, and cleared otherwise. When embedded synchronization codes are used: In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in DCMIPP_CR is set. 16 1 read-only VSYNC This bit gives the state of the VSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit, and cleared otherwise. When embedded synchronization codes are used: In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in DCMIPP_CR is set. 17 1 read-only PRFCR PRFCR DCMIPP parallel interface interrupt clear register 0x1FC 0x20 0x00000000 0xFFFFFFFF CERRF Synchronization error interrupt status clear Writing a 1 into this bit clears the ERRF bit in DCMIPP_PRSR. This bit is available only in embedded synchronization mode. 6 1 write-only CMCR CMCR DCMIPP common configuration register 0x204 0x20 0x00000000 0xFFFFFFFF CFC Clear frame counter When this bit is set, the frame counter associated to a pipe is cleared. It resets DCMIPP_CMFRCR register. This bit is always read at 0. 4 1 write-only CMFRCR CMFRCR DCMIPP common frame counter register 0x208 0x20 0x00000000 0xFFFFFFFF FRMCNT Frame counter, read-only, loops around. Incremented following VSYNC detection mapped to the pipe configured into bits PSFC[1:0] of the DCMIPP_CMCR register. The counter is cleared using the CRC bit in the DCMIPP_CMCR register. 0 32 read-only CMIER CMIER DCMIPP common interrupt enable register 0x3F0 0x20 0x00000000 0xFFFFFFFF ATXERRIE AXI transfer error interrupt enable for IP-Plug 5 1 read-write PRERRIE Limit interrupt enable for the parallel Interface 6 1 read-write P0LINEIE Multi-line capture complete interrupt enable for Pipe0 8 1 read-write P0FRAMEIE Frame capture complete interrupt enable for Pipe0 9 1 read-write P0VSYNCIE Vertical sync interrupt enable for Pipe0 10 1 read-write P0LIMITIE Limit interrupt enable for Pipe0 14 1 read-write P0OVRIE Overrun interrupt enable for Pipe0 15 1 read-write CMSR1 CMSR1 DCMIPP common status register 1 0x3F4 0x20 0x00000003 0xFFFFFFFF PRHSYNC This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit of the DCMIPP_PRCR register, and cleared otherwise. When embedded synchronization codes are used the meaning of this bit is the following: In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in the DCMIPP_PRCR register is set. 0 1 read-only PRVSYNC This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit of the DCMIPP_PRCR register, and cleared otherwise. When embedded synchronization codes are used, the meaning of this bit is the following: In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in the DCMIPP_PRCR register is set. 1 1 read-only P0CPTACT Active frame capture (active from start-of-frame to frame complete) for Pipe0 15 1 read-only CMSR2 CMSR2 DCMIPP common status register 2 0x3F8 0x20 0x00000000 0xFFFFFFFF ATXERRF AXI transfer error interrupt status flag for the IP-Plug. This bit is cleared by writing a 1 to CATXERRF bit in the DCMIPP_CMFCR register. 5 1 read-only PRERRF Synchronization error raw interrupt status for the parallel interface. This bit is valid only in the embedded synchronization mode. It is cleared by writing a 1 to the CPRERRF bit in the DCMIPP_CMFCR register. This bit is available only in embedded synchronization mode. 6 1 read-only P0LINEF Multi-line capture completed raw interrupt status for Pipe0 This bit is set when one/more lines have been completed. The periodicity of LINEF event is configured by LINEMULT bits into DCMIPP_P0PPCR register. When reaching end of frame, this event is triggered out to allow software action even if the LINEMULT value set is not a multiple of the total lines frame. In the case of embedded synchronization, this bit is set only if the CAPTURE bit in the DCMIPP_CR register is set. It is cleared by writing a 1 to the CP0LINEF bit in the DCMIPP_CMFCR register. 8 1 read-only P0FRAMEF Frame capture completed raw interrupt status for Pipe0 This bit is set when all data of a frame or window have been captured. In case of a cropped window, this bit is set at the end of line of the last line in the crop, even if the captured frame is empty (for example window cropped outside the frame). This bit is cleared by writing a 1 to the CP0FRAMEF bit in the DCMIPP_CMFCR register. 9 1 read-only P0VSYNCF VSYNC raw interrupt status for Pipe0 This bit is set when the VSYNC signal changes from the inactive state to the active state. In the case of embedded synchronization, this bit is set only if the CAPTURE bit is set in DCMIPP_CR. It is cleared by writing a 1 to the CP0VSYNCF bit in the DCMIPP_CMFCR register. 10 1 read-only P0LIMITF Limit raw interrupt status for Pipe0 This bit is set when the data counter DCMIPP_P0DCCNT reaches its maximum value DCMIPP_P0DCLIMIT. It is cleared by writing a 1 to the CP0LIMITF bit in the DCMIPP_CMFCR register. 14 1 read-only P0OVRF Overrun raw interrupt status for Pipe0 This bit is cleared by writing a 1 to the CP0OVRF bit in the DCMIPP_CMFCR register. 15 1 read-only CMFCR CMFCR DCMIPP common interrupt clear register 0x3FC 0x20 0x00000000 0xFFFFFFFF CATXERRF AXI transfer error interrupt status clear Writing a 1 into this bit clears the ATXERRF bit in the DCMIPP_CMSR2 register. 5 1 write-only CPRERRF Synchronization error interrupt status clear Writing a 1 into this bit clears the PRERRF bit in the DCMIPP_CMSR2 register. This bit is available only in embedded synchronization mode. 6 1 write-only CP0LINEF Multi-line capture complete interrupt status clear Writing a 1 into this bit clears P0LINEF in the DCMIPP_CMSR2 register 8 1 write-only CP0FRAMEF Frame capture complete interrupt status clear Writing a 1 into this bit clears the P0FRAMEF bit in the DCMIPP_CMSR2 register. 9 1 write-only CP0VSYNCF Vertical synchronization interrupt status clear Writing a 1 into this bit clears the P0VSYNCF bit in the DCMIPP_CMSR2 register. 10 1 write-only CP0LIMITF limit interrupt status clear Writing a 1 into this bit clears P0LIMITF in the DCMIPP_CMSR2 register 14 1 write-only CP0OVRF Overrun interrupt status clear Writing a 1 into this bit clears the P0OVRF bit in the DCMIPP_CMSR2 register 15 1 write-only P0FSCR P0FSCR DCMIPP Pipe0 flow selection configuration register 0x404 0x20 0x00000000 0xFFFFFFFF PIPEN Activation of PipeN Note: This bit is not shadowed, differently from all other bits in this register. 31 1 read-write P0FCTCR P0FCTCR DCMIPP Pipe0 flow control configuration register 0x500 0x20 0x00000000 0xFFFFFFFF FRATE Frame capture rate control These bits define the frequency of frame capture. They are meaningful only in Continuous grab mode, ignored in Snapshot mode. 0 2 read-write CPTMODE Capture mode 2 1 read-write CPTREQ Capture requested When PIPEN = 1 and when the CPTREQ is set to 1 the pipe waits for the first VSync, and automatically starts a capture and sets CPTACT = 1 to mention it. In Snapshot mode the CPTREQ bit is automatically cleared at the start of the first received frame. In Continuous grab mode, the capture remains active and CPTREQ = 1 until the software clears CPTREQ: the capture stops and CPTACT is reset at the end of the ongoing frame. The DCMI and pipe configuration registers must be correctly programmed before enabling this bit. 3 1 read-write P0SCSTR P0SCSTR DCMIPP Pipe0 stat/crop start register 0x504 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 words wide 0 12 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write P0SCSZR P0SCSZR DCMIPP Pipe0 stat/crop size register 0x508 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 word wide (data 32-bit) If the value is maintained at 0 when enabling the crop by means of ENABLE bit, the crop operation is not performed on horizontal direction. 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high If the value is maintained at 0 when enabling the crop by means of ENABLE bit, the crop operation is not performed on vertical direction. 16 12 read-write POSNEG This bit is set and cleared by software. It has a meaning only if ENABLE bit is set. 30 1 read-write ENABLE This bit is set and cleared by software. if POSNEG = 0, the data inside the rectangle area are transmitted (it can correspond to a statistical data removal, or as a crop feature in a data valid image area). if POSNEG = 1, the data outside of the rectangle area are transmitted (it can correspond to a statistical data extraction, rejecting all data inside the window). This bit must be kept cleared if the input format is JPEG, to avoid unpredictable behavior of the pipe. 31 1 read-write P0DCCNTR P0DCCNTR DCMIPP Pipe0 dump counter register 0x5B0 0x20 0x00000000 0xFFFFFFFF CNT Number of data dumped during the frame. The size of the data is expressed in bytes. It counts only the data selected by means of the CROP 2D function. The counter saturates at 0x3FFFFFF. Granularity is 32-bit for all the formats except for the byte stream formats (for example JPEG) having byte granularity. 0 26 read-only P0DCLMTR P0DCLMTR DCMIPP Pipe0 dump limit register 0x5B4 0x20 0x00FFFFFF 0xFFFFFFFF LIMIT Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation. 0 24 read-write ENABLE 31 1 read-write P0PPCR P0PPCR DCMIPP Pipe0 pixel packer configuration register 0x5C0 0x20 0x00000000 0xFFFFFFFF PAD Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment. 5 1 read-write BSM Byte select mode Modes 10 and 11 work only with EDM [2:0] = 000 into the DCMIPP_PRCR register. 7 2 read-write OEBS Odd/even byte select (byte select start) This bit works in conjunction with BSM field (BSM different from 00) 9 1 read-write LSM Line select mode 10 1 read-write OELS Odd/even line select (line select start) This bit works in conjunction with LSM field (LSM = 1). 11 1 read-write LINEMULT Amount of capture completed lines for LINE event and interrupt 13 3 read-write DBM Double buffer mode This bit is set and cleared by software. 16 1 read-write P0PPM0AR1 P0PPM0AR1 DCMIPP Pipe0 pixel packer Memory0 address register 1 0x5C4 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address Base address of memory area 0, to whom data are written. It is assumed to be a multiple of 16, hence its bits 3:0 are always at 0x0. 0 32 read-write P0PPM0AR2 P0PPM0AR2 DCMIPP Pipe0 pixel packer Memory0 address register 2 0x5C8 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address Base address of memory area 0, to whom data are written. It is assumed to be a multiple of 16, hence its bits 3:0 are always at 0x0. 0 32 read-write P0IER P0IER DCMIPP Pipe0 interrupt enable register 0x5F4 0x20 0x00000000 0xFFFFFFFF LINEIE Multi-line capture completed interrupt enable 0 1 read-write FRAMEIE Frame capture completed interrupt enable 1 1 read-write VSYNCIE VSYNC interrupt enable 2 1 read-write LIMITIE Limit interrupt enable 6 1 read-write OVRIE Overrun interrupt enable 7 1 read-write P0SR P0SR DCMIPP Pipe0 status register 0x5F8 0x20 0x00000000 0xFFFFFFFF LINEF Multi-line capture completed raw interrupt status This bit is set when one/more lines have been completed. For the JPEG mode, this bit is raised at the end of the frame. The periodicity of LINEF event is configured by LINEMULT bits into DCMIPP_P0PPCR register. When reaching end of frame, this event is triggered out to allow software action even if the LINEMULT value set is not a multiple of the total lines frame. In case of embedded synchronization, this bit is set only if the CAPTURE bit in the DCMIPP_CR register is set. It is cleared by writing a 1 to the CLINEF bit in the DCMIPP_P0FCR register. 0 1 read-only FRAMEF Frame capture completed raw interrupt status This bit is set when all data of a frame or window have been captured. In case of a cropped window, this bit is set at the end of line of the last line in the crop. It is set even if the captured frame is empty (for example window cropped outside the frame). This bit is cleared by writing a 1 to the CFRAMEF bit in DCMIPP_P0FCR. 1 1 read-only VSYNCF VSYNC raw interrupt status This bit is set when the VSYNC signal changes from the inactive state to the active state. In case of embedded synchronization, this bit is set only if the CAPTURE bit is set in DCMIPP_CR. It is cleared by writing a 1 to the CVSYNCF bit in the DCMIPP_P0FCR register. 2 1 read-only LIMITF Limit raw interrupt status This bit is set when the data counter DCMIPP_PxDCCNTR reaches its maximum value DCMIPP_PxDCLIMITR. It is cleared by writing a 1 to the CLIMITF bit in the DCMIPP_P0FCR register. 6 1 read-only OVRF Overrun raw interrupt status This bit is cleared by writing a 1 to the COVRF bit in the DCMIPP_P0FCR register. 7 1 read-only CPTACT Capture immediate status This bit is automatically reset at the end of frame capture complete event (after all the data of that frame have been captured and the IP-Plug has started to emit the last burst on the AXI, usually before the next VSync). 23 1 read-only P0FCR P0FCR DCMIPP Pipe0 interrupt clear register 0x5FC 0x20 0x00000000 0xFFFFFFFF CLINEF Multi-line capture complete interrupt status clear Writing a 1 into this bit clears LINEF in the DCMIPP_P0SR register. 0 1 write-only CFRAMEF Frame capture complete interrupt status clear Writing a 1 into this bit clears the FRAMEF bit in the DCMIPP_P0SR register. 1 1 write-only CVSYNCF Vertical synchronization interrupt status clear Writing a 1 into this bit clears the VSYNCF bit in the DCMIPP_P0SR register. 2 1 write-only CLIMITF limit interrupt status clear Writing a 1 into this bit clears LIMITF in the DCMIPP_P0SR register. 6 1 write-only COVRF Overrun interrupt status clear Writing a 1 into this bit clears the OVRF bit in the DCMIPP_P0SR register. 7 1 write-only P0CFCTCR P0CFCTCR DCMIPP Pipe0 current flow control configuration register 0x700 0x20 0x00000000 0xFFFFFFFF FRATE Frame capture rate control These bits define the frequency of frame capture. They are meaningful only in Continuous grab mode, ignored in Snapshot mode. 0 2 read-only CPTMODE Capture mode 2 1 read-only CPTREQ Capture requested When PIPEN = 1, and when the CPTREQ is set to 1 the pipe waits for the first VSync, and automatically starts a capture and sets CPTACT = 1 to mention it. In Snapshot mode the CPTREQ bit is automatically cleared at the start of the first frame received. In continuous grab mode the capture remains active and CPTREQ = 1, until the software clears CPTREQ: the capture stops and CPTACT is reset at the end of the ongoing frame. The DCMI and pipe configuration registers must be correctly programmed before enabling this bit. 3 1 read-only P0CSCSTR P0CSCSTR DCMIPP Pipe0 current stat/crop start register 0x704 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 words wide 0 12 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only P0CSCSZR P0CSCSZR DCMIPP Pipe0 current stat/crop size register 0x708 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 word wide (data 32-bit). If the value is maintained at 0 when enabling the crop by means of the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value. 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit, the value is forced internally at 0xFFE which is the maximum value. 16 12 read-only POSNEG Current value of the POSNEG bit This bit has a meaning only if ENABLE bit is set. 30 1 read-only ENABLE Current value of the ENABLE bit if POSNEG = 0, the data inside the rectangle area are transmitted (can correspond to a statistical data removal, or as a crop feature in a data valid image area). if POSNEG = 1, the data outside of the rectangle area are transmitted (can correspond to a statistical data extraction, rejecting all data inside the window) 31 1 read-only P0CPPCR P0CPPCR DCMIPP Pipe0 current pixel packer configuration register 0x7C0 0x20 0x00000000 0xFFFFFFFF PAD Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment 5 1 read-only BSM Current Byte select mode Modes 10 and 11 work only with EDM [2:0] = 000 into the DCMIPP_PRCR register. 7 2 read-only OEBS Current odd/even byte select (byte select start) This bit works in conjunction with BSM field (BSM different from 00) 9 1 read-only LSM Current Line select mode 10 1 read-only OELS Current odd/even line select (ine select start) This bit works in conjunction with LSM field (LSM = 1) 11 1 read-only LINEMULT Current amount of capture completed lines for LINE event and interrupt 13 3 read-only DBM Double buffer mode 16 1 read-only P0CPPM0AR1 P0CPPM0AR1 DCMIPP Pipe0 current pixel packer Memory0 address register 1 0x7C4 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address Base address of the current memory area 0, to whom data are written. It is assumed to be a multiple of 16, hence its bits 3:0 are always at 0x0. 0 32 read-only P0CPPM0AR2 P0CPPM0AR2 DCMIPP Pipe0 current pixel packer Memory0 address register 2 0x7C8 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address Base address of the current memory area 0, to whom data are written. It is assumed to be a multiple of 16, hence its bits 3:0 are always at 0x0. 0 32 read-only DLYB1 DLYB register block DLYB 0x52008000 0x0 0x400 registers CR CR DLYB control register 0x0 0x20 0x00000000 0xFFFFFFFF DEN Delay block enable bit 0 1 read-write SEN Sampler length enable bit 1 1 read-write CFGR CFGR DLYB configuration register 0x4 0x20 0x00000000 0xFFFFFFFF SEL Phase for the output clock. These bits can only be written when SEN = 1. Output clock phase = input clock + SEL[3:0] x unit delay 0 4 read-write UNIT Delay of a unit delay cell. These bits can only be written when SEN = 1. Unit delay = initial delay + UNIT[6:0] x delay step 8 7 read-write LNG Delay line length value These bits reflect the 12 unit delay values sampled at the rising edge of the input clock. The value is only valid when LNGF = 1. 16 12 read-only LNGF Length valid flag This flag indicates when the delay line length value contained in LNG[11:0] is valid after UNIT[6:0] bits changed. 31 1 read-only DLYB2 0x48002800 DMA2D Chrom-Art Accelerator controller DMA2D 0x52001000 0x0 0xC00 registers DMA2D DMA2D global interrupt 98 CR CR DMA2D control register 0x0 0x20 0x00000000 0xFFFFFFFF START Start This bit can be used to launch the DMA2D according to parameters loaded in the various configuration registers. This bit is automatically reset by the following events: at the end of the transfer when the data transfer is aborted by the user by setting ABORT in this register when a data transfer error occurs when the data transfer has not started due to a configuration error, or another transfer operation already ongoing (automatic CLUT loading) 0 1 read-write SUSP Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when START = 0. 1 1 read-write ABORT Abort This bit can be used to abort the current transfer. This bit is set by software, and is automatically reset by hardware when START = 0. 2 1 read-write LOM Line offset mode This bit configures how the line offset is expressed (pixels or bytes) for the foreground, background and output. This bit is set and cleared by software. It can not be modified while a transfer is ongoing. 6 1 read-write TEIE Transfer error (TE) interrupt enable This bit is set and cleared by software. 8 1 read-write TCIE Transfer complete (TC) interrupt enable This bit is set and cleared by software. 9 1 read-write TWIE Transfer watermark (TW) interrupt enable This bit is set and cleared by software. 10 1 read-write CAEIE CLUT access error (CAE) interrupt enable This bit is set and cleared by software. 11 1 read-write CTCIE CLUT transfer complete (CTC) interrupt enable This bit is set and cleared by software. 12 1 read-write CEIE Configuration error (CE) interrupt enable This bit is set and cleared by software. 13 1 read-write MODE DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing. Others: Reserved 16 3 read-write ISR ISR DMA2D interrupt status register 0x4 0x20 0x00000000 0xFFFFFFFF TEIF Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading). 0 1 read-only TCIF Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only). 1 1 read-only TWIF Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred. 2 1 read-only CAEIF CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D. 3 1 read-only CTCIF CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete. 4 1 read-only CEIF Configuration error interrupt flag This bit is set when START is set in DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR, and a wrong configuration has been programmed. 5 1 read-only IFCR IFCR DMA2D interrupt flag clear register 0x8 0x20 0x00000000 0xFFFFFFFF CTEIF Clear transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in DMA2D_ISR. 0 1 read-write CTCIF Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in DMA2D_ISR. 1 1 read-write CTWIF Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in DMA2D_ISR. 2 1 read-write CAECIF Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in DMA2D_ISR. 3 1 read-write CCTCIF Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in DMA2D_ISR. 4 1 read-write CCEIF Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in DMA2D_ISR. 5 1 read-write FGMAR FGMAR DMA2D foreground memory address register 0xC 0x20 0x00000000 0xFFFFFFFF MA Memory address, address of the data used for the foreground image The address alignment must match the image format selected: a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned, and a 4-bit per pixel format must be 8-bit aligned. 0 32 read-write FGOR FGOR DMA2D foreground offset register 0x10 0x20 0x00000000 0xFFFFFFFF LO Line offset This field gives the line offset used for the foreground image, expressed: in pixels when LOM = 0 in DMA2D_CR. Only LO[13:0] bits are considered, LO[15:14] bits are ignored. in bytes when LOM = 1 This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. If the image format is 4-bit per pixel, the line offset must be even. 0 16 read-write BGMAR BGMAR DMA2D background memory address register 0x14 0x20 0x00000000 0xFFFFFFFF MA Memory address, address of the data used for the background image The address alignment must match the image format selected: a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned. 0 32 read-write BGOR BGOR DMA2D background offset register 0x18 0x20 0x00000000 0xFFFFFFFF LO Line offset This field gives the line offset used for the background image, expressed: in pixels when LOM = 0 in DMA2D_CR. Only LO[13:0] bits are considered, LO[15:14] bits are ignored. in bytes when LOM = 1 This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. If the image format is 4-bit per pixel, the line offset must be even. 0 16 read-write FGPFCCR FGPFCCR DMA2D foreground PFC control register 0x1C 0x20 0x00000000 0xFFFFFFFF CM Color mode These bits defines the color format of the foreground image. Others: Reserved 0 4 read-write CCM CLUT color mode This bit defines the color format of the CLUT. 4 1 read-write START Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: at the end of the transfer when the transfer is aborted by the user by setting ABORT in DMA2D_CR when a transfer error occurs when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer) 5 1 read-write CS CLUT size These bits define the size of the CLUT used for the foreground image. The number of CLUT entries is equal to CS[7:0] + 1. 8 8 read-write AM Alpha mode These bits select the alpha channel value to be used for the foreground image. Others: Reserved 16 2 read-write CSS Chroma subsampling These bits define the chroma subsampling mode for YCbCr color mode. Others: Reserved 18 2 read-write AI Alpha inverted This bit inverts the alpha value. 20 1 read-write RBS Red/Blue swap This bit allows to swap Red and Blue to support BGR or ABGR color formats. 21 1 read-write ALPHA Alpha value These bits define a fixed alpha channel value which can replace the original alpha value, or be multiplied by the original alpha value, according to the alpha mode selected through AM[1:0] in this register. 24 8 read-write FGCOLR FGCOLR DMA2D foreground color register 0x20 0x20 0x00000000 0xFFFFFFFF BLUE Blue value for the A4 or A8 mode of the foreground image Used also for fixed color FG in memory-to-memory mode with blending and fixed color FG (BG fetch only with FG and BG PFC active). 0 8 read-write GREEN Green value for the A4 or A8 mode of the foreground image Used also for fixed color FG in memory-to-memory mode with blending and fixed color FG (BG fetch only with FG and BG PFC active). 8 8 read-write RED Red value for the A4 or A8 mode of the foreground image Used also for fixed color FG in memory-to-memory mode with blending and fixed color FG (BG fetch only with FG and BG PFC active). 16 8 read-write BGPFCCR BGPFCCR DMA2D background PFC control register 0x24 0x20 0x00000000 0xFFFFFFFF CM Color mode These bits define the color format of the foreground image. Others: Reserved 0 4 read-write CCM CLUT color mode These bits define the color format of the CLUT. 4 1 read-write START Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: at the end of the transfer when the transfer is aborted by the user by setting ABORT bit in DMA2D_CR when a transfer error occurs when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic background CLUT transfer) 5 1 read-write CS CLUT size These bits define the size of the CLUT used for the BG. The number of CLUT entries is equal to CS[7:0] + 1. 8 8 read-write AM Alpha mode These bits define which alpha channel value to be used for the background image. Others: Reserved 16 2 read-write AI Alpha Inverted This bit inverts the alpha value. 20 1 read-write RBS Red/Blue swap This bit allows to swap Red and Blue to support BGR or ABGR color formats. 21 1 read-write ALPHA Alpha value These bits define a fixed alpha channel value which can replace the original alpha value, or be multiplied with the original alpha value according to the alpha mode selected with AM[1:0]. 24 8 read-write BGCOLR BGCOLR DMA2D background color register 0x28 0x20 0x00000000 0xFFFFFFFF BLUE Blue value for the A4 or A8 mode of the background Used also for fixed color BG in memory-to-memory mode with blending and fixed color BG (FG fetch only with FG and BG PFC active). 0 8 read-write GREEN Green value for the A4 or A8 mode of the background Used also for fixed color BG in memory-to-memory mode with blending and fixed color BG (FG fetch only with FG and BG PFC active). 8 8 read-write RED Red value for the A4 or A8 mode of the background Used also for fixed color BG in memory-to-memory mode with blending and fixed color BG (FG fetch only with FG and BG PFC active). 16 8 read-write FGCMAR FGCMAR DMA2D foreground CLUT memory address register 0x2C 0x20 0x00000000 0xFFFFFFFF MA Memory address Address of the data used for the CLUT address dedicated to the foreground image. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned. 0 32 read-write BGCMAR BGCMAR DMA2D background CLUT memory address register 0x30 0x20 0x00000000 0xFFFFFFFF MA Memory address Address of the data used for the CLUT address dedicated to the background image. If the background CLUT format is 32-bit, the address must be 32-bit aligned. 0 32 read-write OPFCCR OPFCCR DMA2D output PFC control register 0x34 0x20 0x00000000 0xFFFFFFFF CM Color mode These bits define the color format of the output image. Others: Reserved 0 3 read-write SB Swap bytes When this bit is set, the bytes in the output FIFO are swapped two by two. The number of pixels per line (PL) must be even, and the output memory address (OMAR) must be even. 8 1 read-write AI Alpha Inverted This bit inverts the alpha value. 20 1 read-write RBS Red/Blue swap This bit allows to swap Red and Blue to support BGR or ABGR color formats. 21 1 read-write OCOLR_ARGB8888 OCOLR_ARGB8888 DMA2D output color register 0x38 0x20 0x00000000 0xFFFFFFFF BLUE Blue value of the output image in ARGB8888 or RGB888 0 8 read-write GREEN Green value of the output image in ARGB8888 or RGB888 8 8 read-write RED Red value of the output image in ARGB8888 or RGB888 mode 16 8 read-write ALPHA Alpha channel value of the output color in ARGB8888 mode (otherwise reserved) 24 8 read-write OCOLR_RGB565 OCOLR_RGB565 DMA2D output color register OCOLR_ARGB8888 0x38 0x20 0x00000000 0xFFFFFFFF BLUE Blue value of the output image in RGB565 mode 0 5 read-write GREEN Green value of the output image in RGB565 mode 5 6 read-write RED Red value of the output image in RGB565 mode 11 5 read-write OCOLR_ARGB1555 OCOLR_ARGB1555 DMA2D output color register OCOLR_ARGB8888 0x38 0x20 0x00000000 0xFFFFFFFF BLUE Blue value of the output image in ARGB1555 mode 0 5 read-write GREEN Green value of the output image in ARGB1555 mode 5 5 read-write RED Red value of the output image in ARGB1555 mode 10 5 read-write A Alpha channel value of the output color in ARGB1555 mode 15 1 read-write OCOLR_ARGB4444 OCOLR_ARGB4444 DMA2D output color register OCOLR_ARGB8888 0x38 0x20 0x00000000 0xFFFFFFFF BLUE Blue value of the output image in ARGB4444 mode 0 4 read-write GREEN Green value of the output image in ARGB4444 mode 4 4 read-write RED Red value of the output image in ARGB4444 mode 8 4 read-write ALPHA Alpha channel of the output color value in ARGB4444 12 4 read-write OMAR OMAR DMA2D output memory address register 0x3C 0x20 0x00000000 0xFFFFFFFF MA Memory address Address of the data used for the output FIFO. The address alignment must match the image format selected: a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned. 0 32 read-write OOR OOR DMA2D output offset register 0x40 0x20 0x00000000 0xFFFFFFFF LO Line offset This field gives the line offset used for the output, expressed: in pixels when LOM = 0 in DMA2D_CR. Only LO[13:0] bits are considered, LO[15:14] bits are ignored. in bytes when LOM = 1 This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. 0 16 read-write NLR NLR DMA2D number of line register 0x44 0x20 0x00000000 0xFFFFFFFF NL Number of lines of the area to be transferred. 0 16 read-write PL Pixel per lines per lines of the area to be transferred If any of the input image format is 4-bit per pixel, pixel per lines must be even. 16 14 read-write LWR LWR DMA2D line watermark register 0x48 0x20 0x00000000 0xFFFFFFFF LW Line watermark for interrupt generation An interrupt is raised when the last pixel of the watermarked line has been transferred. 0 16 read-write AMTCR AMTCR DMA2D AXI master timer configuration register 0x4C 0x20 0x00000000 0xFFFFFFFF EN Dead-time functionality enable 0 1 read-write DT Dead time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses. 8 8 read-write 256 0x4 0-255 FGCLUT%s FGCLUT%s DMA2D foreground CLUT 0x400 0x20 0x00000000 0x00000000 BLUE Blue Blue value for index 0 for the foreground 0 8 read-write GREEN Green Green value for index 0 for the foreground 8 8 read-write RED Red Red value for index 0 for the foreground 16 8 read-write ALPHA Alpha Alpha value for index 0 for the foreground 24 8 read-write 256 0x4 0-255 BGCLUT%s BGCLUT%s DMA2D background CLUT 0x800 0x20 0x00000000 0x00000000 BLUE Blue Blue value for index 0 for the background 0 8 read-write GREEN Green Green value for index 0 for the background 8 8 read-write RED Red Red value for index 0 for the background 16 8 read-write ALPHA Alpha Alpha value for index 0 for the background 24 8 read-write DTS Digital temperature sensor DTS 0x58006800 0x0 0x400 registers DTS DTS global interrupt 2 CFGR1 CFGR1 Temperature sensor configuration register 1 0x0 0x20 0x00000000 0xFFFFFFFF TS1_EN Temperature sensor 1 enable bit This bit is set and cleared by software. Note: Once enabled, the temperature sensor is active after a specific delay time. The TS1_RDY flag will be set when the sensor is ready. 0 1 read-write TS1_START Start frequency measurement on temperature sensor 1 This bit is set and cleared by software. 4 1 read-write TS1_INTRIG_SEL Input trigger selection bit for temperature sensor 1 These bits are set and cleared by software. They select which input triggers a temperature measurement. Refer to Section 30.3.10: Trigger input. 8 4 read-write TS1_SMP_TIME Sampling time for temperature sensor 1 These bits allow increasing the sampling time to improve measurement precision. When the PCLK clock is selected as reference clock (REFCLK_SEL = 0), the measurement will be performed at TS1_SMP_TIME period of CLK_PTAT. When the LSE is selected as reference clock (REFCLK_SEL =1), the measurement will be performed at TS1_SMP_TIME period of LSE. 16 4 read-write REFCLK_SEL Reference clock selection bit This bit is set and cleared by software. It indicates whether the reference clock is the high speed clock (PCLK) or the low speed clock (LSE). 20 1 read-write Q_MEAS_OPT Quick measurement option bit This bit is set and cleared by software. It is used to increase the measurement speed by suppressing the calibration step. It is effective only when the LSE clock is used as reference clock (REFCLK_SEL=1). 21 1 read-write HSREF_CLK_DIV High speed clock division ratio These bits are set and cleared by software. They can be used to define the division ratio for the main clock in order to obtain the internal frequency lower than 1 MHz required for the calibration. They are applicable only for calibration when PCLK is selected as reference clock (REFCLK_SEL=0). ... 24 7 read-write T0VALR1 T0VALR1 Temperature sensor T0 value register 1 0x8 0x20 0x00000000 0x00000000 TS1_FMT0 Engineering value of the frequency measured at T0 for temperature sensor 1 This value is expressed in 0.1 kHz. 0 16 read-only TS1_T0 Engineering value of the T0 temperature for temperature sensor 1. Others: Reserved, must not be used. 16 2 read-only RAMPVALR RAMPVALR Temperature sensor ramp value register 0x10 0x20 0x00000000 0x00000000 TS1_RAMP_COEFF Engineering value of the ramp coefficient for the temperature sensor 1. This value is expressed in Hz/ C. 0 16 read-only ITR1 ITR1 Temperature sensor interrupt threshold register 1 0x14 0x20 0x00000000 0xFFFFFFFF TS1_LITTHD Low interrupt threshold for temperature sensor 1 These bits are set and cleared by software. They indicate the lowest value than can be reached before raising an interrupt signal. 0 16 read-write TS1_HITTHD High interrupt threshold for temperature sensor 1 These bits are set and cleared by software. They indicate the highest value than can be reached before raising an interrupt signal. 16 16 read-write DR DR Temperature sensor data register 0x1C 0x20 0x00000000 0xFFFFFFFF TS1_MFREQ Value of the counter output value for temperature sensor 1 0 16 read-write SR SR Temperature sensor status register 0x20 0x20 0x00000000 0xFFFFFFFF TS1_ITEF Interrupt flag for end of measurement on temperature sensor 1, synchronized on PCLK. This bit is set by hardware when a temperature measure is done. It is cleared by software by writing 1 to the TS2_CITEF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITEFEN bit is set 0 1 read-only TS1_ITLF Interrupt flag for low threshold on temperature sensor 1, synchronized on PCLK. This bit is set by hardware when the low threshold is set and reached. It is cleared by software by writing 1 to the TS1_CITLF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITLFEN bit is set 1 1 read-only TS1_ITHF Interrupt flag for high threshold on temperature sensor 1, synchronized on PCLK This bit is set by hardware when the high threshold is set and reached. It is cleared by software by writing 1 to the TS1_CITHF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITHFEN bit is set 2 1 read-only TS1_AITEF Asynchronous interrupt flag for end of measure on temperature sensor 1 This bit is set by hardware when a temperature measure is done. It is cleared by software by writing 1 to the TS1_CAITEF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITEFEN bit is set 4 1 read-only TS1_AITLF Asynchronous interrupt flag for low threshold on temperature sensor 1 This bit is set by hardware when the low threshold is reached. It is cleared by software by writing 1 to the TS1_CAITLF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITLFEN bit is set 5 1 read-only TS1_AITHF Asynchronous interrupt flag for high threshold on temperature sensor 1 This bit is set by hardware when the high threshold is reached. It is cleared by software by writing 1 to the TS1_CAITHF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITHFEN bit is set 6 1 read-only TS1_RDY Temperature sensor 1 ready flag This bit is set and reset by hardware. It indicates that a measurement is ongoing. 15 1 read-only ITENR ITENR Temperature sensor interrupt enable register 0x24 0x20 0x00000000 0xFFFFFFFF TS1_ITEEN Interrupt enable flag for end of measurement on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the synchronous interrupt for end of measurement. 0 1 read-write TS1_ITLEN Interrupt enable flag for low threshold on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the synchronous interrupt when the measure reaches or is below the low threshold. 1 1 read-write TS1_ITHEN Interrupt enable flag for high threshold on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the interrupt when the measure reaches or is above the high threshold. 2 1 read-write TS1_AITEEN Asynchronous interrupt enable flag for end of measurement on temperature sensor 1 This bit are set and cleared by software. It enables the asynchronous interrupt for end of measurement (only when REFCLK_SEL = 1). 4 1 read-write TS1_AITLEN Asynchronous interrupt enable flag for low threshold on temperature sensor 1. This bit are set and cleared by software. It enables the asynchronous interrupt when the temperature is below the low threshold (only when REFCLK_SEL= 1) 5 1 read-write TS1_AITHEN Asynchronous interrupt enable flag on high threshold for temperature sensor 1. This bit are set and cleared by software. It enables the asynchronous interrupt when the temperature is above the high threshold (only when REFCLK_SEL= 1) 6 1 read-write ICIFR ICIFR Temperature sensor clear interrupt flag register 0x28 0x20 0x00000000 0xFFFFFFFF TS1_CITEF Interrupt clear flag for end of measurement on temperature sensor 1 Writing 1 to this bit clears the TS1_ITEF flag in the DTS_SR register. 0 1 read-write TS1_CITLF Interrupt clear flag for low threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_ITLF flag in the DTS_SR register. 1 1 read-write TS1_CITHF Interrupt clear flag for high threshold on temperature sensor 1 Writing this bit to 1 clears the TS1_ITHF flag in the DTS_SR register. 2 1 read-write TS1_CAITEF Write once bit. Clear the asynchronous IT flag for End Of Measure for thermal sensor 1. Writing 1 clears the TS1_AITEF flag of the DTS_SR register. 4 1 read-write TS1_CAITLF Asynchronous interrupt clear flag for low threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_AITLF flag in the DTS_SR register. 5 1 read-write TS1_CAITHF Asynchronous interrupt clear flag for high threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_AITHF flag in the DTS_SR register. 6 1 read-write OR OR Temperature sensor option register 0x2C 0x20 0x00000000 0xFFFFFFFF TS_OP0 general purpose option bits 0 1 read-write TS_OP1 general purpose option bits 1 1 read-write TS_OP2 general purpose option bits 2 1 read-write TS_OP3 general purpose option bits 3 1 read-write TS_OP4 general purpose option bits 4 1 read-write TS_OP5 general purpose option bits 5 1 read-write TS_OP6 general purpose option bits 6 1 read-write TS_OP7 general purpose option bits 7 1 read-write TS_OP8 general purpose option bits 8 1 read-write TS_OP9 general purpose option bits 9 1 read-write TS_OP10 general purpose option bits 10 1 read-write TS_OP11 general purpose option bits 11 1 read-write TS_OP12 general purpose option bits 12 1 read-write TS_OP13 general purpose option bits 13 1 read-write TS_OP14 general purpose option bits 14 1 read-write TS_OP15 general purpose option bits 15 1 read-write TS_OP16 general purpose option bits 16 1 read-write TS_OP17 general purpose option bits 17 1 read-write TS_OP18 general purpose option bits 18 1 read-write TS_OP19 general purpose option bits 19 1 read-write TS_OP20 general purpose option bits 20 1 read-write TS_OP21 general purpose option bits 21 1 read-write TS_OP22 general purpose option bits 22 1 read-write TS_OP23 general purpose option bits 23 1 read-write TS_OP24 general purpose option bits 24 1 read-write TS_OP25 general purpose option bits 25 1 read-write TS_OP26 general purpose option bits 26 1 read-write TS_OP27 general purpose option bits 27 1 read-write TS_OP28 general purpose option bits 28 1 read-write TS_OP29 general purpose option bits 29 1 read-write TS_OP30 general purpose option bits 30 1 read-write TS_OP31 general purpose option bits 31 1 read-write ETH Ethernet register block ETH 0x40028000 0x0 0x11F0 registers ETH Ethernet global interrupt 92 MACCR MACCR Operating mode configuration register 0x0 0x20 0x00000000 0xFFFFFFFF RE Receiver Enable When this bit is set, the Rx state machine of the MAC is enabled for receiving packets from the MII interface. When this bit is reset, the MAC Rx state machine is disabled after it completes the reception of the current packet. The Rx state machine does not receive any more packets from the MII interface. 0 1 read-write TE Transmitter Enable When this bit is set, the Tx state machine of the MAC is enabled for transmission on the MII interface. When this bit is reset, the MAC Tx state machine is disabled after it completes the transmission of the current packet. The Tx state machine does not transmit any more packets. 1 1 read-write PRELEN Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet. The preamble reduction occurs only when the MAC is operating in the Full-duplex mode. 2 2 read-write DC Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Packet Abort status, along with the excessive deferral error bit set in the Tx packet status, when the Tx state machine is deferred for more than 24,288 bit times in 10 or 100 Mbps mode. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0, and it is restarted. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in the Half-duplex mode. 4 1 read-write BL Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision: where n = retransmission attempt The random integer r takes the value in the range 0 <= r < 2^k. This bit is applicable only in the Half-duplex mode. 5 2 read-write DR Disable Retry When this bit is set, the MAC attempts only one transmission. When a collision occurs on the MII interface, the MAC ignores the current packet transmission and reports a Packet Abort with excessive collision error in the Tx packet status. When this bit is reset, the MAC retries based on the settings of the BL field. This bit is applicable only in the Half-duplex mode. 8 1 read-write DCRS Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter ignores the MII CRS signal during packet transmission in the Half-duplex mode. As a result, no errors are generated because of Loss of Carrier or No Carrier during transmission. When this bit is reset, the MAC transmitter generates errors because of Carrier Sense. The MAC can even abort the transmission. 9 1 read-write DO Disable Receive Own When this bit is set, the MAC disables the reception of packets when the ETH_TX_EN is asserted in the Half-duplex mode. When this bit is reset, the MAC receives all packets given by the PHY. This bit is not applicable in the Full-duplex mode. This bit is reserved and read-only (RO) with default value in the Full-duplex-only configurations. 10 1 read-write ECRSFD Enable Carrier Sense Before Transmission in Full-duplex mode When this bit is set, the MAC transmitter checks the CRS signal before packet transmission in the Full-duplex mode. The MAC starts the transmission only when the CRS signal is low. When this bit is reset, the MAC transmitter ignores the status of the CRS signal. 11 1 read-write LM Loopback Mode When this bit is set, the MAC operates in the loopback mode at MII. The MII Rx clock input (eth_mii_rx_clk) is required for the loopback to work properly. This is because the Tx clock is not internally looped back. 12 1 read-write DM Duplex Mode When this bit is set, the MAC operates in the Full-duplex mode in which it can transmit and receive simultaneously. 13 1 read-write FES MAC Speed This bit selects the speed in the 10/100 Mbps mode: 14 1 read-write JE Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status. For more information about how the setting of this bit and the JE bit impact the Giant packet status, see Table 563: Giant Packet Status based on S2KP and JE Bits. 16 1 read-write JD Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer packets of up to 16,383 bytes. When this bit is reset, if the application sends more than 2,048 bytes of data (10,240 if JE is set high) during transmission, the MAC does not send rest of the bytes in that packet. 17 1 read-write WD Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive packets of up to 16,383 bytes. When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if JE is set high) of the packet being received. The MAC cuts off any bytes received after 2,048 bytes. 19 1 read-write ACS Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1,536 bytes. All received packets with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming packets to the application, without any modification. Note: For information about how the settings of CST bit and this bit impact the packet length, see Table 564: Packet Length based on the CST and ACS bits. 20 1 read-write CST CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding the packet to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. Note: For information about how the settings of the ACS bit and this bit impact the packet length, see Table 564: Packet Length based on the CST and ACS bits. 21 1 read-write S2KP IEEE 802.3as Support for 2K Packets When this bit is set, the MAC considers all packets with up to 2,000 bytes length as normal packets. When the JE bit is not set, the MAC considers all received packets of size more than 2K bytes as Giant packets. When this bit is reset and the JE bit is not set, the MAC considers all received packets of size more than 1,518 bytes (1,522 bytes for tagged) as giant packets. For more information about how the setting of this bit and the JE bit impact the Giant packet status, see Table 563: Giant Packet Status based on S2KP and JE Bits. Note: When the JE bit is set, setting this bit has no effect on the giant packet status. 22 1 read-write GPSLCE Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the value in GPSL field in ETH_MACECR register to declare a received packet as Giant packet. This field must be programmed to more than 1,518 bytes. Otherwise, the MAC considers 1,518 bytes as giant packet limit. When this bit is reset, the MAC considers a received packet as Giant packet when its size is greater than 1,518 bytes (1522 bytes for tagged packet). The watchdog timeout limit, Jumbo Packet Enable and 2K Packet Enable have higher precedence over this bit, that is the MAC considers a received packet as Giant packet when its size is greater than 9,018 bytes (9,022 bytes for tagged packet) with Jumbo Packet Enabled and greater than 2,000 bytes with 2K Packet Enabled. The watchdog timeout, if enabled, terminates the received packet when watchdog limit is reached. Therefore, the programmed giant packet limit should be less than the watchdog limit to get the giant packet status. 23 1 read-write IPG Inter-Packet Gap These bits control the minimum IPG between packets during transmission. ... This range of minimum IPG is valid in Full-duplex mode. In the Half-duplex mode, the minimum IPG can be configured only for 64-bit times (IPG = 100). Lower values are not considered. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IPG. The above function (IPG less than 96 bit times) is valid only when EIPGEN bit in ETH_MACECR register is reset. When EIPGEN is set, then the minimum IPG (greater than 96 bit times) is controlled as per the description given in EIPG field in ETH_MACECR register. 24 3 read-write IPC Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. When this bit is reset, the COE function in the receiver is disabled. The Layer 3 and Layer 4 Packet Filter feature automatically selects the IPC Full Checksum Offload Engine on the Receive side. When this feature is enabled, you must set the IPC bit. 27 1 read-write SARC Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits[29:28]: Others: Reserved, must not be used. Note: Changes to this field take effect only on the start of a packet. If you write to this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. 28 3 read-write ARPEN ARP Offload Enable When this bit is set, the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission. It forwards the ARP packet to the application and also indicate the events in the RxStatus. When this bit is reset, the MAC receiver does not recognize any ARP packet and indicates them as Type frame in the RxStatus. 31 1 read-write MACECR MACECR Extended operating mode configuration register 0x4 0x20 0x00000000 0xFFFFFFFF GPSL Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes, the MAC declares the received packet as Giant packet. The value programmed in this field must be greater than or equal to 1,518 bytes. Any other programmed value is considered as 1,518 bytes. For VLAN tagged packets, the MAC adds 4 bytes to the programmed value. For double VLAN tagged packets, the MAC adds 8 bytes to the programmed value. The value in this field is applicable when the GPSLCE bit is set in ETH_MACCR register. 0 14 read-write DCRCC Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does not check the CRC field in the received packets. When this bit is reset, the MAC receiver always checks the CRC field in the received packets. 16 1 read-write SPEN Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status. The MAC discards the Slow Protocol packets with invalid subtypes. When this bit is reset, the MAC forwards all error-free Slow Protocol packets to the application. The MAC considers such packets as normal Type packets. 17 1 read-write USP Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC Address 0 high register (ETH_MACA0HR) and MAC Address 0 low register MAC Address x low register (ETH_MACAxLR). The MAC also detects the Slow Protocol packets with the Slow Protocols multicast address (01-80-C2-00-00-02). When this bit is reset, the MAC detects only Slow Protocol packets with the Slow Protocol multicast address specified in the IEEE 802.3-2008, Section 5. 18 1 read-write EIPGEN Extended Inter-Packet Gap Enable When this bit is set, the MAC interprets EIPG field and IPG field in Operating mode configuration register (ETH_MACCR) together as minimum IPG greater than 96 bit times in steps of 8 bit times. When this bit is reset, the MAC ignores EIPG field and interprets IPG field in Operating mode configuration register (ETH_MACCR) as minimum IPG less than or equal to 96 bit times in steps of 8 bit times. Note: The extended Inter-Packet Gap feature must be enabled when operating in Full-duplex mode only. There may be undesirable effects on back-pressure function and frame transmission if it is enabled in Half-duplex mode. 24 1 read-write EIPG Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set. This field (as Most Significant bits) along with IPG field in Operating mode configuration register (ETH_MACCR), gives the minimum IPG greater than 96 bit times in steps of 8 bit times. For example: EIPG = 0 and IPG = 0 give 104 bit times EIPG = 0 and IPG = 1 give 112 bit times EIPG = 0 and IPG = 2 give 120 bit times .. EIPG = 7 and IPG = 31 give 2144 bit times 25 5 read-write MACPFR MACPFR Packet filtering control register 0x8 0x20 0x00000000 0xFFFFFFFF PR Promiscuous Mode When this bit is set, the Address Filtering module passes all incoming packets irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Rx Status Word are always cleared when PR is set. 0 1 read-write HUC Hash Unicast When this bit is set, the MAC performs the destination address filtering of unicast packets according to the Hash table. When this bit is reset, the MAC performs a perfect destination address filtering for unicast packets, that is, it compares the DA field with the values programmed in DA registers. 1 1 read-write HMC Hash Multicast When this bit is set, the MAC performs the destination address filtering of received multicast packets according to the Hash table. When this bit is reset, the MAC performs the perfect destination address filtering for multicast packets, that is, it compares the DA field with the values programmed in DA registers. 2 1 read-write DAIF DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets. When this bit is reset, normal filtering of packets is performed. 3 1 read-write PM Pass All Multicast When this bit is set, it indicates that all received packets with a multicast destination address (first bit in the destination address field is '1') are passed. When this bit is reset, filtering of multicast packet depends on HMC bit. 4 1 read-write DBF Disable Broadcast Packets When this bit is set, the AFM module blocks all incoming broadcast packets. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast packets. 5 1 read-write PCF Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets). 6 2 read-write SAIF SA Inverse Filtering When this bit is set, the Address Check block operates in the inverse filtering mode for SA address comparison. If the SA of a packet matches the values programmed in the SA registers, it is marked as failing the SA Address filter. When this bit is reset, if the SA of a packet does not match the values programmed in the SA registers, it is marked as failing the SA Address filter. 8 1 read-write SAF Source Address Filter Enable When this bit is set, the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the packet. When this bit is reset, the MAC forwards the received packet to the application with updated SAF bit of the Rx Status depending on the SA address comparison. Note: According to the IEEE specification, Bit 47 of the SA is reserved. However, the MAC compares all 48 bits. The software driver should take this into consideration while programming the MAC address registers for SA. 9 1 read-write HPF Hash or Perfect Filter When this bit is set, the address filter passes a packet if it matches either the perfect filtering or Hash filtering as set by the HMC or HUC bit. When this bit is reset and the HUC or HMC bit is set, the packet is passed only if it matches the Hash filter. 10 1 read-write VTFE VLAN Tag Filter Enable When this bit is set, the MAC drops the VLAN tagged packets that do not match the VLAN Tag. When this bit is reset, the MAC forwards all packets irrespective of the match status of the VLAN Tag. 16 1 read-write IPFE Layer 3 and Layer 4 Filter Enable When this bit is set, the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When this bit is reset, the MAC forwards all packets irrespective of the match status of the Layer 3 and Layer 4 fields. 20 1 read-write DNTU Drop Non-TCP/UDP over IP Packets When this bit is set, the MAC drops the non-TCP or UDP over IP packets. The MAC forward only those packets that are processed by the Layer 4 filter. When this bit is reset, the MAC forwards all non-TCP or UDP over IP packets. 21 1 read-write RA Receive All When this bit is set, the MAC Receiver module passes all received packets to the application, irrespective of whether they pass the address filter or not. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bit in the Rx Status Word. When this bit is reset, the Receiver module passes only those packets to the application that pass the SA or DA address filter. 31 1 read-write MACWTR MACWTR Watchdog timeout register 0xC 0x20 0x00000000 0xFFFFFFFF WTO Watchdog Timeout When the PWE bit is set and the WD bit of the Operating mode configuration register (ETH_MACCR) register is reset, this field is used as watchdog timeout for a received packet. If the length of a received packet exceeds the value of this field, such packet is terminated and declared as an error packet. Encoding is as follows: .. Note: When the PWE bit is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE 802.3-specified valid tagged packets are declared as error packets and then dropped. 0 4 read-write PWE Programmable Watchdog Enable When this bit is set and the WD bit of the Operating mode configuration register (ETH_MACCR) register is reset, the WTO field is used as watchdog timeout for a received packet. When this bit is cleared, the watchdog timeout for a received packet is controlled by setting of WD and JE bits in Operating mode configuration register (ETH_MACCR) register. 8 1 read-write MACHT0R MACHT0R Hash Table 0 register 0x10 0x20 0x00000000 0xFFFFFFFF HT31T0 MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table. 0 32 read-write MACHT1R MACHT1R Hash Table 1 register 0x14 0x20 0x00000000 0xFFFFFFFF HT63T32 MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table. 0 32 read-write MACVTR MACVTR VLAN tag register 0x50 0x20 0x00000000 0xFFFFFFFF VL VLAN Tag Identifier for Receive Packets This field contains the 802.1Q VLAN tag to identify the VLAN packets. This VLAN tag identifier is compared to the 15th and 16th bytes of the packets being received for VLAN packets. The following list describes the bits of this field: Bits[15:13]: User Priority Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) Bits[11:0]: VLAN Identifier (VID) field of VLAN tag When the ETV bit is set, only the VID is used for comparison. If this field ([11:0] if ETV is set) is all zeros, the MAC does not check the 15th and 16th bytes for VLAN tag comparison and declares all packets with Type field value of 0x8100 or 0x88a8 as VLAN packets. 0 16 read-write ETV Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits[11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged packet. Similarly, when enabled, only 12 bits of the VLAN tag in the received packet are used for Hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN packet are used for comparison and VLAN Hash filtering. 16 1 read-write VTIM VLAN Tag Inverse Match Enable When this bit is set, this bit enables the VLAN Tag inverse matching. The packets without matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The packets with matched VLAN Tag are marked as matched. 17 1 read-write ESVL Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets. 18 1 read-write ERSVLM Enable Receive S-VLAN Match When this bit is set, the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets. When this bit is reset, the MAC receiver enables filtering or matching for C-VLAN (Type = 0x8100) packets. The ERIVLT bit determines the VLAN tag position considered for filtering or matching. 19 1 read-write DOVLTC Disable VLAN Type Check When this bit is set, the MAC does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN. When this bit is reset, the MAC filters or matches the VLAN Tag specified by the ERIVLT bit only when VLAN Tag type is similar to the one specified by the ERSVLM bit. 20 1 read-write EVLS Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet: 21 2 read-write EVLRXS Enable VLAN Tag in Rx status When this bit is set, MAC provides the outer VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the outer VLAN Tag in Rx status. 24 1 read-write VTHM VLAN Tag Hash Table Match Enable When this bit is set, the most significant four bits of CRC of VLAN Tag are used to index the content of the ETH_MACVLANHTR register. A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the packet matched the VLAN Hash table. When the ETV bit is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison. When the ETV bit is reset, the CRC of the 16-bit VLAN tag is used for comparison. When this bit is reset, the VLAN Hash Match operation is not performed. 25 1 read-write EDVLP Enable Double VLAN Processing When this bit is set, the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present). When this bit is reset, the MAC enables processing of up to one VLAN Tag on Tx and Rx (if present). 26 1 read-write ERIVLT Enable Inner VLAN Tag When this bit and the EDVLP field are set, the MAC receiver enables operation on the inner VLAN Tag (if present). When this bit is reset, the MAC receiver enables operation on the outer VLAN Tag (if present). The ERSVLM bit determines which VLAN type is enabled for filtering or matching.The ERSVLM bit and DOVLTC bit determines which VLAN type is enabled for filtering. 27 1 read-write EIVLS Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet: 28 2 read-write EIVLRXS Enable Inner VLAN Tag in Rx Status When this bit is set, the MAC provides the inner VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the inner VLAN Tag in Rx status. 31 1 read-write MACVHTR MACVHTR VLAN Hash table register 0x58 0x20 0x00000000 0xFFFFFFFF VLHT VLAN Hash Table This field contains the 16-bit VLAN Hash Table. 0 16 read-write MACVIR MACVIR VLAN inclusion register 0x60 0x20 0x00000000 0xFFFFFFFF VLT VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. The following list describes the bits of this field: Bits[15:13]: User Priority Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) Bits[11:0]: VLAN Identifier (VID) field of VLAN tag 0 16 read-write VLC VLAN Tag Control in Transmit Packets Note: Changes to this field take effect only on the start of a packet. If you write this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. 16 2 read-write VLP VLAN Priority Control When this bit is set, the control bits[17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, bits[17:16] are ignored. 18 1 read-write CSVL C-VLAN or S-VLAN When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets. 19 1 read-write VLTI VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from the Tx descriptor. 20 1 read-write MACIVIR MACIVIR Inner VLAN inclusion register 0x64 0x20 0x00000000 0xFFFFFFFF VLT VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. The following list describes the bits of this field: Bits[15:13]: User Priority Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) Bits[11:0]: VLAN Identifier (VID) field of VLAN tag 0 16 read-write VLC VLAN Tag Control in Transmit Packets The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags. The MAC inserts VLT in bytes 19 and 20 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 17 and 18. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag. The MAC replaces VLT in bytes 19 and 20 of all VLAN-type transmitted packets (Bytes 17 and 18 are 0x8100 or 0x88a8). Note: Changes to this field take effect only on the start of a packet. If you write to this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. 16 2 read-write VLP VLAN Priority Control When this bit is set, the VLC field is used for VLAN deletion, insertion, or replacement. When this bit is reset, the VLC field is ignored. 18 1 read-write CSVL C-VLAN or S-VLAN When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets. 19 1 read-write VLTI VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from the Tx descriptor 20 1 read-write MACQTXFCR MACQTXFCR Tx Queue flow control register 0x70 0x20 0x00000000 0xFFFFFFFF FCB_BPA Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the Full-duplex mode and activates the backpressure function in the Half-duplex mode if the TFE bit is set. Full-Duplex mode: this bit should be read as 0 before writing to this register. To initiate a Pause packet, the application must set this bit to 1. During Control packet transfer, this bit continues to be set to indicate that a packet transmission is in progress. When Pause packet transmission is complete, the MAC resets this bit to 0. You should not write to this register until this bit is cleared. Half-duplex mode: When this bit is set (and TFE bit is set) in the Half-duplex mode, the MAC asserts the backpressure. During backpressure, when the MAC receives a new packet, the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the Full-duplex mode, the BPA is automatically disabled. 0 1 read-write TFE Transmit Flow Control Enable Full-duplex mode: when this bit is set, the MAC enables the flow control operation to Tx Pause packets. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause packets. Half-duplex mode: when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. 1 1 read-write PLT Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow is checked for automatic retransmission of the Pause packet. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot times), and PLT = 001, a second Pause packet is automatically transmitted at 228 (256-28) slot times after the first Pause packet is transmitted. The following list provides the threshold values for different values: 110 to 111: Reserved, must not be used The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface. This (approximate) computation is based on the packet size (64, 1518, 2000, 9018, 16384, or 32768) + 2 Pause Packet Size + IPG in Slot Times. 4 3 read-write DZPQ Disable Zero-Quanta Pause When this bit is set, it disables the automatic generation of the zero-quanta Pause packets. When this bit is reset, normal operation with automatic zero-quanta Pause packet generation is enabled. 7 1 read-write PT Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. I 16 16 read-write MACRXFCR MACRXFCR Rx flow control register 0x90 0x20 0x00000000 0xFFFFFFFF RFE Receive Flow Control Enable When this bit is set and the MAC is operating in Full-duplex mode, the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time. When this bit is reset or the MAC is operating in Half-duplex mode, the decode function of the Pause packet is disabled. When PFC is enabled, flow control is enabled for PFC packets. The MAC decodes the received PFC packet and disables the Transmit queue, with matching priorities, for a duration of received Pause time. 0 1 read-write UP Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802.3. When this bit is set, the MAC can also detect Pause packets with unicast address of the station. This unicast address should be as specified in MAC Address 0 high register (ETH_MACA0HR) and MAC Address 0 low register MAC Address x low register (ETH_MACAxLR). When this bit is reset, the MAC only detects Pause packets with unique multicast address. Note: The MAC does not process a Pause packet if the multicast address is different from the unique multicast address. This is also applicable to the received PFC packet when the Priority Flow Control (PFC) is enabled. The unique multicast address (0x01_80_C2_00_00_01) is as specified in IEEE 802.1 Qbb-2011. 1 1 read-write MACISR MACISR Interrupt status register 0xB0 0x20 0x00000000 0xFFFFFFFF PHYIS PHY Interrupt This bit is set when rising edge is detected on the ETH_PHY_INTN input. This bit is cleared when this register is read. 3 1 read-only PMTIS PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in ETH_MACPCSR register). This bit is cleared when Bits[6:5] are cleared because of a Read operation to the PMT control status register (ETH_MACPCSR). 4 1 read-only LPIIS LPI Interrupt Status This bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared when the TLPIEN bit of LPI control and status register (ETH_MACLCSR) is read. 5 1 read-only MMCIS MMC Interrupt Status This bit is set high when MMCTXIS or MMCRXIS is set high. This bit is cleared only when all these bits are low. 8 1 read-only MMCRXIS MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Rx interrupt register (ETH_MMC_RX_INTERRUPT). This bit is cleared when all bits in this interrupt register are cleared. 9 1 read-only MMCTXIS MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Tx interrupt register (ETH_MMC_TX_INTERRUPT). This bit is cleared when all bits in this interrupt register are cleared. 10 1 read-only TSIS Timestamp Interrupt Status If the Timestamp feature is enabled, this bit is set when any of the following conditions is true: The system time value is equal to or exceeds the value specified in the Target Time High and Low registers. There is an overflow in the Seconds register. The Target Time Error occurred, that is, programmed target time already elapsed. If the Auxiliary Snapshot feature is enabled, this bit is set when the auxiliary snapshot trigger is asserted. When drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the Tx timestamp status nanoseconds register (ETH_MACTXTSSNR) and Tx timestamp status seconds register (ETH_MACTXTSSSR) registers. When PTP offload feature is enabled, this bit is set when the captured transmit timestamp is updated in the Tx timestamp status nanoseconds register (ETH_MACTXTSSNR) and Tx timestamp status seconds register (ETH_MACTXTSSSR) registers, for PTO generated Delay Request and Pdelay request packets. This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of CSR software control register (ETH_MACCSRSWCR) is set) in the Timestamp status register (ETH_MACTSSR). 12 1 read-write clear TXSTSIS Transmit Status Interrupt This bit indicates the status of transmitted packets. This bit is set when any of the following bits is set in the Rx Tx status register (ETH_MACRXTXSR): Excessive Collision (EXCOL) Late Collision (LCOL) Excessive Deferral (EXDEF) Loss of Carrier (LCARR) No Carrier (NCARR) Jabber Timeout (TJT) This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of CSR software control register (ETH_MACCSRSWCR) is set) in the ETH_MACISR register. 13 1 read-write clear RXSTSIS Receive Status Interrupt This bit indicates the status of received packets. This bit is set when the RWT bit is set in the Rx Tx status register (ETH_MACRXTXSR). This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of CSR software control register (ETH_MACCSRSWCR) is set) in the ETH_MACISR register. 14 1 read-write clear MACIER MACIER Interrupt enable register 0xB4 0x20 0x00000000 0xFFFFFFFF PHYIE PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of PHYIS bit in Interrupt status register (ETH_MACISR). 3 1 read-write PMTIE PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of PMTIS bit in Interrupt status register (ETH_MACISR). 4 1 read-write LPIIE LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of LPIIS bit in Interrupt status register (ETH_MACISR). 5 1 read-write TSIE Timestamp Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of TSIS bit in Interrupt status register (ETH_MACISR). 12 1 read-write TXSTSIE Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the Interrupt status register (ETH_MACISR). 13 1 read-write RXSTSIE Receive Status Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the Interrupt status register (ETH_MACISR). 14 1 read-write MACRXTXSR MACRXTXSR Rx Tx status register 0xB8 0x20 0x00000000 0xFFFFFFFF TJT Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) and JD bit is reset in the Operating mode configuration register (ETH_MACCR). This bit is set when the packet size exceeds 16,383 bytes and the JD bit is set in the Operating mode configuration register (ETH_MACCR). Cleared on read (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 0 1 read-write clear NCARR No Carrier When the DTXSTS bit is set in the Operating mode Register (ETH_MTLOMR), this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. Cleared on read (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 1 1 read-write clear LCARR Loss of Carrier When the DTXSTS bit is set in the Operating mode Register (ETH_MTLOMR), this bit indicates that the loss of carrier occurred during packet transmission, that is, the ETH_CRS signal was inactive for one or more transmission clock periods during packet transmission. This bit is valid only for packets transmitted without collision. Cleared on read (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 2 1 read-write clear EXDEF Excessive Deferral When the DTXSTS bit is set in the Operating mode Register (ETH_MTLOMR) and the DC bit is set in the Operating mode configuration register (ETH_MACCR), this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when Jumbo packet is enabled). Cleared on read (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 3 1 read-write clear LCOL Late Collision When the DTXSTS bit is set in the Operating mode Register (ETH_MTLOMR), this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode. This bit is not valid if the Underflow error occurs. Cleared on read (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 4 1 read-write clear EXCOL Excessive Collisions When the DTXSTS bit is set in the Operating mode Register (ETH_MTLOMR), this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the Operating mode configuration register (ETH_MACCR), this bit is set after the first collision and the packet transmission is aborted. Cleared on read (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 5 1 read-write clear RWT Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the Operating mode configuration register (ETH_MACCR). This bit is set when a packet with length greater than 16,383 bytes is received and the WD bit is set in the Operating mode configuration register (ETH_MACCR). Cleared on read (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 8 1 read-write clear MACPCSR MACPCSR PMT control status register 0xC0 0x20 0x00000000 0xFFFFFFFF PWRDWN Power Down When this bit is set, the MAC receiver drops all received packets until it receives the expected magic packet or remote wakeup packet. This bit is then self-cleared and the power-down mode is disabled. The software can clear this bit before the expected magic packet or remote wakeup packet is received. The packets received by the MAC after this bit is cleared are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote wakeup Packet Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. 0 1 read-write MGKPKTEN Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet. 1 1 read-write RWKPKTEN Remote wakeup Packet Enable When this bit is set, a power management event is generated when the MAC receives a remote wakeup packet. 2 1 read-write MGKPRCVD Magic Packet Received When this bit is set, it indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared when this register is read (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 5 1 read-write clear RWKPRCVD Remote wakeup Packet Received When this bit is set, it indicates that the power management event is generated because of the reception of a remote wakeup packet. This bit is cleared when this register is read. 6 1 read-only GLBLUCAST Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wakeup packet. 9 1 read-write RWKPFE Remote wakeup Packet Forwarding Enable When this bit is set along with RWKPKTEN, the MAC receiver drops all received frames until it receives the expected wakeup frame. All frames after that event including the received wakeup frame are forwarded to application. This bit is then self-cleared on receiving the wakeup packet. The application can also clear this bit before the expected wakeup frame is received. In such cases, the MAC reverts to the default behavior where packets received are forwarded to the application. This bit must only be set when RWKPKTEN is set high and PWRDWN is set low. The setting of this bit has no effect when PWRDWN is set high. Note: If Magic Packet Enable and wakeup Frame Enable are both set along with setting of this bit and Magic Packet is received prior to wakeup frame, this bit is self-cleared on receiving Magic Packet, the received Magic packet is dropped, and all frames after received Magic Packet are forwarded to application. 10 1 read-write RWKPTR Remote wakeup FIFO Pointer This field gives the current value (0 to 7) of the Remote wakeup Packet Filter register pointer. When the value of this pointer is equal to 7, the contents of the Remote wakeup Packet Filter Register are transferred to the eth_mii_rx_clk domain when a Write occurs to that register. 24 5 read-only RWKFILTRST Remote wakeup Packet Filter Register Pointer Reset When this bit is set, the remote wakeup packet filter register pointer is reset to 0. It is automatically cleared after 1 clock cycle. 31 1 read-write MACRWKPFR MACRWKPFR Remote wakeup packet filter register 0xC4 0x20 0x00000000 0xFFFFFFFF MACRWKPFR Remote wakeup packet filter Refer to Table 532, Table 533 and Table 534 for details on register content and programming sequence. 0 32 read-write MACLCSR MACLCSR LPI control and status register 0xD0 0x20 0x00000000 0xFFFFFFFF TLPIEN Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 0 1 read-only TLPIEX Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 1 1 read-only RLPIEN Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than three clock cycles of CSR clock. 2 1 read-only RLPIEX Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than three clock cycles of CSR clock. 3 1 read-only TLPIST Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface. 8 1 read-only RLPIST Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface. 9 1 read-only LPIEN LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state. When this bit is reset, it instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. 16 1 read-write PLS PHY Link Status This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (OKAY) at least for the time indicated by the LPI LS TIMER. When this bit is set, the link is considered to be okay (UP) and when this bit is reset, the link is considered to be down. 17 1 read-write LPITXA LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding packets (in the core) and pending packets (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any packet for transmission or the application issues a Tx FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If Tx FIFO Flush is set in the FTQ bit of ETH_MTLTxQOMR, when the MAC is in the LPI mode, it exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. 19 1 read-write LPITE LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. When LPITE, LPITXA and LPIEN bits are set, the MAC Transmitter enters LPI state only when the complete MAC TX data path is IDLE for a period indicated by the ETH_MACLETR register. After entering LPI state, if the data path becomes non-IDLE (due to a new packet being accepted for transmission), the Transmitter exits LPI state but does not clear LPIEN bit. This enables the re-entry into LPI state when it is IDLE again. When LPITE is 0, the LPI Auto timer is disabled and MAC Transmitter enters LPI state based on the settings of LPITXA and LPIEN bit descriptions. 20 1 read-write LPITCSE LPI Tx Clock Stop Enable When this bit is set, the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped. When this bit is reset, the MAC does not assert sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode. If RGMII Interface is selected, the Tx clock is required for transmitting the LPI pattern. The Tx Clock cannot be gated and so the LPITCSE bit cannot be programmed. 21 1 read-write MACLTCR MACLTCR LPI timers control register 0xD4 0x20 0x03E80000 0xFFFFFFFF TWT LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. 0 16 read-write LST LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. 16 10 read-write MACLETR MACLETR LPI entry timer register 0xD8 0x20 0x00000000 0xFFFFFFFF LPIET LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI mode, after it has transmitted all the frames. This field is valid and used only when LPITE and LPITXA are set to 1. Bits [2:0] are read-only so that the granularity of this timer is in steps of 8 micro-seconds. 0 20 read-write MAC1USTCR MAC1USTCR One-microsecond-tick counter register 0xDC 0x20 0x00000000 0xFFFFFFFF TIC_1US_CNTR 1 s tick Counter The application must program this counter so that the number of clock cycles of CSR clock is 1 s (subtract 1 from the value before programming). For example if the CSR clock is 100 MHz then this field needs to be programmed to 100 - 1 = 99 (which is 0x63). This is required to generate the 1 s events that are used to update some of the EEE related counters. 0 12 read-write MACVR MACVR Version register 0x110 0x20 0x00003242 0xFFFFFFFF SNPSVER IP version 0 8 read-only USERVER ST-defined version 8 8 read-only MACDR MACDR Debug register 0x114 0x20 0x00000000 0xFFFFFFFF RPESTS MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC MII receive protocol engine is actively receiving data, and it is not in the Idle state. 0 1 read-only RFCFCSTS MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module. 1 2 read-only TPESTS MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC MII transmit protocol engine is actively transmitting data, and it is not in the Idle state. 16 1 read-only TFCSTS MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module: Status of the previous packet IPG or backoff period to be over 17 2 read-only MACHWF0R MACHWF0R HW feature 0 register 0x11C 0x20 0x0A0D73F7 0xFFFFFFFF MIISEL 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as operating mode. 0 1 read-only GMIISEL 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as operating mode. 1 1 read-only HDSEL Half-duplex Support This bit is set to 1 when the Half-duplex mode is selected 2 1 read-only PCSSEL PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI, SGMII, or RTBI PHY interface option is selected 3 1 read-only VLHASH VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected 4 1 read-only SMASEL SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected 5 1 read-only RWKSEL PMT Remote Wakeup Packet Enable This bit is set to 1 when the Enable Remote wakeup Packet Detection option is selected 6 1 read-only MGKSEL PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected 7 1 read-only MMCSEL RMON Module Enable This bit is set to 1 when the Enable MAC management counters (MMC) option is selected 8 1 read-only ARPOFFSEL ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected 9 1 read-only TSSEL IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected 12 1 read-only EEESEL Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected 13 1 read-only TXCOESEL Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected 14 1 read-only RXCOESEL Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected 16 1 read-only ADDMACADRSEL MAC Addresses 1-31 Selected This bit is set to 1 when the Enable Additional 1-31 MAC Address Registers option is selected 18 5 read-only MACADR32SEL MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected 23 1 read-only MACADR64SEL MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected 24 1 read-only TSSTSSEL Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected 25 2 read-only SAVLANINS Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected 27 1 read-only ACTPHYSEL Active PHY Selected When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion: Others: Reserved, must not be used 28 3 read-only MACHWF1R MACHWF1R HW feature 1 register 0x120 0x20 0x11041904 0xFFFFFFFF RXFIFOSIZE MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7: 01100 to 11111: Reserved, must not be used 0 5 read-only TXFIFOSIZE MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7: 01011 to 11111: Reserved, must not be used 6 5 read-only OSTEN One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. 11 1 read-only PTOEN PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. 12 1 read-only ADVTHWORD IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected 13 1 read-only ADDR64 Address width This field indicates the configured address width. Others: Reserved, must not be used 14 2 read-only DCBEN DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected 16 1 read-only SPHEN Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected 17 1 read-only TSOEN TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected 18 1 read-only DBGMEMA DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected 19 1 read-only AVSEL AV Feature Enable This bit is set to 1 when the Enable Audio video bridging option is selected. 20 1 read-only RAVSEL Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio video bridging option on Rx Side Only is selected. 21 1 read-only POUOST One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable one step timestamp for PTP over UDP/IP feature is selected. 23 1 read-only HASHTBLSZ Hash Table Size This field indicates the size of the Hash table: 24 2 read-only L3L4FNUM Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: .. 27 4 read-only MACHWF2R MACHWF2R HW feature 2 register 0x124 0x20 0x41000000 0xFFFFFFFF RXQCNT Number of MTL Receive Queues This field indicates the number of MTL Receive queues: .. 0 4 read-only TXQCNT Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues: .. 6 4 read-only RXCHCNT Number of DMA Receive Channels This field indicates the number of DMA Receive channels: .. 12 4 read-only RDCSZ Rx DMA Descriptor Cache Size in terms of 16-byte descriptors 16 2 read-only TXCHCNT Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels: .. 18 4 read-only TDCSZ Tx DMA Descriptor Cache Size in terms of 16-byte descriptors 22 2 read-only PPSOUTNUM Number of PPS Outputs This field indicates the number of PPS outputs: 101 to 111: Reserved, must not be used 24 3 read-only AUXSNAPNUM Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs: 101 to 111: Reserved, must not be used 28 3 read-only MACHWF3R MACHWF3R HW feature 3 register 0x128 0x20 0x00000020 0xFFFFFFFF NRVF Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected: 110 to 111: Reserved, must not be used 0 3 read-only CBTISEL Queue/Channel based VLAN tag insertion on Tx enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx feature is selected. 4 1 read-only DVLAN Double VLAN processing enable This bit is set to 1 when Double VLAN processing is enabled. 5 1 read-only MACMDIOAR MACMDIOAR MDIO address register 0x200 0x20 0x00000000 0xFFFFFFFF MB MII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIOS. The MAC clears this bit after the MDIO frame transfer is completed. Hence the software must not write or change any of the fields in MDIO address register (ETH_MACMDIOAR) and MDIO data register (ETH_MACMDIODR) as long as this bit is set. For write transfers, the application must first write 16-bit data in the MD field (and also RA field when C45E is set) in MDIO data register (ETH_MACMDIODR) register before setting this bit. When C45E is set, it should also write into the RA field of MDIO data register (ETH_MACMDIODR) before initiating a read transfer. When a read transfer is completed (MII busy=0), the data read from the PHY register is valid in the MD field of the MDIO data register (ETH_MACMDIODR). Note: Even if the addressed PHY is not present, there is no change in the functionality of this bit. 0 1 read-write C45E Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO. When this bit is reset, Clause 22 capable PHY is connected to MDIO. 1 1 read-write GOC MII Operation Command This bit indicates the operation command to the PHY. When Clause 22 PHY is enabled, only Write and Read commands are valid. 2 2 read-write SKAP Skip Address Packet When this bit is set, the SMA does not send the address packets before read, write, or post-read increment address packets. This bit is valid only when C45E is set. 4 1 read-write CR CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: 0110 to 0111: Reserved, must not be used The suggested range of CSR clock frequency applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.0 MHz to 2.5 MHz frequency range. When Bit 11 is set, you can achieve a higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits to 1010, the resultant MDC clock is of 12.5 MHz which is above the range specified in IEEE 802.3. Program the following values only if the interfacing chips support faster MDC clocks: 8 4 read-write NTC Number of Training Clocks This field controls the number of trailing clock cycles generated on ETH_MDC after the end of transmission of MDIO frame. The valid values can be from 0 to 7. Programming the value to 011 indicates that there are additional three clock cycles on the MDC line after the end of MDIO frame transfer. 12 3 read-write RDA Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. These bits select the Device (MMD) in selected Clause 45 capable PHY. 16 5 read-write PA Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. This field indicates which Clause 45 capable PHYs (out of 32 PHYs) the MAC is accessing. 21 5 read-write BTB Back to Back transactions When this bit is set and the NTC has value greater than 0, then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted). The software can thus initiate the next command which is executed immediately irrespective of the number trailing clocks generated for the previous frame. When this bit is reset, then the read/write command completion (MII busy is cleared) only after the trailing clocks are generated. In this mode, it is ensured that the NTC is always generated after each frame. This bit must not be set when NTC=0. 26 1 read-write PSE Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble and transmit MDIO frames with only 1 preamble bit. When this bit is 0, the MDIO frame always has 32 bits of preamble as defined in the IEEE specifications. 27 1 read-write MACMDIODR MACMDIODR MDIO data register 0x204 0x20 0x00000000 0xFFFFFFFF MD MII Data This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. 0 16 read-write RA Register Address This field is valid only when C45E is set. It contains the Register Address in the PHY to which the MDIO frame is intended for. 16 16 read-write MACARPAR MACARPAR ARP address register 0x210 0x20 0x00000000 0xFFFFFFFF ARPPA ARP Protocol Address This field contains the IPv4 Destination Address of the MAC. This address is used for perfect match with the Protocol Address of Target field in the received ARP packet. 0 32 read-write MACCSRSWCR MACCSRSWCR CSR software control register 0x230 0x20 0x00000000 0xFFFFFFFF RCWE Register Clear on Write 1 Enable When this bit is set, the access mode to some register fields changes to rc_w1 (clear on write) meaning that the application needs to set that respective bit to 1 to clear it. When this bit is reset, the access mode to these register fields remains rc_r (clear on read). 0 1 read-write SEEN Slave Error Response Enable When this bit is set, the MAC responds with a Slave Error for accesses to reserved registers in CSR space. When this bit is reset, the MAC responds with an Okay response to any register accessed from CSR space. 8 1 read-write MACA0HR MACA0HR MAC Address 0 high register 0x300 0x20 0x8000FFFF 0xFFFFFFFF ADDRHI MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. 0 16 read-write AE Address Enable This bit is always set to 1. 31 1 read-only MACA0LR MACA0LR MAC Address 0 low register 0x304 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. 0 32 read-write MACA1HR MACA1HR MAC Address 1 high register 0x308 0x20 0x0000FFFF 0xFFFFFFFF ADDRHI MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: Bit 29: ETH_MACAxHR[15:8] Bit 28: ETH_MACAxHR[7:0] Bit 27: ETH_MACAxLR[31:24] Bit 26: ETH_MACAxLR[23:16] Bit 25: ETH_MACAxLR[15:8] Bit 24: ETH_MACAxLR[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. 24 6 read-write SA Source Address When this bit is set, the MAC Addressx[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address x[47:0] is used to compare with the DA fields of the received packet. 30 1 read-write AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. 31 1 read-write MACA1LR MACA1LR MAC Address 1 low register 0x30C 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. 0 32 read-write MACA2HR MACA2HR MAC Address 2 high register 0x310 0x20 0x0000FFFF 0xFFFFFFFF ADDRHI MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: Bit 29: ETH_MACAxHR[15:8] Bit 28: ETH_MACAxHR[7:0] Bit 27: ETH_MACAxLR[31:24] Bit 26: ETH_MACAxLR[23:16] Bit 25: ETH_MACAxLR[15:8] Bit 24: ETH_MACAxLR[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. 24 6 read-write SA Source Address When this bit is set, the MAC Addressx[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address x[47:0] is used to compare with the DA fields of the received packet. 30 1 read-write AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. 31 1 read-write MACA2LR MACA2LR MAC Address 2 low register 0x314 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. 0 32 read-write MACA3HR MACA3HR MAC Address 3 high register 0x318 0x20 0x0000FFFF 0xFFFFFFFF ADDRHI MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: Bit 29: ETH_MACAxHR[15:8] Bit 28: ETH_MACAxHR[7:0] Bit 27: ETH_MACAxLR[31:24] Bit 26: ETH_MACAxLR[23:16] Bit 25: ETH_MACAxLR[15:8] Bit 24: ETH_MACAxLR[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. 24 6 read-write SA Source Address When this bit is set, the MAC Addressx[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address x[47:0] is used to compare with the DA fields of the received packet. 30 1 read-write AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. 31 1 read-write MACA3LR MACA3LR MAC Address 3 low register 0x31C 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. 0 32 read-write MMC_CONTROL MMC_CONTROL MMC control register 0x700 0x20 0x00000000 0xFFFFFFFF CNTRST Counters Reset When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle. 0 1 read-write CNTSTOPRO Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value. 1 1 read-write RSTONRD Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. 2 1 read-write CNTFREEZ MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received packet. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. 3 1 read-write CNTPRST Counters Preset When this bit is set, all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit. This bit is cleared automatically after 1 clock cycle. This bit, along with the CNTPRSTLVL bit, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. 4 1 read-write CNTPRSTLVL Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (Half 2Kbytes) and all packet-counters get preset to 0x7FFF_FFF0 (Half 16). When this bit is high and the CNTPRST bit is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (Full 2Kbytes) and all packet-counters get preset to 0xFFFF_FFF0 (Full 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and packet counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. 5 1 read-write UCDBC Update MMC Counters for Dropped Broadcast Packets The CNTRST bit has a higher priority than the CNTPRST bit. Therefore, when the software tries to set both bits in the same write cycle, all counters are cleared and the CNTPRST bit is not set. When set, the MAC updates all related MMC Counters for Broadcast packets that are dropped because of the setting of the DBF bit of Packet filtering control register (ETH_MACPFR). When reset, the MMC Counters are not updated for dropped Broadcast packets. 8 1 read-write MMC_RX_INTERRUPT MMC_RX_INTERRUPT MMC Rx interrupt register 0x704 0x20 0x00000000 0xFFFFFFFF RXCRCERPIS MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the Rx CRC error packets register (ETH_RX_CRC_ERROR_PACKETS) counter reaches half of the maximum value or the maximum value. 5 1 read-write clear RXALGNERPIS MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the Rx alignment error packets register (ETH_RX_ALIGNMENT_ERROR_PACKETS) counter reaches half of the maximum value or the maximum value. 6 1 read-write clear RXUCGPIS MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the Rx unicast packets good register (ETH_RX_UNICAST_PACKETS_GOOD) counter reaches half of the maximum value or the maximum value. 17 1 read-write clear RXLPIUSCIS MMC Receive LPI microsecond counter interrupt status This bit is set when the Rx LPI microsecond counter register (ETH_RX_LPI_USEC_CNTR) counter reaches half of the maximum value or the maximum value. 26 1 read-write clear RXLPITRCIS MMC Receive LPI transition counter interrupt status This bit is set when the Rx LPI transition counter register (ETH_RX_LPI_TRAN_CNTR) counter reaches half of the maximum value or the maximum value. 27 1 read-write clear MMC_TX_INTERRUPT MMC_TX_INTERRUPT MMC Tx interrupt register 0x708 0x20 0x00000000 0xFFFFFFFF TXSCOLGPIS MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the Tx single collision good packets register (ETH_TX_SINGLE_COLLISION_GOOD_PACKETS) counter reaches half of the maximum value or the maximum value. 14 1 read-write clear TXMCOLGPIS MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the Tx multiple collision good packets register (ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS) counter reaches half of the maximum value or the maximum value. 15 1 read-write clear TXGPKTIS MMC Transmit Good Packet Counter Interrupt Status This bit is set when the Tx packet count good register (ETH_TX_PACKET_COUNT_GOOD) counter reaches half of the maximum value or the maximum value. 21 1 read-write clear TXLPIUSCIS MMC Transmit LPI microsecond counter interrupt status This bit is set when the Tx LPI microsecond timer register (ETH_TX_LPI_USEC_CNTR) counter reaches half of the maximum value or the maximum value. 26 1 read-write clear TXLPITRCIS MMC Transmit LPI transition counter interrupt status This bit is set when the Tx LPI transition counter register (ETH_TX_LPI_TRAN_CNTR) counter reaches half of the maximum value or the maximum value. 27 1 read-write clear MMC_RX_INTERRUPT_MASK MMC_RX_INTERRUPT_MASK MMC Rx interrupt mask register 0x70C 0x20 0x00000000 0xFFFFFFFF RXCRCERPIM MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the Rx CRC error packets register (ETH_RX_CRC_ERROR_PACKETS) counter reaches half of the maximum value or the maximum value. 5 1 read-write RXALGNERPIM MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the Rx alignment error packets register (ETH_RX_ALIGNMENT_ERROR_PACKETS) counter reaches half of the maximum value or the maximum value. 6 1 read-write RXUCGPIM MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the Rx unicast packets good register (ETH_RX_UNICAST_PACKETS_GOOD) counter reaches half of the maximum value or the maximum value. 17 1 read-write RXLPIUSCIM MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Rx LPI microsecond counter register (ETH_RX_LPI_USEC_CNTR) counter reaches half of the maximum value or the maximum value. 26 1 read-write RXLPITRCIM MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Rx LPI transition counter register (ETH_RX_LPI_TRAN_CNTR) counter reaches half of the maximum value or the maximum value. 27 1 read-write MMC_TX_INTERRUPT_MASK MMC_TX_INTERRUPT_MASK MMC Tx interrupt mask register 0x710 0x20 0x00000000 0xFFFFFFFF TXSCOLGPIM MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the Tx single collision good packets register (ETH_TX_SINGLE_COLLISION_GOOD_PACKETS) counter reaches half of the maximum value or the maximum value. 14 1 read-write TXMCOLGPIM MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the Tx multiple collision good packets register (ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS) counter reaches half of the maximum value or the maximum value. 15 1 read-write TXGPKTIM MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the Tx packet count good register (ETH_TX_PACKET_COUNT_GOOD) counter reaches half of the maximum value or the maximum value. 21 1 read-write TXLPIUSCIM MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Tx LPI microsecond timer register (ETH_TX_LPI_USEC_CNTR) counter reaches half of the maximum value or the maximum value. 26 1 read-write TXLPITRCIM MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Tx LPI transition counter register (ETH_TX_LPI_TRAN_CNTR) counter reaches half of the maximum value or the maximum value. 27 1 read-write TX_SINGLE_COLLISION_GOOD_PACKETS TX_SINGLE_COLLISION_GOOD_PACKETS Tx single collision good packets register 0x74C 0x20 0x00000000 0xFFFFFFFF TXSNGLCOLG Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the Half-duplex mode. 0 32 read-only TX_MULTIPLE_COLLISION_GOOD_PACKETS TX_MULTIPLE_COLLISION_GOOD_PACKETS Tx multiple collision good packets register 0x750 0x20 0x00000000 0xFFFFFFFF TXMULTCOLG Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the Half-duplex mode. 0 32 read-only TX_PACKET_COUNT_GOOD TX_PACKET_COUNT_GOOD Tx packet count good register 0x768 0x20 0x00000000 0xFFFFFFFF TXPKTG Tx Packet Count Good This field indicates the number of good packets transmitted. 0 32 read-only RX_CRC_ERROR_PACKETS RX_CRC_ERROR_PACKETS Rx CRC error packets register 0x794 0x20 0x00000000 0xFFFFFFFF RXCRCERR Rx CRC Error Packets This field indicates the number of packets received with CRC error. 0 32 read-only RX_ALIGNMENT_ERROR_PACKETS RX_ALIGNMENT_ERROR_PACKETS Rx alignment error packets register 0x798 0x20 0x00000000 0xFFFFFFFF RXALGNERR Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. It is valid only in 10/100 mode. 0 32 read-only RX_UNICAST_PACKETS_GOOD RX_UNICAST_PACKETS_GOOD Rx unicast packets good register 0x7C4 0x20 0x00000000 0xFFFFFFFF RXUCASTG Rx Unicast Packets Good This field indicates the number of good unicast packets received. 0 32 read-only TX_LPI_USEC_CNTR TX_LPI_USEC_CNTR Tx LPI microsecond timer register 0x7EC 0x20 0x00000000 0xFFFFFFFF TXLPIUSC Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. For every Tx LPI Entry and Exit, the Timer value can have an error of +/- 1 microsecond. 0 32 read-only TX_LPI_TRAN_CNTR TX_LPI_TRAN_CNTR Tx LPI transition counter register 0x7F0 0x20 0x00000000 0xFFFFFFFF TXLPITRC Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. Even if Tx LPI Entry occurs in Automate mode (because of LPITXA bit set in the LPI control and status register (ETH_MACLCSR)), the counter increments. 0 32 read-only RX_LPI_USEC_CNTR RX_LPI_USEC_CNTR Rx LPI microsecond counter register 0x7F4 0x20 0x00000000 0xFFFFFFFF RXLPIUSC Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. For every Rx LPI Entry and Exit, the Timer value can have an error of +/- 1 microsecond. 0 32 read-only RX_LPI_TRAN_CNTR RX_LPI_TRAN_CNTR Rx LPI transition counter register 0x7F8 0x20 0x00000000 0xFFFFFFFF RXLPITRC Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred. 0 32 read-only MACL3L4C0R MACL3L4C0R L3 and L4 control 0 register 0x900 0x20 0x00000000 0xFFFFFFFF L3PEN0 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets. The Layer 3 matching is done only when the L3SAM0 or L3DAM0 bit is set. 0 1 read-write L3SAM0 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching. Note: When the L3PEN0 bit is set, you should set either this bit or the L3DAM0 bit because either IPv6 SA or DA can be checked for filtering. 2 1 read-write L3SAIM0 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when the L3SAM0 bit is set. 3 1 read-write L3DAM0 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When the L3PEN0 bit is set, you should set either this bit or the L3SAM0 bit because either IPv6 DA or SA can be checked for filtering. 4 1 read-write L3DAIM0 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when the L3DAM0 bit is set high. 5 1 read-write L3HSBM0 Layer 3 IP SA higher bits match This field contains the number of lower bits of IP source address that are masked for matching in the IPv4 packets. The following list describes the values of this field: .. Condition: IPv6 packets: This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP source or destination address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high. 6 5 read-write L3HDBM0 Layer 3 IP DA higher bits match This field contains the number of higher bits of IP Destination Address that are masked in the IPv4 packets: .. Bits[12:11] of this field correspond to Bits[6:5] of L3HSBM0 which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. Number of bits masked is given by concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: .. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set. 11 5 read-write L4PEN0 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching. The Layer 4 matching is done only when the L4SPM0 or L4DPM0 bit is set. 16 1 read-write L4SPM0 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching. 18 1 read-write L4SPIM0 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4SPM0 bit is set high. 19 1 read-write L4DPM0 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching. 20 1 read-write L4DPIM0 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4DPM0 bit is set high. 21 1 read-write MACL4A0R MACL4A0R Layer4 Address filter 0 register 0x904 0x20 0x00000000 0xFFFFFFFF L4SP0 Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. When the L4PEN0 and L4DPM0 bits are set in L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP0 Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. When the L4PEN0 and L4DPM0 bits are set in L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MACL3A00R MACL3A00R Layer3 Address 0 filter 0 register 0x910 0x20 0x00000000 0xFFFFFFFF L3A00 Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset and the L3SAM0 bit is set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with the IP Source Address field in the IPv4 packets. 0 32 read-write MACL3A10R MACL3A10R Layer3 Address 1 filter 0 register 0x914 0x20 0x00000000 0xFFFFFFFF L3A10 Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset and the L3SAM0 bit is set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with the IP Destination Address field in the IPv4 packets. 0 32 read-write MACL3A20R MACL3A20R Layer3 Address 2 filter 0 register 0x918 0x20 0x00000000 0xFFFFFFFF L3A20 Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field is not used. 0 32 read-write MACL3A30R MACL3A30R Layer3 Address 3 filter 0 register 0x91C 0x20 0x00000000 0xFFFFFFFF L3A30 Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset in the L3 and L4 control 0 register (ETH_MACL3L4C0R), this field is not used. 0 32 read-write MACL3L4C1R MACL3L4C1R L3 and L4 control 1 register 0x930 0x20 0x00000000 0xFFFFFFFF L3PEN1 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets. The Layer 3 matching is done only when the L3SAM1 or L3DAM1 bit is set. 0 1 read-write L3SAM1 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching. Note: When the L3PEN01 bit is set, you should set either this bit or the L3DAM1 bit because either IPv6 SA or DA can be checked for filtering. 2 1 read-write L3SAIM1 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when the L3SAM1 bit is set. 3 1 read-write L3DAM1 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When the L3PEN1 bit is set, you should set either this bit or the L3SAM1 bit because either IPv6 DA or SA can be checked for filtering. 4 1 read-write L3DAIM1 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when the L3DAM1 bit is set high. 5 1 read-write L3HSBM1 Layer 3 IP SA Higher Bits Match This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field: .. This field contains Bits[4:0] of L3HSBM1. These bits indicate the number of higher bits of IP Source or Destination Address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM1 or L3SAM1 bit is set high. 6 5 read-write L3HDBM1 Layer 3 IP DA higher bits match This field contains the number of lower bits of IP Destination Address that are masked for matching in the IPv4 packets. The following list describes the values of this field: .. Bits[12:11] of this field correspond to Bits[6:5] of L3HSBM1, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. The following list describes the concatenated values of the L3HDBM1[1:0] and L3HSBM1 bits: .. This field is valid and applicable only when the L3DAM1 or L3SAM1 bit is set. 11 5 read-write L4PEN1 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching. The Layer 4 matching is done only when the L4SPM1 or L4DPM1 bit is set. 16 1 read-write L4SPM1 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching. 18 1 read-write L4SPIM1 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4SPM1 bit is set high. 19 1 read-write L4DPM1 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching. 20 1 read-write L4DPIM1 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4DPM1 bit is set high. 21 1 read-write MACL4A1R MACL4A1R Layer 4 address filter 1 register 0x934 0x20 0x00000000 0xFFFFFFFF L4SP1 Layer 4 Source Port Number Field When the L4PEN1 bit is reset and the L4DPM1 bit is set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. When the L4PEN1 and L4DPM1 bits are set in L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP1 Layer 4 Destination Port Number Field When the L4PEN1 bit is reset and the L4DPM1 bit is set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. When the L4PEN1 and L4DPM1 bits are set in L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MACL3A01R MACL3A01R Layer3 address 0 filter 1 Register 0x940 0x20 0x00000000 0xFFFFFFFF L3A01 Layer 3 Address 0 Field When the L3PEN1 and L3SAM1bits are set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. When the L3PEN1 and L3DAM1 bits are set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets. When the L3PEN1 bit is reset and the L3SAM1 bit is set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with the IP Source Address field in the IPv4 packets. 0 32 read-write MACL3A11R MACL3A11R Layer3 address 1 filter 1 register 0x944 0x20 0x00000000 0xFFFFFFFF L3A11 Layer 3 Address 1 Field When the L3PEN1 and L3SAM1 bits are set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. When the L3PEN1 and L3DAM1 bits are set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets. When the L3PEN1 bit is reset and the L3SAM1 bit is set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with the IP Destination Address field in the IPv4 packets. 0 32 read-write MACL3A21R MACL3A21R Layer3 address 2 filter 1 Register 0x948 0x20 0x00000000 0xFFFFFFFF L3A21 Layer 3 Address 2 Field When the L3PEN1 and L3SAM1 bits are set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. When the L3PEN1 and L3DAM1 bits are set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets. When the L3PEN1 bit is reset in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field is not used. 0 32 read-write MACL3A31R MACL3A31R Layer3 address 3 filter 1 register 0x94C 0x20 0x00000000 0xFFFFFFFF L3A31 Layer 3 Address 3 Field When the L3PEN1 and L3SAM1 bits are set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. When the L3PEN1 and L3DAM1 bits are set in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets. When the L3PEN1 bit is reset in the L3 and L4 control 1 register (ETH_MACL3L4C1R), this field is not used. 0 32 read-write MACTSCR MACTSCR Timestamp control Register 0xB00 0x20 0x00002000 0xFFFFFFFF TSENA Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets. When disabled, timestamp is not added for transmit and receive packets and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the Receive side, the MAC processes the 1588 packets only if this bit is set. 0 1 read-write TSCFUPDT Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp. When this bit is reset, Coarse method is used to update the system timestamp. 1 1 read-write TSINIT Initialize Timestamp When this bit is set, the system time is initialized (overwritten) with the value specified in the System time seconds update register (ETH_MACSTSUR) and System time nanoseconds update register (ETH_MACSTNUR). This bit should be zero before it is updated. This bit is reset when the initialization is complete. 2 1 read-write TSUPDT Update Timestamp When this bit is set, the system time is updated (added or subtracted) with the value specified in System time seconds update register (ETH_MACSTSUR) and System time nanoseconds update register (ETH_MACSTNUR). This bit should be zero before updating it. This bit is reset when the update is complete in hardware. 3 1 read-write TSADDREG Update Addend Register When this bit is set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This bit is cleared when the update is complete. This bit should be zero before it is set. 5 1 read-write TSENALL Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is enabled for all packets received by the MAC. 8 1 read-write TSCTRLSSR Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When this bit is reset, the rollover value of subsecond register is 0x7FFF_FFFF. The subsecond increment must be programmed correctly depending on the PTP reference clock frequency and the value of this bit. 9 1 read-write TSVER2ENA Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE 1588 version 2 format is used to process the PTP packets. When this bit is reset, the IEEE 1588 version 1 format is used to process the PTP packets. The IEEE 1588 formats are described in 'PTP Processing and Control'. 10 1 read-write TSIPENA Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets. When this bit is reset, the MAC ignores the PTP over Ethernet packets. 11 1 read-write TSIPV6ENA Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets. When this bit is clear, the MAC ignores the PTP transported over IPv6-UDP packets. 12 1 read-write TSIPV4ENA Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets. When this bit is reset, the MAC ignores the PTP transported over IPv4-UDP packets. This bit is set by default. 13 1 read-write TSEVNTENA Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When this bit is reset, the snapshot is taken for all messages except Announce, Management, and Signaling. For more information about the timestamp snapshots, see Table 518: Timestamp Snapshot Dependency on ETH_MACTSCR Bits. 14 1 read-write TSMSTRENA Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot is taken only for the messages that are relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. 15 1 read-write SNAPTYPSEL Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14, define the set of PTP packet types for which snapshot needs to be taken. The encoding is given in Table 518: Timestamp Snapshot Dependency on ETH_MACTSCR Bits. 16 2 read-write TSENMACADDR Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet. When this bit is set, received PTP packets with DA containing a special multicast or unicast address that matches the one programmed in MAC address registers are considered for processing as indicated below, when PTP is directly sent over Ethernet. For normal timestamping operation, MAC address registers 0 to 31 is considered for unicast destination address matching. For PTP offload, only MAC address register 0 is considered for unicast destination address matching. 18 1 read-write TXTSSTSM Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier transmit timestamp status even if it is not read by the software. The MAC indicates this by setting the TXTSSMIS bit of the Tx timestamp status nanoseconds register (ETH_MACTXTSSNR) register. When this bit is reset, the MAC ignores the timestamp status of current packet if the timestamp status of previous packet is not read by the software. The MAC indicates this by setting the TXTSSMIS bit of the Tx timestamp status nanoseconds register (ETH_MACTXTSSNR). 24 1 read-write AV8021ASMEN AV 802.1AS Mode Enable When this bit is set, the MAC processes only untagged PTP over Ethernet packets for providing PTP status and capturing timestamp snapshots, that is, IEEE 802.1AS operating mode. When PTP offload feature is enabled, for the purpose of PTP offload, the transport specific field in the PTP header is generated and checked based on the value of this bit. 28 1 read-write MACSSIR MACSSIR Subsecond increment register 0xB04 0x20 0x00000000 0xFFFFFFFF SSINC Subsecond Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the subsecond register. For example, when the PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time Nanoseconds register has an accuracy of 1 ns [TSCTRLSSR bit is set in Timestamp control Register (ETH_MACTSCR)]. When TSCTRLSSR is cleared, the Nanoseconds register has a resolution of ~0.465 ns. In this case, you should program a value of 43 (0x2B) which is derived by 20 ns/0.465. 16 8 read-write MACSTSR MACSTSR System time seconds register 0xB08 0x20 0x00000000 0xFFFFFFFF TSS Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC. 0 32 read-only MACSTNR MACSTNR System time nanoseconds register 0xB0C 0x20 0x00000000 0xFFFFFFFF TSSS Timestamp subseconds The value in this field has the subsecond representation of time, with an accuracy of 0.46 ns. When TSCTRLSSR is set in Timestamp control Register (ETH_MACTSCR), each bit represents 1 ns. The maximum value is 0x3B9A_C9FF after which it rolls-over to zero. 0 31 read-only MACSTSUR MACSTSUR System time seconds update register 0xB10 0x20 0x00000000 0xFFFFFFFF TSS Timestamp Seconds The value in this field is the seconds part of the update. When ADDSUB is reset, this field must be programmed with the seconds part of the update value. When ADDSUB is set, this field must be programmed with the complement of the seconds part of the update value. For example, to subtract 2.000000001 seconds from the system time, the TSS field in the ETH_MACSTSUR register must be 0xFFFF_FFFE (that is, 2^32 2). When the ADDSUB bit is set, TSSS[30:0] field cannot be set to 0 in System time nanoseconds update register (ETH_MACSTNUR). The TSSS bitfield must be programmed to 0x7FFF FFFF (resulting in 0.46 ns) even if 0 ns must be subtracted. For example, to subtract 2.000000000 seconds from the system time, the TSS field in the System time seconds update register (ETH_MACSTSUR) must be 0xFFFF FFFE (that is, 2^32 1) and the System time nanoseconds update register (ETH_MACSTNUR) must be 0xFFFF FFFF (ADDSUB = 1 and TSSS[30:0] field = 0x7FFF_FFFF) 0 32 read-write MACSTNUR MACSTNUR System time nanoseconds update register 0xB14 0x20 0x00000000 0xFFFFFFFF TSSS Timestamp subseconds The value in this field is the subseconds part of the update. ADDSUB is 1: This field must be programmed with the complement of the subseconds part of the update value as described. ADDSUB is 0: This field must be programmed with the subseconds part of the update value, with an accuracy based on the TSCTRLSSR bit of the Timestamp control Register (ETH_MACTSCR). TSCTRLSSR field in the Timestamp control Register (ETH_MACTSCR)is 1: - The programmed value must be 10^9 <subsecond value>. - Each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. TSCTRLSSR field in the Timestamp control Register (ETH_MACTSCR) is 0: - The programmed value must be 2^31 - <subsecond_value>. - Each bit represents an accuracy of 0.46 ns. For example, to subtract 2.000000001 seconds from the system time, then the TSSS field in the ETH_MACSTNUR register must be 0x7FFF_FFFF (that is, 2^31 1), when TSCTRLSSR bit in Timestamp control Register (ETH_MACTSCR) is reset and 0x3B9A_C9FF (that is, 10^9 1), when TSCTRLSSR bit in Timestamp control Register (ETH_MACTSCR) is set. When the ADDSUB bit is set, TSSS[30:0] field cannot be set to 0. The TSSS bitfield must be programmed to 0x7FFF FFFF (resulting in 0.46 ns) even if 0 ns must be subtracted. For example, to subtract 2.000000000 seconds from the system time, System time nanoseconds update register (ETH_MACSTNUR) must be 0xFFFF FFFF (ADDSUB = 1 and TSSS[30:0] = 0) and the TSS field in the System time seconds update register (ETH_MACSTSUR) must be 0xFFFF FFFE (that is, 2^32 1). 0 31 read-write ADDSUB Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. 31 1 read-write MACTSAR MACTSAR Timestamp addend register 0xB18 0x20 0x00000000 0xFFFFFFFF TSAR Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. 0 32 read-write MACTSSR MACTSSR Timestamp status register 0xB20 0x20 0x00000000 0xFFFFFFFF TSSOVF Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. This bit is cleared when the application reads this bit (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set) 0 1 read-write clear TSTARGT0 Timestamp Target Time Reached When set, this bit indicates that the value of system time is greater than or equal to the value specified in the PPS target time seconds register (ETH_MACPPSTTSR) and PPS target time nanoseconds register (ETH_MACPPSTTNR). This bit is cleared when the application reads this bit (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set) 1 1 read-write clear AUXTSTRIG Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO. This bit is cleared when the application reads this bit (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 2 1 read-write clear TSTRGTERR0 Timestamp Target Time Error This bit is set when the latest target time programmed in the PPS target time seconds register (ETH_MACPPSTTSR) and PPS target time nanoseconds register (ETH_MACPPSTTNR) elapses. This bit is cleared when the application reads this bit (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 3 1 read-write clear TXTSSIS Tx Timestamp Status Interrupt Status When drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the Tx timestamp status nanoseconds register (ETH_MACTXTSSNR) and Tx timestamp status seconds register (ETH_MACTXTSSSR). When PTP offload feature is enabled, this bit is set when the captured transmit timestamp is updated in the Tx timestamp status nanoseconds register (ETH_MACTXTSSNR) and Tx timestamp status seconds register (ETH_MACTXTSSSR), for PTO generated Delay Request and Pdelay request packets. This bit is cleared when the Tx timestamp status seconds register (ETH_MACTXTSSSR) is read (or write of 1 when RCWE bit in CSR software control register (ETH_MACCSRSWCR) is set). 15 1 read-write clear ATSSTN Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: Bit 16: Auxiliary trigger 0 Bit 17: Auxiliary trigger 1 Bit 18: Auxiliary trigger 2 Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. 16 4 read-write clear ATSSTM Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. 24 1 read-write clear ATSNS Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. A value equal to the depth of FIFO (4) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. 25 5 read-only MACTXTSSNR MACTXTSSNR Tx timestamp status nanoseconds register 0xB30 0x20 0x00000000 0xFFFFFFFF TXTSSLO Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp. 0 31 read-write clear TXTSSMIS Transmit Timestamp Status Missed When this bit is set, it indicates one of the following: The timestamp of the current packet is ignored if TXTSSTSM bit of the Timestamp control Register (ETH_MACTSCR) is reset The timestamp of the previous packet is overwritten with timestamp of the current packet if TXTSSTSM bit of the Timestamp control Register (ETH_MACTSCR) is set. 31 1 read-only MACTXTSSSR MACTXTSSSR Tx timestamp status seconds register 0xB34 0x20 0x00000000 0xFFFFFFFF TXTSSHI Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp. 0 32 read-only MACACR MACACR Auxiliary control register 0xB40 0x20 0x00000000 0xFFFFFFFF ATSFC Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, the auxiliary snapshots are stored in the FIFO. 0 1 read-write ATSEN0 Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg0 input is enabled. When this bit is reset, the events on this input are ignored. 4 1 read-write ATSEN1 Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg1 input is enabled. When this bit is reset, the events on this input are ignored. 5 1 read-write ATSEN2 Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg2 input is enabled. When this bit is reset, the events on this input are ignored. 6 1 read-write ATSEN3 Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg3 input is enabled. When this bit is reset, the events on this input are ignored. 7 1 read-write MACATSNR MACATSNR Auxiliary timestamp nanoseconds register 0xB48 0x20 0x00000000 0xFFFFFFFF AUXTSLO Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp. 0 31 read-only MACATSSR MACATSSR Auxiliary timestamp seconds register 0xB4C 0x20 0x00000000 0xFFFFFFFF AUXTSHI Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. 0 32 read-only MACTSIACR MACTSIACR Timestamp Ingress asymmetric correction register 0xB50 0x20 0x00000000 0xFFFFFFFF OSTIAC One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet. The programmed value should be in units of nanoseconds and multiplied by 2^16. For example, 2.5 ns is represented as 0x00028000. The value can also be negative, which is represented in 2's complement form with bit 31 representing the sign bit. 0 32 read-write MACTSEACR MACTSEACR Timestamp Egress asymmetric correction register 0xB54 0x20 0x00000000 0xFFFFFFFF OSTEAC One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet. The programmed value must be the negated value in units of nanoseconds multiplied by 2^16. For example, if the required correction is +2.5 ns, the programmed value must be 0xFFFD_8000, which is the 2's complement of 0x0002_8000(2.5 * 2^16). Similarly, if the required correction is -3.3 ns, the programmed value is 0x0003_4CCC (3.3 *2^16). 0 32 read-write MACTSICNR MACTSICNR Timestamp Ingress correction nanosecond register 0xB58 0x20 0x00000000 0xFFFFFFFF TSIC Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression. 0 32 read-write MACTSECNR MACTSECNR Timestamp Egress correction nanosecond register 0xB5C 0x20 0x00000000 0xFFFFFFFF TSEC Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression. 0 32 read-write MACPPSCR MACPPSCR PPS control register 0xB70 0x20 0x00000000 0xFFFFFFFF PPSCTRL PPS Output Frequency Control This field controls the frequency of the PPS output (eth_ptp_pps_out) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: .. Note: In the binary rollover mode, the PPS output (eth_ptp_pps_out) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of One clock of 50 percent duty cycle and 537 ms period Second clock of 463 ms period (268 ms low and 195 ms high) When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of Three clocks of 50 percent duty cycle and 268 ms period Fourth clock of 195 ms period (134 ms low and 61 ms high) This behavior is because of the non-linear toggling of bits in the digital rollover mode in the ETH_MACSTNR register. 0 4 read-write PPSEN0 Flexible PPS Output Mode Enable When this bit is set, PPSCTRL[3:0] function as PPSCMD[3:0]. When this bit is reset, PPSCTRL[3:0] function as PPSCTRL (Fixed PPS mode). 4 1 read-write TRGTMODSEL0 Target Time Register Mode for PPS Output This field indicates the Target Time registers (PPS target time seconds register (ETH_MACPPSTTSR) and PPS target time nanoseconds register (ETH_MACPPSTTNR)) mode for PPS output signal: 5 2 read-write MACPPSCR_alternate MACPPSCR_alternate PPS control register MACPPSCR 0xB70 0x20 0x00000000 0xFFFFFFFF PPSCMD Flexible PPS Output (eth_ptp_pps_out) Control Programming these bits with a non-zero value instructs the MAC to initiate an event. When the command is transferred or synchronized to the PTP clock domain, these bits get cleared automatically. The software should ensure that these bits are programmed only when they are all zero. The following list describes the values of PPSCMD0: This command generates single pulse rising at the start point defined in Target Time Registers (register 455 and 456) and of a duration defined in the PPS Width Register. This command generates the train of pulses rising at the start point defined in the Target Time Registers and of a duration defined in the PPS Width Register and repeated at interval defined in the PPS Interval Register. By default, the PPS pulse train is free-running unless stopped by the 'Stop Pulse train at time' or 'Stop Pulse Train immediately' commands. This command cancels the START Single Pulse and START Pulse Train commands if the system time has not crossed the programmed start time. This command stops the train of pulses initiated by the START Pulse Train command (PPSCMD[3:0] = 0010) after the time programmed in the Target Time registers elapses. This command immediately stops the train of pulses initiated by the START Pulse Train command (PPSCMD[3:0] = 0010). This command cancels the STOP pulse train at time command if the programmed stop time has not elapsed. The PPS pulse train becomes free-running on the successful execution of this command. 0111 to 1111: Reserved, must not be used 0 4 read-write PPSEN0 Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD[3:0]. When this bit is reset, Bits[3:0] function as PPSCTRL (Fixed PPS mode). 4 1 read-write TRGTMODSEL0 Target Time Register Mode for PPS Output This field indicates the Target Time registers (MAC registers 96 and 97) mode for PPS output signal: 5 2 read-write MACPPSTTSR MACPPSTTSR PPS target time seconds register 0xB80 0x20 0x00000000 0xFFFFFFFF TSTRH0 PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on Target Time mode selected for the corresponding PPS output in the PPS control register (ETH_MACPPSCR). 0 32 read-write MACPPSTTNR MACPPSTTNR PPS target time nanoseconds register 0xB84 0x20 0x00000000 0xFFFFFFFF TTSL0 Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on the TRGTMODSEL0 field (Bits [6:5]) in PPS control register (ETH_MACPPSCR). When the TSCTRLSSR bit is set in the Timestamp control Register (ETH_MACTSCR), this value should not exceed 0x3B9A_C9FF. The actual start or stop time of the PPS signal output may have an error margin up to one unit of subsecond increment value. 0 31 read-write TRGTBUSY0 PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS control register (ETH_MACPPSCR) is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers with the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. 31 1 read-write MACPPSIR MACPPSIR PPS interval register 0xB88 0x20 0x00000000 0xFFFFFFFF PPSINT0 PPS Output Signal Interval These bits store the interval between the rising edges of PPS signal output. The interval is stored in terms of number of units of subsecond increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20 ns), and desired interval between the rising edges of PPS signal output is 100 ns (that is, 5 units of subsecond increment value), you should program value 4 (5-1) in this register. 0 32 read-write MACPPSWR MACPPSWR PPS width register 0xB8C 0x20 0x00000000 0xFFFFFFFF PPSWIDTH0 PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS signal output. The width is stored in terms of number of units of subsecond increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20 ns), and width between the rising and corresponding falling edges of PPS signal output is 80 ns (that is, four units of subsecond increment value), you should program value 3 (4-1) in this register. Note: The value programmed in this register must be lesser than the value programmed in PPS interval register (ETH_MACPPSIR). 0 32 read-write MACPOCR MACPOCR PTP Offload control register 0xBC0 0x20 0x00000000 0xFFFFFFFF PTOEN PTP Offload Enable When this bit is set, the PTP Offload feature is enabled. 0 1 read-write ASYNCEN Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Clock Master mode. 1 1 read-write APDREQEN Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Peer-to-Peer Transparent mode. 2 1 read-write ASYNCTRIG Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted. This bit is automatically cleared after the PTP SYNC message is transmitted. The application should set the ASYNCEN bit for this operation. 4 1 read-write APDREQTRIG Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted. This bit is automatically cleared after the PTP Pdelay_Req message is transmitted. The application should set the APDREQEN bit for this operation. 5 1 read-write DRRDIS Disable PTO Delay Request/Response response generation When this bit is set, the Delay Request and Delay response are not generated for received SYNC and Delay request packet respectively, as required by the programmed mode. 6 1 read-write DN Domain Number This field indicates the domain Number in which the PTP node is operating. 8 8 read-write MACSPI0R MACSPI0R PTP Source Port Identity 0 Register 0xBC4 0x20 0x00000000 0xFFFFFFFF SPI0 Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node. 0 32 read-write MACSPI1R MACSPI1R PTP Source port identity 1 register 0xBC8 0x20 0x00000000 0xFFFFFFFF SPI1 Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node. 0 32 read-write MACSPI2R MACSPI2R PTP Source port identity 2 register 0xBCC 0x20 0x00000000 0xFFFFFFFF SPI2 Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node. 0 16 read-write MACLMIR MACLMIR Log message interval register 0xBD0 0x20 0x00000000 0xFFFFFFFF LSI Log Sync Interval This field indicates the periodicity of the automatically generated SYNC message when the PTP node is Master. Allowed values are -15 to 15. Negative value must be represented in 2's-complement form. For example, if the required value is -1, the value programmed must be 0xFF. 0 8 read-write DRSYNCR Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted. Others: Reserved, must not be used The master sends this information (logMinDelayReqInterval) in the DelayResp PTP messages to the slave. The reception processes this value from the received DelayResp messages and updates this field accordingly. In the Slave mode, the host must not write/update this register unless it has to override the received value. In Master mode, the sum of this field and logSyncInterval (LSI) field is provided in the logMinDelayReqInterval field of the generated multicast Delay_Resp PTP message. 8 3 read-write LMPDRI Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. This is used to schedule the periodic Pdelay request packet transmission. Allowed values are -15 to 15.Negative value must be represented in 2's-complement form. For example, if the required value is -1, the value programmed must be 0xFF. 24 8 read-write MTLOMR MTLOMR Operating mode Register 0xC00 0x20 0x00000000 0xFFFFFFFF DTXSTS Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. When this bit is reset, the Tx packet status received from the MAC is forwarded to the application. 1 1 read-write CNTPRST Counters Preset When this bit is set: Tx queue underflow register (ETH_MTLTXQUR) is initialized/preset to 0x7F0. Missed Packet and Overflow Packet counters in Rx queue missed packet and overflow counter register (ETH_MTLRXQMPOCR) is initialized/preset to 0x7F0 This bit is cleared automatically. 8 1 read-write CNTCLR Counters Reset When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle. If this bit is set along with CNTPRST bit, CNTPRST has precedence. 9 1 read-write MTLISR MTLISR Interrupt status Register 0xC20 0x20 0x00000000 0xFFFFFFFF Q0IS Queue interrupt status This bit indicates that an interrupt has been generated by Queue. To reset this bit, read ETH_MTLQICSR register to identify the interrupt cause and clear the source. 0 1 read-only MTLTXQOMR MTLTXQOMR Tx queue operating mode Register 0xD00 0x20 0x00070008 0xFFFFFFFF FTQ Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. Therefore, all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, you should not write to the ETH_MTLTXQOMR register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission. Note: The flush operation is complete only when the Tx queue is empty and the application has accepted the pending Tx Status of all transmitted packets. To complete this flush operation, the PHY Tx clock (eth_mii_tx_clk) should be active. 0 1 read-write TSF Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set, the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when the transmission is stopped. 1 1 read-write TXQEN Transmit Queue Enable This field is used to enable/disable the transmit queue . Others: Reserved, must not be used. Note: In multiple Tx queues configuration, all the queues are disabled by default. Enable the Tx queue by programming this field. 2 2 read-only TTC Transmit Threshold Control These bits control the threshold level of the MTL Tx queue. The transmission starts when the packet size within the MTL Tx queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset. 4 3 read-write TQS Transmit queue size This field indicates the size of the allocated transmit queues in blocks of 256 bytes. Queue size range from 256 bytes (TQS=0b000) to 2048 bytes (TQS=0b111). 16 3 read-write MTLTXQUR MTLTXQUR Tx queue underflow register 0xD04 0x20 0x00000000 0xFFFFFFFF UFFRMCNT Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when this register is read. 0 11 read-write clear UFCNTOVF Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. In such a scenario, the overflow packet counter is reset to all-zeros and this bit indicates that the rollover happened. 11 1 read-write clear MTLTXQDR MTLTXQDR Tx queue debug Register 0xD08 0x20 0x00000000 0xFFFFFFFF TXQPAUSED Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx queue is in the Pause condition (in the Full-duplex only mode) because of the following: Reception of the PFC packet for the priorities assigned to the Tx queue when PFC is enabled Reception of 802.3x Pause packet when PFC is disabled 0 1 read-only TRCSTS MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 1 2 read-only TWCSTS MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx queue Write Controller is active, and it is transferring the data to the Tx queue. 3 1 read-only TXQSTS MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx queue is not empty and some data is left for transmission. 4 1 read-only TXSTSFSTS MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. Therefore, the MTL cannot accept any more packets for transmission. 5 1 read-only PTXQ Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx queue. When the DTXSTS bit of Operating mode Register (ETH_MTLOMR) register is set to 1, this field does not reflect the number of packets in the Transmit queue. 16 3 read-only STXSTSF Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of ETH_MTLOMR register is set to 1, this field does not reflect the number of status words in Tx Status FIFO. 20 3 read-only MTLQICSR MTLQICSR Queue interrupt control status Register 0xD2C 0x20 0x00000000 0xFFFFFFFF TXUNFIS Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes 1 to this bit. 0 1 read-write TXUIE Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. When this bit is reset, the Transmit Queue Underflow interrupt is disabled. 8 1 read-write RXOVFIS Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application, the overflow status is set in RDES3[21]. This bit is cleared when the application writes 1 to this bit. 16 1 read-write RXOIE Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. When this bit is reset, the Receive Queue Overflow interrupt is disabled. 24 1 read-write MTLRXQOMR MTLRXQOMR Rx queue operating mode register 0xD30 0x20 0x00700000 0xFFFFFFFF RTC Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition, full packets with length less than the threshold are automatically transferred. This field is valid only when the RSF bit is zero. This field is ignored when the RSF bit is set to 1. 0 2 read-write FUP Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. When this bit is reset, the Rx queue drops all packets of less than 64 bytes, unless a packet is already transferred because of the lower value of Rx Threshold, for example, RTC = 01. 3 1 read-write FEP Forward Error Packets When this bit is reset, the Rx queue drops packets with error status (CRC error, receive error, watchdog timeout, or overflow). However, if the start byte (write) pointer of a packet is already transferred to the read controller side (in Threshold mode), the packet is not dropped. When this bit is set, all packets except the runt error packets are forwarded to the application or DMA. If the RSF bit is set and the Rx queue overflows when a partial packet is written, the packet is dropped irrespective of the setting of this bit. However, if the RSF bit is reset and the Rx queue overflows when a partial packet is written, a partial packet may be forwarded to the application or DMA. 4 1 read-write RSF Receive Queue Store and Forward When this bit is set, the Ethernet peripheral reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. When this bit is reset, the Rx queue operates in the Threshold (cut-through) mode, subject to the threshold specified by the RTC field of this register. 5 1 read-write DIS_TCP_EF Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload. There are no errors (including FCS error) in the Ethernet packet received by the MAC. When this bit is reset, all error packets are dropped if the FEP bit is reset. 6 1 read-write RQS Receive Queue Size This field is read-only and the configured Rx FIFO size in blocks of 256 bytes is reflected in the reset value. The size of the Queue is (RQS + 1) * 256 bytes. 20 3 read-only MTLRXQMPOCR MTLRXQMPOCR Rx queue missed packet and overflow counter register 0xD34 0x20 0x00000000 0xFFFFFFFF OVFPKTCNT Overflow Packet Counter This field indicates the number of packets discarded by the Ethernet peripheral because of Receive queue overflow. This counter is incremented each time the Ethernet peripheral discards an incoming packet because of overflow. This counter is reset when this register is read. 0 11 read-write clear OVFCNTOVF Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. 11 1 read-write clear MISPKTCNT Missed Packet Counter This field indicates the number of packets missed by the Ethernet peripheral because the application requested to flush the packets for this queue. This counter is reset when this register is read. This counter is incremented by 1 when the DMA discards the packet because of buffer unavailability. 16 11 read-write clear MISCNTOVF Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. 27 1 read-write clear MTLRXQDR MTLRXQDR Rx queue debug register 0xD38 0x20 0x00000000 0xFFFFFFFF RWCSTS MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx queue. 0 1 read-only RRCSTS MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 1 2 read-only RXQSTS MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx queue: 4 2 read-only PRXQ Number of Packets in Receive Queue This field indicates the current number of packets in the Rx queue. The theoretical maximum value for this field is 256Kbyte/16bytes = 16K Packets, that is, Max_Queue_Size/Min_Packet_Size. 16 14 read-only DMAMR DMAMR DMA mode register 0x1000 0x20 0x00000000 0xFFFFFFFF SWR Software Reset When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all clock domains. Before reprogramming any register, a value of zero should be read in this bit. Note: The reset operation is complete only when all resets in all active clock domains are deasserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. 0 1 read-write DA DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels: The priority between the paths is according to the priority specified in Bits[14:12] and the priority weight is specified in the TXPR bit. The Tx path has priority over the Rx path when the TXPR bit is set. Otherwise, the Rx path has priority over the Tx path. 1 1 read-write TXPR Transmit priority When set, this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus. 11 1 read-write PR Priority ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when the DA bit is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether the TXPR bit is reset or set. 12 3 read-write INTM Interrupt Mode This field defines the interrupt mode of the Ethernet peripheral. The behavior of the interrupt signal and of the RI/TI bits in the ETH_DMACSR register changes depending on the INTM value (refer to Table 535: Transfer complete interrupt behavior). 16 2 read-write DMASBMR DMASBMR System bus mode register 0x1004 0x20 0x00000000 0xFFFFFFFF FB Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers of specified length (INCRx or SINGLE). When this bit is set to 0, the AHB master will initiate transfers of unspecified length (INCR) or SINGLE transfers. 0 1 read-write AAL Address-Aligned Beats When this bit is set to 1, the master performs address-aligned burst transfers on Read and Write channels. 12 1 read-write MB Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more. For burst length of 16 or less, the AHB master performs fixed burst transfers (INCRx and SINGLE). 14 1 read-only RB Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or Early Burst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. 15 1 read-only DMAISR DMAISR Interrupt status register 0x1008 0x20 0x00000000 0xFFFFFFFF DC0IS DMA Channel Interrupt Status This bit indicates an interrupt event in DMA Channel. To reset this bit to 0, the software must read the corresponding register in DMA Channel to get the exact cause of the interrupt and clear its source. 0 1 read-only MTLIS MTL Interrupt Status This bit indicates an interrupt event in the MTL. To reset this bit to 1'b0, the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source. 16 1 read-only MACIS MAC Interrupt Status This bit indicates an interrupt event in the MAC. To reset this bit to 1'b0, the software must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source. 17 1 read-only DMADSR DMADSR Debug status register 0x100C 0x20 0x00000000 0xFFFFFFFF AXWHSTS AHB Master Write Channel When high, this bit indicates that the write channel of the AHB master FMSs are in non-idle state. 0 1 read-only RPS0 DMA Channel Receive Process State This field indicates the Rx DMA FSM state for Channel: The MSB of this field always returns 0. This field does not generate an interrupt. 8 4 read-only TPS0 DMA Channel Transmit Process State This field indicates the Tx DMA FSM state for Channel: The MSB of this field always returns 0. This field does not generate an interrupt. 12 4 read-only DMACCR DMACCR Channel control register 0x1100 0x20 0x00000000 0xFFFFFFFF MSS Maximum Segment Size This field specifies the maximum segment size that should be used while segmenting the packet. This field is valid only if the TSE bit of Channel transmit control register (ETH_DMACTXCR) is set. The value programmed in this field must be more than the configured Data width in bytes. It is recommended to use a MSS value of 64 bytes or more. 0 14 read-write PBLX8 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in Channel transmit control register (ETH_DMACTXCR) is multiplied eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. 16 1 read-write DSL Descriptor Skip Length This bit specifies the 32-bit word number to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of the next descriptor. When the DSL value is equal to zero, the DMA takes the descriptor table as contiguous. 18 3 read-write DMACTXCR DMACTXCR Channel transmit control register 0x1104 0x20 0x00000000 0xFFFFFFFF ST Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the following positions: The current position in the list: this is the base address of the Transmit list set by the ETH_DMACTXDLAR register. The position at which the transmission was previously stopped If the DMA does not own the current descriptor, the transmission enters the Suspended state and the TBU bit of the ETH_DMACSR is set. The Start Transmission command is effective only when the transmission is stopped. If the command is issued before setting the ETH_DMACTXDLAR register, the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current packet. The Next Descriptor position in the Transmit list is saved, and it becomes the current position when the transmission is restarted. To change the list address, you need to program ETH_DMACTXDLAR register with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current packet is complete or the transmission is in the Suspended state. 0 1 read-write OSF Operate on Second Packet When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 4 1 read-write TSE TCP Segmentation Enabled When this bit is set, the DMA performs the TCP segmentation for packets in Channel i. The TCP segmentation is done only for those packets for which the TSE bit (TDES0[19]) is set in the Tx Normal descriptor. When this bit is set, the TxPBL value must be greater than or equal to 4. 12 1 read-write TXPBL Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps: Set the PBLx8 mode in ETH_DMACCR. Set the TXPBL[5:0]. Note: The maximum value of TXPBL must be less than or equal to half the Tx Queue size (TQS field of Tx queue operating mode Register (ETH_MTLTXQOMR)) in terms of beats. This is required so that the Tx Queue has space to store at least another Tx PBL worth of data while the MTL Tx Queue Controller is transferring data to MAC. The total locations in Tx Queue of size 2048 bytes is 512, TXPBL and 8xPBL needs to be programmed to less than or equal to 512/2. 16 6 read-write DMACRXCR DMACRXCR Channel receive control register 0x1108 0x20 0x00000000 0xFFFFFFFF SR Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: The current position in the list: this is the address set by the Channel Rx descriptor list address register (ETH_DMACRXDLAR). The position at which the Rx process was previously stopped If the DMA does not own the current descriptor, the reception is suspended and the RBU bit of the ETH_DMACSR is set. The Start Receive command is effective only when the reception is stopped. If the command is issued before setting the Channel Rx descriptor list address register (ETH_DMACRXDLAR), the DMA behavior is unpredictable. When this bit is reset, the Rx DMA operation is stopped after the transfer of the current packet. The next descriptor position in the Receive list is saved, and it becomes the current position after the Rx process is restarted. The Stop Receive command is effective only when the Rx process is in the Running (waiting for Rx packet) or Suspended state. 0 1 read-write RBSZ Receive Buffer size This field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16 Kbytes. Note: The buffer size must be a multiple of 4. This is required even if the value of buffer address pointer is not aligned to bus width. If the buffer size is not a multiple of 4, it may result into an undefined behavior. Note: The LSB bits (1:0) are ignored and the DMA internally takes the LSB bits as all-zero. Therefore, these LSB bits are read-only (RO). 1 14 read-write RXPBL Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps: Set the PBLx8 mode in the ETH_DMACCR. Set the RXPBL[5:0]. Note: The maximum value of RXPBL must be less than or equal to half the Rx Queue size (RQS field of Rx queue operating mode register (ETH_MTLRXQOMR)) in terms of beats. This is required so that the Rx Queue has space to store at least another Rx PBL worth of data while the MTL Rx Queue Controller is transferring data to MAC.The total locations in Rx Queue of size 2048 bytes is 512, RXPBL and 8xPBL needs to be programmed to less than or equal to 512/2. 16 6 read-write RPF DMA Rx Channel Packet Flush When this bit is set to 1, the Ethernet peripheral automatically flushes the packet from the Rx queues destined to DMA Rx Channel when the DMA Rx Channel is stopped after a system bus error has occurred. When this bit remains set and the DMA is re-started by the software driver, the packets residing in the Rx Queues that were received when this RxDMA was stopped, are flushed out. The packets that are received by the MAC after the RxDMA is re-started are routed to the RxDMA. The flushing happens on the Read side of the Rx queue. When this bit is set to 0 the Ethernet peripheral does not flush the packet in the Rx queue destined to DMA Rx Channel after the DMA is stopped due to a system bus error. This might cause head-of-line blocking in the corresponding RxQueue. Note: The stopping of packet flow from a Rx DMA Channel to the application by setting RPF works only when there is one-to-one mapping of Rx Queue to Rx DMA channels. In Dynamic mapping mode, setting RPF bit in ETH_DMACRXCR register might flush packets from unintended Rx Queues which are destined to the stopped Rx DMA Channel. 31 1 read-write DMACTXDLAR DMACTXDLAR Channel Tx descriptor list address register 0x1114 0x20 0x00000000 0xFFFFFFFF TDESLA Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0) for 32-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO). 0 32 read-write DMACRXDLAR DMACRXDLAR Channel Rx descriptor list address register 0x111C 0x20 0x00000000 0xFFFFFFFF RDESLA Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0) for 32-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO). 0 32 read-write DMACTXDTPR DMACTXDTPR Channel Tx descriptor tail pointer register 0x1120 0x20 0x00000000 0xFFFFFFFF TDT Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the descriptors between the head and the tail pointer registers. 0 32 read-write DMACRXDTPR DMACRXDTPR Channel Rx descriptor tail pointer register 0x1128 0x20 0x00000000 0xFFFFFFFF RDT Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors referenced between the head and the tail pointer registers. 0 32 read-write DMACTXRLR DMACTXRLR Channel Tx descriptor ring length register 0x112C 0x20 0x00000000 0xFFFFFFFF TDRL Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. It is recommended to put a minimum ring descriptor length of 4. For example, you can program any value up to 0x3FF in this field. This field is 10 bits wide, if you program 0x3FF, you can have 1024 descriptors. If you want to have 10 descriptors, program it to a value of 0x9. 0 10 read-write DMACRXRLR DMACRXRLR Channel Rx descriptor ring length register 0x1130 0x20 0x00000000 0xFFFFFFFF RDRL Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example, you can program any value up to 0x3FF in this field. This field is 10-bit wide. If you program 0x3FF, you can have 1024 descriptors. If you want to have 10 descriptors, program it to a value of 0x9. 0 10 read-write ARBS Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS[7:0] is programmed to a non-zero value. When ARBS[7:0] = 0, Rx Buffer1 and Rx Buffer2 sizes are based on RBSZ[13:0] field of Channel receive control register (ETH_DMACRXCR). 16 8 read-write DMACIER DMACIER Channel interrupt enable register 0x1134 0x20 0x00000000 0xFFFFFFFF TIE Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. 0 1 read-write TXSE Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. When this bit is reset, the Transmission Stopped interrupt is disabled. 1 1 read-write TBUE Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable interrupt is disabled. 2 1 read-write RIE Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. 6 1 read-write RBUE Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable interrupt is disabled. 7 1 read-write RSE Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped interrupt is disabled. 8 1 read-write RWTE Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout interrupt is disabled. 9 1 read-write ETIE Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. When this bit is reset, the Early Transmit interrupt is disabled. 10 1 read-write ERIE Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. When this bit is reset, the Early Receive interrupt is disabled. 11 1 read-write FBEE Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. When this bit is reset, the Fatal Bus Error error interrupt is disabled. 12 1 read-write CDEE Context Descriptor Error Enable When this bit is set along with the AIE bit, the Context Descriptor error interrupt is enabled. When this bit is reset, the Context Descriptor error interrupt is disabled. 13 1 read-write AIE Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. This bit enables the following interrupts in the Channel status register (ETH_DMACSR): Bit 1: Transmit Process Stopped Bit 7: Rx Buffer Unavailable Bit 8: Receive Process Stopped Bit 9: Receive Watchdog Timeout Bit 10: Early Transmit Interrupt Bit 12: Fatal Bus Error When this bit is reset, the abnormal interrupt summary is disabled. 14 1 read-write NIE Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. This bit enables the following interrupts in the Channel status register (ETH_DMACSR): Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt When this bit is reset, the normal interrupt summary is disabled. 15 1 read-write DMACRXIWTR DMACRXIWTR Channel Rx interrupt watchdog timer register 0x1138 0x20 0x00000000 0xFFFFFFFF RWT Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx DMA completes the transfer of a packet for which the RI bit is not set in the ETH_DMACSR, because of the setting of Interrupt Enable bit in the corresponding descriptor RDES3[30]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per the Interrupt Enable bit RDES3[30] of any received packet. 0 8 read-write RWTU Receive Interrupt Watchdog Timer Count Units This field indicates the number of system clock cycles corresponding to one unit in RWT[7:0] field. For example, when RWT[7:0] = 2 and RWTU[1:0] = 1, the watchdog timer is set for 2 * 512 = 1024 system clock cycles. 16 2 read-write DMACCATXDR DMACCATXDR Channel current application transmit descriptor register 0x1144 0x20 0x00000000 0xFFFFFFFF CURTDESAPTR Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset. 0 32 read-only DMACCARXDR DMACCARXDR Channel current application receive descriptor register 0x114C 0x20 0x00000000 0xFFFFFFFF CURRDESAPTR Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset. 0 32 read-only DMACCATXBR DMACCATXBR Channel current application transmit buffer register 0x1154 0x20 0x00000000 0xFFFFFFFF CURTBUFAPTR Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset. 0 32 read-only DMACCARXBR DMACCARXBR Channel current application receive buffer register 0x115C 0x20 0x00000000 0xFFFFFFFF CURRBUFAPTR Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset. 0 32 read-only DMACSR DMACSR Channel status register 0x1160 0x20 0x00000000 0xFFFFFFFF TI Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. 0 1 read-write TPS Transmit Process Stopped This bit is set when the transmission is stopped. 1 1 read-write TBU Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. The TPSi field of the Debug status register (ETH_DMADSR) register explains the Transmit Process state transitions. To resume processing the Transmit descriptors, the application should do the following: 1. Change the ownership of the descriptor by setting Bit 31 of TDES3. 2. Issue a Transmit Poll Demand command. For ring mode, the application should advance the Transmit Descriptor Tail Pointer register of a channel. 2 1 read-write RI Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES1 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. The reception remains in the Running state. 6 1 read-write RBU Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors, the application should change the ownership of the descriptor and issue a Receive Poll Demand command. If this command is not issued, the Rx process resumes when the next recognized incoming packet is received. In ring mode, the application should advance the Receive Descriptor Tail Pointer register of a channel. This bit is set only when the DMA owns the previous Rx descriptor. 7 1 read-write RPS Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. 8 1 read-write RWT Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. 9 1 read-write ETI Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO. 10 1 read-write ERI Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet.The RI bit of this register automatically clears this bit. 11 1 read-write FBE Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses. 12 1 read-write CDE Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow (intermediate descriptor) or all ones descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid. 13 1 read-write AIS Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the ETH_DMACIER register: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8: Receive Process Stopped Bit 10: Early Transmit Interrupt Bit 12: Fatal Bus Error Bit 13: Context Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. 14 1 read-write NIS Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the ETH_DMACIER register: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in ETH_DMACIER register) affect the Normal Interrupt Summary bit. This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared. 15 1 read-write TEB Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example, error response on the AHB interface. Bit[2]: Error during data transfer by Tx DMA when 1, no Error during data transfer by Tx DMA when 0 Bit[1]: Error during descriptor access when 1, Error during data buffer access when 0 Bit[0]: Error during read transfer when 1, Error during write transfer when 0 This field is valid only when the FBE bit is set. This field does not generate an interrupt. 16 3 read-only REB Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example, error response on the AHB interface. Bit [2]: Error during data transfer by Rx DMA when 1, no Error during data transfer by Rx DMA when 0. Bit[1]: Error during descriptor access when 1, Error during data buffer access when 0 Bit[0]: Error during read transfer when 1, Error during write transfer when 0 This field is valid only when the FBE bit is set. This field does not generate an interrupt. 19 3 read-only DMACMFCR DMACMFCR Channel missed frame count register 0x116C 0x20 0x00000000 0xFFFFFFFF MFC Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in Channel receive control register (ETH_DMACRXCR). The counter gets cleared when this register is read. 0 11 read-write clear MFCO Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. 15 1 read-write clear EXTI Extended interrupt and event controller EXTI 0x58000000 0x0 0x400 registers PVD_AVD PVD and AVD through the EXTI line 0 LOOKUP LOOKUP/Overstack 6 CACHE_ECC Error ECC cache 7 ECC_FPU ECC/FPU/ All flag from exec 9 FPU FPU safety Flag 10 EXTI0 EXTI Line 0 interrupt through the EXTI line 16 EXTI1 EXTI Line 1 interrupt through the EXTI line 17 EXTI2 EXTI Line 2 interrupt through the EXTI line 18 EXTI3 EXTI Line 3 interrupt through the EXTI line 19 EXTI4 EXTI Line 4 interrupt through the EXTI line 20 EXTI5 EXTI Line 5 interrupt through the EXTI line 21 EXTI6 EXTI Line 6 interrupt through the EXTI line 22 EXTI7 EXTI Line 7 interrupt through the EXTI line 23 EXTI8 EXTI Line 8 interrupt through the EXTI line 24 EXTI9 EXTI Line 9 interrupt through the EXTI line 25 EXTI10 EXTI Line 10 interrupt through the EXTI line 26 EXTI11 EXTI Line 11 interrupt through the EXTI line 27 EXTI12 EXTI Line 12 interrupt through the EXTI line 28 EXTI13 EXTI Line 13 interrupt through the EXTI line 29 EXTI14 EXTI Line 14 interrupt through the EXTI line 30 EXTI15 EXTI Line 15 interrupt through the EXTI line 31 WAKEUP_PIN Interrupt for 4 wakeup pins (1, 2, 3, 4)through EXTI line 132 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 0x00000000 0xFFFFFFFF TR0 Rising trigger event configuration bit of configurable event input x. 0 1 read-write TR1 Rising trigger event configuration bit of configurable event input x. 1 1 read-write TR2 Rising trigger event configuration bit of configurable event input x. 2 1 read-write TR3 Rising trigger event configuration bit of configurable event input x. 3 1 read-write TR4 Rising trigger event configuration bit of configurable event input x. 4 1 read-write TR5 Rising trigger event configuration bit of configurable event input x. 5 1 read-write TR6 Rising trigger event configuration bit of configurable event input x. 6 1 read-write TR7 Rising trigger event configuration bit of configurable event input x. 7 1 read-write TR8 Rising trigger event configuration bit of configurable event input x. 8 1 read-write TR9 Rising trigger event configuration bit of configurable event input x. 9 1 read-write TR10 Rising trigger event configuration bit of configurable event input x. 10 1 read-write TR11 Rising trigger event configuration bit of configurable event input x. 11 1 read-write TR12 Rising trigger event configuration bit of configurable event input x. 12 1 read-write TR13 Rising trigger event configuration bit of configurable event input x. 13 1 read-write TR14 Rising trigger event configuration bit of configurable event input x. 14 1 read-write TR15 Rising trigger event configuration bit of configurable event input x. 15 1 read-write TR16 Rising trigger event configuration bit of configurable event input x. 16 1 read-write TR17 Rising trigger event configuration bit of configurable event input x. 17 1 read-write TR18 Rising trigger event configuration bit of configurable event input x. 18 1 read-write TR19 Rising trigger event configuration bit of configurable event input x. 19 1 read-write TR20 Rising trigger event configuration bit of configurable event input x. 20 1 read-write TR21 Rising trigger event configuration bit of configurable event input x. 21 1 read-write FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 0x00000000 0xFFFFFFFF TR0 Falling trigger event configuration bit of configurable event input x. 0 1 read-write TR1 Falling trigger event configuration bit of configurable event input x. 1 1 read-write TR2 Falling trigger event configuration bit of configurable event input x. 2 1 read-write TR3 Falling trigger event configuration bit of configurable event input x. 3 1 read-write TR4 Falling trigger event configuration bit of configurable event input x. 4 1 read-write TR5 Falling trigger event configuration bit of configurable event input x. 5 1 read-write TR6 Falling trigger event configuration bit of configurable event input x. 6 1 read-write TR7 Falling trigger event configuration bit of configurable event input x. 7 1 read-write TR8 Falling trigger event configuration bit of configurable event input x. 8 1 read-write TR9 Falling trigger event configuration bit of configurable event input x. 9 1 read-write TR10 Falling trigger event configuration bit of configurable event input x. 10 1 read-write TR11 Falling trigger event configuration bit of configurable event input x. 11 1 read-write TR12 Falling trigger event configuration bit of configurable event input x. 12 1 read-write TR13 Falling trigger event configuration bit of configurable event input x. 13 1 read-write TR14 Falling trigger event configuration bit of configurable event input x. 14 1 read-write TR15 Falling trigger event configuration bit of configurable event input x. 15 1 read-write TR16 Falling trigger event configuration bit of configurable event input x. 16 1 read-write TR17 Falling trigger event configuration bit of configurable event input x. 17 1 read-write TR18 Falling trigger event configuration bit of configurable event input x. 18 1 read-write TR19 Falling trigger event configuration bit of configurable event input x. 19 1 read-write TR20 Falling trigger event configuration bit of configurable event input x. 20 1 read-write TR21 Falling trigger event configuration bit of configurable event input x. 21 1 read-write SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 0x00000000 0xFFFFFFFF SWIER0 Software interrupt on line x This bitfield alway returns 0 when read. 0 1 read-write SWIER1 Software interrupt on line x This bitfield alway returns 0 when read. 1 1 read-write SWIER2 Software interrupt on line x This bitfield alway returns 0 when read. 2 1 read-write SWIER3 Software interrupt on line x This bitfield alway returns 0 when read. 3 1 read-write SWIER4 Software interrupt on line x This bitfield alway returns 0 when read. 4 1 read-write SWIER5 Software interrupt on line x This bitfield alway returns 0 when read. 5 1 read-write SWIER6 Software interrupt on line x This bitfield alway returns 0 when read. 6 1 read-write SWIER7 Software interrupt on line x This bitfield alway returns 0 when read. 7 1 read-write SWIER8 Software interrupt on line x This bitfield alway returns 0 when read. 8 1 read-write SWIER9 Software interrupt on line x This bitfield alway returns 0 when read. 9 1 read-write SWIER10 Software interrupt on line x This bitfield alway returns 0 when read. 10 1 read-write SWIER11 Software interrupt on line x This bitfield alway returns 0 when read. 11 1 read-write SWIER12 Software interrupt on line x This bitfield alway returns 0 when read. 12 1 read-write SWIER13 Software interrupt on line x This bitfield alway returns 0 when read. 13 1 read-write SWIER14 Software interrupt on line x This bitfield alway returns 0 when read. 14 1 read-write SWIER15 Software interrupt on line x This bitfield alway returns 0 when read. 15 1 read-write SWIER16 Software interrupt on line x This bitfield alway returns 0 when read. 16 1 read-write SWIER17 Software interrupt on line x This bitfield alway returns 0 when read. 17 1 read-write SWIER18 Software interrupt on line x This bitfield alway returns 0 when read. 18 1 read-write SWIER19 Software interrupt on line x This bitfield alway returns 0 when read. 19 1 read-write SWIER20 Software interrupt on line x This bitfield alway returns 0 when read. 20 1 read-write SWIER21 Software interrupt on line x This bitfield alway returns 0 when read. 21 1 read-write RTSR2 RTSR2 EXTI rising trigger selection register 0xC 0x20 0x00000000 0xFFFFFFFF TR34 Rising trigger event configuration bit of configurable event input x+32.(1) 2 1 read-write TR46 Rising trigger event configuration bit of configurable event input x+32.(1) 14 1 read-write TR49 Rising trigger event configuration bit of configurable event input x+32.(1) 17 1 read-write TR51 Rising trigger event configuration bit of configurable event input x+32.(1) 19 1 read-write TR54 Rising trigger event configuration bit of configurable event input x+32. 22 1 read-write FTSR2 FTSR2 EXTI falling trigger selection register 0x10 0x20 0x00000000 0xFFFFFFFF TR34 Falling trigger event configuration bit of configurable event input x+32.(1) 2 1 read-write TR46 Falling trigger event configuration bit of configurable event input x+32.(1) 14 1 read-write TR49 Falling trigger event configuration bit of configurable event input x+32.(1) 17 1 read-write TR51 Falling trigger event configuration bit of configurable event input x+32.(1) 19 1 read-write TR54 Falling trigger event configuration bit of configurable event input x+32. 22 1 read-write SWIER2 SWIER2 EXTI software interrupt event register 0x14 0x20 0x00000000 0xFFFFFFFF SWIER34 Software interrupt on line x+32 Always returns 0 when read. 2 1 read-write SWIER46 Software interrupt on line x+32 Always returns 0 when read. 14 1 read-write SWIER49 Software interrupt on line x+32 Always returns 0 when read. 17 1 read-write SWIER51 Software interrupt on line x+32 Always returns 0 when read. 19 1 read-write SWIER54 Software interrupt on line x+32 Always returns 0 when read. 22 1 read-write IMR1 IMR1 EXTI interrupt mask register 0x18 0x20 0xFFC00000 0xFFFFFFFF MR0 CPU interrupt mask on configurable event input x 0 1 read-write MR1 CPU interrupt mask on configurable event input x 1 1 read-write MR2 CPU interrupt mask on configurable event input x 2 1 read-write MR3 CPU interrupt mask on configurable event input x 3 1 read-write MR4 CPU interrupt mask on configurable event input x 4 1 read-write MR5 CPU interrupt mask on configurable event input x 5 1 read-write MR6 CPU interrupt mask on configurable event input x 6 1 read-write MR7 CPU interrupt mask on configurable event input x 7 1 read-write MR8 CPU interrupt mask on configurable event input x 8 1 read-write MR9 CPU interrupt mask on configurable event input x 9 1 read-write MR10 CPU interrupt mask on configurable event input x 10 1 read-write MR11 CPU interrupt mask on configurable event input x 11 1 read-write MR12 CPU interrupt mask on configurable event input x 12 1 read-write MR13 CPU interrupt mask on configurable event input x 13 1 read-write MR14 CPU interrupt mask on configurable event input x 14 1 read-write MR15 CPU interrupt mask on configurable event input x 15 1 read-write MR16 CPU interrupt mask on configurable event input x 16 1 read-write MR17 CPU interrupt mask on configurable event input x 17 1 read-write MR18 CPU interrupt mask on configurable event input x 18 1 read-write MR19 CPU interrupt mask on configurable event input x 19 1 read-write MR20 CPU interrupt mask on configurable event input x 20 1 read-write MR21 CPU interrupt mask on configurable event input x 21 1 read-write MR22 CPU interrupt mask on direct event input x 22 1 read-write MR23 CPU interrupt mask on direct event input x 23 1 read-write MR24 CPU interrupt mask on direct event input x 24 1 read-write MR25 CPU interrupt mask on direct event input x 25 1 read-write MR26 CPU interrupt mask on direct event input x 26 1 read-write MR27 CPU interrupt mask on direct event input x 27 1 read-write MR28 CPU interrupt mask on direct event input x 28 1 read-write MR29 CPU interrupt mask on direct event input x 29 1 read-write MR30 CPU interrupt mask on direct event input x 30 1 read-write MR31 CPU interrupt mask on direct event input x 31 1 read-write EMR1 EMR1 EXTI event mask register 0x1C 0x20 0x00000000 0xFFFFFFFF MR0 CPU event mask on event input x 0 1 read-write MR1 CPU event mask on event input x 1 1 read-write MR2 CPU event mask on event input x 2 1 read-write MR3 CPU event mask on event input x 3 1 read-write MR4 CPU event mask on event input x 4 1 read-write MR5 CPU event mask on event input x 5 1 read-write MR6 CPU event mask on event input x 6 1 read-write MR7 CPU event mask on event input x 7 1 read-write MR8 CPU event mask on event input x 8 1 read-write MR9 CPU event mask on event input x 9 1 read-write MR10 CPU event mask on event input x 10 1 read-write MR11 CPU event mask on event input x 11 1 read-write MR12 CPU event mask on event input x 12 1 read-write MR13 CPU event mask on event input x 13 1 read-write MR14 CPU event mask on event input x 14 1 read-write MR15 CPU event mask on event input x 15 1 read-write MR16 CPU event mask on event input x 16 1 read-write MR17 CPU event mask on event input x 17 1 read-write MR18 CPU event mask on event input x 18 1 read-write MR19 CPU event mask on event input x 19 1 read-write MR20 CPU event mask on event input x 20 1 read-write MR21 CPU event mask on event input x 21 1 read-write MR22 CPU event mask on event input x 22 1 read-write MR23 CPU event mask on event input x 23 1 read-write MR24 CPU event mask on event input x 24 1 read-write MR25 CPU event mask on event input x 25 1 read-write MR26 CPU event mask on event input x 26 1 read-write MR27 CPU event mask on event input x 27 1 read-write MR28 CPU event mask on event input x 28 1 read-write MR29 CPU event mask on event input x 29 1 read-write MR30 CPU event mask on event input x 30 1 read-write MR31 CPU event mask on event input x 31 1 read-write PR1 PR1 EXTI pending register 0x20 0x20 0x00000000 0x00000000 PR0 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 0 1 read-write PR1 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 1 1 read-write PR2 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 2 1 read-write PR3 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 3 1 read-write PR4 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 4 1 read-write PR5 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 5 1 read-write PR6 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 6 1 read-write PR7 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 7 1 read-write PR8 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 8 1 read-write PR9 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 9 1 read-write PR10 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 10 1 read-write PR11 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 11 1 read-write PR12 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 12 1 read-write PR13 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 13 1 read-write PR14 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 14 1 read-write PR15 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 15 1 read-write PR16 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 16 1 read-write PR17 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 17 1 read-write PR18 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 18 1 read-write PR19 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 19 1 read-write PR20 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 20 1 read-write PR21 Configurable event inputs x Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 21 1 read-write IMR2 IMR2 EXTI interrupt mask register 0x24 0x20 0xFFF5FFFF 0xFFFFFFFF MR32 CPU interrupt mask on direct event input i 0 1 read-write MR33 CPU interrupt mask on direct event input i 1 1 read-write MR34 CPU interrupt mask on direct event input i 2 1 read-write MR35 CPU interrupt mask on direct event input i 3 1 read-write MR36 CPU interrupt mask on direct event input i 4 1 read-write MR37 CPU interrupt mask on direct event input i 5 1 read-write MR38 CPU interrupt mask on direct event input i 6 1 read-write MR39 CPU interrupt mask on direct event input i 7 1 read-write MR40 CPU interrupt mask on direct event input i 8 1 read-write MR41 CPU interrupt mask on direct event input i 9 1 read-write MR42 CPU interrupt mask on direct event input i 10 1 read-write MR43 CPU interrupt mask on direct event input i 11 1 read-write MR44 CPU interrupt mask on direct event input i 12 1 read-write MR45 CPU interrupt mask on direct event input i 13 1 read-write MR46 CPU interrupt mask on direct event input i 14 1 read-write MR47 CPU interrupt mask on direct event input i 15 1 read-write MR48 CPU interrupt mask on direct event input i 16 1 read-write MR49 CPU interrupt mask on direct event input i 17 1 read-write MR50 CPU interrupt mask on direct event input i 18 1 read-write MR51 CPU interrupt mask on direct event input i 19 1 read-write MR52 CPU interrupt mask on direct event input i 20 1 read-write MR53 CPU interrupt mask on direct event input i 21 1 read-write MR54 CPU interrupt mask on direct event input i 22 1 read-write MR55 CPU interrupt mask on direct event input i 23 1 read-write MR56 CPU interrupt mask on direct event input i 24 1 read-write MR57 CPU interrupt mask on direct event input i 25 1 read-write MR58 CPU interrupt mask on direct event input i 26 1 read-write MR59 CPU interrupt mask on direct event input i 27 1 read-write EMR2 EMR2 EXTI event mask register 0x28 0x20 0x00000000 0xFFFFFFFF MR32 CPU event mask on event input i 0 1 read-write MR33 CPU event mask on event input i 1 1 read-write MR34 CPU event mask on event input i 2 1 read-write MR35 CPU event mask on event input i 3 1 read-write MR36 CPU event mask on event input i 4 1 read-write MR37 CPU event mask on event input i 5 1 read-write MR38 CPU event mask on event input i 6 1 read-write MR39 CPU event mask on event input i 7 1 read-write MR40 CPU event mask on event input i 8 1 read-write MR41 CPU event mask on event input i 9 1 read-write MR42 CPU event mask on event input i 10 1 read-write MR43 CPU event mask on event input i 11 1 read-write MR44 CPU event mask on event input i 12 1 read-write MR45 CPU event mask on event input i 13 1 read-write MR46 CPU event mask on event input i 14 1 read-write MR47 CPU event mask on event input i 15 1 read-write MR48 CPU event mask on event input i 16 1 read-write MR49 CPU event mask on event input i 17 1 read-write MR50 CPU event mask on event input i 18 1 read-write MR51 CPU event mask on event input i 19 1 read-write MR52 CPU event mask on event input i 20 1 read-write MR53 CPU event mask on event input i 21 1 read-write MR54 CPU event mask on event input i 22 1 read-write MR55 CPU event mask on event input i 23 1 read-write MR56 CPU event mask on event input i 24 1 read-write MR57 CPU event mask on event input i 25 1 read-write MR58 CPU event mask on event input i 26 1 read-write MR59 CPU event mask on event input i 27 1 read-write PR2 PR2 EXTI pending register 0x2C 0x20 0x00000000 0x00000000 PR34 Configurable event inputs x+32 Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 2 1 read-write PR46 Configurable event inputs x+32 Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 14 1 read-write PR49 Configurable event inputs x+32 Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 17 1 read-write PR51 Configurable event inputs x+32 Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 19 1 read-write PR54 Configurable event inputs x+32 Pending bit This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 22 1 read-write IMR3 IMR3 EXTI interrupt mask register 0x30 0x20 0x0F8BFFFF 0xFFFFFFFF MR77 CPU interrupt mask on direct event input x+64 13 1 read-write EMR3 EMR3 EXTI event mask register 0x34 0x20 0x00000000 0xFFFFFFFF MR77 CPU event mask on event input x+64 13 1 read-write FDCAN1 FDCAN 0x4000A000 0x0 0x400 registers FDCAN1_IT0 FDCAN1 Interrupt 0 152 FDCAN1_IT1 FDCAN1 Interrupt 1 153 CREL CREL FDCAN Core Release Register 0x0 0x20 0x32141218 0xFFFFFFFF DAY 18 0 8 read-only MON 12 8 8 read-only YEAR 4 16 4 read-only SUBSTEP 1 20 4 read-only STEP 2 24 4 read-only REL 3 28 4 read-only ENDN ENDN FDCAN Core Release Register 0x4 0x20 0x87654321 0xFFFFFFFF ETV Endianness test value The endianness test value is 0x8765 4321. 0 32 read-only DBTP DBTP FDCAN data bit timing and prescaler register 0xC 0x20 0x00000A33 0xFFFFFFFF DSJW Synchronization jump width Must always be smaller than DTSEG2, valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1: tSJW = (DSJW + 1) x tq. 0 4 read-write DTSEG2 Data time segment after sample point Valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS2 = (DTSEG2 + 1) x tq. 4 4 read-write DTSEG1 Data time segment before sample point Valid values are 0 to 31. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS1 = (DTSEG1 + 1) x tq. 8 5 read-write DBRP Data bit rate prescaler The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1. 16 5 read-write TDC Transceiver delay compensation 23 1 read-write TEST TEST FDCAN test register 0x10 0x20 0x00000000 0xFFFFFFFF LBCK Loop back mode 4 1 read-write TX Control of transmit pin 5 2 read-write RX Receive pin Monitors the actual value of pin FDCANx_RX 7 1 read-only RWD RWD FDCAN RAM watchdog register 0x14 0x20 0x00000000 0xFFFFFFFF WDC Watchdog configuration Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of FDCAN_CCCR register are set to 1. 0 8 read-write WDV Watchdog value Actual message RAM watchdog counter value. 8 8 read-only CCCR CCCR FDCAN CC control register 0x18 0x20 0x00000001 0xFFFFFFFF INIT Initialization 0 1 read-write CCE Configuration change enable 1 1 read-write ASM ASM restricted operation mode The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted operation Mode after it has received a valid frame. In the optional Restricted operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time. 2 1 read-write CSA Clock stop acknowledge 3 1 read-only CSR Clock stop request 4 1 read-write MON Bus monitoring mode Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time. 5 1 read-write DAR Disable automatic retransmission 6 1 read-write TEST Test mode enable 7 1 read-write FDOE FD operation enable 8 1 read-write BRSE FDCAN bit rate switching 9 1 read-write PXHD Protocol exception handling disable 12 1 read-write EFBI Edge filtering during bus integration 13 1 read-write TXP If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. 14 1 read-write NISO Non ISO operation If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 15 1 read-write NBTP NBTP FDCAN nominal bit timing and prescaler register 0x1C 0x20 0x06000A03 0xFFFFFFFF NTSEG2 Nominal time segment after sample point Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. 0 7 read-write NTSEG1 Nominal time segment before sample point Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 8 8 read-write NBRP Bit rate prescaler Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 16 9 read-write NSJW Nominal (re)synchronization jump width Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 25 7 read-write TSCC TSCC FDCAN Timestamp Counter Configuration Register 0x20 0x20 0x00000000 0xFFFFFFFF TSS Timestamp select These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 2 read-write TCP Timestamp counter prescaler 16 4 read-write TSCV TSCV FDCAN Timestamp Counter Value Register 0x24 0x20 0x00000000 0xFFFFFFFF TSC Timestamp counter The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC[TSS] = 01, the timestamp counter is incremented in multiples of CAN bit times [1..16] depending on the configuration of TSCC[TCP]. A wrap around sets interrupt flag IR[TSW]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact. 0 16 read-write TOCC TOCC FDCAN timeout counter configuration register 0x28 0x20 0xFFFF0000 0xFFFFFFFF ETOC Timeout counter enable This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 1 read-write TOS Timeout select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 1 2 read-write TOP Timeout period Start value of the timeout counter (down-counter). Configures the timeout period. 16 16 read-write TOCV TOCV FDCAN Timeout Counter Value Register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF TOC Timeout counter The timeout counter is decremented in multiples of CAN bit times [1..16] depending on the configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the timeout counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. 0 16 read-write ECR ECR FDCAN Error Counter Register 0x40 0x20 0x00000000 0xFFFFFFFF TEC Transmit error counter Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 0 8 read-only REC Receive error counter Actual state of the receive error counter, values between 0 and 127. 8 7 read-only RP Receive error passive 15 1 read-only CEL CAN error logging The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read. 16 8 read-write PSR PSR FDCAN Protocol Status Register 0x44 0x20 0x00000707 0xFFFFFFFF LEC Last error code The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. Access type is RS: set on read. 0 3 read-write ACT Activity Monitors the modules CAN communication state. 3 2 read-only EP Error passive 5 1 read-only EW Warning Sstatus 6 1 read-only BO Bus_Off status 7 1 read-only DLEC Data last error code Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read. 8 3 read-write RESI ESI flag of last received FDCAN message This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read. 11 1 read-write RBRS BRS flag of last received FDCAN message This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read. 12 1 read-write REDL Received FDCAN message This bit is set independent of acceptance filtering. Access type is RX: reset on read. 13 1 read-write PXE Protocol exception event 14 1 read-write TDCV Transmitter delay compensation value Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. 16 7 read-only TDCR TDCR FDCAN Transmitter Delay Compensation Register 0x48 0x20 0x00000000 0xFFFFFFFF TDCF Transmitter delay compensation filter window length Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 7 read-write TDCO Transmitter delay compensation offset Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 8 7 read-write IR IR FDCAN interrupt register 0x50 0x20 0x00000000 0xFFFFFFFF RF0N Rx FIFO 0 new message 0 1 read-write RF0F Rx FIFO 0 full 1 1 read-write RF0L Rx FIFO 0 message lost 2 1 read-write RF1N Rx FIFO 1 new message 3 1 read-write RF1F Rx FIFO 1 full 4 1 read-write RF1L Rx FIFO 1 message lost 5 1 read-write HPM High-priority message 6 1 read-write TC Transmission completed 7 1 read-write TCF Transmission cancellation finished 8 1 read-write TFE Tx FIFO empty 9 1 read-write TEFN Tx event FIFO New Entry 10 1 read-write TEFF Tx event FIFO full 11 1 read-write TEFL Tx event FIFO element lost 12 1 read-write TSW Timestamp wraparound 13 1 read-write MRAF Message RAM access failure The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted operation Mode (see Restricted operation mode). To leave Restricted operation Mode, the Host CPU has to reset CCCR.ASM. 14 1 read-write TOO Timeout occurred 15 1 read-write ELO Error logging overflow 16 1 read-write EP Error passive 17 1 read-write EW Warning status 18 1 read-write BO Bus_Off status 19 1 read-write WDI Watchdog interrupt 20 1 read-write PEA Protocol error in arbitration phase (nominal bit time is used) 21 1 read-write PED Protocol error in data phase (data bit time is used) 22 1 read-write ARA Access to reserved address 23 1 read-write IE IE FDCAN interrupt enable register 0x54 0x20 0x00000000 0xFFFFFFFF RF0NE Rx FIFO 0 new message interrupt enable 0 1 read-write RF0FE Rx FIFO 0 full interrupt enable 1 1 read-write RF0LE Rx FIFO 0 message lost interrupt enable 2 1 read-write RF1NE Rx FIFO 1 new message interrupt enable 3 1 read-write RF1FE Rx FIFO 1 full interrupt enable 4 1 read-write RF1LE Rx FIFO 1 message lost interrupt enable 5 1 read-write HPME High-priority message interrupt enable 6 1 read-write TCE Transmission completed interrupt enable 7 1 read-write TCFE Transmission cancellation finished interrupt enable 8 1 read-write TFEE Tx FIFO empty interrupt enable 9 1 read-write TEFNE Tx event FIFO new entry interrupt enable 10 1 read-write TEFFE Tx event FIFO full interrupt enable 11 1 read-write TEFLE Tx event FIFO element lost interrupt enable 12 1 read-write TSWE Timestamp wraparound interrupt enable 13 1 read-write MRAFE Message RAM access failure interrupt enable 14 1 read-write TOOE Timeout occurred interrupt enable 15 1 read-write ELOE Error logging overflow interrupt enable 16 1 read-write EPE Error passive interrupt enable 17 1 read-write EWE Warning status interrupt enable 18 1 read-write BOE Bus_Off status 19 1 read-write WDIE Watchdog interrupt enable 20 1 read-write PEAE Protocol error in arbitration phase enable 21 1 read-write PEDE Protocol error in data phase enable 22 1 read-write ARAE Access to reserved address enable 23 1 read-write ILS ILS FDCAN interrupt line select register 0x58 0x20 0x00000000 0xFFFFFFFF RXFIFO0 RX FIFO bit grouping the following interruption RF0LL: Rx FIFO 0 message lost interrupt line RF0FL: Rx FIFO 0 full interrupt line RF0NL: Rx FIFO 0 new message interrupt line 0 1 read-write RXFIFO1 RX FIFO bit grouping the following interruption RF1LL: Rx FIFO 1 message lost interrupt line RF1FL: Rx FIFO 1 full interrupt line RF1NL: Rx FIFO 1 new message interrupt line 1 1 read-write SMSG Status message bit grouping the following interruption TCFL: Transmission cancellation finished interrupt line TCL: Transmission completed interrupt line HPML: High-priority message interrupt line 2 1 read-write TFERR Tx FIFO ERROR grouping the following interruption TEFLL: Tx event FIFO element lost interrupt line TEFFL: Tx event FIFO full interrupt line TEFNL: Tx event FIFO new entry interrupt line TFEL: Tx FIFO empty interrupt line 3 1 read-write MISC Interrupt regrouping the following interruption TOOL: Timeout occurred interrupt line MRAFL: Message RAM access failure interrupt line TSWL: Timestamp wraparound interrupt line 4 1 read-write BERR Bit and line error grouping the following interruption EPL Error passive interrupt line ELOL: Error logging overflow interrupt line 5 1 read-write PERR Protocol error grouping the following interruption ARAL: Access to reserved address line PEDL: Protocol error in data phase line PEAL: Protocol error in arbitration phase line WDIL: Watchdog interrupt line BOL: Bus_Off status EWL: Warning status interrupt line 6 1 read-write ILE ILE FDCAN interrupt line enable register 0x5C 0x20 0x00000000 0xFFFFFFFF EINT0 Enable interrupt line 0 0 1 read-write EINT1 Enable interrupt line 1 1 1 read-write RXGFC RXGFC FDCAN global filter configuration register 0x80 0x20 0x00000000 0xFFFFFFFF RRFE Reject remote frames extended These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 1 read-write RRFS Reject remote frames standard These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 1 1 read-write ANFE Accept non-matching frames extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 2 2 read-write ANFS Accept Non-matching frames standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 4 2 read-write F1OM FIFO 1 operation mode (overwrite or blocking) This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 8 1 read-write F0OM FIFO 0 operation mode (overwrite or blocking) This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 9 1 read-write LSS List size standard 1 to 28: Number of standard message ID filter elements >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 16 5 read-write LSE List size extended 1 to 8: Number of extended message ID filter elements >8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 24 4 read-write XIDAM XIDAM FDCAN Extended ID and Mask Register 0x84 0x20 0x1FFFFFFF 0xFFFFFFFF EIDM Extended ID mask For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 29 read-write HPMS HPMS FDCAN high-priority message status register 0x88 0x20 0x00000000 0xFFFFFFFF BIDX Buffer index Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1. 0 3 read-only MSI Message storage indicator 6 2 read-only FIDX Filter index Index of matching filter element. Range is 0 to RXGFC[LSS] - 1 or RXGFC[LSE] - 1. 8 5 read-only FLST Filter list Indicates the filter list of the matching filter element. 15 1 read-only RXF0S RXF0S FDCAN Rx FIFO 0 Status Register 0x90 0x20 0x00000000 0xFFFFFFFF F0FL Rx FIFO 0 fill level Number of elements stored in Rx FIFO 0, range 0 to 3. 0 4 read-only F0GI Rx FIFO 0 get index Rx FIFO 0 read index pointer, range 0 to 2. 8 2 read-only F0PI Rx FIFO 0 put index Rx FIFO 0 write index pointer, range 0 to 2. 16 2 read-only F0F Rx FIFO 0 full 24 1 read-only RF0L Rx FIFO 0 message lost This bit is a copy of interrupt flag IR[RF0L]. When IR[RF0L] is reset, this bit is also reset. 25 1 read-only RXF0A RXF0A CAN Rx FIFO 0 Acknowledge Register 0x94 0x20 0x00000000 0xFFFFFFFF F0AI Rx FIFO 0 acknowledge index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This sets the Rx FIFO 0 get index RXF0S[F0GI] to F0AI + 1 and update the FIFO 0 fill level RXF0S[F0FL]. 0 3 read-write RXF1S RXF1S FDCAN Rx FIFO 1 Status Register 0x98 0x20 0x00000000 0xFFFFFFFF F1FL Rx FIFO 1 fill level Number of elements stored in Rx FIFO 1, range 0 to 3. 0 4 read-only F1GI Rx FIFO 1 get index Rx FIFO 1 read index pointer, range 0 to 2. 8 2 read-only F1PI Rx FIFO 1 put index Rx FIFO 1 write index pointer, range 0 to 2. 16 2 read-only F1F Rx FIFO 1 full 24 1 read-only RF1L Rx FIFO 1 message lost This bit is a copy of interrupt flag IR[RF1L]. When IR[RF1L] is reset, this bit is also reset. 25 1 read-only RXF1A RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0x9C 0x20 0x00000000 0xFFFFFFFF F1AI Rx FIFO 1 acknowledge index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This sets the Rx FIFO 1 get index RXF1S[F1GI] to F1AI + 1 and update the FIFO 1 Fill Level RXF1S[F1FL]. 0 3 read-write TXBC TXBC FDCAN Tx Buffer Configuration Register 0xC0 0x20 0x00000000 0xFFFFFFFF TFQM Tx FIFO/queue mode This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 24 1 read-write TXFQS TXFQS FDCAN Tx FIFO/queue status register 0xC4 0x20 0x00000003 0xFFFFFFFF TFFL Tx FIFO free level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC[TFQM] = 1). 0 3 read-only TFGI Tx FIFO get index Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC.TFQM = 1) 8 2 read-only TFQPI Tx FIFO/queue put index Tx FIFO/queue write index pointer, range 0 to 3 16 2 read-only TFQF Tx FIFO/queue full 21 1 read-only TXBRP TXBRP FDCAN Tx Buffer Request Pending Register 0xC8 0x20 0x00000000 0xFFFFFFFF TRP Transmission request pending Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0 3 read-only TXBAR TXBAR FDCAN Tx Buffer Add Request Register 0xCC 0x20 0x00000000 0xFFFFFFFF AR Add request Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0 3 read-write TXBCR TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD0 0x20 0x00000000 0xFFFFFFFF CR Cancellation request Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset. 0 3 read-write TXBTO TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD4 0x20 0x00000000 0xFFFFFFFF TO Transmission occurred. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR. 0 3 read-only TXBCF TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xD8 0x20 0x00000000 0xFFFFFFFF CF Cancellation finished Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR. 0 3 read-only TXBTIE TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xDC 0x20 0x00000000 0xFFFFFFFF TIE Transmission interrupt enable Each Tx buffer has its own TIE bit. 0 3 read-write TXBCIE TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE0 0x20 0x00000000 0xFFFFFFFF CFIE Cancellation finished interrupt enable. Each Tx buffer has its own CFIE bit. 0 3 read-write TXEFS TXEFS FDCAN Tx Event FIFO Status Register 0xE4 0x20 0x00000000 0xFFFFFFFF EFFL Event FIFO fill level Number of elements stored in Tx event FIFO, range 0 to 3. 0 3 read-only EFGI Event FIFO get index Tx event FIFO read index pointer, range 0 to 3. 8 2 read-only EFPI Event FIFO put index Tx event FIFO write index pointer, range 0 to 3. 16 2 read-only EFF Event FIFO full 24 1 read-only TEFL Tx event FIFO element lost This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset. 0 No Tx event FIFO element lost 1 Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0. 25 1 read-only TXEFA TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xE8 0x20 0x00000000 0xFFFFFFFF EFAI Event FIFO acknowledge index After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS[EFGI] to EFAI + 1 and updates the FIFO 0 fill level TXEFS[EFFL]. 0 2 read-write CKDIV CKDIV FDCAN CFG clock divider Register 0x100 0x20 0x00000000 0xFFFFFFFF PDIV input clock divider The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 4 read-write FDCAN2 0x4000A400 FDCAN2_IT0 FDCAN2 Interrupt 0 154 FDCAN2_IT1 FDCAN2 Interrupt 1 155 FLASH Embedded Flash memory FLASH 0x52002000 0x0 0x1000 registers FLASH Flash memory 8 ACR ACR Access control register 0x0 0x20 0x00000013 0xFFFFFFFF LATENCY Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. Please refer to Table 27 for details. ... Note: Embedded Flash does not verify that the configuration is correct. 0 4 read-write WRHIGHFREQ Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to Table 27 for details. Note: Embedded Flash does not verify that the configuration is correct. 4 2 read-write KEYR KEYR FLASH control key register 0x4 0x20 0x00000000 0xFFFFFFFF CUKEY Control unlock key Following values must be written to FLASH_KEYR consecutively to unlock FLASH_CR register: 1st key = 0x4567 0123 2nd key = 0xCDEF 89AB Reads to this register returns zero. If above sequence is wrong or performed twice, the FLASH_CR register is locked until the next system reset, and access to it generates a bus error. 0 32 write-only CR CR FLASH control register 0x10 0x20 0x00000001 0xFFFFFFFF LOCK Configuration lock bit When this bit is set write to all other bits in this register, and to FLASH_IER register, are ignored. Clearing this bit requires the correct write sequence to FLASH_KEYR register (see this register for details). If a wrong sequence is executed, or if the unlock sequence is performed twice, this bit remains locked until the next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register. 0 1 read-write PG Internal buffer control bit Setting this bit enables internal buffer for write operations. This allows preparing program operations even if a sector or bank erase is ongoing. When PG is cleared, the internal buffer is disabled for write operations, and all the data stored in the buffer but not sent to the operation queue are lost. 1 1 read-write SER Sector erase request Setting this bit requests a sector erase. Write protection error is triggered when a sector erase is required on at least one protected sector. BER has a higher priority than SER: if both bits are set, the embedded Flash memory executes a bank erase. 2 1 read-write BER Bank erase request Setting this bit requests a bank erase operation (user Flash memory only). Write protection error is triggered when a bank erase is required and some sectors are protected. BER has a higher priority than SER: if both are set, the embedded Flash memory executes a bank erase. 3 1 read-write FW Force write This bit forces a write operation even if the write buffer is not full. In this case all bits not written are set by hardware. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it will lead to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively). 4 1 read-write START Erase start control bit This bit is used to start a sector erase or a bank erase operation. The embedded Flash memory resets START when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged. 5 1 read-write SSN Sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). ... 6 2 read-write PG_OTP Program Enable for OTP Area Set this bit to enable write operations to OTP area. 16 1 read-write CRC_EN CRC enable Setting this bit enables the CRC calculation. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR register. When CRC calculation is performed it can be disabled by clearing CRC_EN bit. Doing so sets CRCDATA to 0x0, clears CRC configuration and resets the content of FLASH_CRCDATAR register. 17 1 read-write ALL_BANKS All banks select bit When this bit is set the erase is done on all Flash Memory sectors. ALL_BANKS is used only if a bank erase is required (BER=1). In all others operations, this control bit is ignored. 24 1 read-write SR SR FLASH status register 0x14 0x20 0x00000000 0xFFFFFFFF BUSY Busy flag This bit is set when an effective write, erase or option byte change operation is ongoing. It is possible to know what type of operation is being executed reading the flags IS_PROGRAM, IS_ERASE and IS_OPTCHANGE. BUSY cannot be cleared by application. It is automatically reset by hardware every time a step in a write, erase or option byte change operation completes. It is not recommended to do software polling on BUSY to know when one operation completed because, depending of operation, more pulses are possible for one only operation. For software polling it is therefore better to use QW flag or to check the EOPF flag. 0 1 read-only WBNE Write buffer not empty flag This bit is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_CR the embedded Flash memory detects an error that involves data loss the application software has disabled write operations This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. 1 1 read-only QW Wait queue flag This bit is set when a write, erase or option byte change operation is pending in the command queue buffer. It is not possible to know what type of programming operation is present in the queue. This flag is reset by hardware when all write, erase or option byte change operations have been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if no other operations are requested. 2 1 read-only CRC_BUSY CRC busy flag This bit is set when a CRC calculation is ongoing. This bit cannot be forced to 0. The user must wait until the CRC calculation has completed or disable CRC computation using CRC_EN bit in FLASH_CR register. 3 1 read-only IS_PROGRAM Is a program This bit is set together with BUSY when a program operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_OPTCHANGE, because an program operation can happen during an option change. 4 1 read-only IS_ERASE Is an erase This bit is set together with BUSY when an erase operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_OPTCHANGE, because an erase operation can happen during an option change. 5 1 read-only IS_OPTCHANGE Is an option change This bit is set together with BUSY when an option change operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_PROGRAM or IS_ERASE, because a program or erase step is ongoing during option change. 6 1 read-only RCHECKF Root code check flag This bit returns the status of the root code check performed following the first access to the Flash. This bit is cleared with RCHECKF bit in FLASH_FCR (optional). 25 1 read-only FCR FCR FLASH status register 0x18 0x20 0x00000000 0xFFFFFFFF RCHECKF Root code check flag clear Set this bit to clear RCHECKF bit in FLASH_SR. 25 1 write-only IER IER FLASH interrupt enable register 0x20 0x20 0x00000000 0xFFFFFFFF EOPIE End-of-program interrupt control bit 16 1 read-write WRPERRIE Write protection error interrupt enable bit 17 1 read-write PGSERRIE Programming sequence error interrupt enable bit 18 1 read-write STRBERRIE Strobe error interrupt enable bit 19 1 read-write OBLERRIE Option byte loading error interrupt enable bit 20 1 read-write INCERRIE Inconsistency error interrupt enable bit 21 1 read-write RDSERRIE Read security error interrupt enable bit 24 1 read-write SNECCERRIE ECC single correction error interrupt enable bit 25 1 read-write DBECCERRIE ECC double detection error interrupt enable bit 26 1 read-write CRCENDIE CRC end of calculation interrupt enable bit 27 1 read-write CRCRDERRIE CRC read error interrupt enable bit 28 1 read-write ISR ISR FLASH interrupt status register 0x24 0x20 0x00000000 0xFFFFFFFF EOPF End-of-program flag This bit is set when a programming operation completes. An interrupt is generated if the EOPIE is set. It is not necessary to reset EOPF before starting a new operation. Setting EOPF bit in FLASH_ICR register clears this bit. 16 1 read-only WRPERRF Write protection error flag This bit is set when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set. Setting WRPERRF bit in FLASH_ICR register clears this bit. 17 1 read-only PGSERRF Programming sequence error flag This bit is set when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set. Setting PGSERRF bit in FLASH_ICR register clears this bit. 18 1 read-only STRBERRF Strobe error flag This bit is set when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set. Setting STRBERRF bit in FLASH_ICR register clears this bit. 19 1 read-only OBLERRF Option byte loading error flag This bit is set when an error is found during the option byte loading sequence. An interrupt is generated if OBLERRIE is set. Setting OBLERRF bit in the FLASH_ICR register clears this bit. 20 1 read-only INCERRF Inconsistency error flag This bit is set when a inconsistency error occurs. An interrupt is generated if INCERRIE is set. Setting INCERRF bit in the FLASH_ICR register clears this bit. 21 1 read-only RDSERRF Read security error flag This bit is set when a read security error occurs (read access to hide protected area with incorrect hide protection level). An interrupt is generated if RDSERRIE is set. Setting RDSERRF bit in FLASH_ICR register clears this bit. 24 1 read-only SNECCERRF ECC single error flag This bit is set when an ECC single correction error occurs during a read operation. An interrupt is generated if SNECCERRIE is set. Setting SNECCERRF bit in FLASH_ICR register clears this bit. 25 1 read-only DBECCERRF ECC double error flag This bit is set when an ECC double detection error occurs during a read operation. An interrupt is generated if DBECCERRIE is set. Setting DBECCERRF bit in FLASH_ICR register clears this bit. 26 1 read-only CRCENDF CRC end flag This bit is set when the CRC computation has completed. An interrupt is generated if CRCENDIE is set. It is not necessary to reset CRCEND before restarting CRC computation. Setting CRCENDF bit in FLASH_ICR register clears this bit. 27 1 read-only CRCRDERRF CRC read error flag This bit is set when a word is found read protected during a CRC operation. An interrupt is generated if CRCRDIE is set. Setting CRCRDERRF bit in FLASH_ICR register clears this bit. This flag is valid only when CRCEND bit is set. 28 1 read-only ICR ICR FLASH interrupt clear register 0x28 0x20 0x00000000 0xFFFFFFFF EOPF End-of-program flag clear Setting this bit clears EOPF flag in FLASH_ISR register. 16 1 write-only WRPERRF Write protection error flag clear Setting this bit clears WRPERRF flag in FLASH_ISR register. 17 1 write-only PGSERRF Programming sequence error flag clear Setting this bit clears PGSERRF flag in FLASH_ISR register. 18 1 write-only STRBERRF Strobe error flag clear Setting this bit clears STRBERRF flag in FLASH_ISR register. 19 1 write-only OBLERRF Option byte loading error flag clear Setting this bit clears OBLERRF flag in FLASH_ISR register. 20 1 write-only INCERRF Inconsistency error flag clear Setting this bit clears INCERRF flag in FLASH_ISR register. 21 1 write-only RDSERRF Read security error flag clear Setting this bit clears RDSERRF flag in FLASH_ISR register. 24 1 write-only SNECCERRF ECC single error flag clear Setting this bit clears SNECCERRF flag in FLASH_ISR register. If the DBECCERRF flag of FLASH_ISR register is also cleared, FLASH_ECCFAR register is reset to zero as well. 25 1 write-only DBECCERRF ECC double error flag clear Setting this bit clears DBECCERRF flag in FLASH_ISR register. If the SNECCERRF flag of FLASH_ISR register is also cleared, FLASH_ECCFAR register is reset to zero as well. 26 1 write-only CRCENDF CRC end flag clear Setting this bit clears CRCENDF flag in FLASH_ISR register. 27 1 write-only CRCRDERRF CRC error flag clear Setting this bit clears CRCRDERRF flag in FLASH_ISR register. 28 1 write-only CRCCR CRCCR FLASH CRC control register 0x30 0x20 0x001C0000 0xFFFFFFFF CRC_SECT CRC sector number CRC_SECT is used to select one user Flash sectors to be added to the list of sectors on which the CRC is calculated. The CRC can be computed either between two addresses (using registers FLASH_CRCSADDR and FLASH_CRCEADDR) or on a list of sectors using this register. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting ADD_SECT bit. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. ... 0 2 read-write CRC_BY_SECT CRC sector mode select bit When this bit is set the CRC calculation is performed at sector level, on the sectors present in the list of sectors. To add a sector to this list, use ADD_SECT and CRC_SECT bits. To clean the list, use CLEAN_SECT bit. When CRC_BY_SECT is cleared the CRC calculation is performed on all addresses defined between start and end addresses defined in FLASH_CRCSADDR and FLASH_CRCEADDR registers. 9 1 read-write ADD_SECT CRC sector select bit When this bit is set the sector whose number is written in CRC_SECT is added to the list of sectors on which the CRC is calculated. 10 1 write-only CLEAN_SECT CRC sector list clear bit When this bit is set the list of sectors on which the CRC is calculated is cleared. 11 1 write-only START_CRC CRC start bit START_CRC bit triggers a CRC calculation using the current configuration. No CRC calculation can launched when an option byte change operation is ongoing because all read accesses to embedded Flash memory registers are put on hold until the option byte change operation has completed. This bit is cleared when CRC computation starts. 16 1 read-write CLEAN_CRC CRC clear bit Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR register. 17 1 write-only CRC_BURST CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit. A Flash word is 128-bit. 20 2 read-write ALL_SECT All sectors selection When this bit is set all the sectors in user Flash are added to list of sectors on which the CRC shall be calculated. This bit is cleared when CRC computation starts. 24 1 read-write CRCSADDR CRCSADDR FLASH CRC start address register 0x34 0x20 0x00000000 0xFFFFFFFF CRC_START_ADDR CRC start address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the first Flash word to use for the CRC calculation, done burst by burst. CRC computation starts at an address aligned to the burst size defined in CRC_BURST of FLASH_CRCCR register. Hence least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank. 6 11 read-write CRCEADDR CRCEADDR FLASH CRC end address register 0x38 0x20 0x00000000 0xFFFFFFFF CRC_END_ADDR CRC end address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the Flash word starting the last burst of the CRC calculation. The burst size is defined in CRC_BURST of FLASH_CRCCR register. The least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank. 6 11 read-write CRCDATAR CRCDATAR FLASH CRC data register 0x3C 0x20 0x00000000 0xFFFFFFFF CRC_DATA CRC result This bitfield contains the result of the last CRC calculation. The value is valid only when CRC calculation completed (CRCENDF is set in FLASH_ISR register). CRC_DATA is cleared when CRC_EN is cleared in FLASH_CR register (CRC disabled), or when CLEAN_CRC bit is set in FLASH_CRCCR register. 0 32 read-only ECCSFADDR ECCSFADDR FLASH ECC single error fail address 0x40 0x20 0x00000000 0xFFFFFFFF SEC_FADD ECC single error correction fail address When a single ECC error correction occurs during a read operation, the SEC_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when SNECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC single error correction error is saved in this register. 0 32 read-only ECCDFADDR ECCDFADDR FLASH ECC double error fail address 0x44 0x20 0x00000000 0xFFFFFFFF DED_FADD ECC double error detection fail address When a double ECC detection occurs during a read operation, the DED_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when the DBECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC double error detection error is saved in this register. 0 32 read-only OPTKEYR OPTKEYR FLASH options key register 0x100 0x20 0x00000000 0xFFFFFFFF OCUKEY Options configuration unlock key Following values must be written to FLASH_OPTKEYR consecutively to unlock FLASH_OPTCR register: 1st key = 0x0819 2A3B 2nd key = 0x4C5D 6E7F Reads to this register returns zero. If above sequence is performed twice locks up the corresponding register/bit until the next system reset, and generates a bus error. 0 32 write-only OPTCR OPTCR FLASH options control register 0x104 0x20 0x00000001 0x0FFFFFFF OPTLOCK Options lock When this bit is set write to all other bits in this register, and write to OTP words, option bytes and option bytes keys control registers, are ignored. Clearing this bit requires the correct write sequence to FLASH_OPTKEYR register (see this register for details). If a wrong sequence is executed, or the unlock sequence is performed twice, this bit remains locked until next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register. 0 1 read-write PG_OPT Program options 1 1 read-write KVEIE Key valid error interrupt enable bit This bit controls if an interrupt has to be generated when KVEF is set in FLASH_OPTISR. 27 1 read-write KTEIE Key transfer error interrupt enable bit This bit controls if an interrupt has to be generated when KTEF is set in FLASH_OPTISR. 28 1 read-write OPTERRIE Option byte change error interrupt enable bit This bit controls if an interrupt has to be generated when an error occurs during an option byte change. 30 1 read-write OPTISR OPTISR FLASH options interrupt status register 0x108 0x20 0x00000000 0x00000000 KVEF Key valid error flag This bit is set when loading an unknown or corrupted option byte key. More specifically: Embedded Flash did not find an option byte key that corresponds to the given OBKINDEX[4:0] and the requested HDPL (optionally modified by NEXTKL[1:0]). It can happen for example when requested key has not being provisioned. A double error detection was found when loading the requested option byte key. In this case, if this key is provisioned again the error should disappear. When KVEF is set write to START bit in FLASH_OBKCR is ignored. An interrupt is generated when this flag is raised if the KVEIE bit of FLASH_OPTCR register is set. Setting KVEF bit of register FLASH_OPTICR clears this bit. 27 1 read-only KTEF Key transfer error flag This bit is set when embedded Flash signals an error to the SAES peripheral. It happens when the key size (128-bit or 256-bit) is not matching between embedded Flash OBKSIZE[1:0] and KEYSIZE bit in SAES_CR register. It also happen when an ECC dual error detection occurred while embedded Flash loaded an option byte key for the SAES peripheral. When KTEF is set write to START bit in FLASH_OBKCR is ignored. An interrupt is generated when this flag is raised if the KTEIE bit of FLASH_OPTCR register is set. Setting KTEF bit of register FLASH_OPTICR clears this bit. 28 1 read-only OPTERRF Option byte change error flag When OPTERRF is set, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTERRIE bit of FLASH_OPTCR register is set. Setting OPTERRF of register FLASH_OPTICR clears this bit. 30 1 read-only OPTICR OPTICR FLASH options interrupt clear register 0x10C 0x20 0x00000000 0x00000000 KVEF key valid error flag Set this bit to clear KVEF flag in FLASH_OPTISR register. 27 1 write-only KTEF key transfer error flag Set this bit to clear KTEF flag in FLASH_OPTISR register. 28 1 write-only OPTERRF Option byte change error flag Set this bit to clear OPTERRF flag in FLASH_OPTISR register. 30 1 write-only OBKCR OBKCR FLASH option byte key control register 0x110 0x20 0x00000C00 0xFFFFFFFF OBKINDEX Option byte key index This bitfield represents the index of the option byte key in a given hide protection level. Reading keys with index lower that 8, the value is not be available in OBKDRx registers. It is instead sent directly to SAES peripheral. All others keys can be read using OBKDRx registers. Up to 32 keys can be provisioned per hide protection level (0, 1 or 2), provided there is enough space left in the Flash to store them. 0 5 read-write NEXTKL Next key level 10 or 11: reserved 8 2 read-write OBKSIZE Option byte key size Application must use this bitfield to specify how many bits must be used for the new key. Embedded Flash ignores OBKSIZE during read of option keys because size is stored with the key. 10 2 read-write KEYPROG Key program This bit must be set to write option byte keys (keys are read otherwise). 14 1 read-write KEYSTART Key option start This bit is used to start the option byte key operation defined by the PROG bit. The embedded Flash memory resets START when the corresponding operation has been acknowledged. 15 1 read-write OBKDR0 OBKDR0 FLASH option bytes key data register 0 0x118 0x20 0x00000000 0xFFFFFFFF OBKDATA option byte key data, bits [31+x:0+x] Data register used in conjunction with FLASH_OBKCR register. Reading this register (read value once), or incrementing HDPL value in SBS peripheral automatically clears OBKDATA to 0x0. Writing this register prevents reading OBKDATA until option byte key programming sequence is completed. 0 32 read-write OBKDR1 OBKDR1 FLASH option bytes key data register 1 0x11C 0x20 0x00000000 0xFFFFFFFF OBKDATA option byte key data, bits [31+x:0+x] Data register used in conjunction with FLASH_OBKCR register. Reading this register (read value once), or incrementing HDPL value in SBS peripheral automatically clears OBKDATA to 0x0. Writing this register prevents reading OBKDATA until option byte key programming sequence is completed. 0 32 read-write OBKDR2 OBKDR2 FLASH option bytes key data register 2 0x120 0x20 0x00000000 0xFFFFFFFF OBKDATA option byte key data, bits [31+x:0+x] Data register used in conjunction with FLASH_OBKCR register. Reading this register (read value once), or incrementing HDPL value in SBS peripheral automatically clears OBKDATA to 0x0. Writing this register prevents reading OBKDATA until option byte key programming sequence is completed. 0 32 read-write OBKDR3 OBKDR3 FLASH option bytes key data register 3 0x124 0x20 0x00000000 0xFFFFFFFF OBKDATA option byte key data, bits [31+x:0+x] Data register used in conjunction with FLASH_OBKCR register. Reading this register (read value once), or incrementing HDPL value in SBS peripheral automatically clears OBKDATA to 0x0. Writing this register prevents reading OBKDATA until option byte key programming sequence is completed. 0 32 read-write OBKDR4 OBKDR4 FLASH option bytes key data register 4 0x128 0x20 0x00000000 0xFFFFFFFF OBKDATA option byte key data, bits [31+x:0+x] Data register used in conjunction with FLASH_OBKCR register. Reading this register (read value once), or incrementing HDPL value in SBS peripheral automatically clears OBKDATA to 0x0. Writing this register prevents reading OBKDATA until option byte key programming sequence is completed. 0 32 read-write OBKDR5 OBKDR5 FLASH option bytes key data register 5 0x12C 0x20 0x00000000 0xFFFFFFFF OBKDATA option byte key data, bits [31+x:0+x] Data register used in conjunction with FLASH_OBKCR register. Reading this register (read value once), or incrementing HDPL value in SBS peripheral automatically clears OBKDATA to 0x0. Writing this register prevents reading OBKDATA until option byte key programming sequence is completed. 0 32 read-write OBKDR6 OBKDR6 FLASH option bytes key data register 6 0x130 0x20 0x00000000 0xFFFFFFFF OBKDATA option byte key data, bits [31+x:0+x] Data register used in conjunction with FLASH_OBKCR register. Reading this register (read value once), or incrementing HDPL value in SBS peripheral automatically clears OBKDATA to 0x0. Writing this register prevents reading OBKDATA until option byte key programming sequence is completed. 0 32 read-write OBKDR7 OBKDR7 FLASH option bytes key data register 7 0x134 0x20 0x00000000 0xFFFFFFFF OBKDATA option byte key data, bits [31+x:0+x] Data register used in conjunction with FLASH_OBKCR register. Reading this register (read value once), or incrementing HDPL value in SBS peripheral automatically clears OBKDATA to 0x0. Writing this register prevents reading OBKDATA until option byte key programming sequence is completed. 0 32 read-write NVSR NVSR FLASH non-volatile status register 0x200 0x20 0x00000000 0xFFFF0000 NVSTATE Non-volatile state others: invalid configuration. 0 8 read-only NVSRP NVSRP FLASH security status register programming 0x204 0x20 0x00000000 0xFFFF0000 NVSTATE Non-volatile state programming Write to change corresponding bits in FLASH_NVSR register: Actual option byte change from close to open is triggered only after memory clear hardware process is confirmed. When NVSTATE=0xB4 (resp. 0x51) writing any other value than 0x51 (resp. 0xB4) triggers an option byte change error (OPTERRF). 0 8 read-write ROTSR ROTSR FLASH RoT status register 0x208 0x20 0x00000000 0xFFFF0000 OEM_PROVD OEM provisioned device Any other value: device is not provisioned by the OEM. 0 8 read-only DBG_AUTH Debug authentication method Any other value: no authentication method selected (NotSet). 8 8 read-only IROT_SELECT iRoT selection This option is ignored for STM32H7R devices (OEM iRoT is always selected). Any other value: OEM iRoT is selected at boot. 24 8 read-only ROTSRP ROTSRP FLASH RoT status register programming 0x20C 0x20 0x00000000 0xFFFF0000 OEM_PROVD OEM provisioned device Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 1. 0 8 read-write DBG_AUTH Debug authentication method programming Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 0. 8 8 read-write IROT_SELECT iRoT selection This option is ignored for STM32H7R devices. Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 1 and if NVSTATE is not 0xB4 (OPEN). 24 8 read-only OTPLSR OTPLSR FLASH OTP lock status register 0x210 0x20 0x00000000 0xFFFF0000 OTPL OTP lock n Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. OTPL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and can no longer be programmed. OTPL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked and can still be modified. 0 16 read-only OTPLSRP OTPLSRP FLASH OTP lock status register programming 0x214 0x20 0x00000000 0xFFFF0000 OTPL OTP lock n programming Write to change corresponding option byte bit in FLASH_OTPLSR. OTPL bits can be only be set, not cleared. 0 16 read-write WRPSR WRPSR FLASH write protection status register 0x218 0x20 0x00000000 0xFFFF0000 WRPS Write protection for sector n This bit reflects the write protection status of user Flash sector n 0 8 read-write WRPSRP WRPSRP FLASH write protection status register programming 0x21C 0x20 0x00000000 0xFFFF0000 WRPS Write protection for sector n programming Write to change corresponding bit in FLASH_WRPSR 0 8 read-write HDPSR HDPSR FLASH hide protection status register 0x230 0x20 0x00000000 0xF000FFFF HDP_AREA_START Hide protection user Flash area start This option sets the start address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected. 0 9 read-only HDP_AREA_END Hide protection user Flash area end This option sets the end address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected. 16 9 read-only HDPSRP HDPSRP FLASH hide protection status register programming 0x234 0x20 0x00000000 0xF000FFFF HDP_AREA_START Hide protection user Flash area start programming Write to change corresponding option byte bits in FLASH_HDPSR. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected. 0 9 read-write HDP_AREA_END Hide protection user Flash area end programming Write to change corresponding option byte bits in FLASH_HDPSR. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected. 16 9 read-write EPOCHSR EPOCHSR FLASH epoch status register 0x250 0x20 0x00000000 0xFFFF0000 EPOCH Epoch This value is distributed by hardware to the SAES peripheral. 0 24 read-only EPOCHSRP EPOCHSRP FLASH RoT status register programming 0x254 0x20 0x00000000 0xFFFF0000 EPOCH Epoch programming Write to change corresponding bits in FLASH_EPOCHSR register. 0 24 read-write OBW1SR OBW1SR FLASH option byte word 1 status register 0x260 0x20 0x00000000 0x00000000 BOR_LEV Brownout level These bits reflects the power level that generates a system reset. 2 2 read-only IWDG_HW Independent watchdog HW Control 4 1 read-only NRST_STOP Reset on stop mode 6 1 read-only NRST_STBY Reset on standby mode 7 1 read-only OCTO1_HSLV XSPIM_P1 High-Speed at Low-Voltage 8 1 read-only OCTO2_HSLV XSPIM_P2 High-Speed at Low-Voltage 9 1 read-only IWDG_FZ_STOP IWDG stop mode freeze When set the independent watchdog IWDG is frozen in system Stop mode. 17 1 read-only IWDG_FZ_SDBY IWDG standby mode freeze When set the independent watchdog IWDG is frozen in system Standby mode. 18 1 read-only PERSO_OK Personalization OK This bit is set on STMicroelectronics production line. 28 1 read-only VDDIO_HSLV I/O High-Speed at Low-Voltage This bit indicates that the product operates below 2.5 V. 29 1 read-only OBW1SRP OBW1SRP FLASH option byte word 1 status register programming 0x264 0x20 0x00000000 0x00000000 BOR_LEV Brownout level Write to change corresponding bits in FLASH_OBW1SR register. 2 2 read-write IWDG_HW Independent watchdog HW Control Write to change corresponding bit in FLASH_OBW1SR register. 4 1 read-write NRST_STOP Reset on stop mode programming Write to change corresponding bit in FLASH_OBW1SR register. 6 1 read-write NRST_STBY Reset on standby mode programming Write to change corresponding bit in FLASH_OBW1SR register. 7 1 read-write OCTO1_HSLV XSPIM_P1 High-Speed at Low-Voltage Write to change corresponding bit in FLASH_OBW1SR register. 8 1 read-write OCTO2_HSLV XSPIM_P2 High-Speed at Low-Voltage programming Write to change corresponding bit in FLASH_OBW1SR register. 9 1 read-write IWDG_FZ_STOP IWDG stop mode freeze Write to change corresponding bit in FLASH_OBW1SR register. 17 1 read-write IWDG_FZ_SDBY IWDG standby mode freeze programming Write to change corresponding bit in FLASH_OBW1SR register. 18 1 read-write VDDIO_HSLV I/O High-Speed at Low-Voltage programming Write to change corresponding bit in FLASH_OBW1SR register. 29 1 read-write OBW2SR OBW2SR FLASH option byte word 2 status register 0x268 0x20 0x00000000 0x00000000 ITCM_AXI_SHARE ITCM SRAM configuration 0 3 read-only DTCM_AXI_SHARE DTCM SRAM configuration 4 3 read-only ECC_ON_SRAM ECC on SRAM 8 1 read-only I2C_NI3C I2C Not I3C 9 1 read-only OBW2SRP OBW2SRP FLASH option byte word 2 status register programming 0x26C 0x20 0x00000000 0x00000000 ITCM_AXI_SHARE ITCM AXI share programming Write to change corresponding bits in FLASH_OBW2SR register. Bit 2 should be kept to 0: ITCM_AXI_SHARE: = 000 or 011: ITCM 64 Kbytes ITCM_AXI_SHARE = 001: ITCM 128 Kbytes ITCM_AXI_SHARE = 010: ITCM 192 Kbytes 0 3 read-write DTCM_AXI_SHARE DTCM AXI share programming Write to change corresponding bits in the FLASH_OBW2SR register. Bit 2 should be kept to 0: DTCM_AXI_SHARE = 000 or 011: DTCM 64 Kbytes DTCM_AXI_SHARE = 001: DTCM 128 Kbytes DTCM_AXI_SHARE = 010: DTCM 192 Kbytes 4 3 read-write ECC_ON_SRAM ECC on SRAM programming Write to change corresponding bit in FLASH_OBW2SR register. 8 1 read-write I2C_NI3C I2C Not I3C Write to change corresponding bit in FLASH_OBW2SR register. 9 1 read-write FMC Flexible memory controller 0x52004000 0x0 0x15C registers FMC FMC global interrupt 107 BCR1 BCR1 SRAM/NOR-flash chip-select control registers for bank 1 0x0 0x20 0x000030DB 0xFFFFFFFF MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 read-write MBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 read-write MUXEN Disabled Address/Data non-multiplexed 0 Enabled Address/Data multiplexed on databus 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 read-write MTYP SRAM SRAM memory type 0 PSRAM PSRAM (CRAM) memory type 1 Flash NOR Flash/OneNAND Flash 2 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 read-write MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 FACCEN Flash access enable This bit enables NOR flash memory access operations. 6 1 read-write FACCEN Disabled Corresponding NOR Flash memory access is disabled 0 Enabled Corresponding NOR Flash memory access is enabled 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 read-write BURSTEN Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode: 9 1 read-write WAITPOL ActiveLow NWAIT active low 0 ActiveHigh NWAIT active high 1 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 read-write WAITCFG BeforeWaitState NWAIT signal is active one data cycle before wait state 0 DuringWaitState NWAIT signal is active during wait state 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 read-write WREN Disabled Write operations disabled for the bank by the FMC 0 Enabled Write operations enabled for the bank by the FMC 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. 13 1 read-write WAITEN Disabled Values inside the FMC_BWTR are taken into account 0 Enabled NWAIT signal enabled 1 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 read-write EXTMOD Disabled Values inside the FMC_BWTR are not taken into account 0 Enabled Values inside the FMC_BWTR are taken into account 1 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 read-write ASYNCWAIT Disabled Wait signal not used in asynchronous mode 0 Enabled Wait signal used even in asynchronous mode 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 read-write CPSIZE NoBurstSplit No burst split when crossing page boundary 0 Bytes128 128 bytes CRAM page size 1 Bytes256 256 bytes CRAM page size 2 Bytes512 512 bytes CRAM page size 3 Bytes1024 1024 bytes CRAM page size 4 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 read-write CBURSTRW Disabled Write operations are always performed in asynchronous mode 0 Enabled Write operations are performed in synchronous mode 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 read-write CCLKEN Disabled The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set 0 Enabled The FMC_CLK is only generated during the synchronous memory access (read/write transaction) 1 WFDIS Write FIFO Disable This bit disables the Write FIFO used by the FMC. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 21 1 read-write WFDIS Enabled Write FIFO enabled 0 Disabled Write FIFO disabled 1 BMAP FMC bank mapping These bits allow different remap or swap of the FMC NOR/PSRAM and SDRAM banks (refer to Table 144). Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register. 24 2 read-write BMAP Default Default mapping 0 Swapped NOR/PSRAM bank and SDRAM bank 1/bank2 are swapped 1 Remapped SDRAM Bank2 remapped on FMC bank2 and still accessible at default mapping 2 FMCEN FMC Enable This bit enables/disables the FMC. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 31 1 read-write FMCEN Disabled Disable the FMC controller 0 Enabled Enable the FMC controller 1 4 0x8 1-4 BTR%s BTR%s SRAM/NOR-flash chip-select timing registers for bank %s 0x4 0x20 0x0FFFFFFF 0xFFFFFFFF ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 109 to Figure 121), used in SRAMs, ROMs and asynchronous NOR flash: ... For each access mode address setup phase duration, please refer to the respective figure (refer to Figure 109 to Figure 121). Note: In synchronous accesses, this value is dont care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1. 0 4 read-write 0 15 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 109 to Figure 121), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, please refer to the respective figure (Figure 109 to Figure 121). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 read-write 1 15 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 109 to Figure 121), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, please refer to the respective figure (Figure 109 to Figure 121). Example: Mode1, write access, DATAST = 1: Data-phase duration = DATAST+1 = 1 x fmc_ker_ck clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 read-write 1 255 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-to-write) transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ). The programmed bus turnaround delay is inserted between an asynchronous read (muxed or mode D) or write transaction and any other asynchronous /synchronous read or write to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different except for muxed or mode D. In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed and D modes. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for muxed and D modes. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except for muxed and D modes. An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous writes (burst or single) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or different for the case of read. Two consecutive synchronous reads (burst or single) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous writes (burst or single) to different static bank. A synchronous write (burst or single) access and a synchronous read from the same or a different bank. ... 16 4 read-write 0 15 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of fmc_ker_ck cycles: In asynchronous NOR flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section 23.7.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 read-write 1 15 DATLAT (see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), these bits define the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in fmc_ker_ck periods, but in FMC_CLK periods. For asynchronous access, this value is don't care. 24 4 read-write 0 15 ACCMOD Access mode These bits specify the Asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 read-write ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 3 0x8 2-4 BCR%s BCR%s SRAM/NOR-flash chip-select control registers for bank %s 0x8 0x20 0x000030D2 0xFFFFFFFF MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 read-write MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 read-write MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 read-write MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 read-write FACCEN Flash access enable This bit enables NOR flash memory access operations. 6 1 read-write BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 read-write WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode: 9 1 read-write WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 read-write WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 read-write WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. 13 1 read-write EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 read-write ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 read-write CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 read-write CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 read-write PCR PCR NAND flash control registers 0x80 0x20 0x00000018 0xFFFFFFFF PWAITEN Wait feature enable bit. This bit enables the Wait feature for the NAND flash memory bank: 1 1 read-write PWAITEN Disabled Wait feature disabled 0 Enabled Wait feature enabled 1 PBKEN NAND flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus 2 1 read-write PBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 PWID Data bus width. These bits define the external memory device width. 4 2 read-write PWID Bits8 External memory device width 8 bits 0 Bits16 External memory device width 16 bits 1 ECCEN ECC computation logic enable bit 6 1 read-write ECCEN Disabled ECC logic is disabled and reset 0 Enabled ECC logic is enabled 1 TCLR CLE to RE delay. These bits set time from CLE low to RE low in number of fmc_ker_ck clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) tfmc_ker_ck where tfmc_ker_ck is the fmc_ker_ck clock period Note: Set is MEMSET or ATTSET according to the addressed space. 9 4 read-write 0 15 TAR ALE to RE delay. These bits set time from ALE low to RE low in number of fmc_ker_ck clock cycles. Time is: t_ar = (TAR + SET + 2) tfmc_ker_ck where tfmc_ker_ck is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 13 4 0 15 ECCPS ECC page size. These bits define the page size for the extended ECC: 17 3 read-write ECCPS Bytes256 ECC page size 256 bytes 0 Bytes512 ECC page size 512 bytes 1 Bytes1024 ECC page size 1024 bytes 2 Bytes2048 ECC page size 2048 bytes 3 Bytes4096 ECC page size 4096 bytes 4 Bytes8192 ECC page size 8192 bytes 5 SR SR FIFO status and interrupt register 0x84 0x20 0x00000040 0xFFFFFFFF IRS Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 0 1 read-write IRS DidNotOccur Interrupt rising edge did not occur 0 Occurred Interrupt rising edge occurred 1 ILS Interrupt high-level status The flag is set by hardware and reset by software. 1 1 read-write ILS DidNotOccur Interrupt high-level did not occur 0 Occurred Interrupt high-level occurred 1 IFS Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 2 1 read-write IFS DidNotOccur Interrupt falling edge did not occur 0 Occurred Interrupt falling edge occurred 1 IREN Interrupt rising edge detection enable bit 3 1 read-write IREN Disabled Interrupt rising edge detection request disabled 0 Enabled Interrupt rising edge detection request enabled 1 ILEN Interrupt high-level detection enable bit 4 1 read-write ILEN Disabled Interrupt high-level detection request disabled 0 Enabled Interrupt high-level detection request enabled 1 IFEN Interrupt falling edge detection enable bit 5 1 read-write IFEN Disabled Interrupt falling edge detection request disabled 0 Enabled Interrupt falling edge detection request enabled 1 FEMPT FIFO empty. Read-only bit that provides the status of the FIFO 6 1 read-only FEMPT NotEmpty FIFO not empty 0 Empty FIFO empty 1 PMEM PMEM Common memory space timing register 0x88 0x20 0xFCFCFCFC 0xFFFFFFFF MEMSET Common memory x setup time These bits define the number of fmc_ker_ck (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND flash read or write access to common memory space: 0 8 read-write 0 254 MEMWAIT Common memory wait time These bits define the minimum number of fmc_ker_ck (+1) clock cycles to assert the command (NWE, NOE), for NAND flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of fmc_ker_ck: 8 8 read-write 1 254 MEMHOLD Common memory hold time These bits define the number of fmc_ker_ck clock cycles for write accesses and fmc_ker_ck+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND flash read or write access to common memory space: 16 8 read-write 1 254 MEMHIZ Common memory x data bus Hi-Z time These bits define the number of fmc_ker_ck clock cycles during which the data bus is kept Hi-Z after the start of a NAND flash write access to common memory space. This is only valid for write transactions: 24 8 read-write 0 254 PATT PATT Attribute memory space timing registers 0x8C 0x20 0xFCFCFCFC 0xFFFFFFFF ATTSET Attribute memory setup time These bits define the number of fmc_ker_ck (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND flash read or write access to attribute memory space: 0 8 read-write 0 254 ATTWAIT Attribute memory wait time These bits define the minimum number of x fmc_ker_ck (+1) clock cycles to assert the command (NWE, NOE), for NAND flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of fmc_ker_ck: 8 8 read-write 1 254 ATTHOLD Attribute memory hold time These bits define the number of fmc_ker_ck clock cycles during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND flash read or write access to attribute memory space: 16 8 read-write 1 254 ATTHIZ Attribute memory data bus Hi-Z time These bits define the number of fmc_ker_ck clock cycles during which the data bus is kept in Hi-Z after the start of a NAND flash write access to attribute memory space on socket. Only valid for writ transaction: 24 8 read-write 0 254 ECCR ECCR ECC result registers 0x94 0x20 0x00000000 0xFFFFFFFF ECC ECC result This field contains the value computed by the ECC computation logic. Table 184 describes the contents of these bitfields. 0 32 read-only 0 4294967295 4 0x8 1-4 BWTR%s BWTR%s SRAM/NOR-flash write timing registers for bank %s 0x104 0x20 0x0FFFFFFF 0xFFFFFFFF ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in fmc_ker_ck cycles (refer to Figure 109 to Figure 121), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 read-write 0 15 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 109 to Figure 121), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR flash accesses, this value is not used, the address hold phase is always 1 flash clock period duration. 4 4 read-write 1 15 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 109 to Figure 121), used in asynchronous SRAM, PSRAM and NOR flash memory accesses: ... 8 8 read-write 1 255 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) fmc_ker_ck period more or equal to tEHELmin. The programmed bus turnaround delay is inserted between an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different expect for muxed or mode D. In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed and D modes. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous writes (burst or single) to the same bank. A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous writes (burst or single) to different static bank. A synchronous write (burst or single) transfer and a synchronous read from the same or a different bank. ... 16 4 read-write 0 15 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 read-write ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 SDCR1 SDCR1 SDRAM Control registers for SDRAM memory bank 1 0x140 0x20 0x000002D0 0xFFFFFFFF NC Number of column address bits These bits define the number of bits of a column address. 0 2 read-write NC Bits8 8 bits 0 Bits9 9 bits 1 Bits10 10 bits 2 Bits11 11 bits 3 NR Number of row address bits These bits define the number of bits of a row address. 2 2 read-write NR Bits11 11 bits 0 Bits12 12 bits 1 Bits13 13 bits 2 MWID Memory data bus width. These bits define the memory device width. 4 2 read-write MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 NB Number of internal banks This bit sets the number of internal banks. 6 1 read-write NB NB2 Two internal Banks 0 NB4 Four internal Banks 1 CAS CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles 7 2 read-write CAS Clocks1 1 cycle 1 Clocks2 2 cycles 2 Clocks3 3 cycles 3 WP Write protection This bit enables Write mode access to the SDRAM bank. 9 1 read-write WP Disabled Write accesses allowed 0 Enabled Write accesses ignored 1 SDCLK SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only. 10 2 read-write SDCLK Disabled SDCLK clock disabled 0 Div2 SDCLK period = 2 x HCLK period 2 Div3 SDCLK period = 3 x HCLK period 3 RBURST Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only. 12 1 read-write RBURST Disabled Single read requests are not managed as bursts 0 Enabled Single read requests are always managed as bursts 1 RPIPE Read pipe These bits define the delay, in fmc_ker_ck clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only. 13 2 read-write RPIPE NoDelay No clock cycle delay 0 Clocks1 One clock cycle delay 1 Clocks2 Two clock cycles delay 2 SDCR2 SDCR2 SDRAM Control registers for SDRAM memory bank 2 0x144 0x20 0x000002D0 0xFFFFFFFF NC Number of column address bits These bits define the number of bits of a column address. 0 2 read-write NR Number of row address bits These bits define the number of bits of a row address. 2 2 read-write MWID Memory data bus width. These bits define the memory device width. 4 2 read-write NB Number of internal banks This bit sets the number of internal banks. 6 1 read-write CAS CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles 7 2 read-write WP Write protection This bit enables Write mode access to the SDRAM bank. 9 1 read-write SDCLK SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only. 10 2 read-write RBURST Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only. 12 1 read-write RBURST Disabled Single read requests are not managed as bursts 0 Enabled Single read requests are always managed as bursts 1 RPIPE Read pipe These bits define the delay, in fmc_ker_ck clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only. 13 2 read-write RPIPE NoDelay No clock cycle delay 0 Clocks1 One clock cycle delay 1 Clocks2 Two clock cycles delay 2 2 0x4 1-2 SDTR%s SDTR%s SDRAM Timing registers for SDRAM memory bank %s 0x148 0x20 0x0FFFFFFF 0xFFFFFFFF TMRD Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. .... 0 4 read-write 0 15 TXSR Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device. 4 4 read-write 0 15 TRAS Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. .... 8 4 read-write 0 15 TRC Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care. 12 4 read-write 0 15 TWR Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: Note: TWR TRAS - TRCD and TWR TRC - TRCD - TRP Note: Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Note: If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank. 16 4 read-write 0 15 TRP Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are dont care. 20 4 read-write 0 15 TRCD Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .... 24 4 read-write 0 15 SDCMR SDCMR SDRAM Command mode register 0x150 0x20 0x00000000 0xFFFFFFFF MODE Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0. 0 3 read-write MODE Normal Normal Mode 0 ClockConfigurationEnable Clock Configuration Enable 1 PALL PALL (All Bank Precharge) command 2 AutoRefreshCommand Auto-refresh command 3 LoadModeRegister Load Mode Resgier 4 SelfRefreshCommand Self-refresh command 5 PowerDownCommand Power-down command 6 CTB2 Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. 3 1 read-write CTB2 NotIssued Command not issued to SDRAM Bank 1 0 Issued Command issued to SDRAM Bank 1 1 CTB1 Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not. 4 1 read-write NRFS Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. .... 5 4 read-write 0 15 MRD Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD[13:0] bits are also used to program the extended mode register for mobile SDRAM. 9 14 read-write 0 8191 SDRTR SDRTR SDRAM refresh timer register 0x154 0x20 0x00000000 0xFFFFFFFF CRE Clear Refresh error flag This bit is used to clear the Refresh Error Flag (RE) in the Status Register. 0 1 write-only CRE Clear Refresh Error Flag is cleared 1 COUNT Refresh Timer Count This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20 1 13 read-write 0 8191 REIE RES Interrupt Enable 14 1 read-write REIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated if RE = 1 1 SDSR SDSR SDRAM Status register 0x158 0x20 0x00000000 0xFFFFFFFF RE Refresh error flag An interrupt is generated if REIE = 1 and RE = 1 0 1 read-only RE NoError No refresh error has been detected 0 Error A refresh error has been detected 1 MODES1 Status Mode for Bank 1 These bits define the Status Mode of SDRAM Bank 1. 1 2 read-only MODES1 Normal Normal Mode 0 SelfRefresh Self-refresh mode 1 PowerDown Power-down mode 2 MODES2 Status Mode for Bank 2 These bits define the Status Mode of SDRAM Bank 2. 3 2 read-only GFXMMU Chrom-GRC GFXMMU 0x52010000 0x0 0x3000 registers GFXMMU GFXMMU global interrupt 100 CR CR GFXMMU configuration register 0x0 0x20 0x00000000 0xFFFFFFFF B0OIE Buffer 0 overflow interrupt enable This bit enables the buffer 0 overflow interrupt. 0 1 read-write B1OIE Buffer 1 overflow interrupt enable This bit enables the buffer 1 overflow interrupt. 1 1 read-write B2OIE Buffer 2 overflow interrupt enable This bit enables the buffer 2 overflow interrupt. 2 1 read-write B3OIE Buffer 3 overflow interrupt enable This bit enables the buffer 3 overflow interrupt. 3 1 read-write AMEIE AXI master error interrupt enable This bit enables the AXI master error interrupt. 4 1 read-write BS Block size This bit defines the size of the blocks 6 1 read-write ATE Address translation enable This bit enables the address translation based on the values programmed in the LUT. 15 1 read-write B0PE Buffer 0 packing enable This bit enables the packing on buffer 0. The packing is functional only if the block size is configured in 12-byte mode. In 16-byte mode, this bit is ignored. 24 1 read-write B0PM Buffer 0 packing mode This bit selects the byte to be removed during packing operations on buffer 0 25 1 read-write B1PE Buffer 1 packing enable This bit enables the packing on buffer 1. The packing is functional only if the block size is configured in 12-byte mode. In 16-byte mode, this bit is ignored. 26 1 read-write B1PM Buffer 1 packing mode This bit selects the byte to be removed during packing operations on buffer 1 27 1 read-write B2PE Buffer 2 packing enable This bit enables the packing on buffer 2. The packing is functional only if the block size is configured in 12-byte mode. In 16-byte mode, this bit is ignored. 28 1 read-write B2PM Buffer 2 packing mode This bit selects the byte to be removed during packing operations on buffer 2 29 1 read-write B3PE Buffer 3 packing enable This bit enables the packing on buffer 3. The packing is functional only if the block size is configured in 12-byte mode. In 16-byte mode, this bit is ignored. 30 1 read-write B3PM Buffer 3 packing mode This bit selects the byte to be removed during packing operations on buffer 3 31 1 read-write SR SR GFXMMU status register 0x4 0x20 0x00000000 0xFFFFFFFF B0OF Buffer 0 overflow flag This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. 0 1 read-only B1OF Buffer 1 overflow flag This bit is set when an overflow occurs during the offset calculation of the buffer 1. It is cleared by writing 1 to CB1OF. 1 1 read-only B2OF Buffer 2 overflow flag This bit is set when an overflow occurs during the offset calculation of the buffer 2. It is cleared by writing 1 to CB2OF. 2 1 read-only B3OF Buffer 3 overflow flag This bit is set when an overflow occurs during the offset calculation of the buffer 3. It is cleared by writing 1 to CB3OF. 3 1 read-only AMEF AXI master error flag This bit is set when an AXI error happens during a transaction. It is cleared by writing 1 to CAMEF. 4 1 read-only FCR FCR GFXMMU flag clear register 0x8 0x20 0x00000000 0xFFFFFFFF CB0OF Clear buffer 0 overflow flag Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. 0 1 read-write CB1OF Clear buffer 1 overflow flag Writing 1 clears the buffer 1 overflow flag in the GFXMMU_SR register. 1 1 read-write CB2OF Clear buffer 2 overflow flag Writing 1 clears the buffer 2 overflow flag in the GFXMMU_SR register. 2 1 read-write CB3OF Clear buffer 3 overflow flag Writing 1 clears the buffer 3 overflow flag in the GFXMMU_SR register. 3 1 read-write CAMEF Clear AXI master error flag Writing 1 clears the AXI master error flag in the GFXMMU_SR register. 4 1 read-write DVR DVR GFXMMU default value register 0x10 0x20 0x00000000 0xFFFFFFFF DV Default value This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped. 0 32 read-write DAR DAR GFXMMU default alpha register 0x14 0x20 0x00000000 0xFFFFFFFF DA Default alpha This field indicates the default 8-bit value which is merged with the 24-bit value when a master accesses a virtual memory location in packed mode. 0 8 read-write B0CR B0CR GFXMMU buffer 0 configuration register 0x20 0x20 0x00000000 0xFFFFFFFF PBO Physical buffer offset Offset of the physical buffer. 4 19 read-write PBBA Physical buffer base address Base address MSB of the physical buffer. 23 9 read-write B1CR B1CR GFXMMU buffer 1 configuration register 0x24 0x20 0x00000000 0xFFFFFFFF PBO Physical buffer offset Offset of the physical buffer. 4 19 read-write PBBA Physical buffer base address Base address MSB of the physical buffer. 23 9 read-write B2CR B2CR GFXMMU buffer 2 configuration register 0x28 0x20 0x00000000 0xFFFFFFFF PBO Physical buffer offset Offset of the physical buffer. 4 19 read-write PBBA Physical buffer base address Base address MSB of the physical buffer. 23 9 read-write B3CR B3CR GFXMMU buffer 3 configuration register 0x2C 0x20 0x00000000 0xFFFFFFFF PBO Physical buffer offset Offset of the physical buffer. 4 19 read-write PBBA Physical buffer base address Base address MSB of the physical buffer. 23 9 read-write 1024 0x8 0-1023 LUT%s Cluster LUT%s, containing LUT*L, LUT*H 0x1000 LUTL LUT0L Graphic MMU LUT entry x low 0x0 0x20 0x00000000 0xFFFFFFFF EN Enable Line enable. 0 1 read-write FVB First valid block Number of the first valid block of line number x. 8 8 read-write LVB Last valid block Number of the last valid block of line number X. 16 8 read-write LUTH LUT0H Graphic MMU LUT entry x high 0x4 0x20 0x00000000 0xFFFFFFFF LO Line offset Line offset of line number x expressed in number of blocks 0 18 read-write GFXTIM Graphic timer 0x50004000 0x0 0x400 registers GFXTIM GFXTIM global interrupt 94 CR CR GFXTIM configuration register 0x0 0x20 0x00000000 0xFFFFFFFF TES tearing source This field selects the tearing-effect source. 0 2 read-write TEPOL tearing--effect polarity This bit selects the tearing-effect polarity. 4 1 read-write SYNCS synchronization source This field selects the synchronization signals (HSYNC and VSYNC) sources. 8 2 read-write FCCOE frame-clock calibration output enable This bit enables the frame-clock output. 16 1 read-write LCCOE line-clock calibration output enable This bit enables the line-clock output. 17 1 read-write CGCR CGCR GFXTIM clock generator configuration register 0x4 0x20 0x00000000 0xFFFFFFFF LCS line clock source This field configures the line clock source. 0 3 read-write LCCCS line clock counter clock source This bit configures the clock source for the line clock counter. 4 1 read-write LCCFR line clock counter force reload This bit forces line clock counter reload. 8 1 write-only LCCHRS line clock counter hardware reload source This field configures the hardware reload source for the line clock counter. 12 3 read-write FCS frame clock source This field configures the frame clock source 16 3 read-write FCCCS frame clock counter clock source This field configures the clock source for the frame clock counter. 20 3 read-write FCCFR frame clock counter force reload This bit forces frame clock counter reload 24 1 write-only FCCHRS frame- -clock counter hardware reload source This field configures the hardware reload source for the frame- -clock counter. 28 3 read-write TCR TCR GFXTIM timers configuration register 0x8 0x20 0x00000000 0xFFFFFFFF AFCEN absolute frame counter enable This bit enables the absolute frame counter. 0 1 write-only FAFCR force absolute frame counter reset This bit forces the reset of the absolute frame counter. 1 1 write-only ALCEN absolute line counter enable This bit enables the absolute line counter. 4 1 write-only FALCR force absolute line counter reset This bit forces the reset of the absolute line counter. 5 1 write-only RFC1EN relative frame counter 1 enable This bit enables the relative frame counter 1. 16 1 write-only RFC1CM relative frame counter 1 continuous mode This bit enables the continuous mode of the relative frame counter 1. 17 1 read-write FRFC1R force relative frame counter 1 reload This bit forces the reload of the relative frame counter 1. 18 1 write-only RFC2EN relative frame counter 2 enable This bit enables the relative frame counter 2. 20 1 write-only RFC2CM relative frame counter 2 continuous mode This bit enables the continuous mode of the relative frame counter 2. 21 1 read-write FRFC2R force relative frame counter 2 reload This bit forces the reload of the relative frame counter 2. 22 1 write-only TDR TDR GFXTIM timers disable register 0xC 0x20 0x00000000 0xFFFFFFFF AFCDIS absolute frame counter disable This bit disables the absolute frame counter. 0 1 write-only ALCDIS absolute line counter disable This bit disables the absolute line counter. 4 1 write-only RFC1DIS relative frame counter 1 disable This bit disables the relative frame counter 1. 16 1 write-only RFC2DIS relative frame counter 2 disable This bit disables the relative frame counter 2. 20 1 write-only EVCR EVCR GFXTIM events control register 0x10 0x20 0x00000000 0xFFFFFFFF EV1EN event 1 enable This bit enables the complex event 1 generation. 0 1 read-write EV2EN event 2 enable This bit enables the complex event 2 generation. 1 1 read-write EV3EN event 3 enable This bit enables the complex event 3 generation. 2 1 read-write EV4EN event 4 enable This bit enables the complex event 4 generation. 3 1 read-write EVSR EVSR GFXTIM events selection register 0x14 0x20 0x00000000 0xFFFFFFFF LES1 line-event selection 1 This field defines the line-event selection for complex event 1 generation. others: reserved 0 3 read-write FES1 frame-event selection 1 This field defines the frame-event selection for complex event 1 generation. others: reserved 4 3 read-write LES2 line-event selection 2 This field defines the line-event selection for complex event 2 generation. others: reserved 8 3 read-write FES2 frame-event selection 2 This field defines the frame-event selection for complex event 2 generation. others: reserved 12 3 read-write LES3 line-event selection 3 This field defines the line-event selection for complex event 3 generation. others: reserved 16 3 read-write FES3 frame-event selection 3 This field defines the frame-event selection for complex event 3 generation. others: reserved 20 3 read-write LES4 line-event selection 4 This field defines the line-event selection for complex event 4 generation. others: Reserved 24 3 read-write FES4 frame-event selection 4 This field defines the frame-event selection for complex event 4 generation. others: reserved 28 3 read-write WDGTCR WDGTCR GFXTIM watchdog timer configuration register 0x20 0x20 0x00000000 0xFFFFFFFF WDGEN watchdog enable This bit enables the graphic watchdog. 0 1 write-only WDGDIS watchdog disable This bit disables the graphic watchdog. 1 1 write-only WDGS watchdog status This bit returns the status of the graphic watchdog. 2 1 read-only WDGHRC watchdog hardware reload configuration This field configures the watchdog hardware reload. 4 2 read-write WDGCS watchdog clock source This field selects the watchdog clock source. others: reserved 8 4 read-write FWDGR force watchdog reload This bit forces the reload of the graphic watchdog. 16 1 write-only ISR ISR GFXTIM interrupt status register 0x30 0x20 0x00000000 0xFFFFFFFF AFCOF absolute frame counter overflow flag This bit indicates an overflow occurred on the absolute frame counter. 0 1 read-only ALCOF absolute line counter overflow flag This bit indicates an overflow occurred on the absolute line counter. 1 1 read-only TEF tearing-effect flag This bit indicates a tearing effect event occurred. 2 1 read-only AFCC1F absolute frame counter compare 1 flag This bit indicates match on compare 1 of the absolute frame counter. 4 1 read-only ALCC1F absolute line counter compare 1 flag This bit indicates match on compare 1 of the absolute line counter. 8 1 read-only ALCC2F absolute line counter compare 2 flag This bit indicates match on compare 2 of the absolute line counter. 9 1 read-only RFC1RF relative frame counter 1 reload flag This bit indicates relative frame counter 1 has been reloaded. 12 1 read-only RFC2RF relative frame counter 2 reload flag This bit indicates relative frame counter 2 has been reloaded. 13 1 read-only EV1F event 1 flag This bit indicates a complex event 1 occurred. 16 1 read-only EV2F event 2 flag This bit indicates a complex event 2 occurred. 17 1 read-only EV3F event 3 flag This bit indicates a complex event 3 occurred. 18 1 read-only EV4F event 4 flag This bit indicates a complex event 4 occurred. 19 1 read-only WDGAF watchdog alarm flag This bit indicates that a graphic watchdog alarm occurred. 24 1 read-only WDGPF watchdog pre-alarm flag This bit indicates that a graphic watchdog pre-alarm occurred. 25 1 read-only ICR ICR GFXTIM interrupt clear register 0x34 0x20 0x00000000 0xFFFFFFFF CAFCOF clear absolute frame counter overflow flag This bit clears AFCOF in GXTIM_ISR. 0 1 write-only CALCOF clear absolute line counter overflow flag This bit clears ALCOF in GXTIM_ISR. 1 1 write-only CTEF clear tearing-effect flag This bit clears TEF in GXTIM_ISR. 2 1 write-only CAFCC1F clear absolute frame counter compare 1 flag This bit clears AFCC1F in GXTIM_ISR. 4 1 write-only CALCC1F clear absolute line counter compare 1 flag This bit clears ALCC1F in GXTIM_ISR. 8 1 write-only CALCC2F clear absolute line counter compare 2 flag This bit clears ALCC2F in GXTIM_ISR. 9 1 write-only CRFC1RF clear relative frame counter 1 reload flag This bit clears RFC1RF in GXTIM_ISR. 12 1 write-only CRFC2RF clear relative frame counter 2 reload flag This bit clears RFC2RF in GXFXTIM_ISR. 13 1 write-only CEV1F clear event 1 flag This bit EV1F in GXFXTIM_ISR. 16 1 write-only CEV2F clear event 2 flag This bit clears EV2F in GXFXTIM_ISR. 17 1 write-only CEV3F clear event 3 flag This bit clears EV3F in GXFXTIM_ISR. 18 1 write-only CEV4F clear event 4 flag This bit clears EV4F in GXFXTIM_ISR. 19 1 write-only CWDGAF clear watchdog alarm flag This bit clears WDGAF in GXFXTIM_ISR. 24 1 write-only CWDGPF clear watchdog pre-alarm flag This bit clears WDGPF in GXFXTIM_ISR. 25 1 write-only IER IER GFXTIM interrupt enable register 0x38 0x20 0x00000000 0xFFFFFFFF AFCOIE absolute frame counter overflow interrupt enable This bit enables the absolute frame counter overflow interrupt generation. 0 1 read-write ALCOIE absolute line counter overflow interrupt enable This bit enables the absolute line counter overflow interrupt generation. 1 1 read-write TEIE tearing-effect interrupt enable This bit enables the Tearing Effect interrupt generation. 2 1 read-write AFCC1IE absolute frame counter compare 1 interrupt enable This bit enables the absolute frame counter compare interrupt generation. 4 1 read-write ALCC1IE absolute line counter compare 1 interrupt enable This bit enables the absolute line counter compare 1 interrupt generation. 8 1 read-write ALCC2IE absolute line counter compare 2 interrupt enable This bit enables the absolute line counter compare 2 interrupt generation. 9 1 read-write RFC1RIE relative frame counter 1 reload interrupt enable This bit enables the relative frame counter 1 reload interrupt generation. 12 1 read-write RFC2RIE relative frame counter 2 reload interrupt enable This bit enables the relative frame counter 2 reload interrupt generation. 13 1 read-write EV1IE event 1 interrupt enable This bit enables the complex event 1 interrupt generation. 16 1 read-write EV2IE event 2 interrupt enable This bit enables the complex event 2 interrupt generation. 17 1 read-write EV3IE event 3 interrupt enable This bit enables the complex event 3 interrupt generation. 18 1 read-write EV4IE event 4 interrupt enable This bit enables the complex event 4 interrupt generation. 19 1 read-write WDGAIE watchdog alarm interrupt enable This bit enables the watchdog alarm interrupt generation. 24 1 read-write WDGPIE watchdog pre-alarm interrupt enable This bit enables the watchdog pre-alarm interrupt generation. 25 1 read-write TSR TSR GFXTIM timers status register 0x3C 0x20 0x00000000 0xFFFFFFFF AFCS absolute frame counter status This bit returns the status of the absolute frame counter. 0 1 read-only ALCS absolute line counter status This bit returns the status of the absolute line counter. 4 1 read-only RFC1S relative frame counter 1 status This bit returns the status of the relative frame counter 1. 16 1 read-only RFC2S relative frame counter 2 status This bit returns the status of the relative frame counter 2. 20 1 read-only LCCRR LCCRR GFXTIM line clock counter reload register 0x40 0x20 0x00000000 0xFFFFFFFF RELOAD reload value Reload value of the line clock counter. 0 22 read-write FCCRR FCCRR GFXTIM frame clock counter reload register 0x44 0x20 0x00000000 0xFFFFFFFF RELOAD reload value Reload value of the frame clock counter. 0 12 read-write ATR ATR GFXTIM absolute time register 0x50 0x20 0x00000000 0xFFFFFFFF LINE line number Current value of the absolute line counter. 0 12 read-only FRAME fame number Current value of the absolute frame counter. 12 20 read-only AFCR AFCR GFXTIM absolute frame counter register 0x54 0x20 0x00000000 0xFFFFFFFF FRAME frame number Current value of the absolute frame counter. Note: This field can only be written when the absolute frame counter is disabled. 0 20 read-write ALCR ALCR GFXTIM absolute line counter register 0x58 0x20 0x00000000 0xFFFFFFFF LINE line number Current value of the absolute line counter. Note: This field can only be written when the absolute frame counter is disabled. 0 12 read-write AFCC1R AFCC1R GFXTIM absolute frame counter compare 1 register 0x60 0x20 0x00000000 0xFFFFFFFF FRAME frame number Compare 1 value for the absolute frame counter. 0 20 read-write ALCC1R ALCC1R GFXTIM absolute line counter compare 1 register 0x70 0x20 0x00000000 0xFFFFFFFF LINE line number Compare value 1 for the absolute line counter. 0 12 read-write ALCC2R ALCC2R GFXTIM absolute line counter compare 2 register 0x74 0x20 0x00000000 0xFFFFFFFF LINE line number Compare value 2 for the absolute line counter. 0 12 read-write RFC1R RFC1R GFXTIM relative frame counter 1 register 0x80 0x20 0x00000000 0xFFFFFFFF FRAME frame number Current value of the relative frame counter 1. 0 12 read-only RFC1RR RFC1RR GFXTIM relative frame counter 1 reload register 0x84 0x20 0x00000000 0xFFFFFFFF FRAME frame reload value Reload value for the relative frame counter 1. 0 12 read-write RFC2R RFC2R GFXTIM relative frame counter 2 register 0x88 0x20 0x00000000 0xFFFFFFFF FRAME frame number Current value of the relative frame counter 2. 0 12 read-only RFC2RR RFC2RR GFXTIM relative frame counter 2 reload register 0x8C 0x20 0x00000000 0xFFFFFFFF FRAME frame reload value Reload value for the relative frame counter 2. 0 12 read-write WDGCR WDGCR GFXTIM watchdog counter register 0xA0 0x20 0x00000000 0xFFFFFFFF VALUE value Current value of the watchdog counter. 0 16 read-only WDGRR WDGRR GFXTIM watchdog reload register 0xA4 0x20 0x00000000 0xFFFFFFFF RELOAD reload value Reload value of the watchdog counter. 0 16 read-write WDGPAR WDGPAR GFXTIM watchdog pre-alarm register 0xA8 0x20 0x00000000 0xFFFFFFFF PREALARM pre-alarm value Pre-alarm value of the watchdog counter. 0 16 read-write GPDMA General purpose direct memory access controller GPDMA 0x40021000 0x0 0x1000 registers GPDMA1_CH0 GPDMA1 channel 0 interrupt 39 GPDMA1_CH1 GPDMA1 channel 1 interrupt 40 GPDMA1_CH2 GPDMA1 channel 2 interrupt 41 GPDMA1_CH3 GPDMA1 channel 3 interrupt 42 GPDMA1_CH4 GPDMA1 channel 4 interrupt 43 GPDMA1_CH5 GPDMA1 channel 5 interrupt 44 GPDMA1_CH6 GPDMA1 channel 6 interrupt 45 GPDMA1_CH7 GPDMA1 channel 7 interrupt 46 GPDMA1_CH8 GPDMA1 channel 8 interrupt 133 GPDMA1_CH9 GPDMA1 channel 9 interrupt 134 GPDMA1_CH10 GPDMA1 channel 10 interrupt 135 GPDMA1_CH11 GPDMA1 channel 11 interrupt 136 GPDMA1_CH12 GPDMA1 channel 12 interrupt 137 GPDMA1_CH13 GPDMA1 channel 13 interrupt 138 GPDMA1_CH14 GPDMA1 channel 14 interrupt 139 GPDMA1_CH15 GPDMA1 channel 15 interrupt 140 GPU2D GPU2D global interrupt 149 GPU2D_ER GPU2D error interrupt 150 TCACHE GPU cache interrupt 151 PRIVCFGR PRIVCFGR GPDMA privileged configuration register 0x4 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 PRIV%s privileged state of channel x 0 1 read-write RCFGLOCKR RCFGLOCKR GPDMA configuration lock register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 LOCK%s lock the configuration of GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset. 0 1 read-write MISR MISR GPDMA masked interrupt status register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 MIS%s masked interrupt status of channel x 0 1 read-only 12 0x80 0-11 CH%s Channel cluster 0x50 LBAR C0LBAR GPDMA channel 0 linked-list base address register 0x0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write FCR C0FCR GPDMA channel 0 flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only SR C0SR GPDMA channel 0 status register 0x10 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag This idle flag is deasserted by hardware when the channel is enabled (GPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). 0 1 read-only TCF transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]). 8 1 read-only HTF half transfer flag A half transfer event is either a half block transfer or a half 2D/repeated block transfer, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]). A half block transfer occurs when half of the bytes of the source block size (rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. A half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2)) has been transferred to the destination. 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (see GPDMA_CxTR1.DDW_LOG2[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (GPDMA_CxSR.SUSPF = 1). 16 8 read-only CR C0CR GPDMA channel 0 control register 0x14 0x20 0x00000000 0xFFFFFFFF EN enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is deasserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, for example if LSM = 1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 read-write RESET reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (GPDMA_CxSR.SUSPF = 1 and GPDMA_CxSR.IDLEF = GPDMA_CxCR.EN = 1) - channel in disabled state (GPDMA_CxSR.IDLEF = 1 and GPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR) before enabling again the channel (see the programming sequence in Figure 47). 1 1 write-only SUSP suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel (channel with an ongoing GPDMA transfer over its master ports). The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in Figure 46. 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until GPDMA_CxBR1.BNDT[15:0] = 0 and GPDMA_CxBR1.BRC[10:0] = 0. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 16 1 read-write LAP linked-list allocated port This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 22 2 read-write TR1 C0TR1 GPDMA channel 0 transfer register 1 0x40 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (GPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. Note: A source burst transfer must have an aligned address with its data width (start address GPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. 0 2 read-write SINC source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. Note: If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower singles/bursts, but the data integrity is guaranteed. 4 6 read-write PAM padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else, in the following enumerated values, the condition PAM_1 is when destination data width is higher that source data width, and the condition PAM_2 is when destination data width is higher than source data width. Note: If the transfer from the source peripheral is configured with peripheral flow-control mode (SWREQ = 0 and PFREQ = 1 and DREQ = 0), and if the destination data width > the source data width, packing is not supported. 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word If the source data width is shorter than a word, this bit is ignored. If the source data width is a word: 13 1 read-write SAP source allocated port This bit is used to allocate the master port for the source transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 14 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. Note: A destination burst transfer must have an aligned address with its data width (start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0], versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and no transfer is issued. 16 2 read-write DINC destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. Note: If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower singles/bursts, but the data integrity is guaranteed. 20 6 read-write DBX destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte: 26 1 read-write DHX destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word: 27 1 read-write DAP destination allocated port This bit is used to allocate the master port for the destination transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 30 1 read-write TR2 C0TR2 GPDMA channel 0 transfer register 2 0x44 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per Section 14.3.3. The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (GPDMA_CxCR.EN = 1 and GPDMA_CxTR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 read-write SWREQ software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted. 9 1 read-write DREQ destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note: If the channel x is activated (GPDMA_CxCR.EN is asserted) with SWREQ = 0 and PFREQ = 1 (peripheral hardware request with peripheral flow-control mode), any software assertion to this DREQ bit is ignored: in peripheral flow-control mode, only a peripheral-to-memory transfer is supported. 10 1 read-write BREQ Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: 11 1 read-write PFREQ Hardware request in peripheral flow control mode Important: If a given channel x is not implemented with this feature, this bit is reserved and PFREQ is not present (see Section 14.3.1 for the list of the implemented channels with this feature. If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: Note: In peripheral flow control mode, there are the following restrictions: Note: - no 2D/repeated block support (GPDMA_CxBR1.BRC[10:0] must be set to 0) Note: - the peripheral must be set as the source of the transfer (DREQ = 0). Note: - data packing to a wider destination width is not supported (if destination width > source data width, GPDMA_CxTR1.PAM[1] must be set to 0). Note: - GPDMA_CxBR1.BNDT[15:0] must be programmed as a multiple of the source (peripheral) burst size. 12 1 read-write TRIGM trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (GPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (GPDMA_CxSR.TOF =1 ), and an interrupt is generated if enabled (GPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger. 14 2 read-write TRIGSEL trigger event input selection These bits select the trigger event input of the GPDMA transfer (as per Section 14.3.6), with an active trigger event if TRIGPOL[1:0] different from 00. 16 6 read-write TRIGPOL trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. 24 2 read-write TCEM transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. 30 2 read-write BR1 C0BR1 GPDMA channel 0 block register 1 0x48 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: When configured in packing mode (GPDMA_CxTR1.PAM[1] = 1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 0 16 read-write SAR C0SAR GPDMA channel 0 source address register 0x4C 0x20 0x00000000 0xFFFFFFFF SA source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (GPDMA_CxTR1.SINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.SDW_LOG2[1:0]) after each burst source data, reflecting the next address from which data is read. During the channel activity, this address is updated after each completed source burst, consequently to: the programmed source burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.SINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.SBL_1[5:0] and GPDMA_CxTR1.SDW_LOG2[21:0] the additional source incremented/decremented offset value as programmed by GPDMA_CxBR1.SDEC and GPDMA_CxTR3.SAO[12:0]. once/if completed source block transfer, for a channel x with 2D addressing capability (x = 12 to 15). additional block repeat source incremented/decremented offset value as programmed by GPDMA_CxBR1.BRSDEC and GPDMA_CxBR2.BRSAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source burst (SA[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. 0 32 read-write DAR C0DAR GPDMA channel 0 destination address register 0x50 0x20 0x00000000 0xFFFFFFFF DA destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (GPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.DDW_LOG2[21:0]) after each burst destination data, reflecting the next address from which data is written. During the channel activity, this address is updated after each completed destination burst, consequently to: the programmed destination burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.DINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.DBL_1[5:0] and GPDMA_CxTR1.DDW_LOG2[1:0] the additional destination incremented/decremented offset value as programmed by GPDMA_CxBR1.DDEC and GPDMA_CxTR3.DAO[12:0]. once/if completed destination block transfer, for a channel x with 2D addressing capability (x = 12 to 15), the additional block repeat destination incremented/decremented offset value as programmed by GPDMA_CxBR1.BRDDEC and GPDMA_CxBR2.BRDAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by the GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination burst (DA[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 0 32 read-write LLR C0LLR GPDMA channel 0 linked-list address register 0x7C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (GPDMA_CxTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. 2 14 read-write ULL Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer. 16 1 read-write UDA Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer. 27 1 read-write USA update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer. 28 1 read-write UB1 Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if GPDMA_CxLLR different from 0, the linked-list is not completed. GPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 29 1 read-write UT2 Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer. 30 1 read-write UT1 Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer. 31 1 read-write 4 0x80 12-15 CH2D%s Extended channel cluster 0x650 LBAR C12LBAR GPDMA channel 12 linked-list base address register 0x0 FCR C12FCR GPDMA channel 12 flag clear register 0xC SR C12SR GPDMA channel 12 status register 0x10 CR C12CR GPDMA channel 12 control register 0x14 TR1 C12TR1 GPDMA channel 12 transfer register 1 0x40 TR2 C12TR2 GPDMA channel 12 transfer register 2 0x44 BR1 C12BR1 GPDMA channel 12 alternate block register 1 0x48 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] different from 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: When configured in packing mode (GPDMA_CxTR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 0 16 read-write BRC Block repeat counter This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If GPDMA_CxLLR.UB1 = 1, all GPDMA_CxBR1 fields are updated by the next LLI in the memory. If GPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] different from 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI and data transfer. 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDEC), GPDMA_CxSAR is in the same time also updated by the increment/decrement (depending on SDEC) of the GPDMA_CxTR3.SAO value, as it is done after any programmed burst transfer. 30 1 read-write BRDDEC Block repeat destination address decrement Note: On top of this increment/decrement (depending on BRDDEC), GPDMA_CxDAR is in the same time also updated by the increment/decrement (depending on DDEC) of the GPDMA_CxTR3.DAO value, as it is usually done at the end of each programmed burst transfer. 31 1 read-write SAR C12SAR GPDMA channel 12 source address register 0x4C DAR C12DAR GPDMA channel 12 destination address register 0x50 TR3 C12TR3 GPDMA channel 12 transfer register 3 0x54 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (GPDMA_CxTR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. 0 13 read-write DAO destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (GPDMA_CxTR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 16 13 read-write BR2 C12BR2 GPDMA channel 12 block register 2 0x58 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (GPDMA_CxSAR) at the end of a block transfer. A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: BRSAO[15:0] must be set to 0 in peripheral flow-control mode (if GPDMA_CxTR2.PFREQ = 1). 0 16 read-write BRDAO Block repeated destination address offset For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (GPDMA_CxDAR) at the end of a block transfer. A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: BRDAO[15:0] must be set to 0 in peripheral flow-control mode (if GPDMA_CxTR2.PFREQ = 1). 16 16 read-write LLR C12LLR GPDMA channel 12 alternate linked-list address register 0x7C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (GPDMA_CxTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. 2 14 read-write ULL Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer. 16 1 read-write UB2 Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during the link transfer. 25 1 read-write UT3 Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during the link transfer. 26 1 read-write UDA Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer. 27 1 read-write USA update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer. 28 1 read-write UB1 Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if GPDMA_CxLLR different from 0, the linked-list is not completed. GPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 29 1 read-write UT2 Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer. 30 1 read-write UT1 Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer. 31 1 read-write GPIOA General-purpose I/Os GPIO 0x58020000 0x0 0x30 registers MODER MODER GPIO port mode register 0x0 0x20 0xABFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x64000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 0x00000000 0xFFFF0000 16 0x1 0-15 ID%s Port input data pin %s 0 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 OD%s Port output data pin %s 0 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 BS%s Port x set pin %s 0 1 write-only BitSet Set Sets the corresponding ODx bit 1 16 0x1 0-15 BR%s Port x reset pin %s 16 1 write-only BitReset Reset Resets the corresponding ODx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 AFSEL%s Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: The bitfield is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 AFSEL%s Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: The bitfield is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 4 read-write BRR BRR GPIO port bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 BR%s Port x reset pin %s 0 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 GPIOC General-purpose I/Os GPIO 0x58020800 0x0 0x30 registers MODER MODER GPIO port mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 GPIOD General-purpose I/Os GPIO 0x58020C00 GPIOE General-purpose I/Os GPIO 0x58021000 GPIOF General-purpose I/Os GPIO 0x58021400 GPIOG General-purpose I/Os GPIO 0x58021800 GPIOH General-purpose I/Os GPIO 0x58021C00 GPIOM General-purpose I/Os GPIO 0x58023000 GPION General-purpose I/Os GPIO 0x58023400 GPIOO General-purpose I/Os GPIO 0x58023800 GPIOP GPIOP address block description 0x58023C00 HASH Hash processor HASH 0x48020400 0x0 0x400 registers HASH HASH global interrupt 36 CR CR HASH control register 0x0 0x20 0x00000000 0xFFFFFFFF INIT Initialize message digest calculation Writing this bit to 1 resets the hash processor core, so that the HASH is ready to compute the message digest of a new message. Writing this bit to 0 has no effect. Reading this bit always returns 0. 2 1 read-write DMAE DMA enable After this bit is set, it is cleared by hardware while the last data of the message is written into the hash processor. Setting this bit to 0 while a DMA transfer is ongoing does not abort the current transfer. Instead, the DMA interface of the HASH remains internally enabled until the transfer is completed or INIT is written to 1. Setting INIT bit to 1 does not clear DMAE bit. 3 1 read-write DATATYPE Data type selection This bitfield defines the format of the data entered into the HASH_DIN register: 4 2 read-write MODE Mode selection This bit selects the normal or the keyed HMAC mode for the selected algorithm: This selection is only taken into account when the INIT bit is set. Changing this bit during a computation has no effect. 6 1 read-write NBW Number of words already pushed Refer to NBWP[3:0] bitfield of HASH_SR for a description of NBW[3:0] bitfield. This bit is read-only. 8 4 read-only DINNE DIN not empty Refer to DINNE bit of HASH_SR for a description of DINNE bit. This bit is read-only. 12 1 read-only MDMAT Multiple DMA transfers This bit is set when hashing large files when multiple DMA transfers are needed. 13 1 read-write LKEY Long key selection The application must set this bit if the HMAC key is greater than the block size corresponding to the hash algorithm (see Table 280: Information on supported hash algorithms for details). For example the block size is 64 bytes for SHA2-256. This selection is only taken into account when the INIT and MODE bits are set (HMAC mode selected). Changing this bit during a computation has no effect. 16 1 read-write ALGO Algorithm selection These bits select the hash algorithm: This selection is only taken into account when the INIT bit is set. Changing this bitfield during a computation has no effect. When the ALGO bitfield is updated and INIT bit is set, NBWE in HASH_SR is automatically updated to 0x11. 17 4 read-write DIN DIN HASH data input register 0x4 0x20 0x00000000 0xFFFFFFFF DATAIN Data input Writing this register pushes the current register content into the FIFO, and the register takes the new value presented on the AHB bus. Reading this register returns zeros. 0 32 write-only STR STR HASH start register 0x8 0x20 0x00000000 0xFFFFFFFF NBLW Number of valid bits in the last word When the last word of the message bit string is written to HASH_DIN register, the hash processor takes only the valid bits, specified as below, after internal data swapping: ... The above mechanism is valid only if DCAL = 0. If NBLW bits are written while DCAL is set to 1, the NBLW bitfield remains unchanged. In other words it is not possible to configure NBLW and set DCAL at the same time. Reading NBLW bits returns the last value written to NBLW. 0 5 read-write DCAL Digest calculation Writing this bit to 1 starts the message padding using the previously written value of NBLW, and starts the calculation of the final message digest with all the data words written to the input FIFO since the INIT bit was last written to 1. Reading this bit returns 0. 8 1 read-write 5 0x4 0-4 HRA%s HRA%s HASH digest register alias %s 0xC 0x20 0x00000000 0xFFFFFFFF H Hash data x Refer to Section 34.7.4: HASH digest registers introduction. 0 32 read-only IMR IMR HASH interrupt enable register 0x20 0x20 0x00000000 0xFFFFFFFF DINIE Data input interrupt enable 0 1 read-write DCIE Digest calculation completion interrupt enable 1 1 read-write SR SR HASH status register 0x24 0x20 0x00110001 0xFFFFFFFF DINIS Data input interrupt status This bit is set by hardware when the FIFO is ready to get a new block (16 locations are free). It is cleared by writing it to 0 or by writing the HASH_DIN register. When DINIS = 0, HASH_CSRx registers reads as zero. 0 1 read-write DCIS Digest calculation completion interrupt status This bit is set by hardware when a digest becomes ready (the whole message has been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1 in the HASH_CR register. 1 1 read-write DMAS DMA Status This bit provides information on the DMA interface activity. It is set with DMAE and cleared when DMAE = 0 and no DMA transfer is ongoing. No interrupt is associated with this bit. 2 1 read-only BUSY Busy bit 3 1 read-only NBWP Number of words already pushed This bitfield is the exact number of words in the message that have already been pushed into the FIFO. NBWP is incremented by 1 when a write access is performed to the HASH_DIN register. When a digest calculation starts, NBWP is updated to NBWP- block size (in words), and NBWP goes to zero when the INIT bit is written to 1. 9 5 read-only DINNE DIN not empty This bit is set when the HASH_DIN register holds valid data (that is after being written at least once). It is cleared when either the INIT bit (initialization) or the DCAL bit (completion of the previous message processing) is written to 1. 15 1 read-only NBWE Number of words expected This bitfield reflects the number of words in the message that must be pushed into the FIFO to trigger a partial computation. NBWE is decremented by 1 when a write access is performed to the HASH_DIN register. NBWE is set to the expected block size +1 in words (0x11) when INIT bit is set in HASH_CR. It is set to the expected block size (0x10) when the partial digest calculation ends. 16 5 read-only 103 0x4 0-102 CSR%s CSR%s HASH context swap register %s 0xF8 0x20 0x00000000 0xFFFFFFFF CS Context swap x Refer to Section 34.7.7: HASH context swap registers introduction. 0 32 read-write 16 0x4 0-15 HR%s HR%s HASH digest register %s 0x310 0x20 0x00000000 0xFFFFFFFF H Hash data x Refer to Section 34.7.4: HASH digest registers introduction. 0 32 read-only HPDMA High-performance direct memory access controller HPDMA 0x52000000 0x0 0x1000 registers HPDMA1_CH0 HPDMA1 channel 0 interrupt 64 HPDMA1_CH1 HPDMA1 channel 1 interrupt 65 HPDMA1_CH2 HPDMA1 channel 2 interrupt 66 HPDMA1_CH3 HPDMA1 channel 3 interrupt 67 HPDMA1_CH4 HPDMA1 channel 4 interrupt 68 HPDMA1_CH5 HPDMA1 channel 5 interrupt 69 HPDMA1_CH6 HPDMA1 channel 6 interrupt 70 HPDMA1_CH7 HPDMA1 channel 7 interrupt 71 HPDMA1_CH8 HPDMA1 channel 8 interrupt 141 HPDMA1_CH9 HPDMA1 channel 9 interrupt 142 HPDMA1_CH10 HPDMA1 channel 10 interrupt 143 HPDMA1_CH11 HPDMA1 channel 11 interrupt 144 HPDMA1_CH12 HPDMA1 channel 12 interrupt 145 HPDMA1_CH13 HPDMA1 channel 13 interrupt 146 HPDMA1_CH14 HPDMA1 channel 14 interrupt 147 HPDMA1_CH15 HPDMA1 channel 15 interrupt 148 PRIVCFGR PRIVCFGR HPDMA privileged configuration register 0x4 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 PRIV%s privileged state of channel x 0 1 read-write RCFGLOCKR RCFGLOCKR HPDMA configuration lock register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 LOCK%s lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset This bit is cleared after reset and, once set, it cannot be reset until a global HPDMA reset. 0 1 read-write MISR MISR HPDMA masked interrupt status register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 MIS%s masked interrupt status of channel x 0 1 read-only 12 0x80 0-11 CH%s Channel cluster 0x50 LBAR C0LBAR HPDMA channel 0 linked-list base address register 0x0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write FCR C0FCR HPDMA channel 0 flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only SR C0SR HPDMA channel 0 status register 0x10 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag This idle flag is de-asserted by hardware when the channel is enabled (HPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). 0 1 read-only TCF transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (HPDMA_CxTR2.TCEM[1:0]). 8 1 read-only HTF half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (HPDMA_CxTR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of HPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (HPDMA_CxBR1.BRC[10:0]+1)/2)) has been transferred to the destination. 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only CR C0CR HPDMA channel 0 control register 0x14 0x20 0x00000000 0xFFFFFFFF EN enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, for example if LSM = 1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 read-write RESET reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (HPDMA_CxSR.SUSPF = 1 and HPDMA_CxSR.IDLEF = HPDMA_CxCR.EN = 1) - channel in disabled state (HPDMA_CxSR.IDLEF = 1 and HPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (HPDMA_CxBR1, HPDMA_CxSAR and HPDMA_CxDAR) before enabling again the channel (see the programming sequence in Figure 159). 1 1 write-only SUSP suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel (a channel with an ongoing HPDMA transfer over its master ports). The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in Figure 158. 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by HPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 16 1 read-write LAP linked-list allocated port This bit is used to allocate the master port for the update of the HPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 22 2 read-write TR1 C0TR1 HPDMA channel 0 transfer register 1 0x40 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes if SAP = 1, user setting error reported and no transfer issued Note: A burst with a double-word data width must be allocated to the AXI master port, else a user setting error is reported and none transfer is issued. A source block size must be a multiple of the source data width (HPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. Note: A source burst transfer must have an aligned address with its data width (start address HPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. 0 2 read-write SINC source incrementing burst The source address, pointed by HPDMA_CxSAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1- or 4-Kbyte address boundary on respectively an AHB or an AXI transfer, the HPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. Note: If the burst length exceeds 16 on a AHB transfer, or if the burst on a AXI transfer is both with fixed addressing (SINC=0) and with a burst length which exceeds 16, the HPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with HPDMA re-arbitration between effective and lower singles/bursts, but the data integrity is guaranteed. 4 6 read-write PAM padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else, in the following enumerated values, the condition PAM_1 is when destination data width is higher that source data width, and the condition PAM_2 is when destination data width is higher than source data width. Note: If the transfer from the source peripheral is configured with peripheral flow-control mode (SWREQ = 0 and PFREQ = 1 and DREQ = 0), and if the destination data width > the source data width, packing is not supported. 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word If the source data width is shorter than a word, this bit is ignored. If the source data width is a word or a double-word, and if source bus is AXI (SAP = 0): 13 1 read-write SAP source allocated port This bit is used to allocate the master port for the source transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 14 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes if DAP = 1, user setting error reported and no transfer issued Note: A burst with a double-word data width must be allocated to the AXI master port, else a user setting error is reported and none transfer is issued. Note: A destination burst transfer must have an aligned address with its data width (start address HPDMA_CxDAR[2:0] and address offset HPDMA_CxTR3.DAO[2:0], versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and no transfer is issued. Note: When configured in packing mode (PAM[1] = 1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (see HPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 2 read-write DINC destination incrementing burst The destination address, pointed by HPDMA_CxDAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW_LOG2[1:0]. Note: If a burst transfer crossed a 1- or 4-Kbyte address boundary on respectively an AHB or AXI transfer, the HPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB/AXI protocol. Note: If the burst length exceeds 16 on an AHB transfer, or if the burst on an AXI transfer is both with fixed addressing (DINC = 0) and with a burst length which exceeds 16, the HPDMA modifies and shortens the programmed burst into bursts of lower length, to be compliant with the AHB or AXI protocol. Note: If a burst transfer is of length greater than the FIFO size of the channel x, the HPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with HPDMA re-arbitration between effective and lower singles/bursts, but the data integrity is guaranteed. 20 6 read-write DBX destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte: 26 1 read-write DHX destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word or double-word and if destination bus is AXI (DAP = 0): 27 1 read-write DWX destination word exchange If the destination data size is not a double-word, this bit is ignored. If the destination data size is a double-word and if destination bus is AXI (DAP = 0): 28 1 read-write DAP destination allocated port This bit is used to allocate the master port for the destination transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 30 1 read-write TR2 C0TR2 HPDMA channel 0 transfer register 2 0x44 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection These bits are ignored if channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per Section 27.3.3. The user must not assign a same input hardware request (same REQSEL[4:0] value) to different active HPDMA channels (HPDMA_CxCR.EN = 1 and HPDMA_CxTR2.SWREQ = 0 for these channels). The HPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 5 read-write SWREQ software request This bit is internally taken into account when HPDMA_CxCR.EN is asserted. 9 1 read-write DREQ destination hardware request This bit is ignored if channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note: If the channel x is activated (HPDMA_CxCR.EN is asserted) with SWREQ = 0 and PFREQ = 1 (peripheral hardware request with peripheral flow-control mode), any software assertion to this DREQ bit is ignored: in peripheral flow-control mode, only a peripheral-to-memory transfer is supported. 10 1 read-write BREQ Block hardware request If the channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: 11 1 read-write PFREQ Hardware request in peripheral flow control mode Important: If a given channel x is not implemented with this feature, this bit is reserved and PFREQ is not present (see Section 27.3.5 for the list of the implemented channels with this feature. If the channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: Note: In peripheral flow control mode, there are the following restrictions: Note: - no 2D/repeated block support (HPDMA_CxBR1.BRC[10:0] must be set to 0 if present) Note: - the peripheral must be set as the source of the transfer (DREQ = 0). Note: - data packing to a wider destination width is not supported (if destination width > source data width, HPDMA_CxTR1.PAM[1] must be set to 0). Note: - HPDMA_CxBR1.BNDT[15:0] must be set as a multiple of the source (peripheral) burst size. 12 1 read-write TRIGM trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (HPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, an HPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The HPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the HPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (HPDMA_CxSR.TOF =1 ), and an interrupt is generated if enabled (HPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1/4-Kbyte boundary address crossing maximum burst length vs AHB/AXI protocol): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger. 14 2 read-write TRIGSEL trigger event input selection These bits select the trigger event input of the HPDMA transfer (as per Section 27.3.6), with an active trigger event if TRIGPOL[1:0] different from 00. 16 6 read-write TRIGPOL trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. 24 2 read-write TCEM transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with HPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with HPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with HPDMA_CxBR1.BNDT[15:0] = 0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. 30 2 read-write BR1 C0BR1 HPDMA channel 0 block register 1 0x48 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if HPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if HPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all HPDMA_CxLLR.Uxx = 0 and if HPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if HPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus HPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: When configured in packing mode (HPDMA_CxTR1.PAM[1] = 1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 0 16 read-write SAR C0SAR HPDMA channel 0 source address register 0x4C 0x20 0x00000000 0xFFFFFFFF SA source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (HPDMA_CxTR1.SINC), this field is kept fixed or incremented by the data width (HPDMA_CxTR1.SDW_LOG2[1:0]) after each burst source data, reflecting the next address from which data is read. During the channel activity, this address is updated after each completed source burst, consequently to: the programmed source burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (HPDMA_CxTR1.SINC = 1), then the additional address offset value is the programmed burst size, as defined by HPDMA_CxTR1.SBL_1[5:0] and HPDMA_CxTR1.SDW_LOG2[21:0] the additional source incremented/decremented offset value as programmed by HPDMA_CxBR1.SDEC and HPDMA_CxTR3.SAO[12:0] once/if completed source block transfer, for a channel x with 2D addressing capability (x = 12 to 15). additional block repeat source incremented/decremented offset value as programmed by HPDMA_CxBR1.BRSDEC and HPDMA_CxBR2.BRSAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by HPDMA from the memory, provided the LLI is set with HPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source burst (SA[2:0] versus HPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional HPDMA_CxTR3.SAO[12:0] is not applied. 0 32 read-write DAR C0DAR HPDMA channel 0 destination address register 0x50 0x20 0x00000000 0xFFFFFFFF DA destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (HPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (HPDMA_CxTR1.DDW_LOG2[21:0]) after each burst destination data, reflecting the next address from which data is written. During the channel activity, this address is updated after each completed destination burst, consequently to: the programmed destination burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (HPDMA_CxTR1.DINC = 1), then the additional address offset value is the programmed burst size, as defined by HPDMA_CxTR1.DBL_1[5:0] and HPDMA_CxTR1.DDW_LOG2[1:0] the additional destination incremented/decremented offset value as programmed by HPDMA_CxBR1.DDEC and HPDMA_CxTR3.DAO[12:0] once/if completed destination block transfer, for a channel x with 2D addressing capability (x = 12 to 15), the additional block repeat destination incremented/decremented offset value as programmed by HPDMA_CxBR1.BRDDEC and HPDMA_CxBR2.BRDAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by the HPDMA from the memory, provided the LLI is set with HPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination burst (DA[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 0 32 read-write LLR C0LLR HPDMA channel 0 linked-list address register 0x7C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list HPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR and HPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. 2 14 read-write ULL Update HPDMA_CxLLR register from memory This bit is used to control the update of HPDMA_CxLLR from the memory during the link transfer. 16 1 read-write UDA Update HPDMA_CxDAR register from memory This bit is used to control the update of HPDMA_CxDAR from the memory during the link transfer. 27 1 read-write USA update HPDMA_CxSAR from memory This bit controls the update of HPDMA_CxSAR from the memory during the link transfer. 28 1 read-write UB1 Update HPDMA_CxBR1 from memory This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if HPDMA_CxLLR different from 0, the linked-list is not completed. HPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 29 1 read-write UT2 Update HPDMA_CxTR2 from memory This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer. 30 1 read-write UT1 Update HPDMA_CxTR1 from memory This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer. 31 1 read-write 4 0x80 12-15 CH2D%s Extended channel cluster 0x650 LBAR C12LBAR HPDMA channel 12 linked-list base address register 0x0 FCR C12FCR HPDMA channel 12 flag clear register 0xC SR C12SR HPDMA channel 12 status register 0x10 CR C12CR HPDMA channel 12 control register 0x14 TR1 C12TR1 HPDMA channel 12 transfer register 1 0x40 TR2 C12TR2 HPDMA channel 12 transfer register 2 0x44 BR1 C12BR1 HPDMA channel 12 alternate block register 1 0x48 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if HPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if HPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all HPDMA_CxLLR.Uxx = 0 and if HPDMA_CxLLR.LA[15:0] different from 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if HPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus HPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: When configured in packing mode (HPDMA_CxTR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 0 16 read-write BRC Block repeat counter This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If HPDMA_CxLLR.UB1 = 1, all HPDMA_CxBR1 fields are updated by the next LLI in the memory. If HPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all HPDMA_CxLLR.Uxx = 0 and if HPDMA_CxLLR.LA[15:0] different from 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if HPDMA_CxLLR = 0, this field is kept as zero following the last LLI and data transfer. 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDEC), HPDMA_CxSAR is in the same time also updated by the increment/decrement (depending on SDEC) of the HPDMA_CxTR3.SAO value, as it is done after any programmed burst transfer. 30 1 read-write BRDDEC Block repeat destination address decrement Note: On top of this increment/decrement (depending on BRDDEC), HPDMA_CxDAR is in the same time also updated by the increment/decrement (depending on DDEC) of the HPDMA_CxTR3.DAO value, as it is usually done at the end of each programmed burst transfer. 31 1 read-write SAR C12SAR HPDMA channel 12 source address register 0x4C DAR C12DAR HPDMA channel 12 destination address register 0x50 TR3 C12TR3 HPDMA channel 12 transfer register 3 0x54 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment The source address, pointed by HPDMA_CxSAR, is incremented or decremented (depending on HPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (HPDMA_CxTR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus HPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional HPDMA_CxTR3.SAO[12:0] is not applied. 0 13 read-write DAO destination address offset increment The destination address, pointed by HPDMA_CxDAR, is incremented or decremented (depending on HPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (HPDMA_CxTR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 16 13 read-write BR2 C12BR2 HPDMA channel 12 block register 2 0x58 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on HPDMA_CxBR1.BRSDEC) the current source address (HPDMA_CxSAR) at the end of a block transfer. A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus HPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: BRSAO[15:0] must be set to 0 in peripheral flow-control mode (if HPDMA_CxTR2.PFREQ=1). 0 16 read-write BRDAO Block repeated destination address offset For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on HPDMA_CxBR1.BRDDEC) the current destination address (HPDMA_CxDAR) at the end of a block transfer. A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: BRDAO[15:0] must be set to 0 in peripheral flow-control mode (if HPDMA_CxTR2.PFREQ=1). 16 16 read-write LLR C12LLR HPDMA channel 12 alternate linked-list address register 0x7C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list HPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR and HPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. 2 14 read-write ULL Update HPDMA_CxLLR register from memory This bit is used to control the update of HPDMA_CxLLR from the memory during the link transfer. 16 1 read-write UB2 Update HPDMA_CxBR2 from memory This bit controls the update of HPDMA_CxBR2 from the memory during the link transfer. 25 1 read-write UT3 Update HPDMA_CxTR3 from memory This bit controls the update of HPDMA_CxTR3 from the memory during the link transfer. 26 1 read-write UDA Update HPDMA_CxDAR register from memory This bit is used to control the update of HPDMA_CxDAR from the memory during the link transfer. 27 1 read-write USA update HPDMA_CxSAR from memory This bit controls the update of HPDMA_CxSAR from the memory during the link transfer. 28 1 read-write UB1 Update HPDMA_CxBR1 from memory This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if HPDMA_CxLLR different from 0, the linked-list is not completed. HPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 29 1 read-write UT2 Update HPDMA_CxTR2 from memory This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer. 30 1 read-write UT1 Update HPDMA_CxTR1 from memory This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer. 31 1 read-write ICACHE Texture cache ICACHE 0x52015000 0x0 0x400 registers CR CR ICACHE control register 0x0 0x20 0x00000004 0xFFFFFFFF EN enable 0 1 read-write CACHEINV cache invalidation Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. 1 1 write-only WAYSEL cache associativity mode selection This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). 2 1 read-write HITMEN hit monitor enable 16 1 read-write MISSMEN miss monitor enable 17 1 read-write HITMRST hit monitor reset 18 1 read-write MISSMRST miss monitor reset 19 1 read-write SR SR ICACHE status register 0x4 0x20 0x00000001 0xFFFFFFFF BUSYF busy flag 0 1 read-only BSYENDF busy end flag 1 1 read-only ERRF cache error flag 2 1 read-only IER IER ICACHE interrupt enable register 0x8 0x20 0x00000000 0xFFFFFFFF BSYENDIE interrupt enable on busy end Set by software to enable an interrupt generation at the end of a cache invalidate operation. 1 1 read-write ERRIE interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (cacheable write access) 2 1 read-write FCR FCR ICACHE flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF CBSYENDF clear busy end flag Set by software. 1 1 write-only CERRF clear cache error flag Set by software. 2 1 write-only HMONR HMONR ICACHE hit monitor register 0x10 0x20 0x00000000 0xFFFFFFFF HITMON cache hit monitor counter 0 32 read-only MMONR MMONR ICACHE miss monitor register 0x14 0x20 0x00000000 0xFFFFFFFF MISSMON cache miss monitor counter 0 16 read-only IWDG IWDG register block IWDG 0x58004800 0x0 0x400 registers IWDG Independent watchdog interrupt 3 KR KR IWDG key register 0x0 0x10 0x00000000 0x0000FFFF KEY Key value (write only, read 0x0000) These bits can be used for several functions, depending upon the value written by the application: - 0xAAAA: reloads the RL[11:0] value into the IWDCNT down-counter (watchdog refresh), and write-protects registers. This value must be written by software at regular intervals, otherwise the watchdog generates a reset when the counter reaches 0. - 0x5555: enables write-accesses to the registers. - 0xCCCC: enables the watchdog (except if the hardware watchdog option is selected) and write-protects registers. - values different from 0x5555: write-protects registers. Note that only IWDG_PR, IWDG_RLR, IWDG_EWCR and IWDG_WINR registers have a write-protection mechanism. 0 16 write-only PR PR IWDG prescaler register 0x4 0x10 0x00000000 0x0000FFFF PR Prescaler divider These bits are write access protected, see Section 48.4.6. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the IWDG status register (IWDG_SR) must be reset to be able to change the prescaler divider. Others: divider / 1024 Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG status register (IWDG_SR) is reset. 0 4 read-write RLR RLR IWDG reload register 0x8 0x10 0x00000FFF 0x0000FFFF RL Watchdog counter reload value These bits are write access protected, see Section 48.4.6. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG key register (IWDG_KR). The watchdog counter counts down from this value. The timeout period is a function of this value and the prescaler.clock. It is not recommended to set RL[11:0] to a value lower than 2. The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the RVU bit in the IWDG status register (IWDG_SR) is reset. 0 12 read-write SR SR IWDG status register 0xC 0x10 0x00000000 0x0000FFFF PVU Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to six periods of the IWDG kernel clock iwdg_ker_ck). The prescaler value can be updated only when PVU bit is reset. 0 1 read-only RVU Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to six periods of the IWDG kernel clock iwdg_ker_ck). The reload value can be updated only when RVU bit is reset. 1 1 read-only WVU Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to one period of presc_ck and two periods of the IWDG kernel clock iwdg_ker_ck). The window value can be updated only when WVU bit is reset. This bit is generated only if generic window = 1. 2 1 read-only EWU Watchdog interrupt comparator value update This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the VDD voltage domain (takes up to one period of presc_ck and two periods of the IWDG kernel clock iwdg_ker_ck). The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset. 3 1 read-only ONF Watchdog enable status bit Set to 1 by hardware as soon as the IWDG is started. In software mode, it remains to '1' until the IWDG is reset. In hardware mode, this bit is always set to '1'. 8 1 read-only EWIF Watchdog early interrupt flag This bit is set to 1 by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to 1. 14 1 read-only WINR WINR IWDG window register 0x10 0x10 0x00000FFF 0x0000FFFF WIN Watchdog counter window value These bits are write access protected, see Section 48.4.6.They contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the IWDCNT downcounter must be reloaded when its value is lower than WIN[11:0] + 1 and greater than 1. The WVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG status register (IWDG_SR) is reset. 0 12 read-write EWCR EWCR IWDG early wake-up interrupt register 0x14 0x10 0x00000000 0x0000FFFF EWIT Watchdog counter window value These bits are write access protected (see Section 48.4.6). They are written by software to define at which position of the IWDCNT down-counter the early wake-up interrupt must be generated. The early interrupt is generated when the IWDCNT is lower or equal to EWIT[11:0] - 1. EWIT[11:0] must be bigger than 1. An interrupt is generated only if EWIE = 1. The EWU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. Note: Reading this register returns the Early wake-up comparator value and the Interrupt enable bit from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the EWU bit in the IWDG status register (IWDG_SR) is reset. 0 12 read-write EWIC Watchdog early interrupt acknowledge The software must write a 1 into this bit in order to acknowledge the early wake-up interrupt and to clear the EWIF flag. Writing 0 has not effect, reading this flag returns a 0. 14 1 write-only EWIE Watchdog early interrupt enable Set and reset by software. The EWU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the value of this bit. 15 1 read-write I2C1_I3C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 76 I2C1_ER I2C1 error interrupt 77 I3C1_WKUP I3C wakeup Interrupt through EXTI line 101 I3C1_EV I3C1 event interrupt 89 I3C1_ER I3C1 error interrupt 90 CR1 CR1 I2C control register 1 0x0 0x20 0x00000000 0xFFFFFFFF PE Peripheral enable Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. 0 1 read-write TXIE TX Interrupt enable 1 1 read-write RXIE RX Interrupt enable 2 1 read-write ADDRIE Address match Interrupt enable (slave only) 3 1 read-write NACKIE Not acknowledge received Interrupt enable 4 1 read-write STOPIE Stop detection Interrupt enable 5 1 read-write TCIE Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Note: Transfer Complete (TC) Note: Transfer Complete Reload (TCR) 6 1 read-write ERRIE Error interrupts enable Note: Any of these errors generate an interrupt: Note: Arbitration Loss (ARLO) Note: Bus Error detection (BERR) Note: Overrun/Underrun (OVR) Note: Timeout detection (TIMEOUT) Note: PEC error detection (PECERR) Note: Alert pin event detection (ALERT) 7 1 read-write DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. Note: This filter can only be programmed when the I2C is disabled (PE = 0). 8 4 read-write ANFOFF Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0). 12 1 read-write TXDMAEN DMA transmission requests enable 14 1 read-write RXDMAEN DMA reception requests enable 15 1 read-write SBC Slave byte control This bit is used to enable hardware byte control in slave mode. 16 1 read-write NOSTRETCH Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0). 17 1 read-write WUPEN Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. Note: WUPEN can be set only when DNF = 0000 18 1 read-write GCEN General call enable 19 1 read-write SMBHEN SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 20 1 read-write SMBDEN SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 21 1 read-write ALERTEN SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 22 1 read-write PECEN PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 23 1 read-write FMP Fast-mode Plus 20 mA drive enable 24 1 read-write ADDRACLR Address match flag (ADDR) automatic clear 30 1 read-write STOPFACLR STOP detection flag (STOPF) automatic clear 31 1 read-write CR2 CR2 I2C control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SADD Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed. 0 10 read-write RD_WRN Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed. 10 1 read-write ADD10 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed. 11 1 read-write HEAD10R 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed. 12 1 read-write START Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing 0 to this bit has no effect. Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. Note: This bit has no effect when RELOAD is set. 13 1 read-write STOP Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master mode: Note: Writing 0 to this bit has no effect. 14 1 read-write NACK NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. Note: Writing 0 to this bit has no effect. Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. Note: When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. 15 1 read-write NBYTES Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed. 16 8 read-write RELOAD NBYTES reload mode This bit is set and cleared by software. 24 1 read-write AUTOEND Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set. 25 1 read-write PECBYTE Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. Note: Writing 0 to this bit has no effect. Note: This bit has no effect when RELOAD is set. Note: This bit has no effect is slave mode when SBC=0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 26 1 read-write OAR1 OAR1 I2C own address 1 register 0x8 0x20 0x00000000 0xFFFFFFFF OA1 Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0. 0 10 read-write OA1MODE Own address 1 10-bit mode Note: This bit can be written only when OA1EN=0. 10 1 read-write OA1EN Own address 1 enable 15 1 read-write OAR2 OAR2 I2C own address 2 register 0xC 0x20 0x00000000 0xFFFFFFFF OA2 Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0. 1 7 read-write OA2MSK Own address 2 masks Note: These bits can be written only when OA2EN=0. Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. 8 3 read-write OA2EN Own address 2 enable 15 1 read-write TIMINGR TIMINGR I2C timing register 0x10 0x20 0x00000000 0xFFFFFFFF SCLL SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings. 0 8 read-write SCLH SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing. 8 8 read-write SDADEL Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing. 16 4 read-write SCLDEL Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing. 20 4 read-write PRESC Timing prescaler This field is used to prescale i2c_ker_ck in order to generate the clock period tPRESC used for data setup and hold counters (refer to FMPI2C timings on page 2561) and for SCL high and low level counters (refer to FMPI2C master initialization on page 2584). tPRESC = (PRESC+1) x tI2CCLK 28 4 read-write TIMEOUTR TIMEOUTR I2C timeout register 0x14 0x20 0x00000000 0xFFFFFFFF TIMEOUTA Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0. 0 12 read-write TIDLE Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0. 12 1 read-write TIMOUTEN Clock timeout enable 15 1 read-write TIMEOUTB Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0. 16 12 read-write TEXTEN Extended clock timeout enable 31 1 read-write ISR ISR I2C interrupt and status register 0x18 0x20 0x00000001 0xFFFFFFFF TXE Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE = 0. 0 1 read-write TXIS Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH = 1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1). Note: This bit is cleared by hardware when PE = 0. 1 1 read-write RXNE Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE = 0. 2 1 read-only ADDR Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE = 0. 3 1 read-only NACKF Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE = 0. 4 1 read-only STOPF Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE = 0. 5 1 read-only TC Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE = 0. 6 1 read-only TCR Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE = 0. Note: This flag is only for master mode, or for slave mode when the SBC bit is set. 7 1 read-only BERR Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE = 0. 8 1 read-only ARLO Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE = 0. 9 1 read-only OVR Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE = 0. 10 1 read-only PECERR PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 11 1 read-only TIMEOUT Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 12 1 read-only ALERT SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 13 1 read-only BUSY Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE = 0. 15 1 read-only DIR Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR = 1). 16 1 read-only ADDCODE Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. 17 7 read-only ICR ICR I2C interrupt clear register 0x1C 0x20 0x00000000 0xFFFFFFFF ADDRCF Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. 3 1 write-only NACKCF Not Acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register. 4 1 write-only STOPCF STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. 5 1 write-only BERRCF Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. 8 1 write-only ARLOCF Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. 9 1 write-only OVRCF Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register. 10 1 write-only PECCF PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 11 1 write-only TIMOUTCF Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 12 1 write-only ALERTCF Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 52.3: FMPI2C implementation. 13 1 write-only PECR PECR I2C PEC register 0x20 0x20 0x00000000 0xFFFFFFFF PEC Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE = 0. 0 8 read-only RXDR RXDR I2C receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RXDATA 8-bit receive data Data byte received from the I2C bus 0 8 read-only TXDR TXDR I2C transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TXDATA 8-bit transmit data Data byte to be transmitted to the I2C bus Note: These bits can be written only when TXE = 1. 0 8 read-write I2C2 0x40005800 I2C2_EV I2C2 event interrupt 78 I2C2_ER I2C2 error interrupt 79 I2C3 0x40005C00 I2C3_EV I2C3 event interrupt 80 I2C3_ER I2C3 error interrupt 81 JPEG JPEG codec JPEG 0x52003000 0x0 0x8BC registers JPEG JPEG global interrupt 99 CONFR0 CONFR0 JPEG codec control register 0x0 0x20 0x00000000 0xFFFFFFFF START Start This bit start or stop the encoding or decoding process. Note: Reads always return 0. 0 1 write-only CONFR1 CONFR1 JPEG codec configuration register 1 0x4 0x20 0x00000000 0xFFFFFFFF NF Number of color components This field defines the number of color components minus 1. 0 2 read-write DE Codec operation as coder or decoder This bit selects the code or decode process 3 1 read-write COLSPACE Color space This filed defines the number of quantization tables minus 1 to insert in the output stream. 4 2 read-write NS Number of components for scan This field defines the number of components minus 1 for scan header marker segment. 6 2 read-write HDR Header processing This bit enables the header processing (generation/parsing). 8 1 read-write YSIZE Y Size This field defines the number of lines in source image. 16 16 read-write CONFR2 CONFR2 JPEG codec configuration register 2 0x8 0x20 0x00000000 0xFFFFFFFF NMCU Number of MCUs For encoding: this field defines the number of MCU units minus 1 to encode. For decoding: this field indicates the number of complete MCU units minus 1 to be decoded (this field is updated after the JPEG header parsing). If the decoded image size has not a X or Y size multiple of 8 or 16 (depending on the sub-sampling process), the resulting incomplete or empty MCU must be added to this value to get the total number of MCUs generated. 0 26 read-write CONFR3 CONFR3 JPEG codec configuration register 3 0xC 0x20 0x00000000 0xFFFFFFFF XSIZE X size This field defines the number of pixels per line. 16 16 read-write CONFR4 CONFR4 JPEG codec configuration register 4 0x10 0x20 0x00000000 0xFFFFFFFF HD Huffman DC Selects the Huffman table for encoding DC coefficients. 0 1 read-write HA Huffman AC Selects the Huffman table for encoding AC coefficients. 1 1 read-write QT Quantization table Selects quantization table used for component 0. 2 2 read-write NB Number of blocks Number of data units minus 1 that belong to a particular color in the MCU. 4 4 read-write VSF Vertical sampling factor Vertical sampling factor for component 0. 8 4 read-write HSF Horizontal sampling factor Horizontal sampling factor for component 0. 12 4 read-write CONFR5 CONFR5 JPEG codec configuration register 5 0x14 0x20 0x00000000 0xFFFFFFFF HD Huffman DC Selects the Huffman table for encoding DC coefficients. 0 1 read-write HA Huffman AC Selects the Huffman table for encoding AC coefficients. 1 1 read-write QT Quantization table Selects quantization table used for component 1. 2 2 read-write NB Number of blocks Number of data units minus 1 that belong to a particular color in the MCU. 4 4 read-write VSF Vertical sampling factor Vertical sampling factor for component 1. 8 4 read-write HSF Horizontal sampling factor Horizontal sampling factor for component 1. 12 4 read-write CONFR6 CONFR6 JPEG codec configuration register 6 0x18 0x20 0x00000000 0xFFFFFFFF HD Huffman DC Selects the Huffman table for encoding DC coefficients. 0 1 read-write HA Huffman AC Selects the Huffman table for encoding AC coefficients. 1 1 read-write QT Quantization table Selects quantization table used for component 2. 2 2 read-write NB Number of blocks Number of data units minus 1 that belong to a particular color in the MCU. 4 4 read-write VSF Vertical sampling factor Vertical sampling factor for component 2. 8 4 read-write HSF Horizontal sampling factor Horizontal sampling factor for component 2. 12 4 read-write CONFR7 CONFR7 JPEG codec configuration register 7 0x1C 0x20 0x00000000 0xFFFFFFFF HD Huffman DC Selects the Huffman table for encoding DC coefficients. 0 1 read-write HA Huffman AC Selects the Huffman table for encoding AC coefficients. 1 1 read-write QT Quantization table Selects quantization table used for component 3. 2 2 read-write NB Number of blocks Number of data units minus 1 that belong to a particular color in the MCU. 4 4 read-write VSF Vertical sampling factor Vertical sampling factor for component 3. 8 4 read-write HSF Horizontal sampling factor Horizontal sampling factor for component 3. 12 4 read-write CR CR JPEG control register 0x30 0x20 0x00000000 0xFFFFFFFF JCEN JPEG core enable This bit enables the JPEG codec core. 0 1 read-write IFTIE Input FIFO threshold interrupt enable This bit enables interrupt generation when the input FIFO reaches a threshold. 1 1 read-write IFNFIE Input FIFO not full interrupt enable This bit enables interrupt generation when the input FIFO is not empty. 2 1 read-write OFTIE Output FIFO threshold interrupt enable This bit enables interrupt generation when the output FIFO reaches a threshold. 3 1 read-write OFNEIE Output FIFO not empty interrupt enable This bit enables interrupt generation when the output FIFO is not empty. 4 1 read-write EOCIE End of conversion interrupt enable This bit enables interrupt generation at the end of conversion. 5 1 read-write HPDIE Header parsing done interrupt enable This bit enables interrupt generation upon the completion of the header parsing operation. 6 1 read-write IDMAEN Input DMA enable Enables DMA request generation for the input FIFO. 11 1 read-write ODMAEN Output DMA enable Enables DMA request generation for the output FIFO. 12 1 read-write IFF Input FIFO flush This bit flushes the input FIFO. Note: Reads always return 0. 13 1 write-only OFF Output FIFO flush This bit flushes the output FIFO. Note: Reads always return 0. 14 1 write-only SR SR JPEG status register 0x34 0x20 0x00000006 0xFFFFFFFF IFTF Input FIFO threshold flag This bit flags that the amount of data in the input FIFO is below a threshold. This flag must not be considered when using DMA. 1 1 read-only IFNFF Input FIFO not full flag This bit flags that the input FIFO is not full (data can be written). This flag must not be considered when using DMA. 2 1 read-only OFTF Output FIFO threshold flag This bit flags that the amount of data in the output FIFO reaches or exceeds a threshold. This flag must not be considered when using DMA. 3 1 read-only OFNEF Output FIFO not empty flag This bit flags that data is available in the output FIFO. This flag must not be considered when using DMA. 4 1 read-only EOCF End of conversion flag This bit flags the completion of encode/decode process and data transfer to the output FIFO. 5 1 read-only HPDF Header parsing done flag In decode mode, this bit flags the completion of header parsing and updating internal registers. 6 1 read-only COF Codec operation flag This bit flags code/decode operation in progress. 7 1 read-only CFR CFR JPEG clear flag register 0x38 0x20 0x00000000 0xFFFFFFFF CEOCF Clear end of conversion flag Writing 1 clears the ECF bit of the JPEG_SR register. 5 1 read-write CHPDF Clear header parsing done flag Writing 1 clears the HPDF bit of the JPEG_SR register. 6 1 read-write DIR DIR JPEG data input register 0x40 0x20 0x00000000 0xFFFFFFFF DATAIN Data input FIFO Input FIFO data register 0 32 write-only DOR DOR JPEG data output register 0x44 0x20 0x00000000 0xFFFFFFFF DATAOUT Data output FIFO Output FIFO data register. 0 32 read-only 16 0x4 0-15 QMEM0%s QMEM0_%s JPEG quantization memory 0 0x50 0x20 0x00000000 0x00000000 QCOEF0 Quantization coefficient 0 8-bit quantization coefficient. 0 8 read-write QCOEF1 Quantization coefficient 1 8-bit quantization coefficient. 8 8 read-write QCOEF2 Quantization coefficient 2 8-bit quantization coefficient. 16 8 read-write QCOEF3 Quantization coefficient 3 8-bit quantization coefficient. 24 8 read-write 16 0x4 0-15 QMEM1%s QMEM1_%s JPEG quantization memory 1 0x90 0x20 0x00000000 0x00000000 QCOEF0 Quantization coefficient 0 8-bit quantization coefficient. 0 8 read-write QCOEF1 Quantization coefficient 1 8-bit quantization coefficient. 8 8 read-write QCOEF2 Quantization coefficient 2 8-bit quantization coefficient. 16 8 read-write QCOEF3 Quantization coefficient 3 8-bit quantization coefficient. 24 8 read-write 16 0x4 0-15 QMEM2%s QMEM2_%s JPEG quantization memory 2 0xD0 0x20 0x00000000 0x00000000 QCOEF0 Quantization coefficient 0 8-bit quantization coefficient. 0 8 read-write QCOEF1 Quantization coefficient 1 8-bit quantization coefficient. 8 8 read-write QCOEF2 Quantization coefficient 2 8-bit quantization coefficient. 16 8 read-write QCOEF3 Quantization coefficient 3 8-bit quantization coefficient. 24 8 read-write 16 0x4 0-15 QMEM3%s QMEM3_%s JPEG quantization memory 3 0x110 0x20 0x00000000 0x00000000 QCOEF0 Quantization coefficient 0 8-bit quantization coefficient. 0 8 read-write QCOEF1 Quantization coefficient 1 8-bit quantization coefficient. 8 8 read-write QCOEF2 Quantization coefficient 2 8-bit quantization coefficient. 16 8 read-write QCOEF3 Quantization coefficient 3 8-bit quantization coefficient. 24 8 read-write 4 0x10 0-3 HUFFMIN%s HUFFMIN cluster: 100-bit minimum Huffman value 0x150 HUFFMIN_0 HUFFMIN0_0 Bits 0-31 of the minimum Huffman value 0x0 0x20 0x00000000 0x00000000 DATA0 Minimum Huffman value 100-bit minimum Huffman value used internally by the JPEG decoder. 0 32 read-write HUFFMIN_1 HUFFMIN0_1 Bits 32-63 of the minimum Huffman value 0x4 0x20 0x00000000 0x00000000 DATA0 Minimum Huffman value 100-bit minimum Huffman value used internally by the JPEG decoder. 0 32 read-write HUFFMIN_2 HUFFMIN0_2 Bits 64-95 of the minimum Huffman value 0x8 0x20 0x00000000 0x00000000 DATA0 Minimum Huffman value 100-bit minimum Huffman value used internally by the JPEG decoder. 0 32 read-write HUFFMIN_3 HUFFMIN0_3 Bits 96-99 of the minimum Huffman value 0xC 0x20 0x00000000 0x00000000 DATA0 Minimum Huffman value 100-bit minimum Huffman value used internally by the JPEG decoder. 0 4 read-write 32 0x4 0-31 HUFFBASE%s HUFFBASE%s JPEG Huffman base 0x190 0x20 0x00000000 0x00000000 DATA0 Data 0 Base Huffman value. 0 9 read-write DATA1 Data 1 Base Huffman value. 16 9 read-write 84 0x4 0-83 HUFFSYMB%s HUFFSYMB%s JPEG Huffman symbol 0x210 0x20 0x00000000 0x00000000 DATA0 Data 0 Huffman symbol. 0 8 read-write DATA1 Data 1 Huffman symbol. 8 8 read-write DATA2 Data 2 Huffman symbol. 16 8 read-write DATA3 Data 3 Huffman symbol. 24 8 read-write 103 0x4 0-102 DHTMEM%s DHTMEM%s JPEG DHT memory 0x360 0x20 0x00000000 0x00000000 DATA0 Huffman table data 0 Huffman table data for DHT marker segment generation. 0 8 read-write DATA1 Huffman table data 1 Huffman table data for DHT marker segment generation. 8 8 read-write DATA2 Huffman table data 2 Huffman table data for DHT marker segment generation. 16 8 read-write DATA3 Huffman table data 3 Huffman table data for DHT marker segment generation. 24 8 read-write 88 0x4 0-87 HUFFENC_AC0%s HUFFENC_AC0_%s JPEG encoder, AC Huffman table 0 0x500 0x20 0x00000000 0x00000000 HCODE0 Huffman code 0 8 least significant bits of the Huffman code. If the Huffman code is less than 8 bits long, the unused bits must be 0. 0 8 read-write HLEN0 Huffman length 0 Number of bits in the Huffman code HCODE0 minus 1. 8 4 read-write HCODE1 Huffman code 1 8 least significant bits of the Huffman code. If the Huffman code is less than 8 bits long, the unused bits must be 0. 16 8 read-write HLEN1 Huffman length 1 Number of bits in the Huffman code HCODE1 minus 1. 24 4 read-write 88 0x4 0-87 HUFFENC_AC1%s HUFFENC_AC1_%s JPEG encoder, AC Huffman table 1 HUFFENC_AC0_55 0x5DC 0x20 0x00000000 0x00000000 HCODE0 Huffman code 0 8 least significant bits of the Huffman code. If the Huffman code is less than 8 bits long, the unused bits must be 0. 0 8 read-write HLEN0 Huffman length 0 Number of bits in the Huffman code HCODE0 minus 1. 8 4 read-write HCODE1 Huffman code 1 8 least significant bits of the Huffman code. If the Huffman code is less than 8 bits long, the unused bits must be 0. 16 8 read-write HLEN1 Huffman length 1 Number of bits in the Huffman code HCODE1 minus 1. 24 4 read-write 8 0x4 0-7 HUFFENC_DC0%s HUFFENC_DC0_%s JPEG encoder, DC Huffman table 0 0x7C0 0x20 0x00000000 0x00000000 HCODE0 Huffman code 0 8 least significant bits of the Huffman code. If the Huffman code is less than 8 bits long, the unused bits must be 0. 0 8 read-write HLEN0 Huffman length 0 Number of bits in the Huffman code HCODE0 minus 1. 8 4 read-write HCODE1 Huffman code 1 8 least significant bits of the Huffman code. If the Huffman code is less than 8 bits long, the unused bits must be 0. 16 8 read-write HLEN1 Huffman length 1 Number of bits in the Huffman code HCODE1 minus 1. 24 4 read-write 8 0x4 0-7 HUFFENC_DC1%s HUFFENC_DC1_%s JPEG encoder, DC Huffman table 1 0x89C 0x20 0x00000000 0x00000000 HCODE0 Huffman code 0 8 least significant bits of the Huffman code. If the Huffman code is less than 8 bits long, the unused bits must be 0. 0 8 read-write HLEN0 Huffman length 0 Number of bits in the Huffman code HCODE0 minus 1. 8 4 read-write HCODE1 Huffman code 1 8 least significant bits of the Huffman code. If the Huffman code is less than 8 bits long, the unused bits must be 0. 16 8 read-write HLEN1 Huffman length 1 Number of bits in the Huffman code HCODE1 minus 1. 24 4 read-write LPTIM1 Low power timer LPTIM 0x40002400 0x0 0xC registers LPTIM1 LPTIM1 global interrupt 119 ISR_OUTPUT ISR_OUTPUT LPTIM1 interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF Compare 1 interrupt flag If channel CC1 is configured as output: The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. 0 1 read-only ARRM Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. 1 1 read-only EXTTRIG External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. 2 1 read-only CMP1OK Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. 3 1 read-only ARROK Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. 4 1 read-only UP Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 5 1 read-only DOWN Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 6 1 read-only UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. 7 1 read-only REPOK Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. 8 1 read-only CC2IF Compare 2 interrupt flag If channel CC2 is configured as output: The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 9 1 read-only CMP2OK Compare register 2 update OK CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 19 1 read-only DIEROK Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. 24 1 read-only ISR_INPUT ISR_INPUT LPTIM1 interrupt and status register ISR_OUTPUT 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF capture 1 interrupt flag If channel CC1 is configured as input: CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. 0 1 read-only ARRM Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. 1 1 read-only EXTTRIG External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. 2 1 read-only ARROK Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. 4 1 read-only UP Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 5 1 read-only DOWN Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 6 1 read-only UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. 7 1 read-only REPOK Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. 8 1 read-only CC2IF Capture 2 interrupt flag If channel CC2 is configured as input: CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 9 1 read-only CC1OF Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section 26.3. 12 1 read-only CC2OF Capture 2 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 13 1 read-only DIEROK Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. 24 1 read-only ICR_OUTPUT ICR_OUTPUT LPTIM1 interrupt clear register 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. 0 1 write-only ARRMCF Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register 1 1 write-only EXTTRIGCF External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register 2 1 write-only CMP1OKCF Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. 3 1 write-only ARROKCF Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register 4 1 write-only UPCF Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 5 1 write-only DOWNCF Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 6 1 write-only UECF Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. 7 1 write-only REPOKCF Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. 8 1 write-only CC2CF Capture/compare 2 clear flag Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 9 1 write-only CMP2OKCF Compare register 2 update OK clear flag Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 19 1 write-only DIEROKCF Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. 24 1 write-only ICR_INPUT ICR_INPUT LPTIM1 interrupt clear register ICR_OUTPUT 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. 0 1 write-only ARRMCF Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register 1 1 write-only EXTTRIGCF External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register 2 1 write-only ARROKCF Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register 4 1 write-only UPCF Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 5 1 write-only DOWNCF Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 6 1 write-only UECF Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. 7 1 write-only REPOKCF Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. 8 1 write-only CC2CF Capture/compare 2 clear flag Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 9 1 write-only CC1OCF Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section 26.3. 12 1 write-only CC2OCF Capture/compare 2 over-capture clear flag Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 13 1 write-only DIEROKCF Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. 24 1 write-only DIER_OUTPUT DIER_OUTPUT LPTIM1 interrupt enable register 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write CMP1OKIE Compare register 1 update OK interrupt enable 3 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 5 1 read-write DOWNIE Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 9 1 read-write CMP2OKIE Compare register 2 update OK interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 19 1 read-write UEDE Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section 26.3. 23 1 read-write DIER_INPUT DIER_INPUT LPTIM1 interrupt enable register DIER_OUTPUT 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 5 1 read-write DOWNIE Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 9 1 read-write CC1OIE Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section 26.3. 12 1 read-write CC2OIE Capture/compare 2 over-capture interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 13 1 read-write CC1DE Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section 26.3. 16 1 read-write UEDE Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section 26.3. 23 1 read-write CC2DE Capture/compare 2 DMA request enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section 26.3. 25 1 read-write LPTIM2 Low power timer LPTIM 0x58002400 LPTIM2 LPTIM2 global interrupt 120 LPTIM3 Low power timer LPTIM 0x58002800 LPTIM3 LPTIM3 global interrupt 121 LPTIM4 Low power timer LPTIM 0x58002C00 0x0 0xC registers LPTIM4 LPTIM4 global interrupt 122 ISR ISR LPTIM4 interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. 0 1 read-only ARRM Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. 1 1 read-only EXTTRIG External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. 2 1 read-only CMP1OK Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. 3 1 read-only ARROK Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. 4 1 read-only UP Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3: LPTIM implementation. 5 1 read-only DOWN Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3: LPTIM implementation. 6 1 read-only UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. 7 1 read-only REPOK Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. 8 1 read-only DIEROK Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. 24 1 read-only ICR ICR LPTIM4 interrupt clear register 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. 0 1 write-only ARRMCF Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register 1 1 write-only EXTTRIGCF External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register 2 1 write-only CMP1OKCF Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. 3 1 write-only ARROKCF Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register 4 1 write-only UPCF Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 5 1 write-only DOWNCF Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 6 1 write-only UECF Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. 7 1 write-only REPOKCF Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. 8 1 write-only DIEROKCF Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. 24 1 write-only DIER DIER LPTIM4 interrupt enable register 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write CMP1OKIE Compare register 1 update OK interrupt enable 3 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 5 1 read-write DOWNIE Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3. 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write LPTIM5 Low power timer LPTIM 0x58003000 LPTIM5 LPTIM5 global interrupt 123 LPUART1 Low-power universal asynchronous receiver transmitter LPUART 0x58000C00 0x0 0x30 registers LPUART1 LPUART1 LPUART1 global interrupt 131 CR1 CR1_ENABLED LPUART control register 1 0x0 0x20 0x00000000 0xFFFFFFFF UE LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM LPUART enable in low-power mode When this bit is cleared, the LPUART cannot wake up the MCU from low-power mode. When this bit is set, the LPUART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. 1 1 read-write UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable This bit is set and cleared by software. 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable This bit is set and cleared by software. 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the LPUART is disabled (UE=0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the LPUART is disabled (UE=0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wakeup method This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). This bit can only be written when the LPUART is disabled (UE=0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 DEDT Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 79.4.14: RS232 Hardware flow control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UE=0). 16 5 read-write 0 31 DEAT Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 78.5.21: RS232 Hardware flow control and RS485 Driver Enable. This bitfield can only be written when the LPUART is disabled (UE=0). 21 5 read-write 0 31 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UE=0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable This bit is set and cleared by software. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable This bit is set and cleared by software. 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO Full interrupt enable This bit is set and cleared by software. 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 LPUART control register 2 0x4 0x20 0x00000000 0xFFFFFFFF ADDM7 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the LPUART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 STOP STOP bits These bits are used for programming the stop bits. This bitfield can only be written when the LPUART is disabled (UE=0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop2 2 stop bit 2 SWAP Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the LPUART is disabled (UE=0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the LPUART is disabled (UE=0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ADD Address of the LPUART node These bits give the address of the LPUART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0). 24 8 read-write 0 255 CR3 CR3 LPUART control register 3 0x8 0x20 0x00000000 0xFFFFFFFF EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NE=1 in the LPUART_ISR register). 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 HDSEL Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the LPUART is disabled (UE=0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 DMAR DMA enable receiver This bit is set/reset by software 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter This bit is set/reset by software 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable This bit can only be written when the LPUART is disabled (UE=0). 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable This bit can only be written when the LPUART is disabled (UE=0) 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 OVRDIS Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data. 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA Disable on Reception Error This bit can only be written when the LPUART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the LPUART is disabled (UE=0). 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection This bit can only be written when the LPUART is disabled (UE=0). 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 WUS Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the LPUART is disabled (UE=0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 79.3: LPUART implementation on page 4637. 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 WUFIE Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 79.3: LPUART implementation on page 4637. 22 1 read-write WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 TXFTIE TXFIFO threshold interrupt enable This bit is set and cleared by software. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 RXFTCFG Receive FIFO threshold configuration Remaining combinations: Reserved. 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration Remaining combinations: Reserved. 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR LPUART baud rate register 0xC 0x20 0x00000000 0xFFFFFFFF BRR LPUART baud rate division (LPUARTDIV) 0 20 read-write 0 1048575 RQR RQR LPUART request register 0x18 0x20 0x00000000 0xFFFFFFFF SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request Writing 1 to this bit clears the RXNE flag. This enables discarding the received data without reading it, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR_ENABLED LPUART interrupt and status register 0x1C 0x20 0x008000C0 0xFFFFFFFF PE Parity error This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR. 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the LPUART_CR3 register. Note: This error is associated with the character in the LPUART_RDR. 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Start bit noise detection flag This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: This error is associated with the character in the LPUART_RDR. 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXFNEIE=1 in the LPUART_CR1 register, or EIE = 1 in the LPUART_CR3 register. Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXFNEIE=1 in the LPUART_CR1 register. 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete This bit indicates that the last data written in the LPUART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXFE is set. When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. An interrupt is generated if TCIE=1 in the LPUART_CR1 register. TC bit is cleared by software by writing 1 to the TCCF in the LPUART_ICR register or by writing to the LPUART_TDR register. 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). An interrupt is generated if the TXFNFIE bit =1 in the LPUART_CR1 register. Note: This bit is used during single buffer transmission. 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 CTSIF CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIE=1 in the LPUART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIE=1in the LPUART_CR1 register. 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wakeup from Mute mode This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. 19 1 read-only RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 WUF Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIE=1 in the LPUART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 79.3: LPUART implementation on page 4637. 20 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the LPUART_CR1 register, in order to respect the TE=0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. 22 1 read-only TXFE TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the LPUART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the LPUART_CR1 register. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO Full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the LPUART_RDR register. An interrupt is generated if the RXFFIE bit =1 in the LPUART_CR1 register. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 RXFT RXFIFO threshold flag This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the LPUART_CR3 register. 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the LPUART_CR3 register. 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR LPUART interrupt flag clear register 0x20 0x20 0x00000000 0xFFFFFFFF PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the LPUART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the LPUART_ISR register. 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag Writing 1 to this bit clears the NE flag in the LPUART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag Writing 1 to this bit clears the ORE flag in the LPUART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TCCF Transmission complete clear flag Writing 1 to this bit clears the TC flag in the LPUART_ISR register. 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 CTSCF CTS clear flag Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register. 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 CMCF Character match clear flag Writing 1 to this bit clears the CMF flag in the LPUART_ISR register. 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 WUCF Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 79.3: LPUART implementation on page 4637. 20 1 write-only oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 RDR RDR LPUART receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RDR Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 938). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR LPUART transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TDR Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 938). When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1. 0 9 read-write 0 511 PRESC PRESC LPUART prescaler register 0x2C 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler The LPUART input clock can be divided by a prescaler: Remaining combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. 0 4 read-write PRESCALER Div1 /1 0 Div2 /2 1 Div4 /4 2 Div6 /6 3 Div8 /8 4 Div10 /10 5 Div12 /12 6 Div16 /16 7 Div32 /32 8 Div64 /64 9 Div128 /128 10 Div256 /256 11 LTDC LTDC register block LTDC 0x50001000 0x0 0x148 registers LTDC LCD global interrupt 96 LTDC_ER LCD error interrupt 97 SSCR SSCR LTDC synchronization size configuration register 0x8 0x20 0x00000000 0xFFFFFFFF VSH vertical synchronization height (in units of horizontal scan line) These bits define the vertical Synchronization height minus 1. It represents the number of horizontal synchronization lines. 0 11 read-write 0 2047 HSW horizontal synchronization width (in units of pixel clock period) These bits define the number of Horizontal Synchronization pixel minus 1. 16 12 read-write 0 4095 BPCR BPCR LTDC back porch configuration register 0xC 0x20 0x00000000 0xFFFFFFFF AVBP accumulated Vertical back porch (in units of horizontal scan line) These bits define the accumulated vertical back porch width that includes the vertical synchronization and vertical back porch lines minus 1. The vertical back porch is the number of horizontal scan lines at a start of frame to the start of the first active scan line of the next frame. 0 11 read-write 0 2047 AHBP accumulated horizontal back porch (in units of pixel clock period) These bits define the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1. The horizontal back porch is the period between horizontal synchronization going inactive and the start of the active display part of the next scan line. 16 12 read-write 0 4095 AWCR AWCR LTDC active width configuration register 0x10 0x20 0x00000000 0xFFFFFFFF AAH accumulated active height (in units of horizontal scan line) These bits define the accumulated height which includes the vertical synchronization, vertical back porch and the active height lines minus 1. The active height is the number of active lines in the panel. Refer to device datasheet for maximum active height supported following maximum pixel clock. 0 11 read-write 0 2047 AAW accumulated active width (in units of pixel clock period) These bits define the accumulated active width which includes the horizontal synchronization, horizontal back porch and active pixels minus 1. The active width is the number of pixels in active display area of the panel scan line. Refer to device datasheet for maximum active width supported following maximum pixel clock. 16 12 read-write 0 4095 TWCR TWCR LTDC total width configuration register 0x14 0x20 0x00000000 0xFFFFFFFF TOTALH total height (in units of horizontal scan line) These bits defines the accumulated height which includes the vertical synchronization, vertical back porch, the active height and vertical front porch height lines minus 1. 0 11 read-write 0 2047 TOTALW total width (in units of pixel clock period) These bits defines the accumulated total width which includes the horizontal synchronization, horizontal back porch, active width and horizontal front porch pixels minus 1. 16 12 read-write 0 4095 GCR GCR LTDC global control register 0x18 0x20 0x00002220 0xFFFFFFFF LTDCEN LCD-TFT controller enable This bit is set and cleared by software. 0 1 read-write LTDCEN Disabled LCD-TFT controller disabled 0 Enabled LCD-TFT controller enabled 1 DBW dither blue width These bits return the dither blue bits. 4 3 read-only DGW dither green width These bits return the dither green bits. 8 3 read-only DRW dither red width These bits return the Dither Red Bits. 12 3 read-only DEN dither enable This bit is set and cleared by software. 16 1 read-write DEN Disabled Dither disabled 0 Enabled Dither enabled 1 PCPOL pixel clock polarity This bit is set and cleared by software. 28 1 read-write PCPOL RisingEdge Pixel clock on rising edge 0 FallingEdge Pixel clock on falling edge 1 DEPOL not data enable polarity This bit is set and cleared by software. 29 1 read-write DEPOL ActiveLow Data enable polarity is active low 0 ActiveHigh Data enable polarity is active high 1 VSPOL vertical synchronization polarity This bit is set and cleared by software. 30 1 read-write VSPOL ActiveLow Vertical synchronization polarity is active low 0 ActiveHigh Vertical synchronization polarity is active high 1 HSPOL horizontal synchronization polarity This bit is set and cleared by software. 31 1 read-write HSPOL ActiveLow Horizontal synchronization polarity is active low 0 ActiveHigh Horizontal synchronization polarity is active high 1 SRCR SRCR LTDC shadow reload configuration register 0x24 0x20 0x00000000 0xFFFFFFFF IMR immediate reload This bit is set by software and cleared only by hardware after reload. 0 1 read-write IMR NoEffect This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) 0 Reload The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload 1 VBR vertical blanking reload This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set). 1 1 read-write VBR NoEffect This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) 0 Reload The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). 1 BCCR BCCR LTDC background color configuration register 0x2C 0x20 0x00000000 0xFFFFFFFF BCBLUE background color blue value These bits configure the background blue value. 0 8 read-write 0 255 BCGREEN background color green value These bits configure the background green value. 8 8 read-write 0 255 BCRED background color red value These bits configure the background red value. 16 8 read-write 0 255 IER IER LTDC interrupt enable register 0x34 0x20 0x00000000 0xFFFFFFFF LIE line interrupt enable This bit is set and cleared by software. 0 1 read-write LIE Disabled Line interrupt disabled 0 Enabled Line interrupt enabled 1 FUIE FIFO underrun interrupt enable This bit is set and cleared by software. 1 1 read-write FUIE Disabled FIFO underrun interrupt disabled 0 Enabled FIFO underrun interrupt enabled 1 TERRIE transfer error interrupt enable This bit is set and cleared by software. 2 1 read-write TERRIE Disabled Transfer error interrupt disabled 0 Enabled Transfer error interrupt enabled 1 RRIE register reload interrupt enable This bit is set and cleared by software. 3 1 read-write RRIE Disabled Register reload interrupt disabled 0 Enabled Register reload interrupt enabled 1 ISR ISR LTDC interrupt status register 0x38 0x20 0x00000000 0xFFFFFFFF LIF line interrupt flag 0 1 read-only LIF NotReached Programmed line not reached 0 Reached Line interrupt generated when a programmed line is reached 1 FUIF FIFO underrun interrupt flag 1 1 read-only FUIF NoUnderrun No FIFO underrun 0 Underrun FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO 1 TERRIF transfer error interrupt flag 2 1 read-only TERRIF NoError No transfer error 0 Error Transfer error interrupt generated when a bus error occurs 1 RRIF register reload interrupt flag 3 1 read-only RRIF NoReload No register reload 0 Reload Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) 1 ICR ICR LTDC interrupt clear register 0x3C 0x20 0x00000000 0xFFFFFFFF CLIF clears the line interrupt flag 0 1 write-only oneToClear CLIFW Clear Clears the LIF flag in the ISR register 1 CFUIF clears the FIFO underrun interrupt flag 1 1 write-only oneToClear CFUIFW Clear Clears the FUIF flag in the ISR register 1 CTERRIF clears the transfer error interrupt flag 2 1 write-only oneToClear CTERRIFW Clear Clears the TERRIF flag in the ISR register 1 CRRIF clears register reload interrupt flag 3 1 write-only oneToClear CRRIFW Clear Clears the RRIF flag in the ISR register 1 LIPCR LIPCR LTDC line interrupt position configuration register 0x40 0x20 0x00000000 0xFFFFFFFF LIPOS line interrupt position These bits configure the line interrupt position. 0 11 read-write 0 2047 CPSR CPSR LTDC current position status register 0x44 0x20 0x00000000 0xFFFFFFFF CYPOS current Y position These bits return the current Y position. 0 16 read-only CXPOS current X position These bits return the current X position. 16 16 read-only CDSR CDSR LTDC current display status register 0x48 0x20 0x0000000F 0xFFFFFFFF VDES vertical data enable display status 0 1 read-only VDES NotActive Currently not in vertical Data Enable phase 0 Active Currently in vertical Data Enable phase 1 HDES horizontal data enable display status 1 1 read-only HDES NotActive Currently not in horizontal Data Enable phase 0 Active Currently in horizontal Data Enable phase 1 VSYNCS vertical synchronization display status 2 1 read-only VSYNCS NotActive Currently not in VSYNC phase 0 Active Currently in VSYNC phase 1 HSYNCS horizontal synchronization display status 3 1 read-only HSYNCS NotActive Currently not in HSYNC phase 0 Active Currently in HSYNC phase 1 2 0x80 1-2 LAYER%s Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR 0x84 CR L1CR LTDC layer 1 control register 0x0 0x20 0x00000000 0xFFFFFFFF LEN layer enable This bit is set and cleared by software. 0 1 read-write LEN Disabled Layer disabled 0 Enabled Layer enabled 1 COLKEN color keying enable This bit is set and cleared by software. 1 1 read-write COLKEN Disabled Color keying disabled 0 Enabled Color keying enabled 1 CLUTEN color look-up table enable This bit is set and cleared by software. The CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color look-up table (CLUT) 4 1 read-write CLUTEN Disabled Color look-up table disabled 0 Enabled Color look-up table enabled 1 WHPCR L1WHPCR LTDC layer 1 window horizontal position configuration register 0x4 0x20 0x00000000 0xFFFFFFFF WHSTPOS window horizontal start position These bits configure the first visible pixel of a line of the layer window. WHSTPOS[11:0] must be UNDER OR EQUAL AAW[11:0] bits (programmed in LTDC_AWCR register). 0 12 read-write 0 4095 WHSPPOS window horizontal stop position These bits configure the last visible pixel of a line of the layer window. WHSPPOS[11:0] must be more or equal to AHBP[11:0] bits + 1 (programmed in LTDC_BPCR register). 16 12 read-write 0 4095 WVPCR L1WVPCR LTDC layer 1 window vertical position configuration register 0x8 0x20 0x00000000 0xFFFFFFFF WVSTPOS window vertical start position These bits configure the first visible line of the layer window. WVSTPOS[10:0] must be UNDER OR EQUAL AAH[10:0] bits (programmed in LTDC_AWCR register). 0 11 read-write 0 2047 WVSPPOS window vertical stop position These bits configure the last visible line of the layer window. WVSPPOS[10:0] must be more or equal to AVBP[10:0] bits + 1 (programmed in LTDC_BPCR register). 16 11 read-write 0 2047 CKCR L1CKCR LTDC layer 1 color keying configuration register 0xC 0x20 0x00000000 0xFFFFFFFF CKBLUE color key blue value 0 8 read-write 0 255 CKGREEN color key green value 8 8 read-write 0 255 CKRED color key red value 16 8 read-write 0 255 PFCR L1PFCR LTDC layer 1 pixel format configuration register 0x10 0x20 0x00000000 0xFFFFFFFF PF pixel format These bits configure the pixel format 0 3 read-write PF ARGB8888 ARGB8888 0 RGB888 RGB888 1 RGB565 RGB565 2 ARGB1555 ARGB1555 3 ARGB4444 ARGB4444 4 L8 L8 (8-bit luminance) 5 AL44 AL44 (4-bit alpha, 4-bit luminance) 6 AL88 AL88 (8-bit alpha, 8-bit luminance) 7 CACR L1CACR LTDC layer 1 constant alpha configuration register 0x14 0x20 0x000000FF 0xFFFFFFFF CONSTA constant alpha These bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware. Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. 0 8 read-write 0 255 DCCR L1DCCR LTDC layer 1 default color configuration register 0x18 0x20 0x00000000 0xFFFFFFFF DCBLUE default color blue These bits configure the default blue value. 0 8 read-write 0 255 DCGREEN default color green These bits configure the default green value. 8 8 read-write 0 255 DCRED default color red These bits configure the default red value. 16 8 read-write 0 255 DCALPHA default color alpha These bits configure the default alpha value. 24 8 read-write 0 255 BFCR L1BFCR LTDC layer 1 blending factors configuration register 0x1C 0x20 0x00000607 0xFFFFFFFF BF2 blending factor 2 These bits select the blending factor F2 0 3 read-write BF2 Constant BF2 = 1 - constant alpha 5 Pixel BF2 = 1 - pixel alpha * constant alpha 7 BF1 blending factor 1 These bits select the blending factor F1. 8 3 read-write BF1 Constant BF1 = constant alpha 4 Pixel BF1 = pixel alpha * constant alpha 6 CFBAR L1CFBAR LTDC layer 1 color frame buffer address register 0x28 0x20 0x00000000 0xFFFFFFFF CFBADD color frame buffer start address These bits define the color frame buffer start address. 0 32 read-write 0 4294967295 CFBLR L1CFBLR LTDC layer 1 color frame buffer length register 0x2C 0x20 0x00000000 0xFFFFFFFF CFBLL color frame buffer line length These bits define the length of one line of pixels in bytes + 7. The line length is computed as follows: active high width * number of bytes per pixel + 7. 0 13 read-write 0 8191 CFBP color frame buffer pitch in bytes These bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes. 16 13 read-write 0 8191 CFBLNR L1CFBLNR LTDC layer 1 color frame buffer line number register 0x30 0x20 0x00000000 0xFFFFFFFF CFBLNBR frame buffer line number These bits define the number of lines in the frame buffer that corresponds to the active high width. 0 11 read-write 0 2047 CLUTWR L1CLUTWR LTDC layer 1 CLUT write register 0x40 0x20 0x00000000 0xFFFFFFFF BLUE blue value These bits configure the blue value. 0 8 write-only 0 255 GREEN green value These bits configure the green value. 8 8 write-only 0 255 RED red value These bits configure the red value. 16 8 write-only 0 255 CLUTADD CLUT address These bits configure the CLUT address (color position within the CLUT) of each RGB value. 24 8 write-only 0 255 MCE1 Memory cipher engine MCE 0x5200B800 0x0 0x400 registers MCE1 MCE1 global interrupt 102 CR CR MCE configuration register 0x0 0x20 0x00000000 0xFFFFFFFF GLOCK Global lock Lock the configuration of most MCE registers until next reset. This bit is cleared by default and once set it cannot be reset until MCE reset. 0 1 read-write MKLOCK Master keys lock Lock the master key configurations until next reset. This bit is cleared by default and once set it cannot be reset until MCE reset. Effect of this bit depends on the number of master keys. See Section 35.3: MCE implementation for details. 1 1 read-write SR SR MCE status register 0x4 0x20 0x00000000 0xFFFFFFFF MKVALID Master key valid 0 1 read-only FMKVALID Fast master key valid This bit is reserved when fast master key is not present in the MCE instance. See Section 35.3: MCE implementation for detail. 2 1 read-only ENCDIS encryption disabled This bit is set by hardware when the encryption feature is not functional. When ENCDIS is set application must reset MCE peripheral to be able to use the encryption feature again. 4 1 read-only IASR IASR MCE illegal access status register 0x8 0x20 0x00000000 0xFFFFFFFF CAEF Configuration access error flag This bit is set when an illegal access to any MCE configuration register is detected. Bit is cleared by setting corresponding bit in MCE_IACR register. No additional details on the error is available. 0 1 read-only IAEF Illegal access error flag This bit is set when an illegal access is detected on the system bus. More details on the error can be found in MCE_IAESR and MCE_IADDR registers. This bit is cleared by setting corresponding bit in MCE_IACR register. 1 1 read-only IACR IACR MCE illegal access clear register 0xC 0x20 0x00000000 0xFFFFFFFF CAEF Configuration access error flag clear Set this bit to clear CAEF bit in MCE_IASR register. 0 1 write-only IAEF Illegal access error flag clear Set this bit to clear IAEF bit in MCE_IASR register. Clearing IAEF bit permits to capture new error information in MCE_IAESR and MCE_IADDR registers. Note that clearing this bit does not clear RISAB_IADDR register. 1 1 write-only IAIER IAIER MCE illegal access interrupt enable register 0x10 0x20 0x00000000 0xFFFFFFFF CAEIE Configuration access error interrupt enable 0 1 read-write IAEIE Illegal access error interrupt enable 1 1 read-only PRIVCFGR PRIVCFGR MCE privileged configuration register 0x1C 0x20 0x00000000 0xFFFFFFFF PRIV Privileged configuration 0 1 read-write IAESR IAESR MCE illegal access error status register 0x20 0x20 0x00000000 0xFFFFFFFF IAPRIV Illegal access privilege When IAEF bit is set in MCE_IASR register IAPRIV bit captures the privileged state of the master that issued the illegal access detected on the AXI system bus. 4 1 read-only IANRW Illegal access read/write When IAEF bit is set in MCE_IASR register IANRW bit captures the access type of the illegal access detected. 7 1 read-only IADDR IADDR MCE illegal address register 0x24 0x20 0x00000000 0xFFFFFFFF IADD Illegal address When IAEF bit is set in MCE_IASR register IADD bitfield captures the 32-bit bus address of the erroneous access. Additional information can be found in MCE_IAESR register. 0 32 read-only 4 0x10 1-4 REG%s Region cluster 0x40 REGCR REGCR1 Region configuration register 0x0 0x20 0x00000000 0xFFFFFFFF BREN Base region enable BREN cannot be set if BADDRSTART > BADDREND. 0 1 read-write CTXID Context ID This bitfield defines the cryptographic context used by the cipher engine assigned to this region. If ENC=00 bitfield CTXID is ignored. If BREN is set write to this bitfield is ignored. If ENC=01 the key stored in MCE_CC1KEYR is used by the stream cipher. The nonce in MCE_CC1NRx registers and the version in MCE_CC1CR register are also used. If ENC=01 the key stored in MCE_CC2KEYR is used by the stream cipher. The nonce in MCE_CC2NRx registers and the version in MCE_CC2CR register are also used. 9 2 read-write ENC Encrypted region Those bits are taken into account only if BREN is set and if the corresponding encryption feature is available in the MCE instance (see Section 35.3: MCE implementation). Write to those bits is ignored if BREN is set. 14 2 read-write PRIV Privileged region This bit is taken into account only if BREN is set. 16 1 read-write SADDR SADDR1 Region start address register 0x4 0x20 0x00000000 0xFFFFFFFF BADDSTART Region address start This bitfield defines the absolute start address of the region x on 4 kBytes boundary (inclusive). BREN cannot be set if BADDRSTART > BADDREND. When MCE determines the region, the first 12 bits (LSB) and the last 4 bits (MSB) in this register are ignored, and when this register is accessed in read the 4 MSB bits and the 12 LSB bits return zeros (reference value in MCE). 12 20 read-write EADDR EADDR1 Region end address register 0x8 0x20 0x00000FFF 0xFFFFFFFF BADDEND Region address end This bitfield defines the absolute end address of the region x on 4 kBytes boundary (inclusive). BREN cannot be set if BADDRSTART > BADDREND. When MCE determines the region, the first 12 bits (LSB) and the last 4 bits (MSB) in this register are ignored, and when this register is accessed in read the 4 MSB bits return zeros and the 12 LSB bits return ones (reference value in MCE). 12 20 read-write ATTR ATTR1 Region attribute register 0xC 0x20 0x00000000 0xFFFFFFFF WREN Write enable This bit is taken into account only if BREN is set. 16 1 read-write 4 0x4 0-3 MKEYR%s MKEYR%s MCE master key %s 0x200 0x20 0x00000000 0xFFFFFFFF MKEY0 Master key bit 0 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 0 1 write-only MKEY1 Master key bit 1 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 1 1 write-only MKEY2 Master key bit 2 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 2 1 write-only MKEY3 Master key bit 3 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 3 1 write-only MKEY4 Master key bit 4 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 4 1 write-only MKEY5 Master key bit 5 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 5 1 write-only MKEY6 Master key bit 6 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 6 1 write-only MKEY7 Master key bit 7 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 7 1 write-only MKEY8 Master key bit 8 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 8 1 write-only MKEY9 Master key bit 9 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 9 1 write-only MKEY10 Master key bit 10 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 10 1 write-only MKEY11 Master key bit 11 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 11 1 write-only MKEY12 Master key bit 12 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 12 1 write-only MKEY13 Master key bit 13 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 13 1 write-only MKEY14 Master key bit 14 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 14 1 write-only MKEY15 Master key bit 15 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 15 1 write-only MKEY16 Master key bit 16 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 16 1 write-only MKEY17 Master key bit 17 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 17 1 write-only MKEY18 Master key bit 18 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 18 1 write-only MKEY19 Master key bit 19 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 19 1 write-only MKEY20 Master key bit 20 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 20 1 write-only MKEY21 Master key bit 21 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 21 1 write-only MKEY22 Master key bit 22 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 22 1 write-only MKEY23 Master key bit 23 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 23 1 write-only MKEY24 Master key bit 24 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 24 1 write-only MKEY25 Master key bit 25 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 25 1 write-only MKEY26 Master key bit 26 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 26 1 write-only MKEY27 Master key bit 27 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 27 1 write-only MKEY28 Master key bit 28 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 28 1 write-only MKEY29 Master key bit 29 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 29 1 write-only MKEY30 Master key bit 30 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 30 1 write-only MKEY31 Master key bit 31 This key is used by the MCE block cipher in normal, SCA resistant mode, if CTXID=0x0 in MCE_REGCR register. 31 1 write-only 4 0x4 0-3 FMKEYR%s FMKEYR%s MCE fast master key %s 0x220 0x20 0x00000000 0xFFFFFFFF FMKEY0 Fast master key bit 0 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 0 1 write-only FMKEY1 Fast master key bit 1 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 1 1 write-only FMKEY2 Fast master key bit 2 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 2 1 write-only FMKEY3 Fast master key bit 3 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 3 1 write-only FMKEY4 Fast master key bit 4 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 4 1 write-only FMKEY5 Fast master key bit 5 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 5 1 write-only FMKEY6 Fast master key bit 6 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 6 1 write-only FMKEY7 Fast master key bit 7 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 7 1 write-only FMKEY8 Fast master key bit 8 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 8 1 write-only FMKEY9 Fast master key bit 9 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 9 1 write-only FMKEY10 Fast master key bit 10 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 10 1 write-only FMKEY11 Fast master key bit 11 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 11 1 write-only FMKEY12 Fast master key bit 12 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 12 1 write-only FMKEY13 Fast master key bit 13 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 13 1 write-only FMKEY14 Fast master key bit 14 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 14 1 write-only FMKEY15 Fast master key bit 15 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 15 1 write-only FMKEY16 Fast master key bit 16 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 16 1 write-only FMKEY17 Fast master key bit 17 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 17 1 write-only FMKEY18 Fast master key bit 18 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 18 1 write-only FMKEY19 Fast master key bit 19 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 19 1 write-only FMKEY20 Fast master key bit 20 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 20 1 write-only FMKEY21 Fast master key bit 21 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 21 1 write-only FMKEY22 Fast master key bit 22 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 22 1 write-only FMKEY23 Fast master key bit 23 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 23 1 write-only FMKEY24 Fast master key bit 24 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 24 1 write-only FMKEY25 Fast master key bit 25 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 25 1 write-only FMKEY26 Fast master key bit 26 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 26 1 write-only FMKEY27 Fast master key bit 27 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 27 1 write-only FMKEY28 Fast master key bit 28 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 28 1 write-only FMKEY29 Fast master key bit 29 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 29 1 write-only FMKEY30 Fast master key bit 30 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 30 1 write-only FMKEY31 Fast master key bit 31 This key is used by the MCE block cipher in fast mode, if CTXID=0x0 in MCE_REGCR register. 31 1 write-only 2 0x30 1-2 CC%s Cipher context cluster 0x240 CCCFGR CC1CFGR MCE cipher context 1 configuration register 0x0 0x20 0x00000000 0xFFFFFFFF CCEN Cipher context enable 0 1 read-write CCLOCK Cipher context lock Note: This bit is set once. If this bit is set, it can only be cleared to 0 if MCE is reset. Setting this bit forces KEYLOCK bit to 1. 1 1 read-write KEYLOCK Key lock Note: This bit is set once. If this bit is set, it can only be cleared to 0 if MCE is reset. 2 1 read-write KEYCRC Key CRC When KEYLOCK=0, KEYCRC information is automatically computed by hardware while loading the key of this region in this exact sequence: KEYR0 then KEYR1 then KEYR2 then finally KEYR3 (all written once). A new KEYCRC computation starts as soon as a new valid sequence is initiated. KEYCRC bitfield reads as zero until a valid sequence is completed (after it return the computed CRC value). When GLOCK=1, KEYCRC bitfield always return the computed CRC value until the next reset. CRC computation is an 8-bit checksum using the standard CRC-8-CCITT algorithm X8 + X2 + X + 1 (according the convention). Note: CRC information is updated, and the key is usable by MCE, only after the last bit of the key has been written. When GLOCK=0 any write to MCE_CCxKEYR registers clears KEYCRC in MCE_CCxCFGR, and makes the cipher context key un-usable (bypass mode is selected instead). To be able to use the key again application must perform this sequence: write to KEYR0 then KEYR1 then KEYR2 then finally KEYR3 (all written once). As KEYLOCK=1 all those writes are ignored, so the correct key is used instead. 8 8 read-only VERSION Version This 16-bit bitfield must be correctly initialized before CCEN bit is set. Bitfield usage is defined in Section 35.4.6: MCE stream cipher encryption mode. 16 16 read-write CCNR0 CC1NR0 MCE cipher context 1 nonce register 0 0x4 0x20 0x00000000 0xFFFFFFFF SCNONCE Stream cipher nonce, bits [31:0] This register is used by stream cipher to compute keystream. It must be correctly initialize before CCEN bit is set in MCE_CCzCFGR register. Bitfield usage is defined in Section 35.4.6: MCE stream cipher encryption mode. 0 32 read-write CCNR1 CC1NR1 MCE cipher context 1 nonce register 1 0x8 0x20 0x00000000 0xFFFFFFFF SCNONCE Stream cipher nonce, bits [63:32] Refer to the MCE_CCzNR0 register for description of the SCNONCE[63:0] bitfield. 0 32 read-write CCKEYR0 CC1KEYR0 MCE cipher context 1 key register 0 0xC 0x20 0x00000000 0xFFFFFFFF KEY cipher key, bits [31:0] This register is used by the block or stream cipher of MCE when CTXID = z in encrypted region configuration register. KEY[127:0] must be correctly initialize before CCEN bit is set in MCE_CCzCFGR register. 0 32 write-only CCKEYR1 CC1KEYR1 MCE cipher context 1 key register 1 0x10 0x20 0x00000000 0xFFFFFFFF KEY cipher key, bits [63:32] Refer to the MCE_CCzKEYR0 register for description of the KEY[127:0] bitfield. 0 32 write-only CCKEYR2 CC1KEYR2 MCE cipher context 1 key register 2 0x14 0x20 0x00000000 0xFFFFFFFF KEY cipher key, bits [95:64] Refer to the MCE_CCzKEYR0 register for description of the KEY[127:0] bitfield. 0 32 write-only CCKEYR3 CC1KEYR3 MCE cipher context 1 key register 3 0x18 0x20 0x00000000 0xFFFFFFFF KEY cipher key, bits [127:96] Refer to the MCE_CCzKEYR0 register for description of the KEY[127:0] bitfield. 0 32 write-only MCE2 0x5200BC00 MCE2 MCE2 global interrupt 103 MCE3 0x5200C000 MCE3 MCE3 global interrupt 104 MDIOS Management data input/output MDIOS 0x40009400 0x0 0x400 registers MDIOS MDIOS global interrupt 125 CR CR MDIOS configuration register 0x0 0x20 0x00000000 0xFFFFFFFF EN peripheral enable 0 1 read-write WRIE register write interrupt enable Note: When this bit is set, an interrupt is generated if any of the read flags (WRF[31:0] in the MDIOS_WRFR register) is set. 1 1 read-write RDIE register read interrupt enable Note: When this bit is set, an interrupt is generated if any of the read flags (RDF[31:0] in the MDIOS_RDFR register) is set. 2 1 read-write EIE error interrupt enable Note: When this bit is set, an interrupt is generated if any of the error flags (PERF, SERF, or TERF in the MDIOS_SR register) is set. 3 1 read-write DPC disable preamble check Note: When this bit is set, the application must be sure that no frame is currently in progress when the MDIOS is enabled. Otherwise, the MDIOS can become desynchronized with the master. Note: This bit cannot be changed unless EN = 0 (though it can be changed at the same time that EN is being set). 7 1 read-write PORT_ADDRESS slave address Can be written only when the peripheral is disabled (EN = 0). If the address given by the MDIO master matches PORT_ADRESS[4:0], then the MDIOS services the frame. Otherwise the frame is ignored. 8 5 read-write WRFR WRFR MDIOS write flag register 0x4 0x20 0x00000000 0xFFFFFFFF WRF write flags for MDIOS registers 0 to 31. Each bit is set by hardware when the MDIO master performs a write to the corresponding MDIOS register. An interrupt is generated if WRIE (in MDIOS_CR) is set. Each bit is cleared by software by writing 1 to the corresponding CWRF bit in the MDIOS_CWRFR register. For WRFx: 0 32 read-only CWRFR CWRFR MDIOS clear write flag register 0x8 0x20 0x00000000 0xFFFFFFFF CWRF clear the write flag Writing 1 to CWRFx clears the WRFx bit in the MDIOS_WRF register. 0 32 read-write RDFR RDFR MDIOS read flag register 0xC 0x20 0x00000000 0xFFFFFFFF RDF read flags for MDIOS registers 0 to 31. Each bit is set by hardware when the MDIO master performs a read from the corresponding MDIOS register. An interrupt is generated if RDIE (in MDIOS_CR) is set. Each bit is cleared by software by writing 1 to the corresponding CRDF bit in the MDIOS_CRDFR register. For RDFx: 0 32 read-only CRDFR CRDFR MDIOS clear read flag register 0x10 0x20 0x00000000 0xFFFFFFFF CRDF clear the read flag Writing 1 to CRDFx clears the RDFx bit in the MDIOS_RDF register. 0 32 read-write SR SR MDIOS status register 0x14 0x20 0x00000000 0xFFFFFFFF PERF preamble error flag Note: Writing 1 to CPERF (MDIOS_CLRFR) clears this bit. Note: This bit is not set if DPC (disable preamble check, MDIOS_CR[7]) is set. 0 1 read-only SERF start error flag Note: Writing 1 to CSERF (MDIOS_CLRFR) clears this bit. 1 1 read-only TERF turnaround error flag Note: Writing 1 to CTERF (MDIOS_CLRFR) clears this bit. 2 1 read-only CLRFR CLRFR MDIOS clear flag register 0x18 0x20 0x00000000 0xFFFFFFFF CPERF clear the preamble error flag Writing 1 to this bit clears the PERF flag (in MDIOS_SR). 0 1 read-write CSERF clear the start error flag Writing 1 to this bit clears the SERF flag (in MDIOS_SR). When DPC = 1 (MDIOS_CR[7]), the SERF flag must be cleared only when there is not a frame already in progress. 1 1 read-write CTERF clear the turnaround error flag Writing 1 to this bit clears the TERF flag (in MDIOS_SR). When DPC = 1 (MDIOS_CR[7]), the TERF flag must be cleared only when there is not a frame already in progress. 2 1 read-write DINR0 DINR0 MDIOS input data register 0 0x100 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR1 DINR1 MDIOS input data register 1 0x104 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR2 DINR2 MDIOS input data register 2 0x108 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR3 DINR3 MDIOS input data register 3 0x10C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR4 DINR4 MDIOS input data register 4 0x110 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR5 DINR5 MDIOS input data register 5 0x114 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR6 DINR6 MDIOS input data register 6 0x118 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR7 DINR7 MDIOS input data register 7 0x11C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR8 DINR8 MDIOS input data register 8 0x120 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR9 DINR9 MDIOS input data register 9 0x124 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR10 DINR10 MDIOS input data register 10 0x128 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR11 DINR11 MDIOS input data register 11 0x12C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR12 DINR12 MDIOS input data register 12 0x130 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR13 DINR13 MDIOS input data register 13 0x134 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR14 DINR14 MDIOS input data register 14 0x138 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR15 DINR15 MDIOS input data register 15 0x13C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR16 DINR16 MDIOS input data register 16 0x140 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR17 DINR17 MDIOS input data register 17 0x144 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR18 DINR18 MDIOS input data register 18 0x148 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR19 DINR19 MDIOS input data register 19 0x14C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR20 DINR20 MDIOS input data register 20 0x150 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR21 DINR21 MDIOS input data register 21 0x154 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR22 DINR22 MDIOS input data register 22 0x158 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR23 DINR23 MDIOS input data register 23 0x15C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR24 DINR24 MDIOS input data register 24 0x160 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR25 DINR25 MDIOS input data register 25 0x164 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR26 DINR26 MDIOS input data register 26 0x168 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR27 DINR27 MDIOS input data register 27 0x16C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR28 DINR28 MDIOS input data register 28 0x170 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR29 DINR29 MDIOS input data register 29 0x174 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR30 DINR30 MDIOS input data register 30 0x178 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DINR31 DINR31 MDIOS input data register 31 0x17C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register x. 0 16 read-only DOUTR0 DOUTR0 MDIOS output data register 0 0x180 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR1 DOUTR1 MDIOS output data register 1 0x184 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR2 DOUTR2 MDIOS output data register 2 0x188 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR3 DOUTR3 MDIOS output data register 3 0x18C 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR4 DOUTR4 MDIOS output data register 4 0x190 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR5 DOUTR5 MDIOS output data register 5 0x194 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR6 DOUTR6 MDIOS output data register 6 0x198 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR7 DOUTR7 MDIOS output data register 7 0x19C 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR8 DOUTR8 MDIOS output data register 8 0x1A0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR9 DOUTR9 MDIOS output data register 9 0x1A4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR10 DOUTR10 MDIOS output data register 10 0x1A8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR11 DOUTR11 MDIOS output data register 11 0x1AC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR12 DOUTR12 MDIOS output data register 12 0x1B0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR13 DOUTR13 MDIOS output data register 13 0x1B4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR14 DOUTR14 MDIOS output data register 14 0x1B8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR15 DOUTR15 MDIOS output data register 15 0x1BC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR16 DOUTR16 MDIOS output data register 16 0x1C0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR17 DOUTR17 MDIOS output data register 17 0x1C4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR18 DOUTR18 MDIOS output data register 18 0x1C8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR19 DOUTR19 MDIOS output data register 19 0x1CC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR20 DOUTR20 MDIOS output data register 20 0x1D0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR21 DOUTR21 MDIOS output data register 21 0x1D4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR22 DOUTR22 MDIOS output data register 22 0x1D8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR23 DOUTR23 MDIOS output data register 23 0x1DC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR24 DOUTR24 MDIOS output data register 24 0x1E0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR25 DOUTR25 MDIOS output data register 25 0x1E4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR26 DOUTR26 MDIOS output data register 26 0x1E8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR27 DOUTR27 MDIOS output data register 27 0x1EC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR28 DOUTR28 MDIOS output data register 28 0x1F0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR29 DOUTR29 MDIOS output data register 29 0x1F4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR30 DOUTR30 MDIOS output data register 30 0x1F8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write DOUTR31 DOUTR31 MDIOS output data register 31 0x1FC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register x. 0 16 read-write OTG_HS OTG register block OTG 0x40040000 0x0 0xE08 registers OTG_HS USB OTG HS global interrupt 91 GOTGCTL GOTGCTL OTG control and status register 0x0 0x20 0x00010000 0xFFFFFFFF VBVALOEN VBUS valid override enable. This bit is used to enable/disable the software to override the vbusvalid signal using the VBVALOVAL bit. Note: Only accessible in host mode. 2 1 read-write VBVALOVAL VBUS valid override value. This bit is used to set override value for vbusvalid signal when VBVALOEN bit is set. Note: Only accessible in host mode. 3 1 read-write AVALOEN A-peripheral session valid override enable. This bit is used to enable/disable the software to override the Avalid signal using the AVALOVAL bit. Note: Only accessible in host mode. 4 1 read-write AVALOVAL A-peripheral session valid override value. This bit is used to set override value for Avalid signal when AVALOEN bit is set. Note: Only accessible in host mode. 5 1 read-write BVALOEN B-peripheral session valid override enable. This bit is used to enable/disable the software to override the Bvalid signal using the BVALOVAL bit. 1 Internally Bvalid received from the PHY is overridden with BVALOVAL bit value Note: Only accessible in device mode. 6 1 read-write BVALOVAL B-peripheral session valid override value. This bit is used to set override value for Bvalid signal when BVALOEN bit is set. Note: Only accessible in device mode. 7 1 read-write EHEN Embedded host enable It is used to select between OTG A device state machine and embedded host state machine. 12 1 read-write CIDSTS Connector ID status Indicates the connector ID status on a connect event. Note: Accessible in both device and host modes. 16 1 read-only DBCT Long/short debounce time Indicates the debounce time of a detected connection. Note: Only accessible in host mode. 17 1 read-only ASVLD A-session valid Indicates the host mode transceiver status. Note: Only accessible in host mode. 18 1 read-only BSVLD B-session valid Indicates the device mode transceiver status. In OTG mode, the user can use this bit to determine if the device is connected or disconnected. Note: Only accessible in device mode. 19 1 read-only OTGVER OTG version Selects the OTG revision. 20 1 read-write CURMOD Current mode of operation Indicates the current mode (host or device). 21 1 read-only GOTGINT GOTGINT OTG interrupt register 0x4 0x20 0x00000000 0xFFFFFFFF SEDET Session end detected The core sets this bit to indicate that the level of the voltage on VBUS is no longer valid for a B-Peripheral session when VBUS < 0.8 V. Note: Accessible in both device and host modes. 2 1 read-write ADTOCHG A-device timeout change The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. Note: Accessible in both device and host modes. 18 1 read-write GAHBCFG GAHBCFG OTG AHB configuration register 0x8 0x20 0x00000000 0xFFFFFFFF GINTMSK Global interrupt mask The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bits setting, the interrupt status registers are updated by the core. Note: Accessible in both device and host modes. 0 1 read-write HBSTLEN Burst length/type 0000 Single: Bus transactions use single 32 bit accesses (not recommended) 0001 INCR: Bus transactions use unspecified length accesses (not recommended, uses the INCR AHB bus command) 0011 INCR4: Bus transactions target 4x 32 bit accesses 0101 INCR8: Bus transactions target 8x 32 bit accesses 0111 INCR16: Bus transactions based on 16x 32 bit accesses Others: Reserved 1 4 read-write DMAEN DMA enabled 5 1 read-write TXFELVL Tx FIFO empty level This bit indicates when IN endpoint Transmit FIFO empty interrupt (TXFE in OTG_DIEPINTx) is triggered: This bit indicates when the nonperiodic Tx FIFO empty interrupt (NPTXFE bit in OTG_GINTSTS) is triggered: 7 1 read-write PTXFELVL Periodic Tx FIFO empty level Indicates when the periodic Tx FIFO empty interrupt bit in the OTG_GINTSTS register (PTXFE bit in OTG_GINTSTS) is triggered. Note: Only accessible in host mode. 8 1 read-write GUSBCFG GUSBCFG OTG USB configuration register 0xC 0x20 0x00001400 0xFFFFFFFF TOCAL FS timeout calibration The number of PHY clocks that the application programs in this field is added to the full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the line state condition can vary from one PHY to another. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock is 0.25 bit times. 0 3 read-write TRDT USB turnaround time These bits allows to set the turnaround time in PHY clocks. They must be configured according to Table 683: TRDT values, depending on the application AHB frequency. Higher TRDT values allow stretching the USB response time to IN tokens in order to compensate for longer AHB read access latency to the data FIFO. Note: Only accessible in device mode. 10 4 read-write PHYLPC PHY Low-power clock select This bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48 MHz clock to save power. In 480 MHz mode, the UTMI interface operates at either 60 or 30 MHz, depending on whether the 8- or 16-bit data width is selected. In 48 MHz mode, the UTMI interface operates at 48 MHz in FS and LS modes. 15 1 read-write TSDPS TermSel DLine pulsing selection This bit selects utmi_termselect to drive the data line pulse during SRP (session request protocol). 22 1 read-write FHMOD Force host mode Writing a 1 to this bit, forces the core to host mode irrespective of the OTG_ID input pin. After setting the force bit, the application must wait at least 25 ms before the change takes effect. Note: Accessible in both device and host modes. 29 1 read-write FDMOD Force device mode Writing a 1 to this bit, forces the core to device mode irrespective of the OTG_ID input pin. After setting the force bit, the application must wait at least 25 ms before the change takes effect. Note: Accessible in both device and host modes. 30 1 read-write GRSTCTL GRSTCTL OTG reset register 0x10 0x20 0x80000000 0xFFFFFFFF CSRST Core soft reset Resets the HCLK and PHY clock domains as follows: Clears the interrupts and all the CSR register bits except for the following bits: GATEHCLK bit in OTG_PCGCCTL STPPCLK bit in OTG_PCGCCTL FSLSPCS bits in OTG_HCFG DSPD bit in OTG_DCFG SDIS bit in OTG_DCTL OTG_GCCFG register All module state machines (except for the AHB slave unit) are reset to the Idle state, and all the transmit FIFOs and the receive FIFO are flushed. Any transactions on the AHB Master are terminated as soon as possible, after completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately. The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit has been cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay). The software must also check that bit 31 in this register is set to 1 (AHB Master is Idle) before starting any operation. Typically, the software reset is used during software development and also when the user dynamically changes the PHY selection bits in the above listed USB configuration registers. When the user changes the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper operation. Note: Accessible in both device and host modes. 0 1 read-write PSRST Partial soft reset Resets the internal state machines but keeps the enumeration info. Could be used to recover some specific PHY errors. Note: Accessible in both device and host modes. 1 1 read-write FCRST Host frame counter reset The application writes this bit to reset the (micro-)frame number counter inside the core. When the (micro-)frame counter is reset, the subsequent SOF sent out by the core has a frame number of 0. When application writes '1' to the bit, it might not be able to read back the value as it gets cleared by the core in a few clock cycles. Note: Only accessible in host mode. 2 1 read-write RXFFLSH Rx FIFO flush The application can flush the entire Rx FIFO using this bit, but must first ensure that the core is not in the middle of a transaction. The application must only write to this bit after checking that the core is neither reading from the Rx FIFO nor writing to the Rx FIFO. The application must wait until the bit is cleared before performing any other operations. This bit requires 8 clocks (slowest of PHY or AHB clock) to clear. Note: Accessible in both device and host modes. 4 1 read-write TXFFLSH Tx FIFO flush 5 1 read-write TXFNUM Tx FIFO number This is the FIFO number that must be flushed using the Tx FIFO Flush bit. This field must not be changed until the core clears the Tx FIFO Flush bit. ... Note: Accessible in both device and host modes. 6 5 read-write DMAREQ DMA request signal enabled This bit indicates that the DMA request is in progress. Used for debug. 30 1 read-only AHBIDL AHB master idle Indicates that the AHB master state machine is in the Idle condition. Note: Accessible in both device and host modes. 31 1 read-only GINTSTS_HOST GINTSTS_HOST OTG core interrupt register 0x14 0x20 0x04000020 0xFFFFFFFF CMOD Current mode of operation Indicates the current mode. Note: Accessible in both host and device modes. 0 1 read-only MMIS Mode mismatch interrupt The core sets this bit when the application is trying to access: A host mode register, when the core is operating in device mode A device mode register, when the core is operating in host mode The register access is completed on the AHB with an OKAY response, but is ignored by the core internally and does not affect the operation of the core. Note: Accessible in both host and device modes. 1 1 read-write OTGINT OTG interrupt The core sets this bit to indicate an OTG protocol event. The application must read the OTG interrupt status (OTG_GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_GOTGINT register to clear this bit. Note: Accessible in both host and device modes. 2 1 read-only SOF Start of frame In host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt. In device mode, in the core sets this bit to indicate that an SOF token has been received on the USB. The application can read the OTG_DSTS register to get the current frame number. This interrupt is seen only when the core is operating in FS. Note: This register may return '1' if read immediately after power on reset. If the register bit reads '1' immediately after power on reset it does not indicate that an SOF has been sent (in case of host mode) or SOF has been received (in case of device mode). The read value of this interrupt is valid only after a valid connection between host and device is established. If the bit is set after power on reset the application can clear the bit. Note: Accessible in both host and device modes. 3 1 read-write RXFLVL Rx FIFO non-empty Indicates that there is at least one packet pending to be read from the Rx FIFO. Note: Accessible in both host and device modes. 4 1 read-only NPTXFE Non-periodic Tx FIFO empty This interrupt is asserted when the non-periodic Tx FIFO is either half or completely empty, and there is space for at least one entry to be written to the non-periodic transmit request queue. The half or completely empty status is determined by the non-periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). Note: Accessible in host mode only. 5 1 read-only GINAKEFF Global IN non-periodic NAK effective Indicates that the Set global non-periodic IN NAK bit in the OTG_DCTL register (SGINAK bit in OTG_DCTL), set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing the Clear global non-periodic IN NAK bit in the OTG_DCTL register (CGINAK bit in OTG_DCTL). This interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The STALL bit takes precedence over the NAK bit. Note: Only accessible in device mode. 6 1 read-only GONAKEFF Global OUT NAK effective Indicates that the Set global OUT NAK bit in the OTG_DCTL register (SGONAK bit in OTG_DCTL), set by the application, has taken effect in the core. This bit can be cleared by writing the Clear global OUT NAK bit in the OTG_DCTL register (CGONAK bit in OTG_DCTL). Note: Only accessible in device mode. 7 1 read-only ESUSP Early suspend The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms. Note: Only accessible in device mode. 10 1 read-write USBSUSP USB suspend The core sets this bit to indicate that a suspend was detected on the USB. The core enters the suspended state when there is no activity on the data lines for an extended period of time. Note: Only accessible in device mode. 11 1 read-write USBRST USB reset The core sets this bit to indicate that a reset is detected on the USB. Note: Only accessible in device mode. 12 1 read-write ENUMDNE Enumeration done The core sets this bit to indicate that speed enumeration is complete. The application must read the OTG_DSTS register to obtain the enumerated speed. Note: Only accessible in device mode. 13 1 read-write ISOODRP Isochronous OUT packet dropped interrupt The core sets this bit when it fails to write an isochronous OUT packet into the Rx FIFO because the Rx FIFO does not have enough space to accommodate a maximum size packet for the isochronous OUT endpoint. Note: Only accessible in device mode. 14 1 read-write EOPF End of periodic frame interrupt Indicates that the period specified in the periodic frame interval field of the OTG_DCFG register (PFIVL bit in OTG_DCFG) has been reached in the current frame. Note: Only accessible in device mode. 15 1 read-write IEPINT IN endpoint interrupt The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the IN endpoint on which the interrupt occurred, and then read the corresponding OTG_DIEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DIEPINTx register to clear this bit. Note: Only accessible in device mode. 18 1 read-only OEPINT OUT endpoint interrupt The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding OTG_DOEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DOEPINTx register to clear this bit. Note: Only accessible in device mode. 19 1 read-only IISOIXFR Incomplete isochronous IN transfer The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register. Note: Only accessible in device mode. 20 1 read-write IPXFR Incomplete periodic transfer In host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending, which are scheduled for the current frame. 21 1 read-write DATAFSUSP Data fetch suspended This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or request queue space. This interrupt is used by the application for an endpoint mismatch algorithm. For example, after detecting an endpoint mismatch, the application: Sets a global nonperiodic IN NAK handshake Disables IN endpoints Flushes the FIFO Determines the token sequence from the IN token sequence learning queue Re-enables the endpoints Clears the global nonperiodic IN NAK handshake If the global nonperiodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received: the core generates an IN token received when FIFO empty interrupt. The OTG then sends a NAK response to the host. To avoid this scenario, the application can check the FetSusp interrupt in OTG_GINTSTS, which ensures that the FIFO is full before clearing a global NAK handshake. Alternatively, the application can mask the IN token received when FIFO empty interrupt when clearing a global IN NAK handshake. 22 1 read-write RSTDET Reset detected interrupt In device mode, this interrupt is asserted when a reset is detected on the USB in partial power-down mode when the device is in suspend. Note: Only accessible in device mode. 23 1 read-write HPRTINT Host port interrupt The core sets this bit to indicate a change in port status of one of the OTG_HS controller ports in host mode. The application must read the OTG_HPRT register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_HPRT register to clear this bit. Note: Only accessible in host mode. 24 1 read-only HCINT Host channels interrupt The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the OTG_HAINT register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding OTG_HCINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the OTG_HCINTx register to clear this bit. Note: Only accessible in host mode. 25 1 read-only PTXFE Periodic Tx FIFO empty Asserted when the periodic transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the periodic request queue. The half or completely empty status is determined by the periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (PTXFELVL bit in OTG_GAHBCFG). Note: Only accessible in host mode. 26 1 read-only LPMINT LPM interrupt In device mode, this interrupt is asserted when the device receives an LPM transaction and responds with a non-ERRORed response. In host mode, this interrupt is asserted when the device responds to an LPM transaction with a non-ERRORed response or when the host core has completed LPM transactions for the programmed number of times (RETRYCNT bit in OTG_GLPMCFG). This field is valid only if the LPMEN bit in OTG_GLPMCFG is set to 1. 27 1 read-write CIDSCHG Connector ID status change The core sets this bit when there is a change in connector ID status. Note: Accessible in both device and host modes. 28 1 read-write DISCINT Disconnect detected interrupt Asserted when a device disconnect is detected. Note: Only accessible in host mode. 29 1 read-write SRQINT Session request/new session detected interrupt In host mode, this interrupt is asserted when a session request is detected from the device. In device mode, this interrupt is asserted when VBUS is in the valid range for a B-peripheral device. Accessible in both device and host modes. 30 1 read-write WKUPINT Resume/remote wakeup detected interrupt Wakeup interrupt during suspend(L2) or LPM(L1) state. During suspend(L2): In device mode, this interrupt is asserted when a resume is detected on the USB. In host mode, this interrupt is asserted when a remote wakeup is detected on the USB. During LPM(L1): This interrupt is asserted for either host initiated resume or device initiated remote wakeup on USB. Note: Accessible in both device and host modes. 31 1 read-write GINTSTS_DEVICE GINTSTS_DEVICE OTG core interrupt register GINTSTS_HOST 0x14 0x20 0x04000020 0xFFFFFFFF CMOD Current mode of operation Indicates the current mode. Note: Accessible in both host and device modes. 0 1 read-only MMIS Mode mismatch interrupt The core sets this bit when the application is trying to access: A host mode register, when the core is operating in device mode A device mode register, when the core is operating in host mode The register access is completed on the AHB with an OKAY response, but is ignored by the core internally and does not affect the operation of the core. Note: Accessible in both host and device modes. 1 1 read-write OTGINT OTG interrupt The core sets this bit to indicate an OTG protocol event. The application must read the OTG interrupt status (OTG_GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_GOTGINT register to clear this bit. Note: Accessible in both host and device modes. 2 1 read-only SOF Start of frame In host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt. In device mode, in the core sets this bit to indicate that an SOF token has been received on the USB. The application can read the OTG_DSTS register to get the current frame number. This interrupt is seen only when the core is operating in FS. Note: This register may return '1' if read immediately after power on reset. If the register bit reads '1' immediately after power on reset it does not indicate that an SOF has been sent (in case of host mode) or SOF has been received (in case of device mode). The read value of this interrupt is valid only after a valid connection between host and device is established. If the bit is set after power on reset the application can clear the bit. Note: Accessible in both host and device modes. 3 1 read-write RXFLVL Rx FIFO non-empty Indicates that there is at least one packet pending to be read from the Rx FIFO. Note: Accessible in both host and device modes. 4 1 read-only NPTXFE Non-periodic Tx FIFO empty This interrupt is asserted when the non-periodic Tx FIFO is either half or completely empty, and there is space for at least one entry to be written to the non-periodic transmit request queue. The half or completely empty status is determined by the non-periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). Note: Accessible in host mode only. 5 1 read-only GINAKEFF Global IN non-periodic NAK effective Indicates that the Set global non-periodic IN NAK bit in the OTG_DCTL register (SGINAK bit in OTG_DCTL), set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing the Clear global non-periodic IN NAK bit in the OTG_DCTL register (CGINAK bit in OTG_DCTL). This interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The STALL bit takes precedence over the NAK bit. Note: Only accessible in device mode. 6 1 read-only GONAKEFF Global OUT NAK effective Indicates that the Set global OUT NAK bit in the OTG_DCTL register (SGONAK bit in OTG_DCTL), set by the application, has taken effect in the core. This bit can be cleared by writing the Clear global OUT NAK bit in the OTG_DCTL register (CGONAK bit in OTG_DCTL). Note: Only accessible in device mode. 7 1 read-only ESUSP Early suspend The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms. Note: Only accessible in device mode. 10 1 read-write USBSUSP USB suspend The core sets this bit to indicate that a suspend was detected on the USB. The core enters the suspended state when there is no activity on the data lines for an extended period of time. Note: Only accessible in device mode. 11 1 read-write USBRST USB reset The core sets this bit to indicate that a reset is detected on the USB. Note: Only accessible in device mode. 12 1 read-write ENUMDNE Enumeration done The core sets this bit to indicate that speed enumeration is complete. The application must read the OTG_DSTS register to obtain the enumerated speed. Note: Only accessible in device mode. 13 1 read-write ISOODRP Isochronous OUT packet dropped interrupt The core sets this bit when it fails to write an isochronous OUT packet into the Rx FIFO because the Rx FIFO does not have enough space to accommodate a maximum size packet for the isochronous OUT endpoint. Note: Only accessible in device mode. 14 1 read-write EOPF End of periodic frame interrupt Indicates that the period specified in the periodic frame interval field of the OTG_DCFG register (PFIVL bit in OTG_DCFG) has been reached in the current frame. Note: Only accessible in device mode. 15 1 read-write IEPINT IN endpoint interrupt The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the IN endpoint on which the interrupt occurred, and then read the corresponding OTG_DIEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DIEPINTx register to clear this bit. Note: Only accessible in device mode. 18 1 read-only OEPINT OUT endpoint interrupt The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding OTG_DOEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DOEPINTx register to clear this bit. Note: Only accessible in device mode. 19 1 read-only IISOIXFR Incomplete isochronous IN transfer The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register. Note: Only accessible in device mode. 20 1 read-write INCOMPISOOUT Incomplete isochronous OUT transfer In device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register. 21 1 read-write DATAFSUSP Data fetch suspended This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or request queue space. This interrupt is used by the application for an endpoint mismatch algorithm. For example, after detecting an endpoint mismatch, the application: Sets a global nonperiodic IN NAK handshake Disables IN endpoints Flushes the FIFO Determines the token sequence from the IN token sequence learning queue Re-enables the endpoints Clears the global nonperiodic IN NAK handshake If the global nonperiodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received: the core generates an IN token received when FIFO empty interrupt. The OTG then sends a NAK response to the host. To avoid this scenario, the application can check the FetSusp interrupt in OTG_GINTSTS, which ensures that the FIFO is full before clearing a global NAK handshake. Alternatively, the application can mask the IN token received when FIFO empty interrupt when clearing a global IN NAK handshake. 22 1 read-write RSTDET Reset detected interrupt In device mode, this interrupt is asserted when a reset is detected on the USB in partial power-down mode when the device is in suspend. Note: Only accessible in device mode. 23 1 read-write HPRTINT Host port interrupt The core sets this bit to indicate a change in port status of one of the OTG_HS controller ports in host mode. The application must read the OTG_HPRT register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_HPRT register to clear this bit. Note: Only accessible in host mode. 24 1 read-only HCINT Host channels interrupt The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the OTG_HAINT register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding OTG_HCINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the OTG_HCINTx register to clear this bit. Note: Only accessible in host mode. 25 1 read-only PTXFE Periodic Tx FIFO empty Asserted when the periodic transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the periodic request queue. The half or completely empty status is determined by the periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (PTXFELVL bit in OTG_GAHBCFG). Note: Only accessible in host mode. 26 1 read-only LPMINT LPM interrupt In device mode, this interrupt is asserted when the device receives an LPM transaction and responds with a non-ERRORed response. In host mode, this interrupt is asserted when the device responds to an LPM transaction with a non-ERRORed response or when the host core has completed LPM transactions for the programmed number of times (RETRYCNT bit in OTG_GLPMCFG). This field is valid only if the LPMEN bit in OTG_GLPMCFG is set to 1. 27 1 read-write CIDSCHG Connector ID status change The core sets this bit when there is a change in connector ID status. Note: Accessible in both device and host modes. 28 1 read-write DISCINT Disconnect detected interrupt Asserted when a device disconnect is detected. Note: Only accessible in host mode. 29 1 read-write SRQINT Session request/new session detected interrupt In host mode, this interrupt is asserted when a session request is detected from the device. In device mode, this interrupt is asserted when VBUS is in the valid range for a B-peripheral device. Accessible in both device and host modes. 30 1 read-write WKUPINT Resume/remote wakeup detected interrupt Wakeup interrupt during suspend(L2) or LPM(L1) state. During suspend(L2): In device mode, this interrupt is asserted when a resume is detected on the USB. In host mode, this interrupt is asserted when a remote wakeup is detected on the USB. During LPM(L1): This interrupt is asserted for either host initiated resume or device initiated remote wakeup on USB. Note: Accessible in both device and host modes. 31 1 read-write GINTMSK_HOST GINTMSK_HOST OTG interrupt mask register 0x18 0x20 0x00000000 0xFFFFFFFF MMISM Mode mismatch interrupt mask 1 1 read-write OTGINT OTG interrupt mask 2 1 read-write SOFM Start of frame mask 3 1 read-write RXFLVLM Receive FIFO non-empty mask 4 1 read-write NPTXFEM Non-periodic Tx FIFO empty mask 5 1 read-write IPXFRM Incomplete periodic transfer mask 21 1 read-write PRTIM Host port interrupt mask 24 1 read-only HCIM Host channels interrupt mask 25 1 read-write PTXFEM Periodic Tx FIFO empty mask 26 1 read-write LPMINTM LPM interrupt mask 27 1 read-write CIDSCHGM Connector ID status change mask 28 1 read-write DISCINT Disconnect detected interrupt mask 29 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write WUIM Resume/remote wakeup detected interrupt mask 31 1 read-write GINTMSK_DEVICE GINTMSK_DEVICE OTG interrupt mask register GINTMSK_HOST 0x18 0x20 0x00000000 0xFFFFFFFF MMISM Mode mismatch interrupt mask 1 1 read-write OTGINT OTG interrupt mask 2 1 read-write SOFM Start of frame mask 3 1 read-write RXFLVLM Receive FIFO non-empty mask 4 1 read-write GINAKEFFM Global non-periodic IN NAK effective mask 6 1 read-write GONAKEFFM Global OUT NAK effective mask 7 1 read-write ESUSPM Early suspend mask 10 1 read-write USBSUSPM USB suspend mask 11 1 read-write USBRST USB reset mask 12 1 read-write ENUMDNEM Enumeration done mask 13 1 read-write ISOODRPM Isochronous OUT packet dropped interrupt mask 14 1 read-write EOPFM End of periodic frame interrupt mask 15 1 read-write IEPINT IN endpoints interrupt mask 18 1 read-write OEPINT OUT endpoints interrupt mask 19 1 read-write IISOIXFRM Incomplete isochronous IN transfer mask 20 1 read-write IISOOXFRM Incomplete isochronous OUT transfer mask 21 1 read-write FSUSPM Data fetch suspended mask 22 1 read-write RSTDETM Reset detected interrupt mask 23 1 read-write LPMINTM LPM interrupt mask 27 1 read-write CIDSCHGM Connector ID status change mask 28 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write WUIM Resume/remote wakeup detected interrupt mask 31 1 read-write GRXSTSR_DEVICE GRXSTSR_DEVICE OTG receive status debug read register 0x1C 0x20 0x00000000 0xFFFFFFFF EPNUM Endpoint number Indicates the endpoint number to which the current received packet belongs. 0 4 read-only BCNT Byte count Indicates the byte count of the received data packet. 4 11 read-only DPID Data PID Indicates the data PID of the received OUT data packet 15 2 read-only PKTSTS Packet status Indicates the status of the received packet Others: Reserved 17 4 read-only FRMNUM Frame number This is the least significant 4 bits of the frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. 21 4 read-only STSPHST Status phase start Indicates the start of the status phase for a control write transfer. This bit is set along with the OUT transfer completed PKTSTS pattern. 27 1 read-only GRXSTSR_HOST GRXSTSR_HOST OTG receive status debug read register GRXSTSR_DEVICE 0x1C 0x20 0x00000000 0xFFFFFFFF CHNUM Channel number Indicates the channel number to which the current received packet belongs. 0 4 read-only BCNT Byte count Indicates the byte count of the received IN data packet. 4 11 read-only DPID Data PID Indicates the data PID of the received packet 15 2 read-only PKTSTS Packet status Indicates the status of the received packet Others: Reserved 17 4 read-only GRXSTSP_DEVICE GRXSTSP_DEVICE OTG status read and pop registers 0x20 0x20 0x00000000 0xFFFFFFFF EPNUM Endpoint number Indicates the endpoint number to which the current received packet belongs. 0 4 read-only BCNT Byte count Indicates the byte count of the received data packet. 4 11 read-only DPID Data PID Indicates the data PID of the received OUT data packet 15 2 read-only PKTSTS Packet status Indicates the status of the received packet Others: Reserved 17 4 read-only FRMNUM Frame number This is the least significant 4 bits of the frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. 21 4 read-only STSPHST Status phase start Indicates the start of the status phase for a control write transfer. This bit is set along with the OUT transfer completed PKTSTS pattern. 27 1 read-only GRXSTSP_HOST GRXSTSP_HOST OTG status read and pop registers GRXSTSP_DEVICE 0x20 0x20 0x00000000 0xFFFFFFFF CHNUM Channel number Indicates the channel number to which the current received packet belongs. 0 4 read-only BCNT Byte count Indicates the byte count of the received IN data packet. 4 11 read-only DPID Data PID Indicates the data PID of the received packet 15 2 read-only PKTSTS Packet status Indicates the status of the received packet Others: Reserved 17 4 read-only GRXFSIZ GRXFSIZ OTG receive FIFO size register 0x24 0x20 0x00000400 0xFFFFFFFF RXFD Rx FIFO depth This value is in terms of 32-bit words. Maximum value is 1024 Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. 0 16 read-write HNPTXFSIZ_HOST HNPTXFSIZ_HOST OTG host non-periodic transmit FIFO size register [alternate] 0x28 0x20 0x02000200 0xFFFFFFFF NPTXFSA Non-periodic transmit RAM start address This field configures the memory start address for non-periodic transmit FIFO RAM. 0 16 read-write NPTXFD Non-periodic Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. 16 16 read-write HNPTXFSIZ_DEVICE HNPTXFSIZ_DEVICE OTG host non-periodic transmit FIFO size register [alternate] HNPTXFSIZ_HOST 0x28 0x20 0x02000200 0xFFFFFFFF TX0FSA Endpoint 0 transmit RAM start address This field configures the memory start address for the endpoint 0 transmit FIFO RAM. 0 16 read-write TX0FD Endpoint 0 Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. 16 16 read-write HNPTXSTS HNPTXSTS OTG non-periodic transmit FIFO/queue status register 0x2C 0x20 0x00080400 0xFFFFFFFF NPTXFSAV Non-periodic Tx FIFO space available Indicates the amount of free space available in the non-periodic Tx FIFO. Values are in terms of 32-bit words. n: n words available (where 0 UNDER OR EQUAL n UNDER OR EQUAL 512) Others: Reserved 0 16 read-only NPTQXSAV Non-periodic transmit request queue space available Indicates the amount of free space available in the non-periodic transmit request queue. This queue holds both IN and OUT requests. n: n locations available (0 UNDER OR EQUAL n UNDER OR EQUAL 8) Others: Reserved 16 8 read-only NPTXQTOP Top of the non-periodic transmit request queue Entry in the non-periodic Tx request queue that is currently being processed by the MAC. Bits 30:27: Channel/endpoint number Bits 26:25: XXXX00X: IN/OUT token XXXX01X: Zero-length transmit packet (device IN/host OUT) XXXX11X: Channel halt command Bit 24: Terminate (last entry for selected channel/endpoint) 24 7 read-only GCCFG GCCFG OTG general core configuration register 0x38 0x20 0x00000000 0xFFFF0000 CHGDET Charger detection, result of the current mode (primary or secondary). 0 1 read-only FSVPLUS Single-Ended DP indicator This bit gives the voltage level on DP (also result of the comparison with VLGC threshold as defined in BC v1.2 standard). 1 1 read-only FSVMINUS Single-Ended DM indicator This bit gives the voltage level on DM (also result of the comparison with VLGC threshold as defined in BC v1.2 standard). 2 1 read-only SESSVLD VBUS session indicator Indicates if VBUS is above VBUS session threshold. 3 1 read-only HCDPEN Host CDP behavior enable 16 1 read-write HCDPDETEN Host CDP port voltage detector enable on DP 17 1 read-write HVDMSRCEN Host CDP port Voltage source enable on DM 18 1 read-write DCDEN Data Contact Detection enable 19 1 read-write PDEN Primary detection enable 20 1 read-write VBDEN VBUS detection enable Enables VBUS Sensing Comparators in order to detect VBUS presence and/or perform OTG operation. 21 1 read-write SDEN Secondary detection enable 22 1 read-write VBVALOVAL Software override value of the VBUS B-session detection 23 1 read-write VBVALOVEN Enables a software override of the VBUS B-session detection. 24 1 read-write FORCEHOSTPD Force host mode pull-downs If the ID pin functions are enabled, the host mode pull-downs on DP and DM activate automatically. However, whenever that is not the case, yet host mode is required, this bit must be used to force the pull-downs active. 25 1 read-write CID CID OTG core ID register 0x3C 0x20 0x00005000 0xFFFFFFFF PRODUCT_ID Product ID field Application-programmable ID field. 0 32 read-write GLPMCFG GLPMCFG OTG core LPM configuration register 0x54 0x20 0x00000000 0xFFFFFFFF LPMEN LPM support enable The application uses this bit to control the OTG_HS core LPM capabilities. If the core operates as a non-LPM-capable host, it cannot request the connected device or hub to activate LPM mode. If the core operates as a non-LPM-capable device, it cannot respond to any LPM transactions. 0 1 read-write LPMACK LPM token acknowledge enable Handshake response to LPM token preprogrammed by device application software. Even though ACK is preprogrammed, the core device responds with ACK only on successful LPM transaction. The LPM transaction is successful if: No PID/CRC5 errors in either EXT token or LPM token (else ERROR) Valid bLinkState = 0001B (L1) received in LPM transaction (else STALL) No data pending in transmit queue (else NYET). The preprogrammed software bit is over-ridden for response to LPM token when: The received bLinkState is not L1 (STALL response), or An error is detected in either of the LPM token packets because of corruption (ERROR response). Note: Accessible only in device mode. 1 1 read-write BESL Best effort service latency Host mode 2 4 read-write REMWAKE bRemoteWake value Host mode: The value of remote wake up to be sent in the wIndex field of LPM transaction. Device mode (read-only): This field is updated with the received LPM token bRemoteWake bmAttribute when an ACK, NYET, or STALL response is sent to an LPM transaction. 6 1 read-write L1SSEN L1 Shallow Sleep enable Enables suspending the PHY in L1 Sleep mode. For maximum power saving during L1 Sleep mode, this bit should be set to '1' by application SW in all the cases. 7 1 read-write BESLTHRS BESL threshold 8 4 read-write L1DSEN L1 deep sleep enable Enables suspending the PHY in L1 Sleep mode. For maximum power saving during L1 Sleep mode, this bit should be set to '1' by application SW in all the cases. 12 1 read-write LPMRSP LPM response Device mode: The response of the core to LPM transaction received is reflected in these two bits. Host mode: Handshake response received from local device for LPM transaction 13 2 read-only SLPSTS Port sleep status Device mode: This bit is set as long as a Sleep condition is present on the USB bus. The core enters the Sleep state when an ACK response is sent to an LPM transaction and the TL1TokenRetry timer has expired. To stop the PHY clock, the application must set the STPPCLK bit in OTG_PCGCCTL, which asserts the PHY suspend input signal. The application must rely on SLPSTS and not ACK in LPMRSP to confirm transition into sleep. The core comes out of sleep: When there is any activity on the USB linestate When the application writes to the RWUSIG bit in OTG_DCTL or when the application resets or soft-disconnects the device. Host mode: The host transitions to Sleep (L1) state as a side-effect of a successful LPM transaction by the core to the local port with ACK response from the device. The read value of this bit reflects the current Sleep status of the port. The core clears this bit after: The core detects a remote L1 wakeup signal, The application sets the PRST bit or the PRES bit in the OTG_HPRT register, or The application sets the L1Resume/ remote wakeup detected interrupt bit or disconnect detected interrupt bit in the core interrupt register (WKUPINT or DISCINT bit in OTG_GINTSTS, respectively). 15 1 read-only L1RSMOK Sleep state resume OK 16 1 read-only LPMCHIDX LPM Channel Index The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device. Based on the LPM channel index, the core automatically inserts the device address and endpoint number programmed in the corresponding channel into the LPM transaction. Note: Accessible only in host mode. 17 4 read-write LPMRCNT LPM retry count When the device gives an ERROR response, this is the number of additional LPM retries that the host performs until a valid device response (STALL, NYET, or ACK) is received. Note: Accessible only in host mode. 21 3 read-write SNDLPM Send LPM transaction When the application software sets this bit, an LPM transaction containing two tokens, EXT and LPM is sent. The hardware clears this bit once a valid response (STALL, NYET, or ACK) is received from the device or the core has finished transmitting the programmed number of LPM retries. Note: This bit must be set only when the host is connected to a local port. Note: Accessible only in host mode. 24 1 read-write LPMRCNTSTS LPM retry count status Number of LPM host retries still remaining to be transmitted for the current LPM sequence. Note: Accessible only in host mode. 25 3 read-only ENBESL Enable best effort service latency This bit enables the BESL feature as defined in the LPM errata: USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification, July 16, 2007 Errata for USB 2.0 ECN: Link Power Management (LPM) - 7/2007 Note: Only the updated behavior (described in LPM Errata) is considered in this document and so the ENBESL bit should be set to '1' by application SW. 28 1 read-write HPTXFSIZ HPTXFSIZ OTG host periodic transmit FIFO size register 0x100 0x20 0x04000800 0xFFFFFFFF PTXSA Host periodic Tx FIFO start address This field configures the memory start address for periodic transmit FIFO RAM. 0 16 read-write PTXFSIZ Host periodic Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 16 16 read-write DIEPTXF1 DIEPTXF1 OTG device IN endpoint transmit FIFO 1 size register 0x104 0x20 0x02000400 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 16 16 read-write DIEPTXF2 DIEPTXF2 OTG device IN endpoint transmit FIFO 2 size register 0x108 0x20 0x02000600 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 16 16 read-write DIEPTXF3 DIEPTXF3 OTG device IN endpoint transmit FIFO 3 size register 0x10C 0x20 0x02000800 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 16 16 read-write DIEPTXF4 DIEPTXF4 OTG device IN endpoint transmit FIFO 4 size register 0x110 0x20 0x02000A00 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 16 16 read-write DIEPTXF5 DIEPTXF5 OTG device IN endpoint transmit FIFO 5 size register 0x114 0x20 0x02000C00 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 16 16 read-write DIEPTXF6 DIEPTXF6 OTG device IN endpoint transmit FIFO 6 size register 0x118 0x20 0x02000E00 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 16 16 read-write DIEPTXF7 DIEPTXF7 OTG device IN endpoint transmit FIFO 7 size register 0x11C 0x20 0x02001000 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 16 16 read-write DIEPTXF8 DIEPTXF8 OTG device IN endpoint transmit FIFO 8 size register 0x120 0x20 0x02001200 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 16 16 read-write HCFG HCFG OTG host configuration register 0x400 0x20 0x00000000 0xFFFFFFFF FSLSPCS FS/LS PHY clock select Others: Reserved Note: The FSLSPCS must be set on a connection event according to the speed of the connected device (after changing this bit, a software reset must be performed). 0 2 read-write FSLSS FS- and LS-only support The application uses this bit to control the cores enumeration speed. Using this bit, the application can make the core enumerate as an FS host, even if the connected device supports HS traffic. Do not make changes to this field after initial programming. 2 1 read-only HFIR HFIR OTG host frame interval register 0x404 0x20 0x0000EA60 0xFFFFFFFF FRIVL Frame interval 0 16 read-write RLDCTRL Reload control This bit allows dynamic reloading of the HFIR register during run time. This bit needs to be programmed during initial configuration and its value must not be changed during run time. RLDCTRL = 0 is not recommended. 16 1 read-write HFNUM HFNUM OTG host frame number/frame time remaining register 0x408 0x20 0x00003FFF 0xFFFFFFFF FRNUM Frame number This field increments when a new SOF is transmitted on the USB, and is cleared to 0 when it reaches 0x3FFF. 0 16 read-only FTREM Frame time remaining Indicates the amount of time remaining in the current frame, in terms of PHY clocks. This field decrements on each PHY clock. When it reaches zero, this field is reloaded with the value in the Frame interval register and a new SOF is transmitted on the USB. 16 16 read-only HPTXSTS HPTXSTS OTG_Host periodic transmit FIFO/queue status register 0x410 0x20 0x00080100 0xFFFFFFFF PTXFSAVL Periodic transmit data FIFO space available Indicates the number of free locations available to be written to in the periodic Tx FIFO. Values are in terms of 32-bit words n: n words available (where 0 UNDER OR EQUAL n UNDER OR EQUAL PTXFD) Others: Reserved 0 16 read-only PTXQSAV Periodic transmit request queue space available Indicates the number of free locations available to be written in the periodic transmit request queue. This queue holds both IN and OUT requests. n: n locations available (0 UNDER OR EQUAL n UNDER OR EQUAL 8) Others: Reserved 16 8 read-only PTXQTOP Top of the periodic transmit request queue This indicates the entry in the periodic Tx request queue that is currently being processed by the MAC. This register is used for debugging. Bit 31: Odd/Even frame 0XXXXXXX: send in even frame 1XXXXXXX: send in odd frame Bits 30:27: Channel/endpoint number Bits 26:25: Type XXXXX00X: IN/OUT XXXXX01X: Zero-length packet XXXXX11X: Disable channel command Bit 24: Terminate (last entry for the selected channel/endpoint) 24 8 read-only HAINT HAINT OTG host all channels interrupt register 0x414 0x20 0x00000000 0xFFFFFFFF HAINT Channel interrupts One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 0 16 read-only HAINTMSK HAINTMSK OTG host all channels interrupt mask register 0x418 0x20 0x00000000 0xFFFFFFFF HAINTM Channel interrupt mask One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 0 16 read-write HPRT HPRT OTG host port control and status register 0x440 0x20 0x00000000 0xFFFFFFFF PCSTS Port connect status 0 1 read-only PCDET Port connect detected The core sets this bit when a device connection is detected to trigger an interrupt to the application using the host port interrupt bit in the core interrupt register (HPRTINT bit in OTG_GINTSTS). The application must write a 1 to this bit to clear the interrupt. 1 1 read-write PENA Port enable A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the application clearing this bit. The application cannot set this bit by a register write. It can only clear it to disable the port. This bit does not trigger any interrupt to the application. 2 1 read-write PENCHNG Port enable/disable change The core sets this bit when the status of the port enable bit 2 in this register changes. 3 1 read-write POCA Port overcurrent active Indicates the overcurrent condition of the port. 4 1 read-only POCCHNG Port overcurrent change The core sets this bit when the status of the port overcurrent active bit (bit 4) in this register changes. 5 1 read-write PRES Port resume The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application clears this bit. If the core detects a USB remote wakeup sequence, as indicated by the port resume/remote wakeup detected interrupt bit of the core interrupt register (WKUPINT bit in OTG_GINTSTS), the core starts driving resume signaling without application intervention and clears this bit when it detects a disconnect condition. The read value of this bit indicates whether the core is currently driving resume signaling. When LPM is enabled and the core is in L1 state, the behavior of this bit is as follow: 1. The application sets this bit to drive resume signaling on the port. 2. The core continues to drive the resume signal until a predetermined time specified in BESLTHRS[3:0] field of OTG_GLPMCFG register. 3. If the core detects a USB remote wakeup sequence, as indicated by the port L1Resume/Remote L1Wakeup detected interrupt bit of the core interrupt register (WKUPINT in OTG_GINTSTS), the core starts driving resume signaling without application intervention and clears this bit at the end of resume.This bit can be set or cleared by both the core and the application. This bit is cleared by the core even if there is no device connected to the host. 6 1 read-write PSUSP Port suspend The application sets this bit to put this port in suspend mode. The core only stops sending SOFs when this is set. To stop the PHY clock, the application must set the port clock stop bit, which asserts the suspend input pin of the PHY. The read value of this bit reflects the current suspend status of the port. This bit is cleared by the core after a remote wakeup signal is detected or the application sets the port reset bit or port resume bit in this register or the resume/remote wakeup detected interrupt bit or disconnect detected interrupt bit in the core interrupt register (WKUPINT or DISCINT in OTG_GINTSTS, respectively). 7 1 read-write PRST Port reset When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete. The application must leave this bit set for a minimum duration of at least 10 ms to start a reset on the port. The application can leave it set for another 10 ms in addition to the required minimum duration, before clearing the bit, even though there is no maximum limit set by the USB standard. High speed: 50 ms Full speed/Low speed: 10 ms 8 1 read-write PLSTS Port line status Indicates the current logic level USB data lines Bit 10: Logic level of OTG_DP Bit 11: Logic level of OTG_DM 10 2 read-only PPWR Port power The application uses this field to control power to this port, and the core clears this bit on an overcurrent condition. 12 1 read-write PTCTL Port test control The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port. Others: Reserved 13 4 read-write PSPD Port speed Indicates the speed of the device attached to this port. 17 2 read-only HCCHAR0 HCCHAR0 OTG host channel 0 characteristics register 0x500 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT0 HCSPLT0 OTG host channel 0 split control register 0x504 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT0 HCINT0 OTG host channel 0 interrupt register 0x508 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK0 HCINTMSK0 OTG host channel 0 interrupt mask register 0x50C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ0 HCTSIZ0 OTG host channel 0 transfer size register 0x510 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA0 HCDMA0 OTG host channel 0 DMA address register 0x514 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR1 HCCHAR1 OTG host channel 1 characteristics register 0x520 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT1 HCSPLT1 OTG host channel 1 split control register 0x524 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT1 HCINT1 OTG host channel 1 interrupt register 0x528 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK1 HCINTMSK1 OTG host channel 1 interrupt mask register 0x52C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ1 HCTSIZ1 OTG host channel 1 transfer size register 0x530 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA1 HCDMA1 OTG host channel 1 DMA address register 0x534 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR2 HCCHAR2 OTG host channel 2 characteristics register 0x540 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT2 HCSPLT2 OTG host channel 2 split control register 0x544 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT2 HCINT2 OTG host channel 2 interrupt register 0x548 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK2 HCINTMSK2 OTG host channel 2 interrupt mask register 0x54C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ2 HCTSIZ2 OTG host channel 2 transfer size register 0x550 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA2 HCDMA2 OTG host channel 2 DMA address register 0x554 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR3 HCCHAR3 OTG host channel 3 characteristics register 0x560 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT3 HCSPLT3 OTG host channel 3 split control register 0x564 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT3 HCINT3 OTG host channel 3 interrupt register 0x568 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK3 HCINTMSK3 OTG host channel 3 interrupt mask register 0x56C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ3 HCTSIZ3 OTG host channel 3 transfer size register 0x570 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA3 HCDMA3 OTG host channel 3 DMA address register 0x574 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR4 HCCHAR4 OTG host channel 4 characteristics register 0x580 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT4 HCSPLT4 OTG host channel 4 split control register 0x584 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT4 HCINT4 OTG host channel 4 interrupt register 0x588 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK4 HCINTMSK4 OTG host channel 4 interrupt mask register 0x58C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ4 HCTSIZ4 OTG host channel 4 transfer size register 0x590 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA4 HCDMA4 OTG host channel 4 DMA address register 0x594 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR5 HCCHAR5 OTG host channel 5 characteristics register 0x5A0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT5 HCSPLT5 OTG host channel 5 split control register 0x5A4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT5 HCINT5 OTG host channel 5 interrupt register 0x5A8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK5 HCINTMSK5 OTG host channel 5 interrupt mask register 0x5AC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ5 HCTSIZ5 OTG host channel 5 transfer size register 0x5B0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA5 HCDMA5 OTG host channel 5 DMA address register 0x5B4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR6 HCCHAR6 OTG host channel 6 characteristics register 0x5C0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT6 HCSPLT6 OTG host channel 6 split control register 0x5C4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT6 HCINT6 OTG host channel 6 interrupt register 0x5C8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK6 HCINTMSK6 OTG host channel 6 interrupt mask register 0x5CC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ6 HCTSIZ6 OTG host channel 6 transfer size register 0x5D0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA6 HCDMA6 OTG host channel 6 DMA address register 0x5D4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR7 HCCHAR7 OTG host channel 7 characteristics register 0x5E0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT7 HCSPLT7 OTG host channel 7 split control register 0x5E4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT7 HCINT7 OTG host channel 7 interrupt register 0x5E8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK7 HCINTMSK7 OTG host channel 7 interrupt mask register 0x5EC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ7 HCTSIZ7 OTG host channel 7 transfer size register 0x5F0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA7 HCDMA7 OTG host channel 7 DMA address register 0x5F4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR8 HCCHAR8 OTG host channel 8 characteristics register 0x600 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT8 HCSPLT8 OTG host channel 8 split control register 0x604 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT8 HCINT8 OTG host channel 8 interrupt register 0x608 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK8 HCINTMSK8 OTG host channel 8 interrupt mask register 0x60C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ8 HCTSIZ8 OTG host channel 8 transfer size register 0x610 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA8 HCDMA8 OTG host channel 8 DMA address register 0x614 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR9 HCCHAR9 OTG host channel 9 characteristics register 0x620 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT9 HCSPLT9 OTG host channel 9 split control register 0x624 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT9 HCINT9 OTG host channel 9 interrupt register 0x628 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK9 HCINTMSK9 OTG host channel 9 interrupt mask register 0x62C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ9 HCTSIZ9 OTG host channel 9 transfer size register 0x630 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA9 HCDMA9 OTG host channel 9 DMA address register 0x634 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR10 HCCHAR10 OTG host channel 10 characteristics register 0x640 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT10 HCSPLT10 OTG host channel 10 split control register 0x644 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT10 HCINT10 OTG host channel 10 interrupt register 0x648 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK10 HCINTMSK10 OTG host channel 10 interrupt mask register 0x64C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ10 HCTSIZ10 OTG host channel 10 transfer size register 0x650 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA10 HCDMA10 OTG host channel 10 DMA address register 0x654 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR11 HCCHAR11 OTG host channel 11 characteristics register 0x660 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT11 HCSPLT11 OTG host channel 11 split control register 0x664 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT11 HCINT11 OTG host channel 11 interrupt register 0x668 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK11 HCINTMSK11 OTG host channel 11 interrupt mask register 0x66C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ11 HCTSIZ11 OTG host channel 11 transfer size register 0x670 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA11 HCDMA11 OTG host channel 11 DMA address register 0x674 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR12 HCCHAR12 OTG host channel 12 characteristics register 0x680 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT12 HCSPLT12 OTG host channel 12 split control register 0x684 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT12 HCINT12 OTG host channel 12 interrupt register 0x688 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK12 HCINTMSK12 OTG host channel 12 interrupt mask register 0x68C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ12 HCTSIZ12 OTG host channel 12 transfer size register 0x690 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA12 HCDMA12 OTG host channel 12 DMA address register 0x694 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR13 HCCHAR13 OTG host channel 13 characteristics register 0x6A0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT13 HCSPLT13 OTG host channel 13 split control register 0x6A4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT13 HCINT13 OTG host channel 13 interrupt register 0x6A8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK13 HCINTMSK13 OTG host channel 13 interrupt mask register 0x6AC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ13 HCTSIZ13 OTG host channel 13 transfer size register 0x6B0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA13 HCDMA13 OTG host channel 13 DMA address register 0x6B4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR14 HCCHAR14 OTG host channel 14 characteristics register 0x6C0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT14 HCSPLT14 OTG host channel 14 split control register 0x6C4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT14 HCINT14 OTG host channel 14 interrupt register 0x6C8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK14 HCINTMSK14 OTG host channel 14 interrupt mask register 0x6CC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ14 HCTSIZ14 OTG host channel 14 transfer size register 0x6D0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA14 HCDMA14 OTG host channel 14 DMA address register 0x6D4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write HCCHAR15 HCCHAR15 OTG host channel 15 characteristics register 0x6E0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint. 0 11 read-write EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink. 11 4 read-write EPDIR Endpoint direction Indicates whether the transaction is IN or OUT. 15 1 read-write LSDEV Low-speed device This field is set by the application to indicate that this channel is communicating to a low-speed device. 17 1 read-write EPTYP Endpoint type Indicates the transfer type selected. 18 2 read-write MCNT Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used Note: This field must be set to at least 01. 20 2 read-write DAD Device address This field selects the specific device serving as the data source or sink. 22 7 read-write ODDFRM Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 29 1 read-write CHDIS Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. 30 1 read-write CHENA Channel enable This field is set by the application and cleared by the OTG host. 31 1 read-write HCSPLT15 HCSPLT15 OTG host channel 15 split control register 0x6E4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translators hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT15 HCINT15 OTG host channel 15 interrupt register 0x6E8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. Transfer completed normally without any errors. 0 1 read-write CHH Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. 1 1 read-write AHBERR AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK15 HCINTMSK15 OTG host channel 15 interrupt mask register 0x6EC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ15 HCTSIZ15 OTG host channel 15 transfer size register 0x6F0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). 0 19 read-write PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. 19 10 read-write DPID Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 29 2 read-write DOPNG Do Ping This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. 31 1 read-write HCDMA15 HCDMA15 OTG host channel 15 DMA address register 0x6F4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 read-write DCFG DCFG OTG device configuration register 0x800 0x20 0x02200000 0xFFFFFFFF DSPD Device speed Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support. However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the core is connected. 0 2 read-write NZLSOHSK Non-zero-length status OUT handshake The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfers status stage. 2 1 read-write DAD Device address The application must program this field after every SetAddress control command. 4 7 read-write PFIVL Periodic frame interval Indicates the time within a frame at which the application must be notified using the end of periodic frame interrupt. This can be used to determine if all the isochronous traffic for that frame is complete. 11 2 read-write ERRATIM Erratic error interrupt mask 15 1 read-write PERSCHIVL Periodic schedule interval This field specifies the amount of time the Internal DMA engine must allocate for fetching periodic IN endpoint data. Based on the number of periodic endpoints, this value must be specified as 25, 50 or 75% of the (micro) frame. When any periodic endpoints are active, the internal DMA engine allocates the specified amount of time in fetching periodic IN endpoint data When no periodic endpoint is active, then the internal DMA engine services nonperiodic endpoints, ignoring this field After the specified time within a (micro) frame, the DMA switches to fetching nonperiodic endpoints 24 2 read-write DCTL DCTL OTG device control register 0x804 0x20 0x00000002 0xFFFFFFFF RWUSIG Remote wakeup signaling When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after setting it. If LPM is enabled and the core is in the L1 (sleep) state, when the application sets this bit, the core initiates L1 remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the sleep state. As specified in the LPM specification, the hardware automatically clears this bit 50 s (TL1DevDrvResume) after being set by the application. The application must not set this bit when bRemoteWake from the previous LPM transaction is zero (refer to REMWAKE bit in GLPMCFG register). 0 1 read-write SDIS Soft disconnect The application uses this bit to signal the USB OTG core to perform a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears this bit. 1 1 read-write GINSTS Global IN NAK status 2 1 read-only GONSTS Global OUT NAK status 3 1 read-only TCTL Test control Others: Reserved 4 3 read-write SGINAK Set global IN NAK Writing 1 to this field sets the Global non-periodic IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN endpoints. The application must set this bit only after making sure that the Global IN NAK effective bit in the core interrupt register (GINAKEFF bit in OTG_GINTSTS) is cleared. 7 1 write-only CGINAK Clear global IN NAK Writing 1 to this field clears the Global IN NAK. 8 1 write-only SGONAK Set global OUT NAK Writing 1 to this field sets the Global OUT NAK. The application uses this bit to send a NAK handshake on all OUT endpoints. The application must set the this bit only after making sure that the Global OUT NAK effective bit in the core interrupt register (GONAKEFF bit in OTG_GINTSTS) is cleared. 9 1 write-only CGONAK Clear global OUT NAK Writing 1 to this field clears the Global OUT NAK. 10 1 write-only POPRGDNE Power-on programming done The application uses this bit to indicate that register programming is completed after a wakeup from power down mode. 11 1 read-write DSBESLRJCT Deep sleep BESL reject Core rejects LPM request with BESL value greater than BESL threshold programmed. NYET response is sent for LPM tokens with BESL value greater than BESL threshold. By default, the deep sleep BESL reject feature is disabled. 18 1 read-write DSTS DSTS OTG device status register 0x808 0x20 0x00000010 0xFFFFFFFF SUSPSTS Suspend status In device mode, this bit is set as long as a suspend condition is detected on the USB. The core enters the suspended state when there is no activity on the USB data lines for a period of 3 ms. The core comes out of the suspend: When there is an activity on the USB data lines When the application writes to the remote wakeup signaling bit in the OTG_DCTL register (RWUSIG bit in OTG_DCTL). 0 1 read-only ENUMSPD Enumerated speed Indicates the speed at which the OTG_HS controller has come up after speed detection through a chirp sequence. Others: reserved 1 2 read-only EERR Erratic error The core sets this bit to report any erratic errors. Due to erratic errors, the OTG_HS controller goes into suspended state and an interrupt is generated to the application with Early suspend bit of the OTG_GINTSTS register (ESUSP bit in OTG_GINTSTS). If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover. 3 1 read-only FNSOF Frame number of the received SOF 8 14 read-only DEVLNSTS Device line status Indicates the current logic level USB data lines. Bit [23]: Logic level of D+ Bit [22]: Logic level of D- 22 2 read-only DIEPMSK DIEPMSK OTG device IN endpoint common interrupt mask register 0x810 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed interrupt mask 0 1 read-write EPDM Endpoint disabled interrupt mask 1 1 read-write AHBERRM AHB error mask 2 1 read-write TOM Timeout condition mask (Non-isochronous endpoints) 3 1 read-write ITTXFEMSK IN token received when Tx FIFO empty mask 4 1 read-write INEPNMM IN token received with EP mismatch mask 5 1 read-write INEPNEM IN endpoint NAK effective mask 6 1 read-write TXFURM FIFO underrun mask 8 1 read-write NAKM NAK interrupt mask 13 1 read-write DOEPMSK DOEPMSK OTG device OUT endpoint common interrupt mask register 0x814 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed interrupt mask 0 1 read-write EPDM Endpoint disabled interrupt mask 1 1 read-write AHBERRM AHB error mask 2 1 read-write STUPM STUPM: SETUP phase done mask. Applies to control endpoints only. 3 1 read-write OTEPDM OUT token received when endpoint disabled mask. Applies to control OUT endpoints only. 4 1 read-write STSPHSRXM Status phase received for control write mask 5 1 read-write B2BSTUPM Back-to-back SETUP packets received mask Applies to control OUT endpoints only. 6 1 read-write OUTPKTERRM Out packet error mask 8 1 read-write BERRM Babble error interrupt mask 12 1 read-write NAKMSK NAK interrupt mask 13 1 read-write NYETMSK NYET interrupt mask 14 1 read-write DAINT DAINT OTG device all endpoints interrupt register 0x818 0x20 0x00000000 0xFFFFFFFF IEPINT IN endpoint interrupt bits One bit per IN endpoint: Bit 0 for IN endpoint 0, bit 3 for endpoint 3. 0 16 read-only OEPINT OUT endpoint interrupt bits One bit per OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. 16 16 read-only DAINTMSK DAINTMSK OTG all endpoints interrupt mask register 0x81C 0x20 0x00000000 0xFFFFFFFF IEPM IN EP interrupt mask bits One bit per IN endpoint: Bit 0 for IN EP 0, bit 3 for IN EP 3 0 16 read-write OEPM OUT EP interrupt mask bits One per OUT endpoint: Bit 16 for OUT EP 0, bit 19 for OUT EP 3 16 16 read-write DTHRCTL DTHRCTL OTG device threshold control register 0x830 0x20 0x00000000 0xFFFFFFFF NONISOTHREN Nonisochronous IN endpoints threshold enable When this bit is set, the core enables thresholding for nonisochronous IN endpoints. 0 1 read-write ISOTHREN ISO IN endpoint threshold enable When this bit is set, the core enables thresholding for isochronous IN endpoints. 1 1 read-write TXTHRLEN Transmit threshold length This field specifies the transmit thresholding size in 32-bit words. This field specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmitting on the USB. The threshold length has to be at least eight 32-bit words. This field controls both isochronous and nonisochronous IN endpoint thresholds. The recommended value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). 2 9 read-write RXTHREN Receive threshold enable When this bit is set, the core enables thresholding in the receive direction. 16 1 read-write RXTHRLEN Receive threshold length This field specifies the receive thresholding size in 32-bit words. This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight 32-bit words. The recommended value for RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). 17 9 read-write ARPEN Arbiter parking enable This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default parking is enabled. 27 1 read-write DIEPEMPMSK DIEPEMPMSK OTG device IN endpoint FIFO empty interrupt mask register 0x834 0x20 0x00000000 0xFFFFFFFF INEPTXFEM IN EP Tx FIFO empty interrupt mask bits These bits act as mask bits for OTG_DIEPINTx. TXFE interrupt one bit per IN endpoint: Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3 0 16 read-write DIEPCTL0_INT_BULK DIEPCTL0_INT_BULK OTG device IN endpoint 0 control register 0x900 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPCTL0_ISO DIEPCTL0_ISO OTG device IN endpoint 0 control register DIEPCTL0_INT_BULK 0x900 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPINT0 DIEPINT0 OTG device IN endpoint 0 interrupt register 0x908 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write TOC Timeout condition Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. 3 1 read-write ITTXFE IN token received when Tx FIFO is empty Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. 4 1 read-write INEPNM IN token received with EP mismatch Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. 5 1 read-write INEPNE IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. 6 1 read-write TXFE Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled 8 1 read-write PKTDRPSTS Packet dropped status This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. 11 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write DIEPTSIZ0 DIEPTSIZ0 OTG device IN endpoint 0 transfer size register 0x910 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 0 7 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for endpoint 0. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. 19 2 read-write DIEPDMA0 DIEPDMA0 OTG device IN endpoint 0 DMA address register 0x914 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DTXFSTS0 DTXFSTS0 OTG device IN endpoint transmit FIFO status register 0x918 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available Indicates the amount of free space available in the endpoint Tx FIFO. Values are in terms of 32-bit words: 0xn: n words available Others: Reserved 0 16 read-only DIEPCTL1_INT_BULK DIEPCTL1_INT_BULK OTG device IN endpoint 1 control register 0x920 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPCTL1_ISO DIEPCTL1_ISO OTG device IN endpoint 1 control register DIEPCTL1_INT_BULK 0x920 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPINT1 DIEPINT1 OTG device IN endpoint 1 interrupt register 0x928 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write TOC Timeout condition Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. 3 1 read-write ITTXFE IN token received when Tx FIFO is empty Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. 4 1 read-write INEPNM IN token received with EP mismatch Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. 5 1 read-write INEPNE IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. 6 1 read-write TXFE Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled 8 1 read-write PKTDRPSTS Packet dropped status This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. 11 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write DIEPTSIZ1 DIEPTSIZ1 OTG device IN endpoint 1 transfer size register 0x930 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. 19 10 read-write MCNT Multi count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 29 2 read-write DIEPDMA1 DIEPDMA1 OTG device IN endpoint 1 DMA address register 0x934 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DTXFSTS1 DTXFSTS1 OTG device IN endpoint transmit FIFO status register 0x938 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available Indicates the amount of free space available in the endpoint Tx FIFO. Values are in terms of 32-bit words: 0xn: n words available Others: Reserved 0 16 read-only DIEPCTL2_INT_BULK DIEPCTL2_INT_BULK OTG device IN endpoint 2 control register 0x940 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPCTL2_ISO DIEPCTL2_ISO OTG device IN endpoint 2 control register DIEPCTL2_INT_BULK 0x940 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPINT2 DIEPINT2 OTG device IN endpoint 2 interrupt register 0x948 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write TOC Timeout condition Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. 3 1 read-write ITTXFE IN token received when Tx FIFO is empty Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. 4 1 read-write INEPNM IN token received with EP mismatch Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. 5 1 read-write INEPNE IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. 6 1 read-write TXFE Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled 8 1 read-write PKTDRPSTS Packet dropped status This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. 11 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write DIEPTSIZ2 DIEPTSIZ2 OTG device IN endpoint 2 transfer size register 0x950 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. 19 10 read-write MCNT Multi count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 29 2 read-write DIEPDMA2 DIEPDMA2 OTG device IN endpoint 2 DMA address register 0x954 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DTXFSTS2 DTXFSTS2 OTG device IN endpoint transmit FIFO status register 0x958 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available Indicates the amount of free space available in the endpoint Tx FIFO. Values are in terms of 32-bit words: 0xn: n words available Others: Reserved 0 16 read-only DIEPCTL3_INT_BULK DIEPCTL3_INT_BULK OTG device IN endpoint 3 control register 0x960 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPCTL3_ISO DIEPCTL3_ISO OTG device IN endpoint 3 control register DIEPCTL3_INT_BULK 0x960 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPINT3 DIEPINT3 OTG device IN endpoint 3 interrupt register 0x968 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write TOC Timeout condition Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. 3 1 read-write ITTXFE IN token received when Tx FIFO is empty Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. 4 1 read-write INEPNM IN token received with EP mismatch Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. 5 1 read-write INEPNE IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. 6 1 read-write TXFE Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled 8 1 read-write PKTDRPSTS Packet dropped status This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. 11 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write DIEPTSIZ3 DIEPTSIZ3 OTG device IN endpoint 3 transfer size register 0x970 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. 19 10 read-write MCNT Multi count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 29 2 read-write DIEPDMA3 DIEPDMA3 OTG device IN endpoint 3 DMA address register 0x974 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DTXFSTS3 DTXFSTS3 OTG device IN endpoint transmit FIFO status register 0x978 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available Indicates the amount of free space available in the endpoint Tx FIFO. Values are in terms of 32-bit words: 0xn: n words available Others: Reserved 0 16 read-only DIEPCTL4_INT_BULK DIEPCTL4_INT_BULK OTG device IN endpoint 4 control register 0x980 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPCTL4_ISO DIEPCTL4_ISO OTG device IN endpoint 4 control register DIEPCTL4_INT_BULK 0x980 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPINT4 DIEPINT4 OTG device IN endpoint 4 interrupt register 0x988 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write TOC Timeout condition Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. 3 1 read-write ITTXFE IN token received when Tx FIFO is empty Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. 4 1 read-write INEPNM IN token received with EP mismatch Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. 5 1 read-write INEPNE IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. 6 1 read-write TXFE Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled 8 1 read-write PKTDRPSTS Packet dropped status This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. 11 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write DIEPTSIZ4 DIEPTSIZ4 OTG device IN endpoint 4 transfer size register 0x990 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. 19 10 read-write MCNT Multi count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 29 2 read-write DIEPDMA4 DIEPDMA4 OTG device IN endpoint 4 DMA address register 0x994 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DTXFSTS4 DTXFSTS4 OTG device IN endpoint transmit FIFO status register 0x998 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available Indicates the amount of free space available in the endpoint Tx FIFO. Values are in terms of 32-bit words: 0xn: n words available Others: Reserved 0 16 read-only DIEPCTL5_INT_BULK DIEPCTL5_INT_BULK OTG device IN endpoint 5 control register 0x9A0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPCTL5_ISO DIEPCTL5_ISO OTG device IN endpoint 5 control register DIEPCTL5_INT_BULK 0x9A0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPINT5 DIEPINT5 OTG device IN endpoint 5 interrupt register 0x9A8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write TOC Timeout condition Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. 3 1 read-write ITTXFE IN token received when Tx FIFO is empty Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. 4 1 read-write INEPNM IN token received with EP mismatch Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. 5 1 read-write INEPNE IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. 6 1 read-write TXFE Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled 8 1 read-write PKTDRPSTS Packet dropped status This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. 11 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write DIEPTSIZ5 DIEPTSIZ5 OTG device IN endpoint 5 transfer size register 0x9B0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. 19 10 read-write MCNT Multi count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 29 2 read-write DIEPDMA5 DIEPDMA5 OTG device IN endpoint 5 DMA address register 0x9B4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DTXFSTS5 DTXFSTS5 OTG device IN endpoint transmit FIFO status register 0x9B8 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available Indicates the amount of free space available in the endpoint Tx FIFO. Values are in terms of 32-bit words: 0xn: n words available Others: Reserved 0 16 read-only DIEPCTL6_INT_BULK DIEPCTL6_INT_BULK OTG device IN endpoint 6 control register 0x9C0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPCTL6_ISO DIEPCTL6_ISO OTG device IN endpoint 6 control register DIEPCTL6_INT_BULK 0x9C0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPINT6 DIEPINT6 OTG device IN endpoint 6 interrupt register 0x9C8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write TOC Timeout condition Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. 3 1 read-write ITTXFE IN token received when Tx FIFO is empty Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. 4 1 read-write INEPNM IN token received with EP mismatch Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. 5 1 read-write INEPNE IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. 6 1 read-write TXFE Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled 8 1 read-write PKTDRPSTS Packet dropped status This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. 11 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write DIEPTSIZ6 DIEPTSIZ6 OTG device IN endpoint 6 transfer size register 0x9D0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. 19 10 read-write MCNT Multi count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 29 2 read-write DIEPDMA6 DIEPDMA6 OTG device IN endpoint 6 DMA address register 0x9D4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DTXFSTS6 DTXFSTS6 OTG device IN endpoint transmit FIFO status register 0x9D8 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available Indicates the amount of free space available in the endpoint Tx FIFO. Values are in terms of 32-bit words: 0xn: n words available Others: Reserved 0 16 read-only DIEPCTL7_INT_BULK DIEPCTL7_INT_BULK OTG device IN endpoint 7 control register 0x9E0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPCTL7_ISO DIEPCTL7_ISO OTG device IN endpoint 7 control register DIEPCTL7_INT_BULK 0x9E0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPINT7 DIEPINT7 OTG device IN endpoint 7 interrupt register 0x9E8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write TOC Timeout condition Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. 3 1 read-write ITTXFE IN token received when Tx FIFO is empty Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. 4 1 read-write INEPNM IN token received with EP mismatch Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. 5 1 read-write INEPNE IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. 6 1 read-write TXFE Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled 8 1 read-write PKTDRPSTS Packet dropped status This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. 11 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write DIEPTSIZ7 DIEPTSIZ7 OTG device IN endpoint 7 transfer size register 0x9F0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. 19 10 read-write MCNT Multi count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 29 2 read-write DIEPDMA7 DIEPDMA7 OTG device IN endpoint 7 DMA address register 0x9F4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DTXFSTS7 DTXFSTS7 OTG device IN endpoint transmit FIFO status register 0x9F8 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available Indicates the amount of free space available in the endpoint Tx FIFO. Values are in terms of 32-bit words: 0xn: n words available Others: Reserved 0 16 read-only DIEPCTL8_INT_BULK DIEPCTL8_INT_BULK OTG device IN endpoint 8 control register 0xA00 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPCTL8_ISO DIEPCTL8_ISO OTG device IN endpoint 8 control register DIEPCTL8_INT_BULK 0xA00 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status It indicates the following: When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write STALL STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 21 1 read-write TXFNUM Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. 22 4 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DIEPINT8 DIEPINT8 OTG device IN endpoint 8 interrupt register 0xA08 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write TOC Timeout condition Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. 3 1 read-write ITTXFE IN token received when Tx FIFO is empty Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. 4 1 read-write INEPNM IN token received with EP mismatch Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. 5 1 read-write INEPNE IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. 6 1 read-write TXFE Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled 8 1 read-write PKTDRPSTS Packet dropped status This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. 11 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write DIEPTSIZ8 DIEPTSIZ8 OTG device IN endpoint 8 transfer size register 0xA10 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. 19 10 read-write MCNT Multi count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 29 2 read-write DIEPDMA8 DIEPDMA8 OTG device IN endpoint 8 DMA address register 0xA14 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DTXFSTS8 DTXFSTS8 OTG device IN endpoint transmit FIFO status register 0xA18 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available Indicates the amount of free space available in the endpoint Tx FIFO. Values are in terms of 32-bit words: 0xn: n words available Others: Reserved 0 16 read-only DOEPCTL0 DOEPCTL0 OTG device control OUT endpoint 0 control register 0xB00 0x20 0x00008000 0xFFFFFFFF MPSIZ Maximum packet size The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN endpoint 0. 0 2 read-only USBAEP USB active endpoint This bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces. 15 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit, the core stops receiving data, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type Hardcoded to 00 for control. 18 2 read-only SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only EPDIS Endpoint disable The application cannot disable control OUT endpoint 0. 30 1 read-only EPENA Endpoint enable The application sets this bit to start transmitting data on endpoint 0. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 write-only DOEPINT0 DOEPINT0 OTG device OUT endpoint 0 interrupt register 0xB08 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write STUP SETUP phase done Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. 3 1 read-write OTEPDIS OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. 4 1 read-write STSPHSRX Status phase received for control write This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG_HS has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. 5 1 read-write B2BSTUP Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. 6 1 read-write OUTPKTERR OUT packet error This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. 8 1 read-write BERR Babble error interrupt The core generates this interrupt when babble is received for the endpoint. 12 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write NYET NYET interrupt This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. 14 1 read-write STPKTRX Setup packet received Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. 15 1 read-write DOEPTSIZ0 DOEPTSIZ0 OTG device OUT endpoint 0 transfer size register 0xB10 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 0 7 read-write PKTCNT Packet count This field is decremented to zero after a packet is written into the Rx FIFO. 19 1 read-write STUPCNT SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 29 2 read-write DOEPDMA0 DOEPDMA0 OTG device OUT endpoint 0 DMA address register 0xB14 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DOEPCTL1_INT_BULK DOEPCTL1_INT_BULK OTG device OUT endpoint 1 control register 0xB20 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPCTL1_ISO DOEPCTL1_ISO OTG device OUT endpoint 1 control register DOEPCTL1_INT_BULK 0xB20 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous OUT endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPINT1 DOEPINT1 OTG device OUT endpoint 1 interrupt register 0xB28 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write STUP SETUP phase done Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. 3 1 read-write OTEPDIS OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. 4 1 read-write STSPHSRX Status phase received for control write This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG_HS has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. 5 1 read-write B2BSTUP Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. 6 1 read-write OUTPKTERR OUT packet error This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. 8 1 read-write BERR Babble error interrupt The core generates this interrupt when babble is received for the endpoint. 12 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write NYET NYET interrupt This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. 14 1 read-write STPKTRX Setup packet received Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. 15 1 read-write DOEPTSIZ1 DOEPTSIZ1 OTG device OUT endpoint 1 transfer size register 0xB30 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. 19 10 read-write RXDPID Received data PID This is the data PID received in the last packet for this endpoint. STUPCNT[1:0]: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 29 2 read-write DOEPDMA1 DOEPDMA1 OTG device OUT endpoint 1 DMA address register 0xB34 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DOEPCTL2_INT_BULK DOEPCTL2_INT_BULK OTG device OUT endpoint 2 control register 0xB40 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPCTL2_ISO DOEPCTL2_ISO OTG device OUT endpoint 2 control register DOEPCTL2_INT_BULK 0xB40 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous OUT endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPINT2 DOEPINT2 OTG device OUT endpoint 2 interrupt register 0xB48 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write STUP SETUP phase done Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. 3 1 read-write OTEPDIS OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. 4 1 read-write STSPHSRX Status phase received for control write This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG_HS has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. 5 1 read-write B2BSTUP Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. 6 1 read-write OUTPKTERR OUT packet error This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. 8 1 read-write BERR Babble error interrupt The core generates this interrupt when babble is received for the endpoint. 12 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write NYET NYET interrupt This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. 14 1 read-write STPKTRX Setup packet received Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. 15 1 read-write DOEPTSIZ2 DOEPTSIZ2 OTG device OUT endpoint 2 transfer size register 0xB50 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. 19 10 read-write RXDPID Received data PID This is the data PID received in the last packet for this endpoint. STUPCNT[1:0]: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 29 2 read-write DOEPDMA2 DOEPDMA2 OTG device OUT endpoint 2 DMA address register 0xB54 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DOEPCTL3_INT_BULK DOEPCTL3_INT_BULK OTG device OUT endpoint 3 control register 0xB60 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPCTL3_ISO DOEPCTL3_ISO OTG device OUT endpoint 3 control register DOEPCTL3_INT_BULK 0xB60 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous OUT endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPINT3 DOEPINT3 OTG device OUT endpoint 3 interrupt register 0xB68 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write STUP SETUP phase done Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. 3 1 read-write OTEPDIS OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. 4 1 read-write STSPHSRX Status phase received for control write This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG_HS has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. 5 1 read-write B2BSTUP Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. 6 1 read-write OUTPKTERR OUT packet error This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. 8 1 read-write BERR Babble error interrupt The core generates this interrupt when babble is received for the endpoint. 12 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write NYET NYET interrupt This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. 14 1 read-write STPKTRX Setup packet received Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. 15 1 read-write DOEPTSIZ3 DOEPTSIZ3 OTG device OUT endpoint 3 transfer size register 0xB70 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. 19 10 read-write RXDPID Received data PID This is the data PID received in the last packet for this endpoint. STUPCNT[1:0]: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 29 2 read-write DOEPDMA3 DOEPDMA3 OTG device OUT endpoint 3 DMA address register 0xB74 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DOEPCTL4_INT_BULK DOEPCTL4_INT_BULK OTG device OUT endpoint 4 control register 0xB80 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPCTL4_ISO DOEPCTL4_ISO OTG device OUT endpoint 4 control register DOEPCTL4_INT_BULK 0xB80 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous OUT endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPINT4 DOEPINT4 OTG device OUT endpoint 4 interrupt register 0xB88 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write STUP SETUP phase done Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. 3 1 read-write OTEPDIS OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. 4 1 read-write STSPHSRX Status phase received for control write This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG_HS has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. 5 1 read-write B2BSTUP Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. 6 1 read-write OUTPKTERR OUT packet error This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. 8 1 read-write BERR Babble error interrupt The core generates this interrupt when babble is received for the endpoint. 12 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write NYET NYET interrupt This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. 14 1 read-write STPKTRX Setup packet received Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. 15 1 read-write DOEPTSIZ4 DOEPTSIZ4 OTG device OUT endpoint 4 transfer size register 0xB90 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. 19 10 read-write RXDPID Received data PID This is the data PID received in the last packet for this endpoint. STUPCNT[1:0]: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 29 2 read-write DOEPDMA4 DOEPDMA4 OTG device OUT endpoint 4 DMA address register 0xB94 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DOEPCTL5_INT_BULK DOEPCTL5_INT_BULK OTG device OUT endpoint 5 control register 0xBA0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPCTL5_ISO DOEPCTL5_ISO OTG device OUT endpoint 5 control register DOEPCTL5_INT_BULK 0xBA0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous OUT endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPINT5 DOEPINT5 OTG device OUT endpoint 5 interrupt register 0xBA8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write STUP SETUP phase done Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. 3 1 read-write OTEPDIS OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. 4 1 read-write STSPHSRX Status phase received for control write This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG_HS has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. 5 1 read-write B2BSTUP Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. 6 1 read-write OUTPKTERR OUT packet error This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. 8 1 read-write BERR Babble error interrupt The core generates this interrupt when babble is received for the endpoint. 12 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write NYET NYET interrupt This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. 14 1 read-write STPKTRX Setup packet received Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. 15 1 read-write DOEPTSIZ5 DOEPTSIZ5 OTG device OUT endpoint 5 transfer size register 0xBB0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. 19 10 read-write RXDPID Received data PID This is the data PID received in the last packet for this endpoint. STUPCNT[1:0]: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 29 2 read-write DOEPDMA5 DOEPDMA5 OTG device OUT endpoint 5 DMA address register 0xBB4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DOEPCTL6_INT_BULK DOEPCTL6_INT_BULK OTG device OUT endpoint 6 control register 0xBC0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPCTL6_ISO DOEPCTL6_ISO OTG device OUT endpoint 6 control register DOEPCTL6_INT_BULK 0xBC0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous OUT endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPINT6 DOEPINT6 OTG device OUT endpoint 6 interrupt register 0xBC8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write STUP SETUP phase done Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. 3 1 read-write OTEPDIS OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. 4 1 read-write STSPHSRX Status phase received for control write This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG_HS has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. 5 1 read-write B2BSTUP Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. 6 1 read-write OUTPKTERR OUT packet error This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. 8 1 read-write BERR Babble error interrupt The core generates this interrupt when babble is received for the endpoint. 12 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write NYET NYET interrupt This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. 14 1 read-write STPKTRX Setup packet received Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. 15 1 read-write DOEPTSIZ6 DOEPTSIZ6 OTG device OUT endpoint 6 transfer size register 0xBD0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. 19 10 read-write RXDPID Received data PID This is the data PID received in the last packet for this endpoint. STUPCNT[1:0]: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 29 2 read-write DOEPDMA6 DOEPDMA6 OTG device OUT endpoint 6 DMA address register 0xBD4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DOEPCTL7_INT_BULK DOEPCTL7_INT_BULK OTG device OUT endpoint 7 control register 0xBE0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPCTL7_ISO DOEPCTL7_ISO OTG device OUT endpoint 7 control register DOEPCTL7_INT_BULK 0xBE0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous OUT endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPINT7 DOEPINT7 OTG device OUT endpoint 7 interrupt register 0xBE8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write STUP SETUP phase done Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. 3 1 read-write OTEPDIS OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. 4 1 read-write STSPHSRX Status phase received for control write This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG_HS has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. 5 1 read-write B2BSTUP Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. 6 1 read-write OUTPKTERR OUT packet error This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. 8 1 read-write BERR Babble error interrupt The core generates this interrupt when babble is received for the endpoint. 12 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write NYET NYET interrupt This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. 14 1 read-write STPKTRX Setup packet received Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. 15 1 read-write DOEPTSIZ7 DOEPTSIZ7 OTG device OUT endpoint 7 transfer size register 0xBF0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. 19 10 read-write RXDPID Received data PID This is the data PID received in the last packet for this endpoint. STUPCNT[1:0]: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 29 2 read-write DOEPDMA7 DOEPDMA7 OTG device OUT endpoint 7 DMA address register 0xBF4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write DOEPCTL8_INT_BULK DOEPCTL8_INT_BULK OTG device OUT endpoint 8 control register 0xC00 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write DPID Endpoint data PID Applies to interrupt/bulk OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID and SD1PID register fields to program either DATA0 or DATA1 PID. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SD0PID Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. 28 1 write-only SD1PID Set DATA1 PID Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPCTL8_ISO DOEPCTL8_ISO OTG device OUT endpoint 8 control register DOEPCTL8_INT_BULK 0xC00 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 0 11 read-write USBAEP USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. 15 1 read-write EONUM Even/odd frame Applies to isochronous OUT endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 16 1 read-only NAKSTS NAK status Indicates the following: When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 17 1 read-only EPTYP Endpoint type This is the transfer type supported by this logical endpoint. 18 2 read-write SNPM Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. 20 1 read-write STALL STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake. 21 1 read-write CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint. 26 1 write-only SNAK Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. 27 1 write-only SEVNFRM Set even frame Applies to isochronous OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. 28 1 write-only SODDFRM Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 29 1 write-only EPDIS Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. 30 1 read-write EPENA Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed 31 1 read-write DOEPINT8 DOEPINT8 OTG device OUT endpoint 8 interrupt register 0xC08 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 0 1 read-write EPDISD Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the applications request. 1 1 read-write AHBERR AHB error This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. 2 1 read-write STUP SETUP phase done Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. 3 1 read-write OTEPDIS OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. 4 1 read-write STSPHSRX Status phase received for control write This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG_HS has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. 5 1 read-write B2BSTUP Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. 6 1 read-write OUTPKTERR OUT packet error This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. 8 1 read-write BERR Babble error interrupt The core generates this interrupt when babble is received for the endpoint. 12 1 read-write NAK NAK input The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. 13 1 read-write NYET NYET interrupt This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. 14 1 read-write STPKTRX Setup packet received Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. 15 1 read-write DOEPTSIZ8 DOEPTSIZ8 OTG device OUT endpoint 8 transfer size register 0xC10 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 0 19 read-write PKTCNT Packet count Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. 19 10 read-write RXDPID Received data PID This is the data PID received in the last packet for this endpoint. STUPCNT[1:0]: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 29 2 read-write DOEPDMA8 DOEPDMA8 OTG device OUT endpoint 8 DMA address register 0xC14 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 0 32 read-write PCGCCTL PCGCCTL OTG power and clock gating control register 0xE00 0x20 0x200B8000 0xFFFFFFFF STPPCLK Stop PHY clock The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts. 0 1 read-write GATEHCLK Gate HCLK The application sets this bit to gate HCLK to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts. 1 1 read-write PHYSUSP PHY suspended Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended after the application has set the STPPCLK bit. 4 1 read-only ENL1GTG Enable sleep clock gating When this bit is set, core internal clock gating is enabled in Sleep state if the core cannot assert utmi_l1_suspend_n. When this bit is not set, the PHY clock is not gated in Sleep state. 5 1 read-write PHYSLEEP PHY in Sleep This bit indicates that the PHY is in the Sleep state. 6 1 read-only SUSP Deep Sleep This bit indicates that the PHY is in Deep Sleep when in L1 state. 7 1 read-only PCGCCTL1 PCGCCTL1 OTG power and clock gating control register 1 0xE04 0x20 0x00000000 0xFFFFFFFF GATEEN Enable active clock gating The application programs GATEEN to enable Active Clock Gating feature for the PHY and AHB clocks. 0 1 read-write CNTGATECLK Counter for clock gating Indicates to the controller how many PHY Clock cycles and AHB Clock cycles of 'IDLE' (no activity) the controller waits for before Gating the respective PHY and AHB clocks internal to the controller. 1 2 read-write RAMGATEEN Enable RAM clock gating Enable gating of the FIFO RAM. 3 1 read-write OTG_FS 0x40080000 OTG_FS USB OTG FS global interrupt 112 PKA Public key accelerator PKA 0x48022000 0x0 0x4000 registers PKA PKA global interrupt 35 CR CR PKA control register 0x0 0x20 0x00000000 0xFFFFFFFF EN PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. Note: When EN=0 PKA RAM can still be accessed by the application. 0 1 read-write START start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. Note: START is ignored if PKA is busy. 1 1 read-write MODE PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. 8 6 read-write PROCENDIE End of operation interrupt enable 17 1 read-write RAMERRIE RAM error interrupt enable 19 1 read-write ADDRERRIE Address error interrupt enable 20 1 read-write OPERRIE Operation error interrupt enable 21 1 read-write SR SR PKA status register 0x4 0x20 0x00000000 0xFFFFFFFF INITOK PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. 0 1 read-only LMF Limited mode flag This bit is updated when EN bit in PKA_CR is set 1 1 read-only BUSY PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). 16 1 read-only PROCENDF PKA End of Operation flag 17 1 read-only RAMERRF PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. 19 1 read-only ADDRERRF Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. 20 1 read-only OPERRF Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. 21 1 read-only CLRFR CLRFR PKA clear flag register 0x8 0x20 0x00000000 0xFFFFFFFF PROCENDFC Clear PKA End of Operation flag 17 1 write-only RAMERRFC Clear PKA RAM error flag 19 1 write-only ADDRERRFC Clear address error flag 20 1 write-only OPERRFC Clear operation error flag 21 1 write-only PSSI Parallel synchronous slave interface PSSI 0x48000400 0x0 0x400 registers PSSI PSSI global interrupt 130 CR CR PSSI control register 0x0 0x20 0x40000000 0xFFFFFFFF CKPOL Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN. 5 1 read-write CKPOL FallingEdge Falling edge active for inputs or rising edge active for outputs 0 RisingEdge Rising edge active for inputs or falling edge active for outputs 1 DEPOL Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface. 6 1 read-write DEPOL ActiveLow PSSI_DE active low (0 indicates that data is valid) 0 ActiveHigh PSSI_DE active high (1 indicates that data is valid) 1 RDYPOL Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface. 8 1 read-write RDYPOL ActiveLow PSSI_RDY active low (0 indicates that the receiver is ready to receive) 0 ActiveHigh PSSI_RDY active high (1 indicates that the receiver is ready to receive) 1 EDM Extended data mode 10 2 read-write EDM BitWidth8 Interface captures 8-bit data on every parallel data clock 0 BitWidth16 The interface captures 16-bit data on every parallel data clock 3 ENABLE PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. Note: The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. 14 1 read-write ENABLE Disabled PSSI disabled 0 Enabled PSSI enabled 1 DERDYCFG Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity. 18 3 read-write DERDYCFG Disabled PSSI_DE and PSSI_RDY both disabled 0 Rdy Only PSSI_RDY enabled 1 De Only PSSI_DE enabled 2 RdyDeAlt Both PSSI_RDY and PSSI_DE alternate functions enabled 3 RdyDe Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin 4 RdyRemapped Only PSSI_RDY function enabled, but mapped to PSSI_DE pin 5 DeRemapped Only PSSI_DE function enabled, but mapped to PSSI_RDY pin 6 RdyDeBidi Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin 7 CKSRC Clock source This bit configures the clock source of the PSSI_PDCK. 29 1 read-write DMAEN DMA enable bit 30 1 read-write DMAEN Disabled DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled. 0 Enabled DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR 1 OUTEN Data direction selection bit 31 1 read-write OUTEN ReceiveMode Data is input synchronously with PSSI_PDCK 0 TransmitMode Data is output synchronously with PSSI_PDCK 1 SR SR PSSI status register 0x4 0x20 0x00000000 0xFFFFFFFF RTT4B FIFO is ready to transfer four bytes 2 1 read-only RTT4B NotReady FIFO is not ready for a four-byte transfer 0 Ready FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO 1 RTT1B FIFO is ready to transfer one byte 3 1 read-only RTT1B NotReady FIFO is not ready for a 1-byte transfer 0 Ready FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO 1 RIS RIS PSSI raw interrupt status register 0x8 0x20 0x00000000 0xFFFFFFFF OVR_RIS Data buffer overrun/underrun raw interrupt status This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR. 1 1 read-only OVR_RIS Cleared No overrun/underrun occurred 0 Occurred An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR 1 IER IER PSSI interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF OVR_IE Data buffer overrun/underrun interrupt enable 1 1 read-write OVR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if either an overrun or an underrun error occurred 1 MIS MIS PSSI masked interrupt status register 0x10 0x20 0x00000000 0xFFFFFFFF OVR_MIS Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1. 1 1 read-only OVR_MIS Disabled No interrupt is generated when an overrun/underrun error occurs 0 Enabled An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER 1 ICR ICR PSSI interrupt clear register 0x14 0x20 0x00000000 0xFFFFFFFF OVR_ISC Data buffer overrun/underrun interrupt status clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS. 1 1 write-only OVR_ISC Clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS 1 DR DR PSSI data register 0x28 0x20 0x00000000 0xFFFFFFFF BYTE0 Data byte 0 0 8 read-write 0 255 BYTE1 Data byte 1 8 8 read-write 0 255 BYTE2 Data byte 2 16 8 read-write 0 255 BYTE3 Data byte 3 24 8 read-write 0 255 PWR Power control PWR 0x58024800 0x0 0x54 registers CR1 CR1 PWR control register 1 0x0 0x20 0x00000001 0xFFFFFFFF SVOS System Stop mode voltage scaling selection. 0 1 read-write PVDE Programmable voltage detector enable 4 1 read-write PLS Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. 5 3 read-write DBP Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in the PWR_CSR1 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. 8 1 read-write FLPS Flash low-power mode in Stop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when device is in Stop mode. consumption). 9 1 read-write RLPSN RAM low power mode disable in STOP. When set the RAMs will not enter to low power mode when the system enters to STOP. 10 1 read-write BOOSTE analog switch VBoost control This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits. 11 1 read-write AVDREADY analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected VDDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_CSR1 register) after setting the AVDEN bit and selecting the supply level to be monitored (ALS bits). 12 1 read-write AVDEN Peripheral voltage monitor on VDDA enable 13 1 read-write ALS Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. 14 2 read-write SR1 SR1 PWR control status register 1 0x4 0x20 0x00000000 0xFFFFFFFF ACTVOS VOS currently applied for VCORE voltage scaling selection. These bit reflect the last VOS value applied to the PMU. 0 1 read-only ACTVOSRDY Voltage levels ready bit for currently used ACTVOS and SDHILEVEL This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2). 1 1 read-only PVDO Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. PLS[2:0] bits. bits. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. 4 1 read-only AVDO Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set 13 1 read-only CSR1 CSR1 PWR control status register 1 0x8 0x20 0x00000000 0xFFFFFFFF BREN Backup regulator enable When set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. 0 1 read-write MONEN VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. Note: VBAT and temperature monitoring are only available when the backup regulator is enabled (BREN bit set to 1). 4 1 read-write BRRDY Backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready. 16 1 read-only VBATL VBAT level monitoring versus low threshold 20 1 read-only VBATH VBAT level monitoring versus high threshold 21 1 read-only TEMPL Temperature level monitoring versus low threshold 22 1 read-only TEMPH Temperature level monitoring versus high threshold 23 1 read-only CSR2 CSR2 PWR control register 2 0xC 0x20 0x00000006 0xFFFFFFFF BYPASS Power management unit bypass Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. 0 1 read-writeOnce LDOEN Low drop-out regulator enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. 1 1 read-writeOnce SDEN SMPS step-down converter enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. 2 1 read-writeOnce SMPSEXTHP SMPS external power delivery selection Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. 3 1 read-writeOnce SDHILEVEL SMPS step-down converter voltage output for LDO or external supply This bit is used when both the LDO and SMPS step-down converter are enabled with SDEN and LDOEN enabled or when SMPSEXTHP is enabled. In this case SDHILEVEL has to be set to 1 to confirm the regulator settings 4 1 read-writeOnce VBE VBAT charging enable 8 1 read-write VBRS VBAT charging resistor selection 9 1 read-write XSPICAP1 XSPI port 1 capacitor control bits see the product datasheet for more details 10 2 read-write XSPICAP2 XSPI port 2 capacitor control bits see the product datasheet for more details 12 2 read-write EN_XSPIM1 EN_XSPIM1: this bit allow the SW to enable the XSPI interface. The XSPIM_P1 supply must be stable prior to setting this bit. 14 1 read-write EN_XSPIM2 EN_XSPIM2: this bit allows the SW to enable the XSPI interface, when available. The XSPIM_P2 supply must be stable prior to setting this bit. It should also be set when FMC is used. 15 1 read-write SDEXTRDY SMPS step-down converter external supply ready This bit is set by hardware to indicate that the external supply from the SMPS step-down converter is ready. 16 1 read-only USB33DEN VDD33_USB voltage level detector enable 24 1 read-write USBREGEN USB regulator enable. 25 1 read-write USB33RDY USB supply ready. 26 1 read-only USBHSREGEN USB HS regulator enable. 27 1 read-write CSR3 CSR3 PWR CPU control register 3 0x10 0x20 0x00000000 0xFFFFFFFF PDDS Power Down Deepsleep. This bit allows CPU to define the Deepsleep mode 0 1 read-write CSSF Clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. 1 1 read-write STOPF STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU CSSF bit. 8 1 read-only SBF System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU CSSF bit 9 1 read-only CSR4 CSR4 PWR control status register 4 0x14 0x20 0x00000002 0xFFFFFFFF VOS Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling must be changed before increasing the system frequency. When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. Note: Refer to Section Electrical characteristics of the product datasheet for more details. 0 1 read-write VOSRDY VOS Ready bit 1 1 read-only WKUPCR WKUPCR PWR wakeup clear register 0x20 0x20 0x00000000 0xFFFFFFFF WKUPC1 Clear Wakeup pin flag for WKUP1 These bits are always read as 0. 0 1 read-write WKUPC2 Clear Wakeup pin flag for WKUP2 These bits are always read as 0. 1 1 read-write WKUPC3 Clear Wakeup pin flag for WKUP3 These bits are always read as 0. 2 1 read-write WKUPC4 Clear Wakeup pin flag for WKUP4 These bits are always read as 0. 3 1 read-write WKUPFR WKUPFR PWR wakeup flag register 0x24 0x20 0x00000000 0xFFFFFFFF WKUPF1 Wakeup pin WKUP1 flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR). 0 1 read-only WKUPF2 Wakeup pin WKUP2 flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC2 bit in the PWR wakeup clear register (PWR_WKUPCR). 1 1 read-only WKUPF3 Wakeup pin WKUP3 flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC3 bit in the PWR wakeup clear register (PWR_WKUPCR). 2 1 read-only WKUPF4 Wakeup pin WKUP4 flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC4 bit in the PWR wakeup clear register (PWR_WKUPCR). 3 1 read-only WKUPEPR WKUPEPR PWR wakeup enable and polarity register 0x28 0x20 0x00000000 0xFFFFFFFF WKUPEN1 Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. 0 1 read-write WKUPEN2 Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. 1 1 read-write WKUPEN3 Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. 2 1 read-write WKUPEN4 Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. 3 1 read-write WKUPP1 Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. 8 1 read-write WKUPP2 Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. 9 1 read-write WKUPP3 Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. 10 1 read-write WKUPP4 Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. 11 1 read-write WKUPPUPD1 Wakeup pin pull configuration for WKUPn, These bits define the I/O pad pull configuration used when WKUPENn = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The Wakeup pin pull configuration is kept in Standby mode. 16 2 read-write WKUPPUPD2 Wakeup pin pull configuration for WKUPn, These bits define the I/O pad pull configuration used when WKUPENn = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The Wakeup pin pull configuration is kept in Standby mode. 18 2 read-write WKUPPUPD3 Wakeup pin pull configuration for WKUPn, These bits define the I/O pad pull configuration used when WKUPENn = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The Wakeup pin pull configuration is kept in Standby mode. 20 2 read-write WKUPPUPD4 Wakeup pin pull configuration for WKUPn, These bits define the I/O pad pull configuration used when WKUPENn = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The Wakeup pin pull configuration is kept in Standby mode. 22 2 read-write UCPDR UCPDR PWR USB Type-C and Power Delivery register 0x2C 0x20 0x00000002 0xFFFFFFFF UCPD_DBDIS UCPD dead battery disable 0 1 read-write UCPD_STBY UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers. 1 1 read-write APCR APCR PWR apply pull configuration register 0x30 0x20 0x00030000 0xFFFFFFFF APC Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx, PDCRx registers are applied in Standby mode even after wakeup until APC bit is reset to 0. When this bit is cleared, the I/O pull-up or pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx and PDCRx registers are not applied in Standby mode and IO becomes Hi-Z. 0 1 read-write PN7_PUPD Port N bit 7 pull-up/down configuration When this bit is set, a weak pull-up or pull-down resistor is applied on PN7 following inverse logic applied on PN6. If the PUN6 bit in PWR_PUCRN register is set and APC bit is set the week pull-down is applied on PN7. If the PDN6 bit in PWR_PDCRN register is set and APC bit is set the week pull-up is applied on PN7. 16 1 read-write PO5_PUPD Port O bit 5 pull-up/down configuration When this bit is set, a weak pull-up or pull down resistor is applied on PO5 following inverse logic applied on PO4. If the PUO4 bit in PWR_PUCRO register is set and APC bit is set the week pull-down is applied on PO5. If the PDO4 bit in PWR_PDCRO register is set and APC bit is set the week pull-up is applied on PO5.. 17 1 read-write I3CPB6_PU Port PB6 I3C pull-up bit When I3C is used on PB6, when set, this bit activates the pull-up on I3C1_SCL (PB6) in standby mode. 28 1 read-write I3CPB7_PU Port PB7 I3C pull-up bit When I3C is used on PB7, when set, this bit activates the pull-up on I3C1_SDA (PB7) in standby mode. 29 1 read-write I3CPB8_PU Port PB8 I3C pull-up bit When I3C is used on PB8, when set, this bit activates the pull-up on I3C1_SCL (PB8) in standby mode. 30 1 read-write I3CPB9_PU Port PB9 I3C pull-up bit When I3C is used on PB9, when set, this bit activates the pull-up on I3C1_SDA (PB9) in standby mode. 31 1 read-write PUCRN PUCRN PWR port N pull-up control register 0x34 0x20 0x00000000 0xFFFFFFFF PUN1 Port N pull-up bit 1 When set, each bit activates the pull-up on PN1 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD1 bit is also set. 1 1 read-write PUN6 Port N pull-up bit 6 When set activates the pull-up on PN6 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PDN6 bit is also set. 6 1 read-write PUN12 Port N pull-up bit 12 When set, each bit activates the pull-up on PN12 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD12 bit is also set. 12 1 read-write PDCRN PDCRN PWR port N pull-down control register 0x38 0x20 0x00000000 0xFFFFFFFF PDN0 Port N pull-down bit 0 When set activates the pull-down on PN0 when the APC bit is set in PWR_APCR. 0 1 read-write PDN1 Port N pull-down bit 1 When set activates the pull-down on PN1 when the APC bit is set in PWR_APCR. 1 1 read-write PDN2N5 Port N PN2 to PN5 pull-down activation When set, four pull-down resistors are activated on PN2 to PN5 when the APC bit is set in PWR_APCR. 2 1 read-write PDN6 Port N pull-down bit 6 When set activates the pull-down on PN6 when the APC bit is set in PWR_APCR. 6 1 read-write PDN8N11 Port N - PN8 to PN11 pull-down activation When set, four pull-down resistors are activated on PN8 to PN11 when the APC bit is set in PWR_APCR. 8 1 read-write PDN12 Port N pull-down bit 12 When set activates the pull-down on PN12 when the APC bit is set in PWR_APCR. 12 1 read-write PUCRO PUCRO PWR port O pull-up control register 0x3C 0x20 0x00000000 0xFFFFFFFF PUO0 (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set. 0 1 read-write PUO1 (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set. 1 1 read-write PUO4 Port O pull-up bit 4 When set activates the pull-up on PO4 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits PDO4 in PWR_PDCRO is also set. 4 1 read-write PDCRO PDCRO PWR port O pull-down control register 0x40 0x20 0x00000000 0xFFFFFFFF PDO0 Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. 0 1 read-write PDO1 Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. 1 1 read-write PDO2 Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. 2 1 read-write PDO3 Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. 3 1 read-write PDO4 Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. 4 1 read-write PDCRP PDCRP PWR port P pull-down control register 0x44 0x20 0x00000000 0xFFFFFFFF PDP0P3 Port P0-P3 pull-down activation When set, four pull-down resistors are activated on P0 to P3 when the APC bit is set in PWR_APCR. 0 1 read-write PDP4P7 Port P4-P7 pull-down activation When set, four pull-down resitors are activated on P4 to P7 when the APC bit is set in PWR_APCR. 4 1 read-write PDP8P11 Port P8-P11 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR. 8 1 read-write PDP12P15 Port P12-P15 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR. 12 1 read-write PDR1 PDR1 PWR debug register 1 0x50 0x20 0x00000000 0xFFFFFFFF UNLOCKED Debug Register Unlocked. 0 1 read-write SDFPWMEN Step down converter force PWM mode 3 1 read-write SYNC_ADC (Non-User bit) 16 1 read-write RAMCFG RAMs configuration controller RAMCFG 0x58027000 0x0 0x1000 registers IER IER RAMECC interrupt enable register 0x0 0x20 0x00000000 0xFFFFFFFF GIE Global interrupt enable When GIE bit is set to 1, an interrupt is generated when an enabled global ECC error (GECCDEBWIE, GECCDEIE or GECCSEIE) occurs. 0 1 read-write GECCSEIE Global ECC single error interrupt enable When GECCSEIE bit is set to 1, an interrupt is generated when an ECC single error occurs during a read operation from RAM. 1 1 read-write GECCDEIE Global ECC double error interrupt enable When GECCDEIE bit is set to 1, an interrupt is generated when an ECC double detection error occurs during a read operation from RAM. 2 1 read-write GECCDEBWIE Global ECC double error on byte write (BW) interrupt enable When GECCDEBWIE bit is set to 1, an interrupt is generated when an ECC double detection error occurs during a byte write operation to RAM (incomplete word write). 3 1 read-write M1CR M1CR RAMECC monitor 1 configuration register 0x20 0x20 0x00000000 0xFFFFFFFF ECCSEIE ECC single error interrupt enable When ECCSEIE bit is set to 1, monitor x generates an interrupt when an ECC single error occurs during a read operation from RAM. 2 1 read-write ECCDEIE ECC double error interrupt enable When ECCDEIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a read operation from RAM. 3 1 read-write ECCDEBWIE ECC double error on byte write (BW) interrupt enable When ECCDEBWIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a byte write operation to RAM. 4 1 read-write ECCELEN ECC error latching enable When ECCELEN bit is set to 1, if an ECC error occurs (both for single error correction or double detection) during a read operation, the context (address, data and ECC code) that generated the error are latched to their respective registers. 5 1 read-write ECCSECEN ECC single error counter enable When ECCSECEN bit is set to 1, the occurrence counter is incremented when an ECC single error occurs during a read operation from RAM. 6 1 read-write ECCDECEN ECC double error counter enable When ECCDECEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a read operation from RAM. 7 1 read-write ECCDEBWCEN ECC double error on byte write (BW) counter enable When ECCDEBWCEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a byte write operation to RAM. 8 1 read-write ECCTEA ECC Test ECC access 16 2 read-write M1SR M1SR RAMECC monitor 1 status register 0x24 0x20 0x00000000 0xFFFFFFFF SEDCF ECC single error detected and corrected flag This bit is set by hardware. It is cleared by software by writing a 0 0 1 read-write DEDF ECC double error detected flag This bit is set by hardware. It is cleared by software by writing a 0 1 1 read-write DEBWDF ECC double error on byte write (BW) detected flag This bit is set by hardware. It is cleared by software by writing a 0 2 1 read-write M1FAR M1FAR RAMECC monitor 1 failing address register 0x28 0x20 0x00000000 0xFFFFFFFF FADD ECC error failing address When an ECC error occurs the FADD bitfield contains the address that generated the ECC error. 0 32 read-only M1FDRL M1FDRL RAMECC monitor 1 failing data low register 0x2C 0x20 0x00000000 0xFFFFFFFF FDATAL Failing data low When an ECC error occurs the FDATAL bitfield contains the LSB part of the data that generated the error. For 32-bit word SRAM, this bitfield contains the full memory word that generated the error. 0 32 read-only M1FDRH M1FDRH RAMECC monitor 1 failing data high register 0x30 0x20 0x00000000 0xFFFFFFFF FDATAH Failing data high (64-bit memory) When an ECC error occurs the FDATAH bitfield contains the MSB part of the data that generated the error. 0 32 read-only M1FECR M1FECR RAMECC monitor 1 failing ECC error code register 0x34 0x20 0x00000000 0xFFFFFFFF FEC Failing error code When an ECC error occurs the FEC bitfield contains the ECC failing code that generated the error. 0 32 read-only M2CR M2CR RAMECC monitor 2 configuration register 0x40 0x20 0x00000000 0xFFFFFFFF ECCSEIE ECC single error interrupt enable When ECCSEIE bit is set to 1, monitor x generates an interrupt when an ECC single error occurs during a read operation from RAM. 2 1 read-write ECCDEIE ECC double error interrupt enable When ECCDEIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a read operation from RAM. 3 1 read-write ECCDEBWIE ECC double error on byte write (BW) interrupt enable When ECCDEBWIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a byte write operation to RAM. 4 1 read-write ECCELEN ECC error latching enable When ECCELEN bit is set to 1, if an ECC error occurs (both for single error correction or double detection) during a read operation, the context (address, data and ECC code) that generated the error are latched to their respective registers. 5 1 read-write ECCSECEN ECC single error counter enable When ECCSECEN bit is set to 1, the occurrence counter is incremented when an ECC single error occurs during a read operation from RAM. 6 1 read-write ECCDECEN ECC double error counter enable When ECCDECEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a read operation from RAM. 7 1 read-write ECCDEBWCEN ECC double error on byte write (BW) counter enable When ECCDEBWCEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a byte write operation to RAM. 8 1 read-write ECCTEA ECC Test ECC access 16 2 read-write M2SR M2SR RAMECC monitor 2 status register 0x44 0x20 0x00000000 0xFFFFFFFF SEDCF ECC single error detected and corrected flag This bit is set by hardware. It is cleared by software by writing a 0 0 1 read-write DEDF ECC double error detected flag This bit is set by hardware. It is cleared by software by writing a 0 1 1 read-write DEBWDF ECC double error on byte write (BW) detected flag This bit is set by hardware. It is cleared by software by writing a 0 2 1 read-write M2FAR M2FAR RAMECC monitor 2 failing address register 0x48 0x20 0x00000000 0xFFFFFFFF FADD ECC error failing address When an ECC error occurs the FADD bitfield contains the address that generated the ECC error. 0 32 read-only M2FDRL M2FDRL RAMECC monitor 2 failing data low register 0x4C 0x20 0x00000000 0xFFFFFFFF FDATAL Failing data low When an ECC error occurs the FDATAL bitfield contains the LSB part of the data that generated the error. For 32-bit word SRAM, this bitfield contains the full memory word that generated the error. 0 32 read-only M2FDRH M2FDRH RAMECC monitor 2 failing data high register 0x50 0x20 0x00000000 0xFFFFFFFF FDATAH Failing data high (64-bit memory) When an ECC error occurs the FDATAH bitfield contains the MSB part of the data that generated the error. 0 32 read-only M2FECR M2FECR RAMECC monitor 2 failing ECC error code register 0x54 0x20 0x00000000 0xFFFFFFFF FEC Failing error code When an ECC error occurs the FEC bitfield contains the ECC failing code that generated the error. 0 32 read-only M3CR M3CR RAMECC monitor 3 configuration register 0x60 0x20 0x00000000 0xFFFFFFFF ECCSEIE ECC single error interrupt enable When ECCSEIE bit is set to 1, monitor x generates an interrupt when an ECC single error occurs during a read operation from RAM. 2 1 read-write ECCDEIE ECC double error interrupt enable When ECCDEIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a read operation from RAM. 3 1 read-write ECCDEBWIE ECC double error on byte write (BW) interrupt enable When ECCDEBWIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a byte write operation to RAM. 4 1 read-write ECCELEN ECC error latching enable When ECCELEN bit is set to 1, if an ECC error occurs (both for single error correction or double detection) during a read operation, the context (address, data and ECC code) that generated the error are latched to their respective registers. 5 1 read-write ECCSECEN ECC single error counter enable When ECCSECEN bit is set to 1, the occurrence counter is incremented when an ECC single error occurs during a read operation from RAM. 6 1 read-write ECCDECEN ECC double error counter enable When ECCDECEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a read operation from RAM. 7 1 read-write ECCDEBWCEN ECC double error on byte write (BW) counter enable When ECCDEBWCEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a byte write operation to RAM. 8 1 read-write ECCTEA ECC Test ECC access 16 2 read-write M3SR M3SR RAMECC monitor 3 status register 0x64 0x20 0x00000000 0xFFFFFFFF SEDCF ECC single error detected and corrected flag This bit is set by hardware. It is cleared by software by writing a 0 0 1 read-write DEDF ECC double error detected flag This bit is set by hardware. It is cleared by software by writing a 0 1 1 read-write DEBWDF ECC double error on byte write (BW) detected flag This bit is set by hardware. It is cleared by software by writing a 0 2 1 read-write M3FAR M3FAR RAMECC monitor 3 failing address register 0x68 0x20 0x00000000 0xFFFFFFFF FADD ECC error failing address When an ECC error occurs the FADD bitfield contains the address that generated the ECC error. 0 32 read-only M3FDRL M3FDRL RAMECC monitor 3 failing data low register 0x6C 0x20 0x00000000 0xFFFFFFFF FDATAL Failing data low When an ECC error occurs the FDATAL bitfield contains the LSB part of the data that generated the error. For 32-bit word SRAM, this bitfield contains the full memory word that generated the error. 0 32 read-only M3FDRH M3FDRH RAMECC monitor 3 failing data high register 0x70 0x20 0x00000000 0xFFFFFFFF FDATAH Failing data high (64-bit memory) When an ECC error occurs the FDATAH bitfield contains the MSB part of the data that generated the error. 0 32 read-only M3FECR M3FECR RAMECC monitor 3 failing ECC error code register 0x74 0x20 0x00000000 0xFFFFFFFF FEC Failing error code When an ECC error occurs the FEC bitfield contains the ECC failing code that generated the error. 0 32 read-only M4CR M4CR RAMECC monitor 4 configuration register 0x80 0x20 0x00000000 0xFFFFFFFF ECCSEIE ECC single error interrupt enable When ECCSEIE bit is set to 1, monitor x generates an interrupt when an ECC single error occurs during a read operation from RAM. 2 1 read-write ECCDEIE ECC double error interrupt enable When ECCDEIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a read operation from RAM. 3 1 read-write ECCDEBWIE ECC double error on byte write (BW) interrupt enable When ECCDEBWIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a byte write operation to RAM. 4 1 read-write ECCELEN ECC error latching enable When ECCELEN bit is set to 1, if an ECC error occurs (both for single error correction or double detection) during a read operation, the context (address, data and ECC code) that generated the error are latched to their respective registers. 5 1 read-write ECCSECEN ECC single error counter enable When ECCSECEN bit is set to 1, the occurrence counter is incremented when an ECC single error occurs during a read operation from RAM. 6 1 read-write ECCDECEN ECC double error counter enable When ECCDECEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a read operation from RAM. 7 1 read-write ECCDEBWCEN ECC double error on byte write (BW) counter enable When ECCDEBWCEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a byte write operation to RAM. 8 1 read-write ECCTEA ECC Test ECC access 16 2 read-write M4SR M4SR RAMECC monitor 4 status register 0x84 0x20 0x00000000 0xFFFFFFFF SEDCF ECC single error detected and corrected flag This bit is set by hardware. It is cleared by software by writing a 0 0 1 read-write DEDF ECC double error detected flag This bit is set by hardware. It is cleared by software by writing a 0 1 1 read-write DEBWDF ECC double error on byte write (BW) detected flag This bit is set by hardware. It is cleared by software by writing a 0 2 1 read-write M4FAR M4FAR RAMECC monitor 4 failing address register 0x88 0x20 0x00000000 0xFFFFFFFF FADD ECC error failing address When an ECC error occurs the FADD bitfield contains the address that generated the ECC error. 0 32 read-only M4FDRL M4FDRL RAMECC monitor 4 failing data low register 0x8C 0x20 0x00000000 0xFFFFFFFF FDATAL Failing data low When an ECC error occurs the FDATAL bitfield contains the LSB part of the data that generated the error. For 32-bit word SRAM, this bitfield contains the full memory word that generated the error. 0 32 read-only M4FDRH M4FDRH RAMECC monitor 4 failing data high register 0x90 0x20 0x00000000 0xFFFFFFFF FDATAH Failing data high (64-bit memory) When an ECC error occurs the FDATAH bitfield contains the MSB part of the data that generated the error. 0 32 read-only M4FECR M4FECR RAMECC monitor 4 failing ECC error code register 0x94 0x20 0x00000000 0xFFFFFFFF FEC Failing error code When an ECC error occurs the FEC bitfield contains the ECC failing code that generated the error. 0 32 read-only M5CR M5CR RAMECC monitor 5 configuration register 0xA0 0x20 0x00000000 0xFFFFFFFF ECCSEIE ECC single error interrupt enable When ECCSEIE bit is set to 1, monitor x generates an interrupt when an ECC single error occurs during a read operation from RAM. 2 1 read-write ECCDEIE ECC double error interrupt enable When ECCDEIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a read operation from RAM. 3 1 read-write ECCDEBWIE ECC double error on byte write (BW) interrupt enable When ECCDEBWIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a byte write operation to RAM. 4 1 read-write ECCELEN ECC error latching enable When ECCELEN bit is set to 1, if an ECC error occurs (both for single error correction or double detection) during a read operation, the context (address, data and ECC code) that generated the error are latched to their respective registers. 5 1 read-write ECCSECEN ECC single error counter enable When ECCSECEN bit is set to 1, the occurrence counter is incremented when an ECC single error occurs during a read operation from RAM. 6 1 read-write ECCDECEN ECC double error counter enable When ECCDECEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a read operation from RAM. 7 1 read-write ECCDEBWCEN ECC double error on byte write (BW) counter enable When ECCDEBWCEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a byte write operation to RAM. 8 1 read-write ECCTEA ECC Test ECC access 16 2 read-write M5SR M5SR RAMECC monitor 5 status register 0xA4 0x20 0x00000000 0xFFFFFFFF SEDCF ECC single error detected and corrected flag This bit is set by hardware. It is cleared by software by writing a 0 0 1 read-write DEDF ECC double error detected flag This bit is set by hardware. It is cleared by software by writing a 0 1 1 read-write DEBWDF ECC double error on byte write (BW) detected flag This bit is set by hardware. It is cleared by software by writing a 0 2 1 read-write M5FAR M5FAR RAMECC monitor 5 failing address register 0xA8 0x20 0x00000000 0xFFFFFFFF FADD ECC error failing address When an ECC error occurs the FADD bitfield contains the address that generated the ECC error. 0 32 read-only M5FDRL M5FDRL RAMECC monitor 5 failing data low register 0xAC 0x20 0x00000000 0xFFFFFFFF FDATAL Failing data low When an ECC error occurs the FDATAL bitfield contains the LSB part of the data that generated the error. For 32-bit word SRAM, this bitfield contains the full memory word that generated the error. 0 32 read-only M5FDRH M5FDRH RAMECC monitor 5 failing data high register 0xB0 0x20 0x00000000 0xFFFFFFFF FDATAH Failing data high (64-bit memory) When an ECC error occurs the FDATAH bitfield contains the MSB part of the data that generated the error. 0 32 read-only M5FECR M5FECR RAMECC monitor 5 failing ECC error code register 0xB4 0x20 0x00000000 0xFFFFFFFF FEC Failing error code When an ECC error occurs the FEC bitfield contains the ECC failing code that generated the error. 0 32 read-only RCC Reset and clock control RCC 0x58024400 0x0 0x800 registers RCC RCC global interrupt 5 CR CR RCC source control register 0x0 0x20 0x00000025 0xFFFFFFFF HSION HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW switch) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. 0 1 read-write HSION Off Clock Off 0 On Clock On 1 HSIKERON HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION. 1 1 read-write HSIRDY HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable. 2 1 read-only HSIRDYR NotReady Clock not ready 0 Ready Clock ready 1 HSIDIV HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored. 3 2 read-write HSIDIV Div1 No division 0 Div2 Division by 2 1 Div4 Division by 4 2 Div8 Division by 8 3 HSIDIVF HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. clock setting is completed) 5 1 read-only HSIDIVFR NotPropagated New HSIDIV ratio has not yet propagated to hsi_ck 0 Propagated HSIDIV ratio has propagated to hsi_ck 1 CSION CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. 7 1 read-write CSIRDY CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request). 8 1 read-only CSIKERON CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION. 9 1 read-write HSI48ON HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode. 12 1 read-write HSI48RDY HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable. 13 1 read-only HSEON HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. 16 1 read-write HSERDY HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. 17 1 read-only HSEBYP HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 18 1 read-write HSEBYP NotBypassed HSE crystal oscillator not bypassed 0 Bypassed HSE crystal oscillator bypassed with external clock 1 HSEEXT external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. 19 1 read-write HSECSSON HSE clock security system enable Set by software to enable clock security system on HSE. This bit is set only (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. 20 1 read-write PLL1ON PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1. 24 1 read-write PLL1RDY PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. 25 1 read-only PLL2ON PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if FMCCKP = 1, or XSPICKP = 1. 26 1 read-write PLL2RDY PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked. 27 1 read-only PLL3ON PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop or Standby mode. 28 1 read-write PLL3RDY PLL3 clock ready flag Set by hardware to indicate that the PLL3 is locked. 29 1 read-only HSICFGR HSICFGR RCC HSI calibration register 0x4 0x20 0x40000000 0xFFFFF000 HSICAL HSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value. 0 12 read-only HSITRIM HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt. Note: The reset value of the field is 0x40. 24 7 read-write CRRCR CRRCR RCC clock recovery RC register 0x8 0x20 0x00000000 0xFFFFF000 HSI48CAL Internal RC 48 MHz clock calibration Set by hardware by option byte loading. Read-only. 0 10 read-only CSICFGR CSICFGR RCC CSI calibration register 0xC 0x20 0x20000000 0xFFFFF000 CSICAL CSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value. 0 8 read-only CSITRIM CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_opt. Note: The reset value of the field is 0x20. 24 6 read-write CFGR CFGR RCC clock configuration register 0x10 0x20 0x00000000 0xFFFFFFFF SW system clock switch Set and reset by software to select system clock source (sys_ck). Set by hardware in order to force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode or in case of failure of the HSE when used directly or indirectly as system clock. others: reserved 0 3 read-write SW HSI HSI selected as system clock 0 CSI CSI selected as system clock 1 HSE HSE selected as system clock 2 PLL1 PLL1 selected as system clock 3 SWS system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. others: reserved 3 3 read-only SWSR HSI HSI oscillator used as system clock 0 CSI CSI oscillator used as system clock 1 HSE HSE oscillator used as system clock 2 PLL1 PLL1 used as system clock 3 STOPWUCK system clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10). 6 1 read-write STOPWUCK HSI HSI selected as wake up clock from system Stop 0 CSI CSI selected as wake up clock from system Stop 1 STOPKERWUCK kernel clock selection after a wake up from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. 7 1 read-write RTCPRE HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ... 8 6 read-write 0 63 TIMPRE timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. or 4, else it is equal to 4 x Frcc_pclkx_d2 Refer to Table 64: Ratio between clock timer and pclk for more details. 15 1 read-write TIMPRE DefaultX2 Timer kernel clock equal to 2x pclk by default 0 DefaultX4 Timer kernel clock equal to 4x pclk by default 1 MCO1PRE MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... 18 4 read-write 0 15 MCO1 Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved 22 3 read-write MCO1 HSI HSI selected for micro-controller clock output 0 LSE LSE selected for micro-controller clock output 1 HSE HSE selected for micro-controller clock output 2 PLL1_Q pll1_q selected for micro-controller clock output 3 HSI48 HSI48 selected for micro-controller clock output 4 MCO2PRE MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... 25 4 read-write 0 15 MCO2 microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved 29 3 read-write MCO2 SYSCLK System clock selected for micro-controller clock output 0 PLL2_P pll2_p selected for micro-controller clock output 1 HSE HSE selected for micro-controller clock output 2 PLL1_P pll1_p selected for micro-controller clock output 3 CSI CSI selected for micro-controller clock output 4 LSI LSI selected for micro-controller clock output 5 CDCFGR CDCFGR RCC CPU domain clock configuration register 0x18 0x20 0x00000000 0xFFFFFFFF CPRE CPU domain core prescaler Set and reset by software to control the CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset) 0 4 read-write BMCFGR BMCFGR RCC AHB clock configuration register 0x1C 0x20 0x00000000 0xFFFFFFFF HPRE Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk[5:1] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk[5:1] = rcc_aclk = sys_bus_ck. 0 4 read-write HPRE Div2 sys_ck divided by 2 8 Div4 sys_ck divided by 4 9 Div8 sys_ck divided by 8 10 Div16 sys_ck divided by 16 11 Div64 sys_ck divided by 64 12 Div128 sys_ck divided by 128 13 Div256 sys_ck divided by 256 14 Div512 sys_ck divided by 512 15 Div1 sys_ck not divided true APBCFGR APBCFGR RCC APB clocks configuration register 0x20 0x20 0x00000000 0xFFFFFFFF PPRE1 CPU domain APB1 prescaler Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE1 write. 0xx: rcc_pclk1 = sys_bus_ck (default after reset) 0 3 read-write PPRE2 CPU domain APB2 prescaler Set and reset by software to control the division factor of rcc_pclk2. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE2 write. 0xx: rcc_pclk2 = sys_bus_ck (default after reset) 4 3 read-write PPRE4 CPU domain APB4 prescaler Set and reset by software to control the division factor of rcc_pclk4. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE4 write. 0xx: rcc_pclk4 = sys_bus_ck (default after reset) 8 3 read-write PPRE5 CPU domain APB5 prescaler Set and reset by software to control the division factor of rcc_pclk5. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE5 write. 0xx: rcc_pclk5 = sys_bus_ck (default after reset) 12 3 read-write PLLCKSELR PLLCKSELR RCC PLLs clock source selection register 0x28 0x20 0x02020200 0xFFFFFFFF PLLSRC DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, PLLSRC must be set to 11. 0 2 read-write PLLSRC HSI HSI selected as PLL clock 0 CSI CSI selected as PLL clock 1 HSE HSE selected as PLL clock 2 None No clock sent to DIVMx dividers and PLLs 3 DIVM1 prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... 4 6 read-write 0 63 DIVM2 prescaler for PLL2 Set and cleared by software to configure the prescaler of the PLL2. The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ON = 1). In order to save power when PLL2 is not used, the value of DIVM2 must be set to 0. ... ... 12 6 read-write 0 63 DIVM3 prescaler for PLL3 Set and cleared by software to configure the prescaler of the PLL3. The hardware does not allow any modification of this prescaler when PLL3 is enabled (PLL3ON = 1). In order to save power when PLL3 is not used, the value of DIVM3 must be set to 0. ... ... 20 6 read-write 0 63 PLLCFGR PLLCFGR RCC PLLs configuration register 0x2C 0x20 0x00000000 0xFFFFFFFF PLL1FRACEN PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. 0 1 read-write PLL1FRACEN Reset Reset latch to tranfer FRACN to the Sigma-Delta modulator 0 Set Set latch to tranfer FRACN to the Sigma-Delta modulator 1 PLL1VCOSEL PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref1_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref1_ck must be between 1 and 2 MHz) 1 1 read-write PLL1VCOSEL WideVCO VCO frequency range 192 to 836 MHz 0 MediumVCO VCO frequency range 150 to 420 MHz 1 PLL1SSCGEN PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks. 2 1 read-write PLL1RGE PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 3 2 read-write PLL1RGE Range1 Frequency is between 1 and 2 MHz 0 Range2 Frequency is between 2 and 4 MHz 1 Range4 Frequency is between 4 and 8 MHz 2 Range8 Frequency is between 8 and 16 MHz 3 DIVP1EN PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. 5 1 read-write DIVP1EN Disabled Clock ouput is disabled 0 Enabled Clock output is enabled 1 DIVQ1EN PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. 6 1 read-write DIVR1EN PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. 7 1 read-write DIVS1EN PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used. 8 1 read-write DIVT1EN PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used. 9 1 read-write PLL2FRACEN PLL2 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL2FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. 11 1 read-write PLL2VCOSEL PLL2 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL2. This bit must be written before enabling the PLL2. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref2_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref2_ck must be between 1 and 2 MHz) 12 1 read-write PLL2SSCGEN PLL2 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL2, in order to reduce the amount of EMI peaks. 13 1 read-write PLL2RGE PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. These bits must be written before enabling the PLL2. 14 2 read-write DIVP2EN PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2DIVPEN and DIVP bits must be set to 0 when the pll2_p_ck is not used. 16 1 read-write DIVQ2EN PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL3DIVQEN and DIVQ bits must be set to 0 when the pll2_q_ck is not used. 17 1 read-write DIVR2EN PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. The hardware prevents writing this bit if FMCCKP = 1. To save power, PLL3DIVREN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. 18 1 read-write DIVS2EN PLL2 DIVS divider output enable Set and reset by software to enable the pll2_s_ck output of the PLL2. To save power, PLL2DIVSEN must be set to 0 when the pll2_s_ck is not used. The hardware prevents writing this bit if XSPICKP = 1. 19 1 read-write DIVT2EN PLL2 DIVT divider output enable Set and reset by software to enable the pll2_t_ck output of the PLL2. To save power, PLL2DIVTEN must be set to 0 when the pll2_t_ck is not used. The hardware prevents writing this bit if XSPICKP = 1. 20 1 read-write PLL3FRACEN PLL3 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL3FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. 22 1 read-write PLL3VCOSEL PLL3 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL3. This bit must be written before enabling the PLL3. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref2_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref2_ck must be between 1 and 2 MHz) 23 1 read-write PLL3SSCGEN PLL3 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL3, in order to reduce the amount of EMI peaks. 24 1 read-write PLL3RGE PLL3 input frequency range Set and reset by software to select the proper reference frequency range used for PLL3. These bits must be written before enabling the PLL3. 25 2 read-write DIVP3EN PLL3 DIVP divider output enable Set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3DIVREN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. 27 1 read-write DIVQ3EN PLL3 DIVQ divider output enable Set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3DIVREN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. 28 1 read-write DIVR3EN PLL3 DIVR divider output enable Set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3DIVREN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. 29 1 read-write DIVS3EN PLL3 DIVS divider output enable Set and reset by software to enable the pll3_s_ck output of the PLL3. To save power, PLL3DIVSEN must be set to 0 when the pll3_s_ck is not used. 30 1 read-write DIVT3EN PLL3 DIVT divider output enable Set and reset by software to enable the pll3_t_ck output of the PLL3. To save power, PLL1DIVTEN must be set to 0 when the pll3_t_ck is not used. 31 1 read-write PLL1DIVR1 PLL1DIVR1 RCC PLL1 dividers configuration register 1 0x30 0x20 0x01010280 0xFFFFFFFF DIVN1 multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0). ..........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x DIVN1, when fractional value 0 has been loaded into FRACN, with: DIVN1 between 8 and 420 The input frequency Fref1_ck must be between 1 and 16 MHz. 0 9 read-write DIVP PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1DIVPEN = 0. ... 9 7 read-write DIVQ PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1DIVQEN = 0. ... 16 7 read-write DIVR1 PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1DIVREN = 0. ... 24 7 read-write PLL1FRACR PLL1FRACR RCC PLL1 fractional divider register 0x34 0x20 0x00000000 0xFFFFFFFF FRACN fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (DIVN1 + (FRACN / 213)), with DIVN1 between 8 and 420 FRACN can be between 0 and 213- 1 The input frequency Fref1_ck must be between 1 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACLE to 0. Write the new fractional value into FRACN. Set the bit PLL1FRACLE to 1. 3 13 read-write PLL2DIVR1 PLL2DIVR1 RCC PLL2 dividers configuration register 1 0x38 0x20 0x01010280 0xFFFFFFFF DIVN2 multiplication factor for PLL2 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL2ON = PLL2RDY = 0). ..........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1 VCO output frequency = Fref2_ck x DIVN2, when fractional value 0 has been loaded into FRACN, with DIVN2 between 8 and 420 The input frequency Fref2_ck must be between 1 and 16MHz. 0 9 read-write DIVP PLL2 DIVP division factor Set and reset by software to control the frequency of the pll2_p_ck clock. These bits can be written only when the PLL2DIVPEN = 0. ... 9 7 read-write DIVQ PLL2 DIVQ division factor Set and reset by software to control the frequency of the pll2_q_ck clock. These bits can be written only when the PLL2DIVQEN = 0. ... 16 7 read-write DIVR2 PLL2 DIVR division factor Set and reset by software to control the frequency of the pll2_r_ck clock. These bits can be written only when the PLL2DIVREN = 0. ... 24 7 read-write PLL2FRACR PLL2FRACR RCC PLL2 fractional divider register 0x3C 0x20 0x00000000 0xFFFFFFFF FRACN fractional part of the multiplication factor for PLL2 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1 VCO output frequency = Fref2_ck x (DIVN2 + (FRACN / 213)), with DIVN2 between 8 and 420 FRACN can be between 0 and 213 - 1 The input frequency Fref2_ck must be between 1 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL2FRACLE to 0. Write the new fractional value into FRACN. Set the bit PLL2FRACLE to 1. 3 13 read-write PLL3DIVR1 PLL3DIVR1 RCC PLL3 dividers configuration register 1 0x40 0x20 0x01010280 0xFFFFFFFF DIVN3 Multiplication factor for PLL3 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL3ON = PLL3RDY = 0). ...........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1 VCO output frequency = Fref3_ck x DIVN3, when fractional value 0 has been loaded into FRACN, with: DIVN3 between 8 and 420 The input frequency Fref3_ck must be between 1 and 16MHz 0 9 read-write DIVP PLL3 DIVP division factor Set and reset by software to control the frequency of the pll3_p_ck clock. These bits can be written only when the PLL3DIVPEN = 0. ... 9 7 read-write DIVQ PLL3 DIVQ division factor Set and reset by software to control the frequency of the pll3_q_ck clock. These bits can be written only when the PLL3DIVQEN = 0. ... 16 7 read-write DIVR3 PLL3 DIVR division factor Set and reset by software to control the frequency of the pll3_r_ck clock. These bits can be written only when the PLL3DIVREN = 0. ... 24 7 read-write PLL3FRACR PLL3FRACR RCC PLL3 fractional divider register 0x44 0x20 0x00000000 0xFFFFFFFF FRACN fractional part of the multiplication factor for PLL3 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1 VCO output frequency = Fref3_ck x (DIVN3 + (FRACN / 213)), with DIVN3 between 8 and 420 FRACN can be between 0 and 213 - 1 The input frequency Fref3_ck must be between 1 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACLE to 0. Write the new fractional value into FRACN. Set the bit PLL1FRACLE to 1. 3 13 read-write CCIPR1 AHBPERCKSELR RCC AHB peripheral kernel clock selection register 0x4C 0x20 0x00000A00 0xFFFFFFFF FMCSEL FMC kernel clock source selection Set and reset by software. 0 2 read-write FMCSEL RCC_HCLK5 hclk5 selected as peripheral clock 0 PLL1_Q pll1_q selected as peripheral clock 1 PLL2_R pll2_r selected as peripheral clock 2 HSI_KER hsi_ker selected as peripheral clock 3 SDMMCSEL SDMMC1 and SDMMC2 kernel clock source selection Set and reset by software. 2 1 read-write SDMMCSEL PLL2_S pll1_s selected as peripheral clock 0 PLL2_T pll2_t selected as peripheral clock 1 OCTOSPI1SEL XSPI1 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock 4 2 read-write OCTOSPI1SEL RCC_HCLK5 hclk5 selected as peripheral clock 0 PLL2_S pll2_s_ck selected as peripheral clock 1 PLL2_T pll2_t_ck selected as peripheral clock 2 OCTOSPI2SEL XSPI2 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock 6 2 read-write OCTOSPI2SEL RCC_HCLK5 hclk5 selected as peripheral clock 0 PLL2_S pll2_s_ck selected as peripheral clock 1 PLL2_T pll2_t_ck selected as peripheral clock 2 USBREFCKSEL USBPHYC kernel clock frequency selection Set and reset by software. This field is used to indicate to the USBPHYC, the frequency of the reference kernel clock provided to the USBPHYC. others: reserved 8 4 read-write USBREFCKSEL MHz16 The clock frequency provided to the USBPHYC is 16 MHz 3 MHz19 The clock frequency provided to the USBPHYC is 19.2 MHz 8 MHz20 The clock frequency provided to the USBPHYC is 20MHz 9 MHz24 The clock frequency provided to the USBPHYC is 24 MHz 10 MHz32 The clock frequency provided to the USBPHYC is 32 MHz 11 MHz26 The clock frequency provided to the USBPHYC is 26 MHz 14 USBPHYCSEL USBPHYC kernel clock source selection Set and reset by software. 12 2 read-write USBPHYCSEL HSE_KER hse_ker_ck 0 HSE_KER_DIV2 hse_ker_ck / 2 1 PLL3_Q pll3_q_ck 2 OTGFSSEL OTGFS kernel clock source selection Set and reset by software. 14 2 read-write OTGFSSEL HSI48_KER hsi48_ker_ck 0 PLL3_Q pll3_q_ck 1 HSE_KER hse_ker_ck 2 CLK48 clk48mohci 3 ETH1_REF_CLK_SEL Ethernet reference clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 16 2 read-write ETH1_REF_CLK_SEL ETH_RMII_REF ETH_RMII_REF selected as peripheral clock 0 HSE_KER hse_ker selected as peripheral clock 1 ETH_CLK_FB eth_clk_fb selected as peripheral clock 2 ETHPHY_CLK_SEL Clock source selection for external Ethernet PHY Set and reset by software. 18 1 read-write ETHPHY_CLK_SEL HSE_KER hse_ker selected as clock source 0 PLL3_S pll3_s selected clock source 1 ADFSEL ADF kernel clock source selection Set and reset by software. Note: I2S_CKIN is an external clock taken from a pin. 20 3 read-write ADFSEL HCLK1 hclk1 selected as ADF clock 0 PLL2_p pll2_p_ck selected as ADF clock 1 PLL3_P pll3_p_ck selected as ADF clock 2 I2S_CLKIN I2S_CKIN selected as ADF clock 3 CSI_KER csi_ker_ck selected as ADF clock 4 HSI_KER hsi_ker_ck selected as ADF clock 5 ADCSEL SAR ADC kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 24 2 read-write ADCSEL PLL2_P pll2_p selected as peripheral clock 0 PLL3_R pll3_r selected as peripheral clock 1 PER per selected as peripheral clock 2 PSSISEL PSSI kernel clock source selection Set and reset by software. 27 1 read-write PSSISEL PLL3_R pll3_r selected as peripheral clock 0 PER per selected as kernel peripheral clock 1 CKPERSEL per_ck clock source selection 28 2 read-write CKPERSEL HSI HSI selected as peripheral clock 0 CSI CSI selected as peripheral clock 1 HSE HSE selected as peripheral clock 2 CCIPR2 APB1PERCKSELR RCC APB1 peripherals kernel clock selection register 0x50 0x20 0x00000000 0xFFFFFFFF UART234578SEL USART2,3, UART4,5,7,8 (APB1) kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 3 read-write UART234578SEL PCLK1 pclk1 selected as clock 0 PLL2_Q pll2_q selected as clock 1 PLL3_Q pll3_q selected as clock 2 HSI_KER hsi_ker selected as clock 3 CSI_KER csi_ker selected as clock 4 LSE lse selected as clock 5 SPI23SEL SPI/I2S2 and SPI/I2S3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. 4 3 read-write SPI23SEL PLL1_Q pll1_q selected as clock 0 PLL2_P pll2_p selected as clock 1 PLL3_P pll3_p selected as clock 2 I2S_CKIN I2S_CKIN selected as clock 3 PER per selected as clock 4 I2C23SEL I2C2, I2C3 kernel clock source selection Set and reset by software. 8 2 read-write I2C23SEL PCLK1 pclk1 selected as clock 0 PLL3_R pll3_r selected as clock 1 HSI_KER hsi_ker selected as clock 2 CSI_KER csi_ker selected as clock 3 I2C1I3C1SEL I2C1 or I3C1 kernel clock source selection Set and reset by software. 12 2 read-write I2C1I3C1SEL PCLK1 pclk1 selected as peripheral clock 0 PLL3_R pll3_r selected as peripheral clock 1 HSI_KER hsi_ker selected as peripheral clock 2 CSI_KER csi_ker selected as peripheral clock 3 LPTIM1SEL LPTIM1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 16 3 read-write LPTIM1SEL PCLK1 pclk1 selected as peripheral clock 0 PLL2_P pll2_p selected as peripheral clock 1 PLL3_R pll3_r selected as peripheral clock 2 LSE lse selected as peripheral clock 3 LSI lsi selected as peripheral clock 4 PER per selected as peripheral clock 5 FDCANSEL FDCAN kernel clock source selection 22 2 read-write FDCANSEL HSE_KER hse_ker selected as clock 0 PLL1_Q pll1_q selected as clock 1 PLL2_P pll2_p selected as clock 2 SPDIFRXSEL SPDIFRX kernel clock source selection 24 2 read-write SPDIFRXSEL PLL1_Q pll1_q selected as clock 0 PLL2_R pll2_r selected as clock 1 PLL3_R pll3_r selected as clock 2 HSI_KER hsi_ker selected as clock 3 CECSEL HDMI-CEC kernel clock source selection Set and reset by software. 28 2 read-write CECSEL LSE lse selected as clock 0 LSI lsi selected as clock 1 CSI_KER csi_ker divided by 122 selected as clock 2 CCIPR3 APB2PERCKSELR RCC APB2 peripherals kernel clock selection register 0x54 0x20 0x00000000 0xFFFFFFFF USART1SEL USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 3 read-write USART1SEL PCLK2 pclk2 selected as clock 0 PLL2_Q pll2_q selected as clock 1 PLL3_Q pll3_q selected as clock 2 HSI_KER hsi_ker selected as clock 3 CSI_KER csi_ker selected as clock 4 LSE lse selected as clock 5 SPI45SEL SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 4 3 read-write SPI45SEL PCLK2 pclk2 selected as clock 0 PLL2_Q pll2_q is selected as clock 1 PLL3_Q pll3_q is selected as clock 2 HSI_KER hsi_ker is selected as clock 3 CSI_KER csi_ker is selected as clock 4 HSE_KER hse_ker is selected as clock 5 SPI1SEL SPI/I2S1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. 8 3 read-write SPI1SEL PLL1_Q pll1_q selected as SPI/I2S1 and 7 clock 0 PLL2_P pll2_p selected as SPI/I2S1 and 7 clock 1 PLL3_P pll3_p selected as SPI/I2S1 and 7 clock 2 I2S_CKIN I2S_CKIN selected as SPI/I2S1 and 7 clock 3 PER per selected as SPI/I2S1,and 7 clock 4 SAI1SEL SAI1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. 16 3 read-write SAI1SEL PLL1_Q pll1_q selected as clock 0 PLL2_P pll2_p selected as clock 1 PLL3_P pll3_p selected as clock 2 I2S_CKIN I2S_CKIN selected as clock 3 PER per selected as clock 4 SAI2SEL SAI2 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see Figure 51). 20 3 read-write SAI2SEL PLL1_Q pll1_q selected as clock 0 PLL2_P pll2_p selected as clock 1 PLL3_P pll3_p selected as clock 2 I2S_CKIN I2S_CKIN selected as clock 3 PER per selected as clock 4 SPDIFRX_SYMB spdifrx_symb selected as clock 5 CCIPR4 APB45PERCKSELR RCC APB4,5 peripherals kernel clock selection register 0x58 0x20 0x00000000 0xFFFFFFFF LPUART1SEL LPUART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 3 read-write LPUART1SEL PCLK4 pclk4 selected as peripheral clock 0 PLL2_Q pll2_q selected as peripheral clock 1 PLL3_Q pll3_q selected as peripheral clock 2 HSI_KER hsi_ker selected as peripheral clock 3 CSI_KER csi_ker selected as peripheral clock 4 LSE lse selected as peripheral clock 5 SPI6SEL SPI/I2S6 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 4 3 read-write SPI6SEL PCLK4 pclk4 selected as peripheral clock 0 PLL2_Q pll2_q selected as peripheral clock 1 PLL3_Q pll3_q selected as peripheral clock 2 HSI_KER hsi_ker selected as peripheral clock 3 CSI_KER csi_ker selected as peripheral clock 4 HSE_KER hse_ker selected as peripheral clock 5 LPTIM23SEL LPTIM2 and LPTIM3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 8 3 read-write LPTIM23SEL PCLK4 pclk4 selected as peripheral clock 0 PLL2_P pll2_p selected as peripheral clock 1 PLL3_R pll3_r selected as peripheral clock 2 LSE lse selected as peripheral clock 3 LSI lsi selected as peripheral clock 4 PER per selected as peripheral clock 5 LPTIM45SEL LPTIM4, and LPTIM5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 12 3 read-write LPTIM45SEL PCLK4 pclk4 selected as peripheral clock 0 PLL2_P pll2_p selected as peripheral clock 1 PLL3_R pll3_r selected as peripheral clock 2 LSE lse selected as peripheral clock 3 LSI lsi selected as peripheral clock 4 PER per selected as peripheral clock 5 CIER CIER RCC clock source interrupt enable register 0x60 0x20 0x00000000 0xFFFFFFFF LSIRDYIE LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0 1 read-write LSIRDYIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 LSERDYIE LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. 1 1 read-write HSIRDYIE HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. 2 1 read-write HSERDYIE HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. 3 1 read-write CSIRDYIE CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. 4 1 read-write HSI48RDYIE HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. 5 1 read-write PLL1RDYIE PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. 6 1 read-write PLL2RDYIE PLL2 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL2 lock. 7 1 read-write PLL3RDYIE PLL3 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL3 lock. 8 1 read-write LSECSSIE LSE clock security system interrupt enable Set and reset by software to enable/disable interrupt caused by the clock security system (CSS) on external 32 kHz oscillator. 9 1 read-write CIFR CIFR RCC clock source interrupt flag register 0x64 0x20 0x00000000 0xFFFFFFFF LSIRDYF LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. 0 1 read-only LSIRDYFR NotInterrupted No clock ready interrupt 0 Interrupted Clock ready interrupt 1 LSERDYF LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. 1 1 read-only HSIRDYF HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. 2 1 read-only HSERDYF HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. 3 1 read-only CSIRDYF CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. 4 1 read-only HSI48RDYF HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. 5 1 read-only PLL1RDYF PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. 6 1 read-only PLL2RDYF PLL2 ready interrupt flag Reset by software by writing PLL2RDYC bit. Set by hardware when the PLL2 locks and PLL2RDYIE is set. 7 1 read-only PLL3RDYF PLL3 ready interrupt flag Reset by software by writing PLL3RDYC bit. Set by hardware when the PLL3 locks and PLL3RDYIE is set. 8 1 read-only LSECSSF LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set. 9 1 read-only HSECSSF HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. 10 1 read-only CICR CICR RCC clock source interrupt clear register 0x68 0x20 0x00000000 0xFFFFFFFF LSIRDYC LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done. 0 1 read-write LSIRDYC Clear Clear interrupt flag 1 LSERDYC LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done. 1 1 read-write HSIRDYC HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done. 2 1 read-write HSERDYC HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done. 3 1 read-write CSIRDYC CSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done. 4 1 read-write HSI48RDYC HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. 5 1 read-write PLL1RDYC PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. 6 1 read-write PLL2RDYC PLL2 ready interrupt clear Set by software to clear PLL2RDYF. Reset by hardware when clear done. 7 1 read-write PLL3RDYC PLL3 ready interrupt clear Set by software to clear PLL3RDYF. Reset by hardware when clear done. 8 1 read-write LSECSSC LSE clock security system interrupt clear Set by software to clear LSECSSF. Reset by hardware when clear done. 9 1 read-write HSECSSC HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. 10 1 read-write BDCR BDCR RCC Backup domain control register 0x70 0x20 0x00000010 0xFFFFFFFF LSEON LSE oscillator enabled Set and reset by software. 0 1 read-write LSEON Off LSE oscillator Off 0 On LSE oscillator On 1 LSERDY LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0. 1 1 read-only LSERDYR NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEBYP LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1) 2 1 read-write LSEBYP NotBypassed LSE crystal oscillator not bypassed 0 Bypassed LSE crystal oscillator bypassed with external clock 1 LSEDRV LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. 3 2 read-write LSEDRV Lowest Lowest LSE oscillator driving capability 0 MediumLow Medium low LSE oscillator driving capability 1 MediumHigh Medium high LSE oscillator driving capability 2 Highest Highest LSE oscillator driving capability 3 LSECSSON LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit can only be disabled, After a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. After a back-up domain reset 5 1 read-write LSECSSON SecurityOff Clock security system on 32 kHz oscillator off 0 SecurityOn Clock security system on 32 kHz oscillator on 1 LSECSSD LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator. 6 1 read-only LSECSSDR NoFailure No failure detected on 32 kHz oscillator 0 Failure Failure detected on 32 kHz oscillator 1 LSEEXT low-speed external clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled. 7 1 read-write RTCSEL RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). 8 2 read-writeOnce RTCSEL NoClock No clock 0 LSE LSE oscillator clock used as RTC clock 1 LSI LSI oscillator clock used as RTC clock 2 HSE HSE oscillator clock divided by a prescaler used as RTC clock 3 LSECSSRA Re-Arm the LSECSS function Set by software. After a LSE failure detection, the software application can re-enable the LSECSS by writing this bit to 1. Reading this bit returns the written value. Prior to set this bit to 1, LSECSSON must be set to 0. Please refer to Section : CSS on LSE for details. 12 1 read-write RTCEN RTC clock enable Set and reset by software. 15 1 read-write RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 VSWRST VSwitch domain software reset Set and reset by software. To generate a VSW reset, it is recommended to write this bit to 1, then back to 0. 16 1 read-write VSWRST NotActivated Reset not activated 0 Reset Resets the entire VSW domain 1 CSR CSR RCC clock control and status register 0x74 0x20 0x00000000 0xFFFFFFFF LSION LSI oscillator enable Set and reset by software. 0 1 read-write LSION Off LSI oscillator Off 0 On LSI oscillator On 1 LSIRDY LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC. 1 1 read-only LSIRDYR NotReady LSI oscillator not ready 0 Ready LSI oscillator ready 1 AHB5RSTR AHB5RSTR RCC AHB5 peripheral reset register 0x7C 0x20 0x00000000 0xFFFFFFFF HPDMA1RST HPDMA1 block reset Set and reset by software. 0 1 read-write HPDMA1RST Reset Reset the selected module 1 DMA2DRST DMA2D block reset Set and reset by software. 1 1 read-write JPEGRST JPEG block reset Set and reset by software. 3 1 read-write FMCRST FMC and MCE3 blocks reset Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. 4 1 read-write XSPI1RST XSPI1 and MCE1 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 5 1 read-write SDMMC1RST SDMMC1 and DB_SDMMC1 blocks reset Set and reset by software. 8 1 read-write XSPI2RST XSPI2 and MCE2 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 12 1 read-write XSPIMRST XSPIM reset Set and reset by software. 14 1 read-write GFXMMURST GFXMMU block reset Set and reset by software. 19 1 read-write GPURST GPU block reset Set and reset by software. 20 1 read-write AHB1RSTR AHB1RSTR RCC AHB1 peripheral reset register 0x80 0x20 0x00000000 0xFFFFFFFF GPDMA1RST GPDMA1 blocks reset Set and reset by software. 4 1 read-write GPDMA1RST Reset Reset the selected module 1 ADC12RST ADC1 and 2 blocks reset Set and reset by software. 5 1 read-write ETH1MACRST ETH1 block reset Set and reset by software. 15 1 read-write OTGHSRST OTGHS block reset Set and reset by software. 25 1 read-write USBPHYCRST USBPHYC block reset Set and reset by software. 26 1 read-write OTGFSRST OTGFS block reset Set and reset by software. 27 1 read-write ADFRST ADF block reset Set and reset by software. 31 1 read-write AHB2RSTR AHB2RSTR RCC AHB2 peripheral reset register 0x84 0x20 0x00000000 0xFFFFFFFF PSSIRST PSSI block reset Set and reset by software. 1 1 read-write PSSIRST Reset Reset the selected module 1 SDMMC2RST SDMMC2 and SDMMC2 delay blocks reset Set and reset by software. 9 1 read-write CORDICRST CORDIC reset Set and reset by software. 14 1 read-write AHB4RSTR AHB4RSTR RCC AHB4 peripheral reset register 0x88 0x20 0x00000000 0xFFFFFFFF GPIOARST GPIOA block reset Set and reset by software. 0 1 read-write GPIOARST Reset Reset the selected module 1 GPIOBRST GPIOB block reset Set and reset by software. 1 1 read-write GPIOCRST GPIOC block reset Set and reset by software. 2 1 read-write GPIODRST GPIOD block reset Set and reset by software. 3 1 read-write GPIOERST GPIOE block reset Set and reset by software. 4 1 read-write GPIOFRST GPIOF block reset Set and reset by software. 5 1 read-write GPIOGRST GPIOG block reset Set and reset by software. 6 1 read-write GPIOHRST GPIOH block reset Set and reset by software. 7 1 read-write GPIOMRST GPIOM block reset Set and reset by software. 12 1 read-write GPIONRST GPION block reset Set and reset by software. 13 1 read-write GPIOORST GPIOO block reset Set and reset by software. 14 1 read-write GPIOPRST GPIOP block reset Set and reset by software. 15 1 read-write CRCRST CRC block reset Set and reset by software. 19 1 read-write APB5RSTR APB5RSTR RCC APB5 peripheral reset register 0x8C 0x20 0x00000000 0xFFFFFFFF LTDCRST LTDC block reset Set and reset by software. 1 1 read-write LTDCRST Reset Reset the selected module 1 DCMIPPRST DCMIPP block reset Set and reset by software. 2 1 read-write GFXTIMRST GFXTIM block reset Set and reset by software. 4 1 read-write APB1LRSTR APB1RSTR1 RCC APB1 peripheral reset register 1 0x90 0x20 0x00000000 0xFFFFFFFF TIM2RST TIM2 block reset Set and reset by software. 0 1 read-write TIM2RST Reset Reset the selected module 1 TIM3RST TIM3 block reset Set and reset by software. 1 1 read-write TIM4RST TIM4 block reset Set and reset by software. 2 1 read-write TIM5RST TIM5 block reset Set and reset by software. 3 1 read-write TIM6RST TIM6 block reset Set and reset by software. 4 1 read-write TIM7RST TIM7 block reset Set and reset by software. 5 1 read-write TIM12RST TIM12 block reset Set and reset by software. 6 1 read-write TIM13RST TIM13 block reset Set and reset by software. 7 1 read-write TIM14RST TIM14 block reset Set and reset by software. 8 1 read-write LPTIM1RST LPTIM1 block reset Set and reset by software. 9 1 read-write SPI2RST SPI2S2 block reset Set and reset by software. 14 1 read-write SPI3RST SPI2S3 block reset Set and reset by software. 15 1 read-write SPDIFRXRST SPDIFRX block reset Set and reset by software. 16 1 read-write USART2RST USART2 block reset Set and reset by software. 17 1 read-write USART3RST USART3 block reset Set and reset by software. 18 1 read-write UART4RST UART4 block reset Set and reset by software. 19 1 read-write UART5RST UART5 block reset Set and reset by software. 20 1 read-write I2C1_I3C1RST I2C1/I3C1 block reset Set and reset by software. 21 1 read-write I2C2RST I2C2 block reset Set and reset by software. 22 1 read-write I2C3RST I2C3 block reset Set and reset by software. 23 1 read-write HDMICECRST HDMI-CEC block reset Set and reset by software. 27 1 read-write UART7RST UART7 block reset Set and reset by software. 30 1 read-write UART8RST UART8 block reset Set and reset by software. 31 1 read-write APB1HRSTR APB1RSTR2 RCC APB1 peripheral reset register 2 0x94 0x20 0x00000000 0xFFFFFFFF CRSRST clock recovery system reset Set and reset by software. 1 1 read-write CRSRST Reset Reset the selected module 1 MDIOSRST MDIOS block reset Set and reset by software. 5 1 read-write FDCANRST FDCAN block reset Set and reset by software. 8 1 read-write UCPDRST UCPD block reset Set and reset by software. 27 1 read-write APB2RSTR APB2RSTR RCC APB2 peripheral reset register 0x98 0x20 0x00000000 0xFFFFFFFF TIM1RST TIM1 block reset Set and reset by software. 0 1 read-write TIM1RST Reset Reset the selected module 1 USART1RST USART1 block reset Set and reset by software. 4 1 read-write SPI1RST SPI2S1 block reset Set and reset by software. 12 1 read-write SPI4RST SPI4 block reset Set and reset by software. 13 1 read-write TIM15RST TIM15 block reset Set and reset by software. 16 1 read-write TIM16RST TIM16 block reset Set and reset by software. 17 1 read-write TIM17RST TIM17 block reset Set and reset by software. 18 1 read-write TIM9RST TIM9 block reset Set and reset by software. 19 1 read-write SPI5RST SPI5 block reset Set and reset by software. 20 1 read-write SAI1RST SAI1 block reset Set and reset by software. 22 1 read-write SAI2RST SAI2 block reset Set and reset by software. 23 1 read-write APB4RSTR APB4RSTR RCC APB4 peripheral reset register 0x9C 0x20 0x00000000 0xFFFFFFFF SBSRST SBS block reset Set and reset by software. 1 1 read-write SBSRST Reset Reset the selected module 1 LPUART1RST LPUART1 block reset Set and reset by software. 3 1 read-write SPI6RST SPI/I2S6 block reset Set and reset by software. 5 1 read-write LPTIM2RST LPTIM2 block reset Set and reset by software. 9 1 read-write LPTIM3RST LPTIM3 block reset Set and reset by software. 10 1 read-write LPTIM4RST LPTIM4 block reset Set and reset by software. 11 1 read-write LPTIM5RST LPTIM5 block reset Set and reset by software. 12 1 read-write VREFRST VREF block reset Set and reset by software. 15 1 read-write TMPSENSRST TMPSENS block reset Set and reset by software. 26 1 read-write AHB3RSTR AHB3RSTR RCC AHB3 peripheral reset register 0xA4 0x20 0x00000000 0xFFFFFFFF RNGRST random number generator block reset Set and reset by software. 0 1 read-write RNGRST Reset Reset the selected module 1 HASHRST HASH block reset Set and reset by software. 1 1 read-write CRYPRST CRYP block reset Set and reset by software. 2 1 read-write SAESRST SAES block reset Set and reset by software. 4 1 read-write PKARST PKA block reset Set and reset by software. 6 1 read-write CKGDISR CKGDISR RCC AXI clocks gating disable register 0xB0 0x20 0x80000000 0xFFFFFFFF AXICKG AXI interconnect matrix clock gating disable This bit is set and reset by software. 0 1 read-write AHBMCKG AXI master AHB clock gating disable This bit is set and reset by software. 1 1 read-write SDMMC1CKG AXI master SDMMC1 clock gating disable This bit is set and reset by software. 2 1 read-write HPDMA1CKG AXI master HPDMA1 clock gating disable This bit is set and reset by software. 3 1 read-write CPUCKG AXI master CPU clock gating disable This bit is set and reset by software. 4 1 read-write GPUS0CKG AXI master 0 GPU clock gating disable This bit is set and reset by software. 5 1 read-write GPUS1CKG AXI master 1 GPU clock gating disable This bit is set and reset by software. 6 1 read-write GPUCLCKG AXI master cache GPU clock gating disable This bit is set and reset by software. 7 1 read-write DCMIPPCKG AXI master DCMIPP clock gating disable This bit is set and reset by software. 8 1 read-write DMA2DCKG AXI master DMA2D clock gating disable This bit is set and reset by software. 9 1 read-write GFXMMUSCKG AXI matrix slave GFXMMU clock gating disable This bit is set and reset by software. 10 1 read-write LTDCCKG AXI master LTDC clock gating disable This bit is set and reset by software. 11 1 read-write GFXMMUMCKG AXI master GFXMMU clock gating disable This bit is set and reset by software. 12 1 read-write AHBSCKG AXI slave AHB clock gating disable This bit is set and reset by software. 13 1 read-write FMCCKG AXI slave FMC and MCE3 clock gating disable This bit is set and reset by software. 14 1 read-write XSPI1CKG AXI slave XSPI1 and MCE1 clock gating disable This bit is set and reset by software. 15 1 read-write XSPI2CKG AXI slave XSPI2 and MCE2 clock gating disable This bit is set and reset by software. 16 1 read-write AXIRAM4CKG AXI matrix slave SRAM4 clock gating disable This bit is set and reset by software. 17 1 read-write AXIRAM3CKG AXI matrix slave SRAM3 clock gating disable This bit is set and reset by software. 18 1 read-write AXIRAM2CKG AXI slave SRAM2 clock gating disable This bit is set and reset by software. 19 1 read-write AXIRAM1CKG AXI slave SRAM1 / error code correction (ECC) clock gating disable This bit is set and reset by software. 20 1 read-write FLITFCKG AXI slave Flash interface (FLIFT) clock gating disable This bit is set and reset by software. 21 1 read-write EXTICKG EXTI clock gating disable This bit is set and reset by software. 30 1 read-write JTAGCKG JTAG automatic clock gating disabling This bit is set and reset by software. 31 1 read-write PLL1DIVR2 PLL1DIVR2 RCC PLL1 dividers configuration register 2 0xC0 0x20 0x00000101 0xFFFFFFFF DIVS PLL1 DIVS division factor Set and reset by software to control the frequency of the pll1_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL1DIVSEN = 0. 0 3 read-write DIVT PLL1 DIVT division factor Set and reset by software to control the frequency of the pll1_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL1DIVTEN = 0. 8 3 read-write PLL2DIVR2 PLL2DIVR2 RCC PLL2 dividers configuration register 2 0xC4 0x20 0x00000101 0xFFFFFFFF DIVS PLL2 DIVS division factor Set and reset by software to control the frequency of the pll2_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL2DIVSEN = 0. 0 3 read-write DIVT PLL2 DIVT division factor Set and reset by software to control the frequency of the pll2_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL2DIVTEN = 0. 8 3 read-write PLL3DIVR2 PLL3DIVR2 RCC PLL3 dividers configuration register 2 0xC8 0x20 0x00000101 0xFFFFFFFF DIVS PLL3 DIVS division factor Set and reset by software to control the frequency of the pll3_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL3DIVSEN = 0. 0 3 read-write DIVT PLL3 DIVT division factor Set and reset by software to control the frequency of the pll3_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL3DIVTEN = 0. 8 3 read-write PLL1SSCGR PLL1SSCGR RCC PLL1 Spread Spectrum Clock Generator register 0xCC 0x20 0x00000000 0xFFFFFFFF MOD_PER Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator. 0 13 read-write TPDFN_DIS1 Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function. 13 1 read-write RPDFN_DIS1 Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function. 14 1 read-write DWNSPREAD1 Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode. 15 1 read-write INC_STEP Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator. 16 15 read-write PLL2SSCGR PLL2SSCGR RCC PLL2 Spread Spectrum Clock Generator register 0xD0 0x20 0x00000000 0xFFFFFFFF MOD_PER Modulation Period Adjustment for PLL2 Set and reset by software to adjust the modulation period of the clock spreading generator. 0 13 read-write TPDFN_DIS2 Dithering TPDF noise control for PLL2 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function. 13 1 read-write RPDFN_DIS2 Dithering RPDF noise control for PLL2 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function. 14 1 read-write DWNSPREAD2 Spread spectrum clock generator mode for PLL2 Set and reset by software to select the clock spreading mode. 15 1 read-write INC_STEP Modulation Depth Adjustment for PLL2 Set and reset by software to adjust the modulation depth of the clock spreading generator. 16 15 read-write PLL3SSCGR PLL3SSCGR RCC PLL3 Spread Spectrum Clock Generator register 0xD4 0x20 0x00000000 0xFFFFFFFF MOD_PER Modulation Period Adjustment for PLL3 Set and reset by software to adjust the modulation period of the clock spreading generator. 0 13 read-write TPDFN_DIS3 Dithering TPDF noise control for PLL3 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function. 13 1 read-write RPDFN_DIS3 Dithering RPDF noise control for PLL3 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function. 14 1 read-write DWNSPREAD3 Spread spectrum clock generator mode for PLL3 Set and reset by software to select the clock spreading mode. 15 1 read-write INC_STEP Modulation Depth Adjustment for PLL3 Set and reset by software to adjust the modulation depth of the clock spreading generator. 16 15 read-write CKPROTR CKPROTR RCC clock protection register 0x100 0x20 0x00000000 0xFFFFFFFF XSPICKP XSPI clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the XSPIs. The following fields cannot be modified when this bit is set to 1: PLL2ON, PLL2DIVSEN, PLL2DIVTEN, HSEON, HSION, CSION, XSPIxEN, OCTOSPIxLPEN, OCTOSPIxRST. 0 1 read-write FMCCKP FMC clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the FMC. The following fields cannot be modified when this bit is set to 1: PLL1ON, PLL2ON, PLL1DIVQEN, PLL2DIVREN, HSEON, HSION, CSION, FMCEN, FMCLPEN, FMCRST. 1 1 read-write XSPI1SWP XSPI1 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector. 4 3 read-only XSPI2SWP XSPI2 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector. 8 3 read-only FMCSWP FMC kernel clock switch position Set by hardware. This field can be used to verify the real position of FMC kernel switch selector. 12 3 read-only RSR RSR RCC Reset status register 0x130 0x20 0x00E00000 0xFFFFFFFF RMVF remove reset flag Set and reset by software to reset the value of the reset flags. 16 1 read-write RMVF NotActivated Reset not activated 0 Reset Reset the reset status flags 1 OBLRSTF Option byte loading reset flag (1) Reset by software by the RMVF bit. Set by hardware when a reset from the option byte loading occurs. 17 1 read-only OBLRSTFR NoResetOccurred No reset occurred for block 0 ResetOccurred Reset occurred for block 1 BORRSTF BOR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). 21 1 read-only PINRSTF pin reset flag (NRST) (1) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. 22 1 read-only PORRSTF POR/PDR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs. 23 1 read-only SFTRSTF system reset from CPU reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7. 24 1 read-only IWDGRSTF independent watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. 26 1 read-only WWDGRSTF window watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. 28 1 read-only LPWRRSTF reset due to illegal Stop or Standby flag Reset by software by writing the RMVF bit. Set by hardware when the CPU goes erroneously in Stop or Standby mode, 30 1 read-only AHB5ENR AHB5ENR RCC AHB5 clock enable register 0x134 0x20 0x00000000 0xFFFFFFFF HPDMA1EN HPDMA1 peripheral clock enable Set and reset by software. 0 1 read-write HPDMA1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 DMA2DEN DMA2D peripheral clock enable Set and reset by software. 1 1 read-write JPEGEN JPEG peripheral clock enable Set and reset by software. 3 1 read-write FMCEN FMC and MCE3 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock. 4 1 read-write XSPI1EN XSPI1 and MCE1 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 5 1 read-write SDMMC1EN SDMMC1 and DB_SDMMC1 peripheral clocks enable Set and reset by software. 8 1 read-write XSPI2EN XSPI2 and MCE2 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 12 1 read-write XSPIMEN XSPIM peripheral clock enable Set and reset by software. 14 1 read-write GFXMMUEN GFXMMU peripheral clock enable Set and reset by software. 19 1 read-write GPUEN GPU peripheral clock enable Set and reset by software. 20 1 read-write AHB1ENR AHB1ENR RCC AHB1 clock enable register 0x138 0x20 0x00000000 0xFFFFFFFF GPDMA1EN GPDMA1 clock enable Set and reset by software. 4 1 read-write GPDMA1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 ADC12EN ADC1 and 2 peripheral clocks enable Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the hclk1 bus interface clock. 5 1 read-write ETH1MACEN ETH1 MAC peripheral clock enable Set and reset by software. 15 1 read-write ETH1TXEN ETH1 transmission clock enable Set and reset by software. 16 1 read-write ETH1RXEN ETH1 reception clock enable Set and reset by software. 17 1 read-write OTGHSEN OTGHS clocks enable Set and reset by software. 25 1 read-write USBPHYCEN USBPHYC clocks enable Set and reset by software. 26 1 read-write OTGFSEN OTGFS peripheral clocks enable Set and reset by software. 27 1 read-write ADFEN ADF clocks enable Set and reset by software. 31 1 read-write AHB2ENR AHB2ENR RCC AHB2 clock enable register 0x13C 0x20 0x00000000 0xFFFFFFFF PSSIEN PSSI peripheral clocks enable Set and reset by software. 1 1 read-write PSSIEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 SDMMC2EN SDMMC2 and SDMMC2 delay clock enable Set and reset by software. 9 1 read-write CORDICEN CORDIC clock enable Set and reset by software. 14 1 read-write SRAM1EN SRAM1 clock enable Set and reset by software. 29 1 read-write SRAM2EN SRAM2 clock enable Set and reset by software. 30 1 read-write AHB4ENR AHB4ENR RCC AHB4 clock enable register 0x140 0x20 0x00000000 0xFFFFFFFF GPIOAEN GPIOA peripheral clock enable Set and reset by software. 0 1 read-write GPIOAEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 GPIOBEN GPIOB peripheral clock enable Set and reset by software. 1 1 read-write GPIOCEN GPIOC peripheral clock enable Set and reset by software. 2 1 read-write GPIODEN GPIOD peripheral clock enable Set and reset by software. 3 1 read-write GPIOEEN GPIOE peripheral clock enable Set and reset by software. 4 1 read-write GPIOFEN GPIOF peripheral clock enable Set and reset by software. 5 1 read-write GPIOGEN GPIOG peripheral clock enable Set and reset by software. 6 1 read-write GPIOHEN GPIOH peripheral clock enable Set and reset by software. 7 1 read-write GPIOMEN GPIOM peripheral clock enable Set and reset by software. 12 1 read-write GPIONEN GPION peripheral clock enable Set and reset by software. 13 1 read-write GPIOOEN GPIOO peripheral clock enable Set and reset by software. 14 1 read-write GPIOPEN GPIOP peripheral clock enable Set and reset by software. 15 1 read-write CRCEN CRC clock enable Set and reset by software. 19 1 read-write BKPRAMEN Backup RAM clock enable Set and reset by software. 28 1 read-write APB5ENR APB5ENR RCC APB5 clock enable register 0x144 0x20 0x00000000 0xFFFFFFFF LTDCEN LTDC peripheral clock enable Provides the pixel clock (ltdc_clk) to the LTDC block. Set and reset by software. 1 1 read-write LTDCEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 DCMIPPEN DCMIPP peripheral clock enable Set and reset by software. 2 1 read-write GFXTIMEN GFXTIM peripheral clock enable Set and reset by software. 4 1 read-write APB1LENR APB1ENR1 RCC APB1 clock enable register 1 0x148 0x20 0x00000000 0xFFFFFFFF TIM2EN TIM2 peripheral clock enable Set and reset by software. 0 1 read-write TIM2EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM3EN TIM3 peripheral clock enable Set and reset by software. 1 1 read-write TIM4EN TIM4 peripheral clock enable Set and reset by software. 2 1 read-write TIM5EN TIM5 peripheral clock enable Set and reset by software. 3 1 read-write TIM6EN TIM6 peripheral clock enable Set and reset by software. 4 1 read-write TIM7EN TIM7 peripheral clock enable Set and reset by software. 5 1 read-write TIM12EN TIM12 peripheral clock enable Set and reset by software. 6 1 read-write TIM13EN TIM13 peripheral clock enable Set and reset by software. 7 1 read-write TIM14EN TIM14 peripheral clock enable Set and reset by software. 8 1 read-write LPTIM1EN LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to clk_lpt input, and the rcc_pclk1 bus interface clock. 9 1 read-write WWDGEN WWDG clock enable Set by software, and reset by hardware when a system reset occurs. 11 1 read-write SPI2EN SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock. 14 1 read-write SPI3EN SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock. 15 1 read-write SPDIFRXEN SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to SPDIFRX_CLK input, and the rcc_pclk1 bus interface clock. 16 1 read-write USART2EN USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. 17 1 read-write USART3EN USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. 18 1 read-write UART4EN UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. 19 1 read-write UART5EN UART5 peripheral clocks enable Set and reset by software. 20 1 read-write I2C1_I3C1EN I2C1/I3C1 peripheral clocks enable Set and reset by software. 21 1 read-write I2C2EN I2C2 peripheral clocks enable Set and reset by software. 22 1 read-write I2C3EN I2C3 peripheral clocks enable Set and reset by software. 23 1 read-write HDMICECEN HDMI-CEC peripheral clock enable Set and reset by software. 27 1 read-write UART7EN UART7 peripheral clocks enable Set and reset by software. 30 1 read-write UART8EN UART8 peripheral clocks enable Set and reset by software. 31 1 read-write APB1HENR APB1ENR2 RCC APB1 clock enable register 2 0x14C 0x20 0x00000000 0xFFFFFFFF CRSEN clock recovery system peripheral clock enable Set and reset by software. 1 1 read-write CRSEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 MDIOSEN MDIOS peripheral clock enable Set and reset by software. 5 1 read-write FDCANEN FDCAN peripheral clock enable Set and reset by software. 8 1 read-write UCPDEN UCPD peripheral clock enable Set and reset by software. 27 1 read-write APB2ENR APB2ENR RCC APB2 clock enable register 0x150 0x20 0x00000000 0xFFFFFFFF TIM1EN TIM1 peripheral clock enable Set and reset by software. 0 1 read-write TIM1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 USART1EN USART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART1SEL, and the pclk2 bus interface clock. 4 1 read-write SPI1EN SPI2S1 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by SPI1SEL, and the pclk2 bus interface clock. 12 1 read-write SPI4EN SPI4 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock. 13 1 read-write TIM15EN TIM15 peripheral clock enable Set and reset by software. 16 1 read-write TIM16EN TIM16 peripheral clock enable Set and reset by software. 17 1 read-write TIM17EN TIM17 peripheral clock enable Set and reset by software. 18 1 read-write TIM9EN TIM9 peripheral clock enable Set and reset by software. 19 1 read-write SPI5EN SPI5 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock. 20 1 read-write SAI1EN SAI1 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI1 are the kernel clock selected by SAI1SEL, and the pclk2 bus interface clock. 22 1 read-write SAI2EN SAI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI2SEL, and the pclk2 bus interface clock. 23 1 read-write APB4ENR APB4ENR RCC APB4 clock enable register 0x154 0x20 0x00010000 0xFFFFFFFF SBSEN SBS peripheral clock enable Set and reset by software. 1 1 read-write SBSEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 LPUART1EN LPUART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the pclk4 bus interface clock. 3 1 read-write SPI6EN SPI/I2S6 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_clk input, and the pclk4 bus interface clock. 5 1 read-write LPTIM2EN LPTIM2 peripheral clocks enable Set and reset by software. The LPTIM2 kernel clock can be selected by LPTIM23SEL. 9 1 read-write LPTIM3EN LPTIM3 peripheral clocks enable Set and reset by software. The LPTIM3 kernel clock can be selected by LPTIM23SEL. 10 1 read-write LPTIM4EN LPTIM4 peripheral clocks enable Set and reset by software. The LPTIM4 kernel clock can be selected by LPTIM45SEL. 11 1 read-write LPTIM5EN LPTIM5 peripheral clocks enable Set and reset by software. The LPTIM5 kernel clock can be selected by LPTIM45SEL. 12 1 read-write VREFEN VREF peripheral clock enable Set and reset by software. 15 1 read-write RTCAPBEN RTC APB clock enable Set and reset by software. 16 1 read-write TMPSENSEN Temperature Sensor peripheral clock enable Set and reset by software. 26 1 read-write AHB3ENR AHB3ENR RCC AHB3 clock enable register 0x158 0x20 0x00000000 0xFFFFFFFF RNGEN RNG peripheral clocks enable Set and reset by software. 0 1 read-write RNGEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 HASHEN HASH peripheral clock enable Set and reset by software. 1 1 read-write CRYPEN CRYP peripheral clock enable Set and reset by software. 2 1 read-write SAESEN SAES peripheral clock enable Set and reset by software. This bit controls the enable of the clock delivered to the SAES. 4 1 read-write PKAEN PKA peripheral clock enable Set and reset by software. 6 1 read-write AHB5LPENR AHB5LPENR RCC AHB5 low-power clock enable register 0x15C 0x20 0xF018513F 0xFFFFFFFF HPDMA1LPEN HPDMA1 low-power peripheral clock enable Set and reset by software. 0 1 read-write HPDMA1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 DMA2DLPEN DMA2D low-power peripheral clock enable Set and reset by software. 1 1 read-write FLITFLPEN FLITF low-power peripheral clock enable Set and reset by software. 2 1 read-write JPEGLPEN JPEG clock enable during Sleep mode Set and reset by software. 3 1 read-write FMCLPEN FMC and MCE3 peripheral clocks enable during Sleep mode Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock. 4 1 read-write XSPI1LPEN XSPI1 and MCE1 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 5 1 read-write SDMMC1LPEN SDMMC1 and SDMMC1 delay low-power peripheral clock enable Set and reset by software. 8 1 read-write XSPI2LPEN XSPI2 and MCE2 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 12 1 read-write XSPIMLPEN XSPIM low-power peripheral clock enable Set and reset by software. 14 1 read-write GFXMMULPEN GFXMMU low-power peripheral clock enable Set and reset by software. 19 1 read-write GPULPEN GPU low-power peripheral clock enable Set and reset by software. 20 1 read-write DTCM1LPEN DTCM1 low-power peripheral clock enable Set and reset by software. 28 1 read-write DTCM2LPEN DTCM2 low-power peripheral clock enable Set and reset by software. 29 1 read-write ITCMLPEN ITCM low-power peripheral clock enable Set and reset by software. 30 1 read-write AXISRAMLPEN AXISRAM[4:1] low-power peripheral clock enable Set and reset by software. 31 1 read-write AHB1LPENR AHB1LPENR RCC AHB1 low-power clock enable register 0x160 0x20 0x8E038030 0xFFFFFFFF GPDMA1LPEN GPDMA1 clock enable in low-power mode Set and reset by software. 4 1 read-write GPDMA1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 ADC12LPEN ADC1 and 2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the rcc_hclk1 bus interface clock. 5 1 read-write ETH1MACLPEN ETH1 MAC peripheral clock enable in low-power mode Set and reset by software. 15 1 read-write ETH1TXLPEN ETH1 transmission peripheral clock enable in low-power mode Set and reset by software. 16 1 read-write ETH1RXLPEN ETH1 reception peripheral clock enable in low-power mode Set and reset by software. 17 1 read-write USBPDCTRL USBPHYC common block power-down control Set and reset by software. 24 1 read-write OTGHSLPEN OTGHS peripheral clock enable in low-power mode Set and reset by software. 25 1 read-write USBPHYCLPEN USBPHYC peripheral clock enable in low-power mode Set and reset by software. 26 1 read-write OTGFSLPEN OTGFS clock enable in low-power mode Set and reset by software. 27 1 read-write ADFLPEN ADF clock enable in low-power mode Set and reset by software. 31 1 read-write AHB2LPENR AHB2LPENR RCC AHB2 low-power clock enable register 0x164 0x20 0x60004202 0xFFFFFFFF PSSILPEN PSSI peripheral clock enable in low-power mode Set and reset by software. 1 1 read-write PSSILPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 SDMMC2LPEN SDMMC2 and SDMMC2 delay clock enable in low-power mode Set and reset by software. 9 1 read-write CORDICLPEN CORDIC clock enable in low-power mode Set and reset by software. 14 1 read-write SRAM1LPEN SRAM1 clock enable in low-power mode Set and reset by software. 29 1 read-write SRAM2LPEN SRAM2 clock enable in low-power mode Set and reset by software. 30 1 read-write AHB4LPENR AHB4LPENR RCC AHB4 low-power clock enable register 0x168 0x20 0x1008F0FF 0xFFFFFFFF GPIOALPEN GPIOA peripheral clock enable in low-power mode Set and reset by software. 0 1 read-write GPIOALPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 GPIOBLPEN GPIOB peripheral clock enable in low-power mode Set and reset by software. 1 1 read-write GPIOCLPEN GPIOC peripheral clock enable in low-power mode Set and reset by software. 2 1 read-write GPIODLPEN GPIOD peripheral clock enable in low-power mode Set and reset by software. 3 1 read-write GPIOELPEN GPIOE peripheral clock enable in low-power mode Set and reset by software. 4 1 read-write GPIOFLPEN GPIOF peripheral clock enable in low-power mode Set and reset by software. 5 1 read-write GPIOGLPEN GPIOG peripheral clock enable in low-power mode Set and reset by software. 6 1 read-write GPIOHLPEN GPIOH peripheral clock enable in low-power mode Set and reset by software. 7 1 read-write GPIOMLPEN GPIOM peripheral clock enable in low-power mode Set and reset by software. 12 1 read-write GPIONLPEN GPION peripheral clock enable in low-power mode Set and reset by software. 13 1 read-write GPIOOLPEN GPIOO peripheral clock enable in low-power mode Set and reset by software. 14 1 read-write GPIOPLPEN GPIOP peripheral clock enable in low-power mode Set and reset by software. 15 1 read-write CRCLPEN CRC clock enable in low-power mode Set and reset by software. 19 1 read-write BKPRAMLPEN Backup RAM clock enable in low-power mode Set and reset by software. 28 1 read-write AHB3LPENR AHB3LPENR RCC AHB3 low-power clock enable register 0x16C 0x20 0x00000057 0xFFFFFFFF RNGLPEN RNG peripheral clock enable in low-power mode Set and reset by software. 0 1 read-write RNGLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 HASHLPEN HASH peripheral clock enable in low-power mode Set and reset by software. 1 1 read-write CRYPLPEN CRYP peripheral clock enable in low-power mode Set and reset by software. 2 1 read-write SAESLPEN SAES peripheral clock enable in low-power mode Set and reset by software. 4 1 read-write PKALPEN PKA peripheral clock enable in low-power mode Set and reset by software. 6 1 read-write APB1LLPENR APB1LPENR1 RCC APB1 low-power clock enable register 1 0x170 0x20 0xC8FFCBFF 0xFFFFFFFF TIM2LPEN TIM2 peripheral clock enable in low-power mode Set and reset by software. 0 1 read-write TIM2LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 TIM3LPEN TIM3 peripheral clock enable in low-power mode Set and reset by software. 1 1 read-write TIM4LPEN TIM4 peripheral clock enable in low-power mode Set and reset by software. 2 1 read-write TIM5LPEN TIM5 peripheral clock enable in low-power mode Set and reset by software. 3 1 read-write TIM6LPEN TIM6 peripheral clock enable in low-power mode Set and reset by software. 4 1 read-write TIM7LPEN TIM7 peripheral clock enable in low-power mode Set and reset by software. 5 1 read-write TIM12LPEN TIM12 peripheral clock enable in low-power mode Set and reset by software. 6 1 read-write TIM13LPEN TIM13 peripheral clock enable in low-power mode Set and reset by software. 7 1 read-write TIM14LPEN TIM14 peripheral clock enable in low-power mode Set and reset by software. 8 1 read-write LPTIM1LPEN LPTIM1 peripheral clocks enable in low-power mode Set and reset by software. 9 1 read-write WWDGLPEN WWDG clock enable in low-power mode Set and reset by software. 11 1 read-write SPI2LPEN SPI2 peripheral clocks enable in low-power mode Set and reset by software. 14 1 read-write SPI3LPEN SPI3 peripheral clocks enable in low-power mode Set and reset by software. 15 1 read-write SPDIFRXLPEN SPDIFRX peripheral clocks enable in low-power mode Set and reset by software. 16 1 read-write USART2LPEN USART2 peripheral clocks enable in low-power mode Set and reset by software. 17 1 read-write USART3LPEN USART3 peripheral clocks enable in low-power mode Set and reset by software. 18 1 read-write UART4LPEN UART4 peripheral clocks enable in low-power mode Set and reset by software. 19 1 read-write UART5LPEN UART5 peripheral clocks enable in low-power mode Set and reset by software. 20 1 read-write I2C1_I3C1LPEN I2C1/I3C1 peripheral clocks enable in low-power mode Set and reset by software. 21 1 read-write I2C2LPEN I2C2 peripheral clocks enable in low-power mode Set and reset by software. 22 1 read-write I2C3LPEN I2C3 peripheral clocks enable in low-power mode Set and reset by software. 23 1 read-write HDMICECLPEN HDMI-CEC peripheral clocks enable in low-power mode Set and reset by software. 27 1 read-write UART7LPEN UART7 peripheral clocks enable in low-power mode Set and reset by software. 30 1 read-write UART8LPEN UART8 peripheral clocks enable in low-power mode Set and reset by software. 31 1 read-write APB1HLPENR APB1LPENR2 RCC APB1 low-power clock enable register 2 0x174 0x20 0x08000122 0xFFFFFFFF CRSLPEN clock recovery system peripheral clock enable in low-power mode Set and reset by software. 1 1 read-write CRSLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 MDIOSLPEN MDIOS peripheral clock enable in low-power mode Set and reset by software. 5 1 read-write FDCANLPEN FDCAN peripheral clock enable in low-power mode Set and reset by software. 8 1 read-write UCPDLPEN UCPD peripheral clock enable in low-power mode Set and reset by software. 27 1 read-write APB2LPENR APB2LPENR RCC APB2 low-power clock enable register 0x178 0x20 0x00DF3011 0xFFFFFFFF TIM1LPEN TIM1 peripheral clock enable in low-power mode Set and reset by software. 0 1 read-write TIM1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 USART1LPEN USART1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART169SEL and provided to UCLK inputs, and the pclk2 bus interface clock. 4 1 read-write SPI1LPEN SPI2S1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by I2S1SEL and provided to spi_ker_ck input, and the pclk2 bus interface clock. 12 1 read-write SPI4LPEN SPI4 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock. 13 1 read-write TIM15LPEN TIM15 peripheral clock enable in low-power mode Set and reset by software. 16 1 read-write TIM16LPEN TIM16 peripheral clock enable in low-power mode Set and reset by software. 17 1 read-write TIM17LPEN TIM17 peripheral clock enable in low-power mode Set and reset by software. 18 1 read-write TIM9LPEN TIM9 peripheral clock enable in low-power mode Set and reset by software. 19 1 read-write SPI5LPEN SPI5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock. 20 1 read-write SAI1LPEN SAI1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock. 22 1 read-write SAI2LPEN SAI2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI2 are: the kernel clock selected by SAI2SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock. 23 1 read-write APB4LPENR APB4LPENR RCC APB4 low-power clock enable register 0x17C 0x20 0x04019E2A 0xFFFFFFFF SBSLPEN SBS peripheral clock enable in low-power mode Set and reset by software. 1 1 read-write SBSLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 LPUART1LPEN LPUART1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the rcc_pclk4 bus interface clock. 3 1 read-write SPI6LPEN SPI/I2S6 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_ck input, and the rcc_pclk4 bus interface clock. 5 1 read-write LPTIM2LPEN LPTIM2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock. 9 1 read-write LPTIM3LPEN LPTIM3 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock. 10 1 read-write LPTIM4LPEN LPTIM4 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM4 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock. 11 1 read-write LPTIM5LPEN LPTIM5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM5 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock. 12 1 read-write VREFLPEN VREF peripheral clock enable in low-power mode Set and reset by software. 15 1 read-write RTCAPBLPEN RTC APB clock enable in low-power mode Set and reset by software. 16 1 read-write TMPSENSLPEN temperature sensor peripheral clock enable in low-power mode Set and reset by software. 26 1 read-write APB5LPENR APB5LPENR RCC APB5 sleep clock register 0x180 0x20 0x00000016 0xFFFFFFFF LTDCLPEN LTDC peripheral clock enable in low-power mode Set and reset by software. 1 1 read-write LTDCLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 DCMIPPLPEN DCMIPP peripheral clock enable in low-power mode Set and reset by software. 2 1 read-write GFXTIMLPEN GFXTIM peripheral clock enable in low-power mode Set and reset by software. 4 1 read-write RNG True random number generator RNG 0x48020000 0x0 0x400 registers RNG RNG global interrupt 37 CR CR RNG control register 0x0 0x20 0x00800D00 0xFFFFFFFF RNGEN True random number generator enable 2 1 read-write RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 IE Interrupt Enable 3 1 read-write IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 CED Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, that is to enable or disable CED the RNG must be disabled. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 5 1 read-write CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 ARDIS Auto reset disable When auto-reset is enabled application still need to clear SEIS bit after a noise source error. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 7 1 read-write RNG_CONFIG3 RNG configuration 3 Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details. If NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by RNG. 8 4 read-write RNG_CONFIG3 ConfigB Recommended value for config B (not NIST certifiable) 0 ConfigA Recommended value for config A (NIST certifiable) 13 NISTC NIST custom two conditioning loops are performed and 256 bits of noise source are used. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 12 1 read-write NISTC Default Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used 0 Custom Custom values for NIST compliant RNG 1 RNG_CONFIG2 RNG configuration 2 Reserved to the RNG configuration (bitfield 2). Refer to RNG_CONFIG1 bitfield for details. 13 3 read-write RNG_CONFIG2 ConfigA_B Recommended value for config A and B 0 CLKDIV Clock divider factor This value used to configure an internal programmable divider (from 1 to 16) acting on the incoming RNG clock. These bits can be written only when the core is disabled (RNGEN = 0). ... Writing these bits is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 16 4 read-write CLKDIV Div1 Internal RNG clock after divider is similar to incoming RNG clock 0 Div2 Divide RNG clock by 2^1 1 Div4 Divide RNG clock by 2^2 2 Div8 Divide RNG clock by 2^3 3 Div16 Divide RNG clock by 2^4 4 Div32 Divide RNG clock by 2^5 5 Div64 Divide RNG clock by 2^6 6 Div128 Divide RNG clock by 2^7 7 Div256 Divide RNG clock by 2^8 8 Div512 Divide RNG clock by 2^9 9 Div1024 Divide RNG clock by 2^10 10 Div2048 Divide RNG clock by 2^11 11 Div4096 Divide RNG clock by 2^12 12 Div8192 Divide RNG clock by 2^13 13 Div16384 Divide RNG clock by 2^14 14 Div32768 Divide RNG clock by 2^15 15 RNG_CONFIG1 RNG configuration 1 Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended value documented in Section 37.6: RNG entropy source validation. Writing any bit of RNG_CONFIG1 is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 20 6 read-write RNG_CONFIG1 ConfigA Recommended value for config A (NIST certifiable) 15 ConfigB Recommended value for config B (not NIST certifiable) 24 CONDRST Conditioning soft reset Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new RNG initialization process, with RNG_SR cleared. Registers RNG_CR and RNG_HTCR are not changed by CONDRST. This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be written. When CONDRST is set to 0 by software its value goes to 0 when the reset process is done. It takes about 2 AHB clock cycles + 2 RNG clock cycles. 30 1 read-write CONFIGLOCK RNG Config lock This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset. 31 1 read-write CONFIGLOCK Enabled Writes to the RNG_CR configuration bits [29:4] are allowed 0 Disabled Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset 1 SR SR RNG status register 0x4 0x20 0x00000000 0xFFFFFFFF DRDY Data Ready Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. Note: The DRDY bit can rise when the peripheral is disabled (RNGEN = 0 in the RNG_CR register). If IE=1 in the RNG_CR register, an interrupt is generated when DRDY = 1. 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 CECS Clock error current status Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0. 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 SECS Seed error current status Run-time repetition count test failed (noise source has provided more than 24 consecutive bits at a constant value 0 or 1, or more than 32 consecutive occurrence of two bits patterns 01 or 10) Start-up or continuous adaptive proportion test on noise source failed. Start-up post-processing/conditioning sanity check failed. 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CEIS Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register. 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing 0 (unless CONDRST is used). Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register. 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 DR DR RNG data register 0x8 0x20 0x00000000 0xFFFFFFFF RNDATA Random data 32-bit random data which are valid when DRDY = 1. When DRDY = 0 RNDATA value is zero. When DRDY is set, it is recommended to always verify that RNG_DR is different from zero. Because when it is the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare event). 0 32 read-only 0 4294967295 HTCR HTCR RNG health test control register 0x10 0x20 0x000072AC 0xFFFFFFFF HTCFG health test configuration This configuration is used by RNG to configure the health tests. See Section 37.6: RNG entropy source validation for the recommended value. Note: The RNG behavior, including the read to this register, is not guaranteed if a different value from the recommended value is written. 0 32 read-write HTCFG Recommended Recommended value for RNG certification (0x0000_AA74) 43636 Magic Magic number to be written before any write (0x1759_0ABC) 391711420 RTC RTC register block RTC 0x58004000 0x0 0x400 registers RTC RTC Wakeup and Alarm interrupt through the EXTI line 32 TR TR RTC time register 0x0 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write 0 15 ST Second tens in BCD format 4 3 read-write 0 7 MNU Minute units in BCD format 8 4 read-write 0 15 MNT Minute tens in BCD format 12 3 read-write 0 7 HU Hour units in BCD format 16 4 read-write 0 15 HT Hour tens in BCD format 20 2 read-write 0 3 PM AM/PM notation 22 1 read-write PM AM AM or 24-hour format 0 PM PM 1 DR DR RTC date register 0x4 0x20 0x00002101 0xFFFFFFFF DU Date units in BCD format 0 4 read-write 0 15 DT Date tens in BCD format 4 2 read-write 0 3 MU Month units in BCD format 8 4 read-write 0 15 MT Month tens in BCD format 12 1 read-write 0 1 WDU Week day units ... 13 3 read-write 1 7 YU Year units in BCD format 16 4 read-write 0 15 YT Year tens in BCD format 20 4 read-write 0 15 SSR SSR RTC subsecond register 0x8 0x20 0x00000000 0xFFFFFFFF SS Synchronous binary counter SS[31:16]: Synchronous binary counter MSB values When Binary or Mixed mode is selected (BIN = 01 or 10 or 11): SS[31:16] are the 16 MSB of the SS[31:0] free-running down-counter. When BCD mode is selected (BIN=00): SS[31:16] are forced by hardware to 0x0000. SS[15:0]: Subsecond value/synchronous binary counter LSB values When Binary mode is selected (BIN = 01 or 10 or 11): SS[15:0] are the 16 LSB of the SS[31:0] free-running down-counter. When BCD mode is selected (BIN=00): SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. 0 32 read-only 0 65535 ICSR ICSR RTC initialization control and status register 0xC 0x20 0x00000007 0xFFFFFFFF WUTWF Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 BIN Binary mode 8 2 read-write BCDU BCD update (BIN = 10 or 11) In mixed mode when both BCD calendar and binary extended counter are used (BIN = 10 or 11), the calendar second is incremented using the SSR Least Significant Bits. 10 3 read-write RECALPF Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly. 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER RTC prescaler register 0x10 0x20 0x007F00FF 0xFFFFFFFF PREDIV_S Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) 0 15 read-write 0 32767 PREDIV_A Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) 16 7 read-write 0 127 WUTR WUTR RTC wakeup timer register 0x14 0x20 0x0000FFFF 0xFFFFFFFF WUT Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs between WUT and (WUT + 2) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden. 0 16 read-write 0 65535 WUTOCLR Wakeup auto-reload output clear value When WUTOCLR[15:0] is different from 0x0000, WUTF is set by hardware when the auto-reload down-counter reaches 0 and is cleared by hardware when the auto-reload downcounter reaches WUTOCLR[15:0]. When WUTOCLR[15:0] = 0x0000, WUTF is set by hardware when the WUT down-counter reaches 0 and is cleared by software. 16 16 read-write CR CR RTC control register 0x18 0x20 0x00000000 0xFFFFFFFF WUCKSEL ck_wut wakeup clock selection 10x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. 11x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. Furthermore, 216 is added to the WUT counter value. 0 3 read-write WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. 3 1 read-write TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON RTC_REFIN reference clock detection enable (50 or 60 Hz) Note: BIN must be 0x00 and PREDIV_S must be 0x00FF. 4 1 read-write REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. 5 1 read-write BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT Hour format 6 1 read-write FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 SSRUIE SSR underflow interrupt enable 7 1 read-write 2 0x1 A,B ALR%sE Alarm %s enable 8 1 read-write ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF = 1 before enabling it again. 10 1 read-write WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE timestamp enable 11 1 read-write TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 read-write ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE Wakeup timer interrupt enable 14 1 read-write WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE Timestamp interrupt enable 15 1 read-write TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 16 1 write-only ADD1HW Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 17 1 write-only SUB1HW Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. 18 1 read-write BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 COSEL Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to Section 45.3.17: Calibration clock output. 19 1 read-write COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL Output polarity This bit is used to configure the polarity of TAMPALRM output. 20 1 read-write POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL Output selection These bits are used to select the flag to be routed to TAMPALRM output. 21 2 read-write OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE Calibration output enable This bit enables the CALIB output 23 1 read-write COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ITSE timestamp on internal event enable 24 1 read-write ITSE Disabled Internal event timestamp disabled 0 Enabled Internal event timestamp enabled 1 TAMPTS Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set up to 3 ck_apre cycles after the tamper flags. 25 1 read-write TAMPTS Disabled Tamper detection event does not cause a RTC timestamp to be saved 0 Enabled Save RTC timestamp on tamper detection event 1 TAMPOE Tamper detection output enable on TAMPALRM 26 1 read-write TAMPOE Disabled The tamper flag is not routed on TAMPALRM 0 Enabled The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL 1 ALRAFCLR Alarm A flag automatic clear 27 1 read-write ALRBFCLR Alarm B flag automatic clear 28 1 read-write TAMPALRM_PU TAMPALRM pull-up enable 29 1 read-write TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPALRM_TYPE TAMPALRM output type 30 1 read-write TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 OUT2EN RTC_OUT2 output enable With this bit set, the RTC outputs can be remapped on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different from 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different from 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL different from 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1. 31 1 read-write OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 PRIVCFGR PRIVCFGR RTC privilege mode control register 0x1C 0x20 0x00000000 0xFFFFFFFF ALRAPRIV Alarm A and SSR underflow privilege protection 0 1 read-write ALRBPRIV Alarm B privilege protection 1 1 read-write WUTPRIV Wakeup timer privilege protection 2 1 read-write TSPRIV Timestamp privilege protection 3 1 read-write CALPRIV Shift register, Delight saving, calibration and reference clock privilege protection 13 1 read-write INITPRIV Initialization privilege protection 14 1 read-write PRIV RTC privilege protection 15 1 read-write WPR WPR RTC write protection register 0x24 0x20 0x00000000 0xFFFFFFFF KEY Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection. 0 8 write-only KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR RTC calibration register 0x28 0x20 0x00000000 0xFFFFFFFF CALM Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section 45.3.15: RTC smooth digital calibration on page 2349. 0 9 read-write 0 511 LPCAL RTC low-power mode 12 1 read-write CALW16 Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section 45.3.15: RTC smooth digital calibration. 13 1 read-write CALW16 SixteenSeconds When CALW16 is set to â1â, the 16-second calibration cycle period is selected.This bit must not be set to â1â if CALW8=1 1 CALW8 Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section 45.3.15: RTC smooth digital calibration. 14 1 read-write CALW8 EightSeconds When CALW8 is set to â1â, the 8-second calibration cycle period is selected 1 CALP Increase frequency of RTC by 488.5 ppm 15 1 read-write CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 SHIFTR SHIFTR RTC shift control register 0x2C 0x20 0x00000000 0xFFFFFFFF SUBFS Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). In mixed BCD-binary mode (BIN=10 or 11), the SUBFS[14:BCDU+8] must be written with 0. Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time. 0 15 write-only 0 32767 ADD1S Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. 31 1 write-only ADD1SW Add1 Add one second to the clock/calendar 1 TSTR TSTR RTC timestamp time register 0x30 TSDR TSDR RTC timestamp date register 0x34 TSSSR TSSSR RTC timestamp subsecond register 0x38 2 0x8 A,B ALRM%sR ALRM%sR Alarm %s register 0x40 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write 0 15 ST Second tens in BCD format 4 3 read-write 0 7 MSK1 Alarm seconds mask 7 1 read-write MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day donât care in Alarm comparison 1 MNU Minute units in BCD format 8 4 read-write 0 15 MNT Minute tens in BCD format 12 3 read-write 0 7 MSK2 Alarm minutes mask 15 1 read-write HU Hour units in BCD format 16 4 read-write 0 15 HT Hour tens in BCD format 20 2 read-write 0 3 PM AM/PM notation 22 1 read-write PM AM AM or 24-hour format 0 PM PM 1 MSK3 Alarm hours mask 23 1 read-write DU Date units or day in BCD format 24 4 read-write 0 15 DT Date tens in BCD format 28 2 read-write 0 3 WDSEL Week day selection 30 1 read-write WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is donât care. 1 MSK4 Alarm date mask 31 1 read-write 2 0x8 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 0x00000000 0xFFFFFFFF SS Subseconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. This field is the mirror of SS[14:0] in the RTC_ALRMABINR, and so can also be read or written through RTC_ALRMABINR. 0 15 read-write 0 32767 MASKSS Mask the most-significant bits starting at this bit ... From 32 to 63: All 32 SS bits are compared and must match to activate alarm. Note: In BCD mode (BIN=00) the overflow bits of the synchronous counter (bits 31:15) are never compared. These bits can be different from 0 only after a shift operation. 24 6 read-write SSCLR Clear synchronous counter on alarm (Binary mode only) Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). 31 1 read-write SR SR RTC status register 0x50 0x20 0x00000000 0xFFFFFFFF 2 0x1 A,B ALR%sF Alarm %s flag 0 1 read-only ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 WUTF Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. If WUTOCLR[15:0] is different from 0x0000, WUTF is cleared by hardware when the wakeup auto-reload counter reaches WUTOCLR value. If WUTOCLR[15:0] is 0x0000, WUTF must be cleared by software. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only WUTF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSF Timestamp flag This flag is set by hardware when a timestamp event occurs. If ITSF flag is set, TSF must be cleared together with ITSF. Note: TSF is not set if TAMPTS = 1 and the tamper flag is read during the 3 ck_apre cycles following tamper event. Refer to Timestamp on tamper event for more details. 3 1 read-only TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVF Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSF Internal timestamp flag This flag is set by hardware when a timestamp on the internal event occurs. 5 1 read-only ITSF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SSRUF SSR underflow flag This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1. 6 1 read-only MISR MISR RTC masked interrupt status register 0x54 0x20 0x00000000 0xFFFFFFFF 2 0x1 A,B ALR%sMF Alarm %s masked flag 0 1 read-only ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 WUTMF Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only WUTMF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSMF Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF. 3 1 read-only TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVMF Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSMF Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised. 5 1 read-only ITSMF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SSRUMF SSR underflow masked flag This flag is set by hardware when the SSR underflow interrupt occurs. 6 1 read-only SCR SCR RTC status clear register 0x5C 0x20 0x00000000 0xFFFFFFFF CALRAF Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register. 0 1 write-only CALRAF Clear Clear interrupt flag 1 CALRBF Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register. 1 1 write-only CWUTF Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register. 2 1 write-only CTSF Clear timestamp flag Writing 1 in this bit clears the TSF bit in the RTC_SR register. If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF. 3 1 write-only CTSOVF Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 write-only CITSF Clear internal timestamp flag Writing 1 in this bit clears the ITSF bit in the RTC_SR register. 5 1 write-only CSSRUF Clear SSR underflow flag Writing 1 in this bit clears the SSRUF in the RTC_SR register. 6 1 write-only 2 0x4 A,B ALR%sBINR ALR%sBINR Alarm %s binary mode register 0x70 0x20 0x00000000 0xFFFFFFFF SS Synchronous counter alarm value in Binary mode This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR. 0 32 read-write SAES Secure AES coprocessor SAES 0x48021000 0x0 0x400 registers SAES SAES global interrupt 33 AES AES global interrupt 34 CR CR SAES control register 0x0 0x20 0x00000000 0xFFFFFFFF EN SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD[1:0] = 01 + CHMOD[2:0] = 011 and KMOD[1:0] = 01 + CHMOD[2:0] = 010 + MODE[1:0] = 00. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN. 0 1 read-write DATATYPE Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to Section 32.4.15: SAES data registers and data swapping. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. 1 2 read-write MODE SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. 3 2 read-write CHMOD CHMOD[1:0]: Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. 5 2 read-write DMAINEN DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). 11 1 read-write DMAOUTEN DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). 12 1 read-write GCMPH GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield). 13 2 read-write CHMOD_1 CHMOD[2] 16 1 read-write KEYSIZE Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0] = 01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. 18 1 read-write NPBLB Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ... 20 4 read-write KMOD Key mode selection 24 2 read-write KSHAREID Key share identification This bitfield defines, at the end of a decryption process with KMOD[1:0] = 10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. 26 2 read-write KEYSEL Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. 28 3 read-write IPRST SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers. 31 1 read-write SR SR SAES status register 0x4 0x20 0x00000000 0xFFFFFFFF CCF Computation completed flag This bit mirrors the CCF bit of the SAES_ISR register. 0 1 read-only RDERR Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero. 1 1 read-only WRERR Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored. 2 1 read-only BUSY Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is also set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase. 3 1 read-only KEYVALID Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading, refer to Section 32.4.16: SAES key registers. 7 1 read-only DINR DINR SAES data input register 0x8 0x20 0x00000000 0xFFFFFFFF DIN Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the SAES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. The data signification of the input data block depends on the SAES operating mode: - Mode 1 (encryption): plaintext - Mode 2 (key derivation): the bitfield is not used (SAES_KEYRx registers used for input if KEYSEL = 0) - Mode 3 (decryption): ciphertext The data swap operation is described in Section 32.4.15: SAES data registers and data swapping on page 1755. 0 32 write-only DOUTR DOUTR SAES data output register 0xC 0x20 0x00000000 0xFFFFFFFF DOUT Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the SAES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. The data signification of the output data block depends on the SAES operating mode: - Mode 1 (encryption): ciphertext - Mode 2 (key derivation): the bitfield is not used - Mode 3 (decryption): plaintext The data swap operation is described in Section 32.4.15: SAES data registers and data swapping on page 1755. 0 32 read-only KEYR0 KEYR0 SAES key register 0 0x10 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [31:0] This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation): the value to write into the bitfield is the encryption key. - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. The SAES_KEYRx registers may be written only when KEYSIZE value is correct and when the SAES peripheral is disabled (EN bit of the SAES_CR register cleared). A special writing sequence is also required, as described in KEYVALID bit of the SAES_SR register. Note that, if KEYSEL is different from 0 and KEYVALID = 0, the key is directly loaded to SAES_KEYRx registers (hence writes to key register is ignored and KEIF is set). Refer to Section 32.4.16: SAES key registers on page 1758 for more details. 0 32 write-only KEYR1 KEYR1 SAES key register 1 0x14 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [63:32] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. 0 32 write-only KEYR2 KEYR2 SAES key register 2 0x18 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [95:64] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. 0 32 write-only KEYR3 KEYR3 SAES key register 3 0x1C 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [127:96] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. 0 32 write-only IVR0 IVR0 SAES initialization vector register 0 0x20 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [31:0] Refer to Section 32.4.17: SAES initialization vector registers on page 1760 for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The SAES_IVRx registers may be written only when the SAES peripheral is disabled 0 32 read-write IVR1 IVR1 SAES initialization vector register 1 0x24 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [63:32] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. 0 32 read-write IVR2 IVR2 SAES initialization vector register 2 0x28 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [95:64] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. 0 32 read-write IVR3 IVR3 SAES initialization vector register 3 0x2C 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [127:96] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. 0 32 read-write KEYR4 KEYR4 SAES key register 4 0x30 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [159:128] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. 0 32 write-only KEYR5 KEYR5 SAES key register 5 0x34 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [191:160] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. 0 32 write-only KEYR6 KEYR6 SAES key register 6 0x38 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [223:192] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. 0 32 write-only KEYR7 KEYR7 SAES key register 7 0x3C 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [255:224] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. 0 32 write-only SUSP0R SUSP0R SAES suspend registers 0x40 0x20 0x00000000 0xFFFFFFFF SUSP SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. 0 32 read-write SUSP1R SUSP1R SAES suspend registers 0x44 0x20 0x00000000 0xFFFFFFFF SUSP SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. 0 32 read-write SUSP2R SUSP2R SAES suspend registers 0x48 0x20 0x00000000 0xFFFFFFFF SUSP SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. 0 32 read-write SUSP3R SUSP3R SAES suspend registers 0x4C 0x20 0x00000000 0xFFFFFFFF SUSP SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. 0 32 read-write SUSP4R SUSP4R SAES suspend registers 0x50 0x20 0x00000000 0xFFFFFFFF SUSP SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. 0 32 read-write SUSP5R SUSP5R SAES suspend registers 0x54 0x20 0x00000000 0xFFFFFFFF SUSP SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. 0 32 read-write SUSP6R SUSP6R SAES suspend registers 0x58 0x20 0x00000000 0xFFFFFFFF SUSP SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. 0 32 read-write SUSP7R SUSP7R SAES suspend registers 0x5C 0x20 0x00000000 0xFFFFFFFF SUSP SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. 0 32 read-write IER IER SAES interrupt enable register 0x300 0x20 0x00000000 0xFFFFFFFF CCFIE Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set. 0 1 read-write RWEIE Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set. 1 1 read-write KEIE Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set. 2 1 read-write RNGEIE RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set. 3 1 read-write ISR ISR SAES interrupt status register 0x304 0x20 0x00000000 0xFFFFFFFF CCF Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1. 0 1 read-only RWEIF Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected. 1 1 read-only KEIF Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. SAES fails to load the AHK (KEYSEL = 011 or 101). CRYP fails to load the key shared by SAES peripheral (KMOD = 10). SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set. 2 1 read-only RNGEIF RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. 3 1 read-only ICR ICR SAES interrupt clear register 0x308 0x20 0x00000000 0xFFFFFFFF CCF Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers. 0 1 write-only RWEIF Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register. 1 1 write-only KEIF Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register. 2 1 write-only RNGEIF RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register. 3 1 write-only SAI1 Serial audio interface SAI 0x42005C00 0x0 0x400 registers SAI1_A SAI1 global interrupt A 72 SAI1_B SAI1 global interrupt B 73 GCR GCR SAI global configuration register 0x0 0x20 0x00000000 0xFFFFFFFF SYNCIN Synchronization inputs These bits are set and cleared by software. Refer to Table 418: External synchronization selection (TinyShark, Beluga and STM32U5_Cobra2M and 4M, Viper, Mustang, Python) for information on how to program this field. These bits must be set when both audio blocks (A and B) are disabled. They are meaningful if one of the two audio blocks is defined to operate in synchronous mode with an external SAI (SYNCEN[1:0] = 10 in SAI_ACR1 or in SAI_BCR1 registers). 0 2 read-write SYNCOUT Synchronization outputs These bits are set and cleared by software. 4 2 read-write ACR1 ACR1 SAI configuration register 1 0x4 0x20 0x00000040 0xFFFFFFFF MODE SAIx audio block mode These bits are set and cleared by software. They must be configured when SAIx audio block is disabled. Note: When the audio block is configured in SPDIF mode, the master transmitter mode is forced (MODE[1:0] = 00). 0 2 read-write PRTCFG Protocol configuration These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 read-write DS Data size These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 read-write LSBFIRST Least significant bit first This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 read-write CKSTR Clock strobing edge This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 read-write SYNCEN Synchronization enable These bits are set and cleared by software. They must be configured when the audio subblock is disabled. Note: The audio subblock should be configured as asynchronous when SPDIF mode is enabled. 10 2 read-write MONO Mono mode This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section : Mono/stereo mode for more details. 12 1 read-write OUTDRIV Output drive This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 read-write SAIEN Audio block enable This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command is not taken into account. This bit enables to control the state of the SAI audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When the SAI block (A or B) is configured in master mode, the clock must be present on the SAI block input before setting SAIEN bit. 16 1 read-write DMAEN DMA enable This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 read-write NODIV No divider This bit is set and cleared by software. 19 1 read-write MCKDIV Master clock divider These bits are set and cleared by software. Otherwise, The master clock frequency is calculated according to the formula given in Section 55.4.8: SAI clock generator. These bits have no meaning when the audio block is slave. They have to be configured when the audio block is disabled. 20 6 read-write OSR Oversampling ratio for master clock This bit is meaningful only when NODIV bit is set to 0. 26 1 read-write MCKEN Master clock generation enable 27 1 read-write ACR2 ACR2 SAI configuration register 2 0x8 0x20 0x00000000 0xFFFFFFFF FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section : Output data line management on an inactive slot for more details. 4 1 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section : Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section : Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET is set and an interrupt is generated if bit MUTEDETIE is set. Refer to Section : Mute mode for more details. 7 6 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that is used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section : Companding mode for more details. Note: Companding mode is applicable only when Free protocol mode is selected. 14 2 read-write AFRCR AFRCR SAI frame configuration register 0xC 0x20 0x00000007 0xFFFFFFFF FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots are dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write ASLOTR ASLOTR SAI slot register 0x10 0x20 0x00000000 0xFFFFFFFF FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 read-write SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI is undetermined. Refer to Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 read-write NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 read-write SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 read-write AIM AIM SAI interrupt mask register 0x14 0x20 0x00000000 0xFFFFFFFF OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 read-write MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 read-write WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in Free protocol mode and is meaningless in other modes. 2 1 read-write FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interrupt in receiver mode, 3 1 read-write CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interrupt is generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 read-write AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 read-write LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 read-write ASR ASR SAI status register 0x18 0x20 0x00000008 0xFFFFFFFF OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 read-only MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 read-only WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 read-only FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 read-only CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 read-only AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 read-only LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 read-only FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). Others: Reserved 16 3 read-only ACLRFR ACLRFR SAI clear flag register 0x1C 0x20 0x00000000 0xFFFFFFFF COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 write-only CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 write-only CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 write-only CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 write-only CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97 or SPDIF mode. Reading this bit always returns the value 0. 5 1 write-only CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97 or SPDIF mode Reading this bit always returns the value 0. 6 1 write-only ADR ADR SAI data register 0x20 0x20 0x00000000 0xFFFFFFFF DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 read-write BCR1 BCR1 SAI configuration register 1 0x24 0x20 0x00000040 0xFFFFFFFF MODE SAIx audio block mode These bits are set and cleared by software. They must be configured when SAIx audio block is disabled. Note: When the audio block is configured in SPDIF mode, the master transmitter mode is forced (MODE[1:0] = 00). In Master transmitter mode, the audio block starts generating the FS and the clocks immediately. 0 2 read-write PRTCFG Protocol configuration These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 read-write DS Data size These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 read-write LSBFIRST Least significant bit first This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 read-write CKSTR Clock strobing edge This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 read-write SYNCEN Synchronization enable These bits are set and cleared by software. They must be configured when the audio subblock is disabled. Note: The audio subblock should be configured as asynchronous when SPDIF mode is enabled. 10 2 read-write MONO Mono mode This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section : Mono/stereo mode for more details. 12 1 read-write OUTDRIV Output drive This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 read-write SAIEN Audio block enable This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command is not taken into account. This bit enables to control the state of the SAI audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When the SAI block (A or B) is configured in master mode, the clock must be present on the SAI block input before setting SAIEN bit. 16 1 read-write DMAEN DMA enable This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 read-write NODIV No divider This bit is set and cleared by software. 19 1 read-write MCKDIV Master clock divider These bits are set and cleared by software. Otherwise, The master clock frequency is calculated according to the formula given in Section 55.4.8: SAI clock generator. These bits have no meaning when the audio block is slave. They have to be configured when the audio block is disabled. 20 6 read-write OSR Oversampling ratio for master clock This bit is meaningful only when NODIV bit is set to 0. 26 1 read-write MCKEN Master clock generation enable 27 1 read-write BCR2 BCR2 SAI configuration register 2 0x28 0x20 0x00000000 0xFFFFFFFF FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section : Output data line management on an inactive slot for more details. 4 1 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section : Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section : Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET is set and an interrupt is generated if bit MUTEDETIE is set. Refer to Section : Mute mode for more details. 7 6 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that is used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section : Companding mode for more details. Note: Companding mode is applicable only when Free protocol mode is selected. 14 2 read-write BFRCR BFRCR SAI frame configuration register 0x2C 0x20 0x00000007 0xFFFFFFFF FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots is dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write BSLOTR BSLOTR SAI slot register 0x30 0x20 0x00000000 0xFFFFFFFF FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 read-write SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI is undetermined. Refer to Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 read-write NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 read-write SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 read-write BIM BIM SAI interrupt mask register 0x34 0x20 0x00000000 0xFFFFFFFF OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 read-write MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 read-write WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in Free protocol mode and is meaningless in other modes. 2 1 read-write FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interrupt in receiver mode, 3 1 read-write CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interrupt is generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 read-write AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 read-write LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 read-write BSR BSR SAI status register 0x38 0x20 0x00000008 0xFFFFFFFF OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 read-only MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 read-only WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 read-only FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 read-only CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 read-only AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 read-only LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 read-only FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). Others: Reserved 16 3 read-only BCLRFR BCLRFR SAI clear flag register 0x3C 0x20 0x00000000 0xFFFFFFFF COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 write-only CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 write-only CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 write-only CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 write-only CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. 5 1 write-only CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. 6 1 write-only BDR BDR SAI data register 0x40 0x20 0x00000000 0xFFFFFFFF DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 read-write PDMCR PDMCR SAI PDM control register 0x44 0x20 0x00000000 0xFFFFFFFF PDMEN PDM enable This bit is set and cleared by software. This bit enables to control the state of the PDM interface block. Make sure that the SAI in already operating in TDM master mode before enabling the PDM interface. 0 1 read-write MICNBR Number of microphones This bit is set and cleared by software. Note: It is not recommended to configure this field when PDMEN = 1.* Note: The complete set of data lines might not be available for all SAI instances. Refer to Section 55.3: SAI implementation for details. 4 2 read-write CKEN1 Clock enable of bitstream clock number 1 This bit is set and cleared by software. Note: It is not recommended to configure this bit when PDMEN = 1. Note: SAI_CK1 might not be available for all SAI instances. Refer to Section 55.3: SAI implementation for details. 8 1 read-write CKEN2 Clock enable of bitstream clock number 2 This bit is set and cleared by software. Note: It is not recommended to configure this bit when PDMEN = 1. Note: SAI_CK2 might not be available for all SAI instances. Refer to Section 55.3: SAI implementation for details. 9 1 read-write PDMDLY PDMDLY SAI PDM delay register 0x48 0x20 0x00000000 0xFFFFFFFF DLYM1L Delay line adjust for first microphone of pair 1 This bit is set and cleared by software. ... This field can be changed on-the-fly. Note: This field can be used only if D1 line is available.Refer to Section 55.3: SAI implementation to check if it is available. 0 3 read-write DLYM1R Delay line adjust for second microphone of pair 1 This bit is set and cleared by software. ... This field can be changed on-the-fly. Note: This field can be used only if D1 line is available.Refer to Section 55.3: SAI implementation to check if it is available. 4 3 read-write DLYM2L Delay line for first microphone of pair 2 This bit is set and cleared by software. ... This field can be changed on-the-fly. Note: This field can be used only if D2 line is available.Refer to Section 55.3: SAI implementation to check if it is available. 8 3 read-write DLYM2R Delay line for second microphone of pair 2 This bit is set and cleared by software. ... This field can be changed on-the-fly. Note: This field can be used only if D2 line is available.Refer to Section 55.3: SAI implementation to check if it is available. 12 3 read-write DLYM3L Delay line for first microphone of pair 3 This bit is set and cleared by software. ... This field can be changed on-the-fly. Note: This field can be used only if D3 line is available.Refer to Section 55.3: SAI implementation to check if it is available. 16 3 read-write DLYM3R Delay line for second microphone of pair 3 This bit is set and cleared by software. ... This field can be changed on-the-fly. Note: This field can be used only if D3 line is available.Refer to Section 55.3: SAI implementation to check if it is available. 20 3 read-write DLYM4L Delay line for first microphone of pair 4 This bit is set and cleared by software. ... This field can be changed on-the-fly. Note: This field can be used only if D4 line is available.Refer to Section 55.3: SAI implementation to check if it is available. 24 3 read-write DLYM4R Delay line for second microphone of pair 4 This bit is set and cleared by software. ... This field can be changed on-the-fly. Note: This field can be used only if D4 line is available.Refer to Section 55.3: SAI implementation to check if it is available. 28 3 read-write SAI2 0x42005800 SAI2_A SAI2 global interrupt A 74 SAI2_B SAI2 global interrupt B 75 SBS System configuration, boot and security SBS 0x58000400 0x0 0x140 registers BOOTSR BOOTSR SBS boot status register 0x0 0x20 0x00000000 0xFFFFFFFF INITVTOR initial vector for Cortex-M7 This register includes the physical boot address used by the Cortex-M7 after reset 0 32 read-only HDPLCR HDPLCR SBS hide protection control register 0x10 0x20 0x000000B4 0xFFFFFFFF INCR_HDPL increment HDPL Write 0x6A to increment device HDPL by one. After a write, the register value reverts to its default value (0xB4). 0 8 read-write HDPLSR HDPLSR SBS hide protection status register 0x14 0x20 0x00000000 0xFFFFFF00 HDPL hide protection level This bitfield returns the current HDPL of the device. 0x6F and other codes: HDPL3, corresponding to non-boot application. Note: The device state (open/close) is defined in FLASH_NVSTATER register of the embedded Flash memory. 0 8 read-only DBGCR DBGCR SBS debug control register 0x20 0x20 0x00000000 0xFFFFFFFF AP_UNLOCK access port unlock Write 0xB4 to this bitfield to open the device access port. 0 8 read-write DBG_UNLOCK debug unlock Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register. 8 8 read-write DBG_AUTH_HDPL authenticated debug hide protection level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the authenticated debug always fails. 16 8 read-write DBGLOCKR DBGLOCKR SBS debug lock register 0x24 0x20 0x000000B4 0xFFFFFFFF DBGCFG_LOCK debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. Other: Writes to SBS_DBGCR ignored Note: 0xC3 is the recommended value to lock the debug configuration using this bitfield. 0 8 read-write RSSCMDR RSSCMDR SBS RSS command register 0x34 0x20 0x00000000 0xFFFFFFFF RSSCMD RSS command The application can use this bitfield to pass on a command to the RSS, executed at the next reset. 0 16 read-write PMCR PMCR SBS product mode and configuration register 0x100 0x20 0x00000000 0xFFFFFFFF FMPLUS_PB6 Fast-mode Plus on PB(6) 4 1 read-write FMPLUS_PB7 Fast-mode Plus on PB(7) 5 1 read-write FMPLUS_PB8 Fast-mode Plus on PB(8) 6 1 read-write FMPLUS_PB9 Fast-mode Plus on PB(9) 7 1 read-write BOOSTEN booster enable Set this bit to reduce the THD of the analog switches when the supply voltage is below 2.7 V. guaranteeing the same performance as with the full voltage range. To avoid current consumption due to booster activation when VDDA < 2.7 V and VDD > 2.7 V, VDD can be selected as supply voltage for analog switches by setting BOOSTVDDSEL bit in SBS_PMCR. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. 8 1 read-write BOOSTVDDSEL booster VDD selection This bit selects the analog switch supply voltage, between VDD, VDDA and booster. To avoid current consumption due to booster activation when VDDA < 2.7 V and VDD > 2.7 V, VDD can be selected as supply voltage for analog switches. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. When both VDD and VDDA are below 2.7 V, the booster is still needed to obtain full AC performances from the I/O analog switches. 9 1 read-write ETH_PHYSEL Ethernet PHY interface selection Other: reserved 21 3 read-write AXIRAM_WS AXIRAM wait state Set this bit to add one wait state to all AXIRAMs when ECC = 0. When ECC = 1 there is one wait state by default. 28 1 read-write FPUIMR FPUIMR SBS FPU interrupt mask register 0x104 0x20 0x0000001F 0xFFFFFFFF FPU_IE FPU interrupt enable Set and cleared by software to enable the Cortex-M7 FPU interrupts xxxxx1: Invalid operation interrupt enabled (xxxxx0 to disable) xxxx1x: Divide-by-zero interrupt enabled (xxxx0x to disable) xxx1xx: Underflow interrupt enabled (xxx0xx to disable) xx1xxx: Overflow interrupt enabled (xx0xxx to disable) x1xxxx: Input denormal interrupt enabled (x0xxxx to disable) 1xxxxx: Inexact interrupt enabled (0xxxxx to disable), disabled by default 0 6 read-write MESR MESR SBS memory erase status register 0x108 0x20 0x00000000 0xFFFFFFFF MEF memory erase flag This bit is set by hardware when BKPRAM and PKA SRAM erase is ongoing after a POWER ON reset or one tamper event (see Section 50: Tamper and backup registers (TAMP) for details). This bit is cleared when the erase is done. 0 1 read-only CCCSR CCCSR SBS I/O compensation cell control and status register 0x110 0x20 0x00000000 0xFFFFFFFF EN Compensation cell enable Set this bit to enable the compensation cell. 0 1 read-write CS Compensation cell code selection This bit selects the code to be applied for the I/O compensation cell. 1 1 read-write OCTO1_COMP_EN XSPIM_P1 compensation cell enable Set this bit to enable the XSPIM_P1 compensation cell. 2 1 read-write OCTO1_COMP_CODESEL XSPIM_P1 compensation cell code selection This bit selects the code to be applied for the XSPIM_P1 I/O compensation cell. 3 1 read-write OCTO2_COMP_EN XSPIM_P2 compensation cell enable Set this bit to enable the XSPIM_P2 compensation cell. 4 1 read-only OCTO2_COMP_CODESEL XSPIM_P2 compensation cell code selection This bit selects the code to be applied for the XSPIM_P2 I/O compensation cell. 5 1 read-only READY Compensation cell ready This bit provides the status of the compensation cell. 8 1 read-only OCTO1_COMP_RDY XSPIM_P1 compensation cell ready This bit provides the status of the XSPIM_P1 compensation cell. 9 1 read-only OCTO2_COMP_RDY XSPIM_P2 compensation cell ready This bit provides the status of the XSPIM_P2 compensation cell. 10 1 read-only HSLV I/O high speed at low voltage When this bit is set, the speed of the I/Os is optimized when the device voltage is low. This bit is active only if VDDIO_HSLV user option bit is set in FLASH. It must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. 16 1 read-write OCTO1_IOHSLV XSPIM_P1 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P1 I/Os is optimized when the device voltage is low. This bit is active only if OCTO1_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. 17 1 read-write OCTO2_IOHSLV XSPIM_P2 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P2 I/Os is optimized when the device voltage is low. This bit is active only if OCTO2_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. 18 1 read-write CCVALR CCVALR SBS compensation cell for I/Os value register 0x114 0x20 0x00000088 0xFFFFFFFF NSRC NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register. 0 4 read-only PSRC PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register. 4 4 read-only OCTO1_NSRC XSPIM_P1 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register. 8 4 read-only OCTO1_PSRC XSPIM_P1 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register. 12 4 read-only OCTO2_NSRC XSPIM_P2 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register. 16 4 read-only OCTO2_PSRC XSPIM_P2 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register. 20 4 read-only CCSWVALR CCSWVALR SBS compensation cell for I/Os software value register 0x118 0x20 0x00000088 0xFFFFFFFF SW_NSRC Software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register. 0 4 read-write SW_PSRC Software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register. 4 4 read-write OCTO1_SW_NSRC XSPIM_P1 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew -ate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register. 8 4 read-write OCTO1_SW_PSRC XSPIM_P1 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register. 12 4 read-write OCTO2_SW_NSRC XSPIM_P2 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register. 16 4 read-write OCTO2_SW_PSRC XSPIM_P2 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register. 20 4 read-write BKLOCKR BKLOCKR SBS break lockup register 0x120 0x20 0x00000088 0xFFFFFFFF PVD_BL PVD break lock This bit is set by SW and cleared only by a system reset. it can be used to enable and lock the connection to TIM1/8/15/16/17Break input as well as the PVDE and PLS[2:0] bitfields in the PWR_CR1 register. Once set, this bit is cleared only by a system reset. 2 1 read-write FLASHECC_BL Flash ECC error break lock Set this bit to enable and lock the connection between embedded flash memory ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. 3 1 read-write CM7LCKUP_BL Cortex-M7 lockup break lock Set this bit to enable and lock the connection between the Cortex-M7 lockup (HardFault) output and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. 6 1 read-write BKRAMECC_BL Backup RAM ECC error break lock Set this bit to enable and lock the connection between backup RAM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. 7 1 read-write DTCMECC_BL DTCM ECC error break lock Set this bit to enable and lock the connection between DTCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. Note: The DTCM0 and DTCM1 are Ored to give DTCMECC 13 1 read-write ITCMECC_BL ITCM ECC error break lock Set this bit to enable and lock the connection between ITCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. 14 1 read-write ARAM3ECC_BL AXIRAM3 ECC error break lock Set this bit to enable and lock the connection between AXIRAM3 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set this bit is cleared only by a system reset. 21 1 read-write ARAM1ECC_BL AXIRAM1 ECC error break lock Set this bit to enable and lock the connection between AXIRAM1 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. 23 1 read-write EXTICR1 EXTICR0 SBS external interrupt configuration register 0 0x130 0x20 read-write 0x00000000 0xFFFFFFFF PC_EXTI0 Port configuration EXTI {0 * 4 + i} This bitfield selects the source input to the EXTI input {0 * 4 + i} used for external interrupt/ event detection. Others: reserved 0 4 read-only PC_EXTI1 Port configuration EXTI {0 * 4 + i} This bitfield selects the source input to the EXTI input {0 * 4 + i} used for external interrupt/ event detection. Others: reserved 4 4 read-only PC_EXTI2 Port configuration EXTI {0 * 4 + i} This bitfield selects the source input to the EXTI input {0 * 4 + i} used for external interrupt/ event detection. Others: reserved 8 4 read-only PC_EXTI3 Port configuration EXTI {0 * 4 + i} This bitfield selects the source input to the EXTI input {0 * 4 + i} used for external interrupt/ event detection. Others: reserved 12 4 read-only EXTICR2 EXTICR1 SBS external interrupt configuration register 1 0x134 0x20 read-write 0x00000000 0xFFFFFFFF PC_EXTI4 Port configuration EXTI {1 * 4 + i} This bitfield selects the source input to the EXTI input {1 * 4 + i} used for external interrupt/ event detection. Others: reserved 0 4 read-only PC_EXTI5 Port configuration EXTI {1 * 4 + i} This bitfield selects the source input to the EXTI input {1 * 4 + i} used for external interrupt/ event detection. Others: reserved 4 4 read-only PC_EXTI6 Port configuration EXTI {1 * 4 + i} This bitfield selects the source input to the EXTI input {1 * 4 + i} used for external interrupt/ event detection. Others: reserved 8 4 read-only PC_EXTI7 Port configuration EXTI {1 * 4 + i} This bitfield selects the source input to the EXTI input {1 * 4 + i} used for external interrupt/ event detection. Others: reserved 12 4 read-only EXTICR3 EXTICR2 SBS external interrupt configuration register 2 0x138 0x20 read-write 0x00000000 0xFFFFFFFF PC_EXTI8 Port configuration EXTI {2 * 4 + i} This bitfield selects the source input to the EXTI input {2 * 4 + i} used for external interrupt/ event detection. Others: reserved 0 4 read-only PC_EXTI9 Port configuration EXTI {2 * 4 + i} This bitfield selects the source input to the EXTI input {2 * 4 + i} used for external interrupt/ event detection. Others: reserved 4 4 read-only PC_EXTI10 Port configuration EXTI {2 * 4 + i} This bitfield selects the source input to the EXTI input {2 * 4 + i} used for external interrupt/ event detection. Others: reserved 8 4 read-only PC_EXTI11 Port configuration EXTI {2 * 4 + i} This bitfield selects the source input to the EXTI input {2 * 4 + i} used for external interrupt/ event detection. Others: reserved 12 4 read-only EXTICR4 EXTICR3 SBS external interrupt configuration register 3 0x13C 0x20 read-write 0x00000000 0xFFFFFFFF PC_EXTI12 Port configuration EXTI {3 * 4 + i} This bitfield selects the source input to the EXTI input {3 * 4 + i} used for external interrupt/ event detection. Others: reserved 0 4 read-only PC_EXTI13 Port configuration EXTI {3 * 4 + i} This bitfield selects the source input to the EXTI input {3 * 4 + i} used for external interrupt/ event detection. Others: reserved 4 4 read-only PC_EXTI14 Port configuration EXTI {3 * 4 + i} This bitfield selects the source input to the EXTI input {3 * 4 + i} used for external interrupt/ event detection. Others: reserved 8 4 read-only PC_EXTI15 Port configuration EXTI {3 * 4 + i} This bitfield selects the source input to the EXTI input {3 * 4 + i} used for external interrupt/ event detection. Others: reserved 12 4 read-only SDMMC1 Secure digital input/output MultiMediaCard interface SDMMC 0x52007000 0x0 0x400 registers SDMMC1 SDMMC1 global interrupt 108 POWER POWER SDMMC power control register 0x0 0x20 0x00000000 0xFFFFFFFF PWRCTRL SDMMC state control bits These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL different from 11). These bits are used to define the functional state of the SDMMC signals: When written 00, power-off: the SDMMC is disabled and the clock to the card is stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven high. Any further write is ignored, PWRCTRL value keeps 11. 0 2 read-write VSWITCH Voltage switch sequence start This bit is used to start the timing critical section of the voltage switch sequence: 2 1 read-write VSWITCHEN Voltage switch procedure enable This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response: 3 1 read-write DIRPOL Data and command direction signals polarity selection This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). 4 1 read-write CLKCR CLKCR SDMMC clock control register 0x4 0x20 0x00000000 0xFFFFFFFF CLKDIV Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (sdmmc_ker_ck) and the output clock (SDMMC_CK): SDMMC_CK frequency = sdmmc_ker_ck / [2 * CLKDIV]. 0x0XX: etc.. 0xXXX: etc.. 0 10 read-write PWRSAV Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: 12 1 read-write WIDBUS Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 14 2 read-write NEGEDGE SDMMC_CK dephasing selection bit for data and command This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. Command and data changed on the sdmmc_ker_ck falling edge succeeding the rising edge of SDMMC_CK. SDMMC_CK edge occurs on sdmmc_ker_ck rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: Command changed on the sdmmc_ker_ck falling edge succeeding the rising edge of SDMMC_CK. Data changed on the sdmmc_ker_ck falling edge succeeding a SDMMC_CK edge. SDMMC_CK edge occurs on sdmmc_ker_ck rising edge. Command and data changed on the same sdmmc_ker_ck rising edge generating the SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 1: Command changed on the same sdmmc_ker_ck rising edge generating the SDMMC_CK falling edge. Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. SDMMC_CK edge occurs on sdmmc_ker_ck rising edge. 16 1 read-write HWFC_EN Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, see SDMMC status register definition in Section 58.10.11. 17 1 read-write DDR Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate must only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate must only be selected with clock division >1. (CLKDIV > 0) 18 1 read-write BUSSPEED Bus speed for selection of SDMMC operating modes This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 19 1 read-write SELCLKRX Receive clock selection These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 20 2 read-write ARGR ARGR SDMMC argument register 0x8 0x20 0x00000000 0xFFFFFFFF CMDARG Command argument These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. 0 32 read-write CMDR CMDR SDMMC command register 0xC 0x20 0x00000000 0xFFFFFFFF CMDINDEX Command index This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. 0 6 read-write CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. 6 1 read-write CMDSTOP The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the abort signal to the DPSM when the command is sent. 7 1 read-write WAITRESP Wait for response bits This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 8 2 read-write WAITINT CPSM waits for interrupt request If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, it causes the abort of the interrupt mode. 10 1 read-write WAITPEND CPSM waits for end of data transfer (CmdPend internal signal) from DPSM This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = e.MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. 11 1 read-write CPSMEN Command path state machine (CPSM) enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command is transfered nor boot procedure is started. CPSMEN is cleared to 0. During Read Wait with SDMMC_CK stopped no command is sent and CPSMEN is kept 0. 12 1 read-write DTHOLD Hold new data block transmission and reception in the DPSM If this bit is set, the DPSM does not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. 13 1 read-write BOOTMODE Select the boot mode procedure to be used This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) 14 1 read-write BOOTEN Enable boot mode procedure 15 1 read-write CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. 16 1 read-write RESPCMDR RESPCMDR SDMMC command response register 0x10 0x20 0x00000000 0xFFFFFFFF RESPCMD Response command index Read-only bit field. Contains the command index of the last command response received. 0 6 read-only RESP1R RESP1R SDMMC response 1 register 0x14 0x20 0x00000000 0xFFFFFFFF CARDSTATUS Card status according table below See Table 444. 0 32 read-only RESP2R RESP2R SDMMC response 2 register 0x18 0x20 0x00000000 0xFFFFFFFF CARDSTATUS Card status according table below See Table 444. 0 32 read-only RESP3R RESP3R SDMMC response 3 register 0x1C 0x20 0x00000000 0xFFFFFFFF CARDSTATUS Card status according table below See Table 444. 0 32 read-only RESP4R RESP4R SDMMC response 4 register 0x20 0x20 0x00000000 0xFFFFFFFF CARDSTATUS Card status according table below See Table 444. 0 32 read-only DTIMER DTIMER SDMMC data timer register 0x24 0x20 0x00000000 0xFFFFFFFF DATATIME Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. 0 32 read-write DLENR DLENR SDMMC data length register 0x28 0x20 0x00000000 0xFFFFFFFF DATALENGTH Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data are transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command is transfered. DTEN and CPSMEN are cleared to 0. 0 25 read-write DCTRL DCTRL SDMMC data control register 0x2C 0x20 0x00000000 0xFFFFFFFF DTEN Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit must only be used to transfer data when no associated data transfer command is used, i.e. must not be used with SD or e.MMC cards. 0 1 read-write DTDIR Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 read-write DTMODE Data transfer mode selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 2 2 read-write DBLOCKSIZE Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (None of the remaining data are transfered.) When DDR = 1, DBLOCKSIZE = 0000 must not be used. (No data are transfered) 4 4 read-write RWSTART Read Wait start If this bit is set, Read Wait operation starts. 8 1 read-write RWSTOP Read Wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the R_W state to the Wait_R or Idle state. 9 1 read-write RWMOD Read Wait mode This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 10 1 read-write SDIOEN SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. 11 1 read-write BOOTACKEN Enable the reception of the boot acknowledgment This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 12 1 read-write FIFORST FIFO reset, flushes any remaining data This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit only takes effect when a transfer error or transfer hold occurs. 13 1 read-write DCNTR DCNTR SDMMC data counter register 0x30 0x20 0x00000000 0xFFFFFFFF DATACOUNT Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. 0 25 read-only STAR STAR SDMMC status register 0x34 0x20 0x00000000 0xFFFFFFFF CCRCFAIL Command response received (CRC check failed) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 0 1 read-only DCRCFAIL Data block sent/received (CRC check failed) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 1 1 read-only CTIMEOUT Command response timeout Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. 2 1 read-only DTIMEOUT Data timeout Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 3 1 read-only TXUNDERR Transmit FIFO underrun error (masked by hardware when IDMA is enabled) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 4 1 read-only RXOVERR Received FIFO overrun error (masked by hardware when IDMA is enabled) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 5 1 read-only CMDREND Command response received (CRC check passed, or no CRC) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 6 1 read-only CMDSENT Command sent (no response required) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 7 1 read-only DATAEND Data transfer ended correctly DATAEND is set if data counter DATACOUNT is zero and no errors occur, and no transmit data transfer hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 8 1 read-only DHOLD Data transfer Hold Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 9 1 read-only DBCKEND Data block sent/received DBCKEND is set when: - CRC check passed and DPSM moves to the R_W state or - IDMAEN = 0 and transmit data transfer hold and DATACOUNT >0 and DPSM moves to Wait_S. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 10 1 read-only DABORT Data transfer aborted by CMD12 Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 11 1 read-only DPSMACT Data path state machine active, i.e. not in Idle state This is a hardware status flag only, does not generate an interrupt. 12 1 read-only CPSMACT Command path state machine active, i.e. not in Idle state This is a hardware status flag only, does not generate an interrupt. 13 1 read-only TXFIFOHE Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. 14 1 read-only RXFIFOHF Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. 15 1 read-only TXFIFOF Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. 16 1 read-only RXFIFOF Receive FIFO full This bit is cleared when one FIFO location becomes empty. 17 1 read-only TXFIFOE Transmit FIFO empty This bit is cleared when one FIFO location becomes full. 18 1 read-only RXFIFOE Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. 19 1 read-only BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. 20 1 read-only BUSYD0END end of SDMMC_D0 Busy following a CMD response detected This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 21 1 read-only SDIOIT SDIO interrupt received The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 22 1 read-only ACKFAIL Boot acknowledgment received (boot acknowledgment check fail) The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 23 1 read-only ACKTIMEOUT Boot acknowledgment timeout The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 24 1 read-only VSWEND Voltage switch critical timing section completion The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 25 1 read-only CKSTOP SDMMC_CK stopped in Voltage switch procedure The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 26 1 read-only IDMATE IDMA transfer error The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 27 1 read-only IDMABTC IDMA buffer transfer complete The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 28 1 read-only ICR ICR SDMMC interrupt clear register 0x38 0x20 0x00000000 0xFFFFFFFF CCRCFAILC CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. 0 1 read-write DCRCFAILC DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 1 1 read-write CTIMEOUTC CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 2 1 read-write DTIMEOUTC DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. 3 1 read-write TXUNDERRC TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. 4 1 read-write RXOVERRC RXOVERR flag clear bit Set by software to clear the RXOVERR flag. 5 1 read-write CMDRENDC CMDREND flag clear bit Set by software to clear the CMDREND flag. 6 1 read-write CMDSENTC CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 7 1 read-write DATAENDC DATAEND flag clear bit Set by software to clear the DATAEND flag. 8 1 read-write DHOLDC DHOLD flag clear bit Set by software to clear the DHOLD flag. 9 1 read-write DBCKENDC DBCKEND flag clear bit Set by software to clear the DBCKEND flag. 10 1 read-write DABORTC DABORT flag clear bit Set by software to clear the DABORT flag. 11 1 read-write BUSYD0ENDC BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. 21 1 read-write SDIOITC SDIOIT flag clear bit Set by software to clear the SDIOIT flag. 22 1 read-write ACKFAILC ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. 23 1 read-write ACKTIMEOUTC ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. 24 1 read-write VSWENDC VSWEND flag clear bit Set by software to clear the VSWEND flag. 25 1 read-write CKSTOPC CKSTOP flag clear bit Set by software to clear the CKSTOP flag. 26 1 read-write IDMATEC IDMA transfer error clear bit Set by software to clear the IDMATE flag. 27 1 read-write IDMABTCC IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. 28 1 read-write MASKR MASKR SDMMC mask register 0x3C 0x20 0x00000000 0xFFFFFFFF CCRCFAILIE Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0 1 read-write DCRCFAILIE Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 1 1 read-write CTIMEOUTIE Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 2 1 read-write DTIMEOUTIE Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 3 1 read-write TXUNDERRIE Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 4 1 read-write RXOVERRIE Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 5 1 read-write CMDRENDIE Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 6 1 read-write CMDSENTIE Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 7 1 read-write DATAENDIE Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 8 1 read-write DHOLDIE Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. 9 1 read-write DBCKENDIE Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 10 1 read-write DABORTIE Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. 11 1 read-write TXFIFOHEIE Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 14 1 read-write RXFIFOHFIE Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 15 1 read-write RXFIFOFIE Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 17 1 read-write TXFIFOEIE Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 18 1 read-write BUSYD0ENDIE BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. 21 1 read-write SDIOITIE SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 22 1 read-write ACKFAILIE Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. 23 1 read-write ACKTIMEOUTIE Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. 24 1 read-write VSWENDIE Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. 25 1 read-write CKSTOPIE Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. 26 1 read-write IDMABTCIE IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. 28 1 read-write ACKTIMER ACKTIMER SDMMC acknowledgment timer register 0x40 0x20 0x00000000 0xFFFFFFFF ACKTIME Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. 0 25 read-write IDMACTRLR IDMACTRLR SDMMC DMA control register 0x50 0x20 0x00000000 0xFFFFFFFF IDMAEN IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 1 read-write IDMABMODE Buffer mode selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 read-write IDMABSIZER IDMABSIZER SDMMC IDMA buffer size register 0x54 0x20 0x00000000 0xFFFFFFFF IDMABNDT Number of bytes per buffer This 12-bit value must be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x001: buffer size = 8 words = 32 bytes. Example: IDMABNDT = 0x800: buffer size = 16384 words = 64 Kbyte. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). 5 12 read-write IDMABASER IDMABASER SDMMC IDMA buffer base address register 0x58 0x20 0x00000000 0xFFFFFFFF IDMABASE Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only) This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1). 0 32 read-write IDMALAR IDMALAR SDMMC IDMA linked list address register 0x64 0x20 0x00000000 0xFFFFFFFF IDMALA Word aligned linked list item address offset Linked list item offset pointer to the base of the next linked list item structure. Linked list item base address is IDMABA + IDMALA. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). 2 14 read-write ABR Acknowledge linked list buffer ready This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is not taken into account when starting the first linked list buffer from the software programmed register information. ABR is only taken into account on subsequent loaded linked list items. 29 1 read-write ULS Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1) This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 30 1 read-write ULA Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode) This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 31 1 read-write IDMABAR IDMABAR SDMMC IDMA linked list memory base register 0x68 0x20 0x00000000 0xFFFFFFFF IDMABA Word aligned Linked list memory base address Linked list memory base pointer. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). 2 30 read-write 16 0x4 0-15 FIFOR%s FIFOR%s SDMMC data FIFO registers %s 0x80 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT = 1). The FIFO data occupies 16 entries of 32-bit words. 0 32 read-write SDMMC2 0x48002400 SDMMC2 SDMMC2 global interrupt 109 SPDIFRX SPDIF receiver interface 0x40004000 0x0 0x1C registers SPDIF_RX SPDIFRX global interrupt 124 CR CR SPDIFRX control register 0x0 0x20 0x00000000 0xFFFFFFFF SPDIFRXEN Peripheral block enable(1) This field is modified by software. It must be used to change the peripheral phase among the three possible states: STATE_IDLE, STATE_SYNC and STATE_RCV. It is not possible to transition from STATE_RCV to STATE_SYNC, the user must first go the STATE_IDLE. Note: it is possible to transition from STATE_IDLE to STATE_RCV: in that case the peripheral transitions from STATE_IDLE to STATE_SYNC and as soon as the synchronization is performed goes to STATE_RCV. 0 2 read-write RXDMAEN Receiver DMA enable for data flow(1) This bit is set/reset by software. Note: When this bit is set, the DMA request is made whenever the RXNE flag is set. 2 1 read-write RXSTEO Stereo mode(1) This bit is set/reset by software. Note: This bit is used in case of overrun situation in order to handle misalignment. 3 1 read-write DRFMT RX data format(1) This bit is set/reset by software. 4 2 read-write PMSK Mask parity error bit(1) This bit is set/reset by software. 6 1 read-write VMSK Mask of validity bit(1) This bit is set/reset by software. 7 1 read-write CUMSK Mask of channel status and user bits(1) This bit is set/reset by software. 8 1 read-write PTMSK Mask of preamble type bits(1) This bit is set/reset by software. 9 1 read-write CBDMAEN Control buffer DMA enable for control flow(1) This bit is set/reset by software. Note: When this bit is set, the DMA request is made whenever the CSRNE flag is set. 10 1 read-write CHSEL Channel selection(1) This bit is set/reset by software. 11 1 read-write NBTR Maximum allowed re-tries during synchronization phase(1) 12 2 read-write WFA Wait for activity(1) This bit is set/reset by software. 14 1 read-write INSEL SPDIFRX input selection other: reserved 16 3 read-write CKSEN Symbol clock enable This bit is set/reset by software. 20 1 read-write CKSBKPEN Backup symbol clock enable This bit is set/reset by software. 21 1 read-write IMR IMR SPDIFRX interrupt mask register 0x4 0x20 0x00000000 0xFFFFFFFF RXNEIE RXNE interrupt enable This bit is set and cleared by software. 0 1 read-write CSRNEIE Control buffer ready interrupt enable This bit is set and cleared by software. 1 1 read-write PERRIE Parity error interrupt enable This bit is set and cleared by software. 2 1 read-write OVRIE Overrun error interrupt enable This bit is set and cleared by software. 3 1 read-write SBLKIE Synchronization block detected interrupt enable This bit is set and cleared by software. 4 1 read-write SYNCDIE Synchronization done This bit is set and cleared by software. 5 1 read-write IFEIE Serial interface error interrupt enable This bit is set and cleared by software. 6 1 read-write SR SR SPDIFRX status register 0x8 0x20 0x00000000 0xFFFFFFFF RXNE Read data register not empty This bit is set by hardware when a valid data is available into SPDIFRX_FMTx_DR register. This flag is cleared by reading the SPDIFRX_FMTx_DR register. An interrupt is generated if RXNEIE=1 in the SPDIFRX_IMR register. 0 1 read-only CSRNE Control buffer register not empty This bit is set by hardware when a valid control information is ready. This flag is cleared when reading SPDIFRX_CSR register. An interrupt is generated if CBRDYIE = 1 in the SPDIFRX_IMR register. 1 1 read-only PERR Parity error This bit is set by hardware when the data and status bits of the sub-frame received contain an odd number of 0 and 1. This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_IFCR register. An interrupt is generated if PIE = 1 in the SPDIFRX_IMR register. 2 1 read-only OVR Overrun error This bit is set by hardware when a received data is ready to be transferred in the SPDIFRX_FMTx_DR register while RXNE = 1 and both SPDIFRX_FMTx_DR and RX_BUF are full. This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_IFCR register. An interrupt is generated if OVRIE=1 in the SPDIFRX_IMR register. Note: When this bit is set, the SPDIFRX_FMTx_DR register content is not lost but the last data received are. 3 1 read-only SBD Synchronization block detected This bit is set by hardware when a B preamble is detected. This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_IFCR register. An interrupt is generated if SBLKIE = 1 in the SPDIFRX_IMR register. 4 1 read-only SYNCD Synchronization done This bit is set by hardware when the initial synchronization phase is properly completed. This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_IFCR register. An interrupt is generated if SYNCDIE = 1 in the SPDIFRX_IMR register. 5 1 read-only FERR Framing error This bit is set by hardware when an error occurs during data reception: such as preamble not at the expected place, short transition not grouped by pairs. This is set by the hardware only if the synchronization is completed (SYNCD = 1). This flag is cleared by writing SPDIFRXEN to 0. An interrupt is generated if IFEIE=1 in the SPDIFRX_IMR register. 6 1 read-only SERR Synchronization error This bit is set by hardware when the synchronization fails due to amount of re-tries for NBTR. This flag is cleared by writing SPDIFRXEN to 0. An interrupt is generated if IFEIE = 1 in the SPDIFRX_IMR register. 7 1 read-only TERR Time-out error This bit is set by hardware when the counter TRCNT reaches its max value. It indicates that the time interval between two transitions is too long. It generally indicates that there is no valid signal on SPDIFRX_IN input. This flag is cleared by writing SPDIFRXEN to 0. An interrupt is generated if IFEIE=1 in the SPDIFRX_IMR register. 8 1 read-only WIDTH5 duration of 5 symbols counted with spdifrx_ker_ck This value represents the amount of spdifrx_ker_ck clock periods contained on a length of 5 consecutive symbols. This value can be used to estimate the S/PDIF symbol rate. Its accuracy is limited by the frequency of spdifrx_ker_ck. For example if the spdifrx_ker_ck is fixed to 84 MHz, and WIDTH5 = 147d. The estimated sampling rate of the S/PDIF stream is: Fs = 5 x Fspdifrx_ker_ck / (WIDTH5 x 64) ~ 44.6 kHz, so the closest standard sampling rate is 44.1 kHz. Note that WIDTH5 is updated by the hardware when SYNCD goes high, and then every frame. 16 15 read-only IFCR IFCR SPDIFRX interrupt flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF PERRCF clears the parity error flag Writing 1 in this bit clears the flag PERR in the SPDIFRX_SR register. Reading this bit always returns the value 0. 2 1 write-only OVRCF clears the overrun error flag Writing 1 in this bit clears the flag OVR in the SPDIFRX_SR register. Reading this bit always returns the value 0. 3 1 write-only SBDCF clears the synchronization block detected flag Writing 1 in this bit clears the flag SBD in the SPDIFRX_SR register. Reading this bit always returns the value 0. 4 1 write-only SYNCDCF clears the synchronization done flag Writing 1 in this bit clears the flag SYNCD in the SPDIFRX_SR register. Reading this bit always returns the value 0. 5 1 write-only FMT0_DR FMT0_DR SPDIFRX data input register 0x10 0x20 0x00000000 0xFFFFFFFF DR data value Contains the 24 received data bits, aligned on D[23] 0 24 read-only PE parity error bit Contains a copy of PERR bit if PMSK = 0, otherwise it is forced to 0 24 1 read-only V validity bit Contains the received validity bit if VMSK = 0, otherwise it is forced to 0 25 1 read-only U user bit Contains the received user bit, if CUMSK = 0, otherwise it is forced to 0 26 1 read-only C channel status bit Contains the received channel status bit, if CUMSK = 0, otherwise it is forced to 0 27 1 read-only PT preamble type These bits indicate the preamble received. Note that if PTMSK = 1, this field is forced to zero 28 2 read-only FMT0_DR_alternate1 FMT0_DR_alternate1 SPDIFRX data input register FMT0_DR 0x10 0x20 0x00000000 0xFFFFFFFF PE parity error bit Contains a copy of PERR bit if PMSK = 0, otherwise it is forced to 0 0 1 read-only V validity bit Contains the received validity bit if VMSK = 0, otherwise it is forced to 0 1 1 read-only U user bit Contains the received user bit, if CUMSK = 0, otherwise it is forced to 0 2 1 read-only C channel Status bit Contains the received channel status bit, if CUMSK = 0, otherwise it is forced to 0 3 1 read-only PT preamble type These bits indicate the preamble received. Note that if PTMSK = 1, this field is forced to zero 4 2 read-only DR data value Contains the 24 received data bits, aligned on D[23] 8 24 read-only FMT0_DR_alternate2 FMT0_DR_alternate2 SPDIFRX data input register FMT0_DR 0x10 0x20 0x00000000 0xFFFFFFFF DRNL1 data value This field contains the channel B 0 16 read-only DRNL2 data value This field contains the channel A 16 16 read-only CSR CSR SPDIFRX channel status register 0x14 0x20 0x00000000 0xFFFFFFFF USR user data information Bit USR[0] is the oldest value, and comes from channel A, USR[1] comes channel B. So USR[n] bits come from channel A is n is even, otherwise they come from channel B. 0 16 read-only CS channel A status information Bit CS[0] is the oldest value 16 8 read-only SOB start of block This bit indicates if the bit CS[0] corresponds to the first bit of a new block 24 1 read-only DIR DIR SPDIFRX debug information register 0x18 0x20 0x00000000 0xFFFFFFFF THI threshold HIGH (THI = 2.5 x UI / Tspdifrx_ker_ck) This field contains the current threshold HIGH estimation. This value can be used to estimate the sampling rate of the received stream. The accuracy of THI is limited to a period of the spdifrx_ker_ck. The sampling rate can be estimated as follow: Sampling Rate = [2 x THI x Tspdifrx_ker_ck +/- Tspdifrx_ker_ck] x 2/5 Note that THI is updated by the hardware when SYNCD goes high, and then every frame. 0 13 read-only TLO threshold LOW (TLO = 1.5 x UI / Tspdifrx_ker_ck) This field contains the current threshold LOW estimation. This value can be used to estimate the sampling rate of the received stream. The accuracy of TLO is limited to a period of the spdifrx_ker_ck. The sampling rate can be estimated as follow: Sampling Rate = [2 x TLO x Tspdifrx_ker_ck +/- Tspdifrx_ker_ck] x 2/3 Note that TLO is updated by the hardware when SYNCD goes high, and then every frame. 16 13 read-only SPI1 Serial peripheral interface SPI 0x42003000 0x0 0x400 registers SPI1 SPI1 global interrupt 58 CR1 CR1 SPI/I2S control register 1 0x0 0x20 0x00000000 0xFFFFFFFF SPE serial peripheral enable This bit is set by and cleared by software. When SPE = 1, SPI data transfer is enabled, SPI_CFG1 and SPI_CFG2 configuration registers, CRCPOLY, UDRDR, IOLOCK bit in the SPI_CR1 register are write protected. They can be changed only when SPE = 0. When SPE = 0 any SPI operation is stopped and disabled, all the pending requests of the events with enabled interrupt are blocked except the MODF interrupt request (but their pending still propagates the request of the spi_plck clock), the SS output is deactivated at master, the RDY signal keeps not ready status at slave, the internal state machine is reseted, all the FIFOs content is flushed, CRC calculation initialized, receive data register is read zero. SPE is cleared and cannot be set when MODF error flag is active. 0 1 read-write SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 MASRX master automatic suspension in Receive mode This bit is set and cleared by software to control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. When SPI communication is suspended by hardware automatically, it may happen that few bits of next frame are already clocked out due to internal synchronization delay. This is why, the automatic suspension is not quite reliable when size of data drops below 8 bits. In this case, a safe suspension can be achieved by combination with delay inserted between data frames applied when MIDI parameter keeps a non zero value; sum of data size and the interleaved SPI cycles should always produce interval at length of 8 SPI clock periods at minimum. After software clearing of the SUSP bit, the communication resumes and continues by subsequent bits transaction without any next constraint. Prior the SUSP bit is cleared, the user must release the RxFIFO space as much as possible by reading out all the data packets available at RxFIFO based on the RXP flag indication to prevent any subsequent suspension. 8 1 read-write MASRX Disabled Automatic suspend in master receive-only mode disabled 0 Enabled Automatic suspend in master receive-only mode enabled 1 CSTART master transfer start This bit can be set by software if SPI is enabled only to start an SPI or I2S/PCM communication. In SPI mode, it is cleared by hardware when end of transfer (EOT) flag is set or when a transaction suspend request is accepted. In I2S/PCM mode, it is also cleared by hardware as described in the Section 80.9.8: Stop sequence. In SPI mode, the bit is taken into account at master mode only. If transmission is enabled, communication starts or continues only if any data is available in the transmission FIFO. 9 1 read-write CSTART NotStarted Do not start master transfer 0 Started Start master transfer 1 CSUSP master suspend request This bit reads as zero. In Master mode, when this bit is set by software, the CSTART bit is reset at the end of the current frame and communication is suspended. The user has to check SUSP flag to check end of the frame transaction. The Master mode communication must be suspended (using this bit or keeping TXDR empty) before going to Low-power mode. Can be used in SPI or I2S mode. After software suspension, SUSP flag must be cleared and SPI disabled and re-enabled before the next transaction starts. 10 1 write-only CSUSPW NotRequested Do not request master suspend 0 Requested Request master suspend 1 HDDIR Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/Tx direction of the data transfer. This bit is ignored in Full-Duplex or any Simplex configuration. 11 1 read-write HDDIR Receiver Receiver in half duplex mode 0 Transmitter Transmitter in half duplex mode 1 SSI internal SS signal input level This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the peripheral SS input internally and the I/O value of the SS pin is ignored. 12 1 read-write SSI SlaveSelected 0 is forced onto the SS signal and the I/O value of the SS pin is ignored 0 SlaveNotSelected 1 is forced onto the SS signal and the I/O value of the SS pin is ignored 1 CRC33_17 32-bit CRC polynomial configuration 13 1 read-write CRC33_17 Disabled Full size (33/17 bit) CRC polynomial is not used 0 Enabled Full size (33/17 bit) CRC polynomial is used 1 RCRCINI CRC calculation initialization pattern control for receiver 14 1 read-write RCRCINI AllZeros All zeros RX CRC initialization pattern 0 AllOnes All ones RX CRC initialization pattern 1 TCRCINI CRC calculation initialization pattern control for transmitter 15 1 read-write TCRCINI AllZeros All zeros TX CRC initialization pattern 0 AllOnes All ones TX CRC initialization pattern 1 IOLOCK locking the AF configuration of associated I/Os This bit can be changed by software only when SPI is disabled (SPE = 0). It is cleared by hardware if a MODF event occurs When this bit is set, SPI_CFG2 register content cannot be modified. This bit is write-protected when SPI is enabled (SPE = 1). 16 1 read-write IOLOCK Unlocked IO configuration unlocked 0 Locked IO configuration locked 1 CR2 CR2 SPI/I2S control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TSIZE number of data at current transfer When these bits are changed by software, the SPI must be disabled. Endless transaction is initialized when CSTART is set while zero value is stored at TSIZE. TSIZE cannot be set to 0xFFFF respective 0x3FFF value when CRC is enabled. Note: TSIZE[15:10] bits are reserved at limited feature set instances and must be kept at reset value. 0 16 read-write 0 65535 CFG1 CFG1 SPI/I2S configuration register 1 0x8 0x20 0x00070007 0xFFFFFFFF DSIZE number of bits in at single SPI data frame ..... Maximum data size can be limited up to 16-bits at some instances. At instances with limited set of features, DSIZE[2:0] bits are reserved and must be kept at reset state. DSIZE[4:3] bits then control next settings of data size: 00xxx: 8-bits 01xxx: 16-bits 10xxx: 24-bits Note: 11xxx: 32-bits. 0 5 read-write 0 31 FTHLV FIFO threshold level Defines number of data frames at single data packet. Size of the packet should not exceed 1/2 of FIFO space. SPI interface is more efficient if configured packet sizes are aligned with data register access parallelism: If SPI data register is accessed as a 16-bit register and DSIZE UNDER OR EQUAL 8 bit, better to select FTHLV = 2, 4, 6. If SPI data register is accessed as a 32-bit register and DSIZE> 8 bit, better to select FTHLV = 2, 4, 6, while if DSIZE UNDER OR EQUAL 8bit, better to select FTHLV = 4, 8, 12. Note: FTHLV[3:2] bits are reserved at instances with limited set of features 5 4 read-write FTHLV OneFrame 1 frame 0 TwoFrames 2 frames 1 ThreeFrames 3 frames 2 FourFrames 4 frames 3 FiveFrames 5 frames 4 SixFrames 6 frames 5 SevenFrames 7 frames 6 EightFrames 8 frames 7 NineFrames 9 frames 8 TenFrames 10 frames 9 ElevenFrames 11 frames 10 TwelveFrames 12 frames 11 ThirteenFrames 13 frames 12 FourteenFrames 14 frames 13 FifteenFrames 15 frames 14 SixteenFrames 16 frames 15 UDRCFG behavior of slave transmitter at underrun condition For more details see Figure 962: Optional configurations of slave detecting underrun condition. 9 1 read-write UDRCFG Constant Slave sends a constant underrun pattern 0 RepeatReceived Slave repeats last received data frame from master 1 RXDMAEN Rx DMA stream enable 14 1 read-write RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx DMA stream enable 15 1 read-write TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 CRCSIZE length of CRC frame to be transacted and compared Most significant bits are taken into account from polynomial calculation when CRC result is transacted or compared. The length of the polynomial is not affected by this setting. ..... The value must be set equal or multiply of data size (DSIZE[4:0]). Its maximum size corresponds to DSIZE maximum at the instance. Note: The most significant bit at CRCSIZE bit field is reserved at the peripheral instances where data size is limited to 16-bit. 16 5 read-write 0 31 CRCEN hardware CRC computation enable 22 1 read-write CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 MBR master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too (see Section 80.5.1: TI mode). 28 3 read-write MBR Div2 f_spi_ker_ck / 2 0 Div4 f_spi_ker_ck / 4 1 Div8 f_spi_ker_ck / 8 2 Div16 f_spi_ker_ck / 16 3 Div32 f_spi_ker_ck / 32 4 Div64 f_spi_ker_ck / 64 5 Div128 f_spi_ker_ck / 128 6 Div256 f_spi_ker_ck / 256 7 BPASS bypass of the prescaler at master baud rate clock generator 31 1 read-write BPASS Disabled Bypass is disabled 0 Enabled Bypass is enabled 1 CFG2 CFG2 SPI/I2S configuration register 2 0xC 0x20 0x00000000 0xFFFFFFFF MSSI Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS opening a session and the beginning of the first data frame of the session in Master mode when SSOE is enabled. ... This feature is not supported in TI mode. Note: To include the delay, the SPI must be disabled and re-enabled between sessions. 0 4 read-write 0 15 MIDI master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in Master mode. ... Note: This feature is not supported in TI mode. 4 4 read-write 0 15 RDIOM RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter than 8-bit, the RDIOM bit must be kept at zero. 13 1 read-write RDIOM Active RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) 0 Pin RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) 1 RDIOP RDY signal input/output polarity 14 1 read-write RDIOP High high level of the signal means the slave is ready for communication 0 Low low level of the signal means the slave is ready for communication 1 IOSWP swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins alternate functions are inverted. Original MISO pin becomes MOSI and original MOSI pin becomes MISO. Note: This bit can be also used in PCM and I2S modes to swap SDO and SDI pins. 15 1 read-write IOSWP Disabled MISO and MOSI not swapped 0 Enabled MISO and MOSI swapped 1 COMM SPI Communication Mode 17 2 read-write COMM FullDuplex Full duplex 0 Transmitter Simplex transmitter only 1 Receiver Simplex receiver only 2 HalfDuplex Half duplex 3 SP serial protocol others: reserved, must not be used 19 3 read-write SP Motorola Motorola SPI protocol 0 TI TI SPI protocol 1 MASTER SPI Master 22 1 read-write MASTER Slave Slave configuration 0 Master Master configuration 1 LSBFRST data frame format Note: This bit can be also used in PCM and I2S modes. 23 1 read-write LSBFRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 CPHA clock phase 24 1 read-write CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CPOL clock polarity 25 1 read-write CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 SSM software management of SS signal input When master uses hardware SS output (SSM = 0 and SSOE = 1) the SS signal input is forced to not active state internally to prevent master mode fault error. 26 1 read-write SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSIOP SS input/output polarity 28 1 read-write SSIOP ActiveLow Low level is active for SS signal 0 ActiveHigh High level is active for SS signal 1 SSOE SS output enable This bit is taken into account in Master mode only 29 1 read-write SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 SSOM SS output management in Master mode This bit is taken into account in Master mode when SSOE is enabled. It allows the SS output to be configured between two consecutive data transfers. 30 1 read-write SSOM Asserted SS is asserted until data transfer complete 0 NotAsserted Data frames interleaved with SS not asserted during MIDI 1 AFCNTR alternate function GPIOs control This bit is taken into account when SPE = 0 only When SPI must be disabled temporary for a specific configuration reason (for example CRC reset, CPHA or HDDIR change) setting this bit prevents any glitches on the associated outputs configured at alternate function mode by keeping them forced at state corresponding the current SPI configuration. Note: This bit can be also used in PCM and I2S modes. Note: The bit AFCNTR must not be set, when the block is in slave mode. 31 1 read-write AFCNTR NotControlled Peripheral takes no control of GPIOs while disabled 0 Controlled Peripheral controls GPIOs while disabled 1 IER IER SPI/I2S interrupt enable register 0x10 0x20 0x00000000 0xFFFFFFFF RXPIE RXP interrupt enable 0 1 read-write RXPIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TXPIE TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event. 1 1 read-write DXPIE DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event. 2 1 read-write EOTIE EOT, SUSP and TXC interrupt enable 3 1 read-write TXTFIE TXTFIE interrupt enable 4 1 read-write UDRIE UDR interrupt enable 5 1 read-write OVRIE OVR interrupt enable 6 1 read-write CRCEIE CRC error interrupt enable 7 1 read-write TIFREIE TIFRE interrupt enable 8 1 read-write MODFIE mode Fault interrupt enable 9 1 read-write SR SR SPI/I2S status register 0x14 0x20 0x00001002 0xFFFFFFFF RXP Rx-packet available The flag is changed by hardware. It monitors the total number of data currently available at RxFIFO if SPI is enabled. RXP value depends on the FIFO threshold (FTHLV[3:0]), data frame size (DSIZE[4:0] in SPI mode and DATLEN[1:0] in I2S/PCM mode), and actual communication flow. If the data packet is read by performing consecutive read operations from SPI_RXDR, RXP flag must be checked again once a complete data packet is read out from RxFIFO. 0 1 read-only RXP Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXP Tx-packet space available TXP flag can be changed only by hardware. Its value depends on the physical size of the FIFO and its threshold (FTHLV[3:0]), data frame size (DSIZE[4:0] in SPI mode and respective DATLEN[1:0] in I2S/PCM mode), and actual communication flow. If the data packet is stored by performing consecutive write operations to SPI_TXDR, TXP flag must be checked again once a complete data packet is stored at TxFIFO. TXP is set despite SPI TxFIFO becomes inaccessible when SPI is reset or disabled. 1 1 read-only TXP Full Tx buffer full 0 NotFull Tx buffer not full 1 DXP duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode. 2 1 read-only DXP Unavailable Duplex packet unavailable: no space for transmission and/or no data received 0 Available Duplex packet available: space for transmission and data received 1 EOT end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when SPI is re-enabled or when TSIZE number of data have been transmitted and/or received on the SPI. EOT is cleared when SPI is re-enabled or by writing 1 to EOTC bit of SPI_IFCR optionally. EOT flag triggers an interrupt if EOTIE bit is set. If DXP flag is used until TXTF flag is set and DXPIE is cleared, EOT can be used to download the last packets contained into RxFIFO in one-shot. In master, EOT event terminates the data transaction and handles SS output optionally. When CRC is applied, the EOT event is extended over the CRC frame transaction. To restart the internal state machine properly, SPI is strongly suggested to be disabled and re-enabled before next transaction starts despite its setting is not changed. 3 1 read-only EOT NotCompleted Transfer ongoing or not started 0 Completed Transfer complete 1 TXTF transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transfer have been submitted for transmission by application software or DMA, that is when TSIZE number of data have been pushed into the TxFIFO. This bit is cleared by software write 1 to TXTFC bit of SPI_IFCR exclusively. TXTF flag triggers an interrupt if TXTFIE bit is set. TXTF setting clears the TXPIE and DXPIE masks so to off-load application software from calculating when to disable TXP and DXP interrupts. 4 1 read-only TXTF NotCompleted Transmission buffer incomplete 0 Completed Transmission buffer filled with at least one transfer 1 UDR underrun This bit is cleared when SPI is re-enabled or by writing 1 to UDRC bit of SPI_IFCR optionally. Note: In SPI mode, the UDR flag applies to Slave mode only. In I2S/PCM mode, (when available) this flag applies to Master and Slave mode 5 1 read-only UDR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 OVR overrun This bit is cleared when SPI is re-enabled or by writing 1 to OVRC bit of SPI_IFCR optionally. 6 1 read-only OVR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 CRCE CRC error This bit is cleared when SPI is re-enabled or by writing 1 to CRCEC bit of SPI_IFCR optionally. 7 1 read-only CRCE NoError No CRC error detected 0 Error CRC error detected 1 TIFRE TI frame format error This bit is cleared by writing 1 to TIFREC bit of SPI_IFCR exclusively. 8 1 read-only TIFRE NoError TI frame format error detected 0 Error TI frame format error detected 1 MODF mode fault When MODF is set, SPE and IOLOCK bits of SPI_CR1 register are reset and setting SPE again is blocked until MODF is cleared. This bit is cleared by writing 1 to MODFC bit of SPI_IFCR exclusively. 9 1 read-only MODF NoFault No mode fault detected 0 Fault Mode fault detected 1 SUSP suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is completed after CSUSP request is done or at master automatic suspend receive mode (MASRX bit is set at SPI_CR1 register) on RxFIFO full condition. SUSP generates an interrupt when EOTIE is set. This bit must be cleared prior SPI is disabled and this is done by writing 1 to SUSPC bit of SPI_IFCR exclusively. 11 1 read-only SUSP NotSuspended Master not suspended 0 Suspended Master suspended 1 TXC TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE = 0, the TXC is changed by hardware exclusively and it raises each time the TxFIFO becomes empty and there is no activity on the bus. If TSIZE different from 0 there is no specific reason to monitor TXC as it just copies the EOT flag value including its software clearing. The TXC generates an interrupt when EOTIE is set. This flag is set when SPI is reset or disabled. 12 1 read-only TXC Ongoing Transmission ongoing 0 Completed Transmission completed 1 RXPLVL RxFIFO packing level When RXWNE = 0 and data size is set up to 16-bit, the value gives number of remaining data frames persisting at RxFIFO. Note: (*): Possible value when data size is set up to 8-bit only. When data size is greater than 16-bit, these bits are always read as 00. In that consequence, the single data frame received at the FIFO cannot be detected neither by RWNE nor by RXPLVL bits if data size is set from 17 to 24 bits. The user must then apply other methods to detect the number of data received, such as monitor the EOT event when TSIZE > 0 or RXP events when FTHLV = 0. 13 2 read-only RXPLVL ZeroFrames Zero frames beyond packing ratio available 0 OneFrame One frame beyond packing ratio available 1 TwoFrames Two frame beyond packing ratio available 2 ThreeFrames Three frame beyond packing ratio available 3 RXWNE RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with RXPLVL[1:0] information about RxFIFO occupancy by residual data. 15 1 read-only RXWNE LessThan32 Less than 32-bit data frame received 0 AtLeast32 At least 32-bit data frame received 1 CTSIZE number of data frames remaining in current TSIZE session The value is not quite reliable when traffic is ongoing on bus . Note: CTSIZE[15:0] bits are not available in instances with limited set of features. 16 16 read-only 0 65535 IFCR IFCR SPI/I2S interrupt/status flags clear register 0x18 0x20 0x00000000 0xFFFFFFFF EOTC end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register 3 1 write-only oneToClear EOTCW Clear Clear interrupt flag 1 TXTFC transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR register 4 1 write-only oneToClear UDRC underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register 5 1 write-only oneToClear OVRC overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register 6 1 write-only oneToClear CRCEC CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register 7 1 write-only oneToClear TIFREC TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register 8 1 write-only oneToClear MODFC mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register 9 1 write-only oneToClear SUSPC Suspend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register 11 1 write-only oneToClear TXDR TXDR SPI/I2S transmit data register 0x20 0x20 0x00000000 0xFFFFFFFF TXDR transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFIFO. Note: In SPI mode, data is always right-aligned. Alignment of data at I2S mode depends on DATLEN and DATFMT setting. Unused bits are ignored when writing to the register, and read as zero when the register is read. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is written by single access. Note: halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be written by single access. Note: word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be written by single access. Note: Write access of this register less than the configured data size is forbidden. 0 32 write-only 0 4294967295 TXDR16 Direct 16-bit access to transmit data register TXDR 0x20 0x10 write-only TXDR Transmit data register 0 16 0 65535 TXDR8 Direct 8-bit access to transmit data register TXDR 0x20 0x8 write-only TXDR Transmit data register 0 8 0 255 RXDR RXDR SPI/I2S receive data register 0x30 0x20 0x00000000 0xFFFFFFFF RXDR receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is accessed. Note: In SPI mode, data is always right-aligned. Alignment of data at I2S mode depends on DATLEN and DATFMT setting. Unused bits are read as zero when the register is read. Writing to the register is ignored. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is read by single access Note: halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be read by single access Note: word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be read by single access. Note: Read access of this register less than the configured data size is forbidden. 0 32 read-only RXDR16 Direct 16-bit access to receive data register RXDR 0x30 0x10 read-only RXDR Receive data register 0 16 RXDR8 Direct 8-bit access to receive data register RXDR 0x30 0x8 read-only RXDR Receive data register 0 8 CRCPOLY CRCPOLY SPI/I2S polynomial register 0x40 0x20 0x00000107 0xFFFFFFFF CRCPOLY CRC polynomial register This register contains the polynomial for the CRC calculation. The default 9-bit polynomial setting 0x107 corresponds to default 8-bit setting of DSIZE. It is compatible with setting 0x07 used in other ST products with fixed length of the polynomial string, where the most significant bit of the string is always kept hidden. Length of the polynomial is given by the most significant bit of the value stored in this register. It must be set greater than DSIZE. CRC33_17 bit must be set additionally with CRCPOLY register when DSIZE is configured to maximum 32-bit or 16-bit size and CRC is enabled (to keep polynomial length grater than data size). Note: CRCPOLY[31:16] bits are reserved at instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 0 32 read-write 0 4294967295 TXCRC TXCRC SPI/I2S transmitter CRC register 0x44 0x20 0x00000000 0xFFFFFFFF TXCRC CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the computed CRC value of the subsequently transmitted bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. Note: A read to this register when the communication is ongoing may return an incorrect value. Note: not used for the I2S mode. Note: TXCRC[31-16] bits are reserved at instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. Note: The configuration of CRCSIZE bit field is not taken into account when the content of this register is read by software. No masking is applied for unused bits in this case. 0 32 read-only 0 4294967295 RXCRC RXCRC SPI/I2S receiver CRC register 0x48 0x20 0x00000000 0xFFFFFFFF RXCRC CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the computed CRC value of the subsequently received bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. Note: A read to this register when the communication is ongoing may return an incorrect value. Note: Not used for the I2S mode. Note: RXCRC[31-16] bits are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. Note: The configuration of CRCSIZE bit field is not taken into account when the content of this register is read by software. No masking is applied for unused bits in this case. 0 32 read-only 0 4294967295 UDRDR UDRDR SPI/I2S underrun data register 0x4C 0x20 0x00000000 0xFFFFFFFF UDRDR data at slave underrun condition The register is taken into account in Slave mode and at underrun condition only. The number of bits considered depends on DSIZE bit settings of the SPI_CFG1 register. Underrun condition handling depends on setting UDRCFG bit at SPI_CFG1 register. Note: UDRDR[31-16] bits are reserved at the peripheral instances with data size limited to 16-bit. There is no constraint when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 0 32 read-write 0 4294967295 I2SCFGR I2SCFGR SPI/I2S configuration register 0x50 0x20 0x00000000 0xFFFFFFFF I2SMOD I2S mode selection 0 1 read-write I2SMOD SPI SPI mode selected 0 I2S I2S/PCM mode selected 1 I2SCFG I2S configuration mode others, not used 1 3 read-write I2SCFG SlaveTransmit Slave, transmit 0 SlaveReceive Slave, recteive 1 MasterTransmit Master, transmit 2 MasterReceive Master, receive 3 SlaveFullDuplex Slave, full duplex 4 MasterFullDuplex Master, full duplex 5 I2SSTD I2S standard selection For more details on I2S standards, refer to Section 80.9.5: Supported audio protocols 4 2 read-write I2SSTD Philips I2S Philips standard 0 LeftAligned MSB/left justified standard 1 RightAligned LSB/right justified standard 2 PCM PCM standard 3 PCMSYNC PCM frame synchronization 7 1 read-write PCMSYNC Short Short PCM frame synchronization 0 Long Long PCM frame synchronization 1 DATLEN data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 80.3: SPI implementation to check the supported data size. 8 2 read-write DATLEN Bits16 16 bit data length 0 Bits24 24 bit data length 1 Bits32 32 bit data length 2 CHLEN channel length (number of bits per audio channel) 10 1 read-write CHLEN Bits16 16 bit per channel 0 Bits32 32 bit per channel 1 CKPOL serial audio clock polarity 11 1 read-write CKPOL SampleOnRising Signals are sampled on rising and changed on falling clock edges 0 SampleOnFalling Signals are sampled on falling and changed on rising clock edges 1 FIXCH fixed channel length in slave 12 1 read-write FIXCH NotFixed The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account) 0 Fixed The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN) 1 WSINV word select inversion This bit is used to invert the default polarity of WS signal. In MSB or LSB justified mode, the left channel is transferred when WS is HIGH, and the right channel when WS is LOW. In PCM short mode the data transfer starts at the falling edge of WS, while it starts at the rising edge of WS in PCM long mode. In MSB or LSB justified mode, the left channel is transfered when WS is LOW, and right channel when WS is HIGH. In PCM short mode the data transfer starts at the rising edge of WS, while it starts at the falling edge of WS in PCM long mode. 13 1 read-write WSINV Disabled Word select inversion disabled 0 Enabled Word select inversion enabled 1 DATFMT data format 14 1 read-write DATFMT RightAligned The data inside RXDR and TXDR are right aligned 0 LeftAligned The data inside RXDR and TXDR are left aligned 1 I2SDIV I2S linear prescaler I2SDIV can take any values except the value 1, when ODD is also equal to 1. Refer to Section 80.9.9: Clock generator for details 16 8 read-write ODD odd factor for the prescaler Refer to Section 80.9.9: Clock generator for details 24 1 read-write ODD Even Real divider value is I2SDIV*2 0 Odd Real divider value is I2SDIV*2 + 1 1 MCKOE master clock output enable 25 1 read-write MCKOE Disabled Master clock output disabled 0 Enabled Master clock output enabled 1 SPI2 0x40003800 SPI2 SPI2 global interrupt 59 SPI3 0x40003C00 SPI3 SPI3 global interrupt 60 SPI4 0x42003400 SPI4 SPI4 global interrupt 61 SPI5 0x42005000 SPI5 SPI5 global interrupt 62 SPI6 0x58001400 SPI6 SPI6 global interrupt 63 TAMP TAMP register block TAMP 0x58004400 0x0 0x400 registers TAMP RTC tamper and timestamp interrupts through the EXTI line 13 CR1 CR1 TAMP control register 1 0x0 0x20 0x00000000 0xFFFFFFFF TAMP1E Tamper detection on TAMP_IN1 enable 0 1 read-write TAMP2E Tamper detection on TAMP_IN2 enable(1) 1 1 read-write TAMP3E Tamper detection on TAMP_IN3 enable(1) 2 1 read-write TAMP4E Tamper detection on TAMP_IN4 enable(1) 3 1 read-write TAMP5E Tamper detection on TAMP_IN5 enable(1) 4 1 read-write TAMP6E Tamper detection on TAMP_IN6 enable(1) 5 1 read-write TAMP7E Tamper detection on TAMP_IN7 enable(1) 6 1 read-write TAMP8E Tamper detection on TAMP_IN8 enable(1) 7 1 read-write ITAMP1E Internal tamper 1 enable 16 1 read-write ITAMP2E Internal tamper 2 enable 17 1 read-write ITAMP3E Internal tamper 3 enable 18 1 read-write ITAMP4E Internal tamper 4 enable 19 1 read-write ITAMP5E Internal tamper 5 enable 20 1 read-write ITAMP6E Internal tamper 6 enable 21 1 read-write ITAMP7E Internal tamper 7 enable 22 1 read-write ITAMP8E Internal tamper 8 enable 23 1 read-write ITAMP9E Internal tamper 9 enable 24 1 read-write ITAMP11E Internal tamper 11 enable 26 1 read-write ITAMP15E Internal tamper 15 enable 30 1 read-write CR2 CR2 TAMP control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TAMP1NOER Tamper 1 no erase 0 1 read-write TAMP2NOER Tamper 2 no erase 1 1 read-write TAMP3NOER Tamper 3 no erase 2 1 read-write TAMP4NOER Tamper 4 no erase 3 1 read-write TAMP5NOER Tamper 5 no erase 4 1 read-write TAMP6NOER Tamper 6 no erase 5 1 read-write TAMP7NOER Tamper 7 no erase 6 1 read-write TAMP8NOER Tamper 8 no erase 7 1 read-write TAMP1MSK Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set. 16 1 read-write TAMP2MSK Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set. 17 1 read-write TAMP3MSK Tamper 3 mask The tamper 3 interrupt must not be enabled when TAMP3MSK is set. 18 1 read-write BKBLOCK Backup registers and device secrets(1) access blocked 22 1 read-write BKERASE Backup registers and device secrets(1) erase Writing 1 to this bit reset the backup registers and device secrets(1). Writing 0 has no effect. This bit is always read as 0. 23 1 write-only TAMP1TRG Active level for tamper 1 input If TAMPFLT = 00 Tamper 1 input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper 1 input falling edge triggers a tamper detection event. 24 1 read-write TAMP2TRG Active level for tamper 2 input If TAMPFLT = 00 Tamper 2 input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper 2 input falling edge triggers a tamper detection event. 25 1 read-write TAMP3TRG Active level for tamper 3 input If TAMPFLT = 00 Tamper 3 input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper 3 input falling edge triggers a tamper detection event. 26 1 read-write TAMP4TRG Active level for tamper 4 input (active mode disabled) If TAMPFLT = 00 Tamper 4 input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper 4 input falling edge triggers a tamper detection event. 27 1 read-write TAMP5TRG Active level for tamper 5 input (active mode disabled) If TAMPFLT = 00 Tamper 5 input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper 5 input falling edge triggers a tamper detection event. 28 1 read-write TAMP6TRG Active level for tamper 6 input (active mode disabled) If TAMPFLT = 00 Tamper 6 input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper 6 input falling edge triggers a tamper detection event. 29 1 read-write TAMP7TRG Active level for tamper 7 input (active mode disabled) If TAMPFLT = 00 Tamper 7 input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper 7 input falling edge triggers a tamper detection event. 30 1 read-write TAMP8TRG Active level for tamper 8 input (active mode disabled) If TAMPFLT = 00 Tamper 8 input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper 8 input falling edge triggers a tamper detection event. 31 1 read-write CR3 CR3 TAMP control register 3 0x8 0x20 0x00000000 0xFFFFFFFF ITAMP1NOER Internal Tamper 1 no erase 0 1 read-write ITAMP2NOER Internal Tamper 2 no erase 1 1 read-write ITAMP3NOER Internal Tamper 3 no erase 2 1 read-write ITAMP4NOER Internal Tamper 4 no erase 3 1 read-write ITAMP5NOER Internal Tamper 5 no erase 4 1 read-write ITAMP6NOER Internal Tamper 6 no erase 5 1 read-write ITAMP7NOER Internal Tamper 7 no erase 6 1 read-write ITAMP8NOER Internal Tamper 8 no erase 7 1 read-write ITAMP9NOER Internal Tamper 9 no erase 8 1 read-write ITAMP11NOER Internal Tamper 11 no erase 10 1 read-write ITAMP15NOER Internal Tamper 15 no erase 14 1 read-write FLTCR FLTCR TAMP filter control register 0xC 0x20 0x00000000 0xFFFFFFFF TAMPFREQ Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled. 0 3 read-write TAMPFLT TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs. 3 2 read-write TAMPPRCH TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. 5 2 read-write TAMPPUDIS TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample. 7 1 read-write ATCR1 ATCR1 TAMP active tamper control register 1 0x10 0x20 0x00070000 0xFFFFFFFF TAMP1AM Tamper 1 active mode 0 1 read-write TAMP2AM Tamper 2 active mode 1 1 read-write TAMP3AM Tamper 3 active mode 2 1 read-write TAMP4AM Tamper 4 active mode 3 1 read-write TAMP5AM Tamper 5 active mode 4 1 read-write TAMP6AM Tamper 6 active mode 5 1 read-write TAMP7AM Tamper 7 active mode 6 1 read-write TAMP8AM Tamper 8 active mode 7 1 read-write ATOSEL1 Active tamper shared output 1 selection The selected output must be available in the package pinout 8 2 read-write ATOSEL2 Active tamper shared output 2 selection The selected output must be available in the package pinout 10 2 read-write ATOSEL3 Active tamper shared output 3 selection The selected output must be available in the package pinout 12 2 read-write ATOSEL4 Active tamper shared output 4 selection The selected output must be available in the package pinout. 14 2 read-write ATCKSEL Active tamper RTC asynchronous prescaler clock selection These bits selects the RTC asynchronous prescaler stage output. The selected clock is CK_ATPRE. ... Note: These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 CK_ATPRE cycles after all the active tampers are disable. 16 3 read-write ATPER Active tamper output change period The tamper output is changed every CK_ATPER = (2ATPER x CK_ATPRE) cycles. Refer to Table 386: Minimum ATPER value. 24 3 read-write ATOSHARE Active tamper output sharing TAMP_IN1 is compared with TAMPOUTSEL1 TAMP_IN2 is compared with TAMPOUTSEL2 TAMP_IN3 is compared with TAMPOUTSEL3 TAMP_IN4 is compared with TAMPOUTSEL4 TAMP_IN5 is compared with TAMPOUTSEL5 TAMP_IN6 is compared with TAMPOUTSEL6 TAMP_IN7 is compared with TAMPOUTSEL7 TAMP_IN8 is compared with TAMPOUTSEL8 30 1 read-write FLTEN Active tamper filter enable 31 1 read-write ATSEEDR ATSEEDR TAMP active tamper seed register 0x14 0x20 0x00000000 0xFFFFFFFF SEED Pseudo-random generator seed value This register must be written four times with 32-bit values to provide the 128-bit seed to the PRNG. Writing to this register automatically sends the seed value to the PRNG. 0 32 write-only ATOR ATOR TAMP active tamper output register 0x18 0x20 0x00000000 0xFFFFFFFF PRNG Pseudo-random generator value This field provides the values of the PRNG output. Because of potential inconsistencies due to synchronization delays, PRNG must be read at least twice. The read value is correct if it is equal to previous read value. 0 8 read-only SEEDF Seed running flag This flag is set by hardware when a new seed is written in the TAMP_ATSEEDR. It is cleared by hardware when the PRNG has absorbed this new seed, and by system reset. The TAMP APB cock must not be switched off as long as SEEDF is set. 14 1 read-only INITS Active tamper initialization status This flag is set by hardware when the PRNG has absorbed the first 128-bit seed, meaning that the enabled active tampers are functional. This flag is cleared when the active tampers are disabled. 15 1 read-only ATCR2 ATCR2 TAMP active tamper control register 2 0x1C 0x20 0x00000000 0xFFFFFFFF ATOSEL1 Active tamper shared output 1 selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 8 3 read-write ATOSEL2 Active tamper shared output 2 selection The selected output must be available in the package pinout. Bits 12:11 are the mirror of ATOSEL2[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 11 3 read-write ATOSEL3 Active tamper shared output 3 selection The selected output must be available in the package pinout. Bits 15:14 are the mirror of ATOSEL3[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 14 3 read-write ATOSEL4 Active tamper shared output 4 selection The selected output must be available in the package pinout. Bits 18:17 are the mirror of ATOSEL2[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 17 3 read-write ATOSEL5 Active tamper shared output 5 selection The selected output must be available in the package pinout. 20 3 read-write ATOSEL6 Active tamper shared output 6 selection The selected output must be available in the package pinout. 23 3 read-write ATOSEL7 Active tamper shared output 7 selection The selected output must be available in the package pinout. 26 3 read-write ATOSEL8 Active tamper shared output 8 selection The selected output must be available in the package pinout. 29 3 read-write CFGR CFGR TAMP configuration register 0x20 0x20 0x00000000 0xFFFFFFFF BKPRW Backup registers read/write protection offset BKPRW value must be from 0 to 32. Protection zone 1 is defined for backup registers from TAMP_BKP0R to TAMP_BKPxR (x = BKPRW-1, with BKPRW more or equal to 1). If BKPRW = 0: there is no protection zone 1. Refer to Figure 499: Backup registers protection zones. Note: If BKPRWPRIV is set, BKPRW[7:0] can be written only in privileged mode. 0 8 read-write BKPW Backup registers write protection offset BKPW value must be from 0 to 32. Protection zone 2 is defined for backup registers from TAMP_BKPyR (y = BKPRW) to TAMP_BKPzR (z = BKPW-1, with BKPW > BKPRW): If BKPWSEC = 0 or if BKPWSEC UNDER OR EQUAL BKPRWSEC: there is no protection zone 2. Protection zone 3 is defined for backup registers from TAMP_BKPtR (t = BKPW if BKPWSEC more or equal to BKPRWSEC, else t = BKPRWSEC). If BKPWSEC = 32: there is no protection zone 3. Refer to Figure 499: Backup registers protection zones. Note: If BKPWPRIV is set, BKPRW[7:0] can be written only in privileged mode. 16 8 read-write BHKLOCK Boot hardware key lock This bit can be read and can only be written to 1 by software. It is cleared by hardware together with the backup registers following a tamper detection event or when the readout protection (RDP) is disabled. 30 1 read-write PRIVCFGR PRIVCFGR TAMP privilege configuration register 0x24 0x20 0x00000000 0xFFFFFFFF CNT1PRIV Monotonic counter 1 privilege protection 15 1 read-write BKPRWPRIV Backup registers zone 1 privilege protection 29 1 read-write BKPWPRIV Backup registers zone 2 privilege protection 30 1 read-write TAMPPRIV Tamper privilege protection (excluding backup registers) Note: Refer to Section 46.3.6: TAMP privilege protection modes for details on the read protection. 31 1 read-write IER IER TAMP interrupt enable register 0x2C 0x20 0x00000000 0xFFFFFFFF TAMP1IE Tamper 1 interrupt enable 0 1 read-write TAMP2IE Tamper 2 interrupt enable 1 1 read-write TAMP3IE Tamper 3 interrupt enable 2 1 read-write TAMP4IE Tamper 4 interrupt enable 3 1 read-write TAMP5IE Tamper 5 interrupt enable 4 1 read-write TAMP6IE Tamper 6 interrupt enable 5 1 read-write TAMP7IE Tamper 7interrupt enable 6 1 read-write TAMP8IE Tamper 8 interrupt enable 7 1 read-write ITAMP1IE Internal tamper 1 interrupt enable 16 1 read-write ITAMP2IE Internal tamper 2 interrupt enable 17 1 read-write ITAMP3IE Internal tamper 3 interrupt enable 18 1 read-write ITAMP4IE Internal tamper 4 interrupt enable 19 1 read-write ITAMP5IE Internal tamper 5 interrupt enable 20 1 read-write ITAMP6IE Internal tamper 6 interrupt enable 21 1 read-write ITAMP7IE Internal tamper 7 interrupt enable 22 1 read-write ITAMP8IE Internal tamper 8 interrupt enable 23 1 read-write ITAMP9IE Internal tamper 9 interrupt enable 24 1 read-write ITAMP11IE Internal tamper 11 interrupt enable 26 1 read-write ITAMP15IE Internal tamper 15 interrupt enable 30 1 read-write SR SR TAMP status register 0x30 0x20 0x00000000 0xFFFFFFFF TAMP1F TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP1 input. 0 1 read-only TAMP2F TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP2 input. 1 1 read-only TAMP3F TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP3 input. 2 1 read-only TAMP4F TAMP4 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP4 input. 3 1 read-only TAMP5F TAMP5 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP5 input. 4 1 read-only TAMP6F TAMP6 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP6 input. 5 1 read-only TAMP7F TAMP7 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP7 input. 6 1 read-only TAMP8F TAMP8 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP8 input 7 1 read-only ITAMP1F Internal tamper 1 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 1. 16 1 read-only ITAMP2F Internal tamper 2 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 2. 17 1 read-only ITAMP3F Internal tamper 3 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3. 18 1 read-only ITAMP4F Internal tamper 4 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 4. 19 1 read-only ITAMP5F Internal tamper 5 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5. 20 1 read-only ITAMP6F Internal tamper 6 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. 21 1 read-only ITAMP7F Internal tamper 7 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 7. 22 1 read-only ITAMP8F Internal tamper 8 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 8. 23 1 read-only ITAMP9F Internal tamper 9 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 9. 24 1 read-only ITAMP11F Internal tamper 11 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 11. 26 1 read-only ITAMP15F Internal tamper 15 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 15. 30 1 read-write MISR MISR TAMP masked interrupt status register 0x34 0x20 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 interrupt masked flag This flag is set by hardware when the tamper 1 interrupt is raised. 0 1 read-only TAMP2MF TAMP2 interrupt masked flag This flag is set by hardware when the tamper 2 interrupt is raised. 1 1 read-only TAMP3MF TAMP3 interrupt masked flag This flag is set by hardware when the tamper 3 interrupt is raised. 2 1 read-only TAMP4MF TAMP4 interrupt masked flag This flag is set by hardware when the tamper 4 interrupt is raised. 3 1 read-only TAMP5MF TAMP5 interrupt masked flag This flag is set by hardware when the tamper 5 interrupt is raised. 4 1 read-only TAMP6MF TAMP6 interrupt masked flag This flag is set by hardware when the tamper 6 interrupt is raised. 5 1 read-only TAMP7MF TAMP7 interrupt masked flag This flag is set by hardware when the tamper 7 interrupt is raised. 6 1 read-only TAMP8MF TAMP8 interrupt masked flag This flag is set by hardware when the tamper 8 interrupt is raised. 7 1 read-only ITAMP1MF Internal tamper 1 interrupt masked flag This flag is set by hardware when the internal tamper 1 interrupt is raised. 16 1 read-only ITAMP2MF Internal tamper 2 interrupt masked flag This flag is set by hardware when the internal tamper 2 interrupt is raised. 17 1 read-only ITAMP3MF Internal tamper 3 interrupt masked flag This flag is set by hardware when the internal tamper 3 interrupt is raised. 18 1 read-only ITAMP4MF Internal tamper 4 interrupt masked flag This flag is set by hardware when the internal tamper 4 interrupt is raised. 19 1 read-only ITAMP5MF Internal tamper 5 interrupt masked flag This flag is set by hardware when the internal tamper 5 interrupt is raised. 20 1 read-only ITAMP6MF Internal tamper 6 interrupt masked flag This flag is set by hardware when the internal tamper 6 interrupt is raised. 21 1 read-only ITAMP7MF Internal tamper 7 tamper interrupt masked flag This flag is set by hardware when the internal tamper 7 interrupt is raised. 22 1 read-only ITAMP8MF Internal tamper 8 interrupt masked flag This flag is set by hardware when the internal tamper 8 interrupt is raised. 23 1 read-only ITAMP9MF internal tamper 9 interrupt masked flag This flag is set by hardware when the internal tamper 9 interrupt is raised. 24 1 read-only ITAMP11MF internal tamper 11 interrupt masked flag This flag is set by hardware when the internal tamper 11 interrupt is raised. 26 1 read-only ITAMP15MF internal tamper 15 interrupt masked flag This flag is set by hardware when the internal tamper 15 interrupt is raised. 30 1 read-only SCR SCR TAMP status clear register 0x3C 0x20 0x00000000 0xFFFFFFFF CTAMP1F Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register. 0 1 write-only CTAMP2F Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register. 1 1 write-only CTAMP3F Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register. 2 1 write-only CTAMP4F Clear TAMP4 detection flag Writing 1 in this bit clears the TAMP4F bit in the TAMP_SR register. 3 1 write-only CTAMP5F Clear TAMP5 detection flag Writing 1 in this bit clears the TAMP5F bit in the TAMP_SR register. 4 1 write-only CTAMP6F Clear TAMP6 detection flag Writing 1 in this bit clears the TAMP6F bit in the TAMP_SR register. 5 1 write-only CTAMP7F Clear TAMP7 detection flag Writing 1 in this bit clears the TAMP7F bit in the TAMP_SR register. 6 1 write-only CTAMP8F Clear TAMP8 detection flag Writing 1 in this bit clears the TAMP8F bit in the TAMP_SR register. 7 1 write-only CITAMP1F Clear ITAMP1 detection flag Writing 1 in this bit clears the ITAMP1F bit in the TAMP_SR register. 16 1 write-only CITAMP2F Clear ITAMP2 detection flag Writing 1 in this bit clears the ITAMP2F bit in the TAMP_SR register. 17 1 write-only CITAMP3F Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register. 18 1 write-only CITAMP4F Clear ITAMP4 detection flag Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register. 19 1 write-only CITAMP5F Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register. 20 1 write-only CITAMP6F Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register. 21 1 write-only CITAMP7F Clear ITAMP7 detection flag Writing 1 in this bit clears the ITAMP7F bit in the TAMP_SR register. 22 1 write-only CITAMP8F Clear ITAMP8 detection flag Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register. 23 1 write-only CITAMP9F Clear ITAMP9 detection flag Writing 1 in this bit clears the ITAMP9F bit in the TAMP_SR register. 24 1 write-only CITAMP11F Clear ITAMP11 detection flag Writing 1 in this bit clears the ITAMP11F bit in the TAMP_SR register. 26 1 write-only CITAMP15F Clear ITAMP15 detection flag Writing 1 in this bit clears the ITAMP15F bit in the TAMP_SR register. 30 1 write-only COUNT1R COUNT1R TAMP monotonic counter 1 register 0x40 0x20 0x00000000 0xFFFFFFFF COUNT This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value. 0 32 read-only 32 0x4 0-31 BKP%sR BKP%sR TAMP backup %s register 0x100 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write TIM1 Advanced-control timers TIM 0x42000000 0x0 0x3E4 registers TIM1_BRK TIM1 Break interrupt 47 TIM1_UP TIM1 Update interrupt (tim_upd_it) 48 TIM1_TRG_COM TIM1 Trigger and Commutation interrupts 49 TIM1_CC TIM1 Capture Compare interrupt 50 CR1 CR1 TIM1 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (tim_etr_in, tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM1 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS MMS[2:0]: Master mode selection These bits select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: Other codes reserved Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write TI1S tim_ti1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 4 0x2 1-4 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 MMS2 Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (tim_trgo2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 20 4 read-write MMS_3 MMS[3] 25 1 read-write SMCR SMCR TIM1 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo or the tim_trgo2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write TS TS[2:0]: Trigger selection This bitfield is combined with TS[4:3] bits. This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 613: TIMx internal trigger connection for more details on tim_itrx meaning for each Timer. Note: These bits must be changed only when they are not used (for example when SMS = 000) to avoid wrong edge detections at the transition. 4 3 read-write MSM Master/slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be connected to tim_etrf in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write SMSPE SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded 24 1 read-write SMSPS SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active 25 1 read-write DIER DIER TIM1 DMA/interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 read-write COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write DIRIE Direction change interrupt enable 21 1 read-write IERRIE Index error interrupt enable 22 1 read-write TERRIE Transition error interrupt enable 23 1 read-write SR SR TIM1 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to Section 64.6.3: TIM1 slave mode control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag This flag is set by hardware on COM event (when capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 B2IF Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 8 1 read-write zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 SBIF System break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 13 1 read-write zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 CC5IF Compare 5 interrupt flag Refer to CC1IF description Note: Channel 5 can only be configured as output. 16 1 read-write zeroToClear read write CC6IF Compare 6 interrupt flag Refer to CC1IF description Note: Channel 6 can only be configured as output. 17 1 read-write zeroToClear read write IDXF Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by software by writing it to 0. 20 1 read-write DIRF Direction change interrupt flag This flag is set by hardware when the direction changes in encoder mode (DIR bit value in TIMx_CR is changing). It is cleared by software by writing it to 0. 21 1 read-write IERRF Index error interrupt flag This flag is set by hardware when an index error is detected. It is cleared by software by writing it to 0. 22 1 read-write TERRF Transition error interrupt flag This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to 0. 23 1 read-write EGR EGR TIM1 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 B2G Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 8 1 write-only B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Input CCMR1_Input TIM1 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM1 capture/compare mode register 1 CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM1 capture/compare mode register 2 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM1 capture/compare mode register 2 CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM1 capture/compare enable register 0x20 0x20 0x00000000 0xFFFFFFFF 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM1 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM1 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (ftim_cnt_ck) is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). 0 16 read-write 0 65535 ARR ARR TIM1 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 64.3.3: Time-base unit on page 3685 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 RCR RCR TIM1 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable. It also defines the update interrupt generation rate, if this interrupt is enable. When the repetition down-counter reaches zero, an update event is generated and it restarts counting from REP value. As the repetition counter is reloaded with REP value only at the repetition update event UEV, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode. 0 16 read-write 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 BDTR BDTR TIM1 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 64.6.11: TIM1 capture/compare enable register (TIM1_CCER)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 64.6.11: TIM1 capture/compare enable register (TIM1_CCER)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per Figure 618: Break and Break2 circuitry overview). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (tim_brk or tim_brk2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (Section 64.6.11: TIM1 capture/compare enable register (TIM1_CCER)). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample tim_brk input and the length of the digital filter applied to tim_brk. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write BK2F Break 2 filter This bit-field defines the frequency used to sample tim_brk2 input and the length of the digital filter applied to tim_brk2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 20 4 read-write BK2E Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per Figure 618: Break and Break2 circuitry overview). Note: The BRKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 24 1 read-write BK2P Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 25 1 read-write BKDSRM Break disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write BK2DSRM Break2 disarm Refer to BKDSRM description 27 1 read-write BKBID Break bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write BK2BID Break2 bidirectional Refer to BKBID description 29 1 read-write CCR5 CCR5 capture/compare register 0x48 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 GC5C1 Group channel 5 and channel 1 Distortion on channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 29 1 read-write GC5C2 Group channel 5 and channel 2 Distortion on channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 30 1 read-write GC5C3 Group channel 5 and channel 3 Distortion on channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. 31 1 read-write CCR6 CCR6 capture/compare register 0x4C 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 CCMR3_Output CCMR3_Output TIM1 capture/compare mode register 3 0x50 0x20 0x00000000 0xFFFFFFFF 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 5-6 OC%sM Output compare %s mode 4 3 read-write 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write DTR2 DTR2 TIM1 timer deadtime register 2 0x54 0x20 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs, on the falling edge. DTGF[7:5]=0xx => DTF=DTGF[7:0]x tdtg with tdtg=tDTS. DTGF[7:5]=10x => DTF=(64+DTGF[5:0])xtdtg with Tdtg=2xtDTS. DTGF[7:5]=110 => DTF=(32+DTGF[4:0])xtdtg with Tdtg=8xtDTS. DTGF[7:5]=111 => DTF=(32+DTGF[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write DTAE Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 16 1 read-write DTPE Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 17 1 read-write ECR ECR TIM1 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable This bit indicates if the Index event resets the counter. 0 1 read-write IDIR Index direction This bit indicates in which direction the Index event resets the counter. Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled). 1 2 read-write IBLK Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 or tim_ti4 input 3 2 read-write FIDX First index This bit indicates if the first index only is taken into account 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG 16 8 read-write PWPRSC Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following: tPWG = (2(PWPRSC[2:0])) x ttim_ker_ck 24 3 read-write TISEL TISEL TIM1 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input ... Refer to Section 64.3.2: TIM1 pins and internal signals for interconnects list. 0 4 read-write TI2SEL Selects tim_ti2[15:0] input ... Refer to Section 64.3.2: TIM1 pins and internal signals for interconnects list. 8 4 read-write TI3SEL Selects tim_ti3[15:0] input ... Refer to Section 64.3.2: TIM1 pins and internal signals for interconnects list. 16 4 read-write TI4SEL Selects tim_ti4[15:0] input ... Refer to Section 64.3.2: TIM1 pins and internal signals for interconnects list. 24 4 read-write AF1 AF1 TIM1 alternate function option register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timers tim_brk input. TIMx_BKIN input is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKCMP1E tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timers tim_brk input. tim_brk_cmp1 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP2E tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timers tim_brk input. tim_brk_cmp2 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKCMP3E tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timers tim_brk input. tim_brk_cmp3 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 3 1 read-write BKCMP4E tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timers tim_brk input. tim_brk_cmp4 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 4 1 read-write BKCMP5E tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timers tim_brk input. tim_brk_cmp5 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 5 1 read-write BKCMP6E tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timers tim_brk input. tim_brk_cmp6 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 6 1 read-write BKCMP7E tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timers tim_brk input. tim_brk_cmp7 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 7 1 read-write BKCMP8E tim_brk_cmp8 enable 8 1 read-write BKINP TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 13 1 read-write ETRSEL etr_in source selection These bits select the etr_in input source. ... Refer to Section 64.3.2: TIM1 pins and internal signals for product specific implementation. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 4 read-write AF2 AF2 TIM1 alternate function register 2 0x64 0x20 0x00000001 0xFFFFFFFF BK2INE TIMx_BKIN2 input enable This bit enables the TIMx_BKIN2 alternate function input for the timers tim_brk2 input. TIMx_BKIN2 input is ORed with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BK2CMP1E tim_brk2_cmp1 enable This bit enables the tim_brk2_cmp1 for the timers tim_brk2 input. tim_brk2_cmp1 output is ORed with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BK2CMP2E tim_brk2_cmp2 enable This bit enables the tim_brk2_cmp2 for the timers tim_brk2 input. tim_brk2_cmp2 output is ORed with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BK2CMP3E tim_brk2_cmp3 enable This bit enables the tim_brk2_cmp3 for the timers tim_brk2 input. tim_brk2_cmp3 output is ORed with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 3 1 read-write BK2CMP4E tim_brk2_cmp4 enable This bit enables the tim_brk2_cmp4 for the timers tim_brk2 input. tim_brk2_cmp4 output is ORed with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 4 1 read-write BK2CMP5E tim_brk2_cmp5 enable This bit enables the tim_brk2_cmp5 for the timers tim_brk2 input. tim_brk2_cmp5 output is ORed with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 5 1 read-write BK2CMP6E tim_brk2_cmp6 enable This bit enables the tim_brk2_cmp6 for the timers tim_brk2 input. tim_brk2_cmp6 output is ORed with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 6 1 read-write BK2CMP7E tim_brk2_cmp7 enable This bit enables the tim_brk2_cmp7 for the timers tim_brk2 input. tim_brk2_cmp7 output is ORed with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 7 1 read-write BK2CMP8E tim_brk2_cmp8 enable This bit enables the tim_brk2_cmp8 for the timers tim_brk2 input. tim_brk2_cmp8 output is ORed with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BK2INP TIMx_BKIN2 input polarity This bit selects the TIMx_BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BK2CMP1P tim_brk2_cmp1 input polarity This bit selects the tim_brk2_cmp1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BK2CMP2P tim_brk2_cmp2 input polarity This bit selects the tim_brk2_cmp2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write BK2CMP3P tim_brk2_cmp3 input polarity This bit selects the tim_brk2_cmp3 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 12 1 read-write BK2CMP4P tim_brk2_cmp4 input polarity This bit selects the tim_brk2_cmp4 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 13 1 read-write OCRSEL ocref_clr source selection These bits select the ocref_clr input source. ... Refer to Section 64.3.2: TIM1 pins and internal signals for product specific information. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 3 read-write DCR DCR TIM1 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data are copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data are transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data are also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write 0 18 DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Others: reserved 16 4 read-write DMAR DMAR TIM1 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write TIM2 General-purpose timers TIM 0x40000000 0x0 0x3E4 registers TIM2 TIM2 global interrupt 51 CR1 CR1 TIM2 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and sampling clock used by the digital filters (tim_etr_in, tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering Enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM2 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS MMS[0]: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Others: Reserved Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write TI1S tim_ti1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS_3 MMS[3] 25 1 read-write SMCR SMCR TIM2 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write OCCS OCREF clear selection This bit is used to select the OCREF clear source Note: If the OCREF clear selection feature is not supported, this bit is reserved and forced by hardware to 0. Section 65.3: TIM2/TIM3/TIM4/TIM5 implementation. 3 1 read-write TS TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Section 65.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific implementation details. Note: These bits must be changed only when they are not used (for example when SMS = 000) to avoid wrong edge detections at the transition. 4 3 read-write MSM Master/Slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of tim_ker_ck frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be connected to tim_etrf in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write SMSPE SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded 24 1 read-write SMSPS SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active 25 1 read-write DIER DIER TIM2 DMA/Interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write DIRIE Direction change interrupt enable 21 1 read-write IERRIE Index error interrupt enable 22 1 read-write TERRIE Transition error interrupt enable 23 1 read-write SR SR TIM2 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 IDXF Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by software by writing it to 0. 20 1 read-write DIRF Direction change interrupt flag This flag is set by hardware when the direction changes in encoder mode (DIR bit value in TIMx_CR is changing). It is cleared by software by writing it to 0. 21 1 read-write IERRF Index error interrupt flag This flag is set by hardware when an index error is detected. It is cleared by software by writing it to 0. 22 1 read-write TERRF Transition error interrupt flag This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to 0. 23 1 read-write EGR EGR TIM2 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM2 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM2 capture/compare mode register 1 CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM2 capture/compare mode register 2 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM2 capture/compare mode register 2 CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM2 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM2 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register holds the non-dithered part in CNT[30:0]. The fractional part is not available. 0 32 read-write 0 4294967295 UIFCPY Value depends on IUFREMAP in TIMx_CR1. If UIFREMAP = 0 CNT[31]: Most significant bit of counter value If UIFREMAP = 1 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register 31 1 read-write UIFCPYR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM2 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency tim_cnt_ck is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). 0 16 read-write 0 65535 ARR ARR TIM2 auto-reload register 0x2C 0x20 0xFFFFFFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 65.4.3: Time-base unit on page 3820 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[31:4]. The ARR[3:0] bitfield contains the dithered part. 0 32 read-write 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 32 read-write 0 4294967295 ECR ECR TIM2 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable This bit indicates if the Index event resets the counter. 0 1 read-write IDIR Index direction This bit indicates in which direction the Index event resets the counter. Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled). 1 2 read-write IBLK Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input 3 2 read-write FIDX First index This bit indicates if the first index only is taken into account 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG 16 8 read-write PWPRSC Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following: tPWG = (2(PWPRSC[2:0])) x ttim_ker_ck 24 3 read-write TISEL TISEL TIM2 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input ... Refer to Section 65.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific implementation. 0 4 read-write TI2SEL Selects tim_ti2[15:0] input ... Refer to Section 65.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific implementation. 8 4 read-write TI3SEL Selects tim_ti3[15:0] input ... Refer to Section 65.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific implementation. 16 4 read-write TI4SEL Selects tim_ti4[15:0] input ... Refer to Section 65.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific implementation. 24 4 read-write AF1 AF1 TIM2 alternate function register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection These bits select the etr_in input source. ... Refer to Section 65.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific implementation. 14 4 read-write AF2 AF2 TIM2 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection These bits select the ocref_clr input source. ... Refer to Section 65.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific implementation. 16 3 read-write DCR DCR TIM2 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data are copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data are transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data are also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write 0 18 DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Others: reserved 16 4 read-write DMAR DMAR TIM2 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write TIM3 General-purpose timers TIM 0x40000400 TIM3 TIM3 global interrupt 52 TIM4 General-purpose timers TIM 0x40000800 TIM4 TIM4 global interrupt 53 TIM5 General-purpose timers TIM 0x40000C00 TIM5 TIM5 global interrupt 54 TIM6 Basic timers TIM 0x40001000 0x0 0x30 registers TIM6 TIM6 global interrupt 55 CR1 CR1 TIM6 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM6 control register 2 0x4 0x10 0x00000000 0x0000FFFF MMS Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or he peripheral receiving the tim_trgo must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER TIM6 DMA/Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 SR SR TIM6 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. On counter overflow if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR TIM6 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT TIM6 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM6 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency ftim_cnt_ck is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register. 0 16 read-write 0 65535 ARR ARR TIM6 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded into the actual auto-reload register. Refer to Section 66.3.4: Time-base unit on page 3923 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reserved. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 TIM7 Basic timers TIM 0x40001400 TIM7 TIM7 global interrupt 56 TIM9 General-purpose timers TIM 0x42004C00 0x0 0x60 registers TIM9 TIM9 global interrupt 57 CR1 CR1 TIM9 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable CEN is cleared automatically in one-pulse mode, when an update event occurs. Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable update event (UEV) generation. Counter overflow Setting the UG bit Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and sampling clock used by the digital filters (tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM12 control register 2 0x4 0x10 0x00000000 0x0000FFFF MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: 4 3 read-write TI1S tim_ti1 selection 7 1 read-write SMCR SMCR TIM9 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode (including gated + reset mode) must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC,...) receiving the tim_trgo signals must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write TS TS[0]: Trigger selection This TS[4:0] bitfield selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 658: TIMx internal trigger connection for more details on the meaning of tim_itrx for each timer. Note: These bits must be changed only when they are not used (for example when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write MSM Master/Slave mode 7 1 read-write SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write DIER DIER TIM9 Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 SR SR TIM9 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer toSection 67.7.3: TIMx slave mode control register (TIMx_SMCR)(x = 9, 12) ), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM9 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM9 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM9 capture/compare mode register 1 CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCER CCER TIM9 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM9 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register. 31 1 read-write UIFCPYR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM9 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency tim_cnt_ck is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). 0 16 read-write 0 65535 ARR ARR TIM9 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 67.4.3: Time-base unit on page 3951 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 TISEL TISEL TIM9 timer input selection register 0x5C 0x10 0x00000000 0x0000FFFF TI1SEL selects tim_ti1_in[15:0] input ... Refer to Table 656: Interconnect to the tim_ti1 input multiplexer for interconnects list. 0 4 read-write TI2SEL selects tim_ti2_in[15:0] input ... Refer to Table 657: Interconnect to the tim_ti2 input multiplexer for interconnects list. 8 4 read-write TIM12 General-purpose timers TIM 0x40001800 TIM12 TIM12 global interrupt 113 TIM13 General-purpose timers TIM 0x40001C00 0x0 0x60 registers TIM13 TIM13 global interrupt 114 CR1 CR1 TIM13 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and sampling clock used by the digital filters (tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 DIER DIER TIM13 Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 SR SR TIM13 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM13 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 CCMR1_Input CCMR1_Input TIM13 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 1 0x0 1-1 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CCMR1_Output CCMR1_Output TIM13 capture/compare mode register 1 CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 OC1M_1 OC1M[3] 16 1 read-write CCER CCER TIM13 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM13 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register. 31 1 read-write UIFCPYR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM13 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency tim_cnt_ck is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). 0 16 read-write 0 65535 ARR ARR TIM13 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 67.4.3: Time-base unit on page 3951 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 1 0x4 1-1 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 TISEL TISEL TIM13 timer input selection register 0x5C 0x10 0x00000000 0x0000FFFF TI1SEL selects tim_ti1_in[15:0] input ... Refer to Table 656: Interconnect to the tim_ti1 input multiplexer for interconnects list. 0 4 read-write TIM14 General-purpose timers TIM 0x40002000 TIM14 TIM14 global interrupt 115 TIM15 General purpose timers TIM 0x42004000 0x0 0x3E4 registers TIM15 TIM15 global interrupt 116 CR1 CR1 TIM15 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bitfield indicates the division ratio between the timer clock (tim_ker_ck) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (tim_tix) 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM15 control register 2 0x4 0x10 0x00000000 0x0000FFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: 4 3 read-write TI1S tim_ti1 selection 7 1 read-write 2 0x2 1-2 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 SMCR SMCR TIM15 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Others: Reserved. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write TS TS[0]: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Others: Reserved See Section 68.4.2: TIM15/TIM16/TIM17 pins and internal signals for more details on tim_itrx meaning for each timer. Note: These bits must be changed only when they are not used (for example when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write MSM Master/slave mode 7 1 read-write SMS_3 SMS[3] 16 1 read-write TS2 TS[4:3] 20 2 read-write DIER DIER TIM15 DMA/interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 2 0x1 1-2 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 read-write COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR TIM15 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIM15_CR1 register. When CNT is reinitialized by software using the UG bit in TIM15_EGR register, if URS=0 and UDIS=0 in the TIM15_CR1 register. When CNT is reinitialized by a trigger event (refer to Section 68.7.3: TIM15 slave mode control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIM15_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits CCxE, CCxNE, OCxM have been updated). It is cleared by software. 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM15 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 5 1 read-write COMGW write Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 CCMR1_Input CCMR1_Input TIM15 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIM15_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIM15_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM15 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCER CCER TIM15 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM15 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit in the TIM15_ISR register. 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM15 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (ftim_cnt_ck) is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIM15_EGR register or through trigger controller when configured in reset mode). 0 16 read-write 0 65535 ARR ARR TIM15 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 68.4.3: Time-base unit on page 4032 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 RCR RCR TIM15 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable. It also defines the update interrupt generation rate, if this interrupt is enable. When the repetition down-counter reaches zero, an update event is generated and it restarts counting from REP value. As the reptition counter is reloaded with REP value only at the repetition update event UEV, any write to the TIM15_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode 0 8 read-write 0 255 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 BDTR BDTR TIM15 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 s to 31750 ns by 250 ns steps, 32 s to 63 s by 1 s steps, 64 s to 126 s by 2 s steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIM15_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See tim_ocx/tim_ocxn enable description for more details (Section 68.7.9: TIM15 capture/compare enable register (TIM15_CCER) on page 4085). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIM15_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See tim_ocx/tim_ocxn enable description for more details (Section 68.7.9: TIM15 capture/compare enable register (TIM15_CCER) on page 4085). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIM15_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 1; Break inputs (tim_brk and tim_sys_brk clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as the tim_brk input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See tim_ocx/tim_ocxn enable description for more details (Section 68.7.9: TIM15 capture/compare enable register (TIM15_CCER) on page 4085). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample the tim_brk input signal and the length of the digital filter applied to tim_brk. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 16 4 read-write BKDSRM Break disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write BKBID Break bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write DTR2 DTR2 TIM15 timer deadtime register 2 0x54 0x20 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs, on the falling edge. DTGF[7:5]=0xx => DTF=DTGF[7:0]x tdtg with tdtg=tDTS. DTGF[7:5]=10x => DTF=(64+DTGF[5:0])xtdtg with Tdtg=2xtDTS. DTGF[7:5]=110 => DTF=(32+DTGF[4:0])xtdtg with Tdtg=8xtDTS. DTGF[7:5]=111 => DTF=(32+DTGF[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 0 8 read-write DTAE Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 16 1 read-write DTPE Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 17 1 read-write TISEL TISEL TIM15 input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL selects tim_ti1_in[15:0] input ... Refer to Section 68.4.2: TIM15/TIM16/TIM17 pins and internal signals for interconnects list. 0 4 read-write TI2SEL selects tim_ti2_in[15:0] input ... Refer to Section 68.4.2: TIM15/TIM16/TIM17 pins and internal signals for interconnects list. 8 4 read-write AF1 AF1 TIM15 alternate function register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timers tim_brk input. TIMx_BKIN input is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 0 1 read-write BKCMP1E tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timers tim_brk input. tim_brk_cmp1 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 1 1 read-write BKCMP2E tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timers tim_brk input. tim_brk_cmp2 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 2 1 read-write BKCMP3E tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timers tim_brk input. tim_brk_cmp3 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 3 1 read-write BKCMP4E tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timers tim_brk input. tim_brk_cmp4 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 4 1 read-write BKCMP5E tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timers tim_brk input. tim_brk_cmp5 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 5 1 read-write BKCMP6E tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timers tim_brk input. tim_brk_cmp6 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 6 1 read-write BKCMP7E tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timers tim_brk input. COMP7 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 7 1 read-write BKCMP8E tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timers tim_brk input. mdf_brkx output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 8 1 read-write BKINP TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 13 1 read-write AF2 AF2 TIM15 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection These bits select the ocref_clr input source. Refer to Section 68.4.2: TIM15/TIM16/TIM17 pins and internal signals for product specific implementation. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register). 16 3 read-write DCR DCR TIM15 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIM15_DMAR address). DBA is defined as an offset starting from the address of the TIM15_CR1 register. Example: ... 0 5 read-write DBL DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIM15_DMAR address). ... 8 5 read-write DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Other: reserved 16 4 read-write DMAR DMAR TIM15 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIM15_CR1 address) + (DBA + DMA index) x 4 where TIM15_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIM15_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIM15_DCR). 0 32 read-write TIM16 General purpose timers TIM 0x42004400 0x0 0x3E4 registers TIM16 TIM16 global interrupt 117 CR1 CR1 TIM16 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM16 control register 2 0x4 0x10 0x00000000 0x0000FFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 DIER DIER TIM16 DMA/interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 SR SR TIM16 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits CCxE, CCxNE, OCxM have been updated). It is cleared by software. 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the tim_brk input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM16 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 CCMR1_Input CCMR1_Input TIM16 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 1 0x0 1-1 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CCMR1_Output CCMR1_Output TIM16 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 OC1M_1 OC1M[3] 16 1 read-write OC2M_1 OC2M[3] 24 1 read-write CCER CCER TIM16 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM16 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved. 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM16 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (tim_cnt_ck) is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). 0 16 read-write 0 65535 ARR ARR TIM16 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 68.4.3: Time-base unit on page 4032 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 RCR RCR TIM16 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable. It also defines the update interrupt generation rate, if this interrupt is enable. When the repetition down-counter reaches zero, an update event is generated and it restarts counting from REP value. As the repetition counter is reloaded with REP value only at the repetition update event UEV, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode 0 8 read-write 0 255 1 0x4 1-1 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 BDTR BDTR TIM16 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 s to 31750 ns by 250 ns steps, 32 s to 63 s by 1 s steps, 64 s to 126 s by 2 s steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See tim_oc1/tim_oc1n enable description for more details (Section 68.8.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 4111). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See tim_oc1/tim_oc1n enable description for more details (Section 68.8.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 4111). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 1; Break inputs (tim_brk and tim_sys_brk event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as the tim_brk input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See tim_oc1/tim_oc1n enable description for more details (Section 68.8.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 4111). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample tim_brk input and the length of the digital filter applied to tim_brk. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write BKDSRM Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write BKBID Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write DTR2 DTR2 TIM16 timer deadtime register 2 0x54 0x20 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs, on the falling edge. DTGF[7:5]=0xx => DTF=DTGF[7:0]x tdtg with tdtg=tDTS. DTGF[7:5]=10x => DTF=(64+DTGF[5:0])xtdtg with Tdtg=2xtDTS. DTGF[7:5]=110 => DTF=(32+DTGF[4:0])xtdtg with Tdtg=8xtDTS. DTGF[7:5]=111 => DTF=(32+DTGF[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write DTAE Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 16 1 read-write DTPE Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 17 1 read-write TISEL TISEL TIM16 input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL selects tim_ti1_in[15:0] input ... Refer to Section 68.4.2: TIM15/TIM16/TIM17 pins and internal signals for interconnects list. 0 4 read-write AF1 AF1 TIM16 alternate function register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timers tim_brk input. TIMx_BKIN input is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKCMP1E tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timers tim_brk input. tim_brk_cmp1 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP2E tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timers tim_brk input. tim_brk_cmp2 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKCMP3E tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timers tim_brk input. tim_brk_cmp3 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 3 1 read-write BKCMP4E tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timers tim_brk input. tim_brk_cmp4 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 4 1 read-write BKCMP5E tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timers tim_brk input. tim_brk_cmp5 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 5 1 read-write BKCMP6E tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timers tim_brk input. tim_brk_cmp6 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 6 1 read-write BKCMP7E tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timers tim_brk input. tim_brk_cmp7 output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 7 1 read-write BKCMP8E tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timers tim_brk input. mdf_brkx output is ORed with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BKINP TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 13 1 read-write AF2 AF2 TIM16 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL tim_ocref_clr source selection These bits select the tim_ocref_clr input source. Refer to Section 68.4.2: TIM15/TIM16/TIM17 pins and internal signals for product specific implementation. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 3 read-write DCR DCR TIM16 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write DBL DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... 8 5 read-write DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Other: reserved 16 4 read-write DMAR DMAR TIM16/TIM17 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write TIM17 General purpose timers TIM 0x42004800 TIM17 TIM17 global interrupt 118 UCPD USB Type-C/USB Power Delivery interface UCPD 0x4000EC00 0x0 0x400 registers UCPD1 UCPD global interrupt 128 CFGR1 CFGR1 UCPD configuration register 1 0x0 0x20 0x00000000 0xFFFFFFFF HBITCLKDIV Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a ucpd_clk divider producing half-bit clock (hbit_clk). 0 6 read-write 0 63 IFRGAP Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a ucpd_clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal. 6 5 read-write 1 31 TRANSWIN Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the ucpd_clk frequency and the HBITCLKDIV[5:0] bitfield setting. 11 5 read-write 1 31 PSC_USBPDCLK Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a kernel clock pre-scaler producing UCPD peripheral clock (ucpd_clk). It is recommended to use the pre-scaler so as to set the ucpd_clk frequency in the range from 6 to 9 MHz. 17 3 read-write PSC_USBPDCLK Div1 Divide by 1 0 Div2 Divide by 2 1 Div4 Divide by 4 2 Div8 Divide by 8 3 Div16 Divide by 16 4 TXDMAEN Transmission DMA mode enable When set, the bit enables DMA mode for transmission. 29 1 read-write TXDMAEN Disabled DMA mode for transmission disabled 0 Enabled DMA mode for transmission enabled 1 RXDMAEN Reception DMA mode enable When set, the bit enables DMA mode for reception. 30 1 read-write RXDMAEN Disabled DMA mode for reception disabled 0 Enabled DMA mode for reception enabled 1 UCPDEN UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state. 31 1 read-write UCPDEN Disabled UCPD peripheral disabled 0 Enabled UCPD peripheral enabled 1 RXORDSETEN0 SOP detection 20 1 RXORDSETEN0 Disabled Flag disabled 0 Enabled Flag enabled 1 RXORDSETEN1 SOP' detection 21 1 RXORDSETEN2 SOP'' detection 22 1 RXORDSETEN3 Hard Reset detection 23 1 RXORDSETEN4 Cable Detect reset 24 1 RXORDSETEN5 SOP'_Debug 25 1 RXORDSETEN6 SOP'' Debug 26 1 RXORDSETEN7 SOP extension #1 27 1 RXORDSETEN8 SOP extension #2 28 1 CFGR2 CFGR2 UCPD configuration register 2 0x4 0x20 0x00000000 0xFFFFFFFF RXFILTDIS BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler). 0 1 read-write RXFILTDIS Enabled Rx pre-filter enabled 0 Disabled Rx pre-filter disabled 1 RXFILT2N3 BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value. 1 1 read-write RXFILT2N3 Samp3 3 samples 0 Samp2 2 samples 1 FORCECLK Force ClkReq clock request 2 1 read-write FORCECLK NoForce Do not force clock request 0 Force Force clock request 1 WUPEN Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal. 3 1 read-write WUPEN Disabled Disabled 0 Enabled Enabled 1 RXAFILTEN Rx analog filter enable Setting the bit enables the Rx analog filter required for optimum Power Delivery reception. 8 1 read-write CR CR UCPD control register 0xC 0x20 0x00000000 0xFFFFFFFF TXMODE Type of Tx packet 0 2 read-write TXMODE RegisterSet Transmission of Tx packet previously defined in other registers 0 CableReset Cable Reset sequence 1 BISTTest BIST test sequence (BIST Carrier Mode 2) 2 TXSEND Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded. 2 1 read-write TXSEND NoEffect No effect 0 Start Start Tx packet transmission 1 TXHRST Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded. 3 1 read-write TXHRST NoEffect No effect 0 Start Start Tx Hard Reset message 1 RXMODE Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message. As this mode prevents reception of the header (containing MessageID), software has to auto-increment a received MessageID counter for inclusion in the GoodCRC acknowledge that must still be transmitted during this test. 4 1 read-write RXMODE Normal Normal receive mode 0 BIST BIST receive mode (BIST test data mode) 1 PHYRXEN USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set. 5 1 read-write PHYRXEN Disabled USB Power Delivery receiver disabled 0 Enabled USB Power Delivery receiver enabled 1 PHYCCSEL CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach. 6 1 read-write PHYCCSEL CC1 Use CC1 IO for Power Delivery communication 0 CC2 Use CC2 IO for Power Delivery communication 1 ANASUBMODE Analog PHY sub-mode Refer to Table 876: Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield. 7 2 read-write ANASUBMODE Disabled Disabled 0 Rp_DefaultUSB Default USB Rp 1 Rp_1_5A 1.5A Rp 2 Rp_3A 3A Rp 3 ANAMODE Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to Table 876: Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0]. 9 1 read-write ANAMODE Source Source 0 Sink Sink 1 CCENABLE CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source. 10 2 read-write CCENABLE Disabled Both PHYs disabled 0 CC1Enabled CC1 PHY enabled 1 CC2Enabled CC2 PHY enabled 2 BothEnabled CC1 and CC2 PHYs enabled 3 FRSRXEN FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink. 16 1 read-write FRSRXEN Disabled FRS Rx event detection disabled 0 Enabled FRS Rx event detection enabled 1 FRSTX FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.1. 17 1 read-write FRSTX NoEffect No effect 0 Enabled FRS Tx signaling enabled 1 RDCH Rdch condition drive 18 1 read-write RDCH NoEffect No effect 0 ConditionDrive Rdch condition drive 1 CC1TCDIS CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0]. 20 1 read-write CC1TCDIS Enabled Type-C detector on the CCx line enabled 0 Disabled Type-C detector on the CCx line disabled 1 CC2TCDIS CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0]. 21 1 read-write IMR IMR UCPD interrupt mask register 0x10 0x20 0x00000000 0xFFFFFFFF TXISIE TXIS interrupt enable 0 1 read-write TXISIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TXMSGDISCIE TXMSGDISC interrupt enable 1 1 read-write TXMSGSENTIE TXMSGSENT interrupt enable 2 1 read-write TXMSGABTIE TXMSGABT interrupt enable 3 1 read-write HRSTDISCIE HRSTDISC interrupt enable 4 1 read-write HRSTSENTIE HRSTSENT interrupt enable 5 1 read-write TXUNDIE TXUND interrupt enable 6 1 read-write RXNEIE RXNE interrupt enable 8 1 read-write RXORDDETIE RXORDDET interrupt enable 9 1 read-write RXHRSTDETIE RXHRSTDET interrupt enable 10 1 read-write RXOVRIE RXOVR interrupt enable 11 1 read-write RXMSGENDIE RXMSGEND interrupt enable 12 1 read-write TYPECEVT1IE TYPECEVT1 interrupt enable 14 1 read-write TYPECEVT2IE TYPECEVT2 interrupt enable 15 1 read-write FRSEVTIE FRSEVT interrupt enable 20 1 read-only SR SR UCPD status register 0x14 0x20 0x00000000 0xFFFFFFFF TXIS Transmit interrupt status The flag indicates that the UCPD_TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the UCPD_TXDR register. 0 1 read-only TXIS NotRequired New Tx data write not required 0 Required New Tx data write required 1 TXMSGDISC Message transmission discarded The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit. Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle. 1 1 read-only TXMSGDISC NotDiscarded No Tx message discarded 0 Discarded Tx message discarded 1 TXMSGSENT Message transmission completed The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit. In the event of a message transmission interrupted by a Hard Reset, the flag is not raised. 2 1 read-only TXMSGSENT NotCompleted No Tx message completed 0 Completed Tx message completed 1 TXMSGABT Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit. 3 1 read-only TXMSGABT NoAbort No transmit message abort 0 Abort Transmit message abort 1 HRSTDISC Hard Reset discarded The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit. 4 1 read-only HRSTDISC NotDiscarded No Hard Reset discarded 0 Discarded Hard Reset discarded 1 HRSTSENT Hard Reset message sent The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit. 5 1 read-only HRSTSENT NotSent No Hard Reset message sent 0 Sent Hard Reset message sent 1 TXUND Tx data underrun detection The flag indicates that the Tx data register (UCPD_TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit. 6 1 read-only TXUND NoUnderrun No Tx data underrun detected 0 Underrun Tx data underrun detected 1 RXNE Receive data register not empty detection The flag indicates that the UCPD_RXDR register is not empty. It is automatically cleared upon reading UCPD_RXDR. 8 1 read-only RXNE Empty Rx data register empty 0 NotEmpty Rx data register not empty 1 RXORDDET Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the UCPD_RX_ORDSET register. It is cleared by setting the RXORDDETCF bit. 9 1 read-only RXORDDET NoOrderedSet No ordered set detected 0 OrderedSet Ordered set detected 1 RXHRSTDET Rx Hard Reset receipt detection The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit. 10 1 read-only RXHRSTDET NoHardReset Hard Reset not received 0 HardReset Hard Reset received 1 RXOVR Rx data overflow detection The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit. The buffer overflow can occur if the received data are not read fast enough. 11 1 read-only RXOVR NoOverflow No overflow 0 Overflow Overflow 1 RXMSGEND Rx message received The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit. The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message. 12 1 read-only RXMSGEND NoNewMessage No new Rx message received 0 NewMessage A new Rx message received 1 RXERR Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set. 13 1 read-only RXERR NoError No error detected 0 Error Error(s) detected 1 TYPECEVT1 Type-C voltage level event on CC1 line The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit. 14 1 read-only TYPECEVT1 NoNewEvent No new event 0 NewEvent A new Type-C event occurred 1 TYPECEVT2 Type-C voltage level event on CC2 line The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit. 15 1 read-only TYPEC_VSTATE_CC1 The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value. 16 2 read-only TYPEC_VSTATE_CC1 Lowest Lowest 0 Low Low 1 High High 2 Highest Highest 3 TYPEC_VSTATE_CC2 CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its steady state. The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value. 18 2 read-only FRSEVT FRS detection event The flag is cleared by setting the FRSEVTCF bit. 20 1 read-only FRSEVT NoNewEvent No new event 0 NewEvent New FRS receive event occurred 1 ICR ICR UCPD interrupt clear register 0x18 0x20 0x00000000 0xFFFFFFFF TXMSGDISCCF Tx message discard flag (TXMSGDISC) clear Setting the bit clears the TXMSGDISC flag in the UCPD_SR register. 1 1 write-only TXMSGDISCCFW Clear Clear flag in UCPD_SR 1 TXMSGSENTCF Tx message send flag (TXMSGSENT) clear Setting the bit clears the TXMSGSENT flag in the UCPD_SR register. 2 1 write-only TXMSGABTCF Tx message abort flag (TXMSGABT) clear Setting the bit clears the TXMSGABT flag in the UCPD_SR register. 3 1 write-only HRSTDISCCF Hard reset discard flag (HRSTDISC) clear Setting the bit clears the HRSTDISC flag in the UCPD_SR register. 4 1 write-only HRSTSENTCF Hard reset send flag (HRSTSENT) clear Setting the bit clears the HRSTSENT flag in the UCPD_SR register. 5 1 write-only TXUNDCF Tx underflow flag (TXUND) clear Setting the bit clears the TXUND flag in the UCPD_SR register. 6 1 write-only RXORDDETCF Rx ordered set detect flag (RXORDDET) clear Setting the bit clears the RXORDDET flag in the UCPD_SR register. 9 1 write-only RXHRSTDETCF Rx Hard Reset detect flag (RXHRSTDET) clear Setting the bit clears the RXHRSTDET flag in the UCPD_SR register. 10 1 write-only RXOVRCF Rx overflow flag (RXOVR) clear Setting the bit clears the RXOVR flag in the UCPD_SR register. 11 1 write-only RXMSGENDCF Rx message received flag (RXMSGEND) clear Setting the bit clears the RXMSGEND flag in the UCPD_SR register. 12 1 write-only TYPECEVT1CF Type-C CC1 event flag (TYPECEVT1) clear Setting the bit clears the TYPECEVT1 flag in the UCPD_SR register 14 1 write-only TYPECEVT2CF Type-C CC2 line event flag (TYPECEVT2) clear Setting the bit clears the TYPECEVT2 flag in the UCPD_SR register 15 1 write-only FRSEVTCF FRS event flag (FRSEVT) clear Setting the bit clears the FRSEVT flag in the UCPD_SR register. 20 1 write-only TX_ORDSETR TX_ORDSETR UCPD Tx ordered set type register 0x1C 0x20 0x00000000 0xFFFFFFFF TXORDSET Ordered set to transmit The bitfield determines a full 20-bit sequence to transmit, consisting of four K-codes, each of five bits, defining the packet to transmit. The bit 0 (bit 0 of K-code1) is the first, the bit 19 (bit 4 of code 4) the last. 0 20 read-write 0 1048575 TX_PAYSZR TX_PAYSZR UCPD Tx payload size register 0x20 0x20 0x00000000 0xFFFFFFFF TXPAYSZ Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the UCPD_TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission. 0 10 read-write 0 1023 TXDR TXDR UCPD Tx data register 0x24 0x20 0x00000000 0xFFFFFFFF TXDATA Data byte to transmit 0 8 read-write 0 255 RX_ORDSETR RX_ORDSETR UCPD Rx ordered set register 0x28 0x20 0x00000000 0xFFFFFFFF RXORDSET Rx ordered set code detected 0 3 read-only RXORDSET SOP SOP code detected in receiver 0 SOPPrime SOP' code detected in receiver 1 SOPDoublePrime SOP'' code detected in receiver 2 SOPPrimeDebug SOP'_Debug detected in receiver 3 SOPDoublePrimeDebug SOP''_Debug detected in receiver 4 CableReset Cable Reset detected in receiver 5 SOPExtension1 SOP extension #1 detected in receiver 6 SOPExtension2 SOP extension #2 detected in receiver 7 RXSOP3OF4 The bit indicates the number of correct codes. For debug purposes only. 3 1 read-only RXSOP3OF4 AllCorrect 4 correct K-codes out of 4 0 OneIncorrect 3 correct K-codes out of 4 1 RXSOPKINVALID The bitfield is for debug purposes only. Others: Invalid 4 3 read-only RXSOPKINVALID Valid No K-code corrupted 0 FirstCorrupted First K-code corrupted 1 SecondCorrupted Second K-code corrupted 2 ThirdCorrupted Third K-code corrupted 3 FourthCorrupted Fourth K-code corrupted 4 RX_PAYSZR RX_PAYSZR UCPD Rx payload size register 0x2C 0x20 0x00000000 0xFFFFFFFF RXPAYSZ Rx payload size received This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the UCPD_RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled). The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low). 0 10 read-only 0 1023 RXDR RXDR UCPD receive data register 0x30 0x20 0x00000000 0xFFFFFFFF RXDATA Data byte received 0 8 read-only 0 255 RX_ORDEXTR1 RX_ORDEXTR1 UCPD Rx ordered set extension register 1 0x34 0x20 0x00000000 0xFFFFFFFF RXSOPX1 Ordered set 1 received 0 20 read-write 0 1048575 RX_ORDEXTR2 RX_ORDEXTR2 UCPD Rx ordered set extension register 2 0x38 0x20 0x00000000 0xFFFFFFFF RXSOPX2 Ordered set 2 received 0 20 read-write 0 1048575 USART1 Universal synchronous/asynchronous receiver transmitter USART 0x42001000 0x0 0x400 registers USART1 USART1 global interrupt 82 CR1 CR1_ENABLED USART control register 1 0x0 0x20 0x00000000 0xFFFFFFFF UE USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. 1 1 read-write UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable This bit is set and cleared by software. 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable This bit is set and cleared by software. 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE=0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE=0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE=0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 OVER8 Oversampling mode This bit can only be written when the USART is disabled (UE=0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. 15 1 read-write OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 DEDT Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 16 5 read-write 0 31 DEAT Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 21 5 read-write 0 31 RTOIE Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 78.4: USART implementation on page 4549. 26 1 read-write RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 EOBIE End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 27 1 read-write EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). Note: FIFO mode can be used on standard UART communication, in SPI Master/Slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable This bit is set and cleared by software. 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO Full interrupt enable This bit is set and cleared by software. 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 USART control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SLVEN Synchronous Slave mode enable When the SLVEN bit is set, the Synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 0 1 read-write SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 DIS_NSS When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 3 1 read-write DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 ADDM7 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 LBDL LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 5 1 read-write LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 LBDIE LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 6 1 read-write LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBCL Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in Synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 8 1 read-write LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 CPHA Clock phase This bit is used to select the phase of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 917 and Figure 918) This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 9 1 read-write CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 CPOL Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 10 1 read-write CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CLKEN Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE=0). Note: If neither Synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1 11 1 read-write CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 STOP stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE=0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 LINEN LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 14 1 read-write LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 SWAP Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE=0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE=0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ABREN Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 20 1 read-write ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 ABRMOD Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 21 2 read-write ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 RTOEN Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 23 1 read-write RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ADD Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0). 24 8 read-write 0 255 CR3 CR3 USART control register 3 0x8 0x20 0x00000000 0xFFFFFFFF EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1or UDR = 1 in the USART_ISR register). 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 IREN IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 1 1 read-write IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 IRLP IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 2 1 read-write IRLP Normal Normal mode 0 LowPower Low-power mode 1 HDSEL Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE=0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 NACK Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 4 1 read-write NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 SCEN Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 5 1 read-write SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 DMAR DMA enable receiver This bit is set/reset by software 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter This bit is set/reset by software 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable This bit can only be written when the USART is disabled (UE=0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable This bit can only be written when the USART is disabled (UE=0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 ONEBIT One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE=0). 11 1 read-write ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 OVRDIS Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data are written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 78.4: USART implementation on page 4549. 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 SCARCNT Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In Transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In Reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE=0). When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 17 3 read-write 0 7 WUS Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 WUFIE Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 22 1 read-write WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 TXFTIE TXFIFO threshold interrupt enable This bit is set and cleared by software. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 TCBGTIE Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 24 1 read-write TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 RXFTCFG Receive FIFO threshold configuration Remaining combinations: Reserved 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration Remaining combinations: Reserved 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR USART baud rate register 0xC 0x20 0x00000000 0xFFFFFFFF BRR USART baud rate BRR[15:4] BRR[15:4] correspond to USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared. 0 16 read-write 0 65535 GTPR GTPR USART guard time and prescaler register 0x10 0x20 0x00000000 0xFFFFFFFF PSC Prescaler value 0 8 read-write 0 255 GT Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE=0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 8 8 read-write 0 255 RTOR RTOR USART receiver timeout register 0x14 0x20 0x00000000 0xFFFFFFFF RTO Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bit duration. In Standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character. 0 24 read-write 0 16777215 BLEN Block Length This bitfield gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0 -> 0 information characters + LEC BLEN = 1 -> 0 information characters + CRC BLEN = 255 -> 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. 24 8 read-write 0 255 RQR RQR USART request register 0x18 0x20 0x00000000 0xFFFFFFFF ABRRQ Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 0 1 write-only ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR_ENABLED USART interrupt and status register 0x1C 0x20 0x000000C0 0xF00FFFFF PE Parity error This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR. 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR3 register. Note: This error is associated with the character in the USART_RDR. 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 78.5.9: Tolerance of the USART receiver to clock deviation on page 4568). Note: This error is associated with the character in the USART_RDR. 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE=1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE=1 in the USART_CR1 register. 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXE/TXFE is set. When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. An interrupt is generated if TCIE=1 in the USART_CR1 register. TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE is set at the same time). Note: This bit is used during single buffer transmission. 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 LBDF LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 8 1 read-only LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 CTSIF CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 RTOF Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. 11 1 read-only RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 EOBF End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 12 1 read-only EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 UDR SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 13 1 read-only UDR NoUnderrun No underrun error 0 Underrun underrun error 1 ABRE Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 14 1 read-only ABRF Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 15 1 read-only BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 19 1 read-only RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 WUF Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE=1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 20 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 22 1 read-only TXFE TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO Full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TCBGT Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to Section 78.4: USART implementation on page 4549. 25 1 read-only TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFT RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR USART interrupt flag clear register 0x20 0x20 0x00000000 0xFFFFFFFF PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register. 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TXFECF TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register. 5 1 write-only oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 TCCF Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register. 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TCBGTCF Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. 7 1 write-only oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 LBDCF LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 8 1 write-only oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 CTSCF CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 RTOCF Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 11 1 write-only oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 EOBCF End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 12 1 write-only oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 UDRCF SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549 13 1 write-only oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 CMCF Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register. 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 WUCF Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4549. 20 1 write-only oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 RDR RDR USART receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RDR Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 911). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR USART transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TDR Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 911). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1. 0 9 read-write 0 511 PRESC PRESC USART prescaler register 0x2C 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. 0 4 read-write PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 USART2 0x40004400 USART2 USART2 global interrupt 83 USART3 0x40004800 USART3 USART3 global interrupt 84 UART4 0x40004C00 UART4 UART4 global interrupt 85 UART5 0x40005000 UART5 UART5 global interrupt 86 UART7 0x40007800 UART7 UART7 global interrupt 87 UART8 0x40007C00 UART8 UART8 global interrupt 88 VREFBUF Voltage reference buffer VREFBUF 0x58003C00 0x0 0x8 registers CSR CSR VREFBUF control and status register 0x0 0x20 0x00000002 0xFFFFFFFF ENVR Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. 0 1 read-write HIZ High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table 229: VREF buffer modes for the mode descriptions depending on ENVR bit configuration. 1 1 read-write VRR Voltage reference buffer ready 3 1 read-only VRS Voltage reference scale These bits select the value generated by the voltage reference buffer. VRS = 000: VREFBUF0 voltage selected. VRS = 001: VREFBUF1 voltage selected. VRS = 010: VREFBUF2 voltage selected. VRS = 011: VREFBUF3 voltage selected. Others: Reserved Refer to the product datasheet for each VREFBUFx voltage setting value. Note: The software can program this bitfield only when the VREFBUF is disabled (ENVR=0). 4 3 read-write CCR CCR VREFBUF calibration control register 0x4 0x20 0x00000000 0xFFFFFF00 TRIM Trimming code The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and updated according the mechanism described below. Reset: TRIM[5:0] is automatically initialized with the VRS = 0 trimming value stored in the flash memory during the production test. VRS change: TRIM[5:0] is automatically initialized with the trimming value (corresponding to VRS setting) stored in the flash memory during the production test. Write in TRIM[5:0]: User can modify the TRIM[5:0] with an arbitrary value. This is permanently disabling the control of the trimming value with VRS (until the device is reset). Note: If the user application performs the trimming, the trimming code must start from 000000 to 111111 in ascending order. 0 6 read-write WWDG WWDG WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 4 CR CR Control register 0x0 0x10 read-write 0x0000007F 0x0000FFFF T 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). 0 7 0 127 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset. 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 CFR CFR Configuration register 0x4 0x10 read-write 0x0000007F 0x0000FFFF W 7-bit window value These bits contain the window value to be compared to the downcounter. 0 7 0 127 EWI Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. 9 1 EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base The time base of the prescaler can be modified as follows: 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 Div16 Counter clock (PCLK1 div 4096) div 16 4 Div32 Counter clock (PCLK1 div 4096) div 32 5 Div64 Counter clock (PCLK1 div 4096) div 64 6 Div128 Counter clock (PCLK1 div 4096) div 128 7 SR SR Status register 0x8 0x10 read-write 0x00000000 0x0000FFFF EWIF Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled. 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 XSPI1 XSPI register block XSPI 0x52005000 0x0 0x22C registers OSPI1 OSPI1 / HSPI1 global interrupt 105 OSPI2 OSPI2 global interrupt 106 CR CR XSPI control register 0x0 0x20 0x00000000 0xFFFFFFFF EN Enable This bit enables the XSPI. The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. Note: In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active. 0 1 read-write ABORT Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0. 1 1 read-write DMAEN DMA enable In indirect mode, the DMA can be used to input or output data via XSPI_DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation. 2 1 read-write TCEN Timeout counter enable This bit is valid only when the memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter. Note: This bit can be modified only when BUSY = 0. 3 1 read-write DMM Dual-memory configuration This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity Note: This bit can be modified only when BUSY = 0. 6 1 read-write FTHRES FIFO threshold level This field defines, in indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in XSPI_SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[5:0] value. 8 6 read-write TEIE Transfer error interrupt enable This bit enables the transfer error interrupt. 16 1 read-write TCIE Transfer complete interrupt enable This bit enables the transfer complete interrupt. 17 1 read-write FTIE FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 18 1 read-write SMIE Status match interrupt enable This bit enables the status match interrupt. 19 1 read-write TOIE Timeout interrupt enable This bit enables the timeout interrupt. 20 1 read-write APMS Automatic status-polling mode stop This bit determines if the automatic status-polling is stopped after a match. Note: This bit can be modified only when BUSY = 0. 22 1 read-write PMM Polling match mode This bit indicates which method must be used to determine a match during the automatic status-polling mode. Note: This bit can be modified only when BUSY = 0. 23 1 read-write CSSEL chip select selection This bit indicates if the XSPI must activate NCS1 or NCS2. Note: This bit can be modified only when BUSY = 0. 24 1 read-write FMODE Functional mode This field defines the XSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state. Note: This bitfield can be modified only when BUSY = 0. 28 2 read-write MSEL Flash select 30 2 read-write DCR1 DCR1 XSPI device configuration register 1 0x8 0x20 0x00000000 0xFFFFFFFF CKMODE clock mode 0/mode 3 This bit indicates the level taken by the CLK between commands (when NCS = 1). 0 1 read-write FRCK Free running clock This bit configures the free running clock. 1 1 read-write CSHT Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must remain high between commands issued to the external device. ... 8 6 read-write DEVSIZE Device size This field defines the size of the external device using the following formula: Number of bytes in device = 2[DEVSIZE+1]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256 Mbytes. In regular-command protocol, if DMM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together. 16 5 read-write MTYP Memory type This bit indicates the type of memory to be supported. Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron. Others: Reserved 24 3 read-write DCR2 DCR2 XSPI device configuration register 2 0xC 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). ... For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high. Writing this field automatically starts a new calibration of high-speed interface DLL at the start of next transfer, except in case XSPI_CALOSR or XSPI_CALISR have been written in the meantime. BUSY stays high during the whole calibration execution. 0 8 read-write WRAPSIZE Wrap size This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in XSPI_WPIR. Others: reserved 16 3 read-write DCR3 DCR3 XSPI device configuration register 3 0x10 0x20 0x00000000 0xFFFFFFFF MAXTRAN Maximum transfer This field enables the communication regulation feature. The NCS is released every MAXTRAN+1 clock cycles when the other XSPI request the access to the bus. Others: maximum communication is set to MAXTRAN + 1 bytes. 0 8 read-write CSBOUND NCS boundary This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The NCS is released on each boundary of 2CSBOUND bytes. Others: NCS boundary set to 2CSBOUND bytes 16 5 read-write DCR4 DCR4 XSPI device configuration register 4 0x14 0x20 0x00000000 0xFFFFFFFF REFRESH Refresh rate This field enables the refresh rate feature. The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in single-, dual- or quad-SPI mode, because the byte transmission must be completed. Others: maximum communication length is set to REFRESH + 1 clock cycles. 0 32 read-write SR SR XSPI status register 0x20 0x20 0x00000000 0xFFFFFFFF TEF Transfer error flag This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF. 0 1 read-only TCF Transfer complete flag This bit is set in indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. 1 1 read-only FTF FIFO threshold flag In indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In automatic status-polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read. 2 1 read-only SMF Status match flag This bit is set in automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (XSPI_PSMAR). It is cleared by writing 1 to CSMF. 3 1 read-only TOF Timeout flag This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. 4 1 read-only BUSY Busy This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty. 5 1 read-only FLEVEL FIFO level This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 64 when it is full. In automatic-status polling mode, FLEVEL is zero. 8 7 read-only FCR FCR XSPI flag clear register 0x24 0x20 0x00000000 0xFFFFFFFF CTEF Clear transfer error flag Writing 1 clears the TEF flag in the XSPI_SR register. 0 1 write-only CTCF Clear transfer complete flag Writing 1 clears the TCF flag in the XSPI_SR register. 1 1 write-only CSMF Clear status match flag Writing 1 clears the SMF flag in the XSPI_SR register. 3 1 write-only CTOF Clear timeout flag Writing 1 clears the TOF flag in the XSPI_SR register. 4 1 write-only DLR DLR XSPI data length register 0x40 0x20 0x00000000 0xFFFFFFFF DL Data length 0 32 read-write AR AR XSPIaddress register 0x48 0x20 0x00000000 0xFFFFFFFF ADDRESS Address Address to be sent to the external device. In HyperBus protocol, this field must be even as this protocol is 16-bit word oriented. In dual-memory configuration, AR[0] is forced to 0. Writes to this field are ignored when BUSY = 1 or when FMODE = 11 (memory-mapped mode). Some memory specifications consider that each address corresponds to a 16-bit value. XSPI considers that each address corresponds to an 8-bit value. So the software needs to multiple the address by two when accessing the memory registers. 0 32 read-write DR DR XSPI data register 0x50 0x20 0x00000000 0xFFFFFFFF DATA Data Data to be sent/received to/from the external SPI device In indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In automatic status-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in indirect mode must be aligned to the bottom of this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0]. 0 32 read-write PSMKR PSMKR XSPI polling status mask register 0x80 0x20 0x00000000 0xFFFFFFFF MASK Status mask Mask to be applied to the status bytes received in automatic status-polling mode For bit n: 0 32 read-write PSMAR PSMAR XSPI polling status match register 0x88 0x20 0x00000000 0xFFFFFFFF MATCH Status match Value to be compared with the masked status register to get a match 0 32 read-write PIR PIR XSPI polling interval register 0x90 0x20 0x00000000 0xFFFFFFFF INTERVAL Polling interval Number of CLK cycle between a read during the automatic status-polling phases 0 16 read-write CCR CCR XSPI communication configuration register 0x100 0x20 0x00000000 0xFFFFFFFF IMODE Instruction mode This field defines the instruction phase mode of operation. Others: reserved 0 3 read-write IDTR Instruction double transfer rate This bit sets the DTR mode for the instruction phase. 3 1 read-write ISIZE Instruction size This bit defines instruction size. 4 2 read-write ADMODE Address mode This field defines the address phase mode of operation. Others: reserved 8 3 read-write ADDTR Address double transfer rate This bit sets the DTR mode for the address phase. 11 1 read-write ADSIZE Address size This field defines address size. 12 2 read-write ABMODE Alternate-byte mode This field defines the alternate byte phase mode of operation. Others: reserved 16 3 read-write ABDTR Alternate bytes double transfer rate This bit sets the DTR mode for the alternate bytes phase. Note: This field can be written only when BUSY = 0. 19 1 read-write ABSIZE Alternate bytes size This bit defines alternate bytes size. 20 2 read-write DMODE Data mode This field defines the data phase mode of operation. Others: reserved 24 3 read-write DDTR Data double transfer rate This bit sets the DTR mode for the data phase. 27 1 read-write DQSE DQS enable This bit enables the data strobe management. 29 1 read-write TCR TCR XSPI timing configuration register 0x108 0x20 0x00000000 0xFFFFFFFF DCYC Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). 0 5 read-write DHQC Delay hold quarter cycle 28 1 read-write SSHIFT Sample shift By default, the XSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.) 30 1 read-write IR IR XSPI instruction register 0x110 0x20 0x00000000 0xFFFFFFFF INSTRUCTION Instruction Instruction to be sent to the external SPI device 0 32 read-write ABR ABR XSPI alternate bytes register 0x120 0x20 0x00000000 0xFFFFFFFF ALTERNATE Alternate bytes Optional data to be sent to the external SPI device right after the address. 0 32 read-write LPTR LPTR XSPI low-power timeout register 0x130 0x20 0x00000000 0xFFFFFFFF TIMEOUT Timeout period After each access in memory-mapped mode, the XSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the XSPI waits after the clock becomes inactive and until it raises the NCS, putting the external device in a lower-consumption state. 0 16 read-write WPCCR WPCCR XSPI wrap communication configuration register 0x140 0x20 0x00000000 0xFFFFFFFF IMODE Instruction mode This field defines the instruction phase mode of operation. Others: reserved 0 3 read-write IDTR Instruction double transfer rate This bit sets the DTR mode for the instruction phase. 3 1 read-write ISIZE Instruction size This field defines instruction size. 4 2 read-write ADMODE Address mode This field defines the address phase mode of operation. Others: reserved 8 3 read-write ADDTR Address double transfer rate This bit sets the DTR mode for the address phase. 11 1 read-write ADSIZE Address size This field defines address size. 12 2 read-write ABMODE Alternate-byte mode This field defines the alternate byte phase mode of operation. 16 3 read-write ABDTR Alternate bytes double transfer rate This bit sets the DTR mode for the alternate bytes phase. 19 1 read-write ABSIZE Alternate bytes size This bit defines alternate bytes size. 20 2 read-write DMODE Data mode This field defines the data phase mode of operation. 101; data on 16 lines Others: reserved 24 3 read-write DDTR Data double transfer rate This bit sets the DTR mode for the data phase. 27 1 read-write DQSE DQS enable This bit enables the data strobe management. 29 1 read-write WPTCR WPTCR XSPI wrap timing configuration register 0x148 0x20 0x00000000 0xFFFFFFFF DCYC Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). 0 5 read-write DHQC Delay hold quarter cycle Add a quarter cycle delay on the outputs in DTR communication to match hold requirement. 28 1 read-write SSHIFT Sample shift By default, the XSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1). 30 1 read-write WPIR WPIR XSPI wrap instruction register 0x150 0x20 0x00000000 0xFFFFFFFF INSTRUCTION Instruction Instruction to be sent to the external SPI device 0 32 read-write WPABR WPABR XSPI wrap alternate byte register 0x160 0x20 0x00000000 0xFFFFFFFF ALTERNATE Alternate bytes Optional data to be sent to the external SPI device right after the address 0 32 read-write WCCR WCCR XSPI write communication configuration register 0x180 0x20 0x00000000 0xFFFFFFFF IMODE Instruction mode This field defines the instruction phase mode of operation. Others: reserved 0 3 read-write IDTR Instruction double transfer rate This bit sets the DTR mode for the instruction phase. 3 1 read-write ISIZE Instruction size This bit defines instruction size: 4 2 read-write ADMODE Address mode This field defines the address phase mode of operation. Others: reserved 8 3 read-write ADDTR Address double transfer rate This bit sets the DTR mode for the address phase. 11 1 read-write ADSIZE Address size This field defines address size. 12 2 read-write ABMODE Alternate-byte mode This field defines the alternate-byte phase mode of operation. Others: reserved 16 3 read-write ABDTR Alternate bytes double-transfer rate This bit sets the DTR mode for the alternate-bytes phase. 19 1 read-write ABSIZE Alternate bytes size This field defines alternate bytes size: 20 2 read-write DMODE Data mode This field defines the data phase mode of operation. 24 3 read-write DDTR data double transfer rate This bit sets the DTR mode for the data phase. 27 1 read-write DQSE DQS enable This bit enables the data strobe management. 29 1 read-write WTCR WTCR XSPI write timing configuration register 0x188 0x20 0x00000000 0xFFFFFFFF DCYC Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. 0 5 read-write WIR WIR XSPI write instruction register 0x190 0x20 0x00000000 0xFFFFFFFF INSTRUCTION Instruction Instruction to be sent to the external SPI device 0 32 read-write WABR WABR XSPI write alternate byte register 0x1A0 0x20 0x00000000 0xFFFFFFFF ALTERNATE Alternate bytes Optional data to be sent to the external SPI device right after the address 0 32 read-write HLCR HLCR XSPI HyperBus latency configuration register 0x200 0x20 0x00000000 0xFFFFFFFF LM Latency mode This bit selects the Latency mode. Note: This bit must be set when using the dual-octal HyperBus configuration. 0 1 read-write WZL Write zero latency This bit enables zero latency on write operations. 1 1 read-write TACC Access time Device access time expressed in number of communication clock cycles 8 8 read-write TRWR Read write recovery time Device read write recovery time expressed in number of communication clock cycles 16 8 read-write CALFCR CALFCR XSPI full-cycle calibration configuration 0x210 0x20 0x00000000 0xFFFFFFFF FINE Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet). 0 7 read-only COARSE Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet). 16 5 read-only CALMAX Max value This bit gets set when the memory-clock period is outside the range of DLL master, in which case XSPI_CALFCR and XSPI_CALSR are updated with the values for the maximum delay. 31 1 read-only CALMR CALMR XSPI DLL master calibration configuration 0x218 0x20 0x00000000 0xFFFFFFFF FINE Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet). 0 7 read-write COARSE Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet). 16 5 read-write CALSOR CALSOR XSPI DLL slave output calibration configuration 0x220 0x20 0x00000000 0xFFFFFFFF FINE Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet). 0 7 read-write COARSE Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet). 16 5 read-write CALSIR CALSIR XSPI DLL slave input calibration configuration 0x228 0x20 0x00000000 0xFFFFFFFF FINE Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet). 0 7 read-write COARSE Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet). 16 5 read-write XSPI2 0x5200A000 XSPIM1 XSPIM1 register block XSPI 0x5200B400 0x0 0x20 registers CR CR XSPIM control register 0x0 0x20 read-write 0x00000000 MUXEN Multiplexed mode enable This bit enables the multiplexing of the two XSPIs. 0 1 MODE XSPI multiplexing mode 1 1 CSSEL_OVR_EN Chip select selector override enable 4 1 CSSEL_OVR_O1 Chip select selector override setting for XSPI1 5 1 CSSEL_OVR_O2 Chip select selector override setting for XSPI2 6 1 REQ2ACK_TIME REQ to ACK time In Multiplexed mode (MUXEN = 1), this field defines the time between two transactions. 16 8 GPIOB General-purpose I/Os GPIO 0x58020400 0x0 0x30 registers MODER MODER GPIO port mode register 0x0 0x20 0xFFFFFEBF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x000000C0 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x00000100 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28

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