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Showing content from https://stm32-rs.github.io/stm32-rs/stm32h533.svd.patched below:

STM32H533 1.2 STM32H533 CM33 r0p0 little true true 4 false 8 32 0x20 0xFFFFFFFF ADC1 ADC register block ADC 0x42028000 0x0 0xCC registers ADC1 ADC1 global interrupt 37 ISR ISR ADC interrupt and status register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF ADRDY ADC ready 0 1 read-write oneToClear ADRDYR read NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 ADRDYW write Clear Clear ADC is ready to start conversion flag 1 EOSMP End of sampling flag 1 1 read-write oneToClear EOSMPR read NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOSMPW write Clear Clear end of sampling phase reached flag 1 EOC End of conversion flag 2 1 read-write oneToClear EOCR read NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOCW write Clear Clear regular conversion complete flag 1 EOS End of regular sequence flag 3 1 read-write oneToClear EOSR read NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 EOSW write Clear Clear regular sequence complete flag 1 OVR ADC overrun 4 1 read-write oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear overrun occurred flag 1 JEOC Injected channel end of conversion flag 5 1 read-write oneToClear JEOCR read NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOCW write Clear Clear injected conversion complete flag 1 JEOS Injected channel end of sequence flag 6 1 read-write oneToClear JEOSR read NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 JEOSW write Clear Clear Injected sequence complete flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 read-write oneToClear AWD1R read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD1W write Clear Clear analog watchdog event occurred flag 1 JQOVF Injected context queue overflow 10 1 read-write oneToClear JQOVFR read NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 JQOVFW write Clear Clear injected context queue overflow flag 1 IER IER ADC interrupt enable register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF ADRDYIE ADC ready interrupt enable 0 1 read-write ADRDYIE Disabled ADC ready interrupt disabled 0 Enabled ADC ready interrupt enabled 1 EOSMPIE End of sampling flag interrupt enable for regular conversions 1 1 read-write EOSMPIE Disabled End of regular conversion sampling phase interrupt disabled 0 Enabled End of regular conversion sampling phase interrupt enabled 1 EOCIE End of regular conversion interrupt enable 2 1 read-write EOCIE Disabled End of regular conversion interrupt disabled 0 Enabled End of regular conversion interrupt enabled 1 EOSIE End of regular sequence of conversions interrupt enable 3 1 read-write EOSIE Disabled End of regular sequence interrupt disabled 0 Enabled End of regular sequence interrupt enabled 1 OVRIE Overrun interrupt enable 4 1 read-write OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled 1 JEOCIE End of injected conversion interrupt enable 5 1 read-write JEOCIE Disabled End of injected conversion interrupt disabled 0 Enabled End of injected conversion interrupt enabled 1 JEOSIE End of injected sequence of conversions interrupt enable 6 1 read-write JEOSIE Disabled End of injected sequence interrupt disabled 0 Enabled End of injected sequence interrupt enabled 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 read-write AWD1IE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 JQOVFIE Injected context queue overflow interrupt enable 10 1 read-write JQOVFIE Disabled Injected context queue overflow interrupt disabled 0 Enabled Injected context queue overflow interrupt enabled 1 CR CR ADC control register 0x8 0x20 read-write 0x20000000 0xFFFFFFFF ADEN ADC enable control 0 1 read-write oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 ADDIS ADC disable command 1 1 read-write oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADSTART ADC start of regular conversion 2 1 read-write oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 JADSTART ADC start of injected conversion 3 1 read-write oneToSet read write ADSTP ADC stop of regular conversion command 4 1 read-write oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 JADSTP ADC stop of injected conversion command 5 1 read-write oneToSet read write ADVREGEN ADC voltage regulator enable 28 1 read-write ADVREGEN Disabled ADC Voltage regulator disabled 0 Enabled ADC Voltage regulator enabled 1 DEEPPWD Deep-power-down enable 29 1 read-write DEEPPWD NotDeepPowerDown ADC not in Deep-power down 0 DeepPowerDown ADC in Deep-power-down (default reset state) 1 ADCALDIF Differential mode for calibration 30 1 read-write ADCALDIF SingleEnded Calibration for single-ended mode 0 Differential Calibration for differential mode 1 ADCAL ADC calibration 31 1 read-write oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 CFGR CFGR ADC configuration register 0xC 0x20 read-write 0x80000000 0xFFFFFFFF DMAEN Direct memory access enable 0 1 read-write DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 DMACFG Direct memory access configuration 1 1 read-write DMACFG OneShot DMA One Shot mode selected 0 Circular DMA Circular mode selected 1 RES Data resolution 3 2 read-write RES Bits12 12-bit 0 Bits10 10-bit 1 Bits8 8-bit 2 Bits6 6-bit 3 EXTSEL External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 5 5 EXTSEL TIM1_CC1 Timer 1 CC1 event 0 TIM1_CC2 Timer 1 CC2 event 1 TIM1_CC3 Timer 1 CC3 event 2 TIM2_CC2 Timer 2 CC2 event 3 TIM3_TRGO Timer 3 TRGO event 4 EXTI11 EXTI line 11 6 TIM1_TRGO Timer 1 TRGO event 9 TIM1_TRGO2 Timer 1 TRGO2 event 10 TIM2_TRGO Timer 2 TRGO event 11 TIM6_TRGO Timer 6 TRGO event 13 TIM15_TRGO Timer 15 TRGO event 14 TIM3_CC4 Timer 3 CC4 event 15 EXTEN External trigger enable and polarity selection for regular channels 10 2 read-write EXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 OVRMOD Overrun mode 12 1 read-write OVRMOD Preserve Preserve DR register when an overrun is detected 0 Overwrite Overwrite DR register when an overrun is detected 1 CONT Single / continuous conversion mode for regular conversions 13 1 read-write CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 AUTDLY Delayed conversion mode 14 1 read-write AUTDLY Off Auto delayed conversion mode off 0 On Auto delayed conversion mode on 1 ALIGN Data alignment 15 1 read-write ALIGN Right Right alignment 0 Left Left alignment 1 DISCEN Discontinuous mode for regular channels 16 1 read-write DISCEN Disabled Discontinuous mode on regular channels disabled 0 Enabled Discontinuous mode on regular channels enabled 1 DISCNUM Discontinuous mode channel count 17 3 read-write 0 7 JDISCEN Discontinuous mode on injected channels 20 1 read-write JDISCEN Disabled Discontinuous mode on injected channels disabled 0 Enabled Discontinuous mode on injected channels enabled 1 JQM JSQR queue mode 21 1 read-write JQM Mode0 JSQR Mode 0: Queue maintains the last written configuration into JSQR 0 Mode1 JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence 1 AWD1SGL Enable the watchdog 1 on a single channel or on all channels 22 1 read-write AWD1SGL All Analog watchdog 1 enabled on all channels 0 Single Analog watchdog 1 enabled on single channel selected in AWD1CH 1 AWD1EN Analog watchdog 1 enable on regular channels 23 1 read-write AWD1EN Disabled Analog watchdog 1 disabled on regular channels 0 Enabled Analog watchdog 1 enabled on regular channels 1 JAWD1EN Analog watchdog 1 enable on injected channels 24 1 read-write JAWD1EN Disabled Analog watchdog 1 disabled on injected channels 0 Enabled Analog watchdog 1 enabled on injected channels 1 JAUTO Automatic injected group conversion 25 1 read-write JAUTO Disabled Automatic injected group conversion disabled 0 Enabled Automatic injected group conversion enabled 1 AWD1CH Analog watchdog 1 channel selection 26 5 read-write 0 19 JQDIS Injected queue disable 31 1 read-write CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 0xFFFFFFFF ROVSE Regular oversampling Enable 0 1 read-write ROVSE Disabled Regular Oversampling disabled 0 Enabled Regular Oversampling enabled 1 JOVSE Injected oversampling Enable 1 1 read-write JOVSE Disabled Injected Oversampling disabled 0 Enabled Injected Oversampling enabled 1 OVSR Oversampling ratio 2 3 read-write OVSR Ratio2 2x 0 Ratio4 4x 1 Ratio8 8x 2 Ratio16 16x 3 Ratio32 32x 4 Ratio64 64x 5 Ratio128 128x 6 Ratio256 256x 7 OVSS Oversampling shift 5 4 read-write OVSS NoShift No Shift 0 Shift1Bit Shift 1-bit 1 Shift2Bit Shift 2-bit 2 Shift3Bit Shift 3-bit 3 Shift4Bit Shift 4-bit 4 Shift5Bit Shift 5-bit 5 Shift6Bit Shift 6-bit 6 Shift7Bit Shift 7-bit 7 Shift8Bit Shift 8-bit 8 TROVS Triggered Regular oversampling 9 1 read-write TROVS All All oversampled conversions for a channel are done consecutively following a trigger 0 Single Each oversampled conversion for a channel needs a new trigger 1 ROVSM Regular oversampling mode 10 1 read-write ROVSM ContinuedMode When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 0 ResumedMode When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) 1 SWTRIG Software trigger bit for sampling time control trigger mode 25 1 read-write SWTRIG Conversion Software trigger starts the conversion for sampling time control trigger mode 0 Sampling Software trigger starts the sampling for sampling time control trigger mode 1 BULB Bulb sampling mode 26 1 read-write BULB Disabled Bulb sampling mode disabled 0 Enabled Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion 1 SMPTRIG Sampling time control trigger mode 27 1 read-write SMPTRIG Disabled Sampling time control trigger mode disabled 0 Enabled Sampling time control trigger mode enabled 1 SMPR1 SMPR1 ADC sample time register 1 0x14 0x20 read-write 0x00000000 0xFFFFFFFF 10 0x3 0-9 SMP%s Channel %s sample time selection 0 3 read-write SMP0 Cycles2_5 2.5 ADC clock cycles 0 Cycles6_5 6.5 ADC clock cycles 1 Cycles12_5 12.5 ADC clock cycles 2 Cycles24_5 24.5 ADC clock cycles 3 Cycles47_5 47.5 ADC clock cycles 4 Cycles92_5 92.5 ADC clock cycles 5 Cycles247_5 247.5 ADC clock cycles 6 Cycles640_5 640.5 ADC clock cycles 7 SMPPLUS Addition of one clock cycle to the sampling time. 31 1 read-write SMPPLUS KeepCycles The sampling time remains set to 2.5 ADC clock cycles remains 0 Add1Cycle 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers 1 SMPR2 SMPR2 ADC sample time register 2 0x18 0x20 read-write 0x00000000 0xFFFFFFFF 10 0x3 10-19 SMP%s Channel %s sample time selection 0 3 read-write TR1 TR1 ADC watchdog threshold register 1 0x20 0x20 read-write 0x0FFF0000 0xFFFFFFFF LT1 Analog watchdog 1 lower threshold 0 12 read-write 0 4095 AWDFILT Analog watchdog filtering parameter 12 3 read-write HT1 Analog watchdog 1 higher threshold 16 12 read-write 0 4095 TR2 TR2 ADC watchdog threshold register 2 0x24 0x20 read-write 0x00FF0000 0xFFFFFFFF LT2 Analog watchdog 2 lower threshold 0 8 read-write 0 255 HT2 Analog watchdog 2 higher threshold 16 8 read-write 0 255 TR3 TR3 ADC watchdog threshold register 3 0x28 0x20 read-write 0x00FF0000 0xFFFFFFFF LT3 Analog watchdog 3 lower threshold 0 8 read-write 0 255 HT3 Analog watchdog 3 higher threshold 16 8 read-write 0 255 SQR1 SQR1 ADC regular sequence register 1 0x30 0x20 read-write 0x00000000 0xFFFFFFFF L Regular channel sequence length 0 4 read-write 0 15 4 0x6 1-4 SQ%s %s conversion in regular sequence 6 5 read-write 0 19 SQR2 SQR2 ADC regular sequence register 2 0x34 0x20 read-write 0x00000000 0xFFFFFFFF 5 0x6 5-9 SQ%s %s conversion in regular sequence 0 5 read-write SQR3 SQR3 ADC regular sequence register 3 0x38 0x20 read-write 0x00000000 0xFFFFFFFF 5 0x6 10-14 SQ%s %s conversion in regular sequence 0 5 read-write SQR4 SQR4 ADC regular sequence register 4 0x3C 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x6 15-16 SQ%s %s conversion in regular sequence 0 5 read-write DR DR ADC regular data register 0x40 0x20 read-only 0x00000000 0xFFFFFFFF RDATA Regular data converted 0 16 read-only 0 65535 JSQR JSQR ADC injected sequence register 0x4C 0x20 read-write 0x00000000 0xFFFFFFFF JL Injected channel sequence length 0 2 read-write 0 3 JEXTSEL External Trigger Selection for injected group 2 5 read-write JEXTSEL TIM1_TRGO Timer 1 TRGO event 0 TIM1_CC4 Timer 1 CC4 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM2_CC1 Timer 2 CC1 event 3 TIM3_CC4 Timer 3 CC4 event 4 EXTI15 EXTI line 15 6 TIM1_TRGO2 Timer 1 TRGO2 event 8 TIM3_CC3 Timer 3 CC3 event 11 TIM3_TRGO Timer 3 TRGO event 12 TIM3_CC1 Timer 3 CC1 event 13 TIM6_TRGO Timer 6 TRGO event 14 TIM15_TRGO Timer 15 TRGO event 15 JEXTEN External trigger enable and polarity selection for injected channels 7 2 read-write JEXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 4 0x6 1-4 JSQ%s %s conversion in injected sequence 9 5 read-write 0 19 4 0x4 1-4 OFR%s OFR%s ADC offset %s register 0x60 0x20 read-write 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into bits OFFSET_CH[4:0] 0 12 read-write 0 4095 OFFSETPOS Positive offset 24 1 read-write SATEN Saturation enable 25 1 read-write OFFSET_CH Channel selection for the data offset y 26 5 read-write 0 31 OFFSET_EN Offset y enable 31 1 read-write OFFSET_EN Disabled This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0] 0 Enabled This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0] 1 4 0x4 1-4 JDR%s JDR%s ADC injected channel %s data register 0x80 0x20 read-only 0x00000000 0xFFFFFFFF JDATA Injected data 0 16 read-only 0 65535 AWD2CR AWD2CR ADC analog watchdog 2 configuration register 0xA0 0x20 read-write 0x00000000 0xFFFFFFFF 20 0x1 0-19 AWD2CH%s Analog watchdog 2 channel selection 0 1 AWD2CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 AWD3CR AWD3CR ADC analog watchdog 3 configuration register 0xA4 0x20 read-write 0x00000000 0xFFFFFFFF 20 0x1 0-19 AWD3CH%s Analog watchdog 3 channel selection 0 1 AWD3CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 DIFSEL DIFSEL ADC Differential mode selection register 0xB0 0x20 read-write 0x00000000 0xFFFFFFFF 20 0x1 0-19 DIFSEL%s Differential mode for channel %s 0 1 DIFSEL0 SingleEnded Input channel is configured in single-ended mode 0 Differential Input channel is configured in differential mode 1 CALFACT CALFACT ADC calibration factors 0xB4 0x20 read-write 0x00000000 0xFFFFFFFF CALFACT_S Calibration Factors In single-ended mode 0 7 read-write 0 127 CALFACT_D Calibration Factors in differential mode 16 7 read-write 0 127 OR OR ADC option register 0xC8 0x20 read-write 0x00000000 0xFFFFFFFF OP0 Option bit 0 0 1 read-write ADC1_S 0x52028000 ADC2 0x42028100 ADC2 ADC2 global interrupt 69 ADC2_S 0x52028100 ADCC ADC common registers block ADC 0x42028300 0x0 0x100 registers CSR CSR ADC common status register 0x0 0x20 read-only 0x00000000 0xFFFFFFFF ADRDY_MST Master ADC ready 0 1 read-only EOSMP_MST End of Sampling phase flag of the master ADC 1 1 read-only EOC_MST End of regular conversion of the master ADC 2 1 read-only EOS_MST End of regular sequence flag of the master ADC 3 1 read-only OVR_MST Overrun flag of the master ADC 4 1 read-only JEOC_MST End of injected conversion flag of the master ADC 5 1 read-only JEOS_MST End of injected sequence flag of the master ADC 6 1 read-only AWD1_MST Analog watchdog 1 flag of the master ADC 7 1 read-only AWD2_MST Analog watchdog 2 flag of the master ADC 8 1 read-only AWD3_MST Analog watchdog 3 flag of the master ADC 9 1 read-only JQOVF_MST Injected Context Queue Overflow flag of the master ADC 10 1 read-only ADRDY_SLV Slave ADC ready 16 1 read-only EOSMP_SLV End of Sampling phase flag of the slave ADC 17 1 read-only EOC_SLV End of regular conversion of the slave ADC 18 1 read-only EOS_SLV End of regular sequence flag of the slave ADC. 19 1 read-only OVR_SLV Overrun flag of the slave ADC 20 1 read-only JEOC_SLV End of injected conversion flag of the slave ADC 21 1 read-only JEOS_SLV End of injected sequence flag of the slave ADC 22 1 read-only AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 read-only AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 read-only AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 read-only JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC 26 1 read-only CCR CCR ADC common control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF DUAL Dual ADC mode selection 0 5 read-write DELAY Delay between 2 sampling phases 8 4 read-write DMACFG DMA configuration (for dual ADC mode) 13 1 read-write MDMA Direct memory access mode for dual ADC mode 14 2 read-write CKMODE ADC clock mode 16 2 read-write PRESC ADC prescaler 18 4 read-write VREFEN Vless thansub>REFINTless than/sub> enable 22 1 read-write TSEN Vless thansub>SENSEless than/sub> enable 23 1 read-write VBATEN VBAT enable 24 1 read-write CDR CDR ADC common regular data register for dual mode 0xC 0x20 read-only 0x00000000 0xFFFFFFFF RDATA_MST Regular data of the master ADC. 0 16 read-only RDATA_SLV Regular data of the slave ADC 16 16 read-only HWCFGR0 HWCFGR0 ADC hardware configuration register 0xF0 0x20 read-only 0x00001212 0xFFFFFFFF ADCNUM Number of ADCs implemented 0 4 read-only MULPIPE Number of pipeline stages 4 4 read-only OPBITS Number of option bits 8 4 read-only IDLEVALUE Idle value for non-selected channels 12 4 read-only VERR VERR ADC version register 0xF4 0x20 read-only 0x00000012 0xFFFFFFFF MINREV Minor revision 0 4 read-only MAJREV Major revision 4 4 read-only IPDR IPDR ADC identification register 0xF8 0x20 read-only 0x00110006 0xFFFFFFFF ID Peripheral identifier 0 32 read-only SIDR SIDR ADC size identification register 0xFC 0x20 read-only 0xA3C5DD01 0xFFFFFFFF SID Size Identification 0 32 read-only SEC_ADCC 0x52028300 AES AES register block AES 0x420C0000 0x0 0x400 registers AES AES global interrupt 116 CR CR AES control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF EN Enable 0 1 read-write DATATYPE Data type 1 2 read-write MODE Operating mode 3 2 read-write CHMOD CHMOD[1:0]: Chaining mode 5 2 read-write DMAINEN DMA input enable 11 1 read-write DMAOUTEN DMA output enable 12 1 read-write GCMPH GCM or CCM phase selection 13 2 read-write CHMOD_1 CHMOD[2] 16 1 read-write KEYSIZE Key size selection 18 1 read-write NPBLB Number of padding bytes in last block 20 4 read-write KMOD Key mode selection 24 2 read-write IPRST AES peripheral software reset 31 1 read-write SR SR AES status register 0x4 0x20 read-only 0x00000000 0xFFFFFFFF RDERRF Read error flag 1 1 read-only WRERRF Write error flag 2 1 read-only BUSY Busy 3 1 read-only KEYVALID Key valid flag 7 1 read-only DINR DINR AES data input register 0x8 0x20 write-only 0x00000000 0xFFFFFFFF DIN Data input 0 32 write-only DOUTR DOUTR AES data output register 0xC 0x20 read-only 0x00000000 0xFFFFFFFF DOUT Data output 0 32 read-only KEYR0 KEYR0 AES key register 0 0x10 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [31:0] 0 32 write-only KEYR1 KEYR1 AES key register 1 0x14 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [63:32] 0 32 write-only KEYR2 KEYR2 AES key register 2 0x18 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [95:64] 0 32 write-only KEYR3 KEYR3 AES key register 3 0x1C 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [127:96] 0 32 write-only IVR0 IVR0 AES initialization vector register 0 0x20 0x20 read-write 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [31:0] 0 32 read-write IVR1 IVR1 AES initialization vector register 1 0x24 0x20 read-write 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [63:32] 0 32 read-write IVR2 IVR2 AES initialization vector register 2 0x28 0x20 read-write 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [95:64] 0 32 read-write IVR3 IVR3 AES initialization vector register 3 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [127:96] 0 32 read-write KEYR4 KEYR4 AES key register 4 0x30 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [159:128] 0 32 write-only KEYR5 KEYR5 AES key register 5 0x34 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [191:160] 0 32 write-only KEYR6 KEYR6 AES key register 6 0x38 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [223:192] 0 32 write-only KEYR7 KEYR7 AES key register 7 0x3C 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [255:224] 0 32 write-only SUSPR0 SUSPR0 AES suspend registers 0x40 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR1 SUSPR1 AES suspend registers 0x44 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR2 SUSPR2 AES suspend registers 0x48 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR3 SUSPR3 AES suspend registers 0x4C 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR4 SUSPR4 AES suspend registers 0x50 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR5 SUSPR5 AES suspend registers 0x54 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR6 SUSPR6 AES suspend registers 0x58 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR7 SUSPR7 AES suspend registers 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write IER IER AES interrupt enable register 0x300 0x20 read-write 0x00000000 0xFFFFFFFF CCFIE Computation complete flag interrupt enable 0 1 read-write RWEIE Read or write error interrupt enable 1 1 read-write KEIE Key error interrupt enable 2 1 read-write ISR ISR AES interrupt status register 0x304 0x20 read-only 0x00000000 0xFFFFFFFF CCF Computation complete flag 0 1 read-only RWEIF Read or write error interrupt flag 1 1 read-only KEIF Key error interrupt flag 2 1 read-only ICR ICR AES interrupt clear register 0x308 0x20 write-only 0x00000000 0xFFFFFFFF CCF Computation complete flag clear 0 1 write-only RWEIF Read or write error interrupt flag clear 1 1 write-only KEIF Key error interrupt flag clear 2 1 write-only AES_S 0x520C0000 CRC CRC address block description CRC 0x40023000 0x0 0x18 registers DR DR CRC data register 0x0 0x20 read-write 0xFFFFFFFF 0xFFFFFFFF DR Data register bits 0 32 read-write 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR CRC independent data register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF IDR General-purpose 32-bit data register bits 0 32 read-write 0 4294967295 CR CR CRC control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF RESET RESET bit 0 1 read-write RESETW write Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 POLYSIZE Polynomial size 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 REV_IN Reverse input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 REV_OUT Reverse output data 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 INIT INIT CRC initial value 0x10 0x20 read-write 0xFFFFFFFF 0xFFFFFFFF INIT Programmable initial CRC value 0 32 read-write 0 4294967295 POL POL CRC polynomial 0x14 0x20 read-write 0x04C11DB7 0xFFFFFFFF POL Programmable polynomial 0 32 read-write 0 4294967295 CRC_S 0x50023000 CRS CRS address block description CRS 0x40006000 0x0 0x10 registers CRS Clock Recovery System global interrupt 75 CR CR CRS control register 0x0 0x20 read-write 0x00004000 0xFFFFFFFF SYNCOKIE SYNC event OK interrupt enable 0 1 read-write SYNCOKIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 SYNCWARNIE SYNC warning interrupt enable 1 1 read-write ERRIE Synchronization or trimming error interrupt enable 2 1 read-write ESYNCIE Expected SYNC interrupt enable 3 1 read-write CEN Frequency error counter enable 5 1 read-write CEN Disabled Frequency error counter disabled 0 Enabled Frequency error counter enabled 1 AUTOTRIMEN Automatic trimming enable 6 1 read-write AUTOTRIMEN Disabled Automatic trimming disabled 0 Enabled Automatic trimming enabled 1 SWSYNC Generate software SYNC event 7 1 read-write SWSYNC Sync A software sync is generated 1 TRIM HSI48 oscillator smooth trimming 8 6 read-write 0 63 CFGR CFGR CRS configuration register 0x4 0x20 read-write 0x2022BB7F 0xFFFFFFFF RELOAD Counter reload value 0 16 read-write 0 65535 FELIM Frequency error limit 16 8 read-write 0 255 SYNCDIV SYNC divider 24 3 read-write SYNCDIV Div1 SYNC not divided 0 Div2 SYNC divided by 2 1 Div4 SYNC divided by 4 2 Div8 SYNC divided by 8 3 Div16 SYNC divided by 16 4 Div32 SYNC divided by 32 5 Div64 SYNC divided by 64 6 Div128 SYNC divided by 128 7 SYNCSRC SYNC signal source selection 28 2 read-write SYNCSRC GPIO_AF GPIO AF (crs_sync_in_1) selected as SYNC signal source 0 LSE LSE (crs_sync_in_2) selected as SYNC signal source 1 USB_SOF USB SOF (crs_sync_in_3) selected as SYNC signal source 2 SYNCPOL SYNC polarity selection 31 1 read-write SYNCPOL RisingEdge SYNC active on rising edge 0 FallingEdge SYNC active on falling edge 1 ISR ISR CRS interrupt and status register 0x8 0x20 read-only 0x00000000 0xFFFFFFFF SYNCOKF SYNC event OK flag 0 1 read-only SYNCOKF NotSignaled Signal not set 0 Signaled Signal set 1 SYNCWARNF SYNC warning flag 1 1 read-only ERRF Error flag 2 1 read-only ESYNCF Expected SYNC flag 3 1 read-only SYNCERR SYNC error 8 1 read-only SYNCMISS SYNC missed 9 1 read-only TRIMOVF Trimming overflow or underflow 10 1 read-only FEDIR Frequency error direction 15 1 read-only FEDIR UpCounting Error in up-counting direction 0 DownCounting Error in down-counting direction 1 FECAP Frequency error capture 16 16 read-only 0 65535 ICR ICR CRS interrupt flag clear register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF SYNCOKC SYNC event OK clear flag 0 1 read-write SYNCOKC Clear Clear flag 1 SYNCWARNC SYNC warning clear flag 1 1 read-write ERRC Error clear flag 2 1 read-write ESYNCC Expected SYNC clear flag 3 1 read-write CRS_S 0x50006000 DAC DAC address block description DAC 0x42028400 0x0 0x50 registers DAC1 DAC1 global interrupt 38 CR CR DAC control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x10 1-2 EN%s DAC channel%s enable 0 1 read-write EN1 Disabled DAC Channel X disabled 0 Enabled DAC Channel X enabled 1 2 0x10 1-2 TEN%s DAC channel%s trigger enable 1 1 read-write TEN1 Disabled DAC Channel X trigger disabled 0 Enabled DAC Channel X trigger enabled 1 TSEL1 DAC channel1 trigger selection 2 4 read-write TSEL1 Swtrig Software trigger 0 Tim1Trgo Timer 1 TRGO event 1 Tim2Trgo Timer 2 TRGO event 2 Tim4Trgo Timer 4 TRGO event 3 Tim5Trgo Timer 5 TRGO event 4 Tim6Trgo Timer 6 TRGO event 5 Tim7Trgo Timer 7 TRGO event 6 Tim8Trgo Timer 8 TRGO event 7 Tim15Trgo Timer 15 TRGO event 8 Lptim1Ch1 LPTIM1 CH1 event 11 Lptim2Ch1 LPTIM2 CH1 event 12 Exti9 EXTI line 9 13 2 0x10 1-2 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 read-write WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true 2 0x10 1-2 MAMP%s DAC channel%s mask/amplitude selector 8 4 read-write MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 2 0x10 1-2 DMAEN%s DAC channel%s DMA enable 12 1 read-write DMAEN1 Disabled DAC Channel X DMA mode disabled 0 Enabled DAC Channel X DMA mode enabled 1 2 0x10 1-2 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 read-write DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 2 0x10 1-2 CEN%s DAC channel%s calibration enable 14 1 read-write CEN1 Normal DAC Channel X Normal operating mode 0 Calibration DAC Channel X calibration mode 1 TSEL2 DAC channel2 trigger selection 18 4 read-write SWTRGR SWTRGR DAC software trigger register 0x4 0x20 write-only 0x00000000 0xFFFFFFFF 2 0x1 1-2 SWTRIG%s DAC channel%s software trigger 0 1 write-only SWTRIG1 NoTrigger No trigger 0 Trigger Trigger 1 2 0xC 1-2 DHR12R%s DHR12R%s channel%s 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF DACCDHR DAC channel1 12-bit right-aligned data 0 12 read-write 0 4095 DACC1DHRB DAC channel1 12-bit right-aligned data B 16 12 read-write 0 4095 2 0xC 1-2 DHR12L%s DHR12L%s channel%s 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF DACCDHR DAC channel1 12-bit left-aligned data 4 12 read-write 0 4095 DACC1DHRB DAC channel1 12-bit left-aligned data B 20 12 read-write 0 4095 2 0xC 1-2 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF DACCDHR DAC channel1 8-bit right-aligned data 0 8 read-write 0 255 DACC1DHRB DAC channel1 8-bit right-aligned data 8 8 read-write 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 read-write 0 4095 DHR12LD DHR12LD Dual DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 read-write 0 4095 DHR8RD DHR8RD Dual DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 1-2 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 read-write 0 255 2 0x4 1-2 DOR%s DOR%s channel%s data output register 0x2C 0x20 read-only 0x00000000 0xFFFFFFFF DACCDOR DAC channel1 data output 0 12 read-only 0 4095 DACC1DORB DAC channel1 data output 16 12 read-only 0 4095 SR SR DAC status register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x10 1-2 DAC%sRDY DAC channel%s ready status bit 11 1 read-only DAC1RDY NotReady DAC channelX is not yet ready to accept the trigger nor output data 0 Ready DAC channelX is ready to accept the trigger or output data 1 2 0x10 1-2 DORSTAT%s DAC channel%s output register status bit 12 1 read-only DORSTAT1 Dor DOR[11:0] is used actual DAC output 0 Dorb DORB[11:0] is used actual DAC output 1 2 0x10 1-2 DMAUDR%s DAC channel%s DMA underrun flag 13 1 read-write DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 2 0x10 1-2 CAL_FLAG%s DAC channel%s calibration offset status 14 1 read-only CAL_FLAG1 Lower Calibration trimming value is lower than the offset correction value 0 Equal_Higher Calibration trimming value is equal or greater than the offset correction value 1 2 0x10 1-2 BWST%s DAC channel%s busy writing sample time flag 15 1 read-only BWST1 Idle There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written 0 Busy There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written 1 CCR CCR DAC calibration control register 0x38 0x20 read-write 0x00000000 0xFF00FF00 2 0x10 1-2 OTRIM%s DAC channel%s offset trimming value 0 5 read-write 0 31 MCR MCR DAC mode control register 0x3C 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x10 1-2 MODE%s DAC channel%s mode 0 3 read-write MODE1 NormalPinBuffer Normal mode - DAC channelx is connected to external pin with Buffer enabled 0 NormalPinChipBuffer Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 1 NormalPinNoBuffer Normal mode - DAC channelx is connected to external pin with Buffer disabled 2 NormalChipNoBuffer Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled 3 SHPinBuffer S&H mode - DAC channelx is connected to external pin with Buffer enabled 4 SHPinChipBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 5 SHPinNoBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled 6 SHChipNoBuffer S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled 7 2 0x10 1-2 DMADOUBLE%s DAC channel%s DMA double data mode 8 1 read-write DMADOUBLE1 Normal DMA Normal mode selected 0 DoubleData DMA Double data mode selected 1 2 0x10 1-2 SINFORMAT%s Enable signed format for DAC channel%s 9 1 read-write SINFORMAT1 Unsigned Input data is in unsigned format 0 Signed Input data is in signed format (2's complement). The MSB bit represents the sign. 1 HFSEL High frequency interface mode selection 14 2 read-write HFSEL Disabled High frequency interface mode disabled 0 More80Mhz High frequency interface mode enabled for AHB clock frequency > 80 MHz 1 More160Mhz High frequency interface mode enabled for AHB clock frequency >160 MHz 2 2 0x4 1-2 SHSR%s SHSR%s DAC channel%s sample and hold sample time register 0x40 0x20 read-write 0x00000000 0xFFFFFFFF TSAMPLE DAC channel1 sample time (only valid in Sample and hold mode) 0 10 read-write 0 1023 SHHR SHHR DAC sample and hold time register 0x48 0x20 read-write 0x00010001 0xFFFFFFFF 2 0x10 1-2 THOLD%s DAC channel%s hold time (only valid in Sample and hold mode) 0 10 read-write 0 1023 SHRR SHRR DAC sample and hold refresh time register 0x4C 0x20 read-write 0x00010001 0xFFFFFFFF 2 0x10 1-2 TREFRESH%s DAC channel%s refresh time (only valid in Sample and hold mode) 0 8 read-write 0 255 DAC_S 0x52028400 DBGMCU DBGMCU register block DBGMCU 0x44024000 0x0 0x1000 registers IDCODE IDCODE DBGMCU identity code register 0x0 0x20 read-only 0x00006000 0x0000F000 DEV_ID Device identification 0 12 read-only REV_ID Revision 16 16 read-only CR CR DBGMCU configuration register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF DBG_STOP Allows debug in Stop mode 1 1 read-write DBG_STANDBY Allows debug in Standby mode 2 1 read-write TRACE_IOEN trace pin enable 4 1 read-write TRACE_EN trace port and clock enable. 5 1 read-write TRACE_MODE trace pin assignment 6 2 read-write DCRT Debug credentials reset type 16 1 read-write APB1LFZR APB1LFZR DBGMCU APB1L peripheral freeze register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF DBG_TIM2_STOP TIM2 stop in debug 0 1 read-write DBG_TIM3_STOP TIM3 stop in debug 1 1 read-write DBG_TIM4_STOP TIM4 stop in debug 2 1 read-write DBG_TIM5_STOP TIM5 stop in debug 3 1 read-write DBG_TIM6_STOP TIM6 stop in debug 4 1 read-write DBG_TIM7_STOP TIM7 stop in debug 5 1 read-write DBG_TIM12_STOP TIM12 stop in debug 6 1 read-write DBG_TIM13_STOP TIM13 stop in debug 7 1 read-write DBG_TIM14_STOP TIM14 stop in debug 8 1 read-write DBG_WWDG_STOP WWDG stop in debug 11 1 read-write DBG_IWDG_STOP IWDG stop in debug 12 1 read-write DBG_I2C1_STOP I2C1 SMBUS timeout stop in debug 21 1 read-write DBG_I2C2_STOP I2C2 SMBUS timeout stop in debug 22 1 read-write DBG_I3C1_STOP I3C1 SCL stall counter stop in debug 23 1 read-write APB1HFZR APB1HFZR DBGMCU APB1H peripheral freeze register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF DBG_LPTIM2_STOP LPTIM2 stop in debug 5 1 read-write APB2FZR APB2FZR DBGMCU APB2 peripheral freeze register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF DBG_TIM1_STOP TIM1 stop in debug 11 1 read-write DBG_TIM8_STOP TIM8 stop in debug 13 1 read-write DBG_TIM15_STOP TIM15 stop in debug 16 1 read-write DBG_TIM16_STOP TIM16 stop in debug 17 1 read-write DBG_TIM17_STOP TIM17 stop in debug 18 1 read-write APB3FZR APB3FZR DBGMCU APB3 peripheral freeze register 0x14 0x20 read-write 0x00000000 0xFFFFFFFF DBG_I2C3_STOP I2C3 SMBUS timeout stop in debug 10 1 read-write DBG_I2C4_STOP I2C4 SMBUS timeout stop in debug 11 1 read-write DBG_LPTIM1_STOP LPTIM1 stop in debug 17 1 read-write DBG_LPTIM3_STOP LPTIM3 stop in debug 18 1 read-write DBG_LPTIM4_STOP LPTIM4 stop in debug 19 1 read-write DBG_LPTIM5_STOP LPTIM5 stop in debug 20 1 read-write DBG_LPTIM6_STOP LPTIM6 stop in debug 21 1 read-write DBG_RTC_STOP RTC stop in debug 30 1 read-write AHB1FZR AHB1FZR DBGMCU AHB1 peripheral freeze register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF DBG_GPDMA1_0_STOP GPDMA1 channel 0 stop in debug 0 1 read-write DBG_GPDMA1_1_STOP GPDMA1 channel 1 stop in debug 1 1 read-write DBG_GPDMA1_2_STOP GPDMA1 channel 2 stop in debug 2 1 read-write DBG_GPDMA1_3_STOP GPDMA1 channel 3 stop in debug 3 1 read-write DBG_GPDMA1_4_STOP GPDMA1 channel 4 stop in debug 4 1 read-write DBG_GPDMA1_5_STOP GPDMA1 channel 5 stop in debug 5 1 read-write DBG_GPDMA1_6_STOP GPDMA1 channel 6 stop in debug 6 1 read-write DBG_GPDMA1_7_STOP GPDMA1 channel 7 stop in debug 7 1 read-write DBG_GPDMA2_0_STOP GPDMA2 channel 0 stop in debug 16 1 read-write DBG_GPDMA2_1_STOP GPDMA2 channel 1 stop in debug 17 1 read-write DBG_GPDMA2_2_STOP GPDMA2 channel 2 stop in debug 18 1 read-write DBG_GPDMA2_3_STOP GPDMA2 channel 3 stop in debug 19 1 read-write DBG_GPDMA2_4_STOP GPDMA2 channel 4 stop in debug 20 1 read-write DBG_GPDMA2_5_STOP GPDMA2 channel 5 stop in debug 21 1 read-write DBG_GPDMA2_6_STOP GPDMA2 channel 6 stop in debug 22 1 read-write DBG_GPDMA2_7_STOP GPDMA2 channel 7 stop in debug 23 1 read-write SR SR DBGMCU status register 0xFC 0x20 read-only 0x00010003 0xFFFF00FF AP_PRESENT Bit n identifies whether access port AP n is present in device 0 16 read-only AP_ENABLED Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) 16 16 read-only DBG_AUTH_HOST DBG_AUTH_HOST DBGMCU debug authentication mailbox host register 0x100 0x20 read-write 0x00000000 0x00000000 MESSAGE Debug host to device mailbox message. 0 32 read-write DBG_AUTH_DEVICE DBG_AUTH_DEVICE DBGMCU debug authentication mailbox device register 0x104 0x20 read-write 0x00000000 0x00000000 MESSAGE Device to debug host mailbox message. 0 32 read-write DBG_AUTH_ACK DBG_AUTH_ACK DBGMCU debug authentication mailbox acknowledge register 0x108 0x20 read-only 0x00000000 0xFFFFFFFF HOST_ACK Host to device acknowledge. 0 1 read-only DEV_ACK Device to host acknowledge. 1 1 read-only PIDR4 PIDR4 DBGMCU CoreSight peripheral identity register 4 0xFD0 0x20 read-only 0x00000000 0xFFFFFFFF JEP106CON JEP106 continuation code 0 4 read-only SIZE register file size 4 4 read-only PIDR0 PIDR0 DBGMCU CoreSight peripheral identity register 0 0xFE0 0x20 read-only 0x00000000 0xFFFFFFFF PARTNUM part number bits [7:0] 0 8 read-only PIDR1 PIDR1 DBGMCU CoreSight peripheral identity register 1 0xFE4 0x20 read-only 0x00000000 0xFFFFFFFF PARTNUM part number bits [11:8] 0 4 read-only JEP106ID JEP106 identity code bits [3:0] 4 4 read-only PIDR2 PIDR2 DBGMCU CoreSight peripheral identity register 2 0xFE8 0x20 read-only 0x0000000A 0xFFFFFFFF JEP106ID JEP106 identity code bits [6:4] 0 3 read-only JEDEC JEDEC assigned value 3 1 read-only REVISION component revision number 4 4 read-only PIDR3 PIDR3 DBGMCU CoreSight peripheral identity register 3 0xFEC 0x20 read-only 0x00000000 0xFFFFFFFF CMOD customer modified 0 4 read-only REVAND metal fix version 4 4 read-only CIDR0 CIDR0 DBGMCU CoreSight component identity register 0 0xFF0 0x20 read-only 0x0000000D 0xFFFFFFFF PREAMBLE component identification bits [7:0] 0 8 read-only CIDR1 CIDR1 DBGMCU CoreSight component identity register 1 0xFF4 0x20 read-only 0x000000F0 0xFFFFFFFF PREAMBLE component identification bits [11:8] 0 4 read-only CLASS component identification bits [15:12] - component class 4 4 read-only CIDR2 CIDR2 DBGMCU CoreSight component identity register 2 0xFF8 0x20 read-only 0x00000005 0xFFFFFFFF PREAMBLE component identification bits [23:16] 0 8 read-only CIDR3 CIDR3 DBGMCU CoreSight component identity register 3 0xFFC 0x20 read-only 0x000000B1 0xFFFFFFFF PREAMBLE component identification bits [31:24] 0 8 read-only DBGMCU_S 0x54024000 DCACHE DCACHE register block DCACHE 0x40031400 0x0 0x400 registers DCACHE Data cache global interrupt 105 CR CR DCACHE control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF EN enable 0 1 read-write CACHEINV full cache invalidation 1 1 write-only CACHECMD cache command maintenance operation (cleans and/or invalidates an address range) 8 3 read-write STARTCMD starts maintenance command (maintenance operation defined in CACHECMD). 11 1 write-only RHITMEN read-hit monitor enable 16 1 read-write RMISSMEN read-miss monitor enable 17 1 read-write RHITMRST read-hit monitor reset 18 1 read-write RMISSMRST read-miss monitor reset 19 1 read-write WHITMEN write-hit monitor enable 20 1 read-write WMISSMEN write-miss monitor enable 21 1 read-write WHITMRST write-hit monitor reset 22 1 read-write WMISSMRST write-miss monitor reset 23 1 read-write HBURST output burst type for cache master port read accesses 31 1 read-write SR SR DCACHE status register 0x4 0x20 read-only 0x00000001 0xFFFFFFFF BUSYF full invalidate busy flag 0 1 read-only BSYENDF full invalidate busy end flag 1 1 read-only ERRF cache error flag 2 1 read-only BUSYCMDF command busy flag 3 1 read-only CMDENDF command end flag 4 1 read-only IER IER DCACHE interrupt enable register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF BSYENDIE interrupt enable on busy end 1 1 read-write ERRIE interrupt enable on cache error 2 1 read-write CMDENDIE interrupt enable on command end 4 1 read-write FCR FCR DCACHE flag clear register 0xC 0x20 write-only 0x00000000 0xFFFFFFFF CBSYENDF clear full invalidate busy end flag 1 1 write-only CERRF clear cache error flag 2 1 write-only CCMDENDF clear command end flag 4 1 write-only RHMONR RHMONR DCACHE read-hit monitor register 0x10 0x20 read-only 0x00000000 0xFFFFFFFF RHITMON cache read-hit monitor counter 0 32 read-only RMMONR RMMONR DCACHE read-miss monitor register 0x14 0x20 read-only 0x00000000 0xFFFFFFFF RMISSMON cache read-miss monitor counter 0 16 read-only WHMONR WHMONR DCACHE write-hit monitor register 0x20 0x20 read-only 0x00000000 0xFFFFFFFF WHITMON cache write-hit monitor counter 0 32 read-only WMMONR WMMONR DCACHE write-miss monitor register 0x24 0x20 read-only 0x00000000 0xFFFFFFFF WMISSMON cache write-miss monitor counter 0 16 read-only CMDRSADDRR CMDRSADDRR DCACHE command range start address register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF CMDSTARTADDR start address of range to which the cache maintenance command specified in DCACHE_CR. 4 28 read-write CMDREADDRR CMDREADDRR DCACHE command range end address register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF CMDENDADDR end address of range to which the cache maintenance command specified in DCACHE_CR. 4 28 read-write DCACHE_S 0x50031400 DCMI DCMI address block description DCMI 0x4202C000 0x0 0x2C registers DCMI_PSSI DCMI/PSSI global interrupt 108 CR CR DCMI control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF CAPTURE Capture enable 0 1 read-write CAPTURE Disabled Capture disabled 0 Enabled Capture enabled 1 CM Capture mode 1 1 read-write CM Continuous Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA 0 Snapshot Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset 1 CROP Crop feature 2 1 read-write CROP Full The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four 0 Cropped Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured 1 JPEG JPEG format 3 1 read-write JPEG Uncompressed Uncompressed video format 0 JPEG This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode 1 ESS Embedded synchronization select 4 1 read-write ESS Hardware Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals 0 Embedded Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow 1 PCKPOL Pixel clock polarity 5 1 read-write PCKPOL FallingEdge Falling edge active 0 RisingEdge Rising edge active 1 HSPOL Horizontal synchronization polarity 6 1 read-write HSPOL ActiveLow DCMI_HSYNC active low 0 ActiveHigh DCMI_HSYNC active high 1 VSPOL Vertical synchronization polarity 7 1 read-write VSPOL ActiveLow DCMI_VSYNC active low 0 ActiveHigh DCMI_VSYNC active high 1 FCRC Frame capture rate control 8 2 read-write FCRC All All frames are captured 0 Alternate Every alternate frame captured (50% bandwidth reduction) 1 OneOfFour One frame out of four captured (75% bandwidth reduction) 2 EDM Extended data mode 10 2 read-write EDM BitWidth8 Interface captures 8-bit data on every pixel clock 0 BitWidth10 Interface captures 10-bit data on every pixel clock 1 BitWidth12 Interface captures 12-bit data on every pixel clock 2 BitWidth14 Interface captures 14-bit data on every pixel clock 3 ENABLE DCMI enable 14 1 read-write ENABLE Disabled DCMI disabled 0 Enabled DCMI enabled 1 BSM Byte Select mode 16 2 read-write BSM All Interface captures all received data 0 EveryOther Interface captures every other byte from the received data 1 Fourth Interface captures one byte out of four 2 TwoOfFour Interface captures two bytes out of four 3 OEBS Odd/Even Byte Select (Byte Select Start) 18 1 read-write OEBS Odd Interface captures first data (byte or double byte) from the frame/line start, second one being dropped 0 Even Interface captures second data (byte or double byte) from the frame/line start, first one being dropped 1 LSM Line Select mode 19 1 read-write LSM All Interface captures all received lines 0 Half Interface captures one line out of two 1 OELS Odd/Even Line Select (Line Select Start) 20 1 read-write OELS Odd Interface captures first line after the frame start, second one being dropped 0 Even Interface captures second line from the frame start, first one being dropped 1 SR SR DCMI status register 0x4 0x20 read-only 0x00000000 0xFFFFFFFF HSYNC Horizontal synchronization 0 1 read-only HSYNC ActiveLine Active line 0 BetweenLines Synchronization between lines 1 VSYNC Vertical synchronization 1 1 read-only VSYNC ActiveFrame Active frame 0 BetweenFrames Synchronization between frames 1 FNE FIFO not empty 2 1 read-only FNE NotEmpty FIFO contains valid data 0 Empty FIFO empty 1 RIS RIS DCMI raw interrupt status register 0x8 0x20 read-only 0x00000000 0xFFFFFFFF FRAME_RIS Capture complete raw interrupt status 0 1 read-only FRAME_RIS NoNewCapture No new capture 0 FrameCaptured A frame has been captured 1 OVR_RIS Overrun raw interrupt status 1 1 read-only OVR_RIS NoOverrun No data buffer overrun occurred 0 OverrunOccured A data buffer overrun occurred and the data FIFO is corrupted. The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register 1 ERR_RIS Synchronization error raw interrupt status 2 1 read-only ERR_RIS NoError No synchronization error detected 0 SynchronizationError Embedded synchronization characters are not received in the correct order 1 VSYNC_RIS DCMI_VSYNC raw interrupt status 3 1 read-only VSYNC_RIS Cleared Interrupt cleared 0 Set Interrupt set 1 LINE_RIS Line raw interrupt status 4 1 read-only LINE_RIS Cleared Interrupt cleared 0 Set Interrupt set 1 IER IER DCMI interrupt enable register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF FRAME_IE Capture complete interrupt enable 0 1 read-write FRAME_IE Disabled No interrupt generation 0 Enabled An interrupt is generated at the end of each received frame/crop window (in crop mode) 1 OVR_IE Overrun interrupt enable 1 1 read-write OVR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received 1 ERR_IE Synchronization error interrupt enable 2 1 read-write ERR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if the embedded synchronization codes are not received in the correct order 1 VSYNC_IE DCMI_VSYNC interrupt enable 3 1 read-write VSYNC_IE Disabled No interrupt generation 0 Enabled An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state 1 LINE_IE Line interrupt enable 4 1 read-write LINE_IE Disabled No interrupt generation when the line is received 0 Enabled An Interrupt is generated when a line has been completely received 1 MIS MIS DCMI masked interrupt status register 0x10 0x20 read-only 0x00000000 0xFFFFFFFF FRAME_MIS Capture complete masked interrupt status 0 1 read-only FRAME_MIS Disabled No interrupt is generated after a complete capture 0 Enabled An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER 1 OVR_MIS Overrun masked interrupt status 1 1 read-only OVR_MIS Disabled No interrupt is generated on overrun 0 Enabled An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER 1 ERR_MIS Synchronization error masked interrupt status 2 1 read-only ERR_MIS Disabled No interrupt is generated on a synchronization error 0 Enabled An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set 1 VSYNC_MIS VSYNC masked interrupt status 3 1 read-only VSYNC_MIS Disabled No interrupt is generated on DCMI_VSYNC transitions 0 Enabled An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER 1 LINE_MIS Line masked interrupt status 4 1 read-only LINE_MIS Disabled No interrupt generation when the line is received 0 Enabled An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER 1 ICR ICR DCMI interrupt clear register 0x14 0x20 write-only 0x00000000 0xFFFFFFFF FRAME_ISC Capture complete interrupt status clear 0 1 write-only FRAME_ISC Clear Setting this bit clears the FRAME_RIS flag in the DCMI_RIS register 1 OVR_ISC Overrun interrupt status clear 1 1 write-only OVR_ISC Clear Setting this bit clears the OVR_RIS flag in the DCMI_RIS register 1 ERR_ISC Synchronization error interrupt status clear 2 1 write-only ERR_ISC Clear Setting this bit clears the ERR_RIS flag in the DCMI_RIS register 1 VSYNC_ISC Vertical Synchronization interrupt status clear 3 1 write-only VSYNC_ISC Clear Setting this bit clears the VSYNC_RIS flag in the DCMI_RIS register 1 LINE_ISC line interrupt status clear 4 1 write-only LINE_ISC Clear Setting this bit clears the LINE_RIS flag in the DCMI_RIS register 1 ESCR ESCR DCMI embedded synchronization code register 0x18 0x20 read-write 0x00000000 0xFFFFFFFF FSC Frame start delimiter code 0 8 read-write LSC Line start delimiter code 8 8 read-write LEC Line end delimiter code 16 8 read-write FEC Frame end delimiter code 24 8 read-write ESUR ESUR DCMI embedded synchronization unmask register 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF FSU Frame start delimiter unmask 0 8 read-write LSU Line start delimiter unmask 8 8 read-write LEU Line end delimiter unmask 16 8 read-write FEU Frame end delimiter unmask 24 8 read-write CWSTRT CWSTRT DCMI crop window start 0x20 0x20 read-write 0x00000000 0xFFFFFFFF HOFFCNT Horizontal offset count 0 14 read-write 0 16383 VST Vertical start line count 16 13 read-write 0 8191 CWSIZE CWSIZE DCMI crop window size 0x24 0x20 read-write 0x00000000 0xFFFFFFFF CAPCNT Capture count 0 14 read-write 0 16383 VLINE Vertical line count 16 14 read-write 0 16383 DR DR DCMI data register 0x28 0x20 read-only 0x00000000 0xFFFFFFFF 4 0x8 0-3 BYTE%s Data byte %s 0 8 read-only 0 255 DCMI_S 0x5202C000 DLYBOS1 DLYB address block description DLYB 0x4600F000 0x0 0x8 registers CR CR DLYB control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF DEN Delay block enable bit 0 1 read-write SEN Sampler length enable bit 1 1 read-write CFGR CFGR DLYB configuration register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF SEL Phase for the output clock. 0 4 read-write UNIT Delay of a unit delay cell. 8 7 read-write LNG Delay line length value 16 12 read-only LNGF Length valid flag 31 1 read-only DLYBOS1_S 0x5600F000 DLYBSD1 0x46008400 DLYBSD1_S 0x56008400 DTS DTS address block description DTS 0x40008C00 0x0 0x30 registers DTS_OR_DTS_WKUP DTS interrupt OR DTS AIT through EXTI line 113 CFGR1 CFGR1 Temperature sensor configuration register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF TS1_EN Temperature sensor 1 enable bit 0 1 read-write TS1_START Start frequency measurement on temperature sensor 1 4 1 read-write TS1_INTRIG_SEL Input trigger selection bit for temperature sensor 1 8 4 read-write TS1_SMP_TIME Sampling time for temperature sensor 1 16 4 read-write REFCLK_SEL Reference clock selection bit 20 1 read-write Q_MEAS_OPT Quick measurement option bit 21 1 read-write HSREF_CLK_DIV High speed clock division ratio 24 7 read-write T0VALR1 T0VALR1 Temperature sensor T0 value register 1 0x8 0x20 read-only 0x00000000 0xFFF00000 TS1_FMT0 Engineering value of the frequency measured at T0 for 0 16 read-only TS1_T0 Engineering value of the T0 temperature for temperature sensor 1. 16 2 read-only RAMPVALR RAMPVALR Temperature sensor ramp value register 0x10 0x20 read-only 0x00000000 0x00000000 TS1_RAMP_COEFF Engineering value of the ramp coefficient for the temperature sensor 1. 0 16 read-only ITR1 ITR1 Temperature sensor interrupt threshold register 1 0x14 0x20 read-write 0x00000000 0xFFFFFFFF TS1_LITTHD Low interrupt threshold for temperature sensor 1 0 16 read-write TS1_HITTHD High interrupt threshold for temperature sensor 1 16 16 read-write DR DR Temperature sensor data register 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF TS1_MFREQ Value of the counter output value for temperature sensor 1 0 16 read-write SR SR Temperature sensor status register 0x20 0x20 read-only 0x00000000 0xFFFFFFFF TS1_ITEF Interrupt flag for end of measurement on temperature sensor 1, synchronized on PCLK. 0 1 read-only TS1_ITLF Interrupt flag for low threshold on temperature sensor 1, synchronized on PCLK. 1 1 read-only TS1_ITHF Interrupt flag for high threshold on temperature sensor 1, synchronized on PCLK 2 1 read-only TS1_AITEF Asynchronous interrupt flag for end of measure on temperature sensor 1 4 1 read-only TS1_AITLF Asynchronous interrupt flag for low threshold on temperature sensor 1 5 1 read-only TS1_AITHF Asynchronous interrupt flag for high threshold on temperature sensor 1 6 1 read-only TS1_RDY Temperature sensor 1 ready flag 15 1 read-only ITENR ITENR Temperature sensor interrupt enable register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF TS1_ITEEN Interrupt enable flag for end of measurement on temperature sensor 1, synchronized on PCLK. 0 1 read-write TS1_ITLEN Interrupt enable flag for low threshold on temperature sensor 1, synchronized on PCLK. 1 1 read-write TS1_ITHEN Interrupt enable flag for high threshold on temperature sensor 1, synchronized on PCLK. 2 1 read-write TS1_AITEEN Asynchronous interrupt enable flag for end of measurement on temperature sensor 1 4 1 read-write TS1_AITLEN Asynchronous interrupt enable flag for low threshold on temperature sensor 1. 5 1 read-write TS1_AITHEN Asynchronous interrupt enable flag on high threshold for temperature sensor 1. 6 1 read-write ICIFR ICIFR Temperature sensor clear interrupt flag register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF TS1_CITEF Interrupt clear flag for end of measurement on temperature sensor 1 0 1 read-write TS1_CITLF Interrupt clear flag for low threshold on temperature sensor 1 1 1 read-write TS1_CITHF Interrupt clear flag for high threshold on temperature sensor 1 2 1 read-write TS1_CAITEF Write once bit. 4 1 read-write TS1_CAITLF Asynchronous interrupt clear flag for low threshold on temperature sensor 1 5 1 read-write TS1_CAITHF Asynchronous interrupt clear flag for high threshold on temperature sensor 1 6 1 read-write OR OR Temperature sensor option register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF TS_OP0 general purpose option bits 0 1 read-write TS_OP1 general purpose option bits 1 1 read-write TS_OP2 general purpose option bits 2 1 read-write TS_OP3 general purpose option bits 3 1 read-write TS_OP4 general purpose option bits 4 1 read-write TS_OP5 general purpose option bits 5 1 read-write TS_OP6 general purpose option bits 6 1 read-write TS_OP7 general purpose option bits 7 1 read-write TS_OP8 general purpose option bits 8 1 read-write TS_OP9 general purpose option bits 9 1 read-write TS_OP10 general purpose option bits 10 1 read-write TS_OP11 general purpose option bits 11 1 read-write TS_OP12 general purpose option bits 12 1 read-write TS_OP13 general purpose option bits 13 1 read-write TS_OP14 general purpose option bits 14 1 read-write TS_OP15 general purpose option bits 15 1 read-write TS_OP16 general purpose option bits 16 1 read-write TS_OP17 general purpose option bits 17 1 read-write TS_OP18 general purpose option bits 18 1 read-write TS_OP19 general purpose option bits 19 1 read-write TS_OP20 general purpose option bits 20 1 read-write TS_OP21 general purpose option bits 21 1 read-write TS_OP22 general purpose option bits 22 1 read-write TS_OP23 general purpose option bits 23 1 read-write TS_OP24 general purpose option bits 24 1 read-write TS_OP25 general purpose option bits 25 1 read-write TS_OP26 general purpose option bits 26 1 read-write TS_OP27 general purpose option bits 27 1 read-write TS_OP28 general purpose option bits 28 1 read-write TS_OP29 general purpose option bits 29 1 read-write TS_OP30 general purpose option bits 30 1 read-write TS_OP31 general purpose option bits 31 1 read-write DTS_S 0x50008C00 EXTI EXTI address block description EXTI 0x44022000 0x0 0x98 registers EXTI15 EXTI Line15 interrupt 26 EXTI14 EXTI Line14 interrupt 25 EXTI13 EXTI Line13 interrupt 24 EXTI12 EXTI Line12 interrupt 23 EXTI11 EXTI Line11 interrupt 22 EXTI10 EXTI Line10 interrupt 21 EXTI9 EXTI Line9 interrupt 20 EXTI8 EXTI Line8 interrupt 19 EXTI7 EXTI Line7 interrupt 18 EXTI6 EXTI Line6 interrupt 17 EXTI5 EXTI Line5 interrupt 16 EXTI4 EXTI Line4 interrupt 15 EXTI3 EXTI Line3 interrupt 14 EXTI2 EXTI Line2 interrupt 13 EXTI1 EXTI Line1 interrupt 12 EXTI0 EXTI Line0 interrupt 11 FPU Floating point interrupt 103 CEC HDMI-CEC global interrupt 119 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF RT0 Rising trigger event configuration bit of configurable event input x 0 1 read-write RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT1 Rising trigger event configuration bit of configurable event input x 1 1 read-write RT2 Rising trigger event configuration bit of configurable event input x 2 1 read-write RT3 Rising trigger event configuration bit of configurable event input x 3 1 read-write RT4 Rising trigger event configuration bit of configurable event input x 4 1 read-write RT5 Rising trigger event configuration bit of configurable event input x 5 1 read-write RT6 Rising trigger event configuration bit of configurable event input x 6 1 read-write RT7 Rising trigger event configuration bit of configurable event input x 7 1 read-write RT8 Rising trigger event configuration bit of configurable event input x 8 1 read-write RT9 Rising trigger event configuration bit of configurable event input x 9 1 read-write RT10 Rising trigger event configuration bit of configurable event input x 10 1 read-write RT11 Rising trigger event configuration bit of configurable event input x 11 1 read-write RT12 Rising trigger event configuration bit of configurable event input x 12 1 read-write RT13 Rising trigger event configuration bit of configurable event input x 13 1 read-write RT14 Rising trigger event configuration bit of configurable event input x 14 1 read-write RT15 Rising trigger event configuration bit of configurable event input x 15 1 read-write RT16 Rising trigger event configuration bit of configurable event input x 16 1 read-write FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF FT0 Falling trigger event configuration bit of configurable event input x 0 1 read-write FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT1 Falling trigger event configuration bit of configurable event input x 1 1 read-write FT2 Falling trigger event configuration bit of configurable event input x 2 1 read-write FT3 Falling trigger event configuration bit of configurable event input x 3 1 read-write FT4 Falling trigger event configuration bit of configurable event input x 4 1 read-write FT5 Falling trigger event configuration bit of configurable event input x 5 1 read-write FT6 Falling trigger event configuration bit of configurable event input x 6 1 read-write FT7 Falling trigger event configuration bit of configurable event input x 7 1 read-write FT8 Falling trigger event configuration bit of configurable event input x 8 1 read-write FT9 Falling trigger event configuration bit of configurable event input x 9 1 read-write FT10 Falling trigger event configuration bit of configurable event input x 10 1 read-write FT11 Falling trigger event configuration bit of configurable event input x 11 1 read-write FT12 Falling trigger event configuration bit of configurable event input x 12 1 read-write FT13 Falling trigger event configuration bit of configurable event input x 13 1 read-write FT14 Falling trigger event configuration bit of configurable event input x 14 1 read-write FT15 Falling trigger event configuration bit of configurable event input x 15 1 read-write FT16 Falling trigger event configuration bit of configurable event input x 16 1 read-write SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SWI0 Software interrupt on event x 0 1 read-write SoftwareInterrupt write Pend Generates an interrupt request 1 SWI1 Software interrupt on event x 1 1 read-write SWI2 Software interrupt on event x 2 1 read-write SWI3 Software interrupt on event x 3 1 read-write SWI4 Software interrupt on event x 4 1 read-write SWI5 Software interrupt on event x 5 1 read-write SWI6 Software interrupt on event x 6 1 read-write SWI7 Software interrupt on event x 7 1 read-write SWI8 Software interrupt on event x 8 1 read-write SWI9 Software interrupt on event x 9 1 read-write SWI10 Software interrupt on event x 10 1 read-write SWI11 Software interrupt on event x 11 1 read-write SWI12 Software interrupt on event x 12 1 read-write SWI13 Software interrupt on event x 13 1 read-write SWI14 Software interrupt on event x 14 1 read-write SWI15 Software interrupt on event x 15 1 read-write SWI16 Software interrupt on event x 16 1 read-write RPR1 RPR1 EXTI rising edge pending register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF RPIF0 configurable event inputs x rising edge pending bit 0 1 read-write oneToClear RPIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 RPIF0W write Clear Clears pending bit 1 RPIF1 configurable event inputs x rising edge pending bit 1 1 read-write oneToClear read write RPIF2 configurable event inputs x rising edge pending bit 2 1 read-write oneToClear read write RPIF3 configurable event inputs x rising edge pending bit 3 1 read-write oneToClear read write RPIF4 configurable event inputs x rising edge pending bit 4 1 read-write oneToClear read write RPIF5 configurable event inputs x rising edge pending bit 5 1 read-write oneToClear read write RPIF6 configurable event inputs x rising edge pending bit 6 1 read-write oneToClear read write RPIF7 configurable event inputs x rising edge pending bit 7 1 read-write oneToClear read write RPIF8 configurable event inputs x rising edge pending bit 8 1 read-write oneToClear read write RPIF9 configurable event inputs x rising edge pending bit 9 1 read-write oneToClear read write RPIF10 configurable event inputs x rising edge pending bit 10 1 read-write oneToClear read write RPIF11 configurable event inputs x rising edge pending bit 11 1 read-write oneToClear read write RPIF12 configurable event inputs x rising edge pending bit 12 1 read-write oneToClear read write RPIF13 configurable event inputs x rising edge pending bit 13 1 read-write oneToClear read write RPIF14 configurable event inputs x rising edge pending bit 14 1 read-write oneToClear read write RPIF15 configurable event inputs x rising edge pending bit 15 1 read-write oneToClear read write RPIF16 configurable event inputs x rising edge pending bit 16 1 read-write oneToClear read write FPR1 FPR1 EXTI falling edge pending register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF FPIF0 configurable event inputs x falling edge pending bit 0 1 read-write oneToClear FPIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 FPIF0W write Clear Clears pending bit 1 FPIF1 configurable event inputs x falling edge pending bit 1 1 read-write oneToClear read write FPIF2 configurable event inputs x falling edge pending bit 2 1 read-write oneToClear read write FPIF3 configurable event inputs x falling edge pending bit 3 1 read-write oneToClear read write FPIF4 configurable event inputs x falling edge pending bit 4 1 read-write oneToClear read write FPIF5 configurable event inputs x falling edge pending bit 5 1 read-write oneToClear read write FPIF6 configurable event inputs x falling edge pending bit 6 1 read-write oneToClear read write FPIF7 configurable event inputs x falling edge pending bit 7 1 read-write oneToClear read write FPIF8 configurable event inputs x falling edge pending bit 8 1 read-write oneToClear read write FPIF9 configurable event inputs x falling edge pending bit 9 1 read-write oneToClear read write FPIF10 configurable event inputs x falling edge pending bit 10 1 read-write oneToClear read write FPIF11 configurable event inputs x falling edge pending bit 11 1 read-write oneToClear read write FPIF12 configurable event inputs x falling edge pending bit 12 1 read-write oneToClear read write FPIF13 configurable event inputs x falling edge pending bit 13 1 read-write oneToClear read write FPIF14 configurable event inputs x falling edge pending bit 14 1 read-write oneToClear read write FPIF15 configurable event inputs x falling edge pending bit 15 1 read-write oneToClear read write FPIF16 configurable event inputs x falling edge pending bit 16 1 read-write oneToClear read write SECCFGR1 SECCFGR1 EXTI security configuration register 0x14 0x20 read-write 0x00000000 0xFFFFFFFF SEC0 Security enable on event input x 0 1 read-write SEC1 Security enable on event input x 1 1 read-write SEC2 Security enable on event input x 2 1 read-write SEC3 Security enable on event input x 3 1 read-write SEC4 Security enable on event input x 4 1 read-write SEC5 Security enable on event input x 5 1 read-write SEC6 Security enable on event input x 6 1 read-write SEC7 Security enable on event input x 7 1 read-write SEC8 Security enable on event input x 8 1 read-write SEC9 Security enable on event input x 9 1 read-write SEC10 Security enable on event input x 10 1 read-write SEC11 Security enable on event input x 11 1 read-write SEC12 Security enable on event input x 12 1 read-write SEC13 Security enable on event input x 13 1 read-write SEC14 Security enable on event input x 14 1 read-write SEC15 Security enable on event input x 15 1 read-write SEC16 Security enable on event input x 16 1 read-write SEC17 Security enable on event input x 17 1 read-write SEC18 Security enable on event input x 18 1 read-write SEC19 Security enable on event input x 19 1 read-write SEC20 Security enable on event input x 20 1 read-write SEC21 Security enable on event input x 21 1 read-write SEC22 Security enable on event input x 22 1 read-write SEC23 Security enable on event input x 23 1 read-write SEC24 Security enable on event input x 24 1 read-write SEC25 Security enable on event input x 25 1 read-write SEC26 Security enable on event input x 26 1 read-write SEC27 Security enable on event input x 27 1 read-write SEC28 Security enable on event input x 28 1 read-write SEC29 Security enable on event input x 29 1 read-write SEC30 Security enable on event input x 30 1 read-write SEC31 Security enable on event input x 31 1 read-write PRIVCFGR1 PRIVCFGR1 EXTI privilege configuration register 0x18 0x20 read-write 0x00000000 0xFFFFFFFF PRIV0 Security enable on event input x 0 1 read-write EventPrivilege Unprivileged Event privilege disabled 0 Privileged Event privilege enabled 1 PRIV1 Security enable on event input x 1 1 read-write PRIV2 Security enable on event input x 2 1 read-write PRIV3 Security enable on event input x 3 1 read-write PRIV4 Security enable on event input x 4 1 read-write PRIV5 Security enable on event input x 5 1 read-write PRIV6 Security enable on event input x 6 1 read-write PRIV7 Security enable on event input x 7 1 read-write PRIV8 Security enable on event input x 8 1 read-write PRIV9 Security enable on event input x 9 1 read-write PRIV10 Security enable on event input x 10 1 read-write PRIV11 Security enable on event input x 11 1 read-write PRIV12 Security enable on event input x 12 1 read-write PRIV13 Security enable on event input x 13 1 read-write PRIV14 Security enable on event input x 14 1 read-write PRIV15 Security enable on event input x 15 1 read-write PRIV16 Security enable on event input x 16 1 read-write PRIV17 Security enable on event input x 17 1 read-write PRIV18 Security enable on event input x 18 1 read-write PRIV19 Security enable on event input x 19 1 read-write PRIV20 Security enable on event input x 20 1 read-write PRIV21 Security enable on event input x 21 1 read-write PRIV22 Security enable on event input x 22 1 read-write PRIV23 Security enable on event input x 23 1 read-write PRIV24 Security enable on event input x 24 1 read-write PRIV25 Security enable on event input x 25 1 read-write PRIV26 Security enable on event input x 26 1 read-write PRIV27 Security enable on event input x 27 1 read-write PRIV28 Security enable on event input x 28 1 read-write PRIV29 Security enable on event input x 29 1 read-write PRIV30 Security enable on event input x 30 1 read-write PRIV31 Security enable on event input x 31 1 read-write RTSR2 RTSR2 EXTI rising trigger selection register 2 0x20 0x20 read-write 0x00000000 0xFFFFFFFF RT46 Rising trigger event configuration bit of configurable event input xless thansup>(1)less than/sup> 14 1 read-write RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT50 Rising trigger event configuration bit of configurable event input xless thansup>(1)less than/sup> 18 1 read-write RT53 Rising trigger event configuration bit of configurable event input x 21 1 read-write FTSR2 FTSR2 EXTI falling trigger selection register 2 0x24 0x20 read-write 0x00000000 0xFFFFFFFF FT46 Falling trigger event configuration bit of configurable event input x less thansup>(1)less than/sup> 14 1 read-write FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT50 Falling trigger event configuration bit of configurable event input x less thansup>(1)less than/sup> 18 1 read-write FT53 Falling trigger event configuration bit of configurable event input x 21 1 read-write SWIER2 SWIER2 EXTI software interrupt event register 2 0x28 0x20 read-write 0x00000000 0xFFFFFFFF SWI46 Software interrupt on event x 14 1 read-write SoftwareInterrupt write Pend Generates an interrupt request 1 SWI50 Software interrupt on event x 18 1 read-write SWI53 Software interrupt on event x 21 1 read-write RPR2 RPR2 EXTI rising edge pending register 2 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF RPIF46 configurable event inputs x rising edge pending bit 14 1 read-write oneToClear RPIF46R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 RPIF46W write Clear Clears pending bit 1 RPIF50 configurable event inputs x rising edge pending bit 18 1 read-write oneToClear read write RPIF53 configurable event inputs x rising edge pending bit 21 1 read-write oneToClear read write FPR2 FPR2 EXTI falling edge pending register 2 0x30 0x20 read-write 0x00000000 0xFFFFFFFF FPIF46 configurable event inputs x falling edge pending bit 14 1 read-write oneToClear FPIF46R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 FPIF46W write Clear Clears pending bit 1 FPIF50 configurable event inputs x falling edge pending bit 18 1 read-write oneToClear read write FPIF53 configurable event inputs x falling edge pending bit 21 1 read-write oneToClear read write SECCFGR2 SECCFGR2 EXTI security configuration register 2 0x34 0x20 read-write 0x00000000 0xFFFFFFFF SEC32 Security enable on event input x 0 1 read-write SEC33 Security enable on event input x 1 1 read-write SEC34 Security enable on event input x 2 1 read-write SEC35 Security enable on event input x 3 1 read-write SEC36 Security enable on event input x 4 1 read-write SEC37 Security enable on event input x 5 1 read-write SEC38 Security enable on event input x 6 1 read-write SEC39 Security enable on event input x 7 1 read-write SEC40 Security enable on event input x 8 1 read-write SEC41 Security enable on event input x 9 1 read-write SEC42 Security enable on event input x 10 1 read-write SEC43 Security enable on event input x 11 1 read-write SEC44 Security enable on event input x 12 1 read-write SEC45 Security enable on event input x 13 1 read-write SEC46 Security enable on event input x 14 1 read-write SEC47 Security enable on event input x 15 1 read-write SEC48 Security enable on event input x 16 1 read-write SEC49 Security enable on event input x 17 1 read-write SEC50 Security enable on event input x 18 1 read-write SEC51 Security enable on event input x 19 1 read-write SEC52 Security enable on event input x 20 1 read-write SEC53 Security enable on event input x 21 1 read-write SEC54 Security enable on event input x 22 1 read-write SEC55 Security enable on event input x 23 1 read-write SEC56 Security enable on event input x 24 1 read-write SEC57 Security enable on event input x 25 1 read-write PRIVCFGR2 PRIVCFGR2 EXTI privilege configuration register 2 0x38 0x20 read-write 0x00000000 0xFFFFFFFF PRIV32 Security enable on event input x 0 1 read-write EventPrivilege Unprivileged Event privilege disabled 0 Privileged Event privilege enabled 1 PRIV33 Security enable on event input x 1 1 read-write PRIV34 Security enable on event input x 2 1 read-write PRIV35 Security enable on event input x 3 1 read-write PRIV36 Security enable on event input x 4 1 read-write PRIV37 Security enable on event input x 5 1 read-write PRIV38 Security enable on event input x 6 1 read-write PRIV39 Security enable on event input x 7 1 read-write PRIV40 Security enable on event input x 8 1 read-write PRIV41 Security enable on event input x 9 1 read-write PRIV42 Security enable on event input x 10 1 read-write PRIV43 Security enable on event input x 11 1 read-write PRIV44 Security enable on event input x 12 1 read-write PRIV45 Security enable on event input x 13 1 read-write PRIV46 Security enable on event input x 14 1 read-write PRIV47 Security enable on event input x 15 1 read-write PRIV48 Security enable on event input x 16 1 read-write PRIV49 Security enable on event input x 17 1 read-write PRIV50 Security enable on event input x 18 1 read-write PRIV51 Security enable on event input x 19 1 read-write PRIV52 Security enable on event input x 20 1 read-write PRIV53 Security enable on event input x 21 1 read-write PRIV54 Security enable on event input x 22 1 read-write PRIV55 Security enable on event input x 23 1 read-write PRIV56 Security enable on event input x 24 1 read-write PRIV57 Security enable on event input x 25 1 read-write EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 read-write 0x00000000 0xFFFFFFFF EXTI0 EXTI0 GPIO port selection 0 8 read-write EXTI1 EXTI1 GPIO port selection 8 8 read-write EXTI2 EXTI2 GPIO port selection 16 8 read-write EXTI3 EXTI3 GPIO port selection 24 8 read-write EXTICR4 EXTICR4 EXTI external interrupt selection register EXTICR1 0x60 0x20 read-write 0x00000000 0xFFFFFFFF EXTI12 EXTI12 GPIO port selection 0 8 read-write EXTI13 EXTI13 GPIO port selection 8 8 read-write EXTI14 EXTI14 GPIO port selection 16 8 read-write EXTI15 EXTI15 GPIO port selection 24 8 read-write EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 read-write 0x00000000 0xFFFFFFFF EXTI4 EXTI4 GPIO port selection 0 8 read-write EXTI5 EXTI5 GPIO port selection 8 8 read-write EXTI6 EXTI6 GPIO port selection 16 8 read-write EXTI7 EXTI7 GPIO port selection 24 8 read-write EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 0x20 read-write 0x00000000 0xFFFFFFFF EXTI8 EXTI8 GPIO port selection 0 8 read-write EXTI9 EXTI9 GPIO port selection 8 8 read-write EXTI10 EXTI10 GPIO port selection 16 8 read-write EXTI11 EXTI11 GPIO port selection 24 8 read-write LOCKR LOCKR EXTI lock register 0x70 0x20 read-write 0x00000000 0xFFFFFFFF LOCK Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock 0 1 read-write IMR1 IMR1 EXTI CPU wake-up with interrupt mask register 0x80 0x20 read-write 0xFFFE0000 0xFFFFFFFF IM0 CPU wake-up with interrupt mask on event input x 0 1 read-write InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 IM1 CPU wake-up with interrupt mask on event input x 1 1 read-write IM2 CPU wake-up with interrupt mask on event input x 2 1 read-write IM3 CPU wake-up with interrupt mask on event input x 3 1 read-write IM4 CPU wake-up with interrupt mask on event input x 4 1 read-write IM5 CPU wake-up with interrupt mask on event input x 5 1 read-write IM6 CPU wake-up with interrupt mask on event input x 6 1 read-write IM7 CPU wake-up with interrupt mask on event input x 7 1 read-write IM8 CPU wake-up with interrupt mask on event input x 8 1 read-write IM9 CPU wake-up with interrupt mask on event input x 9 1 read-write IM10 CPU wake-up with interrupt mask on event input x 10 1 read-write IM11 CPU wake-up with interrupt mask on event input x 11 1 read-write IM12 CPU wake-up with interrupt mask on event input x 12 1 read-write IM13 CPU wake-up with interrupt mask on event input x 13 1 read-write IM14 CPU wake-up with interrupt mask on event input x 14 1 read-write IM15 CPU wake-up with interrupt mask on event input x 15 1 read-write IM16 CPU wake-up with interrupt mask on event input x 16 1 read-write IM17 CPU wake-up with interrupt mask on event input x 17 1 read-write IM18 CPU wake-up with interrupt mask on event input x 18 1 read-write IM19 CPU wake-up with interrupt mask on event input x 19 1 read-write IM20 CPU wake-up with interrupt mask on event input x 20 1 read-write IM21 CPU wake-up with interrupt mask on event input x 21 1 read-write IM22 CPU wake-up with interrupt mask on event input x 22 1 read-write IM23 CPU wake-up with interrupt mask on event input x 23 1 read-write IM24 CPU wake-up with interrupt mask on event input x 24 1 read-write IM25 CPU wake-up with interrupt mask on event input x 25 1 read-write IM26 CPU wake-up with interrupt mask on event input x 26 1 read-write IM27 CPU wake-up with interrupt mask on event input x 27 1 read-write IM28 CPU wake-up with interrupt mask on event input x 28 1 read-write IM29 CPU wake-up with interrupt mask on event input x 29 1 read-write IM30 CPU wake-up with interrupt mask on event input x 30 1 read-write IM31 CPU wake-up with interrupt mask on event input x 31 1 read-write EMR1 EMR1 EXTI CPU wake-up with event mask register 0x84 0x20 read-write 0x00000000 0xFFFFFFFF EM0 CPU wake-up with event generation mask on event input x 0 1 read-write EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM1 CPU wake-up with event generation mask on event input x 1 1 read-write EM2 CPU wake-up with event generation mask on event input x 2 1 read-write EM3 CPU wake-up with event generation mask on event input x 3 1 read-write EM4 CPU wake-up with event generation mask on event input x 4 1 read-write EM5 CPU wake-up with event generation mask on event input x 5 1 read-write EM6 CPU wake-up with event generation mask on event input x 6 1 read-write EM7 CPU wake-up with event generation mask on event input x 7 1 read-write EM8 CPU wake-up with event generation mask on event input x 8 1 read-write EM9 CPU wake-up with event generation mask on event input x 9 1 read-write EM10 CPU wake-up with event generation mask on event input x 10 1 read-write EM11 CPU wake-up with event generation mask on event input x 11 1 read-write EM12 CPU wake-up with event generation mask on event input x 12 1 read-write EM13 CPU wake-up with event generation mask on event input x 13 1 read-write EM14 CPU wake-up with event generation mask on event input x 14 1 read-write EM15 CPU wake-up with event generation mask on event input x 15 1 read-write EM16 CPU wake-up with event generation mask on event input x 16 1 read-write EM17 CPU wake-up with event generation mask on event input x 17 1 read-write EM18 CPU wake-up with event generation mask on event input x 18 1 read-write EM19 CPU wake-up with event generation mask on event input x 19 1 read-write EM20 CPU wake-up with event generation mask on event input x 20 1 read-write EM21 CPU wake-up with event generation mask on event input x 21 1 read-write EM22 CPU wake-up with event generation mask on event input x 22 1 read-write EM23 CPU wake-up with event generation mask on event input x 23 1 read-write EM24 CPU wake-up with event generation mask on event input x 24 1 read-write EM25 CPU wake-up with event generation mask on event input x 25 1 read-write EM26 CPU wake-up with event generation mask on event input x 26 1 read-write EM27 CPU wake-up with event generation mask on event input x 27 1 read-write EM28 CPU wake-up with event generation mask on event input x 28 1 read-write EM29 CPU wake-up with event generation mask on event input x 29 1 read-write EM30 CPU wake-up with event generation mask on event input x 30 1 read-write EM31 CPU wake-up with event generation mask on event input x 31 1 read-write IMR2 IMR2 EXTI CPU wake-up with interrupt mask register 2 0x90 0x20 read-write 0x07DBBFFF 0xFFFFFFFF IM32 CPU wake-up with interrupt mask on event input x 0 1 read-write InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 IM33 CPU wake-up with interrupt mask on event input x 1 1 read-write IM34 CPU wake-up with interrupt mask on event input x 2 1 read-write IM35 CPU wake-up with interrupt mask on event input x 3 1 read-write IM36 CPU wake-up with interrupt mask on event input x 4 1 read-write IM37 CPU wake-up with interrupt mask on event input x 5 1 read-write IM38 CPU wake-up with interrupt mask on event input x 6 1 read-write IM39 CPU wake-up with interrupt mask on event input x 7 1 read-write IM40 CPU wake-up with interrupt mask on event input x 8 1 read-write IM41 CPU wake-up with interrupt mask on event input x 9 1 read-write IM42 CPU wake-up with interrupt mask on event input x 10 1 read-write IM43 CPU wake-up with interrupt mask on event input x 11 1 read-write IM44 CPU wake-up with interrupt mask on event input x 12 1 read-write IM45 CPU wake-up with interrupt mask on event input x 13 1 read-write IM46 CPU wake-up with interrupt mask on event input x 14 1 read-write IM47 CPU wake-up with interrupt mask on event input x 15 1 read-write IM48 CPU wake-up with interrupt mask on event input x 16 1 read-write IM49 CPU wake-up with interrupt mask on event input x 17 1 read-write IM50 CPU wake-up with interrupt mask on event input x 18 1 read-write IM51 CPU wake-up with interrupt mask on event input x 19 1 read-write IM52 CPU wake-up with interrupt mask on event input x 20 1 read-write IM53 CPU wake-up with interrupt mask on event input x 21 1 read-write IM54 CPU wake-up with interrupt mask on event input x 22 1 read-write IM55 CPU wake-up with interrupt mask on event input x 23 1 read-write IM56 CPU wake-up with interrupt mask on event input x 24 1 read-write IM57 CPU wake-up with interrupt mask on event input x 25 1 read-write IM58 CPU wake-up with interrupt mask on event input x 26 1 read-write EMR2 EMR2 EXTI CPU wake-up with event mask register 2 0x94 0x20 read-write 0x00000000 0xFFFFFFFF EM32 CPU wake-up with event generation mask on event input x 0 1 read-write EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM33 CPU wake-up with event generation mask on event input x 1 1 read-write EM34 CPU wake-up with event generation mask on event input x 2 1 read-write EM35 CPU wake-up with event generation mask on event input x 3 1 read-write EM36 CPU wake-up with event generation mask on event input x 4 1 read-write EM37 CPU wake-up with event generation mask on event input x 5 1 read-write EM38 CPU wake-up with event generation mask on event input x 6 1 read-write EM39 CPU wake-up with event generation mask on event input x 7 1 read-write EM40 CPU wake-up with event generation mask on event input x 8 1 read-write EM41 CPU wake-up with event generation mask on event input x 9 1 read-write EM42 CPU wake-up with event generation mask on event input x 10 1 read-write EM43 CPU wake-up with event generation mask on event input x 11 1 read-write EM44 CPU wake-up with event generation mask on event input x 12 1 read-write EM45 CPU wake-up with event generation mask on event input x 13 1 read-write EM46 CPU wake-up with event generation mask on event input x 14 1 read-write EM47 CPU wake-up with event generation mask on event input x 15 1 read-write EM48 CPU wake-up with event generation mask on event input x 16 1 read-write EM49 CPU wake-up with event generation mask on event input x 17 1 read-write EM50 CPU wake-up with event generation mask on event input x 18 1 read-write EM51 CPU wake-up with event generation mask on event input x 19 1 read-write EM52 CPU wake-up with event generation mask on event input x 20 1 read-write EM53 CPU wake-up with event generation mask on event input x 21 1 read-write EM54 CPU wake-up with event generation mask on event input x 22 1 read-write EM55 CPU wake-up with event generation mask on event input x 23 1 read-write EM56 CPU wake-up with event generation mask on event input x 24 1 read-write EM57 CPU wake-up with event generation mask on event input x 25 1 read-write EM58 CPU wake-up with event generation mask on event input x 26 1 read-write EXTI_S 0x54022000 FDCAN1 FDCAN register blank and RAM FDCAN 0x4000A400 0x0 0x400 registers FDCAN1_IT1 FDCAN1 Interrupt 1 40 FDCAN1_IT0 FDCAN1 Interrupt 0 39 CREL CREL FDCAN core release register 0x0 0x20 read-only 0x32141218 0xFFFFFFFF DAY 18 0 8 read-only MON 12 8 8 read-only YEAR 4 16 4 read-only SUBSTEP 1 20 4 read-only STEP 2 24 4 read-only REL 3 28 4 read-only ENDN ENDN FDCAN endian register 0x4 0x20 read-only 0x87654321 0xFFFFFFFF ETV Endianness test value 0 32 read-only DBTP DBTP FDCAN data bit timing and prescaler register 0xC 0x20 read-write 0x00000A33 0xFFFFFFFF DSJW Synchronization jump width 0 4 read-write DTSEG2 Data time segment after sample point 4 4 read-write DTSEG1 Data time segment before sample point 8 5 read-write DBRP Data bit rate prescaler 16 5 read-write TDC Transceiver delay compensation 23 1 read-write TEST TEST FDCAN test register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF LBCK Loop back mode 4 1 read-write TX Control of transmit pin 5 2 read-write RX Receive pin 7 1 read-only RWD RWD FDCAN RAM watchdog register 0x14 0x20 read-write 0x00000000 0xFFFFFFFF WDC Watchdog configuration 0 8 read-write WDV Watchdog value 8 8 read-only CCCR CCCR FDCAN CC control register 0x18 0x20 read-write 0x00000001 0xFFFFFFFF INIT Initialization 0 1 read-write CCE Configuration change enable 1 1 read-write ASM ASM restricted operation mode 2 1 read-write CSA Clock stop acknowledge 3 1 read-only CSR Clock stop request 4 1 read-write MON Bus monitoring mode 5 1 read-write DAR Disable automatic retransmission 6 1 read-write TEST Test mode enable 7 1 read-write FDOE FD operation enable 8 1 read-write BRSE FDCAN bit rate switching 9 1 read-write PXHD Protocol exception handling disable 12 1 read-write EFBI Edge filtering during bus integration 13 1 read-write TXP If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. 14 1 read-write NISO Non ISO operation 15 1 read-write NBTP NBTP FDCAN nominal bit timing and prescaler register 0x1C 0x20 read-write 0x06000A03 0xFFFFFFFF NTSEG2 Nominal time segment after sample point 0 7 read-write NTSEG1 Nominal time segment before sample point 8 8 read-write NBRP Bit rate prescaler 16 9 read-write NSJW Nominal (re)synchronization jump width 25 7 read-write TSCC TSCC FDCAN timestamp counter configuration register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF TSS Timestamp select 0 2 read-write TCP Timestamp counter prescaler 16 4 read-write TSCV TSCV FDCAN timestamp counter value register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF TSC Timestamp counter 0 16 read-write TOCC TOCC FDCAN timeout counter configuration register 0x28 0x20 read-write 0xFFFF0000 0xFFFFFFFF ETOC Timeout counter enable 0 1 read-write TOS Timeout select 1 2 read-write TOP Timeout period 16 16 read-write TOCV TOCV FDCAN timeout counter value register 0x2C 0x20 read-write 0x0000FFFF 0xFFFFFFFF TOC Timeout counter 0 16 read-write ECR ECR FDCAN error counter register 0x40 0x20 read-write 0x00000000 0xFFFFFFFF TEC Transmit error counter 0 8 read-only REC Receive error counter 8 7 read-only RP Receive error passive 15 1 read-only CEL CAN error logging 16 8 read-write PSR PSR FDCAN protocol status register 0x44 0x20 read-write 0x00000707 0xFFFFFFFF LEC Last error code 0 3 read-write ACT Activity 3 2 read-only EP Error passive 5 1 read-only EW Warning Sstatus 6 1 read-only BO Bus_Off status 7 1 read-only DLEC Data last error code 8 3 read-write RESI ESI flag of last received FDCAN message 11 1 read-write RBRS BRS flag of last received FDCAN message 12 1 read-write REDL Received FDCAN message 13 1 read-write PXE Protocol exception event 14 1 read-write TDCV Transmitter delay compensation value 16 7 read-only TDCR TDCR FDCAN transmitter delay compensation register 0x48 0x20 read-write 0x00000000 0xFFFFFFFF TDCF Transmitter delay compensation filter window length 0 7 read-write TDCO Transmitter delay compensation offset 8 7 read-write IR IR FDCAN interrupt register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF RF0N Rx FIFO 0 new message 0 1 read-write RF0F Rx FIFO 0 full 1 1 read-write RF0L Rx FIFO 0 message lost 2 1 read-write RF1N Rx FIFO 1 new message 3 1 read-write RF1F Rx FIFO 1 full 4 1 read-write RF1L Rx FIFO 1 message lost 5 1 read-write HPM High-priority message 6 1 read-write TC Transmission completed 7 1 read-write TCF Transmission cancellation finished 8 1 read-write TFE Tx FIFO empty 9 1 read-write TEFN Tx event FIFO New Entry 10 1 read-write TEFF Tx event FIFO full 11 1 read-write TEFL Tx event FIFO element lost 12 1 read-write TSW Timestamp wraparound 13 1 read-write MRAF Message RAM access failure 14 1 read-write TOO Timeout occurred 15 1 read-write ELO Error logging overflow 16 1 read-write EP Error passive 17 1 read-write EW Warning status 18 1 read-write BO Bus_Off status 19 1 read-write WDI Watchdog interrupt 20 1 read-write PEA Protocol error in arbitration phase (nominal bit time is used) 21 1 read-write PED Protocol error in data phase (data bit time is used) 22 1 read-write ARA Access to reserved address 23 1 read-write IE IE FDCAN interrupt enable register 0x54 0x20 read-write 0x00000000 0xFFFFFFFF RF0NE Rx FIFO 0 new message interrupt enable 0 1 read-write RF0FE Rx FIFO 0 full interrupt enable 1 1 read-write RF0LE Rx FIFO 0 message lost interrupt enable 2 1 read-write RF1NE Rx FIFO 1 new message interrupt enable 3 1 read-write RF1FE Rx FIFO 1 full interrupt enable 4 1 read-write RF1LE Rx FIFO 1 message lost interrupt enable 5 1 read-write HPME High-priority message interrupt enable 6 1 read-write TCE Transmission completed interrupt enable 7 1 read-write TCFE Transmission cancellation finished interrupt enable 8 1 read-write TFEE Tx FIFO empty interrupt enable 9 1 read-write TEFNE Tx event FIFO new entry interrupt enable 10 1 read-write TEFFE Tx event FIFO full interrupt enable 11 1 read-write TEFLE Tx event FIFO element lost interrupt enable 12 1 read-write TSWE Timestamp wraparound interrupt enable 13 1 read-write MRAFE Message RAM access failure interrupt enable 14 1 read-write TOOE Timeout occurred interrupt enable 15 1 read-write ELOE Error logging overflow interrupt enable 16 1 read-write EPE Error passive interrupt enable 17 1 read-write EWE Warning status interrupt enable 18 1 read-write BOE Bus_Off status 19 1 read-write WDIE Watchdog interrupt enable 20 1 read-write PEAE Protocol error in arbitration phase enable 21 1 read-write PEDE Protocol error in data phase enable 22 1 read-write ARAE Access to reserved address enable 23 1 read-write ILS ILS FDCAN interrupt line select register 0x58 0x20 read-write 0x00000000 0xFFFFFFFF RXFIFO0 RX FIFO bit grouping the following interruption 0 1 read-write RXFIFO1 RX FIFO bit grouping the following interruption 1 1 read-write SMSG Status message bit grouping the following interruption 2 1 read-write TFERR Tx FIFO ERROR grouping the following interruption 3 1 read-write MISC Interrupt regrouping the following interruption 4 1 read-write BERR Bit and line error grouping the following interruption 5 1 read-write PERR Protocol error grouping the following interruption 6 1 read-write ILE ILE FDCAN interrupt line enable register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF EINT0 Enable interrupt line 0 0 1 read-write EINT1 Enable interrupt line 1 1 1 read-write RXGFC RXGFC FDCAN global filter configuration register 0x80 0x20 read-write 0x00000000 0xFFFFFFFF RRFE Reject remote frames extended 0 1 read-write RRFS Reject remote frames standard 1 1 read-write ANFE Accept non-matching frames extended 2 2 read-write ANFS Accept Non-matching frames standard 4 2 read-write F1OM FIFO 1 operation mode (overwrite or blocking) 8 1 read-write F0OM FIFO 0 operation mode (overwrite or blocking) 9 1 read-write LSS List size standard 16 5 read-write LSE List size extended 24 4 read-write XIDAM XIDAM FDCAN extended ID and mask register 0x84 0x20 read-write 0x1FFFFFFF 0xFFFFFFFF EIDM Extended ID mask 0 29 read-write HPMS HPMS FDCAN high-priority message status register 0x88 0x20 read-only 0x00000000 0xFFFFFFFF BIDX Buffer index 0 3 read-only MSI Message storage indicator 6 2 read-only FIDX Filter index 8 5 read-only FLST Filter list 15 1 read-only RXF0S RXF0S FDCAN Rx FIFO 0 status register 0x90 0x20 read-only 0x00000000 0xFFFFFFFF F0FL Rx FIFO 0 fill level 0 4 read-only F0GI Rx FIFO 0 get index 8 2 read-only F0PI Rx FIFO 0 put index 16 2 read-only F0F Rx FIFO 0 full 24 1 read-only RF0L Rx FIFO 0 message lost 25 1 read-only RXF0A RXF0A CAN Rx FIFO 0 acknowledge register 0x94 0x20 read-write 0x00000000 0xFFFFFFFF F0AI Rx FIFO 0 acknowledge index 0 3 read-write RXF1S RXF1S FDCAN Rx FIFO 1 status register 0x98 0x20 read-only 0x00000000 0xFFFFFFFF F1FL Rx FIFO 1 fill level 0 4 read-only F1GI Rx FIFO 1 get index 8 2 read-only F1PI Rx FIFO 1 put index 16 2 read-only F1F Rx FIFO 1 full 24 1 read-only RF1L Rx FIFO 1 message lost 25 1 read-only RXF1A RXF1A FDCAN Rx FIFO 1 acknowledge register 0x9C 0x20 read-write 0x00000000 0xFFFFFFFF F1AI Rx FIFO 1 acknowledge index 0 3 read-write TXBC TXBC FDCAN Tx buffer configuration register 0xC0 0x20 read-write 0x00000000 0xFFFFFFFF TFQM Tx FIFO/queue mode 24 1 read-write TXFQS TXFQS FDCAN Tx FIFO/queue status register 0xC4 0x20 read-only 0x00000003 0xFFFFFFFF TFFL Tx FIFO free level 0 3 read-only TFGI Tx FIFO get index 8 2 read-only TFQPI Tx FIFO/queue put index 16 2 read-only TFQF Tx FIFO/queue full 21 1 read-only TXBRP TXBRP FDCAN Tx buffer request pending register 0xC8 0x20 read-only 0x00000000 0xFFFFFFFF TRP Transmission request pending 0 3 read-only TXBAR TXBAR FDCAN Tx buffer add request register 0xCC 0x20 read-write 0x00000000 0xFFFFFFFF AR Add request 0 3 read-write TXBCR TXBCR FDCAN Tx buffer cancellation request register 0xD0 0x20 read-write 0x00000000 0xFFFFFFFF CR Cancellation request 0 3 read-write TXBTO TXBTO FDCAN Tx buffer transmission occurred register 0xD4 0x20 read-only 0x00000000 0xFFFFFFFF TO Transmission occurred. 0 3 read-only TXBCF TXBCF FDCAN Tx buffer cancellation finished register 0xD8 0x20 read-only 0x00000000 0xFFFFFFFF CF Cancellation finished 0 3 read-only TXBTIE TXBTIE FDCAN Tx buffer transmission interrupt enable register 0xDC 0x20 read-write 0x00000000 0xFFFFFFFF TIE Transmission interrupt enable 0 3 read-write TXBCIE TXBCIE FDCAN Tx buffer cancellation finished interrupt enable register 0xE0 0x20 read-write 0x00000000 0xFFFFFFFF CFIE Cancellation finished interrupt enable. 0 3 read-write TXEFS TXEFS FDCAN Tx event FIFO status register 0xE4 0x20 read-only 0x00000000 0xFFFFFFFF EFFL Event FIFO fill level 0 3 read-only EFGI Event FIFO get index 8 2 read-only EFPI Event FIFO put index 16 2 read-only EFF Event FIFO full 24 1 read-only TEFL Tx event FIFO element lost 25 1 read-only TXEFA TXEFA FDCAN Tx event FIFO acknowledge register 0xE8 0x20 read-write 0x00000000 0xFFFFFFFF EFAI Event FIFO acknowledge index 0 2 read-write CKDIV CKDIV FDCAN CFG clock divider register 0x100 0x20 read-write 0x00000000 0xFFFFFFFF PDIV input clock divider 0 4 read-write FDCAN1_S 0x5000A400 FDCAN2 0x4000A800 FDCAN2_IT1 FDCAN2 Interrupt 1 110 FDCAN2_IT0 FDCAN2 Interrupt 0 109 FDCAN2_S 0x5000A800 FLASH Mustang_FLASH register block FLASH 0x40022000 0x0 0x400 registers FLASH Flash non-secure global interrupt 6 ACR ACR FLASH access control register 0x0 0x20 read-write 0x00000013 0xFFFFFFFF LATENCY Read latency 0 4 read-write WRHIGHFREQ Flash signal delay 4 2 read-write PRFTEN Prefetch enable. 8 1 read-write NSKEYR NSKEYR FLASH non-secure key register 0x4 0x20 write-only 0x00000000 0xFFFFFFFF NSKEY Non-volatile memory non-secure configuration access unlock key 0 32 write-only SECKEYR SECKEYR FLASH secure key register 0x8 0x20 write-only 0x00000000 0xFFFFFFFF SECKEY Non-volatile memory secure configuration access unlock key 0 32 write-only OPTKEYR OPTKEYR FLASH option key register 0xC 0x20 write-only 0x00000000 0xFFFFFFFF OPTKEY FLASH option bytes control access unlock key 0 32 write-only NSOBKKEYR NSOBKKEYR FLASH non-secure OBK key register 0x10 0x20 write-only 0x00000000 0xFFFFFFFF NSOBKKEY FLASH non-secure option bytes keys control access unlock key 0 32 write-only SECOBKKEYR SECOBKKEYR FLASH secure OBK key register 0x14 0x20 write-only 0x00000000 0xFFFFFFFF SECOBKKEY FLASH secure option bytes keys control access unlock key 0 32 write-only OPSR OPSR FLASH operation status register 0x18 0x20 read-only 0x00000000 0x00000000 ADDR_OP Interrupted operation address 0 20 read-only DATA_OP Flash high-cycle data area operation interrupted 21 1 read-only BK_OP Interrupted operation bank 22 1 read-only SYSF_OP Operation in system flash memory interrupted 23 1 read-only OTP_OP OTP operation interrupted 24 1 read-only CODE_OP Flash memory operation code 29 3 read-only OPTCR OPTCR FLASH option control register 0x1C 0x20 read-write 0x00000001 0x0FFFFFFF OPTLOCK FLASH_OPTCR lock option configuration bit 0 1 read-write OPTSTRT Option byte start change option configuration bit 1 1 read-write SWAP_BANK Bank swapping option configuration bit 31 1 read-only NSSR NSSR FLASH non-secure status register 0x20 0x20 read-only 0x00000000 0xFFFFFFF0 BSY busy flag 0 1 read-only WBNE write buffer not empty flag 1 1 read-only DBNE data buffer not empty flag 3 1 read-only EOP end of operation flag 16 1 read-only WRPERR write protection error flag 17 1 read-only PGSERR programming sequence error flag 18 1 read-only STRBERR strobe error flag 19 1 read-only INCERR inconsistency error flag 20 1 read-only OBKERR OBK general error flag 21 1 read-only OBKWERR OBK write error flag 22 1 read-only OPTCHANGEERR Option byte change error flag 23 1 read-only SECSR SECSR FLASH secure status register 0x24 0x20 read-only 0x00000000 0xFFFFFFF0 BSY busy flag 0 1 read-only WBNE write buffer not empty flag 1 1 read-only DBNE data buffer not empty flag 3 1 read-only EOP end of operation flag 16 1 read-only WRPERR write protection error flag 17 1 read-only PGSERR programming sequence error flag 18 1 read-only STRBERR strobe error flag 19 1 read-only INCERR inconsistency error flag 20 1 read-only OBKERR OBK general error flag 21 1 read-only OBKWERR OBK write error flag 22 1 read-only NSCR NSCR FLASH non-secure control register 0x28 0x20 read-write 0x00000001 0xFFFFFFFF LOCK configuration lock bit 0 1 read-write PG programming control bit 1 1 read-write SER sector erase request 2 1 read-write BER erase request 3 1 read-write FW write forcing control bit 4 1 read-write STRT erase start control bit 5 1 read-write SNB sector erase selection number 6 7 read-write MER mass erase request 15 1 read-write EOPIE end of operation interrupt control bit 16 1 read-write WRPERRIE write protection error interrupt enable bit 17 1 read-write PGSERRIE programming sequence error interrupt enable bit 18 1 read-write STRBERRIE strobe error interrupt enable bit 19 1 read-write INCERRIE inconsistency error interrupt enable bit 20 1 read-write OBKERRIE OBK general error interrupt enable bit 21 1 read-write OBKWERRIE OBK write error interrupt enable bit 22 1 read-write OPTCHANGEERRIE Option byte change error interrupt enable bit 23 1 read-write BKSEL Bank selector bit 31 1 read-write SECCR SECCR FLASH secure control register 0x2C 0x20 read-write 0x00000001 0xFFFFFFFF LOCK configuration lock bit 0 1 read-write PG programming control bit 1 1 read-write SER sector erase request 2 1 read-write BER erase request 3 1 read-write FW write forcing control bit 4 1 read-write STRT erase start control bit 5 1 read-write SNB sector erase selection number 6 7 read-write MER mass erase request 15 1 read-write EOPIE end of operation interrupt control bit 16 1 read-write WRPERRIE write protection error interrupt enable bit 17 1 read-write PGSERRIE programming sequence error interrupt enable bit 18 1 read-write STRBERRIE strobe error interrupt enable bit 19 1 read-write INCERRIE inconsistency error interrupt enable bit 20 1 read-write OBKERRIE OBK general error interrupt enable bit 21 1 read-write OBKWERRIE OBK write error interrupt enable bit 22 1 read-write INV Flash memory security state invert. 29 1 read-write BKSEL Bank selector bit 31 1 read-write NSCCR NSCCR FLASH non-secure clear control register 0x30 0x20 write-only 0x00000000 0xFFFFFFFF CLR_EOP EOP flag clear bit 16 1 write-only CLR_WRPERR WRPERR flag clear bit 17 1 write-only CLR_PGSERR PGSERR flag clear bit 18 1 write-only CLR_STRBERR STRBERR flag clear bit 19 1 write-only CLR_INCERR INCERR flag clear bit 20 1 write-only CLR_OBKERR OBKERR flag clear bit. 21 1 write-only CLR_OBKWERR OBKWERR flag clear bit. 22 1 write-only CLR_OPTCHANGEERR Clear the flag corresponding flag in FLASH_NSSR by writing this bit. 23 1 write-only SECCCR SECCCR FLASH secure clear control register 0x34 0x20 write-only 0x00000000 0xFFFFFFFF CLR_EOP EOP flag clear bit 16 1 write-only CLR_WRPERR WRPERR flag clear bit 17 1 write-only CLR_PGSERR PGSERR flag clear bit 18 1 write-only CLR_STRBERR STRBERR flag clear bit 19 1 write-only CLR_INCERR INCERR flag clear bit 20 1 write-only CLR_OBKERR OBKWERR flag clear bit 21 1 write-only CLR_OBKWERR OBKWERR flag clear bit 22 1 write-only PRIVCFGR PRIVCFGR FLASH privilege configuration register 0x3C 0x20 read-write 0x00000000 0xFFFFFFFF SPRIV privilege attribute for secure registers 0 1 read-write NSPRIV privilege attribute for non secure registers 1 1 read-write NSOBKCFGR NSOBKCFGR FLASH non-secure OBK configuration register 0x40 0x20 read-write 0x01FF0000 0xFFFFFFFF LOCK OBKCFGR lock option configuration bit 0 1 read-write SWAP_SECT_REQ OBK swap sector request bit 1 1 read-write ALT_SECT alternate sector bit 2 1 read-write ALT_SECT_ERASE alternate sector erase bit 3 1 read-write SWAP_OFFSET Key index (offset /16 bits) pointing for next swap. 16 9 read-write SECOBKCFGR SECOBKCFGR FLASH secure OBK configuration register 0x44 0x20 read-write 0x01FF0000 0xFFFFFFFF LOCK OBKCFGR lock option configuration bit 0 1 read-write SWAP_SECT_REQ OBK swap sector request bit 1 1 read-write ALT_SECT alternate sector bit 2 1 read-write ALT_SECT_ERASE alternate sector erase bit 3 1 read-write SWAP_OFFSET key index (offset /16 bits) pointing for next swap. 16 9 read-write HDPEXTR HDPEXTR FLASH HDP extension register 0x48 0x20 read-write 0x00000000 0xFFFFFFFF HDP1_EXT HDP area extension in 8 Kbytes sectors in Bank1. 0 7 read-write HDP2_EXT HDP area extension in 8 Kbytes sectors in Bank2. 16 7 read-write OPTSR_CUR OPTSR_CUR FLASH option status register 0x50 0x20 read-only 0x00000000 0x00000000 BOR_LEV Brownout level option status bit 0 2 read-only BORH_EN Brownout high enable 2 1 read-only IWDG_SW IWDG control mode option status bit 3 1 read-only WWDG_SW WWDG control mode option status bit 4 1 read-only NRST_STOP Core domain Stop entry reset option status bit 6 1 read-only NRST_STDBY Core domain Standby entry reset option status bit 7 1 read-only PRODUCT_STATE Life state code (based on Hamming 8,4). 8 8 read-only IO_VDD_HSLV High-speed IO at low Vless thansub>DDless than/sub> voltage configuration bit. 16 1 read-only IO_VDDIO2_HSLV High-speed IO at low Vless thansub>DDIO2less than/sub> voltage configuration bit. 17 1 read-only IWDG_STOP IWDG Stop mode freeze option status bit 20 1 read-only IWDG_STDBY IWDG Standby mode freeze option status bit 21 1 read-only BOOT_UBE Available only on cryptography enabled devices. 22 8 read-only SWAP_BANK Bank swapping option status bit 31 1 read-only OPTSR_PRG OPTSR_PRG FLASH option status register 0x54 0x20 read-write 0x00000000 0x00000000 BOR_LEV Brownout level option configuration bit 0 2 read-write BORH_EN Brownout high enable configuration bit 2 1 read-write IWDG_SW IWDG control mode option configuration bit 3 1 read-write WWDG_SW WWDG control mode option configuration bit 4 1 read-write NRST_STOP Core domain Stop entry reset option configuration bit 6 1 read-write NRST_STDBY Core domain Standby entry reset option configuration bit 7 1 read-write PRODUCT_STATE Life state code (based on Hamming 8,4). 8 8 read-write IO_VDD_HSLV High-speed IO at low VDD voltage configuration bit. 16 1 read-write IO_VDDIO2_HSLV High-speed IO at low Vless thansub>DDIO2less than/sub> voltage configuration bit. 17 1 read-write IWDG_STOP IWDG Stop mode freeze option status bit 20 1 read-write IWDG_STDBY IWDG Standby mode freeze option status bit 21 1 read-write BOOT_UBE Available only on cryptography enabled devices. 22 8 read-write SWAP_BANK Bank swapping option configuration bit 31 1 read-write NSEPOCHR_CUR NSEPOCHR_CUR FLASH non-secure EPOCH register 0x60 0x20 read-only 0x00000000 0x00000000 NS_EPOCH Non-volatile non-secure EPOCH counter 0 24 read-only SECEPOCHR_CUR SECEPOCHR_CUR FLASH secure EPOCH register 0x68 0x20 read-only 0x00000000 0x00000000 SEC_EPOCH Non-volatile secure EPOCH counter 0 24 read-only OPTSR2_CUR OPTSR2_CUR FLASH option status register 2 0x70 0x20 read-only 0x00000000 0x00000000 SRAM13_RST SRAM1 and SRAM3 erase upon system reset 2 1 read-only SRAM2_RST SRAM2 erase when system reset 3 1 read-only BKPRAM_ECC Backup RAM ECC detection and correction disable 4 1 read-only SRAM3_ECC SRAM3 ECC detection and correction disable 5 1 read-only SRAM2_ECC SRAM2 ECC detection and correction disable 6 1 read-only USBPD_DIS USB power delivery configuration option bit 8 1 read-only TZEN TrustZone enable configuration bits 24 8 read-only OPTSR2_PRG OPTSR2_PRG FLASH option status register 2 0x74 0x20 read-write 0x00000000 0x00000000 SRAM1_3_RST SRAM1 and SRAM3 erase upon system reset 2 1 read-write SRAM2_RST SRAM2 erase when system reset 3 1 read-write BKPRAM_ECC Backup RAM ECC detection and correction disable 4 1 read-write SRAM3_ECC SRAM3 ECC detection and correction disable 5 1 read-write SRAM2_ECC SRAM2 ECC detection and correction disable 6 1 read-write USBPD_DIS USB power delivery configuration option bit 8 1 read-write TZEN TrustZone enable configuration bits 24 8 read-write NSBOOTR_CUR NSBOOTR_CUR FLASH non-secure boot register 0x80 0x20 read-only 0x00000000 0x00000000 NSBOOT_LOCK Field locking the values of SWAP_BANK, and NSBOOTADD settings. 0 8 read-only NSBOOTADD Non secure unique boot entry address 8 24 read-only NSBOOTR_PRG NSBOOTR_PRG FLASH non-secure boot register 0x84 0x20 read-write 0x00000000 0x00000000 NSBOOT_LOCK Field locking the values of SWAP_ BANK, and NSBOOTADD settings. 0 8 read-write NSBOOTADD Non secure unique boot entry address 8 24 read-write SECBOOTR_CUR SECBOOTR_CUR FLASH secure boot register 0x88 0x20 read-only 0x00000000 0x00000000 SECBOOT_LOCK Field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. 0 8 read-only SECBOOTADD Unique boot entry secure address 8 24 read-only BOOTR_PRG BOOTR_PRG FLASH secure boot register 0x8C 0x20 read-write 0x00000000 0x00000000 SECBOOT_LOCK Field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting. 0 8 read-write SECBOOTADD Secure unique boot entry address. 8 24 read-write OTPBLR_CUR OTPBLR_CUR FLASH non-secure OTP block lock 0x90 0x20 read-only 0x00000000 0x00000000 LOCKBL OTP block lock 0 32 read-only OTPBLR_PRG OTPBLR_PRG FLASH non-secure OTP block lock 0x94 0x20 read-write 0x00000000 0x00000000 LOCKBL OTP block lock 0 32 read-write SECBB1R1 SECBB1R1 FLASH secure block based register for Bank1 0xA0 0x20 read-write 0x00000000 0xFFFFFFFF SECBB1 Secure/non-secure 8 Kbytes flash Bank1 sector attributes 0 32 read-write SECBB1R2 SECBB1R2 FLASH secure block based register for Bank1 0xA4 0x20 read-write 0x00000000 0xFFFFFFFF SECBB1 Secure/non-secure 8 Kbytes flash Bank1 sector attributes 0 32 read-write SECBB1R3 SECBB1R3 FLASH secure block based register for Bank1 0xA8 0x20 read-write 0x00000000 0xFFFFFFFF SECBB1 Secure/non-secure 8 Kbytes flash Bank1 sector attributes 0 32 read-write SECBB1R4 SECBB1R4 FLASH secure block based register for Bank1 0xAC 0x20 read-write 0x00000000 0xFFFFFFFF SECBB1 Secure/non-secure 8 Kbytes flash Bank1 sector attributes 0 32 read-write PRIVBB1R1 PRIVBB1R1 FLASH privilege block based register for Bank1 0xC0 0x20 read-write 0x00000000 0xFFFFFFFF PRIVBB1 Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute 0 32 read-write PRIVBB1R2 PRIVBB1R2 FLASH privilege block based register for Bank1 0xC4 0x20 read-write 0x00000000 0xFFFFFFFF PRIVBB1 Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute 0 32 read-write PRIVBB1R3 PRIVBB1R3 FLASH privilege block based register for Bank1 0xC8 0x20 read-write 0x00000000 0xFFFFFFFF PRIVBB1 Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute 0 32 read-write PRIVBB1R4 PRIVBB1R4 FLASH privilege block based register for Bank1 0xCC 0x20 read-write 0x00000000 0xFFFFFFFF PRIVBB1 Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute 0 32 read-write SECWM1R_CUR SECWM1R_CUR FLASH security watermark for Bank1 0xE0 0x20 read-only 0x00000000 0xFF00FF00 SECWM1_STRT Bank1 security WM area 1 start sector 0 7 read-only SECWM1_END Bank1 security WM area 1 end sector 16 7 read-only SECWM1R_PRG SECWM1R_PRG FLASH security watermark for Bank1 0xE4 0x20 read-write 0x00000000 0xFF00FF00 SECWM1_STRT Bank1 security WM area 1 start sector 0 7 read-write SECWM1_END Bank1 security WM area 1 end sector 16 7 read-write WRP1R_CUR WRP1R_CUR FLASH write sector group protection for Bank1 0xE8 0x20 read-only 0x00000000 0x00000000 WRPSG1 Bank1 sector group protection option status byte 0 32 read-only WRP1R_PRG WRP1R_PRG FLASH write sector group protection for Bank1 0xEC 0x20 read-write 0x00000000 0x00000000 WRPSG1 Bank1 sector group protection option status byte 0 32 read-write EDATA1R_CUR EDATA1R_CUR FLASH data sector configuration Bank1 0xF0 0x20 read-only 0x00000000 0x00000000 EDATA1_STRT EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank1 There is no hardware effect to those bits. 0 3 read-only EDATA1_EN Bank1 flash high-cycle data enable 15 1 read-only EDATA1R_PRG EDATA1R_PRG FLASH data sector configuration Bank1 0xF4 0x20 read-write 0x00000000 0x00000000 EDATA1_STRT EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank1 There is no hardware effect to those bits. 0 3 read-write EDATA1_EN Bank1 flash high-cycle data enable 15 1 read-write HDP1R_CUR HDP1R_CUR FLASH HDP Bank1 configuration 0xF8 0x20 read-only 0x00000000 0x00000000 HDP1_STRT HDPL barrier start set in number of 8-Kbyte sectors 0 7 read-only HDP1_END HDPL barrier end set in number of 8-Kbyte sectors 16 7 read-only HDP1R_PRG HDP1R_PRG FLASH HDP Bank1 configuration 0xFC 0x20 read-write 0x00000000 0x00000000 HDP1_STRT HDPL barrier start set in number of 8-Kbyte sectors 0 7 read-write HDP1_END HDPL barrier end set in number of 8-Kbyte sectors 16 7 read-write ECCCORR ECCCORR FLASH ECC correction register 0x100 0x20 read-write 0x00000000 0xFFFFFFFF ADDR_ECC ECC error address 0 16 read-only OBK_ECC Single ECC error corrected in flash OB Keys storage area. 20 1 read-only EDATA_ECC ECC fail for corrected ECC error in flash high-cycle data area 21 1 read-only BK_ECC ECC fail bank for corrected ECC error 22 1 read-only SYSF_ECC ECC fail for corrected ECC error in system flash memory 23 1 read-only OTP_ECC OTP ECC error bit 24 1 read-only ECCCIE ECC single correction error interrupt enable bit 25 1 read-write ECCC ECC correction set by hardware when single ECC error has been detected and corrected. 30 1 read-write ECCDETR ECCDETR FLASH ECC detection register 0x104 0x20 read-write 0x00000000 0xFFFFFFFF ADDR_ECC ECC error address 0 16 read-only OBK_ECC ECC fail double ECC error in flash OB Keys storage area. 20 1 read-only EDATA_ECC ECC fail double ECC error in flash high-cycle data area 21 1 read-only BK_ECC ECC fail bank for double ECC error 22 1 read-only SYSF_ECC ECC fail for double ECC error in system flash memory 23 1 read-only OTP_ECC OTP ECC error bit 24 1 read-only ECCD ECC detection 31 1 read-write ECCDR ECCDR FLASH ECC data 0x108 0x20 read-only 0x00000000 0xFFFFFFFF DATA_ECC ECC error data 0 16 read-only SECBB2R1 SECBB2R1 FLASH secure block-based register for Bank2 0x1A0 0x20 read-write 0x00000000 0xFFFFFFFF SECBB2 Secure/non-secure flash Bank2 sector attribute 0 32 read-write SECBB2R2 SECBB2R2 FLASH secure block-based register for Bank2 0x1A4 0x20 read-write 0x00000000 0xFFFFFFFF SECBB2 Secure/non-secure flash Bank2 sector attribute 0 32 read-write SECBB2R3 SECBB2R3 FLASH secure block-based register for Bank2 0x1A8 0x20 read-write 0x00000000 0xFFFFFFFF SECBB2 Secure/non-secure flash Bank2 sector attribute 0 32 read-write SECBB2R4 SECBB2R4 FLASH secure block-based register for Bank2 0x1AC 0x20 read-write 0x00000000 0xFFFFFFFF SECBB2 Secure/non-secure flash Bank2 sector attribute 0 32 read-write PRIVBB2R1 PRIVBB2R1 FLASH privilege block-based register for Bank2 0x1C0 0x20 read-write 0x00000000 0xFFFFFFFF PRIVBB2 Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute 0 32 read-write PRIVBB2R2 PRIVBB2R2 FLASH privilege block-based register for Bank2 0x1C4 0x20 read-write 0x00000000 0xFFFFFFFF PRIVBB2 Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute 0 32 read-write PRIVBB2R3 PRIVBB2R3 FLASH privilege block-based register for Bank2 0x1C8 0x20 read-write 0x00000000 0xFFFFFFFF PRIVBB2 Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute 0 32 read-write PRIVBB2R4 PRIVBB2R4 FLASH privilege block-based register for Bank2 0x1CC 0x20 read-write 0x00000000 0xFFFFFFFF PRIVBB2 Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute 0 32 read-write SECWM2R_CUR SECWM2R_CUR FLASH security watermark for Bank2 0x1E0 0x20 read-only 0x00000000 0xFF00FF00 SECWM2_STRT Bank2 security WM area start sector 0 7 read-only SECWM2_END Bank2 security WM end sector 16 7 read-only SECWM2R_PRG SECWM2R_PRG FLASH security watermark for Bank2 0x1E4 0x20 read-write 0x00000000 0xFF00FF00 SECWM2_STRT Bank2 security WM area start sector 0 7 read-write SECWM2_END Bank2 security WM area end sector 16 7 read-write WRP2R_CUR WRP2R_CUR FLASH write sector group protection for Bank2 0x1E8 0x20 read-only 0x00000000 0x00000000 WRPSG2 Bank2 sector group protection option status byte 0 32 read-only WRP2R_PRG WRP2R_PRG FLASH write sector group protection for Bank2 0x1EC 0x20 read-write 0x00000000 0x00000000 WRPSG2 Bank2 sector group protection option status byte 0 32 read-write EDATA2R_CUR EDATA2R_CUR FLASH data sectors configuration Bank2 0x1F0 0x20 read-only 0x00000000 0x00000000 EDATA2_STRT EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank2 There is no hardware effect to those bits. 0 3 read-only EDATA2_EN Bank2 flash high-cycle data enable 15 1 read-only EDATA2R_PRG EDATA2R_PRG FLASH data sector configuration Bank2 0x1F4 0x20 read-write 0x00000000 0x00000000 EDATA2_STRT EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank2 There is no hardware effect to those bits. 0 3 read-write EDATA2_EN Bank2 flash high-cycle data enable 15 1 read-write HDP2R_CUR HDP2R_CUR FLASH HDP Bank2 configuration 0x1F8 0x20 read-only 0x00000000 0x00000000 HDP2_STRT HDPL barrier start set in number of 8-Kbyte sectors 0 7 read-only HDP2_END HDPL barrier end set in number of 8-Kbyte sectors 16 7 read-only HDP2R_PRG HDP2R_PRG FLASH HDP Bank2 configuration 0x1FC 0x20 read-write 0x00000000 0x00000000 HDP2_STRT HDPL barrier start set in number of 8-Kbyte sectors 0 7 read-write HDP2_END HDPL barrier end set in number of 8-Kbyte sectors 16 7 read-write FLASH_S 0x50022000 FLASH_S Flash secure global interrupt 7 FMC FMC address block description FMC 0x47000400 0x0 0x15C registers FMC FMC global interrupt 77 BCR1 BCR1 SRAM/NOR-flash chip-select control register for bank 1 0x0 0x20 read-write 0x000030DB 0xFFFFFFFF MBKEN Memory bank enable bit 0 1 read-write MBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 MUXEN Address/data multiplexing enable bit 1 1 read-write MUXEN Disabled Address/Data non-multiplexed 0 Enabled Address/Data multiplexed on databus 1 MTYP Memory type 2 2 read-write MTYP SRAM SRAM memory type 0 PSRAM PSRAM (CRAM) memory type 1 Flash NOR Flash/OneNAND Flash 2 MWID Memory data bus width 4 2 read-write MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 FACCEN Flash access enable 6 1 read-write FACCEN Disabled Corresponding NOR Flash memory access is disabled 0 Enabled Corresponding NOR Flash memory access is enabled 1 BURSTEN Burst enable bit 8 1 read-write BURSTEN Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 WAITPOL Wait signal polarity bit 9 1 read-write WAITPOL ActiveLow NWAIT active low 0 ActiveHigh NWAIT active high 1 WAITCFG Wait timing configuration 11 1 read-write WAITCFG BeforeWaitState NWAIT signal is active one data cycle before wait state 0 DuringWaitState NWAIT signal is active during wait state 1 WREN Write enable bit 12 1 read-write WREN Disabled Write operations disabled for the bank by the FMC 0 Enabled Write operations enabled for the bank by the FMC 1 WAITEN Wait enable bit 13 1 read-write WAITEN Disabled Values inside the FMC_BWTR are taken into account 0 Enabled NWAIT signal enabled 1 EXTMOD Extended mode enable 14 1 read-write EXTMOD Disabled Values inside the FMC_BWTR are not taken into account 0 Enabled Values inside the FMC_BWTR are taken into account 1 ASYNCWAIT Wait signal during asynchronous transfers 15 1 read-write ASYNCWAIT Disabled Wait signal not used in asynchronous mode 0 Enabled Wait signal used even in asynchronous mode 1 CPSIZE CRAM page size 16 3 read-write CPSIZE NoBurstSplit No burst split when crossing page boundary 0 Bytes128 128 bytes CRAM page size 1 Bytes256 256 bytes CRAM page size 2 Bytes512 512 bytes CRAM page size 3 Bytes1024 1024 bytes CRAM page size 4 CBURSTRW Write burst enable 19 1 read-write CBURSTRW Disabled Write operations are always performed in asynchronous mode 0 Enabled Write operations are performed in synchronous mode 1 CCLKEN Continuous clock enable 20 1 read-write CCLKEN Disabled The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set 0 Enabled The FMC_CLK is only generated during the synchronous memory access (read/write transaction) 1 WFDIS Write FIFO disable 21 1 read-write WFDIS Enabled Write FIFO enabled 0 Disabled Write FIFO disabled 1 NBLSET Byte lane (NBL) setup 22 2 read-write FMCEN FMC controller enable 31 1 read-write FMCEN Disabled Disable the FMC controller 0 Enabled Enable the FMC controller 1 4 0x8 1-4 BTR%s BTR%s SRAM/NOR-flash chip-select timing register for bank %s 0x4 0x20 read-write 0x0FFFFFFF 0xFFFFFFFF ADDSET Address setup phase duration 0 4 read-write 0 15 ADDHLD Address-hold phase duration 4 4 read-write 1 15 DATAST Data-phase duration 8 8 read-write 1 255 BUSTURN Bus turnaround phase duration 16 4 read-write 0 15 CLKDIV Clock divide ratio (for FMC_CLK signal) 20 4 read-write 1 15 DATLAT (see note below bit descriptions): Data latency for synchronous memory 24 4 read-write 0 15 ACCMOD Access mode 28 2 read-write ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATAHLD Data hold phase duration 30 2 read-write 3 0x8 2-4 BCR%s BCR%s SRAM/NOR-flash chip-select control register for bank %s 0x8 0x20 read-write 0x000030D2 0xFFFFFFFF MBKEN Memory bank enable bit 0 1 read-write MUXEN Address/data multiplexing enable bit 1 1 read-write MTYP Memory type 2 2 read-write MWID Memory data bus width 4 2 read-write FACCEN Flash access enable 6 1 read-write BURSTEN Burst enable bit 8 1 read-write WAITPOL Wait signal polarity bit 9 1 read-write WAITCFG Wait timing configuration 11 1 read-write WREN Write enable bit 12 1 read-write WAITEN Wait enable bit 13 1 read-write EXTMOD Extended mode enable 14 1 read-write ASYNCWAIT Wait signal during asynchronous transfers 15 1 read-write CPSIZE CRAM page size 16 3 read-write CBURSTRW Write burst enable 19 1 read-write NBLSET Byte lane (NBL) setup 22 2 read-write PCSCNTR PCSCNTR PSRAM chip select counter register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF CSCOUNT Chip select counter. 0 16 read-write 4 0x1 1-4 CNTB%sEN Counter Bank %s enable 16 1 read-write PCR PCR NAND flash control registers 0x80 0x20 read-write 0x00000018 0xFFFFFFFF PWAITEN Wait feature enable bit 1 1 read-write PWAITEN Disabled Wait feature disabled 0 Enabled Wait feature enabled 1 PBKEN NAND flash memory bank enable bit 2 1 read-write PBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 PTYP Memory type 3 1 read-write PTYP NANDFlash NAND Flash 1 PWID Data bus width 4 2 read-write PWID Bits8 External memory device width 8 bits 0 Bits16 External memory device width 16 bits 1 ECCEN ECC computation logic enable bit 6 1 read-write ECCEN Disabled ECC logic is disabled and reset 0 Enabled ECC logic is enabled 1 TCLR CLE to RE delay 9 4 read-write 0 15 TAR ALE to RE delay 13 4 0 15 ECCPS ECC page size 17 3 read-write ECCPS Bytes256 ECC page size 256 bytes 0 Bytes512 ECC page size 512 bytes 1 Bytes1024 ECC page size 1024 bytes 2 Bytes2048 ECC page size 2048 bytes 3 Bytes4096 ECC page size 4096 bytes 4 Bytes8192 ECC page size 8192 bytes 5 SR SR FIFO status and interrupt register 0x84 0x20 read-write 0x00000040 0xFFFFFFFF IRS Interrupt rising edge status 0 1 read-write IRS DidNotOccur Interrupt rising edge did not occur 0 Occurred Interrupt rising edge occurred 1 ILS Interrupt high-level status 1 1 read-write ILS DidNotOccur Interrupt high-level did not occur 0 Occurred Interrupt high-level occurred 1 IFS Interrupt falling edge status 2 1 read-write IFS DidNotOccur Interrupt falling edge did not occur 0 Occurred Interrupt falling edge occurred 1 IREN Interrupt rising edge detection enable bit 3 1 read-write IREN Disabled Interrupt rising edge detection request disabled 0 Enabled Interrupt rising edge detection request enabled 1 ILEN Interrupt high-level detection enable bit 4 1 read-write ILEN Disabled Interrupt high-level detection request disabled 0 Enabled Interrupt high-level detection request enabled 1 IFEN Interrupt falling edge detection enable bit 5 1 read-write IFEN Disabled Interrupt falling edge detection request disabled 0 Enabled Interrupt falling edge detection request enabled 1 FEMPT FIFO empty 6 1 read-only FEMPT NotEmpty FIFO not empty 0 Empty FIFO empty 1 PMEM PMEM Common memory space timing register 0x88 0x20 read-write 0xFCFCFCFC 0xFFFFFFFF MEMSET Common memory x setup time 0 8 read-write 0 254 MEMWAIT Common memory wait time 8 8 read-write 1 254 MEMHOLD Common memory hold time 16 8 read-write 1 254 MEMHIZ Common memory x data bus Hi-Z time 24 8 read-write 0 254 PATT PATT Attribute memory space timing register 0x8C 0x20 read-write 0xFCFCFCFC 0xFFFFFFFF ATTSET Attribute memory setup time 0 8 read-write 0 254 ATTWAIT Attribute memory wait time 8 8 read-write 1 254 ATTHOLD Attribute memory hold time 16 8 read-write 1 254 ATTHIZ Attribute memory data bus Hi-Z time 24 8 read-write 0 254 ECCR ECCR ECC result registers 0x94 0x20 read-only 0x00000000 0xFFFFFFFF ECC ECC result 0 32 read-only 0 4294967295 4 0x8 1-4 BWTR%s BWTR%s SRAM/NOR-flash write timing registers %s 0x104 0x20 read-write 0x0FFFFFFF 0xFFFFFFFF ADDSET Address setup phase duration. 0 4 read-write 0 15 ADDHLD Address-hold phase duration. 4 4 read-write 1 15 DATAST Data-phase duration. 8 8 read-write 1 255 BUSTURN Bus turnaround phase duration 16 4 read-write 0 15 ACCMOD Access mode. 28 2 read-write ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATAHLD Data hold phase duration 30 2 read-write SDCR1 SDCR1 SDRAM control registers 1,2 0x140 0x20 read-write 0x000002D0 0xFFFFFFFF NC Number of column address bits 0 2 read-write NC Bits8 8 bits 0 Bits9 9 bits 1 Bits10 10 bits 2 Bits11 11 bits 3 NR Number of row address bits 2 2 read-write NR Bits11 11 bits 0 Bits12 12 bits 1 Bits13 13 bits 2 MWID Memory data bus width. 4 2 read-write MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 NB Number of internal banks 6 1 read-write NB NB2 Two internal Banks 0 NB4 Four internal Banks 1 CAS CAS Latency 7 2 read-write CAS Clocks1 1 cycle 1 Clocks2 2 cycles 2 Clocks3 3 cycles 3 WP Write protection 9 1 read-write WP Disabled Write accesses allowed 0 Enabled Write accesses ignored 1 SDCLK SDRAM clock configuration 10 2 read-write SDCLK Disabled SDCLK clock disabled 0 Div2 SDCLK period = 2 x HCLK period 2 Div3 SDCLK period = 3 x HCLK period 3 RBURST Burst read 12 1 read-write RBURST Disabled Single read requests are not managed as bursts 0 Enabled Single read requests are always managed as bursts 1 RPIPE Read pipe 13 2 read-write RPIPE NoDelay No clock cycle delay 0 Clocks1 One clock cycle delay 1 Clocks2 Two clock cycles delay 2 SDCR2 SDCR2 SDRAM control registers 1,2 0x144 0x20 read-write 0x000002D0 0xFFFFFFFF NC Number of column address bits 0 2 read-write NR Number of row address bits 2 2 read-write MWID Memory data bus width. 4 2 read-write NB Number of internal banks 6 1 read-write CAS CAS Latency 7 2 read-write WP Write protection 9 1 read-write SDCLK SDRAM clock configuration 10 2 read-write RBURST Burst read 12 1 read-write RBURST Disabled Single read requests are not managed as bursts 0 Enabled Single read requests are always managed as bursts 1 RPIPE Read pipe 13 2 read-write RPIPE NoDelay No clock cycle delay 0 Clocks1 One clock cycle delay 1 Clocks2 Two clock cycles delay 2 2 0x4 1-2 SDTR%s SDTR%s SDRAM timing registers 1,2 0x148 0x20 read-write 0x0FFFFFFF 0xFFFFFFFF TMRD Load Mode Register to Active 0 4 read-write 0 15 TXSR Exit Self-refresh delay 4 4 read-write 0 15 TRAS Self refresh time 8 4 read-write 0 15 TRC Row cycle delay 12 4 read-write 0 15 TWR Recovery delay 16 4 read-write 0 15 TRP Row precharge delay 20 4 read-write 0 15 TRCD Row to column delay 24 4 read-write 0 15 SDCMR SDCMR SDRAM Command Mode register 0x150 0x20 read-write 0x00000000 0xFFFFFFFF MODE Command mode 0 3 read-write MODE Normal Normal Mode 0 ClockConfigurationEnable Clock Configuration Enable 1 PALL PALL (All Bank Precharge) command 2 AutoRefreshCommand Auto-refresh command 3 LoadModeRegister Load Mode Resgier 4 SelfRefreshCommand Self-refresh command 5 PowerDownCommand Power-down command 6 CTB2 Command Target Bank 2 3 1 read-write CTB2 NotIssued Command not issued to SDRAM Bank 1 0 Issued Command issued to SDRAM Bank 1 1 CTB1 Command Target Bank 1 4 1 read-write NRFS Number of Auto-refresh 5 4 read-write 0 15 MRD Mode Register definition 9 13 read-write 0 8191 SDRTR SDRTR SDRAM refresh timer register 0x154 0x20 read-write 0x00000000 0xFFFFFFFF CRE Clear Refresh error flag 0 1 write-only CRE Clear Refresh Error Flag is cleared 1 COUNT Refresh Timer Count 1 13 read-write 0 8191 REIE RES Interrupt Enable 14 1 read-write REIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated if RE = 1 1 SDSR SDSR SDRAM status register 0x158 0x20 read-only 0x00000000 0xFFFFFFFF RE Refresh error flag 0 1 read-only RE NoError No refresh error has been detected 0 Error A refresh error has been detected 1 MODES1 Status Mode for Bank 1 1 2 read-only MODES1 Normal Normal Mode 0 SelfRefresh Self-refresh mode 1 PowerDown Power-down mode 2 MODES2 Status Mode for Bank 2 3 2 read-only BUSY Busy status 5 1 read-only BUSY NotBusy SDRAM Controller is ready to accept a new request 0 Busy SDRAM Controller is not ready to accept a new request 1 FMC_S 0x57000400 GPDMA1 GPDMA register block GPDMA 0x40020000 0x0 0x1000 registers GPDMA1_CH7 GPDMA1 channel7 global interrupt 34 GPDMA1_CH6 GPDMA1 channel6 global interrupt 33 GPDMA1_CH5 GPDMA1 channel5 global interrupt 32 GPDMA1_CH4 GPDMA1 channel4 global interrupt 31 GPDMA1_CH3 GPDMA1 channel3 global interrupt 30 GPDMA1_CH2 GPDMA1 channel2 global interrupt 29 GPDMA1_CH1 GPDMA1 channel1 global interrupt 28 GPDMA1_CH0 GPDMA1 channel0 global interrupt 27 SECCFGR SECCFGR GPDMA secure configuration register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF 8 0x1 0-7 SEC%s secure state of channel x 0 1 read-write PRIVCFGR PRIVCFGR GPDMA privileged configuration register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF 8 0x1 0-7 PRIV%s privileged state of channel x 0 1 read-write PRIV0 Unprivileged Channel is unprivileged 0 Privileged Channel is privileged 1 RCFGLOCKR RCFGLOCKR GPDMA configuration lock register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF 8 0x1 0-7 LOCK%s lock the configuration of GPDMA_SECCFGR. 0 1 read-write MISR MISR GPDMA nonsecure masked interrupt status register 0xC 0x20 read-only 0x00000000 0xFFFFFFFF 8 0x1 0-7 MIS%s masked interrupt status of channel x 0 1 read-only MIS0R NoTrigger No interrupt has occurred on channel 0 Trigger An interrupt has occurred on channel 1 SMISR SMISR GPDMA secure masked interrupt status register 0x10 0x20 read-only 0x00000000 0xFFFFFFFF 8 0x1 0-7 MIS%s masked interrupt status of the secure channel x 0 1 read-only 6 0x80 0-5 CH%s Channel cluster 0x50 LBAR C0LBAR GPDMA channel 0 linked-list base address register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write 0 65535 FCR C0FCR GPDMA channel 0 flag clear register 0xC 0x20 write-only 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only TCFW Clear Clear flag 1 HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only SR C0SR GPDMA channel 0 status register 0x10 0x20 read-only 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only IDLEFR NoTrigger Event not triggered 0 Trigger Event triggered 1 TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only 0 255 CR C0CR GPDMA channel 0 control register 0x14 0x20 read-write 0x00000000 0xFFFFFFFF EN enable 0 1 read-write EN Disabled Channel disabled 0 Enabled Channel enabled 1 RESET reset 1 1 write-only RESETW Reset Reset channel 1 SUSP suspend 2 1 read-write SUSP NotSuspended Channel operation not suspended 0 Suspended Channel operation suspended 1 TCIE transfer complete interrupt enable 8 1 read-write TCIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LSM FullLinkedList Channel executed for full linked list 0 Once Channel executed once for current linked list 1 LAP linked-list allocated port 17 1 read-write LAP Port0 Port 0 (AHB) allocated 0 Port1 Port 1 (AHB) allocated 1 PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write PRIO LowPrioLowWeight Low priority, low weight 0 LowPrioMidWeight Low priority, mid weight 1 LowPrioHighWeight Low priority, high weight 2 HighPrio High priority 3 TR1 C0TR1 GPDMA channel 0 transfer register 1 0x40 0x20 read-write 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SDW_LOG2R read Byte Byte 0 HalfWord Half-word (2 bytes) 1 Word Word (4 bytes) 2 Error User setting error 3 SDW_LOG2W write Byte Byte 0 HalfWord Half-word (2 bytes) 1 Word Word (4 bytes) 2 SINC source incrementing burst 3 1 read-write SINC FixedBurst Fixed burst 0 Contiguous Contiguously incremented burst 1 SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write 0 63 PAM padding/alignment mode 11 2 read-write 0 3 SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SBX NotExchanged No byte-based exchanged within word 0 Exchanged The two consecutive (post PAM) bytes are exchanged in each destination half-word 1 SAP source allocated port 14 1 read-write SAP Port0 Port 0 (AHB) allocated 0 Port1 Port 1 (AHB) allocated 1 SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write read write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write 0 63 DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DHX NotExchanged No halfword-based exchange within word 0 Exchanged The two consecutive (post PAM) half-words are exchanged in each destination word 1 DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write TR2 C0TR2 GPDMA channel 0 transfer register 2 0x44 0x20 read-write 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write REQSEL ADC1_DMA adc1_dma selected 0 DAC1_CH1_DMA dac1_ch1_dma selected 2 DAC1_CH2_DMA dac1_ch2_dma selected 3 TIM6_UPD_DMA tim6_upd_dma selected 4 TIM7_UPD_DMA tim7_upd_dma selected 5 SPI1_RX_DMA spi1_rx_dma selected 6 SPI1_TX_DMA spi1_tx_dma selected 7 SPI2_RX_DMA spi2_rx_dma selected 8 SPI2_TX_DMA spi2_tx_dma selected 9 SPI3_RX_DMA spi3_rx_dma selected 10 SPI3_TX_DMA spi3_tx_dma selected 11 I2C1_RX_DMA i2c1_rx_dma selected 12 I2C1_TX_DMA i2c1_tx_dma selected 13 I2C2_RX_DMA i2c2_rx_dma selected 15 I2C2_TX_DMA i2c2_tx_dma selected 16 I2C3_RX_DMA i2c3_rx_dma selected 18 I2C3_TX_DMA i2c3_tx_dma selected 19 USART1_RX_DMA usart1_rx_dma selected 21 USART1_TX_DMA usart1_tx_dma selected 22 USART2_RX_DMA usart2_rx_dma selected 23 USART2_TX_DMA usart2_tx_dma selected 24 USART3_RX_DMA usart3_rx_dma selected 25 USART3_TX_DMA usart3_tx_dma selected 26 UART4_RX_DMA uart4_rx_dma selected 27 UART4_TX_DMA uart4_tx_dma selected 28 UART5_RX_DMA uart5_rx_dma selected 29 UART5_TX_DMA uart5_tx_dma selected 30 USART6_RX_DMA usart6_rx_dma selected 31 USART6_TX_DMA usart6_tx_dma selected 32 UART7_RX_DMA uart7_rx_dma selected 33 UART7_TX_DMA uart7_tx_dma selected 34 UART8_RX_DMA uart8_rx_dma selected 35 UART8_TX_DMA uart8_tx_dma selected 36 UART9_RX_DMA uart9_rx_dma selected 37 UART9_TX_DMA uart9_tx_dma selected 38 UART10_RX_DMA uart10_rx_dma selected 39 UART10_TX_DMA uart10_tx_dma selected 40 UART11_RX_DMA uart11_rx_dma selected 41 UART11_TX_DMA uart11_tx_dma selected 42 UART12_RX_DMA uart12_rx_dma selected 43 UART12_TX_DMA uart12_tx_dma selected 44 LPUART1_RX_DMA lpuart1_rx_dma selected 45 LPUART1_TX_DMA lpuart1_tx_dma selected 46 SPI4_RX_DMA spi4_rx_dma selected 47 SPI4_TX_DMA spi4_tx_dma selected 48 SPI5_RX_DMA spi5_rx_dma selected 49 SPI5_TX_DMA spi5_tx_dma selected 50 SPI6_RX_DMA spi6_rx_dma selected 51 SPI6_TX_DMA spi6_tx_dma selected 52 SAI1_A_DMA sai1_a_dma selected 53 SAI1_B_DMA sai1_b_dma selected 54 SAI2_A_DMA sai2_a_dma selected 55 SAI2_B_DMA sai2_b_dma selected 56 OSPI1_DMA ospi1_dma selected 57 TIM1_CC1_DMA tim1_cc1_dma selected 58 TIM1_CC2_DMA tim1_cc2_dma selected 59 TIM1_CC3_DMA tim1_cc3_dma selected 60 TIM1_CC4_DMA tim1_cc4_dma selected 61 TIM1_UPD_DMA tim1_upd_dma selected 62 TIM1_TRG_DMA tim1_trg_dma selected 63 TIM1_COM_DMA tim1_com_dma selected 64 TIM8_CC1_DMA tim8_cc1_dma selected 65 TIM8_CC2_DMA tim8_cc2_dma selected 66 TIM8_CC3_DMA tim8_cc3_dma selected 67 TIM8_CC4_DMA tim8_cc4_dma selected 68 TIM8_UPD_DMA tim8_upd_dma selected 69 TIM8_TIG_DMA tim8_tig_dma selected 70 TIM8_COM_DMA tim8_com_dma selected 71 TIM2_CC1_DMA tim2_cc1_dma selected 72 TIM2_CC2_DMA tim2_cc2_dma selected 73 TIM2_CC3_DMA tim2_cc3_dma selected 74 TIM2_CC4_DMA tim2_cc4_dma selected 75 TIM2_UPD_DMA tim2_upd_dma selected 76 TIM3_CC1_DMA tim3_cc1_dma selected 77 TIM3_CC2_DMA tim3_cc2_dma selected 78 TIM3_CC3_DMA tim3_cc3_dma selected 79 TIM3_CC4_DMA tim3_cc4_dma selected 80 TIM3_UPD_DMA tim3_upd_dma selected 81 TIM3_TRG_DMA tim3_trg_dma selected 82 TIM4_CC1_DMA tim4_cc1_dma selected 83 TIM4_CC2_DMA tim4_cc2_dma selected 84 TIM4_CC3_DMA tim4_cc3_dma selected 85 TIM4_CC4_DMA tim4_cc4_dma selected 86 TIM4_UPD_DMA tim4_upd_dma selected 87 TIM5_CC1_DMA tim5_cc1_dma selected 88 TIM5_CC2_DMA tim5_cc2_dma selected 89 TIM5_CC3_DMA tim5_cc3_dma selected 90 TIM5_CC4_DMA tim5_cc4_dma selected 91 TIM5_UPD_DMA tim5_upd_dma selected 92 TIM5_TRG_DMA tim5_trg_dma selected 93 TIM15_CC1_DMA tim15_cc1_dma selected 94 TIM15_UPD_DMA tim15_upd_dma selected 95 TIM15_TRG_DMA tim15_trg_dma selected 96 TIM15_COM_DMA tim15_com_dma selected 97 TIM16_CC1_DMA tim16_cc1_dma selected 98 TIM16_UPD_DMA tim16_upd_dma selected 99 TIM17_CC1_DMA tim17_cc1_dma selected 100 TIM17_UPD_DMA tim17_upd_dma selected 101 LPTIM1_IC1_DMA lptim1_ic1_dma selected 102 LPTIM1_IC2_DMA lptim1_ic2_dma selected 103 LPTIM1_UE_DMA lptim1_ue_dma selected 104 LPTIM2_IC1_DMA lptim2_ic1_dma selected 105 LPTIM2_IC2_DMA lptim2_ic2_dma selected 106 LPTIM2_UE_DMA lptim2_ue_dma selected 107 DCMI_PSSI_DMA dcmi_dma or pssi_dma(1) selected 108 AES_OUT_DMA aes_out_dma selected 109 AES_IN_DMA aes_in_dma selected 110 HASH_IN_DMA hash_in_dma selected 111 UCPD1_RX_DMA ucpd1_rx_dma selected 112 UCPD1_TX_DMA ucpd1_tx_dma selected 113 CORDIC_READ_DMA cordic_read_dma selected 114 CORDIC_WRITE_DMA cordic_write_dma selected 115 FMAC_READ_DMA fmac_read_dma selected 116 FMAC_WRITE_DMA fmac_write_dma selected 117 SAES_OUT_DMA saes_out_dma selected 118 SAES_IN_DMA saes_in_dma selected 119 I3C1_RX_DMA i3c1_rx_dma selected 120 I3C1_TX_DMA i3c1_tx_dma selected 121 I3C1_TC_DMA i3c1_tc_dma selected 122 I3C1_RS_DMA i3c1_rs_dma selected 123 I2C4_RX_DMA i2c4_rx_dma selected 124 I2C4_TX_DMA i2c4_tx_dma selected 125 LPTIM3_IC1_DMA lptim3_ic1_dma selected 127 LPTIM3_IC2_DMA lptim3_ic2_dma selected 128 LPTIM3_UE_DMA lptim3_ue_dma selected 129 LPTIM5_IC1_DMA lptim5_ic1_dma selected 130 LPTIM5_IC2_DMA lptim5_ic2_dma selected 131 LPTIM5_UE_DMA lptim5_ue_dma selected 132 LPTIM6_IC1_DMA lptim6_ic1_dma selected 133 LPTIM6_IC2_DMA lptim6_ic2_dma selected 134 LPTIM6_UE_DMA lptim6_ue_dma selected 135 I3C2_RX i3c2_rx selected 136 I3C2_TX i3c2_tx selected 137 I3C2_TC i3c2_tc selected 138 I3C2_RS i3c2_rs selected 139 SWREQ software request 9 1 read-write SWREQ Hardware No software request. The selected hardware request REQSEL[7:0] is taken into account 0 Software Software request for memory-to-memory transfer 1 DREQ destination hardware request 10 1 read-write DREQ Source Selected hardware request driven by a source peripheral 0 Destination Selected hardware request driven by a destination peripheral 1 BREQ Block hardware request 11 1 read-write BREQ Burst The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level 0 Block The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level 1 PFREQ Hardware request in peripheral flow control mode 12 1 read-write PFREQ GpdmaControlMode The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode 0 PeripheralControlMode The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. 1 TRIGM trigger mode 14 2 read-write TRIGM BlockLevel At block level: the first burst read of each block transfer is conditioned by one hit trigger 0 LinkLevel At link level: a LLI link transfer is conditioned by one hit trigger 2 ProgrammedBurstLevel At programmed burst level: programmed burst read is conditioned by one hit trigger. 3 TRIGSEL trigger event input selection 16 6 read-write TRIGSEL EXTI0 exti0 is trigger input 0 EXTI1 exti1 is trigger input 1 EXTI2 exti2 is trigger input 2 EXTI3 exti3 is trigger input 3 EXTI4 exti4 is trigger input 4 EXTI5 exti5 is trigger input 5 EXTI6 exti6 is trigger input 6 EXTI7 exti7 is trigger input 7 TAMP_TRG1 tamp_trg1 is trigger input 8 TAMP_TRG2 tamp_trg2 is trigger input 9 LPTIM1_CH1 lptim1_ch1 is trigger input 11 LPTIM1_CH2 lptim1_ch2 is trigger input 12 LPTIM2_CH1 lptim2_ch1 is trigger input 13 LPTIM2_CH2 lptim2_ch2 is trigger input 14 RTC_ALRA_TRG rtc_alra_trg is trigger input 15 RTC_ALRB_TRG rtc_alrb_trg is trigger input 16 RTC_WUT_TRG rtc_wut_trg is trigger input 17 GPDMA1_CH0_TC gpdma1_ch0_tc is trigger input 18 GPDMA1_CH1_TC gpdma1_ch1_tc is trigger input 19 GPDMA1_CH2_TC gpdma1_ch2_tc is trigger input 20 GPDMA1_CH3_TC gpdma1_ch3_tc is trigger input 21 GPDMA1_CH4_TC gpdma1_ch4_tc is trigger input 22 GPDMA1_CH5_TC gpdma1_ch5_tc is trigger input 23 GPDMA1_CH6_TC gpdma1_ch6_tc is trigger input 24 GPDMA1_CH7_TC gpdma1_ch7_tc is trigger input 25 GPDMA2_CH0_TC gpdma2_ch0_tc is trigger input 26 GPDMA2_CH1_TC gpdma2_ch1_tc is trigger input 27 GPDMA2_CH2_TC gpdma2_ch2_tc is trigger input 28 GPDMA2_CH3_TC gpdma2_ch3_tc is trigger input 29 GPDMA2_CH4_TC gpdma2_ch4_tc is trigger input 30 GPDMA2_CH5_TC gpdma2_ch5_tc is trigger input 31 GPDMA2_CH6_TC gpdma2_ch6_tc is trigger input 32 GPDMA2_CH7_TC gpdma2_ch7_tc is trigger input 33 TIM2_TRG0 tim2_trgo is trigger input 34 COMP1_OUT comp1_out is trigger input 44 TRIGPOL trigger event polarity 24 2 read-write TRIGPOL NoTrigger No trigger 0 RisingEdge Trigger on rising edge 1 FallingEdge Trigger on falling edge 2 TCEM transfer complete event mode 30 2 read-write TCEM BlockLevel At block level: the complete (and the half) transfer event is generated at the (respectively half of the) end of a block 0 LliLevel At LLI level: the complete transfer event is generated at the end of the LLI transfer. The half transfer event is generated at the half of the LLI data transfer 2 ChannelLevel At channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI 3 BR1 C0BR1 GPDMA channel 0 block register 1 0x48 0x20 read-write 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write 0 65535 SAR C0SAR GPDMA channel 0 source address register 0x4C 0x20 read-write 0x00000000 0xFFFFFFFF SA source address 0 32 read-write 0 4294967295 DAR C0DAR GPDMA channel 0 destination address register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write 0 4294967295 LLR C0LLR GPDMA channel 0 linked-list address register 0x7C 0x20 read-write 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write 0 16383 ULL Update GPDMA_CxLLR register from memory 16 1 read-write ULL NoUpdate No CxLLR update 0 Update CxLLR updated from memory during link transfer 1 UDA Update GPDMA_CxDAR register from memory 27 1 read-write UDA NoUpdate No CxDAR update 0 Update CxDAR updated from memory during link transfer 1 USA update GPDMA_CxSAR from memory 28 1 read-write USA NoUpdate No CxSAR update 0 Update CxSAR updated from memory during link transfer 1 UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UB1 NoUpdate No CxBR1 update 0 Update CxBR1 updated from memory during link transfer 1 UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT2 NoUpdate No CxTR2 update 0 Update CxTR2 updated from memory during link transfer 1 UT1 Update GPDMA_CxTR1 from memory 31 1 read-write UT1 NoUpdate No CxTR1 update 0 Update CxTR1 updated from memory during link transfer 1 2 0x80 6-7 CH2D%s 2D-addressing channel cluster 0x350 LBAR C6LBAR GPDMA channel 6 linked-list base address register 0x0 FCR C6FCR GPDMA channel 6 flag clear register 0xC SR C6SR GPDMA channel 6 status register 0x10 CR C6CR GPDMA channel 6 control register 0x14 TR1 C6TR1 GPDMA channel 6 transfer register 1 0x40 TR2 C6TR2 GPDMA channel 6 transfer register 2 0x44 BR1 C6BR1 GPDMA channel 6 alternate block register 1 0x48 0x20 read-write 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write BRC Block repeat counter 16 11 read-write 0 2047 SDEC source address decrement 28 1 read-write SDEC Increment Source address incremented 0 Decrement Source address decremented 1 DDEC destination address decrement 29 1 read-write DDEC Increment Destination address incremented 0 Decrement Destination address decremented 1 BRSDEC Block repeat source address decrement 30 1 read-write BRSDEC Increment Block repeat source address incremented 0 Decrement Block repeat source address decremented 1 BRDDEC Block repeat destination address decrement 31 1 read-write BRDDEC Increment Block repeat destination address incremented 0 Decrement Block repeat destination address decremented 1 SAR C6SAR GPDMA channel 6 source address register 0x4C DAR C6DAR GPDMA channel 6 destination address register 0x50 TR3 C6TR3 GPDMA channel 6 transfer register 3 0x54 0x20 read-write 0x00000000 0xFFFFFFFF SAO source address offset increment 0 13 read-write 0 4095 DAO destination address offset increment 16 13 read-write 0 4095 BR2 C6BR2 GPDMA channel 6 block register 2 0x58 0x20 read-write 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset 0 16 read-write 0 65535 BRDAO Block repeated destination address offset 16 16 read-write 0 65535 LLR C6LLR GPDMA channel 6 alternate linked-list address register 0x7C 0x20 read-write 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UB2 Update GPDMA_CxBR2 from memory 25 1 read-write UB2 NoUpdate No CxBR2 update 0 Update CxBR2 updated from memory during link transfer 1 UT3 Update GPDMA_CxTR3 from memory 26 1 read-write UT3 NoUpdate No CxTR3 update 0 Update CxTR3 updated from memory during link transfer 1 UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write GPDMA1_S 0x50020000 GPDMA2 0x40021000 GPDMA2_CH7 GPDMA2 channel7 global interrupt 97 GPDMA2_CH6 GPDMA2 channel6 global interrupt 96 GPDMA2_CH5 GPDMA2 channel5 global interrupt 95 GPDMA2_CH4 GPDMA2 channel4 global interrupt 94 GPDMA2_CH3 GPDMA2 channe3 global interrupt 93 GPDMA2_CH2 GPDMA2 channel2 global interrupt 92 GPDMA2_CH1 GPDMA2 channel1 global interrupt 91 GPDMA2_CH0 GPDMA2 channel0 global interrupt 90 GPDMA2_S 0x50021000 GPIOA GPIOA address block description GPIO 0x42020000 0x0 0x34 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00FFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 0xFFFF0000 16 0x1 0-15 ID%s Port input data pin %s 0 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x1 0-15 OD%s Port output data pin %s 0 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 0xFFFFFFFF 16 0x1 0-15 BS%s Port x set pin %s 0 1 write-only BitSet Set Sets the corresponding ODx bit 1 16 0x1 0-15 BR%s Port x reset pin %s 16 1 write-only BitReset Reset Resets the corresponding ODx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK Lock key 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF 8 0x4 0-7 AFSEL%s Alternate function selection for port x I/O pin y 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF 8 0x4 8-15 AFSEL%s Alternate function selection for port x I/O pin y 0 4 read-write BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 0xFFFFFFFF 16 0x1 0-15 BR%s Port x reset pin %s 0 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x1 0-15 HSLV%s Port x high-speed low-voltage configuration 0 1 read-write HighSpeedLowVoltage Disabled I/O speed optimization disabled 0 Enabled I/O speed optimization enabled 1 SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 read-write 0x00000FFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y 0 1 read-write SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 GPIOA_S 0x52020000 GPIOB GPIOB address block description GPIO 0x42020400 0x0 0x34 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00FFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 read-write 0x00000FFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y 0 1 read-write GPIOB_S 0x52020400 GPIOC GPIOC address block description GPIO 0x42020800 0x0 0x34 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00FFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 read-write 0x00000FFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y 0 1 read-write GPIOC_S 0x52020800 GPIOD GPIOD address block description GPIO 0x42020C00 0x0 0x34 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00FFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 read-write 0x00000FFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y 0 1 read-write GPIOD_S 0x52020C00 GPIOE GPIOE address block description GPIO 0x42021000 0x0 0x34 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00FFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 read-write 0x00000FFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y 0 1 read-write GPIOE_S 0x52021000 GPIOF GPIOF address block description GPIO 0x42021400 0x0 0x34 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00FFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 read-write 0x00000FFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y 0 1 read-write GPIOF_S 0x52021400 GPIOG GPIOG address block description GPIO 0x42021800 0x0 0x34 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00FFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 read-write 0x00000FFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y 0 1 read-write GPIOG_S 0x52021800 GPIOH GPIOH address block description GPIO 0x42021C00 0x0 0x34 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00FFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 read-write 0x00000FFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y 0 1 read-write GPIOH_S 0x52021C00 GPIOI GPIOI address block description GPIO 0x000001A0 0x0 0x34 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00FFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 read-write 0x00000FFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin of Port x secure bit enable y 0 1 read-write GPIOI_S 0x100001A0 GTZC1_TZIC GTZC1_MPCBBz register block GTZC 0x40032400 0x0 0x30 registers GTZC GTZC global interrupt 8 IER1 IER1 GTZC1 TZIC interrupt enable register 1 GTZC1_TZSC_CR 0x0 0x20 read-write 0x00000000 0xFFFFFFFF TIM2IE illegal access interrupt enable for TIM2 0 1 read-write TIM3IE illegal access interrupt enable for TIM3 1 1 read-write TIM4IE illegal access interrupt enable for TIM4 2 1 read-write TIM5IE illegal access interrupt enable for TIM5 3 1 read-write TIM6IE illegal access interrupt enable for TIM6 4 1 read-write TIM7IE illegal access interrupt enable for TIM7 5 1 read-write TIM12IE illegal access interrupt enable for TIM12 6 1 read-write WWDGIE illegal access interrupt enable for WWDG 9 1 read-write IWDGIE illegal access interrupt enable for IWDG 10 1 read-write SPI2IE illegal access interrupt enable for SPI2 11 1 read-write SPI3IE illegal access interrupt enable for SPI3 12 1 read-write USART2IE illegal access interrupt enable for USART2 13 1 read-write USART3IE illegal access interrupt enable for USART3 14 1 read-write UART4IE illegal access interrupt enable for UART4 15 1 read-write UART5IE illegal access interrupt enable for UART5 16 1 read-write I2C1IE illegal access interrupt enable for I2C1 17 1 read-write I2C2IE illegal access interrupt enable for I2C2 18 1 read-write I3C1IE illegal access interrupt enable for I3C1 19 1 read-write CRSIE illegal access interrupt enable for CRS 20 1 read-write USART6IE illegal access interrupt enable for USART6 21 1 read-write USART10IE illegal access interrupt enable for USART10 22 1 read-write USART11IE illegal access interrupt enable for USART11 23 1 read-write HDMICECIE illegal access interrupt enable for HDMICEC 24 1 read-write DAC1IE illegal access interrupt enable for DAC1 25 1 read-write UART7IE illegal access interrupt enable for UART7 26 1 read-write UART8IE illegal access interrupt enable for UART8 27 1 read-write UART9IE illegal access interrupt enable for UART9 28 1 read-write UART12IE illegal access interrupt enable for UART12 29 1 read-write DTSIE illegal access interrupt enable for DTS 30 1 read-write LPTIM2IE illegal access interrupt enable for LPTIM2 31 1 read-write IER2 IER2 GTZC1 TZIC interrupt enable register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF FDCAN1IE illegal access interrupt enable for FDCAN1 0 1 read-write FDCAN2IE illegal access interrupt enable for FDCAN2 1 1 read-write UCPDIE illegal access interrupt enable for UCPD 2 1 read-write TIM1IE illegal access interrupt enable for TIM1 8 1 read-write SPI1IE illegal access interrupt enable for SPI1 9 1 read-write TIM8IE illegal access interrupt enable for TIM8 10 1 read-write USART1IE illegal access interrupt enable for USART1 11 1 read-write TIM15IE illegal access interrupt enable for TIM15 12 1 read-write SPI4IE illegal access interrupt enable for SPI4 15 1 read-write SPI6IE illegal access interrupt enable for SPI6 16 1 read-write SAI1IE illegal access interrupt enable for SAI1 17 1 read-write SAI2IE illegal access interrupt enable for SAI2 18 1 read-write USBIE illegal access interrupt enable for USB 19 1 read-write LPUART1IE illegal access interrupt enable for LPUART 25 1 read-write I2C3IE illegal access interrupt enable for I2C3 26 1 read-write LPTIM1IE illegal access interrupt enable for LPTIM1 28 1 read-write LPTIM3IE illegal access interrupt enable for LPTIM3 29 1 read-write LPTIM4IE illegal access interrupt enable for LPTIM4 30 1 read-write LPTIM5IE illegal access interrupt enable for LPTIM5 31 1 read-write IER3 IER3 GTZC1 TZIC interrupt enable register 3 0x8 0x20 read-write 0x00000000 0xFFFFFFFF LPTIM6IE illegal access interrupt enable for LPTIM6 0 1 read-write VREFBUFIE illegal access interrupt enable for VREFBUF 1 1 read-write I3C2IE illegal access interrupt enable for I3C2 2 1 read-write CRCIE illegal access interrupt enable for CRC 8 1 read-write CORDICIE illegal access interrupt enable for CORDIC 9 1 read-write FMACIE illegal access interrupt enable for FMAC 10 1 read-write ETHIE illegal access interrupt enable for register of ETH 11 1 read-write ICACHEIE illegal access interrupt enable for ICACHE 12 1 read-write DCACHEIE illegal access interrupt enable for DCACHE 13 1 read-write ADC12IE illegal access interrupt enable for ADC1 and ADC2 14 1 read-write DCMIIE illegal access interrupt enable for DCMI 15 1 read-write AESIE illegal access interrupt enable for AES 16 1 read-write HASHIE illegal access interrupt enable for HASH 17 1 read-write RNGIE illegal access interrupt enable for RNG 18 1 read-write SAESIE illegal access interrupt enable for SAES 19 1 read-write PKAIE illegal access interrupt enable for PKA 20 1 read-write SDMMC1IE illegal access interrupt enable for SDMMC1 21 1 read-write FMCIE illegal access interrupt enable for FMC 23 1 read-write OCTOSPI1IE illegal access interrupt enable for OCTOSPI1 24 1 read-write RAMCFGIE illegal access interrupt enable for RAMSCFG 26 1 read-write IER4 IER4 GTZC1 TZIC interrupt enable register 4 0xC 0x20 read-write 0x00000000 0xFFFFFFFF GPDMA1IE illegal access interrupt enable for GPDMA1 0 1 read-write GPDMA2IE illegal access interrupt enable for GPDMA2 1 1 read-write FLASH_REGIE illegal access interrupt enable for FLASH registers 2 1 read-write FLASHIE illegal access interrupt enable for FLASH memory 3 1 read-write OTFDEC1IE illegal access interrupt enable for OTFDEC1 4 1 read-write SBSIE illegal access interrupt enable for SBS 6 1 read-write RTCIE illegal access interrupt enable for RTC 7 1 read-write TAMPIE illegal access interrupt enable for TAMP 8 1 read-write PWRIE illegal access interrupt enable for PWR 9 1 read-write RCCIE illegal access interrupt enable for RCC 10 1 read-write EXTIIE illegal access interrupt enable for EXTI 11 1 read-write TZSC1IE illegal access interrupt enable for GTZC1 TZSC registers 16 1 read-write TZIC1IE illegal access interrupt enable for GTZC1 TZIC registers 17 1 read-write OCTOSPI1_MEMIE illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank 18 1 read-write FMC_MEMIE illegal access interrupt enable for MPCWM2 (FMC_NOR bank), MPCWM3 (FMC_NAND bank and FMC_SDRAM bank 1), and MPCWM4 (FMC_SDRAM bank 2) 19 1 read-write BKPSRAMIE illegal access interrupt enable for MPCWM4 (BKPSRAM) memory bank 20 1 read-write SRAM1IE illegal access interrupt enable for SRAM1 24 1 read-write MPCBB1_REGIE illegal access interrupt enable for MPCBB1 registers 25 1 read-write SRAM2IE illegal access interrupt enable for SRAM2 26 1 read-write MPCBB2_REGIE illegal access interrupt enable for MPCBB2 registers 27 1 read-write SRAM3IE illegal access interrupt enable for SRAM3 28 1 read-write MPCBB3_REGIE illegal access interrupt enable for MPCBB3 registers 29 1 read-write SR1 SR1 GTZC1 TZIC status register 1 GTZC1_TZSC_SECCFGR1 0x10 0x20 read-only 0x00000000 0xFFFFFFFF TIM2F illegal access flag for TIM2 0 1 read-only TIM3F illegal access flag for TIM3 1 1 read-only TIM4F illegal access flag for TIM4 2 1 read-only TIM5F illegal access flag for TIM5 3 1 read-only TIM6F illegal access flag for TIM6 4 1 read-only TIM7F illegal access flag for TIM7 5 1 read-only TIM12F illegal access flag for TIM12 6 1 read-only WWDGF illegal access flag for WWDG 9 1 read-only IWDGF illegal access flag for IWDG 10 1 read-only SPI2F illegal access flag for SPI2 11 1 read-only SPI3F illegal access flag for SPI3 12 1 read-only USART2F illegal access flag for USART2 13 1 read-only USART3F illegal access flag for USART3 14 1 read-only UART4F illegal access flag for UART4 15 1 read-only UART5F illegal access flag for UART5 16 1 read-only I2C1F illegal access flag for I2C1 17 1 read-only I2C2F illegal access flag for I2C2 18 1 read-only I3C1F illegal access flag for I3C1 19 1 read-only CRSF illegal access flag for CRS 20 1 read-only USART6F illegal access flag for USART6 21 1 read-only USART10F illegal access flag for USART10 22 1 read-only USART11F illegal access flag for USART11 23 1 read-only HDMICECF illegal access flag for HDMICEC 24 1 read-only DAC1F illegal access flag for DAC1 25 1 read-only UART7F illegal access flag for UART7 26 1 read-only UART8F illegal access flag for UART8 27 1 read-only UART9F illegal access flag for UART9 28 1 read-only UART12F illegal access flag for UART12 29 1 read-only DTSF illegal access flag for DTS 30 1 read-only LPTIM2F illegal access flag for LPTIM2 31 1 read-only SR2 SR2 GTZC1 TZIC status register 2 GTZC1_TZSC_SECCFGR2 0x14 0x20 read-only 0x00000000 0xFFFFFFFF FDCAN1F illegal access flag for FDCAN1 0 1 read-only FDCAN2F illegal access flag for FDCAN2 1 1 read-only UCPDF illegal access flag for UCPD 2 1 read-only TIM1F illegal access flag for TIM1 8 1 read-only SPI1F illegal access flag for SPI1 9 1 read-only TIM8F illegal access flag for TIM8 10 1 read-only USART1F illegal access flag for USART1 11 1 read-only TIM15F illegal access flag for TIM15 12 1 read-only SPI4F illegal access flag for SPI4 15 1 read-only SPI6F illegal access flag for SPI6 16 1 read-only SAI1F illegal access flag for SAI1 17 1 read-only SAI2F illegal access flag for SAI2 18 1 read-only USBF illegal access flag for USB 19 1 read-only LPUART1F illegal access flag for LPUART 25 1 read-only I2C3F illegal access flag for I2C3 26 1 read-only LPTIM1F illegal access flag for LPTIM1 28 1 read-only LPTIM3F illegal access flag for LPTIM3 29 1 read-only LPTIM4F illegal access flag for LPTIM4 30 1 read-only LPTIM5F illegal access flag for LPTIM5 31 1 read-only SR3 SR3 GTZC1 TZIC status register 3 GTZC1_TZSC_SECCFGR3 0x18 0x20 read-only 0x00000000 0xFFFFFFFF LPTIM6F illegal access flag for LPTIM6 0 1 read-only VREFBUFF illegal access flag for VREFBUF 1 1 read-only I3C2F illegal access flag for I3C2 2 1 read-only CRCF illegal access flag for CRC 8 1 read-only CORDICF illegal access flag for CORDIC 9 1 read-only FMACF illegal access flag for FMAC 10 1 read-only ETHF illegal access flag for register of ETH 11 1 read-only ICACHEF illegal access flag for ICACHE 12 1 read-only DCACHEF illegal access flag for DCACHE 13 1 read-only ADC12F illegal access flag for ADC1 and ADC2 14 1 read-only DCMIF illegal access flag for DCMI 15 1 read-only AESF illegal access flag for AES 16 1 read-only HASHF illegal access flag for HASH 17 1 read-only RNGF illegal access flag for RNG 18 1 read-only SAESF illegal access flag for SAES 19 1 read-only PKAF illegal access flag for PKA 20 1 read-only SDMMC1F illegal access flag for SDMMC1 21 1 read-only FMCF illegal access flag for FMC 23 1 read-only OCTOSPI1F illegal access flag for OCTOSPI1 24 1 read-only RAMCFGF illegal access flag for RAMSCFG 26 1 read-only SR4 SR4 GTZC1 TZIC status register 4 0x1C 0x20 read-only 0x00000000 0xFFFFFFFF GPDMA1F illegal access flag for GPDMA1 0 1 read-only GPDMA2F illegal access flag for GPDMA2 1 1 read-only FLASH_REGF illegal access flag for FLASH registers 2 1 read-only FLASHF illegal access flag for FLASH memory 3 1 read-only OTFDEC1F illegal access flag for OTFDEC1 4 1 read-only SBSF illegal access flag for SBS 6 1 read-only RTCF illegal access flag for RTC 7 1 read-only TAMPF illegal access flag for TAMP 8 1 read-only PWRF illegal access flag for PWR 9 1 read-only RCCF illegal access flag for RCC 10 1 read-only EXTIF illegal access flag for EXTI 11 1 read-only TZSC1F illegal access flag for GTZC1 TZSC registers 16 1 read-only TZIC1F illegal access flag for GTZC1 TZIC registers 17 1 read-only OCTOSPI1_MEMF illegal access flag for MPCWM1 (OCTOSPI1) memory bank 18 1 read-only FMC_MEMF illegal access flag for MPCWM2 (FMC_NOR bank), MPCWM3 (FMC_NAND bank and FMC_SDRAM bank 1), and MPCWM4 (FMC_SDRAM bank 2) 19 1 read-only BKPSRAMF illegal access flag for MPCWM4 (BKPSRAM) memory bank 20 1 read-only SRAM1F illegal access flag for SRAM1 24 1 read-only MPCBB1_REGF illegal access flag for MPCBB1 registers 25 1 read-only SRAM2F illegal access flag for SRAM2 26 1 read-only MPCBB2_REGF illegal access flag for MPCBB2 registers 27 1 read-only SRAM3F illegal access flag for SRAM3 28 1 read-only MPCBB3_REGF illegal access flag for MPCBB3 registers 29 1 read-only FCR1 FCR1 GTZC1 TZIC flag clear register 1 GTZC1_TZSC_PRIVCFGR1 0x20 0x20 write-only 0x00000000 0xFFFFFFFF CTIM2F clear the illegal access flag for TIM2 0 1 write-only CTIM3F clear the illegal access flag for TIM3 1 1 write-only CTIM4F clear the illegal access flag for TIM4 2 1 write-only CTIM5F clear the illegal access flag for TIM5 3 1 write-only CTIM6F clear the illegal access flag for TIM6 4 1 write-only CTIM7F clear the illegal access flag for TIM7 5 1 write-only CTIM12F clear the illegal access flag for TIM12 6 1 write-only CTIM13F clear the illegal access flag for TIM13 7 1 write-only CTIM14F clear the illegal access flag for TIM14 8 1 write-only CWWDGF clear the illegal access flag for WWDG 9 1 write-only CIWDGF clear the illegal access flag for IWDG 10 1 write-only CSPI2F clear the illegal access flag for SPI2 11 1 write-only CSPI3F clear the illegal access flag for SPI3 12 1 write-only CUSART2F clear the illegal access flag for USART2 13 1 write-only CUSART3F clear the illegal access flag for USART3 14 1 write-only CUART4F clear the illegal access flag for UART4 15 1 write-only CUART5F clear the illegal access flag for UART5 16 1 write-only CI2C1F clear the illegal access flag for I2C1 17 1 write-only CI2C2F clear the illegal access flag for I2C2 18 1 write-only CI3C1F clear the illegal access flag for I3C1 19 1 write-only CCRSF clear the illegal access flag for CRS 20 1 write-only CUSART6F clear the illegal access flag for USART6 21 1 write-only CUSART10F clear the illegal access flag for USART10 22 1 write-only CUSART11F clear the illegal access flag for USART11 23 1 write-only CHDMICECF clear the illegal access flag for HDMICEC 24 1 write-only CDAC1F clear the illegal access flag for DAC1 25 1 write-only CUART7F clear the illegal access flag for UART7 26 1 write-only CUART8F clear the illegal access flag for UART8 27 1 write-only CUART9F clear the illegal access flag for UART9 28 1 write-only CUART12F clear the illegal access flag for UART12 29 1 write-only CDTSF clear the illegal access flag for DTS 30 1 write-only CLPTIM2F clear the illegal access flag for LPTIM2 31 1 write-only FCR2 FCR2 GTZC1 TZIC flag clear register 2 GTZC1_TZSC_PRIVCFGR2 0x24 0x20 write-only 0x00000000 0xFFFFFFFF CFDCAN1F clear the illegal access flag for FDCAN1 0 1 write-only CFDCAN2F clear the illegal access flag for FDCAN2 1 1 write-only CUCPDF clear the illegal access flag for UCPD 2 1 write-only CTIM1F clear the illegal access flag for TIM1 8 1 write-only CSPI1F clear the illegal access flag for SPI1 9 1 write-only CTIM8F clear the illegal access flag for TIM8 10 1 write-only CUSART1F clear the illegal access flag for USART1 11 1 write-only CTIM15F clear the illegal access flag for TIM15 12 1 write-only CTIM16F clear the illegal access flag for TIM16 13 1 write-only CTIM17F clear the illegal access flag for TIM17 14 1 write-only CSPI4F clear the illegal access flag for SPI4 15 1 write-only CSPI6F clear the illegal access flag for SPI6 16 1 write-only CSAI1F clear the illegal access flag for SAI1 17 1 write-only CSAI2F clear the illegal access flag for SAI2 18 1 write-only CUSBF clear the illegal access flag for USB 19 1 write-only CSPI5F clear the illegal access flag for SPI5 24 1 write-only CLPUART1F clear the illegal access flag for LPUART 25 1 write-only CI2C3F clear the illegal access flag for I2C3 26 1 write-only CI2C4F clear the illegal access flag for I2C4 27 1 write-only CLPTIM1F clear the illegal access flag for LPTIM1 28 1 write-only CLPTIM3F clear the illegal access flag for LPTIM3 29 1 write-only CLPTIM4F clear the illegal access flag for LPTIM4 30 1 write-only CLPTIM5F clear the illegal access flag for LPTIM5 31 1 write-only FCR3 FCR3 GTZC1 TZIC flag clear register 3 GTZC1_TZSC_PRIVCFGR3 0x28 0x20 write-only 0x00000000 0xFFFFFFFF CLPTIM6F clear illegal access flag for LPTIM6 0 1 write-only CVREFBUFF clear illegal access flag for VREFBUF 1 1 write-only CI3C2F clear illegal access flag for I3C2 2 1 write-only CCRCF clear illegal access flag for CRC 8 1 write-only CCORDICF clear illegal access flag for CORDIC 9 1 write-only CFMACF clear illegal access flag for FMAC 10 1 write-only CETHF clear illegal access flag for register of ETH 11 1 write-only CICACHEF clear illegal access flag for ICACHE 12 1 write-only CDCACHEF clear illegal access flag for DCACHE 13 1 write-only CADC12F clear illegal access flag for ADC1 and ADC2 14 1 write-only CDCMIF clear illegal access flag for DCMI 15 1 write-only CAESF clear illegal access flag for AES 16 1 write-only CHASHF clear illegal access flag for HASH 17 1 write-only CRNGF clear illegal access flag for RNG 18 1 write-only CSAESF clear illegal access flag for SAES 19 1 write-only CPKAF clear illegal access flag for PKA 20 1 write-only CSDMMC1F clear illegal access flag for SDMMC1 21 1 write-only CSDMMC2F clear illegal access flag for SDMMC2 22 1 write-only CFMCF clear illegal access flag for FMC 23 1 write-only COCTOSPI1F clear illegal access flag for OCTOSPI1 24 1 write-only CRAMCFGF clear illegal access flag for RAMSCFG 26 1 write-only FCR4 FCR4 GTZC1 TZIC flag clear register 4 0x2C 0x20 write-only 0x00000000 0xFFFFFFFF CGPDMA1F clear the illegal access flag for GPDMA1 0 1 write-only CGPDMA2F clear the illegal access flag for GPDMA2 1 1 write-only CFLASH_REGF clear the illegal access flag for FLASH registers 2 1 write-only CFLASHF clear the illegal access flag for FLASH memory 3 1 write-only COTFDEC1F clear the illegal access flag for OTFDEC1 4 1 write-only CSBSF clear the illegal access flag for SBS 6 1 write-only CRTCF clear the illegal access flag for RTC 7 1 write-only CTAMPF clear the illegal access flag for TAMP 8 1 write-only CPWRF clear the illegal access flag for PWR 9 1 write-only CRCCF clear the illegal access flag for RCC 10 1 write-only CEXTIF clear the illegal access flag for EXTI 11 1 write-only CTZSC1F clear the illegal access flag for GTZC1 TZSC registers 16 1 write-only CTZIC1F clear the illegal access flag for GTZC1 TZIC registers 17 1 write-only COCTOSPI1_MEMF clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank 18 1 write-only CFMC_MEMF clear the illegal access flag for MPCWM2 (FMC_NOR bank), MPCWM3 (FMC_NAND bank and FMC_SDRAM bank 1), and MPCWM4 (FMC_SDRAM bank 2) 19 1 write-only CBKPSRAMF clear the illegal access flag for MPCWM4 (BKPSRAM) memory bank 20 1 write-only CSRAM1F clear the illegal access flag for SRAM1 24 1 write-only CMPCBB1_REGF clear the illegal access flag for MPCBB1 registers 25 1 write-only CSRAM2F clear the illegal access flag for SRAM2 26 1 write-only CMPCBB2_REGF clear the illegal access flag for MPCBB2 registers 27 1 write-only CSRAM3F clear the illegal access flag for SRAM3 28 1 write-only CMPCBB3_REGF clear the illegal access flag for MPCBB3 registers 29 1 write-only GTZC1_TZIC_S GTZC 0x50032400 GTZC1_TZSC GTZC1_MPCBBz register block GTZC 0x40036400 0x0 0x80 registers CR CR GTZC1 TZSC control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF LCK lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx until next reset 0 1 read-write SECCFGR1 SECCFGR1 GTZC1 TZSC secure configuration register 1 0x10 0x20 read-write 0x00000000 0xFFFFFFFF TIM2SEC secure access mode for TIM2 0 1 read-write TIM3SEC secure access mode for TIM3 1 1 read-write TIM4SEC secure access mode for TIM4 2 1 read-write TIM5SEC secure access mode for TIM5 3 1 read-write TIM6SEC secure access mode for TIM6 4 1 read-write TIM7SEC secure access mode for TIM7 5 1 read-write TIM12SEC secure access mode for TIM12 6 1 read-write WWDGSEC secure access mode for WWDG 9 1 read-write IWDGSEC secure access mode for IWDG 10 1 read-write SPI2SEC secure access mode for SPI2 11 1 read-write SPI3SEC secure access mode for SPI3 12 1 read-write USART2SEC secure access mode for USART2 13 1 read-write USART3SEC secure access mode for USART3 14 1 read-write UART4SEC secure access mode for UART4 15 1 read-write UART5SEC secure access mode for UART5 16 1 read-write I2C1SEC secure access mode for I2C1 17 1 read-write I2C2SEC secure access mode for I2C2 18 1 read-write I3C1SEC secure access mode for I3C1 19 1 read-write CRSSEC secure access mode for CRS 20 1 read-write USART6SEC secure access mode for USART6 21 1 read-write USART10SEC secure access mode for USART10 22 1 read-write USART11SEC secure access mode for USART11 23 1 read-write HDMICECSEC secure access mode for HDMICEC 24 1 read-write DAC1SEC secure access mode for DAC1 25 1 read-write UART7SEC secure access mode for UART7 26 1 read-write UART8SEC secure access mode for UART8 27 1 read-write UART9SEC secure access mode for UART9 28 1 read-write UART12SEC secure access mode for UART12 29 1 read-write DTSSEC secure access mode for DTS 30 1 read-write LPTIM2SEC secure access mode for LPTIM2 31 1 read-write SECCFGR2 SECCFGR2 GTZC1 TZSC secure configuration register 2 0x14 0x20 read-write 0x00000000 0xFFFFFFFF FDCAN1SEC secure access mode for FDCAN1 0 1 read-write FDCAN2SEC secure access mode for FDCAN2 1 1 read-write UCPDSEC secure access mode for UCPD 2 1 read-write TIM1SEC secure access mode for TIM1 8 1 read-write SPI1SEC secure access mode for SPI1 9 1 read-write TIM8SEC secure access mode for TIM8 10 1 read-write USART1SEC secure access mode for USART1 11 1 read-write TIM15SEC secure access mode for TIM15 12 1 read-write SPI4SEC secure access mode for SPI4 15 1 read-write SPI6SEC secure access mode for SPI6 16 1 read-write SAI1SEC secure access mode for SAI1 17 1 read-write SAI2SEC secure access mode for SAI2 18 1 read-write USBSEC secure access mode for USB 19 1 read-write LPUART1SEC secure access mode for LPUART 25 1 read-write I2C3SEC secure access mode for I2C3 26 1 read-write LPTIM1SEC secure access mode for LPTIM1 28 1 read-write LPTIM3SEC secure access mode for LPTIM3 29 1 read-write LPTIM4SEC secure access mode for LPTIM4 30 1 read-write LPTIM5SEC secure access mode for LPTIM5 31 1 read-write SECCFGR3 SECCFGR3 GTZC1 TZSC secure configuration register 3 0x18 0x20 read-write 0x00000000 0xFFFFFFFF LPTIM6SEC secure access mode for LPTIM6 0 1 read-write VREFBUFSEC secure access mode for VREFBUF 1 1 read-write I3C2SEC secure access mode for I3C2 2 1 read-write CRCSEC secure access mode for CRC 8 1 read-write CORDICSEC secure access mode for CORDIC 9 1 read-write FMACSEC secure access mode for FMAC 10 1 read-write ETHSEC secure access mode for register of ETH 11 1 read-write ICACHESEC secure access mode for ICACHE 12 1 read-write DCACHESEC secure access mode for DCACHE 13 1 read-write ADC12SEC secure access mode for ADC1 and ADC2 14 1 read-write DCMISEC secure access mode for DCMI 15 1 read-write AESSEC secure access mode for AES 16 1 read-write HASHSEC secure access mode for HASH 17 1 read-write RNGSEC secure access mode for RNG 18 1 read-write SAESSEC secure access mode for SAES 19 1 read-write PKASEC secure access mode for PKA 20 1 read-write SDMMC1SEC secure access mode for SDMMC1 21 1 read-write FMCSEC secure access mode for FMC 23 1 read-write OCTOSPI1SEC secure access mode for OCTOSPI1 24 1 read-write RAMCFGSEC secure access mode for RAMSCFG 26 1 read-write PRIVCFGR1 PRIVCFGR1 GTZC1 TZSC privilege configuration register 1 0x20 0x20 read-write 0x00000000 0xFFFFFFFF TIM2PRIV privileged access mode for TIM2 0 1 read-write TIM3PRIV privileged access mode for TIM3 1 1 read-write TIM4PRIV privileged access mode for TIM4 2 1 read-write TIM5PRIV privileged access mode for TIM5 3 1 read-write TIM6PRIV privileged access mode for TIM6 4 1 read-write TIM7PRIV privileged access mode for TIM7 5 1 read-write WWDGPRIV privileged access mode for WWDG 9 1 read-write IWDGPRIV privileged access mode for IWDG 10 1 read-write SPI2PRIV privileged access mode for SPI2 11 1 read-write SPI3PRIV privileged access mode for SPI3 12 1 read-write USART2PRIV privileged access mode for USART2 13 1 read-write USART3PRIV privileged access mode for USART3 14 1 read-write UART4PRIV privileged access mode for UART4 15 1 read-write UART5PRIV privileged access mode for UART5 16 1 read-write I2C1PRIV privileged access mode for I2C1 17 1 read-write I2C2PRIV privileged access mode for I2C2 18 1 read-write I3C1PRIV privileged access mode for I3C1 19 1 read-write CRSPRIV privileged access mode for CRS 20 1 read-write USART6PRIV privileged access mode for USART6 21 1 read-write USART10PRIV privileged access mode for USART10 22 1 read-write USART11PRIV privileged access mode for USART11 23 1 read-write HDMICECPRIV privileged access mode for HDMICEC 24 1 read-write DAC1PRIV privileged access mode for DAC1 25 1 read-write UART7PRIV privileged access mode for UART7 26 1 read-write UART8PRIV privileged access mode for UART8 27 1 read-write UART9PRIV privileged access mode for UART9 28 1 read-write UART12PRIV privileged access mode for UART12 29 1 read-write DTSPRIV privileged access mode for DTS 30 1 read-write LPTIM2PRIV privileged access mode for LPTIM2 31 1 read-write PRIVCFGR2 PRIVCFGR2 GTZC1 TZSC privilege configuration register 2 0x24 0x20 read-write 0x00000000 0xFFFFFFFF FDCAN1PRIV privileged access mode for FDCAN1 0 1 read-write FDCAN2PRIV privileged access mode for FDCAN2 1 1 read-write UCPDPRIV privileged access mode for UCPD 2 1 read-write TIM1PRIV privileged access mode for TIM1 8 1 read-write SPI1PRIV privileged access mode for SPI1 9 1 read-write TIM8PRIV privileged access mode for TIM8 10 1 read-write USART1PRIV privileged access mode for USART1 11 1 read-write TIM15PRIV privileged access mode for TIM15 12 1 read-write TIM16PRIV privileged access mode for TIM16 13 1 read-write SPI4PRIV privileged access mode for SPI4 15 1 read-write SPI6PRIV privileged access mode for SPI6 16 1 read-write SAI1PRIV privileged access mode for SAI1 17 1 read-write SAI2PRIV privileged access mode for SAI2 18 1 read-write USBPRIV privileged access mode for USB 19 1 read-write LPUART1PRIV privileged access mode for LPUART 25 1 read-write I2C3PRIV privileged access mode for I2C3 26 1 read-write LPTIM1PRIV privileged access mode for LPTIM1 28 1 read-write LPTIM3PRIV privileged access mode for LPTIM3 29 1 read-write LPTIM4PRIV privileged access mode for LPTIM4 30 1 read-write LPTIM5PRIV privileged access mode for LPTIM5 31 1 read-write PRIVCFGR3 PRIVCFGR3 GTZC1 TZSC privilege configuration register 3 0x28 0x20 read-write 0x00000000 0xFFFFFFFF LPTIM6PRIV privileged access mode for LPTIM6 0 1 read-write VREFBUFPRIV privileged access mode for VREFBUF 1 1 read-write I3C2PRIV privileged access mode for I3C2 2 1 read-write CRCPRIV privileged access mode for CRC 8 1 read-write CORDICPRIV privileged access mode for CORDIC 9 1 read-write FMACPRIV privileged access mode for FMAC 10 1 read-write ETHPRIV privileged access mode for register of ETH 11 1 read-write ICACHEPRIV privileged access mode for ICACHE 12 1 read-write DCACHEPRIV privileged access mode for DCACHE 13 1 read-write ADC12PRIV privileged access mode for ADC1 and ADC2 14 1 read-write DCMIPRIV privileged access mode for DCMI 15 1 read-write AESPRIV privileged access mode for AES 16 1 read-write HASHPRIV privileged access mode for HASH 17 1 read-write RNGPRIV privileged access mode for RNG 18 1 read-write SAESPRIV privileged access mode for SAES 19 1 read-write PKAPRIV privileged access mode for PKA 20 1 read-write SDMMC1PRIV privileged access mode for SDMMC1 21 1 read-write FMCPRIV privileged access mode for FMC 23 1 read-write OCTOSPI1PRIV privileged access mode for OCTOSPI1 24 1 read-write RAMCFGPRIV privileged access mode for RAMSCFG 26 1 read-write MPCWM1ACFGR MPCWM1ACFGR GTZC1 TZSC memory 1 subregion A watermark configuration register 0x40 0x20 read-write 0x00000000 0xFFFFFFFF SREN subregion A enable 0 1 read-write SRLOCK subregion A lock 1 1 read-write SEC Secure subregion A of base region x 8 1 read-write PRIV Privileged subregion A of base region x 9 1 read-write MPCWM1AR MPCWM1AR GTZC1 TZSC memory 1 subregion A watermark register 0x44 0x20 read-write 0x00000000 0xFFFFFFFF SUBA_START Start of subregion A in region x 0 11 read-write SUBA_LENGTH Length of subregion A in region x 16 12 read-write MPCWM1BCFGR MPCWM1BCFGR GTZC1 TZSC memory 1 subregion B watermark configuration register 0x48 0x20 read-write 0x00000000 0xFFFFFFFF SREN subregion B enable 0 1 read-write SRLOCK subregion B lock 1 1 read-write SEC Secure subregion B of base region x 8 1 read-write PRIV Privileged subregion B of base region x 9 1 read-write MPCWM1BR MPCWM1BR GTZC1 TZSC memory 1 subregion B watermark register 0x4C 0x20 read-write 0x00000000 0xFFFFFFFF SUBB_START Start of subregion B in region x 0 11 read-write SUBB_LENGTH Length of subregion B in region x 16 12 read-write MPCWM2ACFGR MPCWM2ACFGR GTZC1 TZSC memory 2 subregion A watermark configuration register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF SREN subregion A enable 0 1 read-write SRLOCK subregion A lock 1 1 read-write SEC Secure subregion A of base region x 8 1 read-write PRIV Privileged subregion A of base region x 9 1 read-write MPCWM2AR MPCWM2AR GTZC1 TZSC memory 2 subregion A watermark register 0x54 0x20 read-write 0x00000000 0xFFFFFFFF SUBA_START Start of subregion A in region x 0 11 read-write SUBA_LENGTH Length of subregion A in region x 16 12 read-write MPCWM2BCFGR MPCWM2BCFGR GTZC1 TZSC memory 2 subregion B watermark configuration register 0x58 0x20 read-write 0x00000000 0xFFFFFFFF SREN subregion B enable 0 1 read-write SRLOCK subregion B lock 1 1 read-write SEC Secure subregion B of base region x 8 1 read-write PRIV Privileged subregion B of base region x 9 1 read-write MPCWM2BR MPCWM2BR GTZC1 TZSC memory 2 subregion B watermark register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF SUBB_START Start of subregion B in region x 0 11 read-write SUBB_LENGTH Length of subregion B in region x 16 12 read-write MPCWM3ACFGR MPCWM3ACFGR GTZC1 TZSC memory 3 subregion A watermark configuration register 0x60 0x20 read-write 0x00000000 0xFFFFFFFF SREN subregion A enable 0 1 read-write SRLOCK subregion A lock 1 1 read-write SEC Secure subregion A of base region x 8 1 read-write PRIV Privileged subregion A of base region x 9 1 read-write MPCWM3AR MPCWM3AR GTZC1 TZSC memory 3 subregion A watermark register 0x64 0x20 read-write 0x00000000 0xFFFFFFFF SUBA_START Start of subregion A in region x 0 11 read-write SUBA_LENGTH Length of subregion A in region x 16 12 read-write MPCWM3BCFGR MPCWM3BCFGR GTZC1 TZSC memory 3 subregion B watermark configuration register 0x68 0x20 read-write 0x00000000 0xFFFFFFFF SREN subregion B enable 0 1 read-write SRLOCK subregion B lock 1 1 read-write SEC Secure subregion B of base region x 8 1 read-write PRIV Privileged subregion B of base region x 9 1 read-write MPCWM3BR MPCWM3BR GTZC1 TZSC memory 3 subregion B watermark register 0x6C 0x20 read-write 0x00000000 0xFFFFFFFF SUBB_START Start of subregion B in region x 0 11 read-write SUBB_LENGTH Length of subregion B in region x 16 12 read-write MPCWM4ACFGR MPCWM4ACFGR GTZC1 TZSC memory 4 subregion A watermark configuration register 0x70 0x20 read-write 0x00000000 0xFFFFFFFF SREN subregion A enable 0 1 read-write SRLOCK subregion A lock 1 1 read-write SEC Secure subregion A of base region x 8 1 read-write PRIV Privileged subregion A of base region x 9 1 read-write MPCWM4AR MPCWM4AR GTZC1 TZSC memory 4 subregion A watermark register 0x74 0x20 read-write 0x00000000 0xFFFFFFFF SUBA_START Start of subregion A in region x 0 11 read-write SUBA_LENGTH Length of subregion A in region x 16 12 read-write MPCWM4BCFGR MPCWM4BCFGR GTZC1 TZSC memory 4 subregion B watermark configuration register 0x78 0x20 read-write 0x00000000 0xFFFFFFFF SREN subregion B enable 0 1 read-write SRLOCK subregion B lock 1 1 read-write SEC Secure subregion B of base region x 8 1 read-write PRIV Privileged subregion B of base region x 9 1 read-write MPCWM4BR MPCWM4BR GTZC1 TZSC memory 4 subregion B watermark register 0x7C 0x20 read-write 0x00000000 0xFFFFFFFF SUBB_START Start of subregion B in region x 0 11 read-write SUBB_LENGTH Length of subregion B in region x 16 12 read-write GTZC1_TZSC_S GTZC 0x50036400 HASH HASH register bank HASH 0x420C0400 0x0 0x400 registers HASH HASH interrupt 117 CR CR HASH control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF INIT Initialize message digest calculation 2 1 read-write DMAE DMA enable 3 1 read-write DATATYPE Data type selection 4 2 read-write MODE Mode selection 6 1 read-write NBW Number of words already pushed 8 4 read-only DINNE DIN not empty 12 1 read-only MDMAT Multiple DMA transfers 13 1 read-write LKEY Long key selection 16 1 read-write ALGO Algorithm selection 17 4 read-write DIN DIN HASH data input register 0x4 0x20 write-only 0x00000000 0xFFFFFFFF DATAIN Data input 0 32 write-only STR STR HASH start register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF NBLW Number of valid bits in the last word 0 5 read-write DCAL Digest calculation 8 1 read-write HRA0 HRA0 HASH aliased digest register 0 0xC 0x20 read-only 0x00000000 0xFFFFFFFF H0 Hash data x 0 32 read-only HRA1 HRA1 HASH aliased digest register 1 0x10 0x20 read-only 0x00000000 0xFFFFFFFF H1 Hash data x 0 32 read-only HRA2 HRA2 HASH aliased digest register 2 0x14 0x20 read-only 0x00000000 0xFFFFFFFF H2 Hash data x 0 32 read-only HRA3 HRA3 HASH aliased digest register 3 0x18 0x20 read-only 0x00000000 0xFFFFFFFF H3 Hash data x 0 32 read-only HRA4 HRA4 HASH aliased digest register 4 0x1C 0x20 read-only 0x00000000 0xFFFFFFFF H4 Hash data x 0 32 read-only IMR IMR HASH interrupt enable register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF DINIE Data input interrupt enable 0 1 read-write DCIE Digest calculation completion interrupt enable 1 1 read-write SR SR HASH status register 0x24 0x20 read-write 0x00110001 0xFFFFFFFF DINIS Data input interrupt status 0 1 read-write DCIS Digest calculation completion interrupt status 1 1 read-write DMAS DMA Status 2 1 read-only BUSY Busy bit 3 1 read-only NBWP Number of words already pushed 9 5 read-only DINNE DIN not empty 15 1 read-only NBWE Number of words expected 16 5 read-only CSR0 CSR0 HASH context swap register 0 0xF8 0x20 read-write 0x00000000 0xFFFFFFFF CS0 Context swap x 0 32 read-write CSR1 CSR1 HASH context swap register 1 0xFC 0x20 read-write 0x00000000 0xFFFFFFFF CS1 Context swap x 0 32 read-write CSR2 CSR2 HASH context swap register 2 0x100 0x20 read-write 0x00000000 0xFFFFFFFF CS2 Context swap x 0 32 read-write CSR3 CSR3 HASH context swap register 3 0x104 0x20 read-write 0x00000000 0xFFFFFFFF CS3 Context swap x 0 32 read-write CSR4 CSR4 HASH context swap register 4 0x108 0x20 read-write 0x00000000 0xFFFFFFFF CS4 Context swap x 0 32 read-write CSR5 CSR5 HASH context swap register 5 0x10C 0x20 read-write 0x00000000 0xFFFFFFFF CS5 Context swap x 0 32 read-write CSR6 CSR6 HASH context swap register 6 0x110 0x20 read-write 0x00000000 0xFFFFFFFF CS6 Context swap x 0 32 read-write CSR7 CSR7 HASH context swap register 7 0x114 0x20 read-write 0x00000000 0xFFFFFFFF CS7 Context swap x 0 32 read-write CSR8 CSR8 HASH context swap register 8 0x118 0x20 read-write 0x00000000 0xFFFFFFFF CS8 Context swap x 0 32 read-write CSR9 CSR9 HASH context swap register 9 0x11C 0x20 read-write 0x00000000 0xFFFFFFFF CS9 Context swap x 0 32 read-write CSR10 CSR10 HASH context swap register 10 0x120 0x20 read-write 0x00000000 0xFFFFFFFF CS10 Context swap x 0 32 read-write CSR11 CSR11 HASH context swap register 11 0x124 0x20 read-write 0x00000000 0xFFFFFFFF CS11 Context swap x 0 32 read-write CSR12 CSR12 HASH context swap register 12 0x128 0x20 read-write 0x00000000 0xFFFFFFFF CS12 Context swap x 0 32 read-write CSR13 CSR13 HASH context swap register 13 0x12C 0x20 read-write 0x00000000 0xFFFFFFFF CS13 Context swap x 0 32 read-write CSR14 CSR14 HASH context swap register 14 0x130 0x20 read-write 0x00000000 0xFFFFFFFF CS14 Context swap x 0 32 read-write CSR15 CSR15 HASH context swap register 15 0x134 0x20 read-write 0x00000000 0xFFFFFFFF CS15 Context swap x 0 32 read-write CSR16 CSR16 HASH context swap register 16 0x138 0x20 read-write 0x00000000 0xFFFFFFFF CS16 Context swap x 0 32 read-write CSR17 CSR17 HASH context swap register 17 0x13C 0x20 read-write 0x00000000 0xFFFFFFFF CS17 Context swap x 0 32 read-write CSR18 CSR18 HASH context swap register 18 0x140 0x20 read-write 0x00000000 0xFFFFFFFF CS18 Context swap x 0 32 read-write CSR19 CSR19 HASH context swap register 19 0x144 0x20 read-write 0x00000000 0xFFFFFFFF CS19 Context swap x 0 32 read-write CSR20 CSR20 HASH context swap register 20 0x148 0x20 read-write 0x00000000 0xFFFFFFFF CS20 Context swap x 0 32 read-write CSR21 CSR21 HASH context swap register 21 0x14C 0x20 read-write 0x00000000 0xFFFFFFFF CS21 Context swap x 0 32 read-write CSR22 CSR22 HASH context swap register 22 0x150 0x20 read-write 0x00000000 0xFFFFFFFF CS22 Context swap x 0 32 read-write CSR23 CSR23 HASH context swap register 23 0x154 0x20 read-write 0x00000000 0xFFFFFFFF CS23 Context swap x 0 32 read-write CSR24 CSR24 HASH context swap register 24 0x158 0x20 read-write 0x00000000 0xFFFFFFFF CS24 Context swap x 0 32 read-write CSR25 CSR25 HASH context swap register 25 0x15C 0x20 read-write 0x00000000 0xFFFFFFFF CS25 Context swap x 0 32 read-write CSR26 CSR26 HASH context swap register 26 0x160 0x20 read-write 0x00000000 0xFFFFFFFF CS26 Context swap x 0 32 read-write CSR27 CSR27 HASH context swap register 27 0x164 0x20 read-write 0x00000000 0xFFFFFFFF CS27 Context swap x 0 32 read-write CSR28 CSR28 HASH context swap register 28 0x168 0x20 read-write 0x00000000 0xFFFFFFFF CS28 Context swap x 0 32 read-write CSR29 CSR29 HASH context swap register 29 0x16C 0x20 read-write 0x00000000 0xFFFFFFFF CS29 Context swap x 0 32 read-write CSR30 CSR30 HASH context swap register 30 0x170 0x20 read-write 0x00000000 0xFFFFFFFF CS30 Context swap x 0 32 read-write CSR31 CSR31 HASH context swap register 31 0x174 0x20 read-write 0x00000000 0xFFFFFFFF CS31 Context swap x 0 32 read-write CSR32 CSR32 HASH context swap register 32 0x178 0x20 read-write 0x00000000 0xFFFFFFFF CS32 Context swap x 0 32 read-write CSR33 CSR33 HASH context swap register 33 0x17C 0x20 read-write 0x00000000 0xFFFFFFFF CS33 Context swap x 0 32 read-write CSR34 CSR34 HASH context swap register 34 0x180 0x20 read-write 0x00000000 0xFFFFFFFF CS34 Context swap x 0 32 read-write CSR35 CSR35 HASH context swap register 35 0x184 0x20 read-write 0x00000000 0xFFFFFFFF CS35 Context swap x 0 32 read-write CSR36 CSR36 HASH context swap register 36 0x188 0x20 read-write 0x00000000 0xFFFFFFFF CS36 Context swap x 0 32 read-write CSR37 CSR37 HASH context swap register 37 0x18C 0x20 read-write 0x00000000 0xFFFFFFFF CS37 Context swap x 0 32 read-write CSR38 CSR38 HASH context swap register 38 0x190 0x20 read-write 0x00000000 0xFFFFFFFF CS38 Context swap x 0 32 read-write CSR39 CSR39 HASH context swap register 39 0x194 0x20 read-write 0x00000000 0xFFFFFFFF CS39 Context swap x 0 32 read-write CSR40 CSR40 HASH context swap register 40 0x198 0x20 read-write 0x00000000 0xFFFFFFFF CS40 Context swap x 0 32 read-write CSR41 CSR41 HASH context swap register 41 0x19C 0x20 read-write 0x00000000 0xFFFFFFFF CS41 Context swap x 0 32 read-write CSR42 CSR42 HASH context swap register 42 0x1A0 0x20 read-write 0x00000000 0xFFFFFFFF CS42 Context swap x 0 32 read-write CSR43 CSR43 HASH context swap register 43 0x1A4 0x20 read-write 0x00000000 0xFFFFFFFF CS43 Context swap x 0 32 read-write CSR44 CSR44 HASH context swap register 44 0x1A8 0x20 read-write 0x00000000 0xFFFFFFFF CS44 Context swap x 0 32 read-write CSR45 CSR45 HASH context swap register 45 0x1AC 0x20 read-write 0x00000000 0xFFFFFFFF CS45 Context swap x 0 32 read-write CSR46 CSR46 HASH context swap register 46 0x1B0 0x20 read-write 0x00000000 0xFFFFFFFF CS46 Context swap x 0 32 read-write CSR47 CSR47 HASH context swap register 47 0x1B4 0x20 read-write 0x00000000 0xFFFFFFFF CS47 Context swap x 0 32 read-write CSR48 CSR48 HASH context swap register 48 0x1B8 0x20 read-write 0x00000000 0xFFFFFFFF CS48 Context swap x 0 32 read-write CSR49 CSR49 HASH context swap register 49 0x1BC 0x20 read-write 0x00000000 0xFFFFFFFF CS49 Context swap x 0 32 read-write CSR50 CSR50 HASH context swap register 50 0x1C0 0x20 read-write 0x00000000 0xFFFFFFFF CS50 Context swap x 0 32 read-write CSR51 CSR51 HASH context swap register 51 0x1C4 0x20 read-write 0x00000000 0xFFFFFFFF CS51 Context swap x 0 32 read-write CSR52 CSR52 HASH context swap register 52 0x1C8 0x20 read-write 0x00000000 0xFFFFFFFF CS52 Context swap x 0 32 read-write CSR53 CSR53 HASH context swap register 53 0x1CC 0x20 read-write 0x00000000 0xFFFFFFFF CS53 Context swap x 0 32 read-write CSR54 CSR54 HASH context swap register 54 0x1D0 0x20 read-write 0x00000000 0xFFFFFFFF CS54 Context swap x 0 32 read-write CSR55 CSR55 HASH context swap register 55 0x1D4 0x20 read-write 0x00000000 0xFFFFFFFF CS55 Context swap x 0 32 read-write CSR56 CSR56 HASH context swap register 56 0x1D8 0x20 read-write 0x00000000 0xFFFFFFFF CS56 Context swap x 0 32 read-write CSR57 CSR57 HASH context swap register 57 0x1DC 0x20 read-write 0x00000000 0xFFFFFFFF CS57 Context swap x 0 32 read-write CSR58 CSR58 HASH context swap register 58 0x1E0 0x20 read-write 0x00000000 0xFFFFFFFF CS58 Context swap x 0 32 read-write CSR59 CSR59 HASH context swap register 59 0x1E4 0x20 read-write 0x00000000 0xFFFFFFFF CS59 Context swap x 0 32 read-write CSR60 CSR60 HASH context swap register 60 0x1E8 0x20 read-write 0x00000000 0xFFFFFFFF CS60 Context swap x 0 32 read-write CSR61 CSR61 HASH context swap register 61 0x1EC 0x20 read-write 0x00000000 0xFFFFFFFF CS61 Context swap x 0 32 read-write CSR62 CSR62 HASH context swap register 62 0x1F0 0x20 read-write 0x00000000 0xFFFFFFFF CS62 Context swap x 0 32 read-write CSR63 CSR63 HASH context swap register 63 0x1F4 0x20 read-write 0x00000000 0xFFFFFFFF CS63 Context swap x 0 32 read-write CSR64 CSR64 HASH context swap register 64 0x1F8 0x20 read-write 0x00000000 0xFFFFFFFF CS64 Context swap x 0 32 read-write CSR65 CSR65 HASH context swap register 65 0x1FC 0x20 read-write 0x00000000 0xFFFFFFFF CS65 Context swap x 0 32 read-write CSR66 CSR66 HASH context swap register 66 0x200 0x20 read-write 0x00000000 0xFFFFFFFF CS66 Context swap x 0 32 read-write CSR67 CSR67 HASH context swap register 67 0x204 0x20 read-write 0x00000000 0xFFFFFFFF CS67 Context swap x 0 32 read-write CSR68 CSR68 HASH context swap register 68 0x208 0x20 read-write 0x00000000 0xFFFFFFFF CS68 Context swap x 0 32 read-write CSR69 CSR69 HASH context swap register 69 0x20C 0x20 read-write 0x00000000 0xFFFFFFFF CS69 Context swap x 0 32 read-write CSR70 CSR70 HASH context swap register 70 0x210 0x20 read-write 0x00000000 0xFFFFFFFF CS70 Context swap x 0 32 read-write CSR71 CSR71 HASH context swap register 71 0x214 0x20 read-write 0x00000000 0xFFFFFFFF CS71 Context swap x 0 32 read-write CSR72 CSR72 HASH context swap register 72 0x218 0x20 read-write 0x00000000 0xFFFFFFFF CS72 Context swap x 0 32 read-write CSR73 CSR73 HASH context swap register 73 0x21C 0x20 read-write 0x00000000 0xFFFFFFFF CS73 Context swap x 0 32 read-write CSR74 CSR74 HASH context swap register 74 0x220 0x20 read-write 0x00000000 0xFFFFFFFF CS74 Context swap x 0 32 read-write CSR75 CSR75 HASH context swap register 75 0x224 0x20 read-write 0x00000000 0xFFFFFFFF CS75 Context swap x 0 32 read-write CSR76 CSR76 HASH context swap register 76 0x228 0x20 read-write 0x00000000 0xFFFFFFFF CS76 Context swap x 0 32 read-write CSR77 CSR77 HASH context swap register 77 0x22C 0x20 read-write 0x00000000 0xFFFFFFFF CS77 Context swap x 0 32 read-write CSR78 CSR78 HASH context swap register 78 0x230 0x20 read-write 0x00000000 0xFFFFFFFF CS78 Context swap x 0 32 read-write CSR79 CSR79 HASH context swap register 79 0x234 0x20 read-write 0x00000000 0xFFFFFFFF CS79 Context swap x 0 32 read-write CSR80 CSR80 HASH context swap register 80 0x238 0x20 read-write 0x00000000 0xFFFFFFFF CS80 Context swap x 0 32 read-write CSR81 CSR81 HASH context swap register 81 0x23C 0x20 read-write 0x00000000 0xFFFFFFFF CS81 Context swap x 0 32 read-write CSR82 CSR82 HASH context swap register 82 0x240 0x20 read-write 0x00000000 0xFFFFFFFF CS82 Context swap x 0 32 read-write CSR83 CSR83 HASH context swap register 83 0x244 0x20 read-write 0x00000000 0xFFFFFFFF CS83 Context swap x 0 32 read-write CSR84 CSR84 HASH context swap register 84 0x248 0x20 read-write 0x00000000 0xFFFFFFFF CS84 Context swap x 0 32 read-write CSR85 CSR85 HASH context swap register 85 0x24C 0x20 read-write 0x00000000 0xFFFFFFFF CS85 Context swap x 0 32 read-write CSR86 CSR86 HASH context swap register 86 0x250 0x20 read-write 0x00000000 0xFFFFFFFF CS86 Context swap x 0 32 read-write CSR87 CSR87 HASH context swap register 87 0x254 0x20 read-write 0x00000000 0xFFFFFFFF CS87 Context swap x 0 32 read-write CSR88 CSR88 HASH context swap register 88 0x258 0x20 read-write 0x00000000 0xFFFFFFFF CS88 Context swap x 0 32 read-write CSR89 CSR89 HASH context swap register 89 0x25C 0x20 read-write 0x00000000 0xFFFFFFFF CS89 Context swap x 0 32 read-write CSR90 CSR90 HASH context swap register 90 0x260 0x20 read-write 0x00000000 0xFFFFFFFF CS90 Context swap x 0 32 read-write CSR91 CSR91 HASH context swap register 91 0x264 0x20 read-write 0x00000000 0xFFFFFFFF CS91 Context swap x 0 32 read-write CSR92 CSR92 HASH context swap register 92 0x268 0x20 read-write 0x00000000 0xFFFFFFFF CS92 Context swap x 0 32 read-write CSR93 CSR93 HASH context swap register 93 0x26C 0x20 read-write 0x00000000 0xFFFFFFFF CS93 Context swap x 0 32 read-write CSR94 CSR94 HASH context swap register 94 0x270 0x20 read-write 0x00000000 0xFFFFFFFF CS94 Context swap x 0 32 read-write CSR95 CSR95 HASH context swap register 95 0x274 0x20 read-write 0x00000000 0xFFFFFFFF CS95 Context swap x 0 32 read-write CSR96 CSR96 HASH context swap register 96 0x278 0x20 read-write 0x00000000 0xFFFFFFFF CS96 Context swap x 0 32 read-write CSR97 CSR97 HASH context swap register 97 0x27C 0x20 read-write 0x00000000 0xFFFFFFFF CS97 Context swap x 0 32 read-write CSR98 CSR98 HASH context swap register 98 0x280 0x20 read-write 0x00000000 0xFFFFFFFF CS98 Context swap x 0 32 read-write CSR99 CSR99 HASH context swap register 99 0x284 0x20 read-write 0x00000000 0xFFFFFFFF CS99 Context swap x 0 32 read-write CSR100 CSR100 HASH context swap register 100 0x288 0x20 read-write 0x00000000 0xFFFFFFFF CS100 Context swap x 0 32 read-write CSR101 CSR101 HASH context swap register 101 0x28C 0x20 read-write 0x00000000 0xFFFFFFFF CS101 Context swap x 0 32 read-write CSR102 CSR102 HASH context swap register 102 0x290 0x20 read-write 0x00000000 0xFFFFFFFF CS102 Context swap x 0 32 read-write HR0 HR0 HASH digest register 0 0x310 0x20 read-only 0x00000000 0xFFFFFFFF H0 Hash data x 0 32 read-only HR1 HR1 HASH digest register 1 0x314 0x20 read-only 0x00000000 0xFFFFFFFF H1 Hash data x 0 32 read-only HR2 HR2 HASH digest register 2 0x318 0x20 read-only 0x00000000 0xFFFFFFFF H2 Hash data x 0 32 read-only HR3 HR3 HASH digest register 3 0x31C 0x20 read-only 0x00000000 0xFFFFFFFF H3 Hash data x 0 32 read-only HR4 HR4 HASH digest register 4 0x320 0x20 read-only 0x00000000 0xFFFFFFFF H4 Hash data x 0 32 read-only HR5 HR5 HASH supplementary digest register 5 0x324 0x20 read-only 0x00000000 0xFFFFFFFF H5 Hash data x 0 32 read-only HR6 HR6 HASH supplementary digest register 6 0x328 0x20 read-only 0x00000000 0xFFFFFFFF H6 Hash data x 0 32 read-only HR7 HR7 HASH supplementary digest register 7 0x32C 0x20 read-only 0x00000000 0xFFFFFFFF H7 Hash data x 0 32 read-only HR8 HR8 HASH supplementary digest register 8 0x330 0x20 read-only 0x00000000 0xFFFFFFFF H8 Hash data x 0 32 read-only HR9 HR9 HASH supplementary digest register 9 0x334 0x20 read-only 0x00000000 0xFFFFFFFF H9 Hash data x 0 32 read-only HR10 HR10 HASH supplementary digest register 10 0x338 0x20 read-only 0x00000000 0xFFFFFFFF H10 Hash data x 0 32 read-only HR11 HR11 HASH supplementary digest register 11 0x33C 0x20 read-only 0x00000000 0xFFFFFFFF H11 Hash data x 0 32 read-only HR12 HR12 HASH supplementary digest register 12 0x340 0x20 read-only 0x00000000 0xFFFFFFFF H12 Hash data x 0 32 read-only HR13 HR13 HASH supplementary digest register 13 0x344 0x20 read-only 0x00000000 0xFFFFFFFF H13 Hash data x 0 32 read-only HR14 HR14 HASH supplementary digest register 14 0x348 0x20 read-only 0x00000000 0xFFFFFFFF H14 Hash data x 0 32 read-only HR15 HR15 HASH supplementary digest register 15 0x34C 0x20 read-only 0x00000000 0xFFFFFFFF H15 Hash data x 0 32 read-only HASH_S 0x520C0400 I2C1 I2C address block description I2C 0x40005400 0x0 0x2C registers I2C1_ERR I2C1 error interrupt 52 I2C1_EV I2C1 event interrupt 51 CR1 CR1 I2C control register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF PE Peripheral enable 0 1 read-write PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX interrupt enable 1 1 read-write TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX interrupt enable 2 1 read-write RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match interrupt enable (slave only) 3 1 read-write ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received interrupt enable 4 1 read-write NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE Stop detection interrupt enable 5 1 read-write STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer complete interrupt enable 6 1 read-write TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable 7 1 read-write ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter 8 4 read-write DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF 12 1 read-write ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 read-write TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 read-write RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control 16 1 read-write SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable 17 1 read-write NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wake-up from Stop mode enable 18 1 read-write WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 read-write GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus host address enable 20 1 read-write SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus device default address enable 21 1 read-write SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBus alert enable 22 1 read-write ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable 23 1 read-write PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 FMP Fast-mode Plus 20 mA drive enable 24 1 read-write FMP Disabled 20 mA I/O drive disabled 0 Enabled 20 mA I/O drive enabled 1 ADDRACLR Address match flag (ADDR) automatic clear 30 1 read-write ADDRACLR Disabled ADDR flag is set by hardware, cleared by software 0 Enabled ADDR flag remains cleared by hardware 1 STOPFACLR STOP detection flag (STOPF) automatic clear 31 1 read-write STOPFACLR Disabled STOPF flag is set by hardware, cleared by software 0 Enabled STOPF flag remains cleared by hardware 1 CR2 CR2 I2C control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF SADD Slave address (master mode) 0 10 read-write 0 1023 RD_WRN Transfer direction (master mode) 10 1 read-write RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 ADD10 10-bit addressing mode (master mode) 11 1 read-write ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 read-write HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 START Start generation 13 1 read-write oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 STOP Stop generation (master mode) 14 1 read-write oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 NACK NACK generation (slave mode) 15 1 read-write oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 NBYTES Number of bytes 16 8 read-write 0 255 RELOAD NBYTES reload mode 24 1 read-write RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 AUTOEND Automatic end mode (master mode) 25 1 read-write AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 PECBYTE Packet error checking byte 26 1 read-write oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 OAR1 OAR1 I2C own address 1 register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF OA1 Interface own slave address 0 10 read-write 0 1023 OA1MODE Own address 1 10-bit mode 10 1 read-write OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own address 1 enable 15 1 read-write OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 I2C own address 2 register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF OA2 Interface address 1 7 read-write 0 127 OA2MSK Own address 2 masks 8 3 read-write OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and donât care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and donât care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and donât care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and donât care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and donât care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and donât care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and donât care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own address 2 enable 15 1 read-write OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR I2C timing register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF SCLL SCL low period (master mode) 0 8 read-write 0 255 SCLH SCL high period (master mode) 8 8 read-write 0 255 SDADEL Data hold time 16 4 read-write 0 15 SCLDEL Data setup time 20 4 read-write 0 15 PRESC Timing prescaler 28 4 read-write 0 15 TIMEOUTR TIMEOUTR I2C timeout register 0x14 0x20 read-write 0x00000000 0xFFFFFFFF TIMEOUTA Bus timeout A 0 12 read-write 0 4095 TIDLE Idle clock timeout detection 12 1 read-write TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 read-write TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B 16 12 read-write 0 4095 TEXTEN Extended clock timeout enable 31 1 read-write TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR I2C interrupt and status register 0x18 0x20 read-write 0x00000001 0xFFFFFFFF TXE Transmit data register empty (transmitters) 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 TXIS Transmit interrupt status (transmitters) 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 RXNE Receive data register not empty (receivers) 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 ADDR Address matched (slave mode) 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 NACKF Not acknowledge received flag 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 STOPF Stop detection flag 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 TC Transfer complete (master mode) 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TCR Transfer complete reload 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 BERR Bus error 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 ARLO Arbitration lost 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 OVR Overrun/underrun (slave mode) 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 PECERR PEC error in reception 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 TIMEOUT Timeout or tless thansub>LOWless than/sub> detection flag 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 ALERT SMBus alert 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 BUSY Bus busy 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 DIR Transfer direction (slave mode) 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 ADDCODE Address match code (slave mode) 17 7 read-only 0 127 ICR ICR I2C interrupt clear register 0x1C 0x20 write-only 0x00000000 0xFFFFFFFF ADDRCF Address matched flag clear 3 1 write-only oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 NACKCF Not acknowledge flag clear 4 1 write-only oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 STOPCF STOP detection flag clear 5 1 write-only oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 BERRCF Bus error flag clear 8 1 write-only oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 ARLOCF Arbitration lost flag clear 9 1 write-only oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 OVRCF Overrun/underrun flag clear 10 1 write-only oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 PECCF PEC error flag clear 11 1 write-only oneToClear PECCF Clear Clears the PEC flag in ISR register 1 TIMOUTCF Timeout detection flag clear 12 1 write-only oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 ALERTCF Alert flag clear 13 1 write-only oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 PECR PECR I2C PEC register 0x20 0x20 read-only 0x00000000 0xFFFFFFFF PEC Packet error checking register 0 8 read-only 0 255 RXDR RXDR I2C receive data register 0x24 0x20 read-only 0x00000000 0xFFFFFFFF RXDATA 8-bit receive data 0 8 read-only 0 255 TXDR TXDR I2C transmit data register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF TXDATA 8-bit transmit data 0 8 read-write 0 255 I2C1_S 0x50005400 I2C2 0x40005800 I2C2_ERR I2C2 error interrupt 54 I2C2_EV I2C2 event interrupt 53 I2C2_S 0x50005800 I2C3 0x44002800 I2C3_ERR I2C3 error interrupt 81 I2C3_EV I2C3 event interrupt 80 I2C3_S 0x54002800 I3C1 I3C register block I3C 0x40005C00 0x0 0x400 registers I3C1_ERR I3C1 error interrupt 124 I3C1_EV I3C1 event interrupt 123 CR CR I3C message control register 0x0 0x20 write-only 0x00000000 0xFFFFFFFF DCNT Count of data to transfer during a read or write message, in bytes (whatever I3C acts as controller/target) 0 16 write-only RNW Read / non-write message (when I3C acts as controller) 16 1 write-only ADD 7-bit I3C dynamic / Iless thansup>2less than/sup>C static target address (when I3C acts as controller) 17 7 write-only MTYPE Message type (whatever I3C acts as controller/target) 27 4 write-only MEND Message end type/last message of a frame (when the I3C acts as controller) 31 1 write-only CR_ALTERNATE1 CR_ALTERNATE1 I3C message control register CR 0x0 0x20 write-only 0x00000000 0xFFFFFFFF DCNT Count of related data to the CCC command to transfer as CCC defining bytes, or CCC sub-command bytes, or CCC data bytes, in bytes 0 16 write-only CCC 8-bit CCC code (when I3C acts as controller) 16 8 write-only MTYPE Message type (when I3C acts as controller) 27 4 write-only MEND Message end type/last message of a frame (when I3C acts as controller) 31 1 write-only CFGR CFGR I3C configuration register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF EN I3C enable (whatever I3C acts as controller/target) 0 1 read-write CRINIT Initial controller/target role 1 1 read-write NOARBH No arbitrable header after a start (when I3C acts as a controller) 2 1 read-write RSTPTRN HDR reset pattern enable (when I3C acts as a controller) 3 1 read-write EXITPTRN HDR exit pattern enable (when I3C acts as a controller) 4 1 read-write HKSDAEN High-keeper enable on SDA line (when I3C acts as a controller) 5 1 read-write HJACK Hot-join request acknowledge (when I3C acts as a controller) 7 1 read-write RXDMAEN RX-FIFO DMA request enable (whatever I3C acts as controller/target) 8 1 read-write RXFLUSH RX-FIFO flush (whatever I3C acts as controller/target) 9 1 write-only RXTHRES RX-FIFO threshold (whatever I3C acts as controller/target) 10 1 read-write TXDMAEN TX-FIFO DMA request enable (whatever I3C acts as controller/target) 12 1 read-write TXFLUSH TX-FIFO flush (whatever I3C acts as controller/target) 13 1 write-only TXTHRES TX-FIFO threshold (whatever I3C acts as controller/target) 14 1 read-write SDMAEN S-FIFO DMA request enable (when I3C acts as controller) 16 1 read-write SFLUSH S-FIFO flush (when I3C acts as controller) 17 1 write-only SMODE S-FIFO enable / status receive mode (when I3C acts as controller) 18 1 read-write TMODE Transmit mode (when I3C acts as controller) 19 1 read-write CDMAEN C-FIFO DMA request enable (when I3C acts as controller) 20 1 read-write CFLUSH C-FIFO flush (when I3C acts as controller) 21 1 write-only TSFSET Frame transfer set (software trigger) (when I3C acts as controller) 30 1 write-only RDR RDR I3C receive data byte register 0x10 0x20 read-only 0x00000000 0xFFFFFFFF RDB0 8-bit received data on I3C bus. 0 8 read-only RDWR RDWR I3C receive data word register 0x14 0x20 read-only 0x00000000 0xFFFFFFFF RDB0 8-bit received data (earliest byte on I3C bus). 0 8 read-only RDB1 8-bit received data (next byte after RDB0 on I3C bus). 8 8 read-only RDB2 8-bit received data (next byte after RDB1 on I3C bus). 16 8 read-only RDB3 8-bit received data (latest byte on I3C bus). 24 8 read-only TDR TDR I3C transmit data byte register 0x18 0x20 write-only 0x00000000 0xFFFFFFFF TDB0 8-bit data to transmit on I3C bus. 0 8 write-only TDWR TDWR I3C transmit data word register 0x1C 0x20 write-only 0x00000000 0xFFFFFFFF TDB0 8-bit transmit data (earliest byte on I3C bus) 0 8 write-only TDB1 8-bit transmit data (next byte after TDB0[7:0] on I3C bus). 8 8 write-only TDB2 8-bit transmit data (next byte after TDB1[7:0] on I3C bus). 16 8 write-only TDB3 8-bit transmit data (latest byte on I3C bus). 24 8 write-only IBIDR IBIDR I3C IBI payload data register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF IBIDB0 8-bit IBI payload data (earliest byte on I3C bus, MDB[7:0] mandatory data byte). 0 8 read-write IBIDB1 8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0]). 8 8 read-write IBIDB2 8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0]). 16 8 read-write IBIDB3 8-bit IBI payload data (latest byte on I3C bus). 24 8 read-write TGTTDR TGTTDR I3C target transmit configuration register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF TGTTDCNT Transmit data counter, in bytes (when I3C is configured as target) 0 16 read-write PRELOAD Preload of the TX-FIFO (when I3C is configured as target) 16 1 read-write SR SR I3C status register 0x30 0x20 read-only 0x00000000 0xFFFFFFFF XDCNT Data counter 0 16 read-only ABT A private read message is ended prematurely by the target (when the I3C acts as controller) 17 1 read-only DIR Message direction 18 1 read-only MID Message identifier/counter of a given frame (when the I3C acts as controller) 24 8 read-only SER SER I3C status error register 0x34 0x20 read-only 0x00000000 0xFFFFFFFF CODERR Protocol error code/type 0 4 read-only PERR Protocol error 4 1 read-only STALL SCL stall error (when the I3C acts as target) 5 1 read-only DOVR RX-FIFO overrun or TX-FIFO underrun 6 1 read-only COVR C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller) 7 1 read-only ANACK Address not acknowledged (when the I3C is configured as controller) 8 1 read-only DNACK Data not acknowledged (when the I3C acts as controller) 9 1 read-only DERR Data error (when the I3C acts as controller) 10 1 read-only RMR RMR I3C received message register 0x40 0x20 read-only 0x00000000 0xFFFFFFFF IBIRDCNT IBI received payload data count (when the I3C is configured as controller) 0 3 read-only RCODE Received CCC code (when the I3C is configured as target) 8 8 read-only RADD Received target address (when the I3C is configured as controller) 17 7 read-only EVR EVR I3C event register 0x50 0x20 read-only 0x00000003 0xFFFFFFFF CFEF C-FIFO empty flag (whatever the I3C acts as controller) 0 1 read-only TXFEF TX-FIFO empty flag (whatever the I3C acts as controller/target) 1 1 read-only CFNFF C-FIFO not full flag (when the I3C acts as controller) 2 1 read-only SFNEF S-FIFO not empty flag (when the I3C acts as controller) 3 1 read-only TXFNFF TX-FIFO not full flag (whatever the I3C acts as controller/target) 4 1 read-only RXFNEF RX-FIFO not empty flag (whatever the I3C acts as controller/target) 5 1 read-only TXLASTF Last written data byte/word flag (whatever the I3C acts as controller/target) 6 1 read-only RXLASTF Last read data byte/word flag (when the I3C acts as controller) 7 1 read-only FCF Frame complete flag (whatever the I3C acts as controller/target) 9 1 read-only RXTGTENDF Target-initiated read end flag (when the I3C acts as controller) 10 1 read-only ERRF Flag (whatever the I3C acts as controller/target) 11 1 read-only IBIF IBI flag (when the I3C acts as controller) 15 1 read-only IBIENDF IBI end flag (when the I3C acts as target) 16 1 read-only CRF Controller-role request flag (when the I3C acts as controller) 17 1 read-only CRUPDF Controller-role update flag (when the I3C acts as target) 18 1 read-only HJF Hot-join flag (when the I3C acts as controller) 19 1 read-only WKPF Wake-up/missed start flag (when the I3C acts as target) 21 1 read-only GETF Get flag (when the I3C acts as target) 22 1 read-only STAF Get status flag (when the I3C acts as target) 23 1 read-only DAUPDF Dynamic address update flag (when the I3C acts as target) 24 1 read-only MWLUPDF Maximum write length update flag (when the I3C acts as target) 25 1 read-only MRLUPDF Maximum read length update flag (when the I3C acts as target) 26 1 read-only RSTF Reset pattern flag (when the I3C acts as target) 27 1 read-only ASUPDF Activity state update flag (when the I3C acts as target) 28 1 read-only INTUPDF Interrupt/controller-role/hot-join update flag (when the I3C acts as target) 29 1 read-only DEFF DEFTGTS flag (when the I3C acts as target) 30 1 read-only GRPF Group addressing flag (when the I3C acts as target) 31 1 read-only IER IER I3C interrupt enable register 0x54 0x20 read-only 0x00000000 0xFFFFFFFF CFNFIE C-FIFO not full interrupt enable when the I3C acts as controller 2 1 read-only SFNEIE S-FIFO not empty interrupt enable when the I3C acts as controller 3 1 read-only TXFNFIE TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target) 4 1 read-only RXFNEIE RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target) 5 1 read-only FCIE frame complete interrupt enable (whatever the I3C acts as controller/target) 9 1 read-only RXTGTENDIE target-initiated read end interrupt enable (when the I3C acts as controller) 10 1 read-only ERRIE error interrupt enable (whatever the I3C acts as controller/target) 11 1 read-only IBIIE IBI request interrupt enable (when the I3C acts as controller) 15 1 read-only IBIENDIE IBI end interrupt enable (when the I3C acts as target) 16 1 read-only CRIE Controller-role request interrupt enable (when the I3C acts as controller) 17 1 read-only CRUPDIE Controller-role update interrupt enable (when the I3C acts as target) 18 1 read-only HJIE Hot-join interrupt enable (when the I3C acts as controller) 19 1 read-only WKPIE Wake-up interrupt enable (when the I3C acts as target) 21 1 read-only GETIE GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target) 22 1 read-only STAIE format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target) 23 1 read-only DAUPDIE ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target) 24 1 read-only MWLUPDIE SETMWL CCC interrupt enable (when the I3C acts as target) 25 1 read-only MRLUPDIE SETMRL CCC interrupt enable (when the I3C acts as target) 26 1 read-only RSTIE reset pattern interrupt enable (when the I3C acts as target) 27 1 read-only ASUPDIE ENTASx CCC interrupt enable (when the I3C acts as target) 28 1 read-only INTUPDIE ENEC/DISEC CCC interrupt enable (when the I3C acts as target) 29 1 read-only DEFIE DEFTGTS CCC interrupt enable (when the I3C acts as target) 30 1 read-only GRPIE DEFGRPA CCC interrupt enable (when the I3C acts as target) 31 1 read-only CEVR CEVR I3C clear event register 0x58 0x20 write-only 0x00000000 0xFFFFFFFF CFCF Clear frame complete flag (whatever the I3C acts as controller/target) 9 1 write-only CRXTGTENDF Clear target-initiated read end flag (when the I3C acts as controller) 10 1 write-only CERRF Clear error flag (whatever the I3C acts as controller/target) 11 1 write-only CIBIF Clear IBI request flag (when the I3C acts as controller) 15 1 write-only CIBIENDF Clear IBI end flag (when the I3C acts as target) 16 1 write-only CCRF Clear controller-role request flag (when the I3C acts as controller) 17 1 write-only CCRUPDF Clear controller-role update flag (when the I3C acts as target) 18 1 write-only CHJF Clear hot-join flag (when the I3C acts as controller) 19 1 write-only CWKPF Clear wake-up flag (when the I3C acts as target) 21 1 write-only CGETF Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target) 22 1 write-only CSTAF Clear format 1 GETSTATUS CCC flag (when the I3C acts as target) 23 1 write-only CDAUPDF Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target) 24 1 write-only CMWLUPDF Clear SETMWL CCC flag (when the I3C acts as target) 25 1 write-only CMRLUPDF Clear SETMRL CCC flag (when the I3C acts as target) 26 1 write-only CRSTF Clear reset pattern flag (when the I3C acts as target) 27 1 write-only CASUPDF Clear ENTASx CCC flag (when the I3C acts as target) 28 1 write-only CINTUPDF Clear ENEC/DISEC CCC flag (when the I3C acts as target) 29 1 write-only CDEFF Clear DEFTGTS CCC flag (when the I3C acts as target) 30 1 write-only CGRPF Clear DEFGRPA CCC flag (when the I3C acts as target) 31 1 write-only DEVR0 DEVR0 I3C own device characteristics register 0x60 0x20 read-write 0x00000000 0xFFFFFFFF DAVAL Dynamic address is valid (when the I3C acts as target) 0 1 read-write DA 7-bit dynamic address 1 7 read-write IBIEN IBI request enable (when the I3C acts as target) 16 1 read-write CREN Controller-role request enable (when the I3C acts as target) 17 1 read-write HJEN Hot-join request enable (when the I3C acts as target) 19 1 read-write AS Activity state (when the I3C acts as target) 20 2 read-only RSTACT Reset action/level on received reset pattern (when the I3C acts as target) 22 2 read-only RSTVAL Reset action is valid (when the I3C acts as target) 24 1 read-only DEVR1 DEVR1 I3C device 1 characteristics register 0x64 0x20 read-write 0x00000000 0xFFFFFFFF DA Assigned I3C dynamic address to target x (when the I3C acts as controller) 1 7 read-write IBIACK IBI request acknowledge (when the I3C acts as controller) 16 1 read-write CRACK Controller-role request acknowledge (when the I3C acts as controller) 17 1 read-write IBIDEN IBI data enable (when the I3C acts as controller) 18 1 read-write SUSP Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) 19 1 read-write DIS DA[6:0] write disabled (when the I3C acts as controller) 31 1 read-only DEVR2 DEVR2 I3C device 2 characteristics register 0x68 0x20 read-write 0x00000000 0xFFFFFFFF DA Assigned I3C dynamic address to target x (when the I3C acts as controller) 1 7 read-write IBIACK IBI request acknowledge (when the I3C acts as controller) 16 1 read-write CRACK Controller-role request acknowledge (when the I3C acts as controller) 17 1 read-write IBIDEN IBI data enable (when the I3C acts as controller) 18 1 read-write SUSP Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) 19 1 read-write DIS DA[6:0] write disabled (when the I3C acts as controller) 31 1 read-only DEVR3 DEVR3 I3C device 3 characteristics register 0x6C 0x20 read-write 0x00000000 0xFFFFFFFF DA Assigned I3C dynamic address to target x (when the I3C acts as controller) 1 7 read-write IBIACK IBI request acknowledge (when the I3C acts as controller) 16 1 read-write CRACK Controller-role request acknowledge (when the I3C acts as controller) 17 1 read-write IBIDEN IBI data enable (when the I3C acts as controller) 18 1 read-write SUSP Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) 19 1 read-write DIS DA[6:0] write disabled (when the I3C acts as controller) 31 1 read-only DEVR4 DEVR4 I3C device 4 characteristics register 0x70 0x20 read-write 0x00000000 0xFFFFFFFF DA Assigned I3C dynamic address to target x (when the I3C acts as controller) 1 7 read-write IBIACK IBI request acknowledge (when the I3C acts as controller) 16 1 read-write CRACK Controller-role request acknowledge (when the I3C acts as controller) 17 1 read-write IBIDEN IBI data enable (when the I3C acts as controller) 18 1 read-write SUSP Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) 19 1 read-write DIS DA[6:0] write disabled (when the I3C acts as controller) 31 1 read-only MAXRLR MAXRLR I3C maximum read length register 0x90 0x20 read-write 0x00000000 0xFFFFFFFF MRL Maximum data read length (when I3C acts as target) 0 16 read-write IBIP IBI payload data maximum size, in bytes (when I3C acts as target) 16 3 read-write MAXWLR MAXWLR I3C maximum write length register 0x94 0x20 read-write 0x00000000 0xFFFFFFFF MWL Maximum data write length (when I3C acts as target) 0 16 read-write TIMINGR0 TIMINGR0 I3C timing register 0 0xA0 0x20 read-write 0x00000000 0xFFFFFFFF SCLL_PP SCL low duration in I3C push-pull phases, in number of kernel clocks cycles: 0 8 read-write SCLH_I3C SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles: 8 8 read-write SCLL_OD SCL low duration in open-drain phases, used for legacy Iless thansup>2less than/sup>C messages and for I3C open-drain phases (address phase following a start, ACK phase during controller-initiated messages, and T bit phase during direct/private/IBI payload), in number of kernel clocks cycles: 16 8 read-write SCLH_I2C SCL high duration, used for legacy Iless thansup>2less than/sup>C messages, in number of kernel clocks cycles: 24 8 read-write TIMINGR1 TIMINGR1 I3C timing register 1 0xA4 0x20 read-write 0x00000000 0xFFFFFFFF AVAL Number of kernel clock cycles to set a time unit of 1 s, whatever I3C acts as controller or target. 0 8 read-write ASNCR Activity state of the new controller (when I3C acts as active controller) 8 2 read-write FREE Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller) 16 7 read-write SDA_HD SDA hold time (when the I3C acts as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tless thansub>HD_PPless than/sub>): 28 1 read-write TIMINGR2 TIMINGR2 I3C timing register 2 0xA8 0x20 read-write 0x00000000 0xFFFFFFFF STALLT Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy Iless thansup>2less than/sup>C read) 0 1 read-write STALLD Controller clock stall enable on PAR phase of Data 1 1 read-write STALLC Controller clock stall enable on PAR phase of CCC 2 1 read-write STALLA Controller clock stall enable on ACK phase 3 1 read-write STALL Controller clock stall time, in number of kernel clock cycles 8 8 read-write BCR BCR I3C bus characteristics register 0xC0 0x20 read-write 0x00000000 0xFFFFFFFF BCR0 max data speed limitation 0 1 read-write BCR2 in-band interrupt (IBI) payload 2 1 read-write BCR6 Controller capable 6 1 read-write DCR DCR I3C device characteristics register 0xC4 0x20 read-write 0x00000000 0xFFFFFFFF DCR device characteristics ID 0 8 read-write GETCAPR GETCAPR I3C get capability register 0xC8 0x20 read-write 0x00000000 0xFFFFFFFF CAPPEND IBI MDB support for pending read notification 14 1 read-write CRCAPR CRCAPR I3C controller-role capability register 0xCC 0x20 read-write 0x00000000 0xFFFFFFFF CAPDHOFF delayed controller-role hand-off 3 1 read-write CAPGRP group management support (when acting as controller) 9 1 read-write GETMXDSR GETMXDSR I3C get max data speed register 0xD0 0x20 read-write 0x00000000 0xFFFFFFFF HOFFAS Controller hand-off activity state 0 2 read-write FMT GETMXDS CCC format 8 2 read-write RDTURN programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte) 16 8 read-write TSCO clock-to-data turnaround time (tless thansub>SCOless than/sub>) 24 1 read-write EPIDR EPIDR I3C extended provisioned ID register 0xD4 0x20 read-write 0x02080000 0xFFFFFFFF MIPIID 4-bit MIPI Instance ID 12 4 read-write IDTSEL provisioned ID type selector 16 1 read-only MIPIMID 15-bit MIPI manufacturer ID 17 15 read-only I3C1_S 0x50005C00 I3C2 0x44003000 I3C2_ERR I3C2 error interrupt 132 I3C2_EV I3C2 event interrupt 131 I3C2_S 0x54003000 ICACHE ICACHE register block ICACHE 0x40030400 0x0 0x400 registers ICACHE Instruction cache global interrupt 104 CR CR ICACHE control register 0x0 0x20 read-write 0x00000004 0xFFFFFFFF EN enable 0 1 read-write CACHEINV cache invalidation 1 1 write-only WAYSEL cache associativity mode selection 2 1 read-write HITMEN hit monitor enable 16 1 read-write MISSMEN miss monitor enable 17 1 read-write HITMRST hit monitor reset 18 1 read-write MISSMRST miss monitor reset 19 1 read-write SR SR ICACHE status register 0x4 0x20 read-only 0x00000001 0xFFFFFFFF BUSYF busy flag 0 1 read-only BSYENDF busy end flag 1 1 read-only ERRF cache error flag 2 1 read-only IER IER ICACHE interrupt enable register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF BSYENDIE interrupt enable on busy end 1 1 read-write ERRIE interrupt enable on cache error 2 1 read-write FCR FCR ICACHE flag clear register 0xC 0x20 write-only 0x00000000 0xFFFFFFFF CBSYENDF clear busy end flag 1 1 write-only CERRF clear cache error flag 2 1 write-only HMONR HMONR ICACHE hit monitor register 0x10 0x20 read-only 0x00000000 0xFFFFFFFF HITMON cache hit monitor counter 0 32 read-only MMONR MMONR ICACHE miss monitor register 0x14 0x20 read-only 0x00000000 0xFFFFFFFF MISSMON cache miss monitor counter 0 16 read-only CRR0 CRR0 ICACHE region 0 configuration register 0x20 0x20 read-write 0x00000200 0xFFFFFFFF BASEADDR base address for region x 0 8 read-write RSIZE size for region x 9 3 read-write REN enable for region x 15 1 read-write REMAPADDR remapped address for region x 16 11 read-write MSTSEL AHB cache master selection for region x 28 1 read-write HBURST output burst type for region x 31 1 read-write CRR1 CRR1 ICACHE region 1 configuration register 0x24 0x20 read-write 0x00000200 0xFFFFFFFF BASEADDR base address for region x 0 8 read-write RSIZE size for region x 9 3 read-write REN enable for region x 15 1 read-write REMAPADDR remapped address for region x 16 11 read-write MSTSEL AHB cache master selection for region x 28 1 read-write HBURST output burst type for region x 31 1 read-write CRR2 CRR2 ICACHE region 2 configuration register 0x28 0x20 read-write 0x00000200 0xFFFFFFFF BASEADDR base address for region x 0 8 read-write RSIZE size for region x 9 3 read-write REN enable for region x 15 1 read-write REMAPADDR remapped address for region x 16 11 read-write MSTSEL AHB cache master selection for region x 28 1 read-write HBURST output burst type for region x 31 1 read-write CRR3 CRR3 ICACHE region 3 configuration register 0x2C 0x20 read-write 0x00000200 0xFFFFFFFF BASEADDR base address for region x 0 8 read-write RSIZE size for region x 9 3 read-write REN enable for region x 15 1 read-write REMAPADDR remapped address for region x 16 11 read-write MSTSEL AHB cache master selection for region x 28 1 read-write HBURST output burst type for region x 31 1 read-write ICACHE_S 0x50030400 IWDG IWDG address block description IWDG 0x40003000 0x0 0x18 registers IWDG Independent watchdog interrupt 35 KR KR IWDG key register 0x0 0x10 write-only 0x00000000 0x0000FFFF KEY Key value (write only, read 0x0000) 0 16 write-only KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR IWDG prescaler register 0x4 0x10 read-write 0x00000000 0x0000FFFF PR Prescaler divider 0 4 read-write PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 6 DivideBy512 Divider /512 7 DivideBy1024 Divider /1024 true RLR RLR IWDG reload register 0x8 0x10 read-write 0x00000FFF 0x0000FFFF RL Watchdog counter reload value 0 12 read-write 0 4095 SR SR IWDG status register 0xC 0x10 read-only 0x00000000 0x0000FFFF PVU Watchdog prescaler value update 0 1 read-only PVU Idle No update on-going 0 Busy Update on-going 1 RVU Watchdog counter reload value update 1 1 read-only WVU Watchdog counter window value update 2 1 read-only EWU Watchdog interrupt comparator value update 3 1 read-only ONF Watchdog enable status bit 8 1 read-only ONFR NotActivated IWDG is not activated 0 Activated IWDG is activated 1 EWIF Watchdog early interrupt flag 14 1 read-only EWIFR NotPending No pending interrupt 0 Pending Interrupt pending 1 WINR WINR IWDG window register 0x10 0x10 read-write 0x00000FFF 0x0000FFFF WIN Watchdog counter window value 0 12 read-write 0 4095 EWCR EWCR IWDG early wake-up interrupt register 0x14 0x10 read-write 0x00000000 0x0000FFFF EWIT Watchdog counter window value 0 12 read-write EWIC Watchdog early interrupt acknowledge 14 1 write-only EWIE Watchdog early interrupt enable 15 1 read-write IWDG_S 0x50003000 LPTIM1 LPTIM1 address block description LPTIM 0x44004400 0x0 0x38 registers LPTIM1 LPTIM1 global interrupt OR LPTimer1 AIT through EXTI line 64 ISR ISR LPTIM1 interrupt and status register [alternate] 0x0 0x20 read-only 0x00000000 0xFFFFFFFF CC1IF Compare 1 interrupt flag 0 1 read-only ARRM Autoreload match 1 1 read-only EXTTRIG External trigger edge event 2 1 read-only CMP1OK Compare register 1 update OK 3 1 read-only ARROK Autoreload register update OK 4 1 read-only UP Counter direction change down to up 5 1 read-only DOWN Counter direction change up to down 6 1 read-only UE LPTIM update event occurred 7 1 read-only REPOK Repetition register update OK 8 1 read-only CC2IF Compare 2 interrupt flag 9 1 read-only CMP2OK Compare register 2 update OK 19 1 read-only DIEROK Interrupt enable register update OK 24 1 read-only ISR_ALTERNATE1 ISR_ALTERNATE1 LPTIM1 interrupt and status register ISR 0x0 0x20 read-only 0x00000000 0xFFFFFFFF CC1IF capture 1 interrupt flag 0 1 read-only ARRM Autoreload match 1 1 read-only EXTTRIG External trigger edge event 2 1 read-only ARROK Autoreload register update OK 4 1 read-only UP Counter direction change down to up 5 1 read-only DOWN Counter direction change up to down 6 1 read-only UE LPTIM update event occurred 7 1 read-only REPOK Repetition register update OK 8 1 read-only CC2IF Capture 2 interrupt flag 9 1 read-only CC1OF Capture 1 over-capture flag 12 1 read-only CC2OF Capture 2 over-capture flag 13 1 read-only DIEROK Interrupt enable register update OK 24 1 read-only ICR ICR LPTIM1 interrupt clear register [alternate] 0x4 0x20 write-only 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag 0 1 write-only ARRMCF Autoreload match clear flag 1 1 write-only EXTTRIGCF External trigger valid edge clear flag 2 1 write-only CMP1OKCF Compare register 1 update OK clear flag 3 1 write-only ARROKCF Autoreload register update OK clear flag 4 1 write-only UPCF Direction change to UP clear flag 5 1 write-only DOWNCF Direction change to down clear flag 6 1 write-only UECF Update event clear flag 7 1 write-only REPOKCF Repetition register update OK clear flag 8 1 write-only CC2CF Capture/compare 2 clear flag 9 1 write-only CMP2OKCF Compare register 2 update OK clear flag 19 1 write-only DIEROKCF Interrupt enable register update OK clear flag 24 1 write-only ICR_ALTERNATE1 ICR_ALTERNATE1 LPTIM1 interrupt clear register ICR 0x4 0x20 write-only 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag 0 1 write-only ARRMCF Autoreload match clear flag 1 1 write-only EXTTRIGCF External trigger valid edge clear flag 2 1 write-only ARROKCF Autoreload register update OK clear flag 4 1 write-only UPCF Direction change to UP clear flag 5 1 write-only DOWNCF Direction change to down clear flag 6 1 write-only UECF Update event clear flag 7 1 write-only REPOKCF Repetition register update OK clear flag 8 1 write-only CC2CF Capture/compare 2 clear flag 9 1 write-only CC1OCF Capture/compare 1 over-capture clear flag 12 1 write-only CC2OCF Capture/compare 2 over-capture clear flag 13 1 write-only DIEROKCF Interrupt enable register update OK clear flag 24 1 write-only DIER DIER LPTIM1 interrupt enable register [alternate] 0x8 0x20 read-write 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write CMP1OKIE Compare register 1 update OK interrupt enable 3 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable 5 1 read-write DOWNIE Direction change to down Interrupt Enable 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable 9 1 read-write CMP2OKIE Compare register 2 update OK interrupt enable 19 1 read-write UEDE Update event DMA request enable 23 1 read-write DIER_ALTERNATE1 DIER_ALTERNATE1 LPTIM1 interrupt enable register DIER 0x8 0x20 read-write 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable 5 1 read-write DOWNIE Direction change to down Interrupt Enable 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable 9 1 read-write CC1OIE Capture/compare 1 over-capture interrupt enable 12 1 read-write CC2OIE Capture/compare 2 over-capture interrupt enable 13 1 read-write CC1DE Capture/compare 1 DMA request enable 16 1 read-write UEDE Update event DMA request enable 23 1 read-write CC2DE Capture/compare 2 DMA request enable 25 1 read-write CFGR CFGR LPTIM configuration register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF CKSEL Clock selector 0 1 read-write CKPOL Clock Polarity 1 2 read-write CKFLT Configurable digital filter for external clock 3 2 read-write TRGFLT Configurable digital filter for trigger 6 2 read-write PRESC Clock prescaler 9 3 read-write TRIGSEL Trigger selector 13 3 read-write TRIGEN Trigger enable and polarity 17 2 read-write TIMOUT Timeout enable 19 1 read-write WAVE Waveform shape 20 1 read-write WAVPOL Waveform shape polarity 21 1 read-write PRELOAD Registers update mode 22 1 read-write COUNTMODE counter mode enabled 23 1 read-write ENC Encoder mode enable 24 1 read-write CR CR LPTIM control register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF ENABLE LPTIM enable 0 1 read-write SNGSTRT LPTIM start in Single mode 1 1 read-write CNTSTRT Timer start in Continuous mode 2 1 read-write COUNTRST Counter reset 3 1 read-write RSTARE Reset after read enable 4 1 read-write CCR1 CCR1 LPTIM compare register 1 0x14 0x20 read-write 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 16 read-write ARR ARR LPTIM autoreload register 0x18 0x20 read-write 0x00000001 0xFFFFFFFF ARR Auto reload value 0 16 read-write CNT CNT LPTIM counter register 0x1C 0x20 read-only 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-only CFGR2 CFGR2 LPTIM configuration register 2 0x24 0x20 read-write 0x00000000 0xFFFFFFFF IN1SEL LPTIM input 1 selection 0 2 read-write IN2SEL LPTIM input 2 selection 4 2 read-write IC1SEL LPTIM input capture 1 selection 16 2 read-write IC2SEL LPTIM input capture 2 selection 20 2 read-write RCR RCR LPTIM repetition register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF REP Repetition register value 0 8 read-write CCMR1 CCMR1 LPTIM capture/compare mode register 1 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF CC1SEL Capture/compare 1 selection 0 1 read-write CC1E Capture/compare 1 output enable. 1 1 read-write CC1P Capture/compare 1 output polarity. 2 2 read-write IC1PSC Input capture 1 prescaler 8 2 read-write IC1F Input capture 1 filter 12 2 read-write CC2SEL Capture/compare 2 selection 16 1 read-write CC2E Capture/compare 2 output enable. 17 1 read-write CC2P Capture/compare 2 output polarity. 18 2 read-write IC2PSC Input capture 2 prescaler 24 2 read-write IC2F Input capture 2 filter 28 2 read-write CCR2 CCR2 LPTIM compare register 2 0x34 0x20 read-write 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 16 read-write LPTIM1_S 0x54004400 LPTIM2 LPTIM2 address block description LPTIM 0x40009400 LPTIM2 LPTIM2 global interrupt OR LPTimer2 AIT through EXTI line 70 LPTIM2_S 0x50009400 LPUART LPUART address block description LPUART 0x44002400 0x0 0x30 registers LPUART1 LPUART1 global interrupt OR LPUART1 R Wakeup OR LPUART1 T Wakeup Char(10)through EXTI line 63 CR1 CR1 LPUART control register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF UE LPUART enable 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM LPUART enable in low-power mode 1 1 read-write UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 RE Receiver enable 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wake-up method 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 DEDT Driver Enable deassertion time 16 5 read-write 0 31 DEAT Driver Enable assertion time 21 5 read-write 0 31 M1 Word length 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO Full interrupt enable 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 LPUART control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 STOP STOP bits 12 2 read-write STOP Stop1 1 stop bit 0 Stop2 2 stop bit 2 SWAP Swap TX/RX pins 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ADD Address of the LPUART node 24 8 read-write 0 255 CR3 CR3 LPUART control register 3 0x8 0x20 read-write 0x00000000 0xFFFFFFFF EIE Error interrupt enable 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 HDSEL Half-duplex selection 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 DMAR DMA enable receiver 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 OVRDIS Overrun Disable 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA Disable on reception Error 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 WUS Wake-up from low-power mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 WUFIE Wake-up from low-power mode interrupt enable 22 1 read-write WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 TXFTIE TXFIFO threshold interrupt enable 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 RXFTCFG Receive FIFO threshold configuration 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 CR3_ALTERNATE1 CR3_ALTERNATE1 LPUART control register 3 CR3 0x8 0x20 read-write 0x00000000 0xFFFFFFFF EIE Error interrupt enable 0 1 read-write HDSEL Half-duplex selection 3 1 read-write DMAR DMA enable receiver 6 1 read-write DMAT DMA enable transmitter 7 1 read-write RTSE RTS enable 8 1 read-write CTSE CTS enable 9 1 read-write CTSIE CTS interrupt enable 10 1 read-write OVRDIS Overrun Disable 12 1 read-write DDRE DMA Disable on reception Error 13 1 read-write DEM Driver enable mode 14 1 read-write DEP Driver enable polarity selection 15 1 read-write WUS0 Wake-up from low-power mode interrupt flag selection 20 1 read-write WUS1 Wake-up from low-power mode interrupt flag selection 21 1 read-write WUFIE Wake-up from low-power mode interrupt enable 22 1 read-write BRR BRR LPUART baud rate register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF BRR LPUART baud rate division (LPUARTDIV) 0 20 read-write 0 1048575 RQR RQR LPUART request register 0x18 0x20 write-only 0x00000000 0xFFFFFFFF SBKRQ Send break request 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR LPUART interrupt and status register 0x1C 0x20 read-only 0x008000C0 0xFFFFFFFF PE Parity error 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Start bit noise detection flag 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 CTSIF CTS interrupt flag 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 BUSY Busy flag 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wake-up from mute mode 19 1 read-only RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 WUF Wake-up from low-power mode flag 20 1 read-only TEACK Transmit enable acknowledge flag 21 1 read-only REACK Receive enable acknowledge flag 22 1 read-only TXFE TXFIFO Empty 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO Full 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 RXFT RXFIFO threshold flag 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR LPUART interrupt flag clear register 0x20 0x20 write-only 0x00000000 0xFFFFFFFF PECF Parity error clear flag 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 CTSCF CTS clear flag 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 CMCF Character match clear flag 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 WUCF Wake-up from low-power mode clear flag 20 1 write-only oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 RDR RDR LPUART receive data register 0x24 0x20 read-only 0x00000000 0xFFFFFFFF RDR Receive data value 0 9 read-only 0 511 TDR TDR LPUART transmit data register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF TDR Transmit data value 0 9 read-write 0 511 PRESC PRESC LPUART prescaler register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler 0 4 read-write PRESCALER Div1 /1 0 Div2 /2 1 Div4 /4 2 Div6 /6 3 Div8 /8 4 Div10 /10 5 Div12 /12 6 Div16 /16 7 Div32 /32 8 Div64 /64 9 Div128 /128 10 Div256 /256 11 LPUART_S 0x54002400 OCTOSPI OCTOSPI register block OCTOSPI 0x47001400 0x0 0x400 registers OCTOSPI1 OCTOSPI1 global interrupt 78 CR CR OCTOSPI control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF EN Enable 0 1 read-write EN Disabled OCTOSPI disabled 0 Enabled OCTOSPI enabled 1 ABORT Abort request 1 1 read-write ABORT NotRequested No abort requested 0 Requested Abort requested 1 DMAEN DMA enable 2 1 read-write DMAEN Disabled DMA disabled for Indirect mode 0 Enabled DMA enabled for Indirect mode 1 TCEN Timeout counter enable 3 1 read-write TCEN Disabled Timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in Memory-mapped mode 0 Enabled Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity 1 DMM Dual-memory configuration 6 1 read-write DMM Disabled Dual-memory configuration disabled 0 Enabled Dual-memory configuration enabled 1 MSEL External memory select 7 1 read-write MSEL EXT1 External memory 1 selected (data exchanged over IO[3:0]) 0 EXT2 External memory 2 selected (data exchanged over IO[7:4]) 1 FTHRES FIFO threshold level 8 5 read-write 0 31 TEIE Transfer error interrupt enable 16 1 read-write TEIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TCIE Transfer complete interrupt enable 17 1 read-write FTIE FIFO threshold interrupt enable 18 1 read-write SMIE Status-match interrupt enable 19 1 read-write TOIE Timeout interrupt enable 20 1 read-write APMS Automatic status-polling mode stop 22 1 read-write APMS Running Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI 0 StopMatch Automatic status-polling mode stops as soon as there is a match 1 PMM Polling match mode 23 1 read-write PMM ANDMatchMode AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register 0 ORMatchmode OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register 1 FMODE Functional mode 28 2 read-write FMODE IndirectWrite Indirect-write mode 0 IndirectRead Indirect-read mode 1 AutomaticPolling Automatic status-polling mode 2 MemoryMapped Memory-mapped mode 3 DCR1 DCR1 OCTOSPI device configuration register 1 0x8 0x20 read-write 0x00000000 0xFFFFFFFF CKMODE Clock mode 0/mode 3 0 1 read-write CKMODE Mode0 CLK must stay low while NCS is high (chip-select released). This is referred to as Mode 0 0 Mode3 CLK must stay high while NCS is high (chip-select released). This is referred to as Mode 3 1 FRCK Free running clock 1 1 read-write FRCK Disabled CLK is not free running 0 Enabled CLK is free running (always provided) 1 DLYBYP Delay block bypass 3 1 read-write DLYBYP DelayBlockEnabled The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral) 0 DelayBlockBypassed The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. The delay is shorter than when the delay block is not bypassed, even with the delay value set to minimum value in delay block 1 CSHT Chip-select high time 8 6 read-write 0 63 DEVSIZE Device size 16 5 read-write 0 31 MTYP Memory type 24 3 read-write MTYP MicronMode Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes 0 MacronixMode Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes 1 StandardMode Standard Mode 2 MacronixRamMode Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping 3 HyperBusMemoryMode HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected 4 HyperBusMode HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used 5 DCR2 DCR2 OCTOSPI device configuration register 2 0xC 0x20 read-write 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler 0 8 read-write 0 255 WRAPSIZE Wrap size 16 3 read-write WRAPSIZE NoWrappingSupport Wrapped reads are not supported by the memory 0 WrappingSize16 External memory supports wrap size of 16 bytes 2 WrappingSize32 External memory supports wrap size of 32 bytes 3 WrappingSize64 External memory supports wrap size of 64 bytes 4 WrappingSize128 External memory supports wrap size of 128 bytes 5 DCR3 DCR3 OCTOSPI device configuration register 3 0x10 0x20 read-write 0x00000000 0xFFFFFFFF CSBOUND NCS boundary 16 5 read-write 0 31 DCR4 DCR4 OCTOSPI device configuration register 4 0x14 0x20 read-write 0x00000000 0xFFFFFFFF REFRESH Refresh rate 0 32 read-write 0 4294967295 SR SR OCTOSPI status register 0x20 0x20 read-only 0x00000000 0xFFFFFFFF TEF Transfer error flag 0 1 read-only TEF Cleared This bit is cleared by writing 1 to CTEF 0 InvalidAddressAccessed This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode 1 TCF Transfer complete flag 1 1 read-only TCF Cleared This bit is cleared by writing 1 to CTCF 0 TransferCompleted This bit is set when the programmed number of data has been transferred 1 FTF FIFO threshold flag 2 1 read-only FTF Cleared It is cleared automatically as soon as the threshold condition is no longer true 0 ThresholdReached This bit is set when the FIFO threshold has been reached 1 SMF Status match flag 3 1 read-only SMF Cleared It is cleared by writing 1 to CSMF 0 Matched This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (OCTOSPI_PSMAR) 1 TOF Timeout flag 4 1 read-only TOF Cleared This bit is cleared by writing 1 to CTOF 0 Timeout This bit is set when timeout occurs 1 BUSY Busy 5 1 read-only BUSY Cleared This bit is cleared automatically when the operation with the external device is finished and the FIFO is empty 0 Busy This bit is set when an operation is ongoing 1 FLEVEL FIFO level 8 6 read-only 0 63 FCR FCR OCTOSPI flag clear register 0x24 0x20 write-only 0x00000000 0xFFFFFFFF CTEF Clear transfer error flag 0 1 write-only CTEF Clear Writing 1 clears the TEF flag in the OCTOSPI_SR register 1 CTCF Clear transfer complete flag 1 1 write-only CTCF Clear Writing 1 clears the TCF flag in the OCTOSPI_SR register 1 CSMF Clear status match flag 3 1 write-only CSMF Clear Writing 1 clears the SMF flag in the OCTOSPI_SR register 1 CTOF Clear timeout flag 4 1 write-only CTOF Clear Writing 1 clears the TOF flag in the OCTOSPI_SR register 1 DLR DLR OCTOSPI data length register 0x40 0x20 read-write 0x00000000 0xFFFFFFFF DL Data length 0 32 read-write 0 4294967295 AR AR OCTOSPI address register 0x48 0x20 read-write 0x00000000 0xFFFFFFFF ADDRESS Address 0 32 read-write 0 4294967295 DR DR OCTOSPI data register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write 0 4294967295 PSMKR PSMKR OCTOSPI polling status mask register 0x80 0x20 read-write 0x00000000 0xFFFFFFFF MASK Status mask 0 32 read-write 0 4294967295 PSMAR PSMAR OCTOSPI polling status match register 0x88 0x20 read-write 0x00000000 0xFFFFFFFF MATCH Status match 0 32 read-write 0 4294967295 PIR PIR OCTOSPI polling interval register 0x90 0x20 read-write 0x00000000 0xFFFFFFFF INTERVAL Polling interval 0 16 read-write 0 65535 CCR CCR OCTOSPI communication configuration register 0x100 0x20 read-write 0x00000000 0xFFFFFFFF IMODE Instruction mode 0 3 read-write IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR Instruction double transfer rate 3 1 read-write IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE Instruction size 4 2 read-write ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE Address mode 8 3 read-write ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR Address double transfer rate 11 1 read-write ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE Address size 12 2 read-write ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE Alternate-byte mode 16 3 read-write ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR Alternate- byte double transfer rate 19 1 read-write ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE Alternate-byte size 20 2 read-write ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE Data mode 24 3 read-write DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR Data double transfer rate 27 1 read-write DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQS enable 29 1 read-write DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 TCR TCR OCTOSPI timing configuration register 0x108 0x20 read-write 0x00000000 0xFFFFFFFF DCYC Number of dummy cycles 0 5 read-write 0 31 DHQC Delay hold quarter cycle 28 1 read-write DHQC NoDelay No delay hold 0 QuarterCycleHold 1/4 cycle hold 1 SSHIFT Sample shift 30 1 read-write SSHIFT NoShift No shift 0 HalfCycleShift 1/2 cycle shift 1 IR IR OCTOSPI instruction register 0x110 0x20 read-write 0x00000000 0xFFFFFFFF INSTRUCTION Instruction 0 32 read-write 0 4294967295 ABR ABR OCTOSPI alternate bytes register 0x120 0x20 read-write 0x00000000 0xFFFFFFFF ALTERNATE Alternate bytes 0 32 read-write 0 4294967295 LPTR LPTR OCTOSPI low-power timeout register 0x130 0x20 read-write 0x00000000 0xFFFFFFFF TIMEOUT Timeout period 0 16 read-write 0 65535 WPCCR WPCCR OCTOSPI wrap communication configuration register 0x140 0x20 read-write 0x00000000 0xFFFFFFFF IMODE Instruction mode 0 3 read-write IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR Instruction double transfer rate 3 1 read-write IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE Instruction size 4 2 read-write ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE Address mode 8 3 read-write ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR Address double transfer rate 11 1 read-write ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE Address size 12 2 read-write ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE Alternate-byte mode 16 3 read-write ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR Alternate-byte double transfer rate 19 1 read-write ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE Alternate-byte size 20 2 read-write ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE Data mode 24 3 read-write DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR Data double transfer rate 27 1 read-write DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQS enable 29 1 read-write DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 WPTCR WPTCR OCTOSPI wrap timing configuration register 0x148 0x20 read-write 0x00000000 0xFFFFFFFF DCYC Number of dummy cycles 0 5 read-write 0 31 DHQC Delay hold quarter cycle 28 1 read-write DHQC NoDelay No delay hold 0 QuarterCycleHold 1/4 cycle hold 1 SSHIFT Sample shift 30 1 read-write SSHIFT NoShift No shift 0 HalfCycleShift 1/2 cycle shift 1 WPIR WPIR OCTOSPI wrap instruction register 0x150 0x20 read-write 0x00000000 0xFFFFFFFF INSTRUCTION Instruction 0 32 read-write 0 4294967295 WPABR WPABR OCTOSPI wrap alternate bytes register 0x160 0x20 read-write 0x00000000 0xFFFFFFFF ALTERNATE Alternate bytes 0 32 read-write 0 4294967295 WCCR WCCR OCTOSPI write communication configuration register 0x180 0x20 read-write 0x00000000 0xFFFFFFFF IMODE Instruction mode 0 3 read-write IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 EightLines Instruction on eight lines 4 IDTR Instruction double transfer rate 3 1 read-write IDTR Disabled DTR mode disabled for instruction phase 0 Enabled DTR mode enabled for instruction phase 1 ISIZE Instruction size 4 2 read-write ISIZE Bits8 8-bit instruction 0 Bits16 16-bit instruction 1 Bits24 24-bit instruction 2 Bits32 32-bit instruction 3 ADMODE Address mode 8 3 read-write ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 EightLines Address on eight lines 4 ADDTR Address double transfer rate 11 1 read-write ADDTR Disabled DTR mode disabled for address phase 0 Enabled DTR mode enabled for address phase 1 ADSIZE Address size 12 2 read-write ADSIZE Bits8 8-bit address 0 Bits16 16-bit address 1 Bits24 24-bit address 2 Bits32 32-bit address 3 ABMODE Alternate-byte mode 16 3 read-write ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 EightLines Alternate bytes on eight lines 4 ABDTR Alternate bytes double transfer rate 19 1 read-write ABDTR Disabled DTR mode disabled for alternate bytes phase 0 Enabled DTR mode enabled for alternate bytes phase 1 ABSIZE Alternate-byte size 20 2 read-write ABSIZE Bits8 8-bit alternate bytes 0 Bits16 16-bit alternate bytes 1 Bits24 24-bit alternate bytes 2 Bits32 32-bit alternate bytes 3 DMODE Data mode 24 3 read-write DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 EightLines Data on eight lines 4 DDTR data double transfer rate 27 1 read-write DDTR Disabled DTR mode disabled for data phase 0 Enabled DTR mode enabled for data phase 1 DQSE DQS enable 29 1 read-write DQSE Disabled DQS disabled 0 Enabled DQS enabled 1 WTCR WTCR OCTOSPI write timing configuration register 0x188 0x20 read-write 0x00000000 0xFFFFFFFF DCYC Number of dummy cycles 0 5 read-write 0 31 WIR WIR OCTOSPI write instruction register 0x190 0x20 read-write 0x00000000 0xFFFFFFFF INSTRUCTION Instruction 0 32 read-write 0 4294967295 WABR WABR OCTOSPI write alternate bytes register 0x1A0 0x20 read-write 0x00000000 0xFFFFFFFF ALTERNATE Alternate bytes 0 32 read-write 0 4294967295 HLCR HLCR OCTOSPI HyperBus latency configuration register 0x200 0x20 read-write 0x00000000 0xFFFFFFFF LM Latency mode 0 1 read-write LM Variable Variable initial latency 0 Fixed Fixed latency 1 WZL Write zero latency 1 1 read-write WZL Disabled Latency on write accesses 0 Enabled No latency on write accesses 1 TACC Access time 8 8 read-write 0 255 TRWR Read-write minimum recovery time 16 8 read-write 0 255 OCTOSPI_S 0x57001400 OTFDEC1 OTFDEC register bank OTFDEC 0x46005000 0x0 0x400 registers OTFDEC1 OTFDEC1 secure global interrupt 115 CR CR OTFDEC control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF ENC Encryption mode bit 0 1 read-write PRIVCFGR PRIVCFGR OTFDEC privileged access control configuration register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF PRIV Privileged access protection. 0 1 read-write R1CFGR R1CFGR OTFDEC region 1 configuration register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REG_VERSION region firmware version 16 16 read-write R1STARTADDR R1STARTADDR OTFDEC region 1 start address register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF REG_START_ADDR Region AHB start address 0 32 read-write R1ENDADDR R1ENDADDR OTFDEC region 1 end address register 0x28 0x20 read-write 0x00000FFF 0xFFFFFFFF REG_END_ADDR Region AHB end address 0 32 read-write R1NONCER0 R1NONCER0 OTFDEC region 1 nonce register 0 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF REG_NONCE Region nonce, bits [31:0] 0 32 read-write R1NONCER1 R1NONCER1 OTFDEC region 1 nonce register 1 0x30 0x20 read-write 0x00000000 0xFFFFFFFF REG_NONCE Region nonce, bits [63:32] 0 32 read-write R1KEYR0 R1KEYR0 OTFDEC region 1 key register 0 0x34 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [31:0] 0 32 write-only R1KEYR1 R1KEYR1 OTFDEC region 1 key register 1 0x38 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [63:32] 0 32 write-only R1KEYR2 R1KEYR2 OTFDEC region 1 key register 2 0x3C 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [95:64] 0 32 write-only R1KEYR3 R1KEYR3 OTFDEC region 1 key register 3 0x40 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [127:96] 0 32 write-only R2CFGR R2CFGR OTFDEC region 2 configuration register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REG_VERSION region firmware version 16 16 read-write R2STARTADDR R2STARTADDR OTFDEC region 2 start address register 0x54 0x20 read-write 0x00000000 0xFFFFFFFF REG_START_ADDR Region AHB start address 0 32 read-write R2ENDADDR R2ENDADDR OTFDEC region 2 end address register 0x58 0x20 read-write 0x00000FFF 0xFFFFFFFF REG_END_ADDR Region AHB end address 0 32 read-write R2NONCER0 R2NONCER0 OTFDEC region 2 nonce register 0 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF REG_NONCE Region nonce, bits [31:0] 0 32 read-write R2NONCER1 R2NONCER1 OTFDEC region 2 nonce register 1 0x60 0x20 read-write 0x00000000 0xFFFFFFFF REG_NONCE Region nonce, bits [63:32] 0 32 read-write R2KEYR0 R2KEYR0 OTFDEC region 2 key register 0 0x64 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [31:0] 0 32 write-only R2KEYR1 R2KEYR1 OTFDEC region 2 key register 1 0x68 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [63:32] 0 32 write-only R2KEYR2 R2KEYR2 OTFDEC region 2 key register 2 0x6C 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [95:64] 0 32 write-only R2KEYR3 R2KEYR3 OTFDEC region 2 key register 3 0x70 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [127:96] 0 32 write-only R3CFGR R3CFGR OTFDEC region 3 configuration register 0x80 0x20 read-write 0x00000000 0xFFFFFFFF REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REG_VERSION region firmware version 16 16 read-write R3STARTADDR R3STARTADDR OTFDEC region 3 start address register 0x84 0x20 read-write 0x00000000 0xFFFFFFFF REG_START_ADDR Region AHB start address 0 32 read-write R3ENDADDR R3ENDADDR OTFDEC region 3 end address register 0x88 0x20 read-write 0x00000FFF 0xFFFFFFFF REG_END_ADDR Region AHB end address 0 32 read-write R3NONCER0 R3NONCER0 OTFDEC region 3 nonce register 0 0x8C 0x20 read-write 0x00000000 0xFFFFFFFF REG_NONCE Region nonce, bits [31:0] 0 32 read-write R3NONCER1 R3NONCER1 OTFDEC region 3 nonce register 1 0x90 0x20 read-write 0x00000000 0xFFFFFFFF REG_NONCE Region nonce, bits [63:32] 0 32 read-write R3KEYR0 R3KEYR0 OTFDEC region 3 key register 0 0x94 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [31:0] 0 32 write-only R3KEYR1 R3KEYR1 OTFDEC region 3 key register 1 0x98 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [63:32] 0 32 write-only R3KEYR2 R3KEYR2 OTFDEC region 3 key register 2 0x9C 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [95:64] 0 32 write-only R3KEYR3 R3KEYR3 OTFDEC region 3 key register 3 0xA0 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [127:96] 0 32 write-only R4CFGR R4CFGR OTFDEC region 4 configuration register 0xB0 0x20 read-write 0x00000000 0xFFFFFFFF REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REG_VERSION region firmware version 16 16 read-write R4STARTADDR R4STARTADDR OTFDEC region 4 start address register 0xB4 0x20 read-write 0x00000000 0xFFFFFFFF REG_START_ADDR Region AHB start address 0 32 read-write R4ENDADDR R4ENDADDR OTFDEC region 4 end address register 0xB8 0x20 read-write 0x00000FFF 0xFFFFFFFF REG_END_ADDR Region AHB end address 0 32 read-write R4NONCER0 R4NONCER0 OTFDEC region 4 nonce register 0 0xBC 0x20 read-write 0x00000000 0xFFFFFFFF REG_NONCE Region nonce, bits [31:0] 0 32 read-write R4NONCER1 R4NONCER1 OTFDEC region 4 nonce register 1 0xC0 0x20 read-write 0x00000000 0xFFFFFFFF REG_NONCE Region nonce, bits [63:32] 0 32 read-write R4KEYR0 R4KEYR0 OTFDEC region 4 key register 0 0xC4 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [31:0] 0 32 write-only R4KEYR1 R4KEYR1 OTFDEC region 4 key register 1 0xC8 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [63:32] 0 32 write-only R4KEYR2 R4KEYR2 OTFDEC region 4 key register 2 0xCC 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [95:64] 0 32 write-only R4KEYR3 R4KEYR3 OTFDEC region 4 key register 3 0xD0 0x20 write-only 0x00000000 0xFFFFFFFF REG_KEY Region key, bits [127:96] 0 32 write-only ISR ISR OTFDEC interrupt status register 0x300 0x20 read-only 0x00000000 0xFFFFFFFF SEIF Security error interrupt flag status 0 1 read-only XONEIF Execute-only execute-never error interrupt flag status 1 1 read-only KEIF Key error interrupt flag status 2 1 read-only ICR ICR OTFDEC interrupt clear register 0x304 0x20 write-only 0x00000000 0xFFFFFFFF SEIF Security error interrupt flag clear 0 1 write-only XONEIF Execute-only execute-never error interrupt flag clear 1 1 write-only KEIF Key error interrupt flag clear 2 1 write-only IER IER OTFDEC interrupt enable register 0x308 0x20 read-write 0x00000000 0xFFFFFFFF SEIE Security error interrupt enable 0 1 read-write XONEIE Execute-only execute-never error interrupt enable 1 1 read-write KEIE Key error interrupt enable 2 1 read-write OTFDEC1_S 0x56005000 PKA PKA register blank and RAM PKA 0x420C2000 0x0 0x2000 registers PKA PKA global interrupt 118 CR CR PKA control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF EN PKA enable 0 1 read-write START start the operation 1 1 read-write MODE PKA operation code 8 6 read-write PROCENDIE End of operation interrupt enable 17 1 read-write RAMERRIE RAM error interrupt enable 19 1 read-write ADDRERRIE Address error interrupt enable 20 1 read-write OPERRIE Operation error interrupt enable 21 1 read-write SR SR PKA status register 0x4 0x20 read-only 0x00000000 0xFFFFFFFF INITOK PKA initialization OK 0 1 read-only LMF Limited mode flag 1 1 read-only BUSY Busy flag 16 1 read-only PROCENDF PKA end of operation flag 17 1 read-only RAMERRF PKA RAM error flag 19 1 read-only ADDRERRF Address error flag 20 1 read-only OPERRF Operation error flag 21 1 read-only CLRFR CLRFR PKA clear flag register 0x8 0x20 write-only 0x00000000 0xFFFFFFFF PROCENDFC Clear PKA end of operation flag 17 1 write-only RAMERRFC Clear PKA RAM error flag 19 1 write-only ADDRERRFC Clear address error flag 20 1 write-only OPERRFC Clear operation error flag 21 1 write-only PKA_S 0x520C2000 PSSI PSSI register block PSSI 0x4202C400 0x0 0x400 registers CR CR PSSI control register 0x0 0x20 read-write 0x40000000 0xFFFFFFFF CKPOL Parallel data clock polarity 5 1 read-write CKPOL FallingEdge Falling edge active for inputs or rising edge active for outputs 0 RisingEdge Rising edge active for inputs or falling edge active for outputs 1 DEPOL Data enable (PSSI_DE) polarity 6 1 read-write DEPOL ActiveLow PSSI_DE active low (0 indicates that data is valid) 0 ActiveHigh PSSI_DE active high (1 indicates that data is valid) 1 RDYPOL Ready (PSSI_RDY) polarity 8 1 read-write RDYPOL ActiveLow PSSI_RDY active low (0 indicates that the receiver is ready to receive) 0 ActiveHigh PSSI_RDY active high (1 indicates that the receiver is ready to receive) 1 EDM Extended data mode 10 2 read-write EDM BitWidth8 Interface captures 8-bit data on every parallel data clock 0 BitWidth16 The interface captures 16-bit data on every parallel data clock 3 ENABLE PSSI enable 14 1 read-write ENABLE Disabled PSSI disabled 0 Enabled PSSI enabled 1 DERDYCFG Data enable and ready configuration 18 3 read-write DERDYCFG Disabled PSSI_DE and PSSI_RDY both disabled 0 Rdy Only PSSI_RDY enabled 1 De Only PSSI_DE enabled 2 RdyDeAlt Both PSSI_RDY and PSSI_DE alternate functions enabled 3 RdyDe Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin 4 RdyRemapped Only PSSI_RDY function enabled, but mapped to PSSI_DE pin 5 DeRemapped Only PSSI_DE function enabled, but mapped to PSSI_RDY pin 6 RdyDeBidi Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin 7 DMAEN DMA enable bit 30 1 read-write DMAEN Disabled DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled. 0 Enabled DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR 1 OUTEN Data direction selection bit 31 1 read-write OUTEN ReceiveMode Data is input synchronously with PSSI_PDCK 0 TransmitMode Data is output synchronously with PSSI_PDCK 1 SR SR PSSI status register 0x4 0x20 read-only 0x00000000 0xFFFFFFFF RTT4B FIFO is ready to transfer four bytes 2 1 read-only RTT4B NotReady FIFO is not ready for a four-byte transfer 0 Ready FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO 1 RTT1B FIFO is ready to transfer one byte 3 1 read-only RTT1B NotReady FIFO is not ready for a 1-byte transfer 0 Ready FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO 1 RIS RIS PSSI raw interrupt status register 0x8 0x20 read-only 0x00000000 0xFFFFFFFF OVR_RIS Data buffer overrun/underrun raw interrupt status 1 1 read-only OVR_RIS Cleared No overrun/underrun occurred 0 Occurred An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR 1 IER IER PSSI interrupt enable register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF OVR_IE Data buffer overrun/underrun interrupt enable 1 1 read-write OVR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if either an overrun or an underrun error occurred 1 MIS MIS PSSI masked interrupt status register 0x10 0x20 read-only 0x00000000 0xFFFFFFFF OVR_MIS Data buffer overrun/underrun masked interrupt status 1 1 read-only OVR_MIS Disabled No interrupt is generated when an overrun/underrun error occurs 0 Enabled An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER 1 ICR ICR PSSI interrupt clear register 0x14 0x20 write-only 0x00000000 0xFFFFFFFF OVR_ISC Data buffer overrun/underrun interrupt status clear 1 1 write-only OVR_ISC Clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS 1 DR DR PSSI data register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF BYTE0 Data byte 0 0 8 read-write 0 255 BYTE1 Data byte 1 8 8 read-write 0 255 BYTE2 Data byte 2 16 8 read-write 0 255 BYTE3 Data byte 3 24 8 read-write 0 255 PSSI_S 0x5202C400 PWR PWR address block description PWR 0x44020800 0x0 0x108 registers PMCR PMCR PWR power mode control register 0x0 0x20 read-write 0x0000000C 0xFFFFFFFF LPMS low-power mode selection 0 1 read-write LPMS StopMode Keeps Stop mode when entering DeepSleep 0 StandbyMode Allows Standby mode when entering DeepSleep 1 SVOS system Stop mode voltage scaling selection 2 2 read-write SVOS Scale5 SVOS5 scale 5 1 Scale4 SVOS4 scale 4 2 Scale3 SVOS3 scale 3 3 CSSF clear Standby and Stop flags (always read as 0) 7 1 read-write CSSF Clear STOPF and SBF flags cleared 1 FLPS flash memory low-power mode in Stop mode 9 1 read-write FLPS NormalMode Flash memory remains in normal mode when the system enters Stop mode 0 LowPowerMode Flash memory enters low-power mode when the system enters Stop mode 1 BOOSTE analog switch Vless thansub>BOOSTless than/sub> control 12 1 read-write BOOSTE Disabled Booster disabled 0 Enabled Booster enabled if analog voltage ready (AVD_READY = 1) 1 AVD_READY analog voltage ready 13 1 read-write AVD_READY NotReady Peripheral analog voltage VDDA not ready (default) 0 Ready Peripheral analog voltage VDDA ready 1 ETHERNETSO ETHERNET RAM shut-off in Stop mode. 16 1 read-write SRAM3SO AHB SRAM3 shut-off in Stop mode. 23 1 read-write SRAM2_16SO AHB SRAM2 16-Kbyte shut-off in Stop mode. 24 1 read-write SRAM2_16SO Kept AHB RAM2 content is kept in Stop mode 0 Lost AHB RAM2 content is lost in Stop mode 1 SRAM2_48SO AHB SRAM2 48-Kbyte shut-off in Stop mode. 25 1 read-write SRAM1SO AHB SRAM1 shut-off in Stop mode 26 1 read-write SRAM1SO Kept AHB RAM1 content is kept in Stop mode 0 Lost AHB RAM1 content is lost in Stop mode 1 PMCR_ALTERNATE1 PMCR_ALTERNATE1 PWR power mode control register PMCR 0x0 0x20 read-write 0x0000000C 0xFFFFFFFF LPMS low-power mode selection 0 1 read-write SVOS system Stop mode voltage scaling selection 2 2 read-write CSSF clear Standby and Stop flags (always read as 0) 7 1 read-write FLPS flash memory low-power mode in Stop mode 9 1 read-write BOOSTE analog switch Vless thansub>BOOSTless than/sub> control 12 1 read-write AVD_READY analog voltage ready 13 1 read-write SRAM3SO AHB SRAM3 shut-off in Stop mode. 23 1 read-write SRAM2_16LSO AHB SRAM2 low 16-Kbyte shut-off in Stop mode. 24 1 read-write SRAM2_16HSO AHB SRAM2 high 16-Kbyte shut-off in Stop mode. 25 1 read-write SRAM2_48SO AHB SRAM2 48-Kbyte shut-off in Stop mode. 26 1 read-write SRAM1SO AHB SRAM1 shut-off in Stop mode 27 1 read-write PMSR PMSR PWR status register 0x4 0x20 read-only 0x00000000 0xFFFFFFFF STOPF Stop flag 5 1 read-only STOPFR NoStopMode System has not been in stop mode 0 StopModePreviouslyEntered System has been in Stop mode 1 SBF System standby flag 6 1 read-only SBFR NoStandbyMode System has not been in standby mode 0 StandbyModePreviouslyEntered System has been in Standby mode 1 VOSCR VOSCR PWR voltage scaling control register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF VOS voltage scaling selection according to performance 4 2 read-write VOS VOS3 Scale 3 (default) 0 VOS1 Scale 1 1 VOS2 Scale 2 2 VOS0 Scale 0 3 VOSSR VOSSR PWR voltage scaling status register 0x14 0x20 read-only 0x00002008 0xFFFFFFFF VOSRDY Ready bit for Vless thansub>COREless than/sub> voltage scaling output selection. 3 1 read-only VOSRDYR NotReady Not ready, voltage level below VOS selected level 0 Ready Ready, voltage level at or above VOS selected level 1 ACTVOSRDY Voltage level ready for currently used VOS 13 1 read-only ACTVOSRDYR NotReady VCORE is above or below the current voltage scaling provided by ACTVOS[1:0] 0 Ready VCORE is equal to the current voltage scaling provided by ACTVOS[1:0] 1 ACTVOS voltage output scaling currently applied to Vless thansub>COREless than/sub> 14 2 read-only ACTVOSR VOS3 VOS3 (lowest power) 0 VOS2 VOS2 1 VOS1 VOS1 2 VOS0 VOS0 (highest frequency) 3 BDCR BDCR PWR Backup domain control register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF BREN Backup RAM retention in Standby and Vless thansub>BATless than/sub> modes 0 1 read-write BREN Disabled Backup regulator enabled; backup RAM content lost in Standby and VBAT modes 0 Enabled Backup regulator disabled; backup RAM content preserved in Standby and VBAT modes 1 MONEN Backup domain voltage and temperature monitoring enable 1 1 read-write MONEN Disabled Backup domain voltage and temperature monitoring disabled 0 Enabled Backup domain voltage and temperature monitoring enabled 1 VBE Vless thansub>BATless than/sub> charging enable 8 1 read-write VBE Disabled VBAT battery charging disabled 0 Enabled VBAT battery charging enabled 1 VBRS Vless thansub>BATless than/sub> charging resistor selection 9 1 read-write VBRS Charge5k Charge VBAT through a 5 kâ¦ resistor 0 Charge1k5 Charge VBAT through a 1.5 kâ¦ resistor 1 DBPCR DBPCR PWR Backup domain control register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF DBP Disable Backup domain write protection 0 1 read-write DBP Disabled Write access to backup domain disabled 0 Enabled Write access to backup domain enabled 1 BDSR BDSR PWR Backup domain status register 0x28 0x20 read-only 0x00000000 0xFFFFFFFF BRRDY backup regulator ready 16 1 read-only BRRDYR NotReady Backup regulator not ready 0 Ready Backup regulator ready 1 VBATL Vless thansub>BATless than/sub> level monitoring versus low threshold 20 1 read-only VBATLR AboveThreshold Above low threshold level 0 BelowThreshold Equal to or below low threshold level 1 VBATH Vless thansub>BATless than/sub> level monitoring versus high threshold 21 1 read-only VBATHR BelowThreshold Below high threshold level 0 AboveThreshold Equal to or Above high threshold level 1 TEMPL temperature level monitoring versus low threshold 22 1 read-only TEMPH temperature level monitoring versus high threshold 23 1 read-only UCPDR UCPDR PWR USB Type-C power delivery register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF UCPD_DBDIS USB Type-C and power delivery dead battery disable 0 1 read-write UCPD_STBY USB Type-c and Power delivery Standby mode 1 1 read-write SCCR SCCR PWR supply configuration control register 0x30 0x20 read-writeOnce 0x00000100 0xFFFFFFFF BYPASS power management unit bypass 0 1 read-writeOnce BYPASS InternalRegulator Power management unit normal operation. Use the internal regulator. 0 Bypassed Power management unit bypassed. Use the external power. 1 LDOEN LDO enable 8 1 read-only LDOENR Disabled Package does not use LDO regulator 0 Enabled Package uses LDO regulator 1 SMPSEN SMPS enable 9 1 read-only VMCR VMCR PWR voltage monitor control register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF PVDE PVD enable 0 1 read-write PVDE Disabled PVD Disabled 0 Enabled PVD Enabled 1 PLS programmable voltage detector (PVD) level selection 1 3 read-write PLS PvdLevel0 PVD level0 (VPVD0 around 1.95 V) 0 PvdLevel1 PVD level1 (VPVD1 around 2.1 V) 1 PvdLevel2 PVD level2 (VPVD2 around 2.25 V) 2 PvdLevel3 PVD level3 (VPVD3 around 2.4 V) 3 PvdLevel4 PVD level4 (VPVD4 around 2.55 V) 4 PvdLevel5 PVD level5 (VPVD5 around 2.7 V) 5 PvdLevel6 PVD level6 (VPVD6 around 2.85 V) 6 PvdIn PVD_IN pin 7 AVDEN peripheral voltage monitor on Vless thansub>DDAless than/sub> enable 8 1 read-write AVDEN Disabled Peripheral voltage monitor on VDDA disabled 0 Enabled Peripheral voltage monitor on VDDA enabled 1 ALS analog voltage detector (AVD) level selection 9 2 read-write ALS AvdLevel0 AVD level0 (VAVD0 around 1.7 V) 0 AvdLevel1 AVD level1 (VAVD1 around 2.1 V) 1 AvdLevel2 AVD level2 (VAVD2 around 2.5 V) 2 AvdLevel3 AVD level3 (VAVD3 around 2.8 V) 3 USBSCR USBSCR PWR USB supply control register 0x38 0x20 read-write 0x00000000 0xFFFFFFFF USB33DEN Vless thansub>DDUSBless than/sub> voltage level detector enable 24 1 read-write USB33SV independent USB supply valid 25 1 read-write VMSR VMSR PWR voltage monitor status register 0x3C 0x20 read-only 0x00000000 0xFF0FFFFF AVDO analog voltage detector output on Vless thansub>DDAless than/sub> 19 1 read-only AVDOR AboveThreshold VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits 0 BelowThreshold VDDA is lower than the AVD threshold selected with the ALS[2:0] bits 1 VDDIO2RDY voltage detector output on Vless thansub>DDIO2less than/sub> 20 1 read-only VDDIO2RDYR BelowThreshold VDDIO2 is below the threshold of the VDDIO2 voltage monitor 0 AboveThreshold VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor 1 PVDO programmable voltage detect output 22 1 read-only PVDOR AboveThreshold VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits. 0 BelowThreshold VDD is lower than the PVD threshold selected through the PLS[2:0] bits 1 USB33RDY Vless thansub>DDUSBless than/sub> ready 24 1 read-only WUSCR WUSCR PWR wake-up status clear register 0x40 0x20 write-only 0x00000000 0xFFFFFFFF CWUF1 clear wake-up pin flag for WUFx (x = 8 to 1) 0 1 write-only CWUF1W Clear Writing 1 clears the WUFx wakeup pin flag (bit is cleared to 0 by hardware) 1 CWUF2 clear wake-up pin flag for WUFx (x = 8 to 1) 1 1 write-only CWUF3 clear wake-up pin flag for WUFx (x = 8 to 1) 2 1 write-only CWUF4 clear wake-up pin flag for WUFx (x = 8 to 1) 3 1 write-only CWUF5 clear wake-up pin flag for WUFx (x = 8 to 1) 4 1 write-only CWUF6 clear wake-up pin flag for WUFx (x = 8 to 1) 5 1 write-only CWUF7 clear wake-up pin flag for WUFx (x = 8 to 1) 6 1 write-only CWUF8 clear wake-up pin flag for WUFx (x = 8 to 1) 7 1 write-only WUSR WUSR PWR wake-up status register 0x44 0x20 read-only 0x00000000 0xFFFFFFFF WUF1 wake-up pin WUFx flag 0 1 read-only WUF1R NoEventOccurred No wakeup event occurred 0 EventOccurred A wakeup event received from WUFx pin 1 WUF2 wake-up pin WUFx flag 1 1 read-only WUF3 wake-up pin WUFx flag 2 1 read-only WUF4 wake-up pin WUFx flag 3 1 read-only WUF5 wake-up pin WUFx flag 4 1 read-only WUF6 wake-up pin WUFx flag 5 1 read-only WUF7 wake-up pin WUFx flag 6 1 read-only WUF8 wake-up pin WUFx flag 7 1 read-only WUCR WUCR PWR wake-up configuration register 0x48 0x20 read-write 0x00000000 0xFFFFFFFF WUPEN1 enable wake-up pin WUPx (x = 8 to 1) 0 1 read-write WUPEN1 Disabled An event on WUPx pin does not wakeup the system from Standby mode 0 Enabled A rising or falling edge on WUPx pin wakes up the system from Standby mode 1 WUPEN2 enable wake-up pin WUPx (x = 8 to 1) 1 1 read-write WUPEN3 enable wake-up pin WUPx (x = 8 to 1) 2 1 read-write WUPEN4 enable wake-up pin WUPx (x = 8 to 1) 3 1 read-write WUPEN5 enable wake-up pin WUPx (x = 8 to 1) 4 1 read-write WUPEN6 enable wake-up pin WUPx (x = 8 to 1) 5 1 read-write WUPEN7 enable wake-up pin WUPx (x = 8 to 1) 6 1 read-write WUPEN8 enable wake-up pin WUPx (x = 8 to 1) 7 1 read-write WUPP1 wake-up pin polarity bit for WUPx (x = 8 to 1) 8 1 read-write WUPP1 HighLevel Detection on high level 0 LowLevel Detection on low level 1 WUPP2 wake-up pin polarity bit for WUPx (x = 8 to 1) 9 1 read-write WUPP3 wake-up pin polarity bit for WUPx (x = 8 to 1) 10 1 read-write WUPP4 wake-up pin polarity bit for WUPx (x = 8 to 1) 11 1 read-write WUPP5 wake-up pin polarity bit for WUPx (x = 8 to 1) 12 1 read-write WUPP6 wake-up pin polarity bit for WUPx (x = 8 to 1) 13 1 read-write WUPP7 wake-up pin polarity bit for WUPx (x = 8 to 1) 14 1 read-write WUPP8 wake-up pin polarity bit for WUPx (x = 8 to 1) 15 1 read-write WUPPUPD1 wake-up pin pull configuration for WKUPx (x = 8 to 1) 16 2 read-write WUPPUPD1 NoPull No pull-up or pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 WUPPUPD2 wake-up pin pull configuration for WKUPx (x = 8 to 1) 18 2 read-write WUPPUPD3 wake-up pin pull configuration for WKUPx (x = 8 to 1) 20 2 read-write WUPPUPD4 wake-up pin pull configuration for WKUPx (x = 8 to 1) 22 2 read-write WUPPUPD5 wake-up pin pull configuration for WKUPx (x = 8 to 1) 24 2 read-write WUPPUPD6 wake-up pin pull configuration for WKUPx (x = 8 to 1) 26 2 read-write WUPPUPD7 wake-up pin pull configuration for WKUPx (x = 8 to 1) 28 2 read-write WUPPUPD8 wake-up pin pull configuration for WKUPx (x = 8 to 1) 30 2 read-write IORETR IORETR PWR I/O retention register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF IORETEN IO retention enable 0 1 read-write IORETEN Disabled IO Retention mode is disabled 0 Enabled IO Retention mode is enabled 1 JTAGIORETEN IO retention enable for JTAG IOs 16 1 read-write JTAGIORETEN Disabled IO Retention mode is disabled 0 Enabled IO Retention mode is enabled 1 SECCFGR SECCFGR PWR security configuration register 0x100 0x20 read-write 0x00000000 0xFFFFFFFF WUP1SEC WUPx secure protection (x = 8 to 1) 0 1 read-write WUP2SEC WUPx secure protection (x = 8 to 1) 1 1 read-write WUP3SEC WUPx secure protection (x = 8 to 1) 2 1 read-write WUP4SEC WUPx secure protection (x = 8 to 1) 3 1 read-write WUP5SEC WUPx secure protection (x = 8 to 1) 4 1 read-write WUP6SEC WUPx secure protection (x = 8 to 1) 5 1 read-write WUP7SEC WUPx secure protection (x = 8 to 1) 6 1 read-write WUP8SEC WUPx secure protection (x = 8 to 1) 7 1 read-write RETSEC retention secure protection 11 1 read-write LPMSEC low-power modes secure protection 12 1 read-write SCMSEC supply configuration and monitoring secure protection. 13 1 read-write VBSEC Backup domain secure protection 14 1 read-write VUSBSEC voltage USB secure protection 15 1 read-write PRIVCFGR PRIVCFGR PWR privilege configuration register 0x104 0x20 read-write 0x00000000 0xFFFFFFFF SPRIV PWR secure functions privilege configuration 0 1 read-write NSPRIV PWR non-secure functions privilege configuration 1 1 read-write NSPRIV Unprivileged Read and write to PWR functions can be done by privileged or unprivileged access 0 Privileged Read and write to PWR functions can be done by privileged access only 1 PWR_S 0x54020800 RAMCFG RAMCFG address block description RAMCFG 0x40026000 0x0 0x12C registers RAMCFG RAM configuration global interrupt 5 M1CR M1CR RAMCFG memory 1 control register 0x0 0x20 read-write 0x00000000 0xFFFFFFF0 ECCE ECC enable. 0 1 read-write ALE Address latch enable 4 1 read-write SRAMER SRAM erase 8 1 read-write M1ISR M1ISR RAMCFG memory interrupt status register 0x8 0x20 read-only 0x00000000 0xFFFFFFFF SEDC ECC single error detected and corrected 0 1 read-only DED ECC double error detected 1 1 read-only SRAMBUSY SRAM busy with erase operation 8 1 read-only M1ERKEYR M1ERKEYR RAMCFG memory 1 erase key register 0x28 0x20 write-only 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only M2CR M2CR RAMCFG memory 2 control register 0x40 0x20 read-write 0x00000000 0xFFFFFFF0 ECCE ECC enable. 0 1 read-write ALE Address latch enable 4 1 read-write SRAMER SRAM erase 8 1 read-write M2IER M2IER RAMCFG memory 2 interrupt enable register 0x44 0x20 read-write 0x00000000 0xFFFFFFFF SEIE ECC single error interrupt enable 0 1 read-write DEIE ECC double error interrupt enable 1 1 read-write ECCNMI Double error NMI 3 1 read-write M2ISR M2ISR RAMCFG memory interrupt status register 0x48 0x20 read-only 0x00000000 0xFFFFFFFF SEDC ECC single error detected and corrected 0 1 read-only DED ECC double error detected 1 1 read-only SRAMBUSY SRAM busy with erase operation 8 1 read-only M2SEAR M2SEAR RAMCFG memory 2 ECC single error address register 0x4C 0x20 read-only 0x00000000 0xFFFFFFFF ESEA ECC single error address 0 32 read-only M2DEAR M2DEAR RAMCFG memory 2 ECC double error address register 0x50 0x20 read-only 0x00000000 0xFFFFFFFF EDEA ECC double error address 0 32 read-only M2ICR M2ICR RAMCFG memory 2 interrupt clear register 2 0x54 0x20 read-write 0x00000000 0xFFFFFFFF CSEDC Clear ECC single error detected and corrected 0 1 read-write CDED Clear ECC double error detected 1 1 read-write M2WPR1 M2WPR1 RAMCFG memory 2 write protection register 1 0x58 0x20 read-write 0x00000000 0xFFFFFFFF P0WP SRAM2 1-Kbyte page y write protection 0 1 read-write P1WP SRAM2 1-Kbyte page y write protection 1 1 read-write P2WP SRAM2 1-Kbyte page y write protection 2 1 read-write P3WP SRAM2 1-Kbyte page y write protection 3 1 read-write P4WP SRAM2 1-Kbyte page y write protection 4 1 read-write P5WP SRAM2 1-Kbyte page y write protection 5 1 read-write P6WP SRAM2 1-Kbyte page y write protection 6 1 read-write P7WP SRAM2 1-Kbyte page y write protection 7 1 read-write P8WP SRAM2 1-Kbyte page y write protection 8 1 read-write P9WP SRAM2 1-Kbyte page y write protection 9 1 read-write P10WP SRAM2 1-Kbyte page y write protection 10 1 read-write P11WP SRAM2 1-Kbyte page y write protection 11 1 read-write P12WP SRAM2 1-Kbyte page y write protection 12 1 read-write P13WP SRAM2 1-Kbyte page y write protection 13 1 read-write P14WP SRAM2 1-Kbyte page y write protection 14 1 read-write P15WP SRAM2 1-Kbyte page y write protection 15 1 read-write P16WP SRAM2 1-Kbyte page y write protection 16 1 read-write P17WP SRAM2 1-Kbyte page y write protection 17 1 read-write P18WP SRAM2 1-Kbyte page y write protection 18 1 read-write P19WP SRAM2 1-Kbyte page y write protection 19 1 read-write P20WP SRAM2 1-Kbyte page y write protection 20 1 read-write P21WP SRAM2 1-Kbyte page y write protection 21 1 read-write P22WP SRAM2 1-Kbyte page y write protection 22 1 read-write P23WP SRAM2 1-Kbyte page y write protection 23 1 read-write P24WP SRAM2 1-Kbyte page y write protection 24 1 read-write P25WP SRAM2 1-Kbyte page y write protection 25 1 read-write P26WP SRAM2 1-Kbyte page y write protection 26 1 read-write P27WP SRAM2 1-Kbyte page y write protection 27 1 read-write P28WP SRAM2 1-Kbyte page y write protection 28 1 read-write P29WP SRAM2 1-Kbyte page y write protection 29 1 read-write P30WP SRAM2 1-Kbyte page y write protection 30 1 read-write P31WP SRAM2 1-Kbyte page y write protection 31 1 read-write M2WPR2 M2WPR2 RAMCFG memory 2 write protection register 2 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF P32WP SRAM2 1-Kbyte page y write protection 0 1 read-write P33WP SRAM2 1-Kbyte page y write protection 1 1 read-write P34WP SRAM2 1-Kbyte page y write protection 2 1 read-write P35WP SRAM2 1-Kbyte page y write protection 3 1 read-write P36WP SRAM2 1-Kbyte page y write protection 4 1 read-write P37WP SRAM2 1-Kbyte page y write protection 5 1 read-write P38WP SRAM2 1-Kbyte page y write protection 6 1 read-write P39WP SRAM2 1-Kbyte page y write protection 7 1 read-write P40WP SRAM2 1-Kbyte page y write protection 8 1 read-write P41WP SRAM2 1-Kbyte page y write protection 9 1 read-write P42WP SRAM2 1-Kbyte page y write protection 10 1 read-write P43WP SRAM2 1-Kbyte page y write protection 11 1 read-write P44WP SRAM2 1-Kbyte page y write protection 12 1 read-write P45WP SRAM2 1-Kbyte page y write protection 13 1 read-write P46WP SRAM2 1-Kbyte page y write protection 14 1 read-write P47WP SRAM2 1-Kbyte page y write protection 15 1 read-write P48WP SRAM2 1-Kbyte page y write protection 16 1 read-write P49WP SRAM2 1-Kbyte page y write protection 17 1 read-write P50WP SRAM2 1-Kbyte page y write protection 18 1 read-write P51WP SRAM2 1-Kbyte page y write protection 19 1 read-write P52WP SRAM2 1-Kbyte page y write protection 20 1 read-write P53WP SRAM2 1-Kbyte page y write protection 21 1 read-write P54WP SRAM2 1-Kbyte page y write protection 22 1 read-write P55WP SRAM2 1-Kbyte page y write protection 23 1 read-write P56WP SRAM2 1-Kbyte page y write protection 24 1 read-write P57WP SRAM2 1-Kbyte page y write protection 25 1 read-write P58WP SRAM2 1-Kbyte page y write protection 26 1 read-write P59WP SRAM2 1-Kbyte page y write protection 27 1 read-write P60WP SRAM2 1-Kbyte page y write protection 28 1 read-write P61WP SRAM2 1-Kbyte page y write protection 29 1 read-write P62WP SRAM2 1-Kbyte page y write protection 30 1 read-write P63WP SRAM2 1-Kbyte page y write protection 31 1 read-write M2WPR3 M2WPR3 RAMCFG memory 2 write protection register 3 0x60 0x20 read-write 0x00000000 0xFFFFFFFF P64WP SRAM2 1-Kbyte page y write protection 0 1 read-write P65WP SRAM2 1-Kbyte page y write protection 1 1 read-write P66WP SRAM2 1-Kbyte page y write protection 2 1 read-write P67WP SRAM2 1-Kbyte page y write protection 3 1 read-write P68WP SRAM2 1-Kbyte page y write protection 4 1 read-write P69WP SRAM2 1-Kbyte page y write protection 5 1 read-write P70WP SRAM2 1-Kbyte page y write protection 6 1 read-write P71WP SRAM2 1-Kbyte page y write protection 7 1 read-write P72WP SRAM2 1-Kbyte page y write protection 8 1 read-write P73WP SRAM2 1-Kbyte page y write protection 9 1 read-write P74WP SRAM2 1-Kbyte page y write protection 10 1 read-write P75WP SRAM2 1-Kbyte page y write protection 11 1 read-write P76WP SRAM2 1-Kbyte page y write protection 12 1 read-write P77WP SRAM2 1-Kbyte page y write protection 13 1 read-write P78WP SRAM2 1-Kbyte page y write protection 14 1 read-write P79WP SRAM2 1-Kbyte page y write protection 15 1 read-write M2ECCKEYR M2ECCKEYR RAMCFG memory 2 ECC key register 0x64 0x20 write-only 0x00000000 0xFFFFFFFF ECCKEY ECC write protection key 0 8 write-only M2ERKEYR M2ERKEYR RAMCFG memory 2 erase key register 0x68 0x20 write-only 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only M3CR M3CR RAMCFG memory 3 control register 0x80 0x20 read-write 0x00000000 0xFFFFFFF0 ECCE ECC enable. 0 1 read-write ALE Address latch enable 4 1 read-write SRAMER SRAM erase 8 1 read-write M3IER M3IER RAMCFG memory 3 interrupt enable register 0x84 0x20 read-write 0x00000000 0xFFFFFFFF SEIE ECC single error interrupt enable 0 1 read-write DEIE ECC double error interrupt enable 1 1 read-write ECCNMI Double error NMI 3 1 read-write M3ISR M3ISR RAMCFG memory interrupt status register 0x88 0x20 read-only 0x00000000 0xFFFFFFFF SEDC ECC single error detected and corrected 0 1 read-only DED ECC double error detected 1 1 read-only SRAMBUSY SRAM busy with erase operation 8 1 read-only M3SEAR M3SEAR RAMCFG memory 3 ECC single error address register 0x8C 0x20 read-only 0x00000000 0xFFFFFFFF ESEA ECC single error address 0 32 read-only M3DEAR M3DEAR RAMCFG memory 3 ECC double error address register 0x90 0x20 read-only 0x00000000 0xFFFFFFFF EDEA ECC double error address 0 32 read-only M3ICR M3ICR RAMCFG memory 3 interrupt clear register 3 0x94 0x20 read-write 0x00000000 0xFFFFFFFF CSEDC Clear ECC single error detected and corrected 0 1 read-write CDED Clear ECC double error detected 1 1 read-write M3ECCKEYR M3ECCKEYR RAMCFG memory 3 ECC key register 0xA4 0x20 write-only 0x00000000 0xFFFFFFFF ECCKEY ECC write protection key 0 8 write-only M3ERKEYR M3ERKEYR RAMCFG memory 3 erase key register 0xA8 0x20 write-only 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only M4ERKEYR M4ERKEYR RAMCFG memory 4 erase key register 0xE8 0x20 write-only 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only M5CR M5CR RAMCFG memory 5 control register 0x100 0x20 read-write 0x00000000 0xFFFFFFF0 ECCE ECC enable. 0 1 read-write ALE Address latch enable 4 1 read-write SRAMER SRAM erase 8 1 read-write M5IER M5IER RAMCFG memory 5 interrupt enable register 0x104 0x20 read-write 0x00000000 0xFFFFFFFF SEIE ECC single error interrupt enable 0 1 read-write DEIE ECC double error interrupt enable 1 1 read-write ECCNMI Double error NMI 3 1 read-write M5ISR M5ISR RAMCFG memory interrupt status register 0x108 0x20 read-only 0x00000000 0xFFFFFFFF SEDC ECC single error detected and corrected 0 1 read-only DED ECC double error detected 1 1 read-only SRAMBUSY SRAM busy with erase operation 8 1 read-only M5SEAR M5SEAR RAMCFG memory 5 ECC single error address register 0x10C 0x20 read-only 0x00000000 0xFFFFFFFF ESEA ECC single error address 0 32 read-only M5DEAR M5DEAR RAMCFG memory 5 ECC double error address register 0x110 0x20 read-only 0x00000000 0xFFFFFFFF EDEA ECC double error address 0 32 read-only M5ICR M5ICR RAMCFG memory 5 interrupt clear register 5 0x114 0x20 read-write 0x00000000 0xFFFFFFFF CSEDC Clear ECC single error detected and corrected 0 1 read-write CDED Clear ECC double error detected 1 1 read-write M5ECCKEYR M5ECCKEYR RAMCFG memory 5 ECC key register 0x124 0x20 write-only 0x00000000 0xFFFFFFFF ECCKEY ECC write protection key 0 8 write-only M5ERKEYR M5ERKEYR RAMCFG memory 5 erase key register 0x128 0x20 write-only 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only RAMCFG_S 0x50026000 RCC RCC address block description RCC 0x44020C00 0x0 0x118 registers RCC_S RCC secure global interrupt 10 RCC RCC non-secure global interrupt 9 CR CR RCC clock control register 0x0 0x20 read-write 0x0000002B 0xFFFFFFFF HSION HSI clock enable 0 1 read-write HSION Off Clock Off 0 On Clock On 1 HSIRDY HSI clock ready flag 1 1 read-only HSIRDYR NotReady Clock not ready 0 Ready Clock ready 1 HSIKERON HSI clock enable in Stop mode 2 1 read-write HSIDIV HSI clock divider 3 2 read-write HSIDIV Div1 No division 0 Div2 Division by 2 1 Div4 Division by 4 2 Div8 Division by 8 3 HSIDIVF HSI divider flag 5 1 read-only HSIDIVFR NotPropagated New HSIDIV ratio has not yet propagated to hsi_ck 0 Propagated HSIDIV ratio has propagated to hsi_ck 1 CSION CSI clock enable 8 1 read-write CSIRDY CSI clock ready flag 9 1 read-only CSIKERON CSI clock enable in Stop mode 10 1 read-write HSI48ON HSI48 clock enable 12 1 read-write HSI48RDY HSI48 clock ready flag 13 1 read-only HSEON HSE clock enable 16 1 read-write HSERDY HSE clock ready flag 17 1 read-only HSEBYP HSE clock bypass 18 1 read-write HSEBYP NotBypassed HSE crystal oscillator not bypassed 0 Bypassed HSE crystal oscillator bypassed with external clock 1 HSECSSON HSE clock security system enable 19 1 read-write HSEEXT external high speed clock type in Bypass mode 20 1 read-write HSEEXT Analog HSE in analog mode 0 Digital HSE in digital mode 1 PLL1ON PLL1 enable 24 1 read-write PLL1RDY PLL1 clock ready flag 25 1 read-only PLL2ON PLL2 enable 26 1 read-write PLL2RDY PLL2 clock ready flag 27 1 read-only PLL3ON PLL3 enable 28 1 read-write PLL3RDY PLL3 clock ready flag 29 1 read-only HSICFGR HSICFGR RCC HSI calibration register 0x10 0x20 read-write 0x00400000 0xFFFFF000 HSICAL HSI clock calibration 0 12 read-only HSITRIM HSI clock trimming 16 7 read-write 0 127 CRRCR CRRCR RCC clock recovery RC register 0x14 0x20 read-only 0x00000000 0xFFFFF000 HSI48CAL Internal RC 48 MHz clock calibration 0 10 read-only CSICFGR CSICFGR RCC CSI calibration register 0x18 0x20 read-write 0x00200000 0xFFFFF000 CSICAL CSI clock calibration 0 8 read-write CSITRIM CSI clock trimming 16 6 read-write 0 63 CFGR1 CFGR1 RCC clock configuration register1 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF SW system clock and trace clock switch 0 2 read-write SW HSI HSI selected as system clock 0 CSI CSI selected as system clock 1 HSE HSE selected as system clock 2 PLL1 PLL1 selected as system clock 3 SWS system clock switch status 3 2 read-only SWSR HSI HSI oscillator used as system clock 0 CSI CSI oscillator used as system clock 1 HSE HSE oscillator used as system clock 2 PLL1 PLL1 used as system clock 3 STOPWUCK system clock selection after a wakeup from system Stop 6 1 read-write STOPWUCK HSI HSI selected as wake up clock from system Stop 0 CSI CSI selected as wake up clock from system Stop 1 STOPKERWUCK kernel clock selection after a wakeup from system Stop 7 1 read-write RTCPRE HSE division factor for RTC clock 8 6 read-write 0 63 TIMPRE timers clocks prescaler selection 15 1 read-write TIMPRE DefaultX2 Timer kernel clock equal to 2x pclk by default 0 DefaultX4 Timer kernel clock equal to 4x pclk by default 1 MCO1PRE MCO1 prescaler 18 4 read-write 0 15 MCO1SEL Microcontroller clock output 1 22 3 read-write MCO1SEL HSI HSI clock selected (hsi_ck) 0 LSE LSE clock selected (lse_ck) 1 HSE HSE clock selected (hse_ck) 2 PLL1_Q PLL1 clock selected (pll1_q_ck) 3 HSI48 HSI48 clock selected (hsi48_ck) 4 MCO2PRE MCO2 prescaler 25 4 read-write 0 15 MCO2SEL microcontroller clock output 2 29 3 read-write MCO2SEL SYSCLK System clock selected (sys_ck) 0 PLL2_P PLL2 oscillator clock selected (pll2_p_ck) 1 HSE HSE clock selected (hse_ck) 2 PLL1_P PLL1 clock selected (pll1_p_ck) 3 CSI CSI clock selected (csi_ck) 4 LSI LSI clock selected (lsi_ck) 5 CFGR2 CFGR2 RCC CPU domain clock configuration register 2 0x20 0x20 read-write 0x00000000 0xFFFFFFFF HPRE AHB prescaler 0 4 read-write HPRE Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 Div1 SYSCLK not divided true PPRE1 APB low-speed prescaler (APB1) 4 3 read-write PPRE1 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true PPRE2 APB high-speed prescaler (APB2) 8 3 read-write PPRE3 APB low-speed prescaler (APB3) 12 3 read-write AHB1DIS AHB1 clock disable 16 1 read-write AHB1DIS Enabled The selected clock is enabled 0 Disabled The selected clock is disabled 1 AHB2DIS AHB2 clock disable 17 1 read-write AHB4DIS AHB4 clock disable 19 1 read-write APB1DIS APB1 clock disable value 20 1 read-write APB2DIS APB2 clock disable value 21 1 read-write APB3DIS APB3 clock disable value. 22 1 read-write PLL1CFGR PLL1CFGR RCC PLL clock source selection register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF PLL1SRC PLL1M and PLLs clock source selection 0 2 read-write PLL1SRC None No clock sent to DIVMx dividers and PLLs 0 HSI HSI selected as PLL clock 1 CSI CSI selected as PLL clock 2 HSE HSE selected as PLL clock 3 PLL1RGE PLL1 input frequency range 2 2 read-write PLL1RGE Range1 Frequency is between 1 and 2 MHz 0 Range2 Frequency is between 2 and 4 MHz 1 Range4 Frequency is between 4 and 8 MHz 2 Range8 Frequency is between 8 and 16 MHz 3 PLL1FRACEN PLL1 fractional latch enable 4 1 read-write PLL1FRACEN Reset Reset latch to transfer FRACN to the Sigma-Delta modulator 0 Set Set latch to transfer FRACN to the Sigma-Delta modulator 1 PLL1VCOSEL PLL1 VCO selection 5 1 read-write PLL1VCOSEL WideVCO VCO frequency range 192 to 836 MHz 0 MediumVCO VCO frequency range 150 to 420 MHz 1 PLL1M prescaler for PLL1 8 6 read-write PLL1PEN PLL1 DIVP divider output enable 16 1 read-write PLL1PEN Disabled Clock output is disabled 0 Enabled Clock output is enabled 1 PLL1QEN PLL1 DIVQ divider output enable 17 1 read-write PLL1REN PLL1 DIVR divider output enable 18 1 read-write PLL2CFGR PLL2CFGR RCC PLL clock source selection register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF PLL2SRC PLL2M and PLLs clock source selection 0 2 read-write PLL2SRC None No clock sent to DIVMx dividers and PLLs 0 HSI HSI selected as PLL clock 1 CSI CSI selected as PLL clock 2 HSE HSE selected as PLL clock 3 PLL2RGE PLL2 input frequency range 2 2 read-write PLL2RGE Range1 Frequency is between 1 and 2 MHz 0 Range2 Frequency is between 2 and 4 MHz 1 Range4 Frequency is between 4 and 8 MHz 2 Range8 Frequency is between 8 and 16 MHz 3 PLL2FRACEN PLL2 fractional latch enable 4 1 read-write PLL2FRACEN Reset Reset latch to transfer FRACN to the Sigma-Delta modulator 0 Set Set latch to transfer FRACN to the Sigma-Delta modulator 1 PLL2VCOSEL PLL2 VCO selection 5 1 read-write PLL2VCOSEL WideVCO VCO frequency range 192 to 836 MHz 0 MediumVCO VCO frequency range 150 to 420 MHz 1 PLL2M prescaler for PLL2 8 6 read-write PLL2PEN PLL2 DIVP divider output enable 16 1 read-write PLL2PEN Disabled Clock output is disabled 0 Enabled Clock output is enabled 1 PLL2QEN PLL2 DIVQ divider output enable 17 1 read-write PLL2REN PLL2 DIVR divider output enable 18 1 read-write PLL3CFGR PLL3CFGR RCC PLL clock source selection register 0x30 0x20 read-write 0x00000000 0xFFFFFFFF PLL3SRC PLL3M and PLLs clock source selection 0 2 read-write PLL3SRC None No clock sent to DIVMx dividers and PLLs 0 HSI HSI selected as PLL clock 1 CSI CSI selected as PLL clock 2 HSE HSE selected as PLL clock 3 PLL3RGE PLL3 input frequency range 2 2 read-write PLL3RGE Range1 Frequency is between 1 and 2 MHz 0 Range2 Frequency is between 2 and 4 MHz 1 Range4 Frequency is between 4 and 8 MHz 2 Range8 Frequency is between 8 and 16 MHz 3 PLL3FRACEN PLL3 fractional latch enable 4 1 read-write PLL3FRACEN Reset Reset latch to transfer FRACN to the Sigma-Delta modulator 0 Set Set latch to transfer FRACN to the Sigma-Delta modulator 1 PLL3VCOSEL PLL3 VCO selection 5 1 read-write PLL3VCOSEL WideVCO VCO frequency range 192 to 836 MHz 0 MediumVCO VCO frequency range 150 to 420 MHz 1 PLL3M prescaler for PLL3 8 6 read-write PLL3PEN PLL3 DIVP divider output enable 16 1 read-write PLL3PEN Disabled Clock output is disabled 0 Enabled Clock output is enabled 1 PLL3QEN PLL3 DIVQ divider output enable 17 1 read-write PLL3REN PLL3 DIVR divider output enable 18 1 read-write PLL1DIVR PLL1DIVR RCC PLL1 dividers register 0x34 0x20 read-write 0x01010280 0xFFFFFFFF PLL1N Multiplication factor for PLL1VCO 0 9 read-write 3 511 PLL1P PLL1 DIVP division factor 9 7 read-write 0 127 PLL1Q PLL1 DIVQ division factor 16 7 read-write 0 127 PLL1R PLL1 DIVR division factor 24 7 read-write 0 127 PLL1FRACR PLL1FRACR RCC PLL1 fractional divider register 0x38 0x20 read-write 0x00000000 0xFFFFFFFF PLL1FRACN fractional part of the multiplication factor for PLL1 VCO 3 13 read-write 0 8191 PLL2DIVR PLL2DIVR RCC PLL1 dividers register 0x3C 0x20 read-write 0x01010280 0xFFFFFFFF PLL2N Multiplication factor for PLL2VCO 0 9 read-write 3 511 PLL2P PLL2 DIVP division factor 9 7 read-write 0 127 PLL2Q PLL2 DIVQ division factor 16 7 read-write 0 127 PLL2R PLL2 DIVR division factor 24 7 read-write 0 127 PLL2FRACR PLL2FRACR RCC PLL2 fractional divider register 0x40 0x20 read-write 0x00000000 0xFFFFFFFF PLL2FRACN fractional part of the multiplication factor for PLL2 VCO 3 13 read-write 0 8191 PLL3DIVR PLL3DIVR RCC PLL3 dividers register 0x44 0x20 read-write 0x01010280 0xFFFFFFFF PLL3N Multiplication factor for PLL3VCO 0 9 read-write 3 511 PLL3P PLL3 DIVP division factor 9 7 read-write 0 127 PLL3Q PLL3 DIVQ division factor 16 7 read-write 0 127 PLL3R PLL3 DIVR division factor 24 7 read-write 0 127 PLL3FRACR PLL3FRACR RCC PLL3 fractional divider register 0x48 0x20 read-write 0x00000000 0xFFFFFFFF PLL3FRACN fractional part of the multiplication factor for PLL3 VCO 3 13 read-write 0 8191 CIER CIER RCC clock source interrupt enable register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF LSIRDYIE LSI ready interrupt enable 0 1 read-write LSIRDYIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 LSERDYIE LSE ready interrupt enable 1 1 read-write CSIRDYIE CSI ready interrupt enable 2 1 read-write HSIRDYIE HSI ready interrupt enable 3 1 read-write HSERDYIE HSE ready interrupt enable 4 1 read-write HSI48RDYIE HSI48 ready interrupt enable 5 1 read-write PLL1RDYIE PLL1 ready interrupt enable 6 1 read-write PLL2RDYIE PLL2 ready interrupt enable 7 1 read-write PLL3RDYIE PLL3 ready interrupt enable 8 1 read-write CIFR CIFR RCC clock source interrupt flag register 0x54 0x20 read-only 0x00000000 0xFFFFFFFF LSIRDYF LSI ready interrupt flag 0 1 read-only LSIRDYFR NotInterrupted No clock ready interrupt 0 Interrupted Clock ready interrupt 1 LSERDYF LSE ready interrupt flag 1 1 read-only CSIRDYF CSI ready interrupt flag 2 1 read-only HSIRDYF HSI ready interrupt flag 3 1 read-only HSERDYF HSE ready interrupt flag 4 1 read-only HSI48RDYF HSI48 ready interrupt flag 5 1 read-only PLL1RDYF PLL1 ready interrupt flag 6 1 read-only PLL2RDYF PLL2 ready interrupt flag 7 1 read-only PLL3RDYF PLL3 ready interrupt flag 8 1 read-only HSECSSF HSE clock security system interrupt flag 10 1 read-only HSECSSFR NoInterrupt No clock security interrupt caused by HSE clock failure 0 Interrupt Clock security interrupt caused by HSE clock failure 1 CICR CICR RCC clock source interrupt clear register 0x58 0x20 read-write 0x00000000 0xFFFFFFFF LSIRDYC LSI ready interrupt clear 0 1 read-write LSIRDYC Clear Clear interrupt flag 1 LSERDYC LSE ready interrupt clear 1 1 read-write CSIRDYC HSI ready interrupt clear 2 1 read-write HSIRDYC HSI ready interrupt clear 3 1 read-write HSERDYC HSE ready interrupt clear 4 1 read-write HSI48RDYC HSI48 ready interrupt clear 5 1 read-write PLL1RDYC PLL1 ready interrupt clear 6 1 read-write PLL2RDYC PLL2 ready interrupt clear 7 1 read-write PLL3RDYC PLL3 ready interrupt clear 8 1 read-write HSECSSC HSE clock security system interrupt clear 10 1 read-write AHB1RSTR AHB1RSTR RCC AHB1 reset register 0x60 0x20 read-write 0x00000000 0xFFFFFFFF GPDMA1RST GPDMA1 block reset 0 1 read-write GPDMA1RST Reset Reset the selected module 1 GPDMA2RST GPDMA2 block reset 1 1 read-write CRCRST CRC block reset Set and reset by software. 12 1 read-write CORDICRST CORDIC block reset 14 1 read-write FMACRST FMAC block reset 15 1 read-write RAMCFGRST RAMCFG block reset 17 1 read-write ETHRST ETHRST block reset 19 1 read-write AHB2RSTR AHB2RSTR RCC AHB2 peripheral reset register 0x64 0x20 read-write 0x00000000 0xFFFFFFFF GPIOARST GPIOA block reset 0 1 read-write GPIOARST Reset Reset the selected module 1 GPIOBRST GPIOB block reset 1 1 read-write GPIOCRST GPIOC block reset 2 1 read-write GPIODRST GPIOD block reset 3 1 read-write GPIOERST GPIOE block reset 4 1 read-write GPIOFRST GPIOF block reset 5 1 read-write GPIOGRST GPIOG block reset 6 1 read-write GPIOHRST GPIOH block reset 7 1 read-write GPIOIRST GPIOI block reset 8 1 read-write ADCRST ADC1 and 2 blocks reset 10 1 read-write DAC1RST DAC block reset 11 1 read-write DCMI_PSSIRST digital camera interface block reset (DCMI or PSSI depending which interface is active) 12 1 read-write AESRST AES block reset 16 1 read-write HASHRST HASH block reset 17 1 read-write RNGRST RNG block reset 18 1 read-write PKARST PKA block reset 19 1 read-write SAESRST SAES block reset 20 1 read-write AHB4RSTR AHB4RSTR RCC AHB4 peripheral reset register 0x6C 0x20 read-write 0x00000000 0xFFFFFFFF OTFDEC1RST OTFDEC1 block reset 7 1 read-write OTFDEC1RST Reset Reset the selected module 1 SDMMC1RST SDMMC1 and SDMMC1 delay blocks reset 11 1 read-write FMCRST FMC block reset 16 1 read-write OCTOSPI1RST OCTOSPI1 block reset 20 1 read-write APB1LRSTR APB1LRSTR RCC APB1 peripheral low reset register 0x74 0x20 read-write 0x00000000 0xFFFFFFFF TIM2RST TIM2 block reset 0 1 read-write TIM2RST Reset Reset the selected module 1 TIM3RST TIM3 block reset 1 1 read-write TIM4RST TIM4 block reset 2 1 read-write TIM5RST TIM5 block reset 3 1 read-write TIM6RST TIM6 block reset 4 1 read-write TIM7RST TIM7 block reset 5 1 read-write TIM12RST TIM12 block reset 6 1 read-write SPI2RST SPI2 block reset 14 1 read-write SPI3RST SPI3 block reset 15 1 read-write USART2RST USART2 block reset 17 1 read-write USART3RST USART3 block reset 18 1 read-write UART4RST UART4 block reset 19 1 read-write UART5RST UART5 block reset 20 1 read-write I2C1RST I2C1 block reset 21 1 read-write I2C2RST I2C2 block reset 22 1 read-write I3C1RST I3C1 block reset 23 1 read-write CRSRST CRS block reset 24 1 read-write USART6RST USART6 block reset 25 1 read-write USART10RST USART10 block reset 26 1 read-write USART11RST USART11 block reset 27 1 read-write CECRST HDMI-CEC block reset 28 1 read-write UART7RST UART7 block reset 30 1 read-write UART8RST UART8 block reset 31 1 read-write APB1HRSTR APB1HRSTR RCC APB1 peripheral high reset register 0x78 0x20 read-write 0x00000000 0xFFFFFFFF UART9RST UART9 block reset 0 1 read-write UART9RST Reset Reset the selected module 1 UART12RST UART12 block reset 1 1 read-write DTSRST DTS block reset 3 1 read-write LPTIM2RST LPTIM2 block reset 5 1 read-write FDCANRST FDCAN1 and FDCAN2 blocks reset 9 1 read-write UCPD1RST UCPD1 block reset 23 1 read-write APB2RSTR APB2RSTR RCC APB2 peripheral reset register 0x7C 0x20 read-write 0x00000000 0xFFFFFFFF TIM1RST TIM1 block reset 11 1 read-write TIM1RST Reset Reset the selected module 1 SPI1RST SPI1 block reset 12 1 read-write TIM8RST TIM8 block reset 13 1 read-write USART1RST USART1 block reset 14 1 read-write TIM15RST TIM15 block reset 16 1 read-write SPI4RST SPI4 block reset 19 1 read-write SPI6RST SPI6 block reset 20 1 read-write SAI1RST SAI1 block reset 21 1 read-write SAI2RST SAI2 block reset 22 1 read-write USBRST USB block reset 24 1 read-write APB3RSTR APB3RSTR RCC APB3 peripheral reset register 0x80 0x20 read-write 0x00000000 0xFFFFFFFF LPUART1RST LPUART1 block reset 6 1 read-write LPUART1RST Reset Reset the selected module 1 I2C3RST I2C3 block reset 7 1 read-write I3C2RST I3C2 block reset 9 1 read-write LPTIM1RST LPTIM1 block reset 11 1 read-write LPTIM3RST LPTIM3 block reset 12 1 read-write LPTIM4RST LPTIM4 block reset 13 1 read-write LPTIM5RST LPTIM5 block reset 14 1 read-write LPTIM6RST LPTIM6 block reset 15 1 read-write VREFRST VREFBUF block reset 20 1 read-write AHB1ENR AHB1ENR RCC AHB1 peripherals clock register 0x88 0x20 read-write 0xD0000100 0xFFFFFFFF GPDMA1EN GPDMA1 clock enable 0 1 read-write GPDMA1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 GPDMA2EN GPDMA2 clock enable 1 1 read-write FLITFEN Flash interface clock enable 8 1 read-write CRCEN CRC clock enable 12 1 read-write CORDICEN CORDIC clock enable 14 1 read-write FMACEN FMAC clock enable 15 1 read-write RAMCFGEN RAMCFG clock enable 17 1 read-write ETHEN ETH clock enable 19 1 read-write ETHTXEN ETHTX clock enable 20 1 read-write ETHRXEN ETHRX clock enable 21 1 read-write TZSC1EN TZSC1 clock enable 24 1 read-write BKPRAMEN BKPRAM clock enable 28 1 read-write DCACHEEN DCACHE clock enable 30 1 read-write SRAM1EN SRAM1 clock enable 31 1 read-write AHB2ENR AHB2ENR RCC AHB2 peripheral clock register 0x8C 0x20 read-write 0xC0000000 0xFFFFFFFF GPIOAEN GPIOA clock enable 0 1 read-write GPIOAEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 GPIOBEN GPIOB clock enable 1 1 read-write GPIOCEN GPIOC clock enable 2 1 read-write GPIODEN GPIOD clock enable 3 1 read-write GPIOEEN GPIOE clock enable 4 1 read-write GPIOFEN GPIOF clock enable 5 1 read-write GPIOGEN GPIOG clock enable 6 1 read-write GPIOHEN GPIOH clock enable 7 1 read-write GPIOIEN GPIOI clock enable 8 1 read-write ADCEN ADC1 and 2 peripherals clock enable 10 1 read-write DAC1EN DAC clock enable 11 1 read-write DCMI_PSSIEN digital camera interface clock enable (DCMI or PSSI depending which interface is active) 12 1 read-write AESEN AES clock enable 16 1 read-write HASHEN HASH clock enable 17 1 read-write RNGEN RNG clock enable 18 1 read-write PKAEN PKA clock enable 19 1 read-write SAESEN SAES clock enable 20 1 read-write SRAM2EN SRAM2 clock enable 30 1 read-write SRAM3EN SRAM3 clock enable 31 1 read-write AHB4ENR AHB4ENR RCC AHB4 peripheral clock register 0x94 0x20 read-write 0x00000000 0xFFFFFFFF OTFDEC1EN OTFDEC1 clock enable 7 1 read-write OTFDEC1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 SDMMC1EN SDMMC1 and SDMMC1 delay peripheral clock enable reset 11 1 read-write FMCEN FMC clock enable 16 1 read-write OCTOSPI1EN OCTOSPI1 clock enable 20 1 read-write APB1LENR APB1LENR RCC APB1 peripheral clock register 0x9C 0x20 read-write 0x00000000 0xFFFFFFFF TIM2EN TIM2 clock enable 0 1 read-write TIM2EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM3EN TIM3 clock enable 1 1 read-write TIM4EN TIM4 clock enable 2 1 read-write TIM5EN TIM5 clock enable 3 1 read-write TIM6EN TIM6 clock enable 4 1 read-write TIM7EN TIM7 clock enable 5 1 read-write TIM12EN TIM12 clock enable 6 1 read-write WWDGEN WWDG clock enable 11 1 read-write SPI2EN SPI2 clock enable 14 1 read-write SPI3EN SPI3 clock enable 15 1 read-write USART2EN USART2 clock enable 17 1 read-write USART3EN USART3 clock enable 18 1 read-write UART4EN UART4 clock enable 19 1 read-write UART5EN UART5 clock enable 20 1 read-write I2C1EN I2C1 clock enable 21 1 read-write I2C2EN I2C2 clock enable 22 1 read-write I3C1EN I3C1 clock enable 23 1 read-write CRSEN CRS clock enable 24 1 read-write USART6EN USART6 clock enable 25 1 read-write USART10EN USART10 clock enable 26 1 read-write USART11EN USART11 clock enable 27 1 read-write CECEN HDMI-CEC clock enable 28 1 read-write UART7EN UART7 clock enable 30 1 read-write UART8EN UART8 clock enable 31 1 read-write APB1HENR APB1HENR RCC APB1 peripheral clock register 0xA0 0x20 read-write 0x00000000 0xFFFFFFFF UART9EN UART9 clock enable 0 1 read-write UART9EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 UART12EN UART12 clock enable 1 1 read-write DTSEN DTS clock enable 3 1 read-write LPTIM2EN LPTIM2 clock enable 5 1 read-write FDCANEN FDCAN1 and FDCAN2 peripheral clock enable 9 1 read-write UCPD1EN UCPD1 clock enable 23 1 read-write APB2ENR APB2ENR RCC APB2 peripheral clock register 0xA4 0x20 read-write 0x00000000 0xFFFFFFFF TIM1EN TIM1 clock enable 11 1 read-write TIM1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 SPI1EN SPI1 clock enable 12 1 read-write TIM8EN TIM8 clock enable 13 1 read-write USART1EN USART1 clock enable 14 1 read-write TIM15EN TIM15 clock enable 16 1 read-write SPI4EN SPI4 clock enable 19 1 read-write SPI6EN SPI6 clock enable 20 1 read-write SAI1EN SAI1 clock enable 21 1 read-write SAI2EN SAI2 clock enable 22 1 read-write USBEN USB clock enable 24 1 read-write APB3ENR APB3ENR RCC APB3 peripheral clock register 0xA8 0x20 read-write 0x00000000 0xFFFFFFFF SBSEN SBS clock enable 1 1 read-write SBSEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 LPUART1EN LPUART1 clock enable 6 1 read-write I2C3EN I2C3 clock enable 7 1 read-write I3C2EN I3C2 clock enable 9 1 read-write LPTIM1EN LPTIM1 clock enable 11 1 read-write LPTIM3EN LPTIM3 clock enable 12 1 read-write LPTIM4EN LPTIM4 clock enable 13 1 read-write LPTIM5EN LPTIM5 clock enable 14 1 read-write LPTIM6EN LPTIM6 clock enable 15 1 read-write VREFEN VREFBUF clock enable 20 1 read-write RTCAPBEN RTC APB interface clock enable 21 1 read-write AHB1LPENR AHB1LPENR RCC AHB1 sleep clock register 0xB0 0x20 read-write 0xF1021103 0xFFFFFFFF GPDMA1LPEN GPDMA1 clock enable during Sleep mode 0 1 read-write GPDMA1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 GPDMA2LPEN GPDMA2 clock enable during Sleep mode 1 1 read-write FLITFLPEN Flash interface (FLITF) clock enable during Sleep mode 8 1 read-write CRCLPEN CRC clock enable during Sleep mode 12 1 read-write CORDICLPEN CORDIC clock enable during Sleep mode 14 1 read-write FMACLPEN FMAC clock enable during Sleep mode 15 1 read-write RAMCFGLPEN RAMCFG clock enable during Sleep mode 17 1 read-write ETHLPEN ETH clock enable during Sleep mode 19 1 read-write ETHTXLPEN ETHTX clock enable during Sleep mode 20 1 read-write ETHRXLPEN ETHRX clock enable during Sleep mode 21 1 read-write TZSC1LPEN TZSC1 clock enable during Sleep mode 24 1 read-write BKPRAMLPEN BKPRAM clock enable during Sleep mode 28 1 read-write ICACHELPEN ICACHE clock enable during Sleep mode 29 1 read-write DCACHELPEN DCACHE clock enable during Sleep mode 30 1 read-write SRAM1LPEN SRAM1 clock enable during Sleep mode 31 1 read-write AHB2LPENR AHB2LPENR RCC AHB2 sleep clock register 0xB4 0x20 read-write 0xC01F1CFF 0xFFFFFFFF GPIOALPEN GPIOA clock enable during Sleep mode 0 1 read-write GPIOALPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 GPIOBLPEN GPIOB clock enable during Sleep mode 1 1 read-write GPIOCLPEN GPIOC clock enable during Sleep mode 2 1 read-write GPIODLPEN GPIOD clock enable during Sleep mode 3 1 read-write GPIOELPEN GPIOE clock enable during Sleep mode 4 1 read-write GPIOFLPEN GPIOF clock enable during Sleep mode 5 1 read-write GPIOGLPEN GPIOG clock enable during Sleep mode 6 1 read-write GPIOHLPEN GPIOH clock enable during Sleep mode 7 1 read-write GPIOILPEN GPIOI clock enable during Sleep mode 8 1 read-write ADCLPEN ADC1 and 2 peripherals clock enable during Sleep mode 10 1 read-write DAC1LPEN DAC clock enable during Sleep mode 11 1 read-write DCMI_PSSILPEN digital camera interface clock enable during Sleep mode (DCMI or PSSI depending which interface is active) 12 1 read-write AESLPEN AES clock enable during Sleep mode 16 1 read-write HASHLPEN HASH clock enable during Sleep mode 17 1 read-write RNGLPEN RNG clock enable during Sleep mode 18 1 read-write PKALPEN PKA clock enable during Sleep mode 19 1 read-write SAESLPEN SAES clock enable during Sleep mode 20 1 read-write SRAM2LPEN SRAM2 clock enable during Sleep mode 30 1 read-write SRAM3LPEN SRAM3 clock enable during Sleep mode 31 1 read-write AHB4LPENR AHB4LPENR RCC AHB4 sleep clock register 0xBC 0x20 read-write 0x00110880 0xFFFFFFFF OTFDEC1LPEN OTFDEC1 clock enable during Sleep mode 7 1 read-write OTFDEC1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 SDMMC1LPEN SDMMC1 and SDMMC1 delay peripheral clock enable during Sleep mode 11 1 read-write FMCLPEN FMC clock enable during Sleep mode 16 1 read-write OCTOSPI1LPEN OCTOSPI1 clock enable during Sleep mode 20 1 read-write APB1LLPENR APB1LLPENR RCC APB1 sleep clock register 0xC4 0x20 read-write 0x13FEC87F 0xFFFFFFFF TIM2LPEN TIM2 clock enable during Sleep mode 0 1 read-write TIM2LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 TIM3LPEN TIM3 clock enable during Sleep mode 1 1 read-write TIM4LPEN TIM4 clock enable during Sleep mode 2 1 read-write TIM5LPEN TIM5 clock enable during Sleep mode 3 1 read-write TIM6LPEN TIM6 clock enable during Sleep mode 4 1 read-write TIM7LPEN TIM7 clock enable during Sleep mode 5 1 read-write TIM12LPEN TIM12 clock enable during Sleep mode 6 1 read-write WWDGLPEN WWDG clock enable during Sleep mode 11 1 read-write SPI2LPEN SPI2 clock enable during Sleep mode 14 1 read-write SPI3LPEN SPI3 clock enable during Sleep mode 15 1 read-write USART2LPEN USART2 clock enable during Sleep mode 17 1 read-write USART3LPEN USART3 clock enable during Sleep mode 18 1 read-write UART4LPEN UART4 clock enable during Sleep mode 19 1 read-write UART5LPEN UART5 clock enable during Sleep mode 20 1 read-write I2C1LPEN I2C1 clock enable during Sleep mode 21 1 read-write I2C2LPEN I2C2 clock enable during Sleep mode 22 1 read-write I3C1LPEN I3C1 clock enable during Sleep mode 23 1 read-write CRSLPEN CRS clock enable during Sleep mode 24 1 read-write USART6LPEN USART6 clock enable during Sleep mode 25 1 read-write USART10LPEN USART10 clock enable during Sleep mode 26 1 read-write USART11LPEN USART11 clock enable during Sleep mode 27 1 read-write CECLPEN HDMI-CEC clock enable during Sleep mode 28 1 read-write UART7LPEN UART7 clock enable during Sleep mode 30 1 read-write UART8LPEN UART8 clock enable during Sleep mode 31 1 read-write APB1HLPENR APB1HLPENR RCC APB1 sleep clock register 0xC8 0x20 read-write 0x40800228 0xFFFFFFFF UART9LPEN UART9 clock enable during Sleep mode 0 1 read-write UART9LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 UART12LPEN UART12 clock enable during Sleep mode 1 1 read-write DTSLPEN DTS clock enable during Sleep mode 3 1 read-write LPTIM2LPEN LPTIM2 clock enable during Sleep mode 5 1 read-write FDCANLPEN FDCAN1 and FDCAN2 peripheral clock enable during Sleep mode 9 1 read-write UCPD1LPEN UCPD1 clock enable during Sleep mode 23 1 read-write APB2LPENR APB2LPENR RCC APB2 sleep clock register 0xCC 0x20 read-write 0x01097800 0xFFFFFFFF TIM1LPEN TIM1 clock enable during Sleep mode 11 1 read-write TIM1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 SPI1LPEN SPI1 clock enable during Sleep mode 12 1 read-write TIM8LPEN TIM8 clock enable during Sleep mode 13 1 read-write USART1LPEN USART1 clock enable during Sleep mode 14 1 read-write TIM15LPEN TIM15 clock enable during Sleep mode 16 1 read-write SPI4LPEN SPI4 clock enable during Sleep mode 19 1 read-write SPI6LPEN SPI6 clock enable during Sleep mode 20 1 read-write SAI1LPEN SAI1 clock enable during Sleep mode 21 1 read-write SAI2LPEN SAI2 clock enable during Sleep mode 22 1 read-write USBLPEN USB clock enable during Sleep mode 24 1 read-write APB3LPENR APB3LPENR RCC APB3 sleep clock register 0xD0 0x20 read-write 0x0030FAE2 0xFFFFFFFF SBSLPEN SBS clock enable during Sleep mode 1 1 read-write SBSLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 LPUART1LPEN LPUART1 clock enable during Sleep mode 6 1 read-write I2C3LPEN I2C3 clock enable during Sleep mode 7 1 read-write I3C2LPEN I3C2 clock enable during Sleep mode 9 1 read-write LPTIM1LPEN LPTIM1 clock enable during Sleep mode 11 1 read-write LPTIM3LPEN LPTIM3 clock enable during Sleep mode 12 1 read-write LPTIM4LPEN LPTIM4 clock enable during Sleep mode 13 1 read-write LPTIM5LPEN LPTIM5 clock enable during Sleep mode 14 1 read-write LPTIM6LPEN LPTIM6 clock enable during Sleep mode 15 1 read-write VREFLPEN VREFBUF clock enable during Sleep mode 20 1 read-write RTCAPBLPEN RTC APB interface clock enable during Sleep mode 21 1 read-write CCIPR1 CCIPR1 RCC kernel clock configuration register 0xD8 0x20 read-write 0x00000000 0xFFFFFFFF USART1SEL USART1 kernel clock source selection 0 3 read-write USARTSEL PCLK Peripheral bus clock used as selected as clock source (rcc_pclk_x) 0 PLL2_Q PLL2 Q clock selected as clock source (pll2_q_ck) 1 PLL3_Q PLL3 Q clock selected as clock source (pll3_q_ck) 2 HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 3 CSI_KER CSI kernel clock selected as clock source (csi_ker_ck) 4 LSE LSE clock selected as clock source (lse_ck) 5 USART2SEL USART2 kernel clock source selection 3 3 read-write USART3SEL USART3 kernel clock source selection 6 3 read-write UART4SEL UART4 kernel clock source selection 9 3 read-write UART5SEL UART5 kernel clock source selection 12 3 read-write USART6SEL USART6 kernel clock source selection 15 3 read-write UART7SEL UART7 kernel clock source selection 18 3 read-write UART8SEL UART8 kernel clock source selection 21 3 read-write UART9SEL UART9 kernel clock source selection 24 3 read-write USART10SEL USART10 kernel clock source selection 27 3 read-write TIMICSEL TIM12, TIM15 and LPTIM2 input capture source selection 31 1 read-write TIMICSEL Disabled No internal clock available for timers input capture 0 Enabled hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture 1 CCIPR2 CCIPR2 RCC kernel clock configuration register 0xDC 0x20 read-write 0x00000000 0xFFFFFFFF USART11SEL USART11 kernel clock source selection 0 3 read-write UART12SEL UART12 kernel clock source selection 4 3 read-write LPTIM1SEL LPTIM1 kernel clock source selection 8 3 read-write LPTIMSEL PCLK Peripheral bus clock used as selected as clock source (rcc_pclk_x) 0 PLL2_P PLL2 P clock selected as clock source (pll2_p_ck) 1 PLL3_R PLL3 R clock selected as clock source (pll3_r_ck) 2 LSE_KER LSE kernel selected as clock source (lse_ck) 3 LSI_KER LSI kernel selected as clock source (lsi_ker_ck) 4 PER_CK per_ck clock selected as clock source 5 LPTIM2SEL LPTIM2 kernel clock source selection 12 3 read-write LPTIM3SEL LPTIM3 kernel clock source selection 16 3 read-write LPTIM4SEL LPTIM4 kernel clock source selection 20 3 read-write LPTIM5SEL LPTIM5 kernel clock source selection 24 3 read-write LPTIM6SEL LPTIM6 kernel clock source selection 28 3 read-write CCIPR3 CCIPR3 RCC kernel clock configuration register 0xE0 0x20 read-write 0x00000000 0xFFFFFFFF SPI1SEL SPI1 kernel clock source selection 0 3 read-write SPI123SEL PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 0 PLL2_P PLL2 P clock selected as clock source (pll2_p_ck) 1 PLL3_P PLL3 P clock selected as clock source (pll3_p_ck) 2 AUDIOCLK AUDIOCLK clock selected as clock source 3 PER_CK per_ck clock selected as clock source 4 SPI2SEL SPI2 kernel clock source selection 3 3 read-write SPI3SEL SPI3 kernel clock source selection 6 3 read-write SPI4SEL SPI4 kernel clock source selection 9 3 read-write SPI456SEL PCLK Peripheral bus clock used as selected as clock source (rcc_pclk_x) 0 PLL2_Q PLL2 Q clock selected as clock source (pll2_p_ck) 1 PLL3_Q PLL3 Q clock selected as clock source (pll3_p_ck) 2 HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 3 CSI_KER CSI kernel clock selected as clock source (csi_ker_ck) 4 HSE HSE clock selected as clock source (hse_ck) 5 SPI6SEL SPI6 kernel clock source selection 15 3 read-write LPUART1SEL LPUART1 kernel clock source selection 24 3 read-write CCIPR4 CCIPR4 RCC kernel clock configuration register 0xE4 0x20 read-write 0x00000000 0xFFFFFFFF OCTOSPI1SEL OCTOSPI1 kernel clock source selection 0 2 read-write OCTOSPI1SEL RCC_HCLK4 HCLK4 selected as clock source (rcc_hclk4) 0 PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 1 PLL2_R PLL2 R clock selected as clock source (pll2_r_ck) 2 PER_CK per_ck clock selected as clock source 3 SYSTICKSEL SYSTICK clock source selection 2 2 read-write SYSTICKSEL HCLK_DIV8 RCC HLCK divided by 8 selected as clock source (rcc_hclk / 8) 0 LSI_KER LSI kernel selected as clock source (lsi_ker_ck) 1 LSE LSE selected as clock source (lse_ck) 2 USBSEL USB kernel clock source selection 4 2 read-write USBSEL DISABLE Disable the clock 0 PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 1 PLL3_Q PLL3 Q clock selected as clock source (pll3_q_ck) 2 HSI48 HSI48 clock selected as clock source (hsi48_ker_ck) 3 SDMMC1SEL SDMMC1 kernel clock source selection 6 1 read-write SDMMCSEL PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 0 PLL2_R PLL2 R clock selected as clock source (pll2_r_ck) 1 I2C1SEL I2C1 kernel clock source selection 16 2 read-write I2CSEL PCLK Peripheral bus clock used as selected as clock source (rcc_pclk_x) 0 PLL3_R PLL3 R Clock selected as clock source (pll3_r_ck) 1 HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 2 CSI_KER CSI kernel clock selected as clock source (csi_ker_ck) 3 I2C2SEL I2C2 kernel clock source selection 18 2 read-write I2C3SEL I2C3 kernel clock source selection 20 2 read-write I3C1SEL I3C1 kernel clock source selection 24 2 read-write I3CSEL PCLK Peripheral bus clock used as selected as clock source (rcc_pclk_x) 0 PLL3_R PLL3 R clock selected as clock source (pll3_r_ck) 1 HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 2 I3C2SEL I3C2 kernel clock source selection 26 2 read-write CCIPR5 CCIPR5 RCC kernel clock configuration register 0xE8 0x20 read-write 0x00000000 0xFFFFFFFF ADCDACSEL ADC and DAC kernel clock source selection 0 3 read-write ADCDACSEL HCLK HLCK clock selected as clock source (rcc_hclk) 0 SYS System clock selected as pclock source (sys_ck) 1 PLL2_R PLL2 R clock selected as clock source (pll2_r_ck) 2 HSE HSE clock selected as clock source (hse_ck) 3 HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 4 CSI_KER CSI kernel clock selected as clock source (csi_ker_ck) 5 DACSEL DAC sample and hold clock 3 1 read-write DACSEL LSE LSE selected as clock source (lse_ck) 0 LSI_KER LSI kernel selected as clock source (lsi_ker_ck) 1 RNGSEL RNG kernel clock source selection 4 2 read-write RNGSEL HSI48_KER HSI48 kernel clock selected as clock source (hsi48_ker_ck) 0 PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 1 LSE LSE clock selected as clock source (lse_ck) 2 LSI LSI kernel clock selected as clock source (lsi_ker_ck) 3 CECSEL HSMI-CEC kernel clock source selection 6 2 read-write CECSEL LSE LSE selected as clock source (lse_ck) 0 LSI_KER LSI kernel selected as clock source (lsi_ker_ck) 1 CSI_KER CSI kernel clock divided by 122 selected as clock source (csi_ker_ck/122) 2 FDCANSEL FDCAN1 and FDCAN2 kernel clock source selection 8 2 read-write FDCANSEL HSE HSE clock selected as clock source (hse_ck) 0 PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 1 PLL2_Q PLL2 Q clock selected as clock source (pll2_q_ck) 2 SAI1SEL SAI1 kernel clock source selection 16 3 read-write SAISEL PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 0 PLL2_P PLL2 P clock selected as clock source (pll2_p_ck) 1 PLL3_P PLL3 P clock selected as clock source (pll3_p_ck) 2 AUDIOCLK AUDIOCLK clock selected as clock source 3 PER_CK per_ck clock selected as clock source 4 SAI2SEL SAI2 kernel clock source selection 19 3 read-write CKPERSEL per_ck clock source selection 30 2 read-write CKPERSEL HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 0 CSI_KER CSI kernel clock selected as clock source (csi_ker_ck) 1 HSE HSE clock selected as clock source (hse_ck) 2 BDCR BDCR RCC Backup domain control register 0xF0 0x20 read-write 0x00000000 0xFFFFFFFF LSEON LSE oscillator enabled 0 1 read-write LSEON Off LSE oscillator Off 0 On LSE oscillator On 1 LSERDY LSE oscillator ready 1 1 read-write LSERDYR read NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEBYP LSE oscillator bypass 2 1 read-write LSEBYP NotBypassed LSE crystal oscillator not bypassed 0 Bypassed LSE crystal oscillator bypassed with external clock 1 LSEDRV LSE oscillator driving capability 3 2 read-write LSEDRV Lowest Lowest LSE oscillator driving capability 0 MediumLow Medium low LSE oscillator driving capability 1 MediumHigh Medium high LSE oscillator driving capability 2 Highest Highest LSE oscillator driving capability 3 LSECSSON LSE clock security system enable 5 1 read-write LSECSSON SecurityOff Clock security system on 32 kHz oscillator off 0 SecurityOn Clock security system on 32 kHz oscillator on 1 LSECSSD LSE clock security system failure detection 6 1 read-write LSECSSDR read NoFailure No failure detected on 32 kHz oscillator 0 Failure Failure detected on 32 kHz oscillator 1 LSEEXT low-speed external clock type in bypass mode 7 1 read-write LSEEXT Analog HSE in analog mode 0 Digital HSE in digital mode 1 RTCSEL RTC clock source selection 8 2 read-write RTCSEL NoClock No clock 0 LSE LSE oscillator clock used as RTC clock 1 LSI LSI oscillator clock used as RTC clock 2 HSE HSE oscillator clock divided by a prescaler used as RTC clock 3 RTCEN RTC clock enable 15 1 read-write RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 VSWRST VSwitch domain software reset 16 1 read-write VSWRST NotActivated Reset not activated 0 Reset Resets the entire VSW domain 1 LSCOEN Low-speed clock output (LSCO) enable 24 1 read-write LSCOSEL Low-speed clock output selection 25 1 read-write LSCOSEL LSI LSI clock selected 0 LSE LSE clock selected 1 LSION LSI oscillator enable 26 1 read-write LSION Disabled Oscillator disabled 0 Enabled Oscillator enabled 1 LSIRDY LSI oscillator ready 27 1 read-write LSIRDYR read NotReady Clock not ready 0 Ready Clock ready 1 RSR RSR RCC reset status register 0xF4 0x20 read-write 0x0C000000 0xFFFFFFFF RMVF remove reset flag 23 1 read-write RMVF NotActivated Reset not activated 0 Reset Reset the reset status flags 1 PINRSTF pin reset flag (NRST) 26 1 read-write PINRSTFR read NoResetOccurred No reset occurred for block 0 ResetOccurred Reset occurred for block 1 BORRSTF BOR reset flag 27 1 read-write SFTRSTF system reset from CPU reset flag 28 1 read-write IWDGRSTF independent watchdog reset flag 29 1 read-write WWDGRSTF window watchdog reset flag 30 1 read-write LPWRRSTF Low-power reset flag 31 1 read-write SECCFGR SECCFGR RCC secure configuration register 0x110 0x20 read-write 0x00000000 0xFFFFFFFF HSISEC HSI clock configuration and status bits security 0 1 read-write HSISEC NonSecure Non secure 0 Secure Secure 1 HSESEC HSE clock configuration bits, status bits and HSE_CSS security 1 1 read-write CSISEC CSI clock configuration and status bits security 2 1 read-write LSISEC LSI clock configuration and status bits security 3 1 read-write LSESEC LSE clock configuration and status bits security 4 1 read-write SYSCLKSEC SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security 5 1 read-write PRESCSEC AHBx/APBx prescaler configuration bits security 6 1 read-write PLL1SEC PLL1 clock configuration and status bits security 7 1 read-write PLL2SEC PLL2 clock configuration and status bits security 8 1 read-write PLL3SEC PLL3 clock configuration and status bits security 9 1 read-write HSI48SEC HSI48 clock configuration and status bits security 11 1 read-write RMVFSEC Remove reset flag security 12 1 read-write CKPERSELSEC per_ck selection security 13 1 read-write PRIVCFGR PRIVCFGR RCC privilege configuration register 0x114 0x20 read-write 0x00000000 0xFFFFFFFF SPRIV RCC secure functions privilege configuration 0 1 read-write SPRIV Any RCC functions can be modified by privileged or unprivileged access 0 PrivilegedOnly RCC functions can only be modified by privileged access 1 NSPRIV RCC non-secure functions privilege configuration 1 1 read-write RCC_S 0x54020C00 RNG RNG address block description RNG 0x420C0800 0x0 0x14 registers RNG RNG global interrupt 114 CR CR RNG control register 0x0 0x20 read-write 0x00800D00 0xFFFFFFFF RNGEN True random number generator enable 2 1 read-write RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 IE Interrupt enable 3 1 read-write IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 CED Clock error detection 5 1 read-write CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 ARDIS Auto reset disable 7 1 read-write RNG_CONFIG3 RNG configuration 3 8 4 read-write RNG_CONFIG3 ConfigB Recommended value for config B (not NIST certifiable) 0 ConfigA Recommended value for config A (NIST certifiable) 13 NISTC NIST custom 12 1 read-write NISTC Default Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used 0 Custom Custom values for NIST compliant RNG 1 RNG_CONFIG2 RNG configuration 2 13 3 read-write RNG_CONFIG2 ConfigA_B Recommended value for config A and B 0 CLKDIV Clock divider factor 16 4 read-write CLKDIV Div1 Internal RNG clock after divider is similar to incoming RNG clock 0 Div2 Divide RNG clock by 2^1 1 Div4 Divide RNG clock by 2^2 2 Div8 Divide RNG clock by 2^3 3 Div16 Divide RNG clock by 2^4 4 Div32 Divide RNG clock by 2^5 5 Div64 Divide RNG clock by 2^6 6 Div128 Divide RNG clock by 2^7 7 Div256 Divide RNG clock by 2^8 8 Div512 Divide RNG clock by 2^9 9 Div1024 Divide RNG clock by 2^10 10 Div2048 Divide RNG clock by 2^11 11 Div4096 Divide RNG clock by 2^12 12 Div8192 Divide RNG clock by 2^13 13 Div16384 Divide RNG clock by 2^14 14 Div32768 Divide RNG clock by 2^15 15 RNG_CONFIG1 RNG configuration 1 20 6 read-write RNG_CONFIG1 ConfigA Recommended value for config A (NIST certifiable) 15 ConfigB Recommended value for config B (not NIST certifiable) 24 CONDRST Conditioning soft reset 30 1 read-write CONFIGLOCK RNG Config lock 31 1 read-write CONFIGLOCK Enabled Writes to the RNG_CR configuration bits [29:4] are allowed 0 Disabled Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset 1 SR SR RNG status register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF DRDY Data ready 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 CECS Clock error current status 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 SECS Seed error current status 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CEIS Clock error interrupt status 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 DR DR RNG data register 0x8 0x20 read-only 0x00000000 0xFFFFFFFF RNDATA Random data 0 32 read-only 0 4294967295 NSCR NSCR RNG noise source control register 0xC 0x20 read-write 0x0003FFFF 0xFFFFFFFF EN_OSC1 Each bit drives one oscillator enable signal input of instance number 1, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 0 3 read-write EN_OSC2 Each bit drives one oscillator enable signal input of instance number 2, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 3 3 read-write EN_OSC3 Each bit drives one oscillator enable signal input of instance number 3, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 6 3 read-write EN_OSC4 Each bit drives one oscillator enable signal input of instance number 4, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 9 3 read-write EN_OSC5 Each bit drives one oscillator enable signal input of instance number 5, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 12 3 read-write EN_OSC6 Each bit drives one oscillator enable signal input of instance number 6, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 15 3 read-write HTCR HTCR RNG health test control register 0x10 0x20 read-write 0x000072AC 0xFFFFFFFF HTCFG health test configuration 0 32 read-write HTCFG Recommended Recommended value for RNG certification (0x0000_AA74) 43636 Magic Magic number to be written before any write (0x1759_0ABC) 391711420 RNG_S 0x520C0800 RTC RTC register block RTC 0x44007800 0x0 0x400 registers RTC_S RTC global secure interrupts 3 RTC RTC global non-secure interrupts 2 TR TR RTC time register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write 0 15 ST Second tens in BCD format 4 3 read-write 0 7 MNU Minute units in BCD format 8 4 read-write 0 15 MNT Minute tens in BCD format 12 3 read-write 0 7 HU Hour units in BCD format 16 4 read-write 0 15 HT Hour tens in BCD format 20 2 read-write 0 3 PM AM/PM notation 22 1 read-write PM AM AM or 24-hour format 0 PM PM 1 DR DR RTC date register 0x4 0x20 read-write 0x00002101 0xFFFFFFFF DU Date units in BCD format 0 4 read-write 0 15 DT Date tens in BCD format 4 2 read-write 0 3 MU Month units in BCD format 8 4 read-write 0 15 MT Month tens in BCD format 12 1 read-write 0 1 WDU Week day units 13 3 read-write 1 7 YU Year units in BCD format 16 4 read-write 0 15 YT Year tens in BCD format 20 4 read-write 0 15 SSR SSR RTC subsecond register 0x8 0x20 read-only 0x00000000 0xFFFFFFFF SS Synchronous binary counter 0 32 read-only 0 65535 ICSR ICSR RTC initialization control and status register 0xC 0x20 read-write 0x00000007 0xFFFFFFFF WUTWF Wake-up timer write flag 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 BIN Binary mode 8 2 read-write BCDU BCD update (BIN = 10 or 11) 10 3 read-write RECALPF Recalibration pending Flag 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER RTC prescaler register 0x10 0x20 read-write 0x007F00FF 0xFFFFFFFF PREDIV_S Synchronous prescaler factor 0 15 read-write 0 32767 PREDIV_A Asynchronous prescaler factor 16 7 read-write 0 127 WUTR WUTR RTC wake-up timer register 0x14 0x20 read-write 0x0000FFFF 0xFFFFFFFF WUT Wake-up auto-reload value bits 0 16 read-write 0 65535 WUTOCLR Wake-up auto-reload output clear value 16 16 read-write CR CR RTC control register 0x18 0x20 read-write 0x00000000 0xFFFFFFFF WUCKSEL ck_wut wake-up clock selection 0 3 read-write WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE Timestamp event active edge 3 1 read-write TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON RTC_REFIN reference clock detection enable (50 or 60 Hz) 4 1 read-write REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD Bypass the shadow registers 5 1 read-write BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT Hour format 6 1 read-write FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 SSRUIE SSR underflow interrupt enable 7 1 read-write 2 0x1 A,B ALR%sE Alarm %s enable 8 1 read-write ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE Wake-up timer enable 10 1 read-write WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE timestamp enable 11 1 read-write TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 read-write ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE Wake-up timer interrupt enable 14 1 read-write WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE Timestamp interrupt enable 15 1 read-write TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H Add 1 hour (summer time change) 16 1 write-only ADD1HW Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H Subtract 1 hour (winter time change) 17 1 write-only SUB1HW Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP Backup 18 1 read-write BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 COSEL Calibration output selection 19 1 read-write COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL Output polarity 20 1 read-write POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL Output selection 21 2 read-write OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE Calibration output enable 23 1 read-write COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ITSE timestamp on internal event enable 24 1 read-write ITSE Disabled Internal event timestamp disabled 0 Enabled Internal event timestamp enabled 1 TAMPTS Activate timestamp on tamper detection event 25 1 read-write TAMPTS Disabled Tamper detection event does not cause a RTC timestamp to be saved 0 Enabled Save RTC timestamp on tamper detection event 1 TAMPOE Tamper detection output enable on TAMPALRM 26 1 read-write TAMPOE Disabled The tamper flag is not routed on TAMPALRM 0 Enabled The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL 1 ALRAFCLR Alarm A flag automatic clear 27 1 read-write ALRBFCLR Alarm B flag automatic clear 28 1 read-write TAMPALRM_PU TAMPALRM pull-up enable 29 1 read-write TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPALRM_TYPE TAMPALRM output type 30 1 read-write TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 OUT2EN RTC_OUT2 output enable 31 1 read-write OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 PRIVCFGR PRIVCFGR RTC privilege mode control register 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF ALRAPRIV Alarm A and SSR underflow privilege protection 0 1 read-write ALRBPRIV Alarm B privilege protection 1 1 read-write WUTPRIV Wake-up timer privilege protection 2 1 read-write TSPRIV Timestamp privilege protection 3 1 read-write CALPRIV Shift register, Delight saving, calibration and reference clock privilege protection 13 1 read-write INITPRIV Initialization privilege protection 14 1 read-write PRIV RTC privilege protection 15 1 read-write SECCFGR SECCFGR RTC secure configuration register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF ALRASEC Alarm A and SSR underflow protection 0 1 read-write ALRBSEC Alarm B protection 1 1 read-write WUTSEC Wake-up timer protection 2 1 read-write TSSEC Timestamp protection 3 1 read-write CALSEC Shift register, daylight saving, calibration and reference clock protection 13 1 read-write INITSEC Initialization protection 14 1 read-write SEC RTC global protection 15 1 read-write WPR WPR RTC write protection register 0x24 0x20 write-only 0x00000000 0xFFFFFFFF KEY Write protection key 0 8 write-only KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR RTC calibration register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF CALM Calibration minus 0 9 read-write 0 511 LPCAL RTC low-power mode 12 1 read-write CALW16 Use a 16-second calibration cycle period 13 1 read-write CALW16 SixteenSeconds When CALW16 is set to â1â, the 16-second calibration cycle period is selected.This bit must not be set to â1â if CALW8=1 1 CALW8 Use an 8-second calibration cycle period 14 1 read-write CALW8 EightSeconds When CALW8 is set to â1â, the 8-second calibration cycle period is selected 1 CALP Increase frequency of RTC by 488. 15 1 read-write CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 SHIFTR SHIFTR RTC shift control register 0x2C 0x20 write-only 0x00000000 0xFFFFFFFF SUBFS Subtract a fraction of a second 0 15 write-only 0 32767 ADD1S Add one second 31 1 write-only ADD1SW Add1 Add one second to the clock/calendar 1 TSTR TSTR RTC timestamp time register 0x30 TSDR TSDR RTC timestamp date register 0x34 TSSSR TSSSR RTC timestamp subsecond register 0x38 2 0x8 A,B ALRM%sR ALRM%sR Alarm %s register 0x40 0x20 read-write 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write 0 15 ST Second tens in BCD format 4 3 read-write 0 7 MSK1 Alarm seconds mask 7 1 read-write MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day donât care in Alarm comparison 1 MNU Minute units in BCD format 8 4 read-write 0 15 MNT Minute tens in BCD format 12 3 read-write 0 7 MSK2 Alarm minutes mask 15 1 read-write HU Hour units in BCD format 16 4 read-write 0 15 HT Hour tens in BCD format 20 2 read-write 0 3 PM AM/PM notation 22 1 read-write PM AM AM or 24-hour format 0 PM PM 1 MSK3 Alarm hours mask 23 1 read-write DU Date units or day in BCD format 24 4 read-write 0 15 DT Date tens in BCD format 28 2 read-write 0 3 WDSEL Week day selection 30 1 read-write WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is donât care. 1 MSK4 Alarm date mask 31 1 read-write 2 0x8 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 0xFFFFFFFF SS Subseconds value 0 15 read-write 0 32767 MASKSS Mask the most-significant bits starting at this bit 24 6 read-write SSCLR Clear synchronous counter on alarm (Binary mode only) 31 1 read-write SR SR RTC status register 0x50 0x20 read-only 0x00000000 0xFFFFFFFF 2 0x1 A,B ALR%sF Alarm %s flag 0 1 read-only ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 WUTF Wake-up timer flag 2 1 read-only WUTF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSF Timestamp flag 3 1 read-only TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVF Timestamp overflow flag 4 1 read-only TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSF Internal timestamp flag 5 1 read-only ITSF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SSRUF SSR underflow flag 6 1 read-only MISR MISR RTC nonsecure masked interrupt status register 0x54 0x20 read-only 0x00000000 0xFFFFFFFF 2 0x1 A,B ALR%sMF Alarm %s masked flag 0 1 read-only ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 WUTMF Wake-up timer nonsecure masked flag 2 1 read-only WUTMF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSMF Timestamp nonsecure masked flag 3 1 read-only TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVMF Timestamp overflow nonsecure masked flag 4 1 read-only TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSMF Internal timestamp nonsecure masked flag 5 1 read-only ITSMF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SSRUMF SSR underflow nonsecure masked flag 6 1 read-only SMISR SMISR RTC secure masked interrupt status register 0x58 0x20 read-only 0x00000000 0xFFFFFFFF ALRAMF Alarm A interrupt secure masked flag 0 1 read-only ALRBMF Alarm B interrupt secure masked flag 1 1 read-only WUTMF Wake-up timer interrupt secure masked flag 2 1 read-only TSMF Timestamp interrupt secure masked flag 3 1 read-only TSOVMF Timestamp overflow interrupt secure masked flag 4 1 read-only ITSMF Internal timestamp interrupt secure masked flag 5 1 read-only SSRUMF SSR underflow secure masked flag 6 1 read-only SCR SCR RTC status clear register 0x5C 0x20 write-only 0x00000000 0xFFFFFFFF CALRAF Clear alarm A flag 0 1 write-only CALRAF Clear Clear interrupt flag 1 CALRBF Clear alarm B flag 1 1 write-only CWUTF Clear wake-up timer flag 2 1 write-only CTSF Clear timestamp flag 3 1 write-only CTSOVF Clear timestamp overflow flag 4 1 write-only CITSF Clear internal timestamp flag 5 1 write-only CSSRUF Clear SSR underflow flag 6 1 write-only OR OR RTC option register 0x60 0x20 read-write 0x00000000 0xFFFFFFFF OUT2_RMP RTC_OUT2 mapping 0 1 read-write 2 0x4 A,B ALR%sBINR ALR%sBINR Alarm %s binary mode register 0x70 0x20 read-write 0x00000000 0xFFFFFFFF SS Synchronous counter alarm value in Binary mode 0 32 read-write RTC_S 0x54007800 SAES SAES register block SAES 0x420C0C00 0x0 0x400 registers SAES Secure AES 36 CR CR SAES control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF EN Enable 0 1 read-write DATATYPE Data type 1 2 read-write MODE Operating mode 3 2 read-write CHMOD CHMOD[1:0]: Chaining mode 5 2 read-write DMAINEN DMA input enable 11 1 read-write DMAOUTEN DMA output enable 12 1 read-write GCMPH GCM or CCM phase selection 13 2 read-write CHMOD_1 CHMOD[2] 16 1 read-write KEYSIZE Key size selection 18 1 read-write KEYPROT Key protection 19 1 read-write NPBLB Number of padding bytes in last block 20 4 read-write KMOD Key mode selection 24 2 read-write KSHAREID Key share identification 26 2 read-write KEYSEL Key selection 28 3 read-write IPRST SAES peripheral software reset 31 1 read-write SR SR SAES status register 0x4 0x20 read-only 0x00000000 0xFFFFFFFF RDERRF Read error flag 1 1 read-only WRERRF Write error flag 2 1 read-only BUSY Busy 3 1 read-only KEYVALID Key valid flag 7 1 read-only DINR DINR SAES data input register 0x8 0x20 write-only 0x00000000 0xFFFFFFFF DIN Data input 0 32 write-only DOUTR DOUTR SAES data output register 0xC 0x20 read-only 0x00000000 0xFFFFFFFF DOUT Data output 0 32 read-only KEYR0 KEYR0 SAES key register 0 0x10 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [31:0] 0 32 write-only KEYR1 KEYR1 SAES key register 1 0x14 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [63:32] 0 32 write-only KEYR2 KEYR2 SAES key register 2 0x18 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [95:64] 0 32 write-only KEYR3 KEYR3 SAES key register 3 0x1C 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [127:96] 0 32 write-only IVR0 IVR0 SAES initialization vector register 0 0x20 0x20 read-write 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [31:0] 0 32 read-write IVR1 IVR1 SAES initialization vector register 1 0x24 0x20 read-write 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [63:32] 0 32 read-write IVR2 IVR2 SAES initialization vector register 2 0x28 0x20 read-write 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [95:64] 0 32 read-write IVR3 IVR3 SAES initialization vector register 3 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [127:96] 0 32 read-write KEYR4 KEYR4 SAES key register 4 0x30 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [159:128] 0 32 write-only KEYR5 KEYR5 SAES key register 5 0x34 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [191:160] 0 32 write-only KEYR6 KEYR6 SAES key register 6 0x38 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [223:192] 0 32 write-only KEYR7 KEYR7 SAES key register 7 0x3C 0x20 write-only 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [255:224] 0 32 write-only SUSPR0 SUSPR0 SAES suspend registers 0x40 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR1 SUSPR1 SAES suspend registers 0x44 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR2 SUSPR2 SAES suspend registers 0x48 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR3 SUSPR3 SAES suspend registers 0x4C 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR4 SUSPR4 SAES suspend registers 0x50 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR5 SUSPR5 SAES suspend registers 0x54 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR6 SUSPR6 SAES suspend registers 0x58 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write SUSPR7 SUSPR7 SAES suspend registers 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF SUSP Suspend data 0 32 read-write IER IER SAES interrupt enable register 0x300 0x20 read-write 0x00000000 0xFFFFFFFF CCFIE Computation complete flag interrupt enable 0 1 read-write RWEIE Read or write error interrupt enable 1 1 read-write KEIE Key error interrupt enable 2 1 read-write RNGEIE RNG error interrupt enable 3 1 read-write ISR ISR SAES interrupt status register 0x304 0x20 read-only 0x00000000 0xFFFFFFFF CCF Computation complete flag 0 1 read-only RWEIF Read or write error interrupt flag 1 1 read-only KEIF Key error interrupt flag 2 1 read-only RNGEIF RNG error interrupt flag 3 1 read-only ICR ICR SAES interrupt clear register 0x308 0x20 write-only 0x00000000 0xFFFFFFFF CCF Computation complete flag clear 0 1 write-only RWEIF Read or write error interrupt flag clear 1 1 write-only KEIF Key error interrupt flag clear 2 1 write-only RNGEIF RNG error interrupt flag clear 3 1 write-only SAES_S 0x520C0C00 SBS SBS address block description SBS 0x44000400 0x0 0x150 registers HDPLCR HDPLCR SBS temporal isolation control register 0x10 0x20 read-write 0x000000B4 0xFFFFFFFF INCR_HDPL increment HDPL value 0 8 read-write HDPLSR HDPLSR SBS temporal isolation status register 0x14 0x20 read-only 0x00000000 0x00000000 HDPL temporal isolation level 0 8 read-only NEXTHDPLCR NEXTHDPLCR SBS next HDPL control register 0x18 0x20 read-write 0x00000000 0xFFFFFFFF NEXTHDPL index to point to a higher HDPL than the current one 0 2 read-write DBGCR DBGCR SBS debug control register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF AP_UNLOCK access port unlock 0 8 read-write DBG_UNLOCK debug unlock when DBG_AUTH_HDPL is reached 8 8 read-write DBG_AUTH_HDPL authenticated debug temporal isolation level 16 8 read-write DBG_AUTH_SEC control debug opening secure/non-secure 24 8 read-write DBGLOCKR DBGLOCKR SBS debug lock register 0x24 0x20 read-write 0x000000B4 0xFFFFFFFF DBGCFG_LOCK debug configuration lock 0 8 read-write RSSCMDR RSSCMDR SBS RSS command register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF RSSCMD RSS command 0 16 read-write EPOCHSELCR EPOCHSELCR SBS EPOCH selection control register 0xA0 0x20 read-write 0x00000000 0xFFFFFFFF EPOCH_SEL select EPOCH value to be sent to the SAES 0 2 read-write SECCFGR SECCFGR SBS security mode configuration control register 0xC0 0x20 read-write 0x00000000 0xFFFFFFFF SBSSEC SBS clock control, memory-erase status register and compensation cell register security enable 0 1 read-write CLASSBSEC ClassB security enable 1 1 read-write FPUSEC FPU security enable 3 1 read-write PMCR PMCR SBS product mode and configuration register 0x100 0x20 read-write 0x00000000 0xFFFFFFFF PB6_FMP Fast-mode Plus driving capability activation on PB6 16 1 read-write PB7_FMP Fast-mode Plus driving capability activation on PB7 17 1 read-write PB8_FMP Fast-mode Plus driving capability activation on PB8 18 1 read-write PB9_FMP Fast-mode Plus driving capability activation on PB9 19 1 read-write ETH_SEL_PHY Ethernet PHY interface selection 21 3 read-write FPUIMR FPUIMR SBS FPU interrupt mask register 0x104 0x20 read-write 0x0000001F 0xFFFFFFFF FPU_IE0 FPU interrupt enable 0 1 FPU_IE1 FPU interrupt enable 1 1 FPU_IE2 FPU interrupt enable 2 1 FPU_IE3 FPU interrupt enable 3 1 FPU_IE4 FPU interrupt enable 4 1 FPU_IE5 FPU interrupt enable 5 1 MESR MESR SBS memory erase status register 0x108 0x20 read-write 0x00000000 0xFFFFFFF0 MCLR device memories erase status 0 1 read-write IPMEE ICACHE erase status 16 1 read-write CCCSR CCCSR SBS compensation cell for I/Os control and status register 0x110 0x20 read-write 0x00000000 0xFFFFFFFF EN1 enable compensation cell for VDDIO power rail 0 1 read-write CS1 code selection for VDDIO power rail (reset value set to 1) 1 1 read-write EN2 enable compensation cell for VDDIO2 power rail 2 1 read-write CS2 code selection for VDDIO2 power rail (reset value set to 1) 3 1 read-write RDY1 VDDIO compensation cell ready flag 8 1 read-only RDY2 VDDIO2 compensation cell ready flag 9 1 read-only CCVALR CCVALR SBS compensation cell for I/Os value register 0x114 0x20 read-only 0x00000088 0xFFFFFFFF ANSRC1 compensation value for the NMOS transistor 0 4 read-only APSRC1 compensation value for the PMOS transistor 4 4 read-only ANSRC2 Compensation value for the NMOS transistor 8 4 read-only APSRC2 compensation value for the PMOS transistor 12 4 read-only CCSWCR CCSWCR SBS compensation cell for I/Os software code register 0x118 0x20 read-write 0x00007878 0xFFFFFFFF SW_ANSRC1 NMOS compensation code for VDD power rails 0 4 read-write SW_APSRC1 PMOS compensation code for the VDD power rails 4 4 read-write SW_ANSRC2 NMOS compensation code for VDDIO power rails 8 4 read-write SW_APSRC2 PMOS compensation code for the Vless thansub>DDIOless than/sub> power rails 12 4 read-write CFGR2 CFGR2 SBS Class B register 0x120 0x20 read-write 0x00000000 0xFFFFFFFF CLL core lockup lock 0 1 read-write SEL SRAM ECC error lock 1 1 read-write PVDL PVD lock 2 1 read-write ECCL ECC lock 3 1 read-write CNSLCKR CNSLCKR SBS CPU non-secure lock register 0x144 0x20 read-write 0x00000000 0xFFFFFFFF LOCKNSVTOR VTOR_NS register lock 0 1 read-write LOCKNSMPU non-secure MPU register lock 1 1 read-write CSLCKR CSLCKR SBS CPU secure lock register 0x148 0x20 read-write 0x00000000 0xFFFFFFFF LOCKSVTAIRCR VTOR_S and AIRCR register lock 0 1 read-write LOCKSMPU secure MPU registers lock 1 1 read-write LOCKSAU SAU registers lock 2 1 read-write ECCNMIR ECCNMIR SBS flift ECC NMI mask register 0x14C 0x20 read-write 0x00000000 0xFFFFFFFF ECCNMI_MASK_EN NMI behavior setup when a double ECC error occurs on flitf data part 0 1 read-write SBS_S 0x54000400 SDMMC1 SDMMC address block description SDMMC 0x46008000 0x0 0xC0 registers SDMMC1 SDMMC1 global interrupt 79 POWER POWER SDMMC power control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF PWRCTRL SDMMC state control bits 0 2 read-write VSWITCH Voltage switch sequence start 2 1 read-write VSWITCHEN Voltage switch procedure enable 3 1 read-write DIRPOL Data and command direction signals polarity selection 4 1 read-write CLKCR CLKCR SDMMC clock control register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF CLKDIV Clock divide factor 0 10 read-write PWRSAV Power saving configuration bit 12 1 read-write WIDBUS Wide bus mode enable bit 14 2 read-write NEGEDGE SDMMC_CK dephasing selection bit for data and command 16 1 read-write HWFC_EN Hardware flow control enable 17 1 read-write DDR Data rate signaling selection 18 1 read-write BUSSPEED Bus speed for selection of SDMMC operating modes 19 1 read-write SELCLKRX Receive clock selection 20 2 read-write ARGR ARGR SDMMC argument register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF CMDARG Command argument 0 32 read-write CMDR CMDR SDMMC command register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF CMDINDEX Command index 0 6 read-write CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM 6 1 read-write CMDSTOP The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM 7 1 read-write WAITRESP Wait for response bits 8 2 read-write WAITINT CPSM waits for interrupt request 10 1 read-write WAITPEND CPSM waits for end of data transfer (CmdPend internal signal) from DPSM 11 1 read-write CPSMEN Command path state machine (CPSM) enable bit 12 1 read-write DTHOLD Hold new data block transmission and reception in the DPSM 13 1 read-write BOOTMODE Select the boot mode procedure to be used 14 1 read-write BOOTEN Enable boot mode procedure 15 1 read-write CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end 16 1 read-write RESPCMDR RESPCMDR SDMMC command response register 0x10 0x20 read-only 0x00000000 0xFFFFFFFF RESPCMD Response command index 0 6 read-only 4 0x4 1-4 RESP%sR RESP%sR SDMMC response %s register 0x14 0x20 read-only 0x00000000 0xFFFFFFFF CARDSTATUS Card status according table below 0 32 read-only DTIMER DTIMER SDMMC data timer register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF DATATIME Data and R1b busy timeout period 0 32 read-write DLENR DLENR SDMMC data length register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF DATALENGTH Data length value 0 25 read-write DCTRL DCTRL SDMMC data control register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF DTEN Data transfer enable bit 0 1 read-write DTDIR Data transfer direction selection 1 1 read-write DTMODE Data transfer mode selection 2 2 read-write DBLOCKSIZE Data block size 4 4 read-write RWSTART Read Wait start 8 1 read-write RWSTOP Read Wait stop 9 1 read-write RWMOD Read Wait mode 10 1 read-write SDIOEN SD I/O interrupt enable functions 11 1 read-write BOOTACKEN Enable the reception of the boot acknowledgment 12 1 read-write FIFORST FIFO reset, flushes any remaining data 13 1 read-write DCNTR DCNTR SDMMC data counter register 0x30 0x20 read-only 0x00000000 0xFFFFFFFF DATACOUNT Data count value 0 25 read-only STAR STAR SDMMC status register 0x34 0x20 read-only 0x00000000 0xFFFFFFFF CCRCFAIL Command response received (CRC check failed) 0 1 read-only DCRCFAIL Data block sent/received (CRC check failed) 1 1 read-only CTIMEOUT Command response timeout 2 1 read-only DTIMEOUT Data timeout 3 1 read-only TXUNDERR Transmit FIFO underrun error (masked by hardware when IDMA is enabled) 4 1 read-only RXOVERR Received FIFO overrun error (masked by hardware when IDMA is enabled) 5 1 read-only CMDREND Command response received (CRC check passed, or no CRC) 6 1 read-only CMDSENT Command sent (no response required) 7 1 read-only DATAEND Data transfer ended correctly 8 1 read-only DHOLD Data transfer Hold 9 1 read-only DBCKEND Data block sent/received 10 1 read-only DABORT Data transfer aborted by CMD12 11 1 read-only DPSMACT Data path state machine active, i. 12 1 read-only CPSMACT Command path state machine active, i. 13 1 read-only TXFIFOHE Transmit FIFO half empty 14 1 read-only RXFIFOHF Receive FIFO half full 15 1 read-only TXFIFOF Transmit FIFO full 16 1 read-only RXFIFOF Receive FIFO full 17 1 read-only TXFIFOE Transmit FIFO empty 18 1 read-only RXFIFOE Receive FIFO empty 19 1 read-only BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response 20 1 read-only BUSYD0END end of SDMMC_D0 Busy following a CMD response detected 21 1 read-only SDIOIT SDIO interrupt received 22 1 read-only ACKFAIL Boot acknowledgment received (boot acknowledgment check fail) 23 1 read-only ACKTIMEOUT Boot acknowledgment timeout 24 1 read-only VSWEND Voltage switch critical timing section completion 25 1 read-only CKSTOP SDMMC_CK stopped in Voltage switch procedure 26 1 read-only IDMATE IDMA transfer error 27 1 read-only IDMABTC IDMA buffer transfer complete 28 1 read-only ICR ICR SDMMC interrupt clear register 0x38 0x20 read-write 0x00000000 0xFFFFFFFF CCRCFAILC CCRCFAIL flag clear bit 0 1 read-write DCRCFAILC DCRCFAIL flag clear bit 1 1 read-write CTIMEOUTC CTIMEOUT flag clear bit 2 1 read-write DTIMEOUTC DTIMEOUT flag clear bit 3 1 read-write TXUNDERRC TXUNDERR flag clear bit 4 1 read-write RXOVERRC RXOVERR flag clear bit 5 1 read-write CMDRENDC CMDREND flag clear bit 6 1 read-write CMDSENTC CMDSENT flag clear bit 7 1 read-write DATAENDC DATAEND flag clear bit 8 1 read-write DHOLDC DHOLD flag clear bit 9 1 read-write DBCKENDC DBCKEND flag clear bit 10 1 read-write DABORTC DABORT flag clear bit 11 1 read-write BUSYD0ENDC BUSYD0END flag clear bit 21 1 read-write SDIOITC SDIOIT flag clear bit 22 1 read-write ACKFAILC ACKFAIL flag clear bit 23 1 read-write ACKTIMEOUTC ACKTIMEOUT flag clear bit 24 1 read-write VSWENDC VSWEND flag clear bit 25 1 read-write CKSTOPC CKSTOP flag clear bit 26 1 read-write IDMATEC IDMA transfer error clear bit 27 1 read-write IDMABTCC IDMA buffer transfer complete clear bit 28 1 read-write MASKR MASKR SDMMC mask register 0x3C 0x20 read-write 0x00000000 0xFFFFFFFF CCRCFAILIE Command CRC fail interrupt enable 0 1 read-write DCRCFAILIE Data CRC fail interrupt enable 1 1 read-write CTIMEOUTIE Command timeout interrupt enable 2 1 read-write DTIMEOUTIE Data timeout interrupt enable 3 1 read-write TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 read-write RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 read-write CMDRENDIE Command response received interrupt enable 6 1 read-write CMDSENTIE Command sent interrupt enable 7 1 read-write DATAENDIE Data end interrupt enable 8 1 read-write DHOLDIE Data hold interrupt enable 9 1 read-write DBCKENDIE Data block end interrupt enable 10 1 read-write DABORTIE Data transfer aborted interrupt enable 11 1 read-write TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 read-write RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 read-write RXFIFOFIE Rx FIFO full interrupt enable 17 1 read-write TXFIFOEIE Tx FIFO empty interrupt enable 18 1 read-write BUSYD0ENDIE BUSYD0END interrupt enable 21 1 read-write SDIOITIE SDIO mode interrupt received interrupt enable 22 1 read-write ACKFAILIE Acknowledgment Fail interrupt enable 23 1 read-write ACKTIMEOUTIE Acknowledgment timeout interrupt enable 24 1 read-write VSWENDIE Voltage switch critical timing section completion interrupt enable 25 1 read-write CKSTOPIE Voltage Switch clock stopped interrupt enable 26 1 read-write IDMABTCIE IDMA buffer transfer complete interrupt enable 28 1 read-write ACKTIMER ACKTIMER SDMMC acknowledgment timer register 0x40 0x20 read-write 0x00000000 0xFFFFFFFF ACKTIME Boot acknowledgment timeout period 0 25 read-write IDMACTRLR IDMACTRLR SDMMC DMA control register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF IDMAEN IDMA enable 0 1 read-write IDMABMODE Buffer mode selection 1 1 read-write IDMABSIZER IDMABSIZER SDMMC IDMA buffer size register 0x54 0x20 read-write 0x00000000 0xFFFFFFFF IDMABNDT Number of bytes per buffer 5 12 read-write IDMABASER IDMABASER SDMMC IDMA buffer base address register 0x58 0x20 read-write 0x00000000 0xFFFFFFFF IDMABASE Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only) 0 32 read-write IDMALAR IDMALAR SDMMC IDMA linked list address register 0x64 0x20 read-write 0x00000000 0xFFFFFFFF IDMALA Word aligned linked list item address offset 2 14 read-write ABR Acknowledge linked list buffer ready 29 1 read-write ULS Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR. 30 1 read-write ULA Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR. 31 1 read-write IDMABAR IDMABAR SDMMC IDMA linked list memory base register 0x68 0x20 read-write 0x00000000 0xFFFFFFFF IDMABA Word aligned Linked list memory base address 2 30 read-write 16 0x4 0-15 FIFOR%s FIFOR%s SDMMC data FIFO registers %s 0x80 0x20 read-write 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write SDMMC1_S 0x56008000 SPI1 SPI address block description SPI 0x40013000 0x0 0x54 registers SPI1 SPI1 global interrupt 55 CR1 CR1 SPI/I2S control register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF SPE serial peripheral enable 0 1 read-write SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 MASRX master automatic suspension in Receive mode 8 1 read-write MASRX Disabled Automatic suspend in master receive-only mode disabled 0 Enabled Automatic suspend in master receive-only mode enabled 1 CSTART master transfer start 9 1 read-write CSTART NotStarted Do not start master transfer 0 Started Start master transfer 1 CSUSP master suspend request 10 1 write-only CSUSPW NotRequested Do not request master suspend 0 Requested Request master suspend 1 HDDIR Rx/Tx direction at half-duplex mode 11 1 read-write HDDIR Receiver Receiver in half duplex mode 0 Transmitter Transmitter in half duplex mode 1 SSI internal SS signal input level 12 1 read-write SSI SlaveSelected 0 is forced onto the SS signal and the I/O value of the SS pin is ignored 0 SlaveNotSelected 1 is forced onto the SS signal and the I/O value of the SS pin is ignored 1 CRC33_17 32-bit CRC polynomial configuration 13 1 read-write CRC33_17 Disabled Full size (33/17 bit) CRC polynomial is not used 0 Enabled Full size (33/17 bit) CRC polynomial is used 1 RCRCINI CRC calculation initialization pattern control for receiver 14 1 read-write RCRCINI AllZeros All zeros RX CRC initialization pattern 0 AllOnes All ones RX CRC initialization pattern 1 TCRCINI CRC calculation initialization pattern control for transmitter 15 1 read-write TCRCINI AllZeros All zeros TX CRC initialization pattern 0 AllOnes All ones TX CRC initialization pattern 1 IOLOCK locking the AF configuration of associated I/Os 16 1 read-write IOLOCK Unlocked IO configuration unlocked 0 Locked IO configuration locked 1 CR2 CR2 SPI/I2S control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF TSIZE number of data at current transfer 0 16 read-write 0 65535 CFG1 CFG1 SPI/I2S configuration register 1 0x8 0x20 read-write 0x00070007 0xFFFFFFFF DSIZE number of bits in a single SPI data frame 0 5 read-write 0 31 FTHLV FIFO threshold level 5 4 read-write FTHLV OneFrame 1 frame 0 TwoFrames 2 frames 1 ThreeFrames 3 frames 2 FourFrames 4 frames 3 FiveFrames 5 frames 4 SixFrames 6 frames 5 SevenFrames 7 frames 6 EightFrames 8 frames 7 NineFrames 9 frames 8 TenFrames 10 frames 9 ElevenFrames 11 frames 10 TwelveFrames 12 frames 11 ThirteenFrames 13 frames 12 FourteenFrames 14 frames 13 FifteenFrames 15 frames 14 SixteenFrames 16 frames 15 UDRCFG behavior of slave transmitter at underrun condition 9 1 read-write UDRCFG Constant Slave sends a constant underrun pattern 0 RepeatReceived Slave repeats last received data frame from master 1 RXDMAEN Rx DMA stream enable 14 1 read-write RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx DMA stream enable 15 1 read-write TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 CRCSIZE length of CRC frame to be transacted and compared 16 5 read-write 0 31 CRCEN hardware CRC computation enable 22 1 read-write CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 MBR master baud rate prescaler setting 28 3 read-write MBR Div2 f_spi_ker_ck / 2 0 Div4 f_spi_ker_ck / 4 1 Div8 f_spi_ker_ck / 8 2 Div16 f_spi_ker_ck / 16 3 Div32 f_spi_ker_ck / 32 4 Div64 f_spi_ker_ck / 64 5 Div128 f_spi_ker_ck / 128 6 Div256 f_spi_ker_ck / 256 7 BPASS bypass of the prescaler at master baud rate clock generator 31 1 read-write BPASS Disabled Bypass is disabled 0 Enabled Bypass is enabled 1 CFG2 CFG2 SPI/I2S configuration register 2 0xC 0x20 read-write 0x00000000 0xFFFFFFFF MSSI Master SS Idleness 0 4 read-write 0 15 MIDI master Inter-Data Idleness 4 4 read-write 0 15 RDIOM RDY signal input/output management 13 1 read-write RDIOM Active RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) 0 Pin RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) 1 RDIOP RDY signal input/output polarity 14 1 read-write RDIOP High high level of the signal means the slave is ready for communication 0 Low low level of the signal means the slave is ready for communication 1 IOSWP swap functionality of MISO and MOSI pins 15 1 read-write IOSWP Disabled MISO and MOSI not swapped 0 Enabled MISO and MOSI swapped 1 COMM SPI Communication Mode 17 2 read-write COMM FullDuplex Full duplex 0 Transmitter Simplex transmitter only 1 Receiver Simplex receiver only 2 HalfDuplex Half duplex 3 SP serial protocol 19 3 read-write SP Motorola Motorola SPI protocol 0 TI TI SPI protocol 1 MASTER SPI master 22 1 read-write MASTER Slave Slave configuration 0 Master Master configuration 1 LSBFRST data frame format 23 1 read-write LSBFRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 CPHA clock phase 24 1 read-write CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CPOL clock polarity 25 1 read-write CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 SSM software management of SS signal input 26 1 read-write SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSIOP SS input/output polarity 28 1 read-write SSIOP ActiveLow Low level is active for SS signal 0 ActiveHigh High level is active for SS signal 1 SSOE SS output enable 29 1 read-write SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 SSOM SS output management in master mode 30 1 read-write SSOM Asserted SS is asserted until data transfer complete 0 NotAsserted Data frames interleaved with SS not asserted during MIDI 1 AFCNTR alternate function GPIOs control 31 1 read-write AFCNTR NotControlled Peripheral takes no control of GPIOs while disabled 0 Controlled Peripheral controls GPIOs while disabled 1 IER IER SPI/I2S interrupt enable register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF RXPIE RXP interrupt enable 0 1 read-write RXPIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TXPIE TXP interrupt enable 1 1 read-write DXPIE DXP interrupt enabled 2 1 read-write EOTIE EOT, SUSP and TXC interrupt enable 3 1 read-write TXTFIE TXTFIE interrupt enable 4 1 read-write UDRIE UDR interrupt enable 5 1 read-write OVRIE OVR interrupt enable 6 1 read-write CRCEIE CRC error interrupt enable 7 1 read-write TIFREIE TIFRE interrupt enable 8 1 read-write MODFIE mode Fault interrupt enable 9 1 read-write SR SR SPI/I2S status register 0x14 0x20 read-only 0x00001002 0xFFFFFFFF RXP Rx-packet available 0 1 read-only RXP Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXP Tx-packet space available 1 1 read-only TXP Full Tx buffer full 0 NotFull Tx buffer not full 1 DXP duplex packet 2 1 read-only DXP Unavailable Duplex packet unavailable: no space for transmission and/or no data received 0 Available Duplex packet available: space for transmission and data received 1 EOT end of transfer 3 1 read-only EOT NotCompleted Transfer ongoing or not started 0 Completed Transfer complete 1 TXTF transmission transfer filled 4 1 read-only TXTF NotCompleted Transmission buffer incomplete 0 Completed Transmission buffer filled with at least one transfer 1 UDR underrun 5 1 read-only UDR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 OVR overrun 6 1 read-only OVR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 CRCE CRC error 7 1 read-only CRCE NoError No CRC error detected 0 Error CRC error detected 1 TIFRE TI frame format error 8 1 read-only TIFRE NoError TI frame format error detected 0 Error TI frame format error detected 1 MODF mode fault 9 1 read-only MODF NoFault No mode fault detected 0 Fault Mode fault detected 1 SUSP suspension status 11 1 read-only SUSP NotSuspended Master not suspended 0 Suspended Master suspended 1 TXC TxFIFO transmission complete 12 1 read-only TXC Ongoing Transmission ongoing 0 Completed Transmission completed 1 RXPLVL RxFIFO packing level 13 2 read-only RXPLVL ZeroFrames Zero frames beyond packing ratio available 0 OneFrame One frame beyond packing ratio available 1 TwoFrames Two frame beyond packing ratio available 2 ThreeFrames Three frame beyond packing ratio available 3 RXWNE RxFIFO word not empty 15 1 read-only RXWNE LessThan32 Less than 32-bit data frame received 0 AtLeast32 At least 32-bit data frame received 1 CTSIZE number of data frames remaining in current TSIZE session 16 16 read-only 0 65535 IFCR IFCR SPI/I2S interrupt/status flags clear register 0x18 0x20 write-only 0x00000000 0xFFFFFFFF EOTC end of transfer flag clear 3 1 write-only oneToClear EOTCW Clear Clear interrupt flag 1 TXTFC transmission transfer filled flag clear 4 1 write-only oneToClear UDRC underrun flag clear 5 1 write-only oneToClear OVRC overrun flag clear 6 1 write-only oneToClear CRCEC CRC error flag clear 7 1 write-only oneToClear TIFREC TI frame format error flag clear 8 1 write-only oneToClear MODFC mode fault flag clear 9 1 write-only oneToClear SUSPC Suspend flag clear 11 1 write-only oneToClear TXDR TXDR /I2SSPI/I2S transmit data register 0x20 0x20 write-only 0x00000000 0xFFFFFFFF TXDR transmit data register 0 32 write-only 0 4294967295 TXDR16 Direct 16-bit access to transmit data register TXDR 0x20 0x10 write-only TXDR Transmit data register 0 16 0 65535 TXDR8 Direct 8-bit access to transmit data register TXDR 0x20 0x8 write-only TXDR Transmit data register 0 8 0 255 RXDR RXDR SPI/I2S receive data register 0x30 0x20 read-only 0x00000000 0xFFFFFFFF RXDR receive data register 0 32 read-only RXDR16 Direct 16-bit access to receive data register RXDR 0x30 0x10 read-only RXDR Receive data register 0 16 RXDR8 Direct 8-bit access to receive data register RXDR 0x30 0x8 read-only RXDR Receive data register 0 8 CRCPOLY CRCPOLY SPI/I2S polynomial register 0x40 0x20 read-write 0x00000107 0xFFFFFFFF CRCPOLY CRC polynomial register 0 32 read-write 0 4294967295 TXCRC TXCRC SPI/I2S transmitter CRC register 0x44 0x20 read-only 0x00000000 0xFFFFFFFF TXCRC CRC register for transmitter 0 32 read-only 0 4294967295 RXCRC RXCRC SPI/I2S receiver CRC register 0x48 0x20 read-only 0x00000000 0xFFFFFFFF RXCRC CRC register for receiver 0 32 read-only 0 4294967295 UDRDR UDRDR SPI underrun data register 0x4C 0x20 read-write 0x00000000 0xFFFFFFFF UDRDR data at slave underrun condition 0 32 read-write 0 4294967295 I2SCFGR I2SCFGR SPI/I2S configuration register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF I2SMOD I2S mode selection 0 1 read-write I2SMOD SPI SPI mode selected 0 I2S I2S/PCM mode selected 1 I2SCFG I2S configuration mode 1 3 read-write I2SCFG SlaveTransmit Slave, transmit 0 SlaveReceive Slave, recteive 1 MasterTransmit Master, transmit 2 MasterReceive Master, receive 3 SlaveFullDuplex Slave, full duplex 4 MasterFullDuplex Master, full duplex 5 I2SSTD Iless thansup>2less than/sup>S standard selection 4 2 read-write I2SSTD Philips I2S Philips standard 0 LeftAligned MSB/left justified standard 1 RightAligned LSB/right justified standard 2 PCM PCM standard 3 PCMSYNC PCM frame synchronization 7 1 read-write PCMSYNC Short Short PCM frame synchronization 0 Long Long PCM frame synchronization 1 DATLEN data length to be transferred. 8 2 read-write DATLEN Bits16 16 bit data length 0 Bits24 24 bit data length 1 Bits32 32 bit data length 2 CHLEN channel length (number of bits per audio channel) 10 1 read-write CHLEN Bits16 16 bit per channel 0 Bits32 32 bit per channel 1 CKPOL serial audio clock polarity 11 1 read-write CKPOL SampleOnRising Signals are sampled on rising and changed on falling clock edges 0 SampleOnFalling Signals are sampled on falling and changed on rising clock edges 1 FIXCH fixed channel length in slave 12 1 read-write FIXCH NotFixed The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account) 0 Fixed The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN) 1 WSINV word select inversion 13 1 read-write WSINV Disabled Word select inversion disabled 0 Enabled Word select inversion enabled 1 DATFMT data format 14 1 read-write DATFMT RightAligned The data inside RXDR and TXDR are right aligned 0 LeftAligned The data inside RXDR and TXDR are left aligned 1 I2SDIV Iless thansup>2less than/sup>S linear prescaler 16 8 read-write ODD odd factor for the prescaler 24 1 read-write ODD Even Real divider value is I2SDIV*2 0 Odd Real divider value is I2SDIV*2 + 1 1 MCKOE master clock output enable 25 1 read-write MCKOE Disabled Master clock output disabled 0 Enabled Master clock output enabled 1 SPI1_S 0x50013000 SPI2 0x40003800 SPI2 SPI2 global interrupt 56 SPI2_S 0x50003800 SPI3 0x40003C00 SPI3 SPI3 global interrupt 57 SPI3_S 0x50003C00 SPI4 0x40014C00 SPI4 SPI4 global interrupt 82 SPI4_S 0x50014C00 TAMP TAMP register block TAMP 0x44007C00 0x0 0x400 registers TAMP Tamper global interrupts 4 CR1 CR1 TAMP control register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF TAMP1E Tamper detection on TAMP_IN1 enable 0 1 read-write TAMP2E Tamper detection on TAMP_IN2 enableless thansup>(1)less than/sup> 1 1 read-write TAMP3E Tamper detection on TAMP_IN3 enableless thansup>(1)less than/sup> 2 1 read-write TAMP4E Tamper detection on TAMP_IN4 enableless thansup>(1)less than/sup> 3 1 read-write TAMP5E Tamper detection on TAMP_IN5 enableless thansup>(1)less than/sup> 4 1 read-write TAMP6E Tamper detection on TAMP_IN6 enableless thansup>(1)less than/sup> 5 1 read-write TAMP7E Tamper detection on TAMP_IN7 enableless thansup>(1)less than/sup> 6 1 read-write TAMP8E Tamper detection on TAMP_IN8 enableless thansup>(1)less than/sup> 7 1 read-write ITAMP1E Internal tamper 1 enable 16 1 read-write ITAMP2E Internal tamper 2 enable 17 1 read-write ITAMP3E Internal tamper 3 enable 18 1 read-write ITAMP4E Internal tamper 4 enable 19 1 read-write ITAMP5E Internal tamper 5 enable 20 1 read-write ITAMP6E Internal tamper 6 enable 21 1 read-write ITAMP7E Internal tamper 7 enable 22 1 read-write ITAMP8E Internal tamper 8 enable 23 1 read-write ITAMP9E Internal tamper 9 enable 24 1 read-write ITAMP11E Internal tamper 11 enable 26 1 read-write ITAMP12E Internal tamper 12 enable 27 1 read-write ITAMP13E Internal tamper 13 enable 28 1 read-write ITAMP15E Internal tamper 15 enable 30 1 read-write CR2 CR2 TAMP control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF TAMP1POM Tamper 1 potential mode 0 1 read-write TAMP2POM Tamper 2 potential mode 1 1 read-write TAMP3POM Tamper 3 potential mode 2 1 read-write TAMP4POM Tamper 4 potential mode 3 1 read-write TAMP5POM Tamper 5 potential mode 4 1 read-write TAMP6POM Tamper 6 potential mode 5 1 read-write TAMP7POM Tamper 7 potential mode 6 1 read-write TAMP8POM Tamper 8 potential mode 7 1 read-write TAMP1MSK Tamper 1 mask 16 1 read-write TAMP2MSK Tamper 2 mask 17 1 read-write TAMP3MSK Tamper 3 mask 18 1 read-write BKBLOCK Backup registers and device secretsless thansup>(1)less than/sup> access blocked 22 1 read-write BKERASE Backup registers and device secretsless thansup>(1)less than/sup> erase 23 1 write-only TAMP1TRG Active level for tamper 1 input 24 1 read-write TAMP2TRG Active level for tamper 2 input 25 1 read-write TAMP3TRG Active level for tamper 3 input 26 1 read-write TAMP4TRG Active level for tamper 4 input (active mode disabled) 27 1 read-write TAMP5TRG Active level for tamper 5 input (active mode disabled) 28 1 read-write TAMP6TRG Active level for tamper 6 input (active mode disabled) 29 1 read-write TAMP7TRG Active level for tamper 7 input (active mode disabled) 30 1 read-write TAMP8TRG Active level for tamper 8 input (active mode disabled) 31 1 read-write CR3 CR3 TAMP control register 3 0x8 0x20 read-write 0x00000000 0xFFFFFFFF ITAMP1POM Internal tamper 1 potential mode 0 1 read-write ITAMP2POM Internal tamper 2 potential mode 1 1 read-write ITAMP3POM Internal tamper 3 potential mode 2 1 read-write ITAMP4POM Internal tamper 4 potential mode 3 1 read-write ITAMP5POM Internal tamper 5 potential mode 4 1 read-write ITAMP6POM Internal tamper 6 potential mode 5 1 read-write ITAMP7POM Internal tamper 7 potential mode 6 1 read-write ITAMP8POM Internal tamper 8 potential mode 7 1 read-write ITAMP9POM Internal tamper 9 potential mode 8 1 read-write ITAMP11POM Internal tamper 11 potential mode 10 1 read-write ITAMP12POM Internal tamper 12 potential mode 11 1 read-write ITAMP13POM Internal tamper 13 potential mode 12 1 read-write ITAMP15POM Internal tamper 15 potential mode 14 1 read-write FLTCR FLTCR TAMP filter control register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF TAMPFREQ Tamper sampling frequency 0 3 read-write TAMPFLT TAMP_INx filter count 3 2 read-write TAMPPRCH TAMP_INx precharge duration 5 2 read-write TAMPPUDIS TAMP_INx pull-up disable 7 1 read-write ATCR1 ATCR1 TAMP active tamper control register 1 0x10 0x20 read-write 0x00070000 0xFFFFFFFF TAMP1AM Tamper 1 active mode 0 1 read-write TAMP2AM Tamper 2 active mode 1 1 read-write TAMP3AM Tamper 3 active mode 2 1 read-write TAMP4AM Tamper 4 active mode 3 1 read-write TAMP5AM Tamper 5 active mode 4 1 read-write TAMP6AM Tamper 6 active mode 5 1 read-write TAMP7AM Tamper 7 active mode 6 1 read-write TAMP8AM Tamper 8 active mode 7 1 read-write ATOSEL1 Active tamper shared output 1 selection 8 2 read-write ATOSEL2 Active tamper shared output 2 selection 10 2 read-write ATOSEL3 Active tamper shared output 3 selection 12 2 read-write ATOSEL4 Active tamper shared output 4 selection 14 2 read-write ATCKSEL Active tamper RTC asynchronous prescaler clock selection 16 4 read-write ATPER Active tamper output change period 24 3 read-write ATOSHARE Active tamper output sharing 30 1 read-write FLTEN Active tamper filter enable 31 1 read-write ATSEEDR ATSEEDR TAMP active tamper seed register 0x14 0x20 write-only 0x00000000 0xFFFFFFFF SEED Pseudo-random generator seed value 0 32 write-only ATOR ATOR TAMP active tamper output register 0x18 0x20 read-only 0x00000000 0xFFFFFFFF PRNG Pseudo-random generator value 0 8 read-only SEEDF Seed running flag 14 1 read-only INITS Active tamper initialization status 15 1 read-only ATCR2 ATCR2 TAMP active tamper control register 2 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF ATOSEL1 Active tamper shared output 1 selection 8 3 read-write ATOSEL2 Active tamper shared output 2 selection 11 3 read-write ATOSEL3 Active tamper shared output 3 selection 14 3 read-write ATOSEL4 Active tamper shared output 4 selection 17 3 read-write ATOSEL5 Active tamper shared output 5 selection 20 3 read-write ATOSEL6 Active tamper shared output 6 selection 23 3 read-write ATOSEL7 Active tamper shared output 7 selection 26 3 read-write ATOSEL8 Active tamper shared output 8 selection 29 3 read-write SECCFGR SECCFGR TAMP secure configuration register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF BKPRWSEC Backup registers read/write protection offset 0 8 read-write CNT1SEC Monotonic counter 1 secure protection 15 1 read-write BKPWSEC Backup registers write protection offset 16 8 read-write BHKLOCK Boot hardware key lock 30 1 read-write TAMPSEC Tamper protection (excluding monotonic counters and backup registers) 31 1 read-write PRIVCFGR PRIVCFGR TAMP privilege configuration register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF CNT1PRIV Monotonic counter 1 privilege protection 15 1 read-write BKPRWPRIV Backup registers zone 1 privilege protection 29 1 read-write BKPWPRIV Backup registers zone 2 privilege protection 30 1 read-write TAMPPRIV Tamper privilege protection (excluding backup registers) 31 1 read-write IER IER TAMP interrupt enable register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF TAMP1IE Tamper 1 interrupt enable 0 1 read-write TAMP2IE Tamper 2 interrupt enable 1 1 read-write TAMP3IE Tamper 3 interrupt enable 2 1 read-write TAMP4IE Tamper 4 interrupt enable 3 1 read-write TAMP5IE Tamper 5 interrupt enable 4 1 read-write TAMP6IE Tamper 6 interrupt enable 5 1 read-write TAMP7IE Tamper 7interrupt enable 6 1 read-write TAMP8IE Tamper 8 interrupt enable 7 1 read-write ITAMP1IE Internal tamper 1 interrupt enable 16 1 read-write ITAMP2IE Internal tamper 2 interrupt enable 17 1 read-write ITAMP3IE Internal tamper 3 interrupt enable 18 1 read-write ITAMP4IE Internal tamper 4 interrupt enable 19 1 read-write ITAMP5IE Internal tamper 5 interrupt enable 20 1 read-write ITAMP6IE Internal tamper 6 interrupt enable 21 1 read-write ITAMP7IE Internal tamper 7 interrupt enable 22 1 read-write ITAMP8IE Internal tamper 8 interrupt enable 23 1 read-write ITAMP9IE Internal tamper 9 interrupt enable 24 1 read-write ITAMP11IE Internal tamper 11 interrupt enable 26 1 read-write ITAMP12IE Internal tamper 12 interrupt enable 27 1 read-write ITAMP13IE Internal tamper 13 interrupt enable 28 1 read-write ITAMP15IE Internal tamper 15 interrupt enable 30 1 read-write SR SR TAMP status register 0x30 0x20 read-write 0x00000000 0xFFFFFFFF TAMP1F TAMP1 detection flag 0 1 read-only TAMP2F TAMP2 detection flag 1 1 read-only TAMP3F TAMP3 detection flag 2 1 read-only TAMP4F TAMP4 detection flag 3 1 read-only TAMP5F TAMP5 detection flag 4 1 read-only TAMP6F TAMP6 detection flag 5 1 read-only TAMP7F TAMP7 detection flag 6 1 read-only TAMP8F TAMP8 detection flag 7 1 read-only ITAMP1F Internal tamper 1 flag 16 1 read-only ITAMP2F Internal tamper 2 flag 17 1 read-only ITAMP3F Internal tamper 3 flag 18 1 read-only ITAMP4F Internal tamper 4 flag 19 1 read-only ITAMP5F Internal tamper 5 flag 20 1 read-only ITAMP6F Internal tamper 6 flag 21 1 read-only ITAMP7F Internal tamper 7 flag 22 1 read-only ITAMP8F Internal tamper 8 flag 23 1 read-only ITAMP9F Internal tamper 9 flag 24 1 read-only ITAMP11F Internal tamper 11 flag 26 1 read-only ITAMP12F Internal tamper 12 flag 27 1 read-only ITAMP13F Internal tamper 13 flag 28 1 read-only ITAMP15F Internal tamper 15 flag 30 1 read-write MISR MISR TAMP nonsecure masked interrupt status register 0x34 0x20 read-only 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 nonsecure interrupt masked flag 0 1 read-only TAMP2MF TAMP2 nonsecure interrupt masked flag 1 1 read-only TAMP3MF TAMP3 nonsecure interrupt masked flag 2 1 read-only TAMP4MF TAMP4 nonsecure interrupt masked flag 3 1 read-only TAMP5MF TAMP5 nonsecure interrupt masked flag 4 1 read-only TAMP6MF TAMP6 nonsecure interrupt masked flag 5 1 read-only TAMP7MF TAMP7 nonsecure interrupt masked flag 6 1 read-only TAMP8MF TAMP8 nonsecure interrupt masked flag 7 1 read-only ITAMP1MF Internal tamper 1 nonsecure interrupt masked flag 16 1 read-only ITAMP2MF Internal tamper 2 nonsecure interrupt masked flag 17 1 read-only ITAMP3MF Internal tamper 3 nonsecure interrupt masked flag 18 1 read-only ITAMP4MF Internal tamper 4 nonsecure interrupt masked flag 19 1 read-only ITAMP5MF Internal tamper 5 nonsecure interrupt masked flag 20 1 read-only ITAMP6MF Internal tamper 6 nonsecure interrupt masked flag 21 1 read-only ITAMP7MF Internal tamper 7 tamper nonsecure interrupt masked flag 22 1 read-only ITAMP8MF Internal tamper 8 nonsecure interrupt masked flag 23 1 read-only ITAMP9MF internal tamper 9 nonsecure interrupt masked flag 24 1 read-only ITAMP11MF internal tamper 11 nonsecure interrupt masked flag 26 1 read-only ITAMP12MF internal tamper 12 nonsecure interrupt masked flag 27 1 read-only ITAMP13MF internal tamper 13 nonsecure interrupt masked flag 28 1 read-only ITAMP15MF internal tamper 15 nonsecure interrupt masked flag 30 1 read-only SMISR SMISR TAMP secure masked interrupt status register 0x38 0x20 read-only 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 secure interrupt masked flag 0 1 read-only TAMP2MF TAMP2 secure interrupt masked flag 1 1 read-only TAMP3MF TAMP3 secure interrupt masked flag 2 1 read-only TAMP4MF TAMP4 secure interrupt masked flag 3 1 read-only TAMP5MF TAMP5 secure interrupt masked flag 4 1 read-only TAMP6MF TAMP6 secure interrupt masked flag 5 1 read-only TAMP7MF TAMP7 secure interrupt masked flag 6 1 read-only TAMP8MF TAMP8 secure interrupt masked flag 7 1 read-only ITAMP1MF Internal tamper 1 secure interrupt masked flag 16 1 read-only ITAMP2MF Internal tamper 2 secure interrupt masked flag 17 1 read-only ITAMP3MF Internal tamper 3 secure interrupt masked flag 18 1 read-only ITAMP4MF Internal tamper 4 secure interrupt masked flag 19 1 read-only ITAMP5MF Internal tamper 5 secure interrupt masked flag 20 1 read-only ITAMP6MF Internal tamper 6 secure interrupt masked flag 21 1 read-only ITAMP7MF Internal tamper 7 secure interrupt masked flag 22 1 read-only ITAMP8MF Internal tamper 8 secure interrupt masked flag 23 1 read-only ITAMP9MF internal tamper 9 secure interrupt masked flag 24 1 read-only ITAMP11MF internal tamper 11 secure interrupt masked flag 26 1 read-only ITAMP12MF internal tamper 12 secure interrupt masked flag 27 1 read-only ITAMP13MF internal tamper 13 secure interrupt masked flag 28 1 read-only ITAMP15MF internal tamper 15 secure interrupt masked flag 30 1 read-only SCR SCR TAMP status clear register 0x3C 0x20 write-only 0x00000000 0xFFFFFFFF CTAMP1F Clear TAMP1 detection flag 0 1 write-only CTAMP2F Clear TAMP2 detection flag 1 1 write-only CTAMP3F Clear TAMP3 detection flag 2 1 write-only CTAMP4F Clear TAMP4 detection flag 3 1 write-only CTAMP5F Clear TAMP5 detection flag 4 1 write-only CTAMP6F Clear TAMP6 detection flag 5 1 write-only CTAMP7F Clear TAMP7 detection flag 6 1 write-only CTAMP8F Clear TAMP8 detection flag 7 1 write-only CITAMP1F Clear ITAMP1 detection flag 16 1 write-only CITAMP2F Clear ITAMP2 detection flag 17 1 write-only CITAMP3F Clear ITAMP3 detection flag 18 1 write-only CITAMP4F Clear ITAMP4 detection flag 19 1 write-only CITAMP5F Clear ITAMP5 detection flag 20 1 write-only CITAMP6F Clear ITAMP6 detection flag 21 1 write-only CITAMP7F Clear ITAMP7 detection flag 22 1 write-only CITAMP8F Clear ITAMP8 detection flag 23 1 write-only CITAMP9F Clear ITAMP9 detection flag 24 1 write-only CITAMP11F Clear ITAMP11 detection flag 26 1 write-only CITAMP12F Clear ITAMP12 detection flag 27 1 write-only CITAMP13F Clear ITAMP13 detection flag 28 1 write-only CITAMP15F Clear ITAMP15 detection flag 30 1 write-only COUNT1R COUNT1R TAMP monotonic counter 1 register 0x40 0x20 read-only 0x00000000 0xFFFFFFFF COUNT This register is read-only only and is incremented by one when a write access is done to this register. 0 32 read-only OR OR TAMP option register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF OUT3_RMP TAMP_OUT3 mapping 1 2 read-write OUT5_RMP TAMP_OUT5 mapping 3 1 read-write IN2_RMP TAMP_IN2 mapping 8 1 read-write IN3_RMP TAMP_IN3 mapping 9 1 read-write IN4_RMP TAMP_IN4 mapping 10 1 read-write RPCFGR RPCFGR TAMP resources protection configuration register 0x54 0x20 read-write 0x00000000 0xFFFFFFFF RPCFG0 Configurable resource 0 protection 0 1 read-write 32 0x4 0-31 BKP%sR BKP%sR TAMP backup %s register 0x100 0x20 read-write 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. 0 32 read-write TAMP_S 0x54007C00 TIM1 TIM1 address block description TIM 0x40012C00 0x0 0x3E4 registers TIM1_CC TIM1 capture compare interrupt 44 TIM1_TRGI_COM_DIR_IDX TIM1 trigger and commutation/TIM1 Direction Change interrupt/TIM1 Index 43 TIM1_UPD TIM1 Update 42 TIM1_BRK_TERR_IERR TIM1 Break/TIM1 Transition error/TIM1 Index error 41 CR1 CR1 TIM1 control register 1 0x0 0x10 read-write 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM1 control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF CCPC Capture/compare preloaded control 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS MMS[2:0]: Master mode selection 4 3 read-write 0 7 TI1S tim_ti1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 4 0x2 1-4 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 MMS2 Master mode selection 2 20 4 read-write MMS_3 MMS[3] 25 1 read-write 0 1 SMCR SMCR TIM1 slave mode control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection 0 3 read-write 0 7 OCCS OCREF clear selection 3 1 read-write TS TS[2:0]: Trigger selection 4 3 read-write 0 7 MSM Master/slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write 0 1 TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write 0 3 SMSPE SMS preload enable 24 1 read-write SMSPE NotPreloaded SMSM[3:0] is not preloaded 0 PreloadEnabled SMSM[3:0] is preload is enabled 1 SMSPS SMS preload source 25 1 read-write SMSPS Update SMSM[3:0] is preloaded from Update event 0 Index SMSM[3:0] is preloaded from Index event 1 DIER DIER TIM1 DMA/interrupt enable register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 read-write COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write IDXIE Disabled Index change interrupt disabled 0 Enabled Index change interrupt enabled 1 DIRIE Direction change interrupt enable 21 1 read-write DIRIE Disabled Direction change interrupt disabled 0 Enabled Direction change interrupt enabled 1 IERRIE Index error interrupt enable 22 1 read-write IERRIE Disabled Index error interrupt disabled 0 Enabled Index error interrupt enabled 1 TERRIE Transition error interrupt enable 23 1 read-write TERRIE Disabled Transition error interrupt disabled 0 Enabled Transition error interrupt enabled 1 SR SR TIM1 status register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF UIF Update interrupt flag 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 B2IF Break 2 interrupt flag 8 1 read-write zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 SBIF System break interrupt flag 13 1 read-write zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 CC5IF Compare 5 interrupt flag 16 1 read-write zeroToClear read write CC6IF Compare 6 interrupt flag 17 1 read-write zeroToClear read write IDXF Index interrupt flag 20 1 read-write zeroToClear IDXFR read NoTrigger No index event occurred 0 Trigger An index event has occurred 1 IDXFW write Clear Clear flag 0 DIRF Direction change interrupt flag 21 1 read-write zeroToClear DIRFR read NoTrigger No direction change has been detected 0 Trigger A direction change has been detected 1 DIRFW write Clear Clear flag 0 IERRF Index error interrupt flag 22 1 read-write zeroToClear IERRFR read NoTrigger No index error has been detected 0 Trigger An index erorr has been detected 1 IERRFW write Clear Clear flag 0 TERRF Transition error interrupt flag 23 1 read-write zeroToClear TERRFR read NoTrigger No encoder transition error has been detected 0 Trigger An encoder transition error has been detected 1 TERRFW write Clear Clear flag 0 EGR EGR TIM1 event generation register 0x14 0x10 write-only 0x00000000 0x0000FFFF UG Update generation 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/compare control update generation 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 B2G Break 2 generation 8 1 write-only B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Input CCMR1_Input TIM1 capture/compare mode register 1 0x18 0x20 read-write 0x00000000 0xFFFFFFFF CC1S Capture/compare 1 Selection 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM1 capture/compare mode register 1 CCMR1_Input 0x18 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM1 capture/compare mode register 2 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/compare 4 selection 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM1 capture/compare mode register 2 CCMR2_Input 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM1 capture/compare enable register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM1 counter 0x24 0x20 read-write 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY UIF copy 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM1 prescaler 0x28 0x10 read-write 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write 0 65535 ARR ARR TIM1 auto-reload register 0x2C 0x20 read-write 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write 0 1048575 RCR RCR TIM1 repetition counter register 0x30 0x10 read-write 0x00000000 0x0000FFFF REP Repetition counter reload value 0 16 read-write 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 BDTR BDTR TIM1 break and dead-time register 0x44 0x20 read-write 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write 0 255 LOCK Lock configuration 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for idle mode 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter 16 4 read-write BK2F Break 2 filter 20 4 read-write BK2E Break 2 enable 24 1 read-write BK2P Break 2 polarity 25 1 read-write BKDSRM Break disarm 26 1 read-write BK2DSRM Break2 disarm 27 1 read-write BKBID Break bidirectional 28 1 read-write BK2BID Break2 bidirectional 29 1 read-write CCR5 CCR5 capture/compare register 0x48 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 GC5C1 Group channel 5 and channel 1 29 1 read-write GC5C2 Group channel 5 and channel 2 30 1 read-write GC5C3 Group channel 5 and channel 3 31 1 read-write CCR6 CCR6 capture/compare register 0x4C 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 CCMR3_Output CCMR3_Output TIM1 capture/compare mode register 3 0x50 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 5-6 OC%sM Output compare %s mode 4 3 read-write 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write DTR2 DTR2 TIM1 timer deadtime register 2 0x54 0x20 read-write 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup 0 8 read-write DTAE Deadtime asymmetric enable 16 1 read-write DTPE Deadtime preload enable 17 1 read-write ECR ECR TIM1 timer encoder control register 0x58 0x20 read-write 0x00000000 0xFFFFFFFF IE Index enable 0 1 read-write IDIR Index direction 1 2 read-write IBLK Index blanking 3 2 read-write FIDX First index 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width 16 8 read-write PWPRSC Pulse width prescaler 24 3 read-write TISEL TISEL TIM1 timer input selection register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM1 alternate function option register 1 0x60 0x20 read-write 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable 0 1 read-write BKCMP1E tim_brk_cmp1 enable 1 1 read-write BKCMP2E tim_brk_cmp2 enable 2 1 read-write BKCMP3E tim_brk_cmp3 enable 3 1 read-write BKCMP4E tim_brk_cmp4 enable 4 1 read-write BKCMP5E tim_brk_cmp5 enable 5 1 read-write BKCMP6E tim_brk_cmp6 enable 6 1 read-write BKCMP7E tim_brk_cmp7 enable 7 1 read-write BKCMP8E tim_brk_cmp8 enable 8 1 read-write BKINP TIMx_BKIN input polarity 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity 13 1 read-write ETRSEL etr_in source selection 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM1 alternate function register 2 0x64 0x20 read-write 0x00000001 0xFFFFFFFF BK2INE TIMx_BKIN2 input enable 0 1 read-write BK2CMP1E tim_brk2_cmp1 enable 1 1 read-write BK2CMP2E tim_brk2_cmp2 enable 2 1 read-write BK2CMP3E tim_brk2_cmp3 enable 3 1 read-write BK2CMP4E tim_brk2_cmp4 enable 4 1 read-write BK2CMP5E tim_brk2_cmp5 enable 5 1 read-write BK2CMP6E tim_brk2_cmp6 enable 6 1 read-write BK2CMP7E tim_brk2_cmp7 enable 7 1 read-write BK2CMP8E tim_brk2_cmp8 enable 8 1 read-write BK2INP TIMx_BKIN2 input polarity 9 1 read-write BK2CMP1P tim_brk2_cmp1 input polarity 10 1 read-write BK2CMP2P tim_brk2_cmp2 input polarity 11 1 read-write BK2CMP3P tim_brk2_cmp3 input polarity 12 1 read-write BK2CMP4P tim_brk2_cmp4 input polarity 13 1 read-write OCRSEL ocref_clr source selection 16 3 read-write 0 7 DCR DCR TIM1 DMA control register 0x3DC 0x20 read-write 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write 0 31 DBL DMA burst length 8 5 read-write 0 18 DBSS DMA burst source selection 16 4 read-write 0 7 DMAR DMAR TIM1 DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM1_S TIM 0x50012C00 TIM2 TIM2 address block description TIM 0x40000000 0x0 0x3E4 registers TIM2 TIM2 global interrupt 45 CR1 CR1 TIM2 control register 1 0x0 0x10 read-write 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering Enable 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM2 control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS MMS[2:0]: Master mode selection 4 3 read-write 0 7 TI1S tim_ti1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS_3 MMS[3] 25 1 read-write 0 1 SMCR SMCR TIM2 slave mode control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection 0 3 read-write 0 7 OCCS OCREF clear selection 3 1 read-write TS TS[2:0]: Trigger selection 4 3 read-write 0 7 MSM Master/Slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write 0 1 TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write 0 3 SMSPE SMS preload enable 24 1 read-write SMSPE NotPreloaded SMSM[3:0] is not preloaded 0 PreloadEnabled SMSM[3:0] is preload is enabled 1 SMSPS SMS preload source 25 1 read-write SMSPS Update SMSM[3:0] is preloaded from Update event 0 Index SMSM[3:0] is preloaded from Index event 1 DIER DIER TIM2 DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write IDXIE Disabled Index change interrupt disabled 0 Enabled Index change interrupt enabled 1 DIRIE Direction change interrupt enable 21 1 read-write DIRIE Disabled Direction change interrupt disabled 0 Enabled Direction change interrupt enabled 1 IERRIE Index error interrupt enable 22 1 read-write IERRIE Disabled Index error interrupt disabled 0 Enabled Index error interrupt enabled 1 TERRIE Transition error interrupt enable 23 1 read-write TERRIE Disabled Transition error interrupt disabled 0 Enabled Transition error interrupt enabled 1 SR SR TIM2 status register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF UIF Update interrupt flag 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 IDXF Index interrupt flag 20 1 read-write zeroToClear IDXFR read NoTrigger No index event occurred 0 Trigger An index event has occurred 1 IDXFW write Clear Clear flag 0 DIRF Direction change interrupt flag 21 1 read-write zeroToClear DIRFR read NoTrigger No direction change has been detected 0 Trigger A direction change has been detected 1 DIRFW write Clear Clear flag 0 IERRF Index error interrupt flag 22 1 read-write zeroToClear IERRFR read NoTrigger No index error has been detected 0 Trigger An index erorr has been detected 1 IERRFW write Clear Clear flag 0 TERRF Transition error interrupt flag 23 1 read-write zeroToClear TERRFR read NoTrigger No encoder transition error has been detected 0 Trigger An encoder transition error has been detected 1 TERRFW write Clear Clear flag 0 EGR EGR TIM2 event generation register 0x14 0x10 write-only 0x00000000 0x0000FFFF UG Update generation 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM2 capture/compare mode register 1 0x18 0x20 read-write 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM2 capture/compare mode register 1 CCMR1_Input 0x18 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM2 capture/compare mode register 2 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM2 capture/compare mode register 2 CCMR2_Input 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM2 capture/compare enable register 0x20 0x10 read-write 0x00000000 0x0000FFFF 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM2 counter 0x24 0x20 read-write 0x00000000 0xFFFFFFFF CNT Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register holds the non-dithered part. The fractional part is not available. 0 32 read-write 0 4294967295 UIFCPY_CNT Value depends on IUFREMAP in TIMx_CR1. 31 1 read-write UIFCPY Read-only copy of the UIF bit of the TIMx_ISR register 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM2 prescaler 0x28 0x10 read-write 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write 0 65535 ARR ARR TIM2 auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF 0xFFFFFFFF ARR Auto-reload value 0 32 read-write 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 32 read-write 0 4294967295 ECR ECR TIM2 timer encoder control register 0x58 0x20 read-write 0x00000000 0xFFFFFFFF IE Index enable 0 1 read-write IDIR Index direction 1 2 read-write IBLK Index blanking 3 2 read-write FIDX First index 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width 16 8 read-write PWPRSC Pulse width prescaler 24 3 read-write TISEL TISEL TIM2 timer input selection register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM2 alternate function register 1 0x60 0x20 read-write 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM2 alternate function register 2 0x64 0x20 read-write 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection 16 3 read-write 0 7 DCR DCR TIM2 DMA control register 0x3DC 0x20 read-write 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write 0 31 DBL DMA burst length 8 5 read-write 0 18 DBSS DMA burst source selection 16 4 read-write 0 7 DMAR DMAR TIM2 DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM2_S TIM 0x50000000 TIM3 TIM3 address block description TIM 0x40000400 0x0 0x3E4 registers TIM3 TIM3 global interrupt 46 CR1 CR1 TIM3 control register 1 0x0 0x10 read-write 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering Enable 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM3 control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS MMS[2:0]: Master mode selection 4 3 read-write 0 7 TI1S tim_ti1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS_3 MMS[3] 25 1 read-write 0 1 SMCR SMCR TIM3 slave mode control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection 0 3 read-write 0 7 OCCS OCREF clear selection 3 1 read-write TS TS[2:0]: Trigger selection 4 3 read-write 0 7 MSM Master/Slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write 0 1 TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write 0 3 SMSPE SMS preload enable 24 1 read-write SMSPE NotPreloaded SMSM[3:0] is not preloaded 0 PreloadEnabled SMSM[3:0] is preload is enabled 1 SMSPS SMS preload source 25 1 read-write SMSPS Update SMSM[3:0] is preloaded from Update event 0 Index SMSM[3:0] is preloaded from Index event 1 DIER DIER TIM3 DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write IDXIE Disabled Index change interrupt disabled 0 Enabled Index change interrupt enabled 1 DIRIE Direction change interrupt enable 21 1 read-write DIRIE Disabled Direction change interrupt disabled 0 Enabled Direction change interrupt enabled 1 IERRIE Index error interrupt enable 22 1 read-write IERRIE Disabled Index error interrupt disabled 0 Enabled Index error interrupt enabled 1 TERRIE Transition error interrupt enable 23 1 read-write TERRIE Disabled Transition error interrupt disabled 0 Enabled Transition error interrupt enabled 1 SR SR TIM3 status register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF UIF Update interrupt flag 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 IDXF Index interrupt flag 20 1 read-write zeroToClear IDXFR read NoTrigger No index event occurred 0 Trigger An index event has occurred 1 IDXFW write Clear Clear flag 0 DIRF Direction change interrupt flag 21 1 read-write zeroToClear DIRFR read NoTrigger No direction change has been detected 0 Trigger A direction change has been detected 1 DIRFW write Clear Clear flag 0 IERRF Index error interrupt flag 22 1 read-write zeroToClear IERRFR read NoTrigger No index error has been detected 0 Trigger An index erorr has been detected 1 IERRFW write Clear Clear flag 0 TERRF Transition error interrupt flag 23 1 read-write zeroToClear TERRFR read NoTrigger No encoder transition error has been detected 0 Trigger An encoder transition error has been detected 1 TERRFW write Clear Clear flag 0 EGR EGR TIM3 event generation register 0x14 0x10 write-only 0x00000000 0x0000FFFF UG Update generation 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM3 capture/compare mode register 1 0x18 0x20 read-write 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM3 capture/compare mode register 1 CCMR1_Input 0x18 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM3 capture/compare mode register 2 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM3 capture/compare mode register 2 CCMR2_Input 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM3 capture/compare enable register 0x20 0x10 read-write 0x00000000 0x0000FFFF 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM3 counter 0x24 0x20 read-write 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY Value depends on IUFREMAP in TIMx_CR1. 31 1 read-write UIFCPYR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM3 prescaler 0x28 0x10 read-write 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write 0 65535 ARR ARR TIM3 auto-reload register 0x2C 0x20 read-write 0x0000FFFF 0xFFFFFFFF ARR Low Auto-reload value 0 20 read-write 0 1048575 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 ECR ECR TIM3 timer encoder control register 0x58 0x20 read-write 0x00000000 0xFFFFFFFF IE Index enable 0 1 read-write IDIR Index direction 1 2 read-write IBLK Index blanking 3 2 read-write FIDX First index 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width 16 8 read-write PWPRSC Pulse width prescaler 24 3 read-write TISEL TISEL TIM3 timer input selection register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM3 alternate function register 1 0x60 0x20 read-write 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM3 alternate function register 2 0x64 0x20 read-write 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection 16 3 read-write 0 7 DCR DCR TIM3 DMA control register 0x3DC 0x20 read-write 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write 0 31 DBL DMA burst length 8 5 read-write 0 18 DBSS DMA burst source selection 16 4 read-write 0 7 DMAR DMAR TIM3 DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM3_S TIM 0x50000400 TIM4 TIM4 address block description TIM 0x40000800 0x0 0x3E4 registers TIM4 TIM4 global interrupt 47 CR1 CR1 TIM4 control register 1 0x0 CR2 CR2 TIM4 control register 2 0x4 SMCR SMCR TIM4 slave mode control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection 0 3 read-write OCCS OCREF clear selection 3 1 read-write TS TS[2:0]: Trigger selection 4 3 read-write 0 7 MSM Master/Slave mode 7 1 read-write ETF External trigger filter 8 4 read-write ETPS External trigger prescaler 12 2 read-write ECE External clock enable 14 1 read-write ETP External trigger polarity 15 1 read-write SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write 0 3 SMSPE SMS preload enable 24 1 read-write SMSPS SMS preload source 25 1 read-write DIER DIER TIM4 DMA/Interrupt enable register 0xC SR SR TIM4 status register 0x10 EGR EGR TIM4 event generation register 0x14 CCMR1_Input CCMR1_Input TIM4 capture/compare mode register 1 0x18 CCMR1_Output CCMR1_Output TIM4 capture/compare mode register 1 CCMR1_Input 0x18 CCMR2_Input CCMR2_Input TIM4 capture/compare mode register 2 0x1C CCMR2_Output CCMR2_Output TIM4 capture/compare mode register 2 CCMR2_Input 0x1C CCER CCER TIM4 capture/compare enable register 0x20 CNT CNT TIM4 counter 0x24 PSC PSC TIM4 prescaler 0x28 ARR ARR TIM4 auto-reload register 0x2C 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 ECR ECR TIM4 timer encoder control register 0x58 TISEL TISEL TIM4 timer input selection register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM4 alternate function register 1 0x60 0x20 read-write 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM4 alternate function register 2 0x64 0x20 read-write 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection 16 3 read-write 0 7 DCR DCR TIM4 DMA control register 0x3DC DMAR DMAR TIM4 DMA address for full transfer 0x3E0 TIM4_S TIM 0x50000800 TIM5 TIM5 address block description TIM 0x40000C00 0x0 0x3E4 registers TIM5 TIM5 global interrupt 48 CR1 CR1 TIM5 control register 1 0x0 CR2 CR2 TIM5 control register 2 0x4 SMCR SMCR TIM5 slave mode control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection 0 3 read-write OCCS OCREF clear selection 3 1 read-write TS TS[2:0]: Trigger selection 4 3 read-write 0 7 MSM Master/Slave mode 7 1 read-write ETF External trigger filter 8 4 read-write ETPS External trigger prescaler 12 2 read-write ECE External clock enable 14 1 read-write ETP External trigger polarity 15 1 read-write SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write 0 3 SMSPE SMS preload enable 24 1 read-write SMSPS SMS preload source 25 1 read-write DIER DIER TIM5 DMA/Interrupt enable register 0xC SR SR TIM5 status register 0x10 EGR EGR TIM5 event generation register 0x14 CCMR1_Input CCMR1_Input TIM5 capture/compare mode register 1 0x18 CCMR1_Output CCMR1_Output TIM5 capture/compare mode register 1 CCMR1_Input 0x18 CCMR2_Input CCMR2_Input TIM5 capture/compare mode register 2 0x1C CCMR2_Output CCMR2_Output TIM5 capture/compare mode register 2 CCMR2_Input 0x1C CCER CCER TIM5 capture/compare enable register 0x20 CNT CNT TIM5 counter 0x24 PSC PSC TIM5 prescaler 0x28 ARR ARR TIM5 auto-reload register 0x2C 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 ECR ECR TIM5 timer encoder control register 0x58 TISEL TISEL TIM5 timer input selection register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM5 alternate function register 1 0x60 0x20 read-write 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM5 alternate function register 2 0x64 0x20 read-write 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection 16 3 read-write 0 7 DCR DCR TIM5 DMA control register 0x3DC DMAR DMAR TIM5 DMA address for full transfer 0x3E0 TIM5_S TIM 0x50000C00 TIM6 TIM6 address block description TIM 0x40001000 0x0 0x30 registers TIM6 TIM6 global interrupt 49 CR1 CR1 TIM6 control register 1 0x0 0x10 read-write 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM6 control register 2 0x4 0x10 read-write 0x00000000 0x0000FFFF MMS Master mode selection 4 3 read-write MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER TIM6 DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 SR SR TIM6 status register 0x10 0x10 read-write 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR TIM6 event generation register 0x14 0x10 write-only 0x00000000 0x0000FFFF UG Update generation 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT TIM6 counter 0x24 0x20 read-write 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY UIF copy 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM6 prescaler 0x28 0x10 read-write 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write 0 65535 ARR ARR TIM6 auto-reload register 0x2C 0x20 read-write 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write 0 1048575 TIM6_S TIM 0x50001000 TIM7 TIM7 address block description TIM 0x40001400 TIM7 TIM7 global interrupt 50 TIM7_S TIM 0x50001400 TIM8 TIM8 address block description TIM 0x40013400 0x0 0x3E4 registers TIM8_CC TIM8 capture compare interrupt 68 TIM8_TRGI_DIR_IDX TIM8 trigger and commutation interrupt/TIM8 Direction Change interrupt/TIM8 Index 67 TIM8_UPD TIM8 Update interrupt 66 TIM8_BRK_TERR_IERR TIM8 Break interrupt/TIM8 Transition error/TIM8 Index error 65 CR1 CR1 TIM8 control register 1 0x0 CR2 CR2 TIM8 control register 2 0x4 SMCR SMCR TIM8 slave mode control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection 0 3 read-write OCCS OCREF clear selection 3 1 read-write TS TS[2:0]: Trigger selection 4 3 read-write 0 7 MSM Master/slave mode 7 1 read-write ETF External trigger filter 8 4 read-write ETPS External trigger prescaler 12 2 read-write ECE External clock enable 14 1 read-write ETP External trigger polarity 15 1 read-write SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write 0 3 SMSPE SMS preload enable 24 1 read-write SMSPS SMS preload source 25 1 read-write DIER DIER TIM8 DMA/interrupt enable register 0xC SR SR TIM8 status register 0x10 EGR EGR TIM8 event generation register 0x14 CCMR1_Input CCMR1_Input TIM8 capture/compare mode register 1 0x18 CCMR1_Output CCMR1_Output TIM8 capture/compare mode register 1 CCMR1_Input 0x18 CCMR2_Input CCMR2_Input TIM8 capture/compare mode register 2 0x1C CCMR2_Output CCMR2_Output TIM8 capture/compare mode register 2 CCMR2_Input 0x1C CCER CCER TIM8 capture/compare enable register 0x20 CNT CNT TIM8 counter 0x24 PSC PSC TIM8 prescaler 0x28 ARR ARR TIM8 auto-reload register 0x2C RCR RCR TIM8 repetition counter register 0x30 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR TIM8 break and dead-time register 0x44 CCR5 CCR5 capture/compare register 0x48 CCR6 CCR6 capture/compare register 0x4C CCMR3_Output CCMR3_Output TIM8 capture/compare mode register 3 0x50 DTR2 DTR2 TIM8 timer deadtime register 2 0x54 ECR ECR TIM8 timer encoder control register 0x58 TISEL TISEL TIM8 timer input selection register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM8 alternate function option register 1 0x60 0x20 read-write 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable 0 1 read-write BKCMP1E tim_brk_cmp1 enable 1 1 read-write BKCMP2E tim_brk_cmp2 enable 2 1 read-write BKCMP3E tim_brk_cmp3 enable 3 1 read-write BKCMP4E tim_brk_cmp4 enable 4 1 read-write BKCMP5E tim_brk_cmp5 enable 5 1 read-write BKCMP6E tim_brk_cmp6 enable 6 1 read-write BKCMP7E tim_brk_cmp7 enable 7 1 read-write BKCMP8E tim_brk_cmp8 enable 8 1 read-write BKINP TIMx_BKIN input polarity 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity 13 1 read-write ETRSEL etr_in source selection 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM8 alternate function register 2 0x64 0x20 read-write 0x00000001 0xFFFFFFFF BK2INE TIMx_BKIN2 input enable 0 1 read-write BK2CMP1E tim_brk2_cmp1 enable 1 1 read-write BK2CMP2E tim_brk2_cmp2 enable 2 1 read-write BK2CMP3E tim_brk2_cmp3 enable 3 1 read-write BK2CMP4E tim_brk2_cmp4 enable 4 1 read-write BK2CMP5E tim_brk2_cmp5 enable 5 1 read-write BK2CMP6E tim_brk2_cmp6 enable 6 1 read-write BK2CMP7E tim_brk2_cmp7 enable 7 1 read-write BK2CMP8E tim_brk2_cmp8 enable 8 1 read-write BK2INP TIMx_BKIN2 input polarity 9 1 read-write BK2CMP1P tim_brk2_cmp1 input polarity 10 1 read-write BK2CMP2P tim_brk2_cmp2 input polarity 11 1 read-write BK2CMP3P tim_brk2_cmp3 input polarity 12 1 read-write BK2CMP4P tim_brk2_cmp4 input polarity 13 1 read-write OCRSEL ocref_clr source selection 16 3 read-write 0 7 DCR DCR TIM8 DMA control register 0x3DC DMAR DMAR TIM8 DMA address for full transfer 0x3E0 TIM8_S TIM 0x50013400 TIM12 General-purpose timers TIM 0x40001800 0x0 0x400 registers TIM12 TIM12 global interrupt 120 CR1 CR1 TIM12 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering Enable 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM12 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF MMS Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write SMCR SMCR TIM12 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS Slave mode selection 0 3 read-write TS Trigger selection (see bits 21:20 for TS[4:3]) 4 3 read-write MSM Master/Slave mode 7 1 read-write SMS_3 Slave mode selection 16 1 read-write TS2 Trigger selection (see bits 21:20 for TS[4:3]) 20 2 read-write DIER DIER TIM12 DMA/Interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 SR SR TIM12 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM12 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM12 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM12 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCER CCER TIM12 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM12 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT or UIFCPY: Value depends on IUFREMAP in TIMx_CR1. 0 16 read-write 0 65535 UIFCPY UIF Copy 31 1 read-write UIFCPYR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM12 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write 0 65535 ARR ARR TIM12 auto-reload register 0x2C 0x20 0xFFFFFFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write 0 1048575 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 TISEL TISEL TIM12 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[0..15] input 0 4 read-write TI2SEL Selects tim_ti2[0..15] input 8 4 read-write SEC_TIM12 0x50001800 TIM15 TIM15 address block description TIM 0x40014000 0x0 0x3E4 registers TIM15 TIM15 global interrupt 71 CR1 CR1 TIM15 control register 1 0x0 0x10 read-write 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM15 control register 2 0x4 0x10 read-write 0x00000000 0x0000FFFF CCPC Capture/compare preloaded control 0 1 read-write CCUS Capture/compare control update selection 2 1 read-write CCDS Capture/compare DMA selection 3 1 read-write MMS Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write 2 0x2 1-2 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 SMCR SMCR TIM15 slave mode control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection 0 3 read-write TS TS[2:0]: Trigger selection 4 3 read-write MSM Master/slave mode 7 1 read-write SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write SMSPE SMS preload enable 24 1 read-write DIER DIER TIM15 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 read-write UDE Update DMA request enable 8 1 read-write 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 read-write TDE Trigger DMA request enable 14 1 read-write SR SR TIM15 status register 0x10 0x10 read-write 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 read-write 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM15 event generation register 0x14 0x10 read-write 0x00000000 0x0000FFFF UG Update generation 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation 5 1 read-write TG Trigger generation 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation 7 1 write-only CCMR1_Input CCMR1_Input TIM15 capture/compare mode register 1 0x18 0x20 read-write 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/Compare 2 selection 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM15 capture/compare mode register 1 CCMR1_Input 0x18 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCER CCER TIM15 capture/compare enable register 0x20 0x10 read-write 0x00000000 0x0000FFFF 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM15 counter 0x24 0x20 read-write 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY UIF Copy 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM15 prescaler 0x28 0x10 read-write 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write 0 65535 ARR ARR TIM15 auto-reload register 0x2C 0x20 read-write 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write 0 1048575 RCR RCR TIM15 repetition counter register 0x30 0x10 read-write 0x00000000 0x0000FFFF REP Repetition counter reload value 0 8 read-write 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 BDTR BDTR TIM15 break and dead-time register 0x44 0x20 read-write 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write LOCK Lock configuration 8 2 read-write OSSI Off-state selection for Idle mode 10 1 read-write OSSR Off-state selection for Run mode 11 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write AOE Automatic output enable 14 1 read-write MOE Main output enable 15 1 read-write BKF Break filter 16 4 read-write BKDSRM Break disarm 26 1 read-write BKBID Break bidirectional 28 1 read-write DTR2 DTR2 TIM15 timer deadtime register 2 0x54 0x20 read-write 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup 0 8 read-write DTAE Deadtime asymmetric enable 16 1 read-write DTPE Deadtime preload enable 17 1 read-write TISEL TISEL TIM15 input selection register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF TI1SEL selects tim_ti1_in[15:0] input 0 4 read-write TI2SEL selects tim_ti2_in[15:0] input 8 4 read-write AF1 AF1 TIM15 alternate function register 1 0x60 0x20 read-write 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable 0 1 read-write BKCMP1E tim_brk_cmp1 enable 1 1 read-write BKCMP2E tim_brk_cmp2 enable 2 1 read-write BKCMP3E tim_brk_cmp3 enable 3 1 read-write BKCMP4E tim_brk_cmp4 enable 4 1 read-write BKCMP5E tim_brk_cmp5 enable 5 1 read-write BKCMP6E tim_brk_cmp6 enable 6 1 read-write BKCMP7E tim_brk_cmp7 enable 7 1 read-write BKCMP8E tim_brk_cmp8 enable 8 1 read-write BKINP TIMx_BKIN input polarity 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity 13 1 read-write AF2 AF2 TIM15 alternate function register 2 0x64 0x20 read-write 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection 16 3 read-write DCR DCR TIM15 DMA control register 0x3DC 0x20 read-write 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write DBL DMA burst length 8 5 read-write DBSS DMA burst source selection 16 4 read-write DMAR DMAR TIM15 DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM15_S TIM 0x50014000 UCPD1 UCPD register block UCPD 0x4000DC00 0x0 0x400 registers UCPD1 UCPD1 global interrupt 76 CFGR1 CFGR1 UCPD configuration register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF HBITCLKDIV Division ratio for producing half-bit clock 0 6 read-write IFRGAP Division ratio for producing inter-frame gap timer clock 6 5 read-write TRANSWIN Transition window duration 11 5 read-write PSC_USBPDCLK Pre-scaler division ratio for generating ucpd_clk 17 3 read-write TXDMAEN Transmission DMA mode enable 29 1 read-write RXDMAEN Reception DMA mode enable 30 1 read-write UCPDEN UCPD peripheral enable 31 1 read-write RXORDSETEN0 SOP detection 20 1 RXORDSETEN1 SOP' detection 21 1 RXORDSETEN2 SOP'' detection 22 1 RXORDSETEN3 Hard Reset detection 23 1 RXORDSETEN4 Cable Detect reset 24 1 RXORDSETEN5 SOP'_Debug 25 1 RXORDSETEN6 SOP'' Debug 26 1 RXORDSETEN7 SOP extension #1 27 1 RXORDSETEN8 SOP extension #2 28 1 CFGR2 CFGR2 UCPD configuration register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF RXFILTDIS BMC decoder Rx pre-filter enable 0 1 read-write RXFILT2N3 BMC decoder Rx pre-filter sampling method 1 1 read-write FORCECLK Force ClkReq clock request 2 1 read-write WUPEN Wake-up from Stop mode enable 3 1 read-write RXAFILTEN Rx analog filter enable 8 1 read-write CFGR3 CFGR3 UCPD configuration register 3 0x8 0x20 read-write 0x00000000 0xFFFFFFFF TRIM_CC1_RD SW trim value for Rd resistor on the CC1 line 0 4 read-write TRIM_CC1_RP SW trim value for Rp current sources on the CC1 line 9 4 read-write TRIM_CC2_RD SW trim value for Rd resistor on the CC2 line 16 4 read-write TRIM_CC2_RP SW trim value for Rp current sources on the CC2 line 25 4 read-write CR CR UCPD control register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF TXMODE Type of Tx packet 0 2 read-write TXSEND Command to send a Tx packet 2 1 read-write TXHRST Command to send a Tx Hard Reset 3 1 read-write RXMODE Receiver mode 4 1 read-write PHYRXEN USB Power Delivery receiver enable 5 1 read-write PHYCCSEL CC1/CC2 line selector for USB Power Delivery signaling 6 1 read-write ANASUBMODE Analog PHY sub-mode 7 2 read-write ANAMODE Analog PHY operating mode 9 1 read-write CCENABLE CC line enable 10 2 read-write FRSRXEN FRS event detection enable 16 1 read-write FRSTX FRS Tx signaling enable. 17 1 read-write RDCH Rdch condition drive 18 1 read-write CC1TCDIS CC1 Type-C detector disable 20 1 read-write CC2TCDIS CC2 Type-C detector disable 21 1 read-write IMR IMR UCPD interrupt mask register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF TXISIE TXIS interrupt enable 0 1 read-write TXMSGDISCIE TXMSGDISC interrupt enable 1 1 read-write TXMSGSENTIE TXMSGSENT interrupt enable 2 1 read-write TXMSGABTIE TXMSGABT interrupt enable 3 1 read-write HRSTDISCIE HRSTDISC interrupt enable 4 1 read-write HRSTSENTIE HRSTSENT interrupt enable 5 1 read-write TXUNDIE TXUND interrupt enable 6 1 read-write RXNEIE RXNE interrupt enable 8 1 read-write RXORDDETIE RXORDDET interrupt enable 9 1 read-write RXHRSTDETIE RXHRSTDET interrupt enable 10 1 read-write RXOVRIE RXOVR interrupt enable 11 1 read-write RXMSGENDIE RXMSGEND interrupt enable 12 1 read-write TYPECEVT1IE TYPECEVT1 interrupt enable 14 1 read-write TYPECEVT2IE TYPECEVT2 interrupt enable 15 1 read-write FRSEVTIE FRSEVT interrupt enable 20 1 read-only SR SR UCPD status register 0x14 0x20 read-only 0x00000000 0xFFFFFFFF TXIS Transmit interrupt status 0 1 read-only TXMSGDISC Message transmission discarded 1 1 read-only TXMSGSENT Message transmission completed 2 1 read-only TXMSGABT Transmit message abort 3 1 read-only HRSTDISC Hard Reset discarded 4 1 read-only HRSTSENT Hard Reset message sent 5 1 read-only TXUND Tx data underrun detection 6 1 read-only RXNE Receive data register not empty detection 8 1 read-only RXORDDET Rx ordered set (4 K-codes) detection 9 1 read-only RXHRSTDET Rx Hard Reset receipt detection 10 1 read-only RXOVR Rx data overflow detection 11 1 read-only RXMSGEND Rx message received 12 1 read-only RXERR Receive message error 13 1 read-only TYPECEVT1 Type-C voltage level event on CC1 line 14 1 read-only TYPECEVT2 Type-C voltage level event on CC2 line 15 1 read-only TYPEC_VSTATE_CC1 The status bitfield indicates the voltage level on the CC1 line in its steady state. 16 2 read-only TYPEC_VSTATE_CC2 CC2 line voltage level 18 2 read-only FRSEVT FRS detection event 20 1 read-only ICR ICR UCPD interrupt clear register 0x18 0x20 write-only 0x00000000 0xFFFFFFFF TXMSGDISCCF Tx message discard flag (TXMSGDISC) clear 1 1 write-only TXMSGSENTCF Tx message send flag (TXMSGSENT) clear 2 1 write-only TXMSGABTCF Tx message abort flag (TXMSGABT) clear 3 1 write-only HRSTDISCCF Hard reset discard flag (HRSTDISC) clear 4 1 write-only HRSTSENTCF Hard reset send flag (HRSTSENT) clear 5 1 write-only TXUNDCF Tx underflow flag (TXUND) clear 6 1 write-only RXORDDETCF Rx ordered set detect flag (RXORDDET) clear 9 1 write-only RXHRSTDETCF Rx Hard Reset detect flag (RXHRSTDET) clear 10 1 write-only RXOVRCF Rx overflow flag (RXOVR) clear 11 1 write-only RXMSGENDCF Rx message received flag (RXMSGEND) clear 12 1 write-only TYPECEVT1CF Type-C CC1 event flag (TYPECEVT1) clear 14 1 write-only TYPECEVT2CF Type-C CC2 line event flag (TYPECEVT2) clear 15 1 write-only FRSEVTCF FRS event flag (FRSEVT) clear 20 1 write-only TX_ORDSETR TX_ORDSETR UCPD Tx ordered set type register 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF TXORDSET Ordered set to transmit 0 20 read-write TX_PAYSZR TX_PAYSZR UCPD Tx payload size register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF TXPAYSZ Payload size yet to transmit 0 10 read-write TXDR TXDR UCPD Tx data register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF TXDATA Data byte to transmit 0 8 read-write RX_ORDSETR RX_ORDSETR UCPD Rx ordered set register 0x28 0x20 read-only 0x00000000 0xFFFFFFFF RXORDSET Rx ordered set code detected 0 3 read-only RXSOP3OF4 The bit indicates the number of correct K-codes. 3 1 read-only RXSOPKINVALID The bitfield is for debug purposes only. 4 3 read-only RX_PAYSZR RX_PAYSZR UCPD Rx payload size register 0x2C 0x20 read-only 0x00000000 0xFFFFFFFF RXPAYSZ Rx payload size received 0 10 read-only RXDR RXDR UCPD receive data register 0x30 0x20 read-only 0x00000000 0xFFFFFFFF RXDATA Data byte received 0 8 read-only RX_ORDEXTR1 RX_ORDEXTR1 UCPD Rx ordered set extension register 1 0x34 0x20 read-write 0x00000000 0xFFFFFFFF RXSOPX1 Ordered set 1 received 0 20 read-write RX_ORDEXTR2 RX_ORDEXTR2 UCPD Rx ordered set extension register 2 0x38 0x20 read-write 0x00000000 0xFFFFFFFF RXSOPX2 Ordered set 2 received 0 20 read-write UCPD1_S 0x5000DC00 USART1 USART address block description USART 0x40013800 0x0 0x30 registers USART1 USART1 global interrupt 58 CR1 CR1 USART control register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF UE USART enable 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM USART enable in low-power mode 1 1 read-write UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 RE Receiver enable 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wake-up method 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 OVER8 Oversampling mode 15 1 read-write OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 DEDT Driver Enable deassertion time 16 5 read-write 0 31 DEAT Driver Enable assertion time 21 5 read-write 0 31 RTOIE Receiver timeout interrupt enable 26 1 read-write RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 EOBIE End of block interrupt enable 27 1 read-write EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 M1 Word length 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO Full interrupt enable 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 USART control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF SLVEN Synchronous slave mode enable 0 1 read-write SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 DIS_NSS When the DIS_NSS bit is set, the NSS pin input is ignored. 3 1 read-write DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 LBDL LIN break detection length 5 1 read-write LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 LBDIE LIN break detection interrupt enable 6 1 read-write LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBCL Last bit clock pulse 8 1 read-write LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 CPHA Clock phase 9 1 read-write CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 CPOL Clock polarity 10 1 read-write CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CLKEN Clock enable 11 1 read-write CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 STOP stop bits 12 2 read-write STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 LINEN LIN mode enable 14 1 read-write LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 SWAP Swap TX/RX pins 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ABREN Auto baud rate enable 20 1 read-write ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 ABRMOD Auto baud rate mode 21 2 read-write ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 RTOEN Receiver timeout enable 23 1 read-write RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ADD Address of the USART node 24 8 read-write 0 255 CR3 CR3 USART control register 3 0x8 0x20 read-write 0x00000000 0xFFFFFFFF EIE Error interrupt enable 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 IREN IrDA mode enable 1 1 read-write IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 IRLP IrDA low-power 2 1 read-write IRLP Normal Normal mode 0 LowPower Low-power mode 1 HDSEL Half-duplex selection 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 NACK Smartcard NACK enable 4 1 read-write NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 SCEN Smartcard mode enable 5 1 read-write SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 DMAR DMA enable receiver 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 ONEBIT One sample bit method enable 11 1 read-write ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 OVRDIS Overrun Disable 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA Disable on reception Error 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 SCARCNT Smartcard auto-retry count 17 3 read-write 0 7 WUS Wake-up from low-power mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 WUFIE Wake-up from low-power mode interrupt enable 22 1 read-write WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 TXFTIE TXFIFO threshold interrupt enable 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 TCBGTIE Transmission Complete before guard time, interrupt enable 24 1 read-write TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 RXFTCFG Receive FIFO threshold configuration 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 CR3_ALTERNATE1 CR3_ALTERNATE1 USART control register 3 CR3 0x8 0x20 read-write 0x00000000 0xFFFFFFFF EIE Error interrupt enable 0 1 read-write IREN IrDA mode enable 1 1 read-write IRLP IrDA low-power 2 1 read-write HDSEL Half-duplex selection 3 1 read-write NACK Smartcard NACK enable 4 1 read-write SCEN Smartcard mode enable 5 1 read-write DMAR DMA enable receiver 6 1 read-write DMAT DMA enable transmitter 7 1 read-write RTSE RTS enable 8 1 read-write CTSE CTS enable 9 1 read-write CTSIE CTS interrupt enable 10 1 read-write ONEBIT One sample bit method enable 11 1 read-write OVRDIS Overrun Disable 12 1 read-write DDRE DMA Disable on reception Error 13 1 read-write DEM Driver enable mode 14 1 read-write DEP Driver enable polarity selection 15 1 read-write SCARCNT Smartcard auto-retry count 17 3 read-write WUS0 Wake-up from low-power mode interrupt flag selection 20 1 read-write WUS1 Wake-up from low-power mode interrupt flag selection 21 1 read-write WUFIE Wake-up from low-power mode interrupt enable 22 1 read-write TCBGTIE Transmission Complete before guard time, interrupt enable 24 1 read-write BRR BRR USART baud rate register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF BRR USART baud rate 0 16 read-write 0 65535 GTPR GTPR USART guard time and prescaler register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF PSC Prescaler value 0 8 read-write 0 255 GT Guard time value 8 8 read-write 0 255 RTOR RTOR USART receiver timeout register 0x14 0x20 read-write 0x00000000 0xFFFFFFFF RTO Receiver timeout value 0 24 read-write 0 16777215 BLEN Block Length 24 8 read-write 0 255 RQR RQR USART request register 0x18 0x20 write-only 0x00000000 0xFFFFFFFF ABRRQ Auto baud rate request 0 1 write-only ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 SBKRQ Send break request 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR USART interrupt and status register 0x1C 0x20 read-only 0x000000C0 0xF00FFFFF PE Parity error 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Noise detection flag 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 LBDF LIN break detection flag 8 1 read-only LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 CTSIF CTS interrupt flag 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 RTOF Receiver timeout 11 1 read-only RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 EOBF End of block flag 12 1 read-only EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 UDR SPI slave underrun error flag 13 1 read-only UDR NoUnderrun No underrun error 0 Underrun underrun error 1 ABRE Auto baud rate error 14 1 read-only ABRF Auto baud rate flag 15 1 read-only BUSY Busy flag 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wake-up from mute mode 19 1 read-only RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 WUF Wake-up from low-power mode flag 20 1 read-only TEACK Transmit enable acknowledge flag 21 1 read-only REACK Receive enable acknowledge flag 22 1 read-only TXFE TXFIFO Empty 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO Full 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TCBGT Transmission complete before guard time flag 25 1 read-only TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFT RXFIFO threshold flag 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR USART interrupt flag clear register 0x20 0x20 write-only 0x00000000 0xFFFFFFFF PECF Parity error clear flag 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TXFECF TXFIFO empty clear flag 5 1 write-only oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 write-only oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 LBDCF LIN break detection clear flag 8 1 write-only oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 CTSCF CTS clear flag 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 RTOCF Receiver timeout clear flag 11 1 write-only oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 EOBCF End of block clear flag 12 1 write-only oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 UDRCF SPI slave underrun clear flag 13 1 write-only oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 CMCF Character match clear flag 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 WUCF Wake-up from low-power mode clear flag 20 1 write-only oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 RDR RDR USART receive data register 0x24 0x20 read-only 0x00000000 0xFFFFFFFF RDR Receive data value 0 9 read-only 0 511 TDR TDR USART transmit data register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF TDR Transmit data value 0 9 read-write 0 511 PRESC PRESC USART prescaler register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler 0 4 read-write PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 USART1_S 0x50013800 USART2 0x40004400 USART2 USART2 global interrupt 59 USART2_S 0x50004400 USART3 0x40004800 USART3 USART3 global interrupt 60 USART3_S 0x50004800 UART4 0x40004C00 UART4 UART4 global interrupt 61 UART4_S 0x50004C00 UART5 0x40005000 UART5 UART5 global interrupt 62 UART5_S 0x50005000 USART6 0x40006400 USART6 USART6 global interrupt 85 USART6_S 0x50006400 USB USB address block description USB 0x40016000 0x0 0x5C registers USB_FS USB OTG FS global interrupt 74 8 0x4 0-7 CHEP%sR CHEP%sR USB endpoint/channel %s register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF EA endpoint/channel address 0 4 read-write STATTX Status bits, for transmission transfers 4 2 read-write oneToToggle STATTXR read Disabled All transmission requests addressed to this endpoint/channel are ignored. 0 Stall Device mode: the endpoint is stalled and all transmission requests result in a STALL handshake. Host mode: this indicates that the device has STALLed the channel. 1 Nak Device mode: the endpoint is NAKed and all transmission requests result in a NAK handshake. Host mode: this indicates that the device has NAKed the transmission request. 2 Valid This endpoint/channel is enabled for transmission. 3 STATTXW write Keep Do not change bits 0 DTOGTX Data toggle, for transmission transfers 6 1 write-only oneToToggle DTOGTXW Toggle Flip bit 1 VTTX Valid USB transaction transmitted 7 1 read-write zeroToClear VTTXW write Clear Clear flag 0 EPKIND endpoint/channel kind 8 1 read-write UTYPE USB type of transaction 9 2 read-write UTYPE Bulk Bulk endpoint 0 Control Control endpoint 1 Iso Isochronous endpoint 2 Interrupt Interrupt endpoint 3 SETUP Setup transaction completed 11 1 read-only STATRX Status bits, for reception transfers 12 2 read-write oneToToggle STATRXR read Disabled All reception requests addressed to this endpoint/channel are ignored. 0 Stall Device mode: the endpoint is stalled and all reception requests result in a STALL handshake. Host mode: this indicates that the device has STALLed the channel. 1 Nak Device mode: the endpoint is NAKed and all reception requests result in a NAK handshake. Host mode: this indicates that the device has NAKed the reception request. 2 Valid This endpoint/channel is enabled for reception. 3 STATRXW write Keep Do not change bits 0 DTOGRX Data Toggle, for reception transfers 14 1 write-only oneToToggle DTOGRXW Toggle Flip bit 1 VTRX USB valid transaction received 15 1 read-write zeroToClear VTRXW write Clear Clear flag 0 DEVADDR Host mode 16 7 read-write NAK Host mode 23 1 read-write zeroToClear NAKW write Clear Clear flag 0 LS_EP Low speed endpoint host with HUB only 24 1 read-write ERR_TX Received error for an OUT/SETUP transaction 25 1 read-write zeroToClear ERR_TXW write Clear Clear flag 0 ERR_RX Received error for an IN transaction 26 1 read-write zeroToClear ERR_RXW write Clear Clear flag 0 THREE_ERR_TX Three errors for an OUT or SETUP transaction 27 2 read-write THREE_ERR_RX Three errors for an IN transaction 29 2 read-write CNTR CNTR USB control register 0x40 0x20 read-write 0x00000003 0xFFFFFFFF USBRST USB Reset 0 1 read-write USBRST NoEffect No effect 0 Reset USB core is under reset / USB reset driven 1 PDWN Power down 1 1 read-write SUSPRDY Suspend state effective 2 1 read-only SUSPEN Suspend state enable 3 1 read-write SUSPEN NoEffect No effect 0 Suspend Enter L1/L2 suspend 1 L2RES L2 remote wake-up / resume driver 4 1 read-write L1RES L1 remote wake-up / resume driver 5 1 read-write L1RES NoEffect No effect 0 WakeupResume Send 50us remote-wakeup signaling to host / Send L1 resume signaling to device 1 L1REQM LPM L1 state request interrupt mask 7 1 read-write ESOFM Expected start of frame interrupt mask 8 1 read-write SOFM Start of frame interrupt mask 9 1 read-write RST_DCONM USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask 10 1 read-write SUSPM Suspend mode interrupt mask 11 1 read-write WKUPM Wake-up interrupt mask 12 1 read-write ERRM Error interrupt mask 13 1 read-write PMAOVRM Packet memory area over / underrun interrupt mask 14 1 read-write CTRM Correct transfer interrupt mask 15 1 read-write THR512M 512 byte threshold interrupt mask 16 1 read-write DDISCM Device disconnection mask 17 1 read-write HOST HOST mode 31 1 read-write ISTR ISTR USB interrupt status register 0x44 0x20 read-write 0x00000000 0xFFFFFFFF IDN Device Endpoint / host channel identification number 0 4 read-only DIR Direction of transaction 4 1 read-only DIR To Data transmitted by the USB peripheral to the host PC 0 From Data received by the USB peripheral from the host PC 1 L1REQ LPM L1 state request 7 1 read-write zeroToClear L1REQR read NotL1State NotL1State 0 L1State LPM command to enter the L1 state is successfully received and acknowledged 1 L1REQW write Clear Clear flag 0 ESOF Expected start of frame 8 1 read-write zeroToClear ESOFR read NotExpectedStartOfFrame NotExpectedStartOfFrame 0 ExpectedStartOfFrame An SOF packet is expected but not received 1 ESOFW write Clear Clear flag 0 SOF Start of frame 9 1 read-write zeroToClear SOFR read NotStartOfFrame NotStartOfFrame 0 StartOfFrame Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus 1 SOFW write Clear Clear flag 0 RST_DCON USB reset request (Device mode) or device connect/disconnect (Host mode) 10 1 read-write zeroToClear RST_DCONR read NotReset NotReset 0 Reset Peripheral detects an active USB RESET signal at its inputs 1 RST_DCONW write Clear Clear flag 0 SUSP Suspend mode request 11 1 read-write zeroToClear SUSPR read NotSuspend NotSuspend 0 Suspend No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus 1 SUSPW write Clear Clear flag 0 WKUP Wake-up 12 1 read-write zeroToClear WKUPR read NotWakeup NotWakeup 0 Wakeup Activity is detected that wakes up the USB peripheral 1 WKUPW write Clear Clear flag 0 ERR Error 13 1 read-write zeroToClear ERRR read NotError Errors are not occurred 0 Error One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred 1 ERRW write Clear Clear flag 0 PMAOVR Packet memory area over / underrun 14 1 read-write zeroToClear PMAOVRR read NotOverrun Overrun is not occurred 0 Overrun Microcontroller has not been able to respond in time to an USB memory request 1 PMAOVRW write Clear Clear flag 0 CTR Completed transfer in host mode 15 1 read-only CTR Completed Endpoint has successfully completed a transaction 1 THR512 512 byte threshold interrupt 16 1 read-write zeroToClear THR512R read NotReached 512 bytes threshold not reached 0 Reached 512 bytes have been transmitted or received during isochronous transfers 1 THR512W write Clear Clear flag 0 DDISC Device connection 17 1 read-write DCON_STAT Device connection status 29 1 read-only LS_DCON Low speed device connected 30 1 read-only FNR FNR USB frame number register 0x48 0x20 read-only 0x00000000 0xFFFFF000 FN Frame number 0 11 read-only LSOF Lost SOF 11 2 read-only LCK Locked 13 1 read-only RXDM Receive data - line status 14 1 read-only RXDP Receive data + line status 15 1 read-only DADDR DADDR USB Device address 0x4C 0x20 read-write 0x00000000 0xFFFFFFFF ADD Device address 0 7 read-write EF Enable function 7 1 read-write LPMCSR LPMCSR LPM control and status register 0x54 0x20 read-write 0x00000000 0xFFFFFFFF LPMEN LPM support enable 0 1 read-write LPMACK LPM token acknowledge enable 1 1 read-write LPMACK Nyet The valid LPM Token will be NYET / NYET answer 0 Ack The valid LPM Token will be ACK / ACK answer 1 REMWAKE bRemoteWake value 3 1 read-only BESL BESL value 4 4 read-only BCDR BCDR Battery charging detector 0x58 0x20 read-write 0x00000000 0xFFFFFFFF BCDEN Battery charging detector (BCD) enable 0 1 read-write DCDEN Data contact detection (DCD) mode enable 1 1 read-write PDEN Primary detection (PD) mode enable 2 1 read-write SDEN Secondary detection (SD) mode enable 3 1 read-write DCDET Data contact detection (DCD) status 4 1 read-only PDET Primary detection (PD) status 5 1 read-only SDET Secondary detection (SD) status 6 1 read-only PS2DET DM pull-up detection status 7 1 read-only DPPU_DPD DP pull-up / DPDM pull-down 15 1 read-write USB_S 0x50016000 USBSRAM USBSRAM address block description USBSRAM 0x40016400 0x0 0x40 registers TXRXBD_0 TXRXBD_0 Channel/endpoint transmit buffer descriptor 0 0x0 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_0_ALTERNATE1 TXRXBD_0_ALTERNATE1 Channel/endpoint receive buffer descriptor 0 TXRXBD_0 0x0 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_0 RXTXBD_0 Channel/endpoint receive buffer descriptor 0 0x4 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_0_ALTERNATE1 RXTXBD_0_ALTERNATE1 Channel/endpoint transmit buffer descriptor 0 RXTXBD_0 0x4 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_1 TXRXBD_1 Channel/endpoint transmit buffer descriptor 1 0x8 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_1_ALTERNATE1 TXRXBD_1_ALTERNATE1 Channel/endpoint receive buffer descriptor 1 TXRXBD_1 0x8 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_1 RXTXBD_1 Channel/endpoint receive buffer descriptor 1 0xC 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_1_ALTERNATE1 RXTXBD_1_ALTERNATE1 Channel/endpoint transmit buffer descriptor 1 RXTXBD_1 0xC 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_2 TXRXBD_2 Channel/endpoint transmit buffer descriptor 2 0x10 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_2_ALTERNATE1 TXRXBD_2_ALTERNATE1 Channel/endpoint receive buffer descriptor 2 TXRXBD_2 0x10 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_2 RXTXBD_2 Channel/endpoint receive buffer descriptor 2 0x14 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_2_ALTERNATE1 RXTXBD_2_ALTERNATE1 Channel/endpoint transmit buffer descriptor 2 RXTXBD_2 0x14 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_3 TXRXBD_3 Channel/endpoint transmit buffer descriptor 3 0x18 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_3_ALTERNATE1 TXRXBD_3_ALTERNATE1 Channel/endpoint receive buffer descriptor 3 TXRXBD_3 0x18 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_3 RXTXBD_3 Channel/endpoint receive buffer descriptor 3 0x1C 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_3_ALTERNATE1 RXTXBD_3_ALTERNATE1 Channel/endpoint transmit buffer descriptor 3 RXTXBD_3 0x1C 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_4 TXRXBD_4 Channel/endpoint transmit buffer descriptor 4 0x20 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_4_ALTERNATE1 TXRXBD_4_ALTERNATE1 Channel/endpoint receive buffer descriptor 4 TXRXBD_4 0x20 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_4 RXTXBD_4 Channel/endpoint receive buffer descriptor 4 0x24 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_4_ALTERNATE1 RXTXBD_4_ALTERNATE1 Channel/endpoint transmit buffer descriptor 4 RXTXBD_4 0x24 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_5 TXRXBD_5 Channel/endpoint transmit buffer descriptor 5 0x28 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_5_ALTERNATE1 TXRXBD_5_ALTERNATE1 Channel/endpoint receive buffer descriptor 5 TXRXBD_5 0x28 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_5 RXTXBD_5 Channel/endpoint receive buffer descriptor 5 0x2C 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_5_ALTERNATE1 RXTXBD_5_ALTERNATE1 Channel/endpoint transmit buffer descriptor 5 RXTXBD_5 0x2C 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_6 TXRXBD_6 Channel/endpoint transmit buffer descriptor 6 0x30 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_6_ALTERNATE1 TXRXBD_6_ALTERNATE1 Channel/endpoint receive buffer descriptor 6 TXRXBD_6 0x30 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_6 RXTXBD_6 Channel/endpoint receive buffer descriptor 6 0x34 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_6_ALTERNATE1 RXTXBD_6_ALTERNATE1 Channel/endpoint transmit buffer descriptor 6 RXTXBD_6 0x34 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_7 TXRXBD_7 Channel/endpoint transmit buffer descriptor 7 0x38 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write TXRXBD_7_ALTERNATE1 TXRXBD_7_ALTERNATE1 Channel/endpoint receive buffer descriptor 7 TXRXBD_7 0x38 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_7 RXTXBD_7 Channel/endpoint receive buffer descriptor 7 0x3C 0x20 read-write 0x00000000 0x00000000 ADDR_RX Reception buffer address 0 16 read-write COUNT_RX Reception byte count 16 10 read-only NUM_BLOCK Number of blocks 26 5 read-write BLSIZE Block size 31 1 read-write RXTXBD_7_ALTERNATE1 RXTXBD_7_ALTERNATE1 Channel/endpoint transmit buffer descriptor 7 RXTXBD_7 0x3C 0x20 read-write 0x00000000 0x00000000 ADDR_TX Transmission buffer address 0 16 read-write COUNT_TX Transmission byte count 16 10 read-write USBSRAM_S 0x50016400 VREFBUF VREFBUF address block description VREFBUF 0x44007400 0x0 0x8 registers CSR CSR VREFBUF control and status register 0x0 0x20 read-write 0x00000002 0xFFFFFFFF ENVR Voltage reference buffer mode enable 0 1 read-write HIZ High impedance mode 1 1 read-write VRR Voltage reference buffer ready 3 1 read-only VRS Voltage reference scale 4 3 read-write CCR CCR VREFBUF calibration control register 0x4 0x20 read-write 0x00000000 0xFFFFFF00 TRIM Trimming code 0 6 read-write VREFBUF_S 0x54007400 WWDG WWDG address block description WWDG 0x40002C00 0x0 0xC registers WWDG Window Watchdog interrupt 0 CR CR WWDG control register 0x0 0x10 read-write 0x0000007F 0x0000FFFF T 7-bit counter (MSB to LSB) 0 7 read-write 0 127 WDGA Activation bit 7 1 read-write WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 CFR CFR WWDG configuration register 0x4 0x10 read-write 0x0000007F 0x0000FFFF W 7-bit window value 0 7 read-write 0 127 EWI Early wake-up interrupt enable 9 1 read-write EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 Div16 Counter clock (PCLK1 div 4096) div 16 4 Div32 Counter clock (PCLK1 div 4096) div 32 5 Div64 Counter clock (PCLK1 div 4096) div 64 6 Div128 Counter clock (PCLK1 div 4096) div 128 7 SR SR WWDG status register 0x8 0x10 read-write 0x00000000 0x0000FFFF EWIF Early wake-up interrupt flag 0 1 read-write zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 WWDG_S 0x50002C00

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