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Showing content from https://stm32-rs.github.io/stm32-rs/stm32h503.svd.patched below:

STM32H503 1.5 STM32H503 CM33 r0p0 little true true 4 false 8 32 0x20 0x00000000 0xFFFFFFFF ADC1 Analog to digital converter ADC 0x42028000 0x0 0x400 registers ADC1 ADC1 global interrupt 37 ISR ISR ADC interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF ADRDY ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0 1 read-write oneToClear ADRDYR read NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 ADRDYW write Clear Clear ADC is ready to start conversion flag 1 EOSMP End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase. 1 1 read-write oneToClear EOSMPR read NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOSMPW write Clear Clear end of sampling phase reached flag 1 EOC End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register 2 1 read-write oneToClear EOCR read NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOCW write Clear Clear regular conversion complete flag 1 EOS End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it. 3 1 read-write oneToClear EOSR read NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 EOSW write Clear Clear regular sequence complete flag 1 OVR ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it. 4 1 read-write oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear overrun occurred flag 1 JEOC Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register 5 1 read-write oneToClear JEOCR read NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOCW write Clear Clear injected conversion complete flag 1 JEOS Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it. 6 1 read-write oneToClear JEOSR read NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 JEOSW write Clear Clear Injected sequence complete flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 read-write oneToClear AWD1R read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD1W write Clear Clear analog watchdog event occurred flag 1 JQOVF Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information. 10 1 read-write oneToClear JQOVFR read NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 JQOVFW write Clear Clear injected context queue overflow flag 1 IER IER ADC interrupt enable register 0x4 0x20 0x00000000 0xFFFFFFFF ADRDYIE ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 1 read-write ADRDYIE Disabled ADC ready interrupt disabled 0 Enabled ADC ready interrupt enabled 1 EOSMPIE End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 1 1 read-write EOSMPIE Disabled End of regular conversion sampling phase interrupt disabled 0 Enabled End of regular conversion sampling phase interrupt enabled 1 EOCIE End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 2 1 read-write EOCIE Disabled End of regular conversion interrupt disabled 0 Enabled End of regular conversion interrupt enabled 1 EOSIE End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 3 1 read-write EOSIE Disabled End of regular sequence interrupt disabled 0 Enabled End of regular sequence interrupt enabled 1 OVRIE Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 4 1 read-write OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled 1 JEOCIE End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 5 1 read-write JEOCIE Disabled End of injected conversion interrupt disabled 0 Enabled End of injected conversion interrupt enabled 1 JEOSIE End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 6 1 read-write JEOSIE Disabled End of injected sequence interrupt disabled 0 Enabled End of injected sequence interrupt enabled 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 read-write AWD1IE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 JQOVFIE Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 10 1 read-write JQOVFIE Disabled Injected context queue overflow interrupt disabled 0 Enabled Injected context queue overflow interrupt enabled 1 CR CR ADC control register 0x8 0x20 0x20000000 0xFFFFFFFF ADEN ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator) 0 1 read-write oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 ADDIS ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 1 1 read-write oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADSTART ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion immediately starts (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) 2 1 read-write oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 JADSTART ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion immediately starts (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) 3 1 read-write oneToSet read write ADSTP ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). 4 1 read-write oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 JADSTP ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP) 5 1 read-write oneToSet read write ADVREGEN ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 28 1 read-write ADVREGEN Disabled ADC Voltage regulator disabled 0 Enabled ADC Voltage regulator enabled 1 DEEPPWD Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 29 1 read-write DEEPPWD NotDeepPowerDown ADC not in Deep-power down 0 DeepPowerDown ADC in Deep-power-down (default reset state) 1 ADCALDIF Differential mode for calibration This bit is set and cleared by software to configure the Single-ended or Differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 30 1 read-write ADCALDIF SingleEnded Calibration for single-ended mode 0 Differential Calibration for differential mode 1 ADCAL ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for Single-ended or Differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing) 31 1 read-write oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 CFGR CFGR ADC configuration register 0xC 0x20 0x80000000 0xFFFFFFFF DMAEN Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to conversions using the DMA. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 1 read-write DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 DMACFG Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 1 1 read-write DMACFG OneShot DMA One Shot mode selected 0 Circular DMA Circular mode selected 1 RES Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 3 2 read-write RES Bits12 12-bit 0 Bits10 10-bit 1 Bits8 8-bit 2 Bits6 6-bit 3 EXTSEL External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 5 5 EXTSEL TIM1_CC1 Timer 1 CC1 event 0 TIM1_CC2 Timer 1 CC2 event 1 TIM1_CC3 Timer 1 CC3 event 2 TIM2_CC2 Timer 2 CC2 event 3 TIM3_TRGO Timer 3 TRGO event 4 EXTI11 EXTI line 11 6 TIM1_TRGO Timer 1 TRGO event 9 TIM1_TRGO2 Timer 1 TRGO2 event 10 TIM2_TRGO Timer 2 TRGO event 11 TIM6_TRGO Timer 6 TRGO event 13 TIM15_TRGO Timer 15 TRGO event 14 TIM3_CC4 Timer 3 CC4 event 15 EXTEN External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 10 2 read-write EXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 OVRMOD Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 12 1 read-write OVRMOD Preserve Preserve DR register when an overrun is detected 0 Overwrite Overwrite DR register when an overrun is detected 1 CONT Single / Continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 13 1 read-write CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 AUTDLY Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 14 1 read-write AUTDLY Off Auto delayed conversion mode off 0 On Auto delayed conversion mode on 1 ALIGN Data alignment This bit is set and cleared by software to select right or left alignment. Refer to register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 15 1 read-write ALIGN Right Right alignment 0 Left Left alignment 1 DISCEN Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 16 1 read-write DISCEN Disabled Discontinuous mode on regular channels disabled 0 Enabled Discontinuous mode on regular channels enabled 1 DISCNUM Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in Discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 17 3 read-write 0 7 JDISCEN Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable Discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. 20 1 read-write JDISCEN Disabled Discontinuous mode on injected channels disabled 0 Enabled Discontinuous mode on injected channels enabled 1 JQM JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to for more information. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 21 1 read-write JQM Mode0 JSQR Mode 0: Queue maintains the last written configuration into JSQR 0 Mode1 JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence 1 AWD1SGL Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 22 1 read-write AWD1SGL All Analog watchdog 1 enabled on all channels 0 Single Analog watchdog 1 enabled on single channel selected in AWD1CH 1 AWD1EN Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 23 1 read-write AWD1EN Disabled Analog watchdog 1 disabled on regular channels 0 Enabled Analog watchdog 1 enabled on regular channels 1 JAWD1EN Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 24 1 read-write JAWD1EN Disabled Analog watchdog 1 disabled on injected channels 0 Enabled Analog watchdog 1 enabled on injected channels 1 JAUTO Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). 25 1 read-write JAUTO Disabled Automatic injected group conversion disabled 0 Enabled Automatic injected group conversion enabled 1 AWD1CH Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: reserved, must not be used Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 26 5 read-write 0 19 JQDIS Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared. 31 1 read-write CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 0x00000000 0xFFFFFFFF ROVSE Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 0 1 read-write ROVSE Disabled Regular Oversampling disabled 0 Enabled Regular Oversampling enabled 1 JOVSE Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 1 1 read-write JOVSE Disabled Injected Oversampling disabled 0 Enabled Injected Oversampling enabled 1 OVSR Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). 2 3 read-write OVSR Ratio2 2x 0 Ratio4 4x 1 Ratio8 8x 2 Ratio16 16x 3 Ratio32 32x 4 Ratio64 64x 5 Ratio128 128x 6 Ratio256 256x 7 OVSS Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). 5 4 read-write OVSS NoShift No Shift 0 Shift1Bit Shift 1-bit 1 Shift2Bit Shift 2-bit 2 Shift3Bit Shift 3-bit 3 Shift4Bit Shift 4-bit 4 Shift5Bit Shift 5-bit 5 Shift6Bit Shift 6-bit 6 Shift7Bit Shift 7-bit 7 Shift8Bit Shift 8-bit 8 TROVS Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 9 1 read-write TROVS All All oversampled conversions for a channel are done consecutively following a trigger 0 Single Each oversampled conversion for a channel needs a new trigger 1 ROVSM Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 10 1 read-write ROVSM ContinuedMode When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 0 ResumedMode When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) 1 SWTRIG Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 25 1 read-write SWTRIG Conversion Software trigger starts the conversion for sampling time control trigger mode 0 Sampling Software trigger starts the sampling for sampling time control trigger mode 1 BULB Bulb sampling mode This bit is set and cleared by software to enable the bulb sampling mode. SAMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 26 1 read-write BULB Disabled Bulb sampling mode disabled 0 Enabled Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion 1 SMPTRIG Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 27 1 read-write SMPTRIG Disabled Sampling time control trigger mode disabled 0 Enabled Sampling time control trigger mode enabled 1 SMPR1 SMPR1 ADC sample time register 1 0x14 0x20 0x00000000 0xFFFFFFFF 10 0x3 0-9 SMP%s Channel %s sample time selection 0 3 read-write SMP0 Cycles2_5 2.5 ADC clock cycles 0 Cycles6_5 6.5 ADC clock cycles 1 Cycles12_5 12.5 ADC clock cycles 2 Cycles24_5 24.5 ADC clock cycles 3 Cycles47_5 47.5 ADC clock cycles 4 Cycles92_5 92.5 ADC clock cycles 5 Cycles247_5 247.5 ADC clock cycles 6 Cycles640_5 640.5 ADC clock cycles 7 SMPPLUS Addition of one clock cycle to the sampling time. To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0. 31 1 read-write SMPPLUS KeepCycles The sampling time remains set to 2.5 ADC clock cycles remains 0 Add1Cycle 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers 1 SMPR2 SMPR2 ADC sample time register 2 0x18 0x20 0x00000000 0xFFFFFFFF 10 0x3 10-19 SMP%s Channel %s sample time selection 0 3 read-write TR1 TR1 ADC watchdog threshold register 1 0x20 0x20 0x0FFF0000 0xFFFFFFFF LT1 Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 12 read-write 0 4095 AWDFILT Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 12 3 read-write HT1 Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 16 12 read-write 0 4095 TR2 TR2 ADC watchdog threshold register 2 0x24 0x20 0x00FF0000 0xFFFFFFFF LT2 Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 8 read-write 0 255 HT2 Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 16 8 read-write 0 255 TR3 TR3 ADC watchdog threshold register 3 0x28 0x20 0x00FF0000 0xFFFFFFFF LT3 Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 8 read-write 0 255 HT3 Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 16 8 read-write 0 255 SQR1 SQR1 ADC regular sequence register 1 0x30 0x20 0x00000000 0xFFFFFFFF L Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 0 4 read-write 0 15 4 0x6 1-4 SQ%s %s conversion in regular sequence 6 5 read-write 0 19 SQR2 SQR2 ADC regular sequence register 2 0x34 0x20 0x00000000 0xFFFFFFFF 5 0x6 5-9 SQ%s %s conversion in regular sequence 0 5 read-write SQR3 SQR3 ADC regular sequence register 3 0x38 0x20 0x00000000 0xFFFFFFFF 5 0x6 10-14 SQ%s %s conversion in regular sequence 0 5 read-write SQR4 SQR4 ADC regular sequence register 4 0x3C 0x20 0x00000000 0xFFFFFFFF 2 0x6 15-16 SQ%s %s conversion in regular sequence 0 5 read-write DR DR ADC regular data register 0x40 0x20 0x00000000 0xFFFFFFFF RDATA Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in . 0 16 read-only 0 65535 JSQR JSQR ADC injected sequence register 0x4C 0x20 0x00000000 0xFFFFFFFF JL Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 0 2 read-write 0 3 JEXTSEL External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 2 5 read-write JEXTSEL TIM1_TRGO Timer 1 TRGO event 0 TIM1_CC4 Timer 1 CC4 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM2_CC1 Timer 2 CC1 event 3 TIM3_CC4 Timer 3 CC4 event 4 EXTI15 EXTI line 15 6 TIM1_TRGO2 Timer 1 TRGO2 event 8 TIM3_CC3 Timer 3 CC3 event 11 TIM3_TRGO Timer 3 TRGO event 12 TIM3_CC1 Timer 3 CC1 event 13 TIM6_TRGO Timer 6 TRGO event 14 TIM15_TRGO Timer 15 TRGO event 15 JEXTEN External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). If JQM = 1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions) 7 2 read-write JEXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 4 0x6 1-4 JSQ%s %s conversion in injected sequence 9 5 read-write 0 19 4 0x4 1-4 OFR%s OFR%s ADC offset %s register 0x60 0x20 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. 0 12 read-write 0 4095 OFFSETPOS Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 24 1 read-write SATEN Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 25 1 read-write OFFSET_CH Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. 26 5 read-write 0 31 OFFSET_EN Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 31 1 read-write OFFSET_EN Disabled This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0] 0 Enabled This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0] 1 4 0x4 1-4 JDR%s JDR%s ADC injected channel %s data register 0x80 0x20 0x00000000 0xFFFFFFFF JDATA Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in . 0 16 read-only 0 65535 AWD2CR AWD2CR ADC Analog Watchdog 2 Configuration Register 0xA0 0x20 0x00000000 0xFFFFFFFF 20 0x1 0-19 AWD2CH%s Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog. 0 1 AWD2CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 AWD3CR AWD3CR ADC Analog Watchdog 3 Configuration Register 0xA4 0x20 0x00000000 0xFFFFFFFF 20 0x1 0-19 AWD3CH%s Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[19:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog. 0 1 AWD3CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 DIFSEL DIFSEL ADC Differential mode Selection Register 0xB0 0x20 0x00000000 0xFFFFFFFF 20 0x1 0-19 DIFSEL%s Differential mode for channel %s 0 1 DIFSEL0 SingleEnded Input channel is configured in single-ended mode 0 Differential Input channel is configured in differential mode 1 CALFACT CALFACT ADC Calibration Factors 0xB4 0x20 0x00000000 0xFFFFFFFF CALFACT_S Calibration Factors In Single-ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). 0 7 read-write 0 127 CALFACT_D Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new differential calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). 16 7 read-write 0 127 OR OR ADC option register 0xC8 0x20 0x00000000 0xFFFFFFFF OP0 Option bit 0 0 1 read-write OP1 Option bit 1 1 1 read-write CCR CCR ADC common control register 0x308 0x20 0x00000000 0xFFFFFFFF CKMODE ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 16 2 read-write PRESC ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00. 18 4 read-write VREFEN VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel. 22 1 read-write TSEN VSENSE enable This bit is set and cleared by software to control VSENSE. 23 1 read-write VBATEN VBAT enable This bit is set and cleared by software to control. 24 1 read-write HWCFGR0 HWCFGR0 ADC hardware configuration register 0x3F0 0x20 0x00001211 0xFFFFFFFF ADCNUM Number of ADCs implemented 0 4 read-only MULPIPE Number of pipeline stages 4 4 read-only OPBITS Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8 8 4 read-only IDLEVALUE Idle value for non-selected channels 12 4 read-only VERR VERR ADC version register 0x3F4 0x20 0x00000012 0xFFFFFFFF MINREV Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2 0 4 read-only MAJREV Major revision These bits returns the ADC IP major revision 4 4 read-only IPDR IPDR ADC identification register 0x3F8 0x20 0x00110006 0xFFFFFFFF ID Peripheral identifier These bits returns the ADC identifier. ID[31:0] = 0x0011 0006: c7amba_aditf5_90_v1 0 32 read-only SIDR SIDR ADC size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size Identification SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address: 0 32 read-only COMP Comparator COMP 0x40004000 0x0 0x400 registers COMP COMP global interrupt 133 COMP_SR COMP_SR Comparator status register 0x0 0x20 0x00000000 0xFFFFFFFF C1VAL COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect. 0 1 read-only C1IF COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register. 16 1 read-only COMP_ICFR COMP_ICFR Comparator interrupt clear flag register 0x4 0x20 0x00000000 0xFFFFFFFF CC1IF Clear COMP Channel1 interrupt flag Writing 1 clears the C1IF flag in the COMP_SR register. 16 1 read-write COMP_CFGR1 COMP_CFGR1 Comparator configuration register 1 0xC 0x20 0x00000000 0xFFFFFFFF EN COMP Channel1 enable This bit is set and cleared by software (only if LOCK not set). It enables the COMP Channel1. 0 1 read-write BRGEN Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level V REF_COMP (similar to V REFINT ). If SCALEN and BRGEN are set, the four scaler outputs provide V REF_COMP , 3/4 V REF_COMP , 1/2 V REF_COMP and 1/4 V REF_COMP levels, respectively. 1 1 read-write SCALEN Voltage scaler enable This bit is set and cleared by software (only if LOCK not set). This bit enables the V REFINT scaler for the COMP channels. 2 1 read-write POLARITY COMP channel1 polarity selection This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel1 polarity. 3 1 read-write ITEN COMP channel1 interrupt enable This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel1. 6 1 read-write HYST COMP channel1 hysteresis selection These bits are set and cleared by software (only if LOCK not set). They select the hysteresis voltage of the COMP channel1. 8 2 read-write PWRMODE Power mode of the COMP channel1 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel1. 12 2 read-write INMSEL COMP channel1 inverting input selection These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of the COMP channel. Note: See Table 146: COMP1 inverting input assignment for more details. 16 4 read-write INPSEL1 COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. Note: See Table 145: COMP1 noninverting input assignment for more details. 20 1 read-write INPSEL2 COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of the COMP channel. See Table 145: COMP1 noninverting input assignment for more details. 22 1 read-write BLANKING COMP Channel1 blanking source selection Bits of this field are set and cleared by software (only if LOCK not set). The field selects the input source for COMP Channel1 output blanking: All other values: reserved 24 4 read-write LOCK Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR1[31:0] 31 1 read-write COMP_CFGR2 COMP_CFGR2 Comparator configuration register 2 0x10 0x20 0x00000000 0xFFFFFFFF INPSEL0 COMP non-inverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. See Table 145: COMP1 noninverting input assignment for more details. 4 1 read-write LOCK Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR2[31:0] 31 1 read-write CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR CRC data register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF DR Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. 0 32 read-write 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR CRC independent data register 0x4 0x20 0x00000000 0xFFFFFFFF IDR General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register 0 32 read-write 0 4294967295 CR CR CRC control register 0x8 0x20 0x00000000 0xFFFFFFFF RESET RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 0 1 read-write RESETW write Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 POLYSIZE Polynomial size These bits control the size of the polynomial. 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 REV_IN Reverse input data These bits control the reversal of the bit order of the input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 REV_OUT Reverse output data This bit controls the reversal of the bit order of the output data. 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 INIT INIT CRC initial value 0x10 0x20 0xFFFFFFFF 0xFFFFFFFF INIT Programmable initial CRC value This register is used to write the CRC initial value. 0 32 read-write 0 4294967295 POL POL CRC polynomial 0x14 0x20 0x04C11DB7 0xFFFFFFFF POL Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. 0 32 read-write 0 4294967295 CRS Clock recovery system CRS 0x40006000 0x0 0x400 registers CRS Clock Recovery System global interrupt 75 CR CR CRS control register 0x0 0x20 0x00002000 0xFFFFFFFF SYNCOKIE SYNC event OK interrupt enable 0 1 read-write SYNCOKIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 SYNCWARNIE SYNC warning interrupt enable 1 1 read-write ERRIE Synchronization or trimming error interrupt enable 2 1 read-write ESYNCIE Expected SYNC interrupt enable 3 1 read-write CEN Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. 5 1 read-write CEN Disabled Frequency error counter disabled 0 Enabled Frequency error counter enabled 1 AUTOTRIMEN Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section 10.5.3 for more details. 6 1 read-write AUTOTRIMEN Disabled Automatic trimming disabled 0 Enabled Automatic trimming enabled 1 SWSYNC Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. 7 1 read-write SWSYNC Sync A software sync is generated 1 TRIM HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48 oscillator. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is specified in the product datasheet. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. 8 6 read-write 0 63 CFGR CFGR CRS configuration register 0x4 0x20 0x2022BB7F 0xFFFFFFFF RELOAD Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section 10.5.2 for more details about counter behavior. 0 16 read-write 0 65535 FELIM Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 10.5.3 for more details about FECAP evaluation. 16 8 read-write 0 255 SYNCDIV SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 24 3 read-write SYNCDIV Div1 SYNC not divided 0 Div2 SYNC divided by 2 1 Div4 SYNC divided by 4 2 Div8 SYNC divided by 8 3 Div16 SYNC divided by 16 4 Div32 SYNC divided by 32 5 Div64 SYNC divided by 64 6 Div128 SYNC divided by 128 7 SYNCSRC SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source (see Table 68: CRS internal input/output signals for STM32U575/585): Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF is not generated by the host. No SYNC signal is therefore provided to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs must be used as SYNC signal. 28 2 read-write SYNCSRC GPIO_AF GPIO AF (crs_sync_in_1) selected as SYNC signal source 0 LSE LSE (crs_sync_in_2) selected as SYNC signal source 1 USB_SOF USB SOF (crs_sync_in_3) selected as SYNC signal source 2 SYNCPOL SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. 31 1 read-write SYNCPOL RisingEdge SYNC active on rising edge 0 FallingEdge SYNC active on falling edge 1 ISR ISR CRS interrupt and status register 0x8 0x20 0x00000000 0xFFFFFFFF SYNCOKF SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. 0 1 read-only SYNCOKF NotSignaled Signal not set 0 Signaled Signal set 1 SYNCWARNF SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. 1 1 read-only ERRF Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. 2 1 read-only ESYNCF Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. 3 1 read-only SYNCERR SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action has to be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 8 1 read-only SYNCMISS SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action has to be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 9 1 read-only TRIMOVF Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 10 1 read-only FEDIR Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. 15 1 read-only FEDIR UpCounting Error in up-counting direction 0 DownCounting Error in down-counting direction 1 FECAP Frequency error capture FECAP is the frequency error counter value latched in the time of the last SYNC event. Refer to Section 10.5.3 for more details about FECAP usage. 16 16 read-only 0 65535 ICR ICR CRS interrupt flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF SYNCOKC SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. 0 1 read-write SYNCOKC Clear Clear flag 1 SYNCWARNC SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. 1 1 read-write ERRC Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. 2 1 read-write ESYNCC Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. 3 1 read-write DAC Digital to analog converter DAC 0x42028400 0x0 0x400 registers DAC1 DAC1 global interrupt 38 CR CR DAC control register 0x0 0x20 0x00000000 0xFFFFFFFF 2 0x10 1-2 EN%s DAC channel%s enable 0 1 read-write EN1 Disabled DAC Channel X disabled 0 Enabled DAC Channel X enabled 1 2 0x10 1-2 TEN%s DAC channel%s trigger enable 1 1 read-write TEN1 Disabled DAC Channel X trigger disabled 0 Enabled DAC Channel X trigger enabled 1 TSEL1 DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 2 4 read-write TSEL1 Software Software trigger 0 Tim1Trgo Timer 1 TRGO event 1 Tim2Trgo Timer 2 TRGO event 2 Tim3Trgo Timer 4 TRGO event 3 Tim6Trgo Timer 6 TRGO event 5 Tim7Trgo Timer 7 TRGO event 6 Tim8Trgo Timer 8 TRGO event 7 Lptim1Ch1 LPTIM1 CH1 event 11 Lptim2Ch1 LPTIM2 CH1 event 12 Exti9 EXTI line 9 13 2 0x10 1-2 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 read-write WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true 2 0x10 1-2 MAMP%s DAC channel%s mask/amplitude selector 8 4 read-write MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 2 0x10 1-2 DMAEN%s DAC channel%s DMA enable 12 1 read-write DMAEN1 Disabled DAC Channel X DMA mode disabled 0 Enabled DAC Channel X DMA mode enabled 1 2 0x10 1-2 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 read-write DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 2 0x10 1-2 CEN%s DAC channel%s calibration enable 14 1 read-write CEN1 Normal DAC Channel X Normal operating mode 0 Calibration DAC Channel X calibration mode 1 TSEL2 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). These bits are available only on dual-channel DACs. Refer to implementation. 18 4 read-write SWTRGR SWTRGR DAC software trigger register 0x4 0x20 0x00000000 0xFFFFFFFF 2 0x1 1-2 SWTRIG%s DAC channel%s software trigger 0 1 write-only SWTRIG1 NoTrigger No trigger 0 Trigger Trigger 1 2 0xC 1-2 DHR12R%s DHR12R%s channel%s 12-bit right-aligned data holding register 0x8 0x20 0x00000000 0xFFFFFFFF DACCDHR DAC channel1 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel1. 0 12 read-write 0 4095 DACC1DHRB DAC channel1 12-bit right-aligned data B These bits are written by software. They specify 12-bit data for DAC channel1 when the DAC operates in Double data mode. 16 12 read-write 0 4095 2 0xC 1-2 DHR12L%s DHR12L%s channel%s 12-bit left aligned data holding register 0xC 0x20 0x00000000 0xFFFFFFFF DACCDHR DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1. 4 12 read-write 0 4095 DACC1DHRB DAC channel1 12-bit left-aligned data B These bits are written by software. They specify 12-bit data for DAC channel1 when the DAC operates in Double data mode. 20 12 read-write 0 4095 2 0xC 1-2 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 0x00000000 0xFFFFFFFF DACCDHR DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1. 0 8 read-write 0 255 DACC1DHRB DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1 when the DAC operates in Double data mode. 8 8 read-write 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 0x00000000 0xFFFFFFFF 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 read-write 0 4095 DHR12LD DHR12LD Dual DAC 12-bit left aligned data holding register 0x24 0x20 0x00000000 0xFFFFFFFF 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 read-write 0 4095 DHR8RD DHR8RD Dual DAC 8-bit right aligned data holding register 0x28 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 read-write 0 255 2 0x4 1-2 DOR%s DOR%s channel%s data output register 0x2C 0x20 0x00000000 0xFFFFFFFF DACCDOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 read-only 0 4095 DACC1DORB DAC channel1 data output These bits are read-only. They contain data output for DAC channel1 B. 16 12 read-only 0 4095 SR SR DAC status register 0x34 0x20 0x00000000 0xFFFFFFFF 2 0x10 1-2 DAC%sRDY DAC channel%s ready status bit 11 1 read-only DAC1RDY NotReady DAC channelX is not yet ready to accept the trigger nor output data 0 Ready DAC channelX is ready to accept the trigger or output data 1 2 0x10 1-2 DORSTAT%s DAC channel%s output register status bit 12 1 read-only DORSTAT1 Dor DOR[11:0] is used actual DAC output 0 Dorb DORB[11:0] is used actual DAC output 1 2 0x10 1-2 DMAUDR%s DAC channel%s DMA underrun flag 13 1 read-write DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 2 0x10 1-2 CAL_FLAG%s DAC channel%s calibration offset status 14 1 read-only CAL_FLAG1 Lower Calibration trimming value is lower than the offset correction value 0 Equal_Higher Calibration trimming value is equal or greater than the offset correction value 1 2 0x10 1-2 BWST%s DAC channel%s busy writing sample time flag 15 1 read-only BWST1 Idle There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written 0 Busy There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written 1 CCR CCR DAC calibration control register 0x38 0x20 0x00000000 0xFF00FF00 2 0x10 1-2 OTRIM%s DAC channel%s offset trimming value 0 5 read-write 0 31 MCR MCR DAC mode control register 0x3C 0x20 0x00000000 0xFFFFFFFF 2 0x10 1-2 MODE%s DAC channel%s mode 0 3 read-write MODE1 NormalPinBuffer Normal mode - DAC channelx is connected to external pin with Buffer enabled 0 NormalPinChipBuffer Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 1 NormalPinNoBuffer Normal mode - DAC channelx is connected to external pin with Buffer disabled 2 NormalChipNoBuffer Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled 3 SHPinBuffer S&H mode - DAC channelx is connected to external pin with Buffer enabled 4 SHPinChipBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 5 SHPinNoBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled 6 SHChipNoBuffer S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled 7 2 0x10 1-2 DMADOUBLE%s DAC channel%s DMA double data mode 8 1 read-write DMADOUBLE1 Normal DMA Normal mode selected 0 DoubleData DMA Double data mode selected 1 2 0x10 1-2 SINFORMAT%s Enable signed format for DAC channel%s 9 1 read-write SINFORMAT1 Unsigned Input data is in unsigned format 0 Signed Input data is in signed format (2's complement). The MSB bit represents the sign. 1 HFSEL High frequency interface mode selection 14 2 HFSEL Disabled High frequency interface mode disabled 0 More80Mhz High frequency interface mode enabled for AHB clock frequency > 80 MHz 1 More160Mhz High frequency interface mode enabled for AHB clock frequency >160 MHz 2 2 0x4 1-2 SHSR%s SHSR%s DAC channel%s sample and hold sample time register 0x40 0x20 0x00000000 0xFFFFFFFF TSAMPLE DAC channel1 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST1 = 1, the write operation is ignored. 0 10 read-write 0 1023 SHHR SHHR DAC sample and hold time register 0x48 0x20 0x00010001 0xFFFFFFFF 2 0x10 1-2 THOLD%s DAC channel%s hold time (only valid in Sample and hold mode) 0 10 read-write 0 1023 SHRR SHRR DAC sample and hold refresh time register 0x4C 0x20 0x00010001 0xFFFFFFFF 2 0x10 1-2 TREFRESH%s DAC channel%s refresh time (only valid in Sample and hold mode) 0 8 read-write 0 255 DBGMCU Microcontroller debug unit DBG 0x44024000 0x0 0x1000 registers IDCODE IDCODE DBGMCU identity code register 0x0 0x20 0x00006000 0x0000F000 DEV_ID device identification 0 12 read-only REV_ID revision This field indicates the revision of the device. 16 16 read-only CR CR DBGMCU configuration register 0x4 0x20 0x00000000 0xFFFFFFFF DBG_STOP Allows debug in Stop mode All clocks are disabled automatically in Stop mode. All active clocks and oscillators continue to run during Stop mode, allowing full debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state. 1 1 read-write DBG_STANDBY Allows debug in Standby mode All clocks are disabled and the core powered down automatically in Standby mode. All active clocks and oscillators continue to run during Standby mode, and the core supply is maintained, allowing full debug capability. On exit from Standby mode, a system reset is performed. 2 1 read-write TRACE_IOEN trace pin enable 4 1 read-write TRACE_EN trace port and clock enable. This bit enables the trace port clock, TRACECK. 5 1 read-write TRACE_MODE trace pin assignment 6 2 read-write DCRT Debug credentials reset type This bit selects which type of reset is used to revoke the debug authentication credentials 16 1 read-write APB1LFZR APB1LFZR DBGMCU APB1L peripheral freeze register 0x8 0x20 0x00000000 0xFFFFFFFF DBG_TIM2_STOP TIM2 stop in debug 0 1 read-write DBG_TIM3_STOP TIM3 stop in debug 1 1 read-write DBG_TIM6_STOP TIM6 stop in debug 4 1 read-write DBG_TIM7_STOP TIM7 stop in debug 5 1 read-write DBG_WWDG_STOP WWDG stop in debug 11 1 read-write DBG_IWDG_STOP IWDG stop in debug 12 1 read-write DBG_I2C1_STOP I2C1 SMBUS timeout stop in debug 21 1 read-write DBG_I2C2_STOP I2C2 SMBUS timeout stop in debug 22 1 read-write DBG_I3C1_STOP I3C1 SCL stall counter stop in debug 23 1 read-write APB1HFZR APB1HFZR DBGMCU APB1H peripheral freeze register 0xC 0x20 0x00000000 0xFFFFFFFF DBG_LPTIM2_STOP LPTIM2 stop in debug 5 1 read-write APB2FZR APB2FZR DBGMCU APB2 peripheral freeze register 0x10 0x20 0x00000000 0xFFFFFFFF DBG_TIM1_STOP TIM1 stop in debug 11 1 read-write APB3FZR APB3FZR DBGMCU APB3 peripheral freeze register 0x14 0x20 0x00000000 0xFFFFFFFF DBG_I3C2_STOP I3C2 SCL stall counter stop in debug 12 1 read-write DBG_LPTIM1_STOP LPTIM1 stop in debug 17 1 read-write DBG_RTC_STOP RTC stop in debug 30 1 read-write AHB1FZR AHB1FZR DBGMCU AHB1 peripheral freeze register 0x20 0x20 0x00000000 0xFFFFFFFF DBG_GPDMA1_0_STOP GPDMA1 channel 0 stop in debug 0 1 read-write DBG_GPDMA1_1_STOP GPDMA1 channel 1 stop in debug 1 1 read-write DBG_GPDMA1_2_STOP GPDMA1 channel 2 stop in debug 2 1 read-write DBG_GPDMA1_3_STOP GPDMA1 channel 3 stop in debug 3 1 read-write DBG_GPDMA1_4_STOP GPDMA1 channel 4 stop in debug 4 1 read-write DBG_GPDMA1_5_STOP GPDMA1 channel 5 stop in debug 5 1 read-write DBG_GPDMA1_6_STOP GPDMA1 channel 6 stop in debug 6 1 read-write DBG_GPDMA1_7_STOP GPDMA1 channel 7 stop in debug 7 1 read-write DBG_GPDMA2_0_STOP GPDMA2 channel 0 stop in debug 16 1 read-write DBG_GPDMA2_1_STOP GPDMA2 channel 1 stop in debug 17 1 read-write DBG_GPDMA2_2_STOP GPDMA2 channel 2 stop in debug 18 1 read-write DBG_GPDMA2_3_STOP GPDMA2 channel 3 stop in debug 19 1 read-write DBG_GPDMA2_4_STOP GPDMA2 channel 4 stop in debug 20 1 read-write DBG_GPDMA2_5_STOP GPDMA2 channel 5 stop in debug 21 1 read-write DBG_GPDMA2_6_STOP GPDMA2 channel 6 stop in debug 22 1 read-write DBG_GPDMA2_7_STOP GPDMA2 channel 7 stop in debug 23 1 read-write SR SR DBGMCU status register 0xFC 0x20 0x00010003 0xFFFF00FF AP_PRESENT Bit n identifies whether access port AP n is present in device Bit n = 0: APn absent Bit n = 1: APn present 0 16 write-only AP_ENABLED Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) Bit n = 0: APn locked Bit n = 1: APn enabled 16 16 write-only DBG_AUTH_HOST DBG_AUTH_HOST DBGMCU debug authentication mailbox host register 0x100 0x20 0x00000000 0x00000000 MESSAGE Debug host to device mailbox message. During debug authentication the debug host communicates with the device via this register. 0 32 read-write DBG_AUTH_DEVICE DBG_AUTH_DEVICE DBGMCU debug authentication mailbox device register 0x104 0x20 0x00000000 0x00000000 MESSAGE Device to debug host mailbox message. During debug authentication the device communicates with the debug host via this register. 0 32 read-only DBG_AUTH_ACK DBG_AUTH_ACK DBGMCU debug authentication mailbox acknowledge register 0x108 0x20 0x00000000 0xFFFFFFFF HOST_ACK Host to device acknowledge. The device sets this bit to indicate that it has placed a message in the DBGMCU_DBG_AUTH_DEVICE register. It should be reset by the host after reading the message 0 1 read-write DEV_ACK Device to device acknowledge. The host sets this bit to indicate that it has placed a message in the DBGMCU_DBG_AUTH_HOST register. It is reset by the device after reading the message 1 1 read-write PIDR4 PIDR4 DBGMCU CoreSight peripheral identity register 4 0xFD0 0x20 0x00000000 0xFFFFFFFF JEP106CON JEP106 continuation code 0 4 read-only SIZE register file size 4 4 read-only PIDR0 PIDR0 DBGMCU CoreSight peripheral identity register 0 0xFE0 0x20 0x00000000 0xFFFFFFFF PARTNUM part number bits [7:0] 0 8 read-only PIDR1 PIDR1 DBGMCU CoreSight peripheral identity register 1 0xFE4 0x20 0x00000000 0xFFFFFFFF PARTNUM part number bits [11:8] 0 4 read-only JEP106ID JEP106 identity code bits [3:0] 4 4 read-only PIDR2 PIDR2 DBGMCU CoreSight peripheral identity register 2 0xFE8 0x20 0x0000000A 0xFFFFFFFF JEP106ID JEP106 identity code bits [6:4] 0 3 read-only JEDEC JEDEC assigned value 3 1 read-only REVISION component revision number 4 4 read-only PIDR3 PIDR3 DBGMCU CoreSight peripheral identity register 3 0xFEC 0x20 0x00000000 0xFFFFFFFF CMOD customer modified 0 4 read-only REVAND metal fix version 4 4 read-only CIDR0 CIDR0 DBGMCU CoreSight component identity register 0 0xFF0 0x20 0x0000000D 0xFFFFFFFF PREAMBLE component identification bits [7:0] 0 8 read-only CIDR1 CIDR1 DBGMCU CoreSight component identity register 1 0xFF4 0x20 0x000000F0 0xFFFFFFFF PREAMBLE component identification bits [11:8] 0 4 read-only CLASS component identification bits [15:12] - component class 4 4 read-only CIDR2 CIDR2 DBGMCU CoreSight component identity register 2 0xFF8 0x20 0x00000005 0xFFFFFFFF PREAMBLE component identification bits [23:16] 0 8 read-only CIDR3 CIDR3 DBGMCU CoreSight component identity register 3 0xFFC 0x20 0x000000B1 0xFFFFFFFF PREAMBLE component identification bits [31:24] 0 8 read-only DTS Digital temperature sensor DTS 0x40008C00 0x0 0x400 registers DTS_WKUP DTS interrupt or DTS AIT through EXTI line 113 CFGR1 CFGR1 Temperature sensor configuration register 1 0x0 0x20 0x00000000 0xFFFFFFFF TS1_EN Temperature sensor 1 enable bit This bit is set and cleared by software. Note: Once enabled, the temperature sensor is active after a specific delay time. The TS1_RDY flag will be set when the sensor is ready. 0 1 read-write TS1_START Start frequency measurement on temperature sensor 1 This bit is set and cleared by software. 4 1 read-write TS1_INTRIG_SEL Input trigger selection bit for temperature sensor 1 These bits are set and cleared by software. They select which input triggers a temperature measurement. Refer to Section 19.3.10: Trigger input. 8 4 read-write TS1_SMP_TIME Sampling time for temperature sensor 1 These bits allow increasing the sampling time to improve measurement precision. When the PCLK clock is selected as reference clock (REFCLK_SEL = 0), the measurement will be performed at TS1_SMP_TIME period of CLK_PTAT. When the LSE is selected as reference clock (REFCLK_SEL =1), the measurement will be performed at TS1_SMP_TIME period of LSE. 16 4 read-write REFCLK_SEL Reference clock selection bit This bit is set and cleared by software. It indicates whether the reference clock is the high speed clock (PCLK) or the low speed clock (LSE). 20 1 read-write Q_MEAS_OPT Quick measurement option bit This bit is set and cleared by software. It is used to increase the measurement speed by suppressing the calibration step. It is effective only when the LSE clock is used as reference clock (REFCLK_SEL=1). 21 1 read-write HSREF_CLK_DIV High speed clock division ratio These bits are set and cleared by software. They can be used to define the division ratio for the main clock in order to obtain the internal frequency lower than 1 MHz required for the calibration. They are applicable only for calibration when PCLK is selected as reference clock (REFCLK_SEL=0). ... 24 7 read-write T0VALR1 T0VALR1 Temperature sensor T0 value register 1 0x8 0x20 0x00000000 0x00000000 TS1_FMT0 Engineering value of the frequency measured at T0 for temperature sensor 1 This value is expressed in 0.1 kHz. 0 16 read-only TS1_T0 Engineering value of the T0 temperature for temperature sensor 1. Others: Reserved, must not be used. 16 2 read-only RAMPVALR RAMPVALR Temperature sensor ramp value register 0x10 0x20 0x00000000 0x00000000 TS1_RAMP_COEFF Engineering value of the ramp coefficient for the temperature sensor 1. This value is expressed in Hz/ C. 0 16 read-only ITR1 ITR1 Temperature sensor interrupt threshold register 1 0x14 0x20 0x00000000 0xFFFFFFFF TS1_LITTHD Low interrupt threshold for temperature sensor 1 These bits are set and cleared by software. They indicate the lowest value than can be reached before raising an interrupt signal. 0 16 read-write TS1_HITTHD High interrupt threshold for temperature sensor 1 These bits are set and cleared by software. They indicate the highest value than can be reached before raising an interrupt signal. 16 16 read-write DR DR Temperature sensor data register 0x1C 0x20 0x00000000 0xFFFFFFFF TS1_MFREQ Value of the counter output value for temperature sensor 1 0 16 read-write SR SR Temperature sensor status register 0x20 0x20 0x00000000 0xFFFFFFFF TS1_ITEF Interrupt flag for end of measurement on temperature sensor 1, synchronized on PCLK. This bit is set by hardware when a temperature measure is done. It is cleared by software by writing 1 to the TS2_CITEF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITEFEN bit is set 0 1 read-only TS1_ITLF Interrupt flag for low threshold on temperature sensor 1, synchronized on PCLK. This bit is set by hardware when the low threshold is set and reached. It is cleared by software by writing 1 to the TS1_CITLF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITLFEN bit is set 1 1 read-only TS1_ITHF Interrupt flag for high threshold on temperature sensor 1, synchronized on PCLK This bit is set by hardware when the high threshold is set and reached. It is cleared by software by writing 1 to the TS1_CITHF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITHFEN bit is set 2 1 read-only TS1_AITEF Asynchronous interrupt flag for end of measure on temperature sensor 1 This bit is set by hardware when a temperature measure is done. It is cleared by software by writing 1 to the TS1_CAITEF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITEFEN bit is set 4 1 read-only TS1_AITLF Asynchronous interrupt flag for low threshold on temperature sensor 1 This bit is set by hardware when the low threshold is reached. It is cleared by software by writing 1 to the TS1_CAITLF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITLFEN bit is set 5 1 read-only TS1_AITHF Asynchronous interrupt flag for high threshold on temperature sensor 1 This bit is set by hardware when the high threshold is reached. It is cleared by software by writing 1 to the TS1_CAITHF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITHFEN bit is set 6 1 read-only TS1_RDY Temperature sensor 1 ready flag This bit is set and reset by hardware. It indicates that a measurement is ongoing. 15 1 read-only ITENR ITENR Temperature sensor interrupt enable register 0x24 0x20 0x00000000 0xFFFFFFFF TS1_ITEEN Interrupt enable flag for end of measurement on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the synchronous interrupt for end of measurement. 0 1 read-write TS1_ITLEN Interrupt enable flag for low threshold on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the synchronous interrupt when the measure reaches or is below the low threshold. 1 1 read-write TS1_ITHEN Interrupt enable flag for high threshold on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the interrupt when the measure reaches or is above the high threshold. 2 1 read-write TS1_AITEEN Asynchronous interrupt enable flag for end of measurement on temperature sensor 1 This bit are set and cleared by software. It enables the asynchronous interrupt for end of measurement (only when REFCLK_SEL = 1). 4 1 read-write TS1_AITLEN Asynchronous interrupt enable flag for low threshold on temperature sensor 1. This bit are set and cleared by software. It enables the asynchronous interrupt when the temperature is below the low threshold (only when REFCLK_SEL= 1) 5 1 read-write TS1_AITHEN Asynchronous interrupt enable flag on high threshold for temperature sensor 1. This bit are set and cleared by software. It enables the asynchronous interrupt when the temperature is above the high threshold (only when REFCLK_SEL= 1'') 6 1 read-write ICIFR ICIFR Temperature sensor clear interrupt flag register 0x28 0x20 0x00000000 0xFFFFFFFF TS1_CITEF Interrupt clear flag for end of measurement on temperature sensor 1 Writing 1 to this bit clears the TS1_ITEF flag in the DTS_SR register. 0 1 read-write TS1_CITLF Interrupt clear flag for low threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_ITLF flag in the DTS_SR register. 1 1 read-write TS1_CITHF Interrupt clear flag for high threshold on temperature sensor 1 Writing this bit to 1 clears the TS1_ITHF flag in the DTS_SR register. 2 1 read-write TS1_CAITEF Write once bit. Clear the asynchronous IT flag for End Of Measure for thermal sensor 1. Writing 1 clears the TS1_AITEF flag of the DTS_SR register. 4 1 read-write TS1_CAITLF Asynchronous interrupt clear flag for low threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_AITLF flag in the DTS_SR register. 5 1 read-write TS1_CAITHF Asynchronous interrupt clear flag for high threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_AITHF flag in the DTS_SR register. 6 1 read-write OR OR Temperature sensor option register 0x2C 0x20 0x00000000 0xFFFFFFFF TS_OP0 general purpose option bits 0 1 read-write TS_OP1 general purpose option bits 1 1 read-write TS_OP2 general purpose option bits 2 1 read-write TS_OP3 general purpose option bits 3 1 read-write TS_OP4 general purpose option bits 4 1 read-write TS_OP5 general purpose option bits 5 1 read-write TS_OP6 general purpose option bits 6 1 read-write TS_OP7 general purpose option bits 7 1 read-write TS_OP8 general purpose option bits 8 1 read-write TS_OP9 general purpose option bits 9 1 read-write TS_OP10 general purpose option bits 10 1 read-write TS_OP11 general purpose option bits 11 1 read-write TS_OP12 general purpose option bits 12 1 read-write TS_OP13 general purpose option bits 13 1 read-write TS_OP14 general purpose option bits 14 1 read-write TS_OP15 general purpose option bits 15 1 read-write TS_OP16 general purpose option bits 16 1 read-write TS_OP17 general purpose option bits 17 1 read-write TS_OP18 general purpose option bits 18 1 read-write TS_OP19 general purpose option bits 19 1 read-write TS_OP20 general purpose option bits 20 1 read-write TS_OP21 general purpose option bits 21 1 read-write TS_OP22 general purpose option bits 22 1 read-write TS_OP23 general purpose option bits 23 1 read-write TS_OP24 general purpose option bits 24 1 read-write TS_OP25 general purpose option bits 25 1 read-write TS_OP26 general purpose option bits 26 1 read-write TS_OP27 general purpose option bits 27 1 read-write TS_OP28 general purpose option bits 28 1 read-write TS_OP29 general purpose option bits 29 1 read-write TS_OP30 general purpose option bits 30 1 read-write TS_OP31 general purpose option bits 31 1 read-write EXTI Extended interrupt/event controller EXTI 0x44022000 0x0 0x400 registers EXTI0 EXTI Line0 interrupt 11 EXTI1 EXTI Line1 interrupt 12 EXTI2 EXTI Line2 interrupt 13 EXTI3 EXTI Line3 interrupt 14 EXTI4 EXTI Line4 interrupt 15 EXTI5 EXTI Line5 interrupt 16 EXTI6 EXTI Line6 interrupt 17 EXTI7 EXTI Line7 interrupt 18 EXTI8 EXTI Line8 interrupt 19 EXTI9 EXTI Line9 interrupt 20 EXTI10 EXTI Line10 interrupt 21 EXTI11 EXTI Line11 interrupt 22 EXTI12 EXTI Line12 interrupt 23 EXTI13 EXTI Line13 interrupt 24 EXTI14 EXTI Line14 interrupt 25 EXTI15 EXTI Line15 interrupt 26 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 0x00000000 0xFFFFFFFF RT0 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 0 1 read-write RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT1 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 1 1 read-write RT2 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 2 1 read-write RT3 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 3 1 read-write RT4 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 4 1 read-write RT5 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 5 1 read-write RT6 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 6 1 read-write RT7 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 7 1 read-write RT8 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 8 1 read-write RT9 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 9 1 read-write RT10 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 10 1 read-write RT11 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 11 1 read-write RT12 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 12 1 read-write RT13 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 13 1 read-write RT14 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 14 1 read-write RT15 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 15 1 read-write RT16 Rising trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 16 1 read-write FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 0x00000000 0xFFFFFFFF FT0 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 0 1 read-write FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT1 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 1 1 read-write FT2 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 2 1 read-write FT3 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 3 1 read-write FT4 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 4 1 read-write FT5 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 5 1 read-write FT6 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 6 1 read-write FT7 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 7 1 read-write FT8 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 8 1 read-write FT9 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 9 1 read-write FT10 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 10 1 read-write FT11 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 11 1 read-write FT12 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 12 1 read-write FT13 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 13 1 read-write FT14 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 14 1 read-write FT15 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 15 1 read-write FT16 Falling trigger event configuration bit of configurable event input x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 16 1 read-write SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 0x00000000 0xFFFFFFFF SWI0 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 1 read-write SoftwareInterrupt write Pend Generates an interrupt request 1 SWI1 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 1 1 read-write SWI2 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 2 1 read-write SWI3 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 3 1 read-write SWI4 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 4 1 read-write SWI5 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 5 1 read-write SWI6 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 6 1 read-write SWI7 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 7 1 read-write SWI8 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 8 1 read-write SWI9 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 9 1 read-write SWI10 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 10 1 read-write SWI11 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 11 1 read-write SWI12 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 12 1 read-write SWI13 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 13 1 read-write SWI14 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 14 1 read-write SWI15 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 15 1 read-write SWI16 Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 16 1 read-write RPR1 RPR1 EXTI rising edge pending register 0xC 0x20 0x00000000 0xFFFFFFFF RPIF0 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 0 1 read-write oneToClear RPIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 RPIF0W write Clear Clears pending bit 1 RPIF1 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 1 1 read-write oneToClear read write RPIF2 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 2 1 read-write oneToClear read write RPIF3 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 3 1 read-write oneToClear read write RPIF4 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 4 1 read-write oneToClear read write RPIF5 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 5 1 read-write oneToClear read write RPIF6 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 6 1 read-write oneToClear read write RPIF7 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 7 1 read-write oneToClear read write RPIF8 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 8 1 read-write oneToClear read write RPIF9 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 9 1 read-write oneToClear read write RPIF10 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 10 1 read-write oneToClear read write RPIF11 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 11 1 read-write oneToClear read write RPIF12 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 12 1 read-write oneToClear read write RPIF13 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 13 1 read-write oneToClear read write RPIF14 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 14 1 read-write oneToClear read write RPIF15 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 15 1 read-write oneToClear read write RPIF16 configurable event inputs x rising edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 16 1 read-write oneToClear read write FPR1 FPR1 EXTI falling edge pending register 0x10 0x20 0x00000000 0xFFFFFFFF FPIF0 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 0 1 read-write oneToClear FPIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 FPIF0W write Clear Clears pending bit 1 FPIF1 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 1 1 read-write oneToClear read write FPIF2 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 2 1 read-write oneToClear read write FPIF3 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 3 1 read-write oneToClear read write FPIF4 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 4 1 read-write oneToClear read write FPIF5 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 5 1 read-write oneToClear read write FPIF6 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 6 1 read-write oneToClear read write FPIF7 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 7 1 read-write oneToClear read write FPIF8 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 8 1 read-write oneToClear read write FPIF9 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 9 1 read-write oneToClear read write FPIF10 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 10 1 read-write oneToClear read write FPIF11 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 11 1 read-write oneToClear read write FPIF12 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 12 1 read-write oneToClear read write FPIF13 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 13 1 read-write oneToClear read write FPIF14 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 14 1 read-write oneToClear read write FPIF15 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 15 1 read-write oneToClear read write FPIF16 configurable event inputs x falling edge pending bit (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 16 1 read-write oneToClear read write PRIVCFGR1 PRIVCFGR1 EXTI privilege configuration register 0x18 0x20 0x00000000 0xFFFFFFFF PRIV0 Privilege enable on event input x (x = 17 to 0) 0 1 read-write EventPrivilege Unprivileged Event privilege disabled 0 Privileged Event privilege enabled 1 PRIV1 Privilege enable on event input x (x = 17 to 0) 1 1 read-write PRIV2 Privilege enable on event input x (x = 17 to 0) 2 1 read-write PRIV3 Privilege enable on event input x (x = 17 to 0) 3 1 read-write PRIV4 Privilege enable on event input x (x = 17 to 0) 4 1 read-write PRIV5 Privilege enable on event input x (x = 17 to 0) 5 1 read-write PRIV6 Privilege enable on event input x (x = 17 to 0) 6 1 read-write PRIV7 Privilege enable on event input x (x = 17 to 0) 7 1 read-write PRIV8 Privilege enable on event input x (x = 17 to 0) 8 1 read-write PRIV9 Privilege enable on event input x (x = 17 to 0) 9 1 read-write PRIV10 Privilege enable on event input x (x = 17 to 0) 10 1 read-write PRIV11 Privilege enable on event input x (x = 17 to 0) 11 1 read-write PRIV12 Privilege enable on event input x (x = 17 to 0) 12 1 read-write PRIV13 Privilege enable on event input x (x = 17 to 0) 13 1 read-write PRIV14 Privilege enable on event input x (x = 17 to 0) 14 1 read-write PRIV15 Privilege enable on event input x (x = 17 to 0) 15 1 read-write PRIV16 Privilege enable on event input x (x = 17 to 0) 16 1 read-write PRIV17 Privilege enable on event input x (x = 17 to 0) 17 1 read-write PRIV19 Privilege enable on event input 19 19 1 read-write PRIV21 Privilege enable on event input x (x = 22 to 21) 21 1 read-write PRIV22 Privilege enable on event input x (x = 22 to 21) 22 1 read-write PRIV24 Privilege enable on event input x (x = 29 to 24) 24 1 read-write PRIV25 Privilege enable on event input x (x = 29 to 24) 25 1 read-write PRIV26 Privilege enable on event input x (x = 29 to 24) 26 1 read-write PRIV27 Privilege enable on event input x (x = 29 to 24) 27 1 read-write PRIV28 Privilege enable on event input x (x = 29 to 24) 28 1 read-write PRIV29 Privilege enable on event input x (x = 29 to 24) 29 1 read-write RTSR2 RTSR2 EXTI rising trigger selection register 2 0x20 0x20 0x00000000 0xFFFFFFFF RT50 Rising trigger event configuration bit of configurable event input x When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 18 1 read-write RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT53 Rising trigger event configuration bit of configurable event input x When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 21 1 read-write FTSR2 FTSR2 EXTI falling trigger selection register 2 0x24 0x20 0x00000000 0xFFFFFFFF FT50 Falling trigger event configuration bit of configurable event input x When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 18 1 read-write FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT53 Falling trigger event configuration bit of configurable event input x When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 21 1 read-write SWIER2 SWIER2 EXTI software interrupt event register 2 0x28 0x20 0x00000000 0xFFFFFFFF SWI50 Software interrupt on event x When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 18 1 read-write SoftwareInterrupt write Pend Generates an interrupt request 1 SWI53 Software interrupt on event x When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 21 1 read-write RPR2 RPR2 EXTI rising edge pending register 2 0x2C 0x20 0x00000000 0xFFFFFFFF RPIF50 configurable event inputs x rising edge pending bit When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 18 1 read-write oneToClear RPIF50R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 RPIF50W write Clear Clears pending bit 1 RPIF53 configurable event inputs x rising edge pending bit When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 21 1 read-write oneToClear read write FPR2 FPR2 EXTI falling edge pending register 2 0x30 0x20 0x00000000 0xFFFFFFFF FPIF50 configurable event inputs x falling edge pending bit When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 18 1 read-write oneToClear FPIF50R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 FPIF50W write Clear Clears pending bit 1 FPIF53 configurable event inputs x falling edge pending bit When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 21 1 read-write oneToClear read write PRIVCFGR2 PRIVCFGR2 EXTI privilege configuration register 2 0x38 0x20 0x00000000 0xFFFFFFFF PRIV37 Privilege enable on event input x (x = 42 to 37) 5 1 read-write EventPrivilege Unprivileged Event privilege disabled 0 Privileged Event privilege enabled 1 PRIV38 Privilege enable on event input x (x = 42 to 37) 6 1 read-write PRIV39 Privilege enable on event input x (x = 42 to 37) 7 1 read-write PRIV40 Privilege enable on event input x (x = 42 to 37) 8 1 read-write PRIV41 Privilege enable on event input x (x = 42 to 37) 9 1 read-write PRIV42 Privilege enable on event input x (x = 42 to 37) 10 1 read-write PRIV47 Privilege enable on event input x 15 1 read-write PRIV49 Privilege enable on event input x (x = 50 to 49) 17 1 read-write PRIV50 Privilege enable on event input x (x = 50 to 49) 18 1 read-write PRIV53 Privilege enable on event input x 21 1 read-write EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 0x00000000 0xFFFFFFFF EXTI0 EXTI0 GPIO port selection These bits are written by software to select the source input for EXTI0 external interrupt. When EXTI_PRIVCFGR.PRIV0 is disabled, EXTI0 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV0 is enabled, EXTI0 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 8 read-write EXTI1 EXTI1 GPIO port selection These bits are written by software to select the source input for EXTI1 external interrupt. When EXTI_PRIVCFGR.PRIV1 is disabled, EXTI1 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV1 is enabled, EXTI1 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 8 8 read-write EXTI2 EXTI2 GPIO port selection These bits are written by software to select the source input for EXTI2 external interrupt. When EXTI_PRIVCFGR.PRIV2 is disabled, EXTI2 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV2 is enabled, EXTI2 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 16 8 read-write EXTI3 EXTI3 GPIO port selectio These bits are written by software to select the source input for EXTI3 external interrupt. When EXTI_PRIVCFGR.PRIV3 is disabled, EXTI3 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV3 is enabled, EXTI3 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 24 8 read-write EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 0x00000000 0xFFFFFFFF EXTI4 EXTI4 GPIO port selection These bits are written by software to select the source input for EXTI4 external interrupt. When EXTI_PRIVCFGR.PRIV4 is disabled, EXTI4 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV4 is enabled, EXTI4 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 8 read-write EXTI5 EXTI5 GPIO port selection These bits are written by software to select the source input for EXTI5 external interrupt. When EXTI_PRIVCFGR.PRIV5 is disabled, EXTI5 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV5 is enabled, EXTI5 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 8 8 read-write EXTI6 EXTI6 GPIO port selection These bits are written by software to select the source input for EXTI6 external interrupt. When EXTI_PRIVCFGR.PRIV6 is disabled, EXTI6 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV6 is enabled, EXTI6 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 16 8 read-write EXTI7 EXTI7 GPIO port selection These bits are written by software to select the source input for EXTI7 external interrupt. When EXTI_PRIVCFGR.PRIV7 is disabled, EXTI7 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV7 is enabled, EXTI7 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 24 8 read-write EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 0x20 0x00000000 0xFFFFFFFF EXTI8 EXTI8 GPIO port selection These bits are written by software to select the source input for EXTIm external interrupt. When EXTI_PRIVCFGR.PRIV8 is disabled, EXTI8 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV8 is enabled, EXTI8 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 8 read-write EXTI9 EXTI9 GPIO port selection These bits are written by software to select the source input for EXTI9 external interrupt. When EXTI_PRIVCFGR.PRIV9 is disabled, EXTI9 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV9 is enabled, EXTI9 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 8 8 read-write EXTI10 EXTI10 GPIO port selection These bits are written by software to select the source input for EXTI10 external interrupt. When EXTI_PRIVCFGR.PRIV10 is disabled, EXTI10 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV10 is enabled, EXTI10 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 16 8 read-write EXTI11 EXTI11 GPIO port selection These bits are written by software to select the source input for EXTI11 external interrupt. When EXTI_PRIVCFGR.PRIV11 is disabled, EXTI11 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV11 is enabled, EXTI11 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 24 8 read-write EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 0x20 0x00000000 0xFFFFFFFF EXTI12 EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 8 read-write EXTI13 EXTI13 GPIO port selection These bits are written by software to select the source input for EXTI13 external interrupt. When EXTI_PRIVCFGR.PRIV13 is disabled, EXTI13 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV13 is enabled, EXTI13 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 8 8 read-write EXTI14 EXTI14 GPIO port selection These bits are written by software to select the source input for EXTI14 external interrupt. When EXTI_PRIVCFGR.PRIV14 is disabled, EXTI14 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV14 is enabled, EXTI14 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 16 8 read-write EXTI15 EXTI15 GPIO port selection These bits are written by software to select the source input for EXTI15 external interrupt. When EXTI_PRIVCFGR.PRIV15 is disabled, EXTI15 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV15 is enabled, EXTI15 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 24 8 read-write IMR1 IMR1 EXTI CPU wakeup with interrupt mask register 0x80 0x20 0xFFFE0000 0xFFFFFFFF IM0 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 1 read-write InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 IM1 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 1 1 read-write IM2 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 2 1 read-write IM3 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 3 1 read-write IM4 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 4 1 read-write IM5 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 5 1 read-write IM6 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 6 1 read-write IM7 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 7 1 read-write IM8 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 8 1 read-write IM9 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 9 1 read-write IM10 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 10 1 read-write IM11 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 11 1 read-write IM12 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 12 1 read-write IM13 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 13 1 read-write IM14 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 14 1 read-write IM15 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 15 1 read-write IM16 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 16 1 read-write IM17 CPU wakeup with interrupt mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 17 1 read-write IM19 CPU wakeup with interrupt mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 19 1 read-write IM21 CPU wakeup with interrupt mask on event input x (x = 22 to 21) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 21 1 read-write IM22 CPU wakeup with interrupt mask on event input x (x = 22 to 21) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 22 1 read-write IM24 CPU wakeup with interrupt mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 24 1 read-write IM25 CPU wakeup with interrupt mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 25 1 read-write IM26 CPU wakeup with interrupt mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 26 1 read-write IM27 CPU wakeup with interrupt mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 27 1 read-write IM28 CPU wakeup with interrupt mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 28 1 read-write IM29 CPU wakeup with interrupt mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 29 1 read-write EMR1 EMR1 EXTI CPU wakeup with event mask register 0x84 0x20 0xFFFE0000 0xFFFFFFFF EM0 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 1 read-write EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM1 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 1 1 read-write EM2 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 2 1 read-write EM3 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 3 1 read-write EM4 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 4 1 read-write EM5 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 5 1 read-write EM6 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 6 1 read-write EM7 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 7 1 read-write EM8 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 8 1 read-write EM9 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 9 1 read-write EM10 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 10 1 read-write EM11 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 11 1 read-write EM12 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 12 1 read-write EM13 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 13 1 read-write EM14 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 14 1 read-write EM15 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 15 1 read-write EM16 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 16 1 read-write EM17 CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 17 1 read-write EM19 CPU wakeup with event generation mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 19 1 read-write EM21 CPU wakeup with event generation mask on event input x (x = 22 to 21) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 21 1 read-write EM22 CPU wakeup with event generation mask on event input x (x = 22 to 21) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 22 1 read-write EM24 CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 24 1 read-write EM25 CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 25 1 read-write EM26 CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 26 1 read-write EM27 CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 27 1 read-write EM28 CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 28 1 read-write EM29 CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 29 1 read-write IMR2 IMR2 EXTI CPU wakeup with interrupt mask register 2 0x90 0x20 0x00DBBFFF 0xFFFFFFFF IM37 CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 5 1 read-write InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 IM38 CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 6 1 read-write IM39 CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 7 1 read-write IM40 CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 8 1 read-write IM41 CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 9 1 read-write IM42 CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 10 1 read-write IM47 CPU wakeup with interrupt mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 15 1 read-write IM49 CPU wakeup with interrupt mask on event input x (x = 50 to 49) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 17 1 read-write IM50 CPU wakeup with interrupt mask on event input x (x = 50 to 49) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 18 1 read-write IM53 CPU wakeup with interrupt mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 21 1 read-write EMR2 EMR2 EXTI CPU wakeup with event mask register 2 0x94 0x20 0x00DBBFFF 0xFFFFFFFF EM37 CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 5 1 read-write EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM38 CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 6 1 read-write EM39 CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 7 1 read-write EM40 CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 8 1 read-write EM41 CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 9 1 read-write EM42 CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 10 1 read-write EM47 CPU wakeup with event generation mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 15 1 read-write EM49 CPU wakeup with event generation mask on event input x (x = 50 to 49) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 17 1 read-write EM50 CPU wakeup with event generation mask on event input x (x = 50 to 49) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 18 1 read-write EM53 CPU wakeup with event generation mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 21 1 read-write FDCAN1 Controller area network FDCAN 0x4000A400 0x0 0x400 registers FDCAN1_IT0 FDCAN1 interrupt 0 39 FDCAN1_IT1 FDCAN1 interrupt 1 40 CREL CREL FDCAN core release register 0x0 0x20 0x32141218 0xFFFFFFFF DAY 18 0 8 read-only MON 12 8 8 read-only YEAR 4 16 4 read-only SUBSTEP 1 20 4 read-only STEP 2 24 4 read-only REL 3 28 4 read-only ENDN ENDN FDCAN endian register 0x4 0x20 0x87654321 0xFFFFFFFF ETV Endianness test value The endianness test value is 0x8765 4321. 0 32 read-only DBTP DBTP FDCAN data bit timing and prescaler register 0xC 0x20 0x00000A33 0xFFFFFFFF DSJW Synchronization jump width Must always be smaller than DTSEG2, valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1: tSJW = (DSJW + 1) x tq. 0 4 read-write DTSEG2 Data time segment after sample point Valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS2 = (DTSEG2 + 1) x tq. 4 4 read-write DTSEG1 Data time segment before sample point Valid values are 0 to 31. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS1 = (DTSEG1 + 1) x tq. 8 5 read-write DBRP Data bit rate prescaler The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1. 16 5 read-write TDC Transceiver delay compensation 23 1 read-write TEST TEST FDCAN test register 0x10 0x20 0x00000000 0xFFFFFFFF LBCK Loop back mode 4 1 read-write TX Control of transmit pin 5 2 read-write RX Receive pin Monitors the actual value of pin FDCANx_RX 7 1 read-only RWD RWD FDCAN RAM watchdog register 0x14 0x20 0x00000000 0xFFFFFFFF WDC Watchdog configuration Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of FDCAN_CCCR register are set to 1. 0 8 read-write WDV Watchdog value Actual message RAM watchdog counter value. 8 8 read-only CCCR CCCR FDCAN CC control register 0x18 0x20 0x00000001 0xFFFFFFFF INIT Initialization 0 1 read-write CCE Configuration change enable 1 1 read-write ASM ASM restricted operation mode The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted operation Mode after it has received a valid frame. In the optional Restricted operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time. 2 1 read-write CSA Clock stop acknowledge 3 1 read-only CSR Clock stop request 4 1 read-write MON Bus monitoring mode Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time. 5 1 read-write DAR Disable automatic retransmission 6 1 read-write TEST Test mode enable 7 1 read-write FDOE FD operation enable 8 1 read-write BRSE FDCAN bit rate switching 9 1 read-write PXHD Protocol exception handling disable 12 1 read-write EFBI Edge filtering during bus integration 13 1 read-write TXP If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. 14 1 read-write NISO Non ISO operation If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 15 1 read-write NBTP NBTP FDCAN nominal bit timing and prescaler register 0x1C 0x20 0x06000A03 0xFFFFFFFF NTSEG2 Nominal time segment after sample point Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. 0 7 read-write NTSEG1 Nominal time segment before sample point Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 8 8 read-write NBRP Bit rate prescaler Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 16 9 read-write NSJW Nominal (re)synchronization jump width Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 25 7 read-write TSCC TSCC FDCAN timestamp counter configuration register 0x20 0x20 0x00000000 0xFFFFFFFF TSS Timestamp select These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 2 read-write TCP Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times . 16 4 read-write TSCV TSCV FDCAN timestamp counter value register 0x24 0x20 0x00000000 0xFFFFFFFF TSC Timestamp counter The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). 0 16 read-write TOCC TOCC FDCAN timeout counter configuration register 0x28 0x20 0xFFFF0000 0xFFFFFFFF ETOC Timeout counter enable This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 1 read-write TOS Timeout select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 1 2 read-write TOP Timeout period Start value of the timeout counter (down-counter). Configures the timeout period. 16 16 read-write TOCV TOCV FDCAN timeout counter value register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF TOC Timeout counter The timeout counter is decremented in multiples of CAN bit times depending on the configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the timeout counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. 0 16 read-write ECR ECR FDCAN error counter register 0x40 0x20 0x00000000 0xFFFFFFFF TEC Transmit error counter Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 0 8 read-only REC Receive error counter Actual state of the receive error counter, values between 0 and 127. 8 7 read-only RP Receive error passive 15 1 read-only CEL CAN error logging The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read. 16 8 read-write PSR PSR FDCAN protocol status register 0x44 0x20 0x00000707 0xFFFFFFFF LEC Last error code The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. Access type is RS: set on read. 0 3 read-write ACT Activity Monitors the module's CAN communication state. 3 2 read-only EP Error passive 5 1 read-only EW Warning Sstatus 6 1 read-only BO Bus_Off status 7 1 read-only DLEC Data last error code Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read. 8 3 read-write RESI ESI flag of last received FDCAN message This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read. 11 1 read-write RBRS BRS flag of last received FDCAN message This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read. 12 1 read-write REDL Received FDCAN message This bit is set independent of acceptance filtering. Access type is RX: reset on read. 13 1 read-write PXE Protocol exception event 14 1 read-write TDCV Transmitter delay compensation value Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. 16 7 read-only TDCR TDCR FDCAN transmitter delay compensation register 0x48 0x20 0x00000000 0xFFFFFFFF TDCF Transmitter delay compensation filter window length Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 7 read-write TDCO Transmitter delay compensation offset Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 8 7 read-write IR IR FDCAN interrupt register 0x50 0x20 0x00000000 0xFFFFFFFF RF0N Rx FIFO 0 new message 0 1 read-write RF0F Rx FIFO 0 full 1 1 read-write RF0L Rx FIFO 0 message lost 2 1 read-write RF1N Rx FIFO 1 new message 3 1 read-write RF1F Rx FIFO 1 full 4 1 read-write RF1L Rx FIFO 1 message lost 5 1 read-write HPM High-priority message 6 1 read-write TC Transmission completed 7 1 read-write TCF Transmission cancellation finished 8 1 read-write TFE Tx FIFO empty 9 1 read-write TEFN Tx event FIFO New Entry 10 1 read-write TEFF Tx event FIFO full 11 1 read-write TEFL Tx event FIFO element lost 12 1 read-write TSW Timestamp wraparound 13 1 read-write MRAF Message RAM access failure The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted operation Mode (see mode). To leave Restricted operation Mode, the Host CPU has to reset CCCR.ASM. 14 1 read-write TOO Timeout occurred 15 1 read-write ELO Error logging overflow 16 1 read-write EP Error passive 17 1 read-write EW Warning status 18 1 read-write BO Bus_Off status 19 1 read-write WDI Watchdog interrupt 20 1 read-write PEA Protocol error in arbitration phase (nominal bit time is used) 21 1 read-write PED Protocol error in data phase (data bit time is used) 22 1 read-write ARA Access to reserved address 23 1 read-write IE IE FDCAN interrupt enable register 0x54 0x20 0x00000000 0xFFFFFFFF RF0NE Rx FIFO 0 new message interrupt enable 0 1 read-write RF0FE Rx FIFO 0 full interrupt enable 1 1 read-write RF0LE Rx FIFO 0 message lost interrupt enable 2 1 read-write RF1NE Rx FIFO 1 new message interrupt enable 3 1 read-write RF1FE Rx FIFO 1 full interrupt enable 4 1 read-write RF1LE Rx FIFO 1 message lost interrupt enable 5 1 read-write HPME High-priority message interrupt enable 6 1 read-write TCE Transmission completed interrupt enable 7 1 read-write TCFE Transmission cancellation finished interrupt enable 8 1 read-write TFEE Tx FIFO empty interrupt enable 9 1 read-write TEFNE Tx event FIFO new entry interrupt enable 10 1 read-write TEFFE Tx event FIFO full interrupt enable 11 1 read-write TEFLE Tx event FIFO element lost interrupt enable 12 1 read-write TSWE Timestamp wraparound interrupt enable 13 1 read-write MRAFE Message RAM access failure interrupt enable 14 1 read-write TOOE Timeout occurred interrupt enable 15 1 read-write ELOE Error logging overflow interrupt enable 16 1 read-write EPE Error passive interrupt enable 17 1 read-write EWE Warning status interrupt enable 18 1 read-write BOE Bus_Off status 19 1 read-write WDIE Watchdog interrupt enable 20 1 read-write PEAE Protocol error in arbitration phase enable 21 1 read-write PEDE Protocol error in data phase enable 22 1 read-write ARAE Access to reserved address enable 23 1 read-write ILS ILS FDCAN interrupt line select register 0x58 0x20 0x00000000 0xFFFFFFFF RxFIFO0 RX FIFO bit grouping the following interruption RF0LL: Rx FIFO 0 message lost interrupt line RF0FL: Rx FIFO 0 full interrupt line RF0NL: Rx FIFO 0 new message interrupt line 0 1 read-write RxFIFO1 RX FIFO bit grouping the following interruption RF1LL: Rx FIFO 1 message lost interrupt line RF1FL: Rx FIFO 1 full Interrupt line RF1NL: Rx FIFO 1 new message interrupt line 1 1 read-write SMSG Status message bit grouping the following interruption TCFL: Transmission cancellation finished interrupt line TCL: Transmission completed interrupt line HPML: High-priority message interrupt line 2 1 read-write TFERR Tx FIFO ERROR grouping the following interruption TEFLL: Tx event FIFO element lost interrupt line TEFFL: Tx event FIFO full interrupt line TEFNL: Tx event FIFO new entry interrupt line TFEL: Tx FIFO empty interrupt line 3 1 read-write MISC Interrupt regrouping the following interruption TOOL: Timeout occurred interrupt line MRAFL: Message RAM access failure interrupt line TSWL: Timestamp wraparound interrupt line 4 1 read-write BERR Bit and line error grouping the following interruption EPL Error passive interrupt line ELOL: Error logging overflow interrupt line 5 1 read-write PERR Protocol error grouping the following interruption ARAL: Access to reserved address line PEDL: Protocol error in data phase line PEAL: Protocol error in arbitration phase line WDIL: Watchdog interrupt line BOL: Bus_Off status EWL: Warning status interrupt line 6 1 read-write ILE ILE FDCAN interrupt line enable register 0x5C 0x20 0x00000000 0xFFFFFFFF EINT0 Enable interrupt line 0 0 1 read-write EINT1 Enable interrupt line 1 1 1 read-write RXGFC RXGFC FDCAN global filter configuration register 0x80 0x20 0x00000000 0xFFFFFFFF RRFE Reject remote frames extended These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 1 read-write RRFS Reject remote frames standard These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 1 1 read-write ANFE Accept non-matching frames extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 2 2 read-write ANFS Accept Non-matching frames standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 4 2 read-write F1OM FIFO 1 operation mode (overwrite or blocking) This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 8 1 read-write F0OM FIFO 0 operation mode (overwrite or blocking) This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 9 1 read-write LSS List size standard 28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 16 5 read-write LSE List size extended 8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 24 4 read-write XIDAM XIDAM FDCAN extended ID and mask register 0x84 0x20 0x1FFFFFFF 0xFFFFFFFF EIDM Extended ID mask For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 29 read-write HPMS HPMS FDCAN high-priority message status register 0x88 0x20 0x00000000 0xFFFFFFFF BIDX Buffer index Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1. 0 3 read-only MSI Message storage indicator 6 2 read-only FIDX Filter index Index of matching filter element. Range is 0 to RXGFC[LSS] - 1 or RXGFC[LSE] - 1. 8 5 read-only FLST Filter list Indicates the filter list of the matching filter element. 15 1 read-only RXF0S RXF0S FDCAN Rx FIFO 0 status register 0x90 0x20 0x00000000 0xFFFFFFFF F0FL Rx FIFO 0 fill level Number of elements stored in Rx FIFO 0, range 0 to 3. 0 4 read-only F0GI Rx FIFO 0 get index Rx FIFO 0 read index pointer, range 0 to 2. 8 2 read-only F0PI Rx FIFO 0 put index Rx FIFO 0 write index pointer, range 0 to 2. 16 2 read-only F0F Rx FIFO 0 full 24 1 read-only RF0L Rx FIFO 0 message lost This bit is a copy of interrupt flag IR[RF0L]. When IR[RF0L] is reset, this bit is also reset. 25 1 read-only RXF0A RXF0A CAN Rx FIFO 0 acknowledge register 0x94 0x20 0x00000000 0xFFFFFFFF F0AI Rx FIFO 0 acknowledge index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This sets the Rx FIFO 0 get index RXF0S[F0GI] to F0AI + 1 and update the FIFO 0 fill level RXF0S[F0FL]. 0 3 read-write RXF1S RXF1S FDCAN Rx FIFO 1 status register 0x98 0x20 0x00000000 0xFFFFFFFF F1FL Rx FIFO 1 fill level Number of elements stored in Rx FIFO 1, range 0 to 3. 0 4 read-only F1GI Rx FIFO 1 get index Rx FIFO 1 read index pointer, range 0 to 2. 8 2 read-only F1PI Rx FIFO 1 put index Rx FIFO 1 write index pointer, range 0 to 2. 16 2 read-only F1F Rx FIFO 1 full 24 1 read-only RF1L Rx FIFO 1 message lost This bit is a copy of interrupt flag IR[RF1L]. When IR[RF1L] is reset, this bit is also reset. 25 1 read-only RXF1A RXF1A FDCAN Rx FIFO 1 acknowledge register 0x9C 0x20 0x00000000 0xFFFFFFFF F1AI Rx FIFO 1 acknowledge index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This sets the Rx FIFO 1 get index RXF1S[F1GI] to F1AI + 1 and update the FIFO 1 Fill Level RXF1S[F1FL]. 0 3 read-write TXBC TXBC FDCAN Tx buffer configuration register 0xC0 0x20 0x00000000 0xFFFFFFFF TFQM Tx FIFO/queue mode This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 24 1 read-write TXFQS TXFQS FDCAN Tx FIFO/queue status register 0xC4 0x20 0x00000003 0xFFFFFFFF TFFL Tx FIFO free level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC[TFQM] = 1). 0 3 read-only TFGI Tx FIFO get index Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC.TFQM = 1) 8 2 read-only TFQPI Tx FIFO/queue put index Tx FIFO/queue write index pointer, range 0 to 3 16 2 read-only TFQF Tx FIFO/queue full 21 1 read-only TXBRP TXBRP FDCAN Tx buffer request pending register 0xC8 0x20 0x00000000 0xFFFFFFFF TRP Transmission request pending Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0 3 read-only TXBAR TXBAR FDCAN Tx buffer add request register 0xCC 0x20 0x00000000 0xFFFFFFFF AR Add request Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0 3 read-write TXBCR TXBCR FDCAN Tx buffer cancellation request register 0xD0 0x20 0x00000000 0xFFFFFFFF CR Cancellation request Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset. 0 3 read-write TXBTO TXBTO FDCAN Tx buffer transmission occurred register 0xD4 0x20 0x00000000 0xFFFFFFFF TO Transmission occurred. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR. 0 3 read-only TXBCF TXBCF FDCAN Tx buffer cancellation finished register 0xD8 0x20 0x00000000 0xFFFFFFFF CF Cancellation finished Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR. 0 3 read-only TXBTIE TXBTIE FDCAN Tx buffer transmission interrupt enable register 0xDC 0x20 0x00000000 0xFFFFFFFF TIE Transmission interrupt enable Each Tx buffer has its own TIE bit. 0 3 read-write TXBCIE TXBCIE FDCAN Tx buffer cancellation finished interrupt enable register 0xE0 0x20 0x00000000 0xFFFFFFFF CFIE Cancellation finished interrupt enable. Each Tx buffer has its own CFIE bit. 0 3 read-write TXEFS TXEFS FDCAN Tx event FIFO status register 0xE4 0x20 0x00000000 0xFFFFFFFF EFFL Event FIFO fill level Number of elements stored in Tx event FIFO, range 0 to 3. 0 3 read-only EFGI Event FIFO get index Tx event FIFO read index pointer, range 0 to 3. 8 2 read-only EFPI Event FIFO put index Tx event FIFO write index pointer, range 0 to 3. 16 2 read-only EFF Event FIFO full 24 1 read-only TEFL Tx event FIFO element lost This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset. 0 No Tx event FIFO element lost 1 Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0. 25 1 read-only TXEFA TXEFA FDCAN Tx event FIFO acknowledge register 0xE8 0x20 0x00000000 0xFFFFFFFF EFAI Event FIFO acknowledge index After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS[EFGI] to EFAI + 1 and updates the FIFO 0 fill level TXEFS[EFFL]. 0 2 read-write CKDIV CKDIV FDCAN CFG clock divider register 0x100 0x20 0x00000000 0xFFFFFFFF PDIV input clock divider The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 4 read-write FLASH FLASH address block description FLASH 0x40022000 0x0 0x400 registers FLASH FLASH non-secure global interrupt 6 ACR ACR FLASH access control register 0x0 0x20 0x00000013 0xFFFFFFFF LATENCY Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. ... Note: No check is performed by hardware to verify that the configuration is correct. 0 4 read-write WRHIGHFREQ Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to for details. Note: No check is performed to verify that the configuration is correct. Two WRHIGHFREQ values can be selected for some frequencies. 4 2 read-write PRFTEN Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account. Bits used to control the prefetch. 8 1 read-write S_PRFTEN Smart prefetch enable. When bit value is modified, user must read back ACR register to be sure S_PRFTEN has been taken into account. Bits used to control the prefetch functionality. 9 1 read-write NSKEYR NSKEYR FLASH key register 0x4 0x20 0x00000000 0xFFFFFFFF NSKEY Non-volatile memory configuration access unlock key 0 32 write-only OPTKEYR OPTKEYR FLASH option key register 0xC 0x20 0x00000000 0xFFFFFFFF OPTKEY FLASH option bytes control access unlock key 0 32 write-only OPSR OPSR FLASH operation status register 0x18 0x20 0x00000000 0x00000000 ADDR_OP Interrupted operation address. 0 20 read-only BK_OP Interrupted operation bank It indicates which bank was concerned by operation. 22 1 read-only SYSF_OP Operation in system Flash memory interrupted Indicates that reset interrupted an ongoing operation in System Flash. 23 1 read-only OTP_OP OTP operation interrupted Indicates that reset interrupted an ongoing operation in OTP area. 24 1 read-only CODE_OP Flash memory operation code 29 3 read-only OPTCR OPTCR FLASH option control register 0x1C 0x20 0x00000001 0x0FFFFFFF OPTLOCK FLASH_OPTCR lock option configuration bit The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset. It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change. 0 1 read-write OPTSTRT Option byte start change option configuration bit OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It's set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It's reseted at the same time as BSY bit. The user application cannot modify any FLASH_XXX_PRG embedded Flash memory register until the option change operation has been completed. Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in non-volatile memory. 1 1 read-write SWAP_BANK Bank swapping option configuration bit SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR. 31 1 read-only NSSR NSSR FLASH non-secure status register 0x20 0x20 0x00000000 0xFFFFFFF0 BSY busy flag BSY flag indicates that a Flash memory is busy by an operation (write, erase, option byte change). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs. 0 1 read-only WBNE write buffer not empty flag WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_NSCR the embedded Flash memory detects an error that involves data loss This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. 1 1 read-only DBNE data buffer not empty flag DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. 3 1 read-only EOP end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register. 16 1 read-only WRPERR write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR. 17 1 read-only PGSERR programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR. 18 1 read-only STRBERR strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR. 19 1 read-only INCERR inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears INCERR. 20 1 read-only OPTCHANGEERR Option byte change error flag OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1. Writing 1 to CLR_OPTCHANGEERR of register FLASH_CCR clears OPTCHANGEERR. Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set. 23 1 read-only SECSR SECSR FLASH secure status register 0x24 0x20 0x00000000 0xFFFFFFF0 SECBSY busy flag BSY flag indicates that a FLASH memory is busy by an operation (write, erase, option byte change, OBK operations, PUF operation). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs. 0 1 read-only SECWBNE write buffer not empty flag WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_SECCR the embedded Flash memory detects an error that involves data loss This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. 1 1 read-only SECDBNE data buffer not empty flag DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. 3 1 read-only SECEOP end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register. 16 1 read-only SECWRPERR write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR. 17 1 read-only SECPGSERR programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR. 18 1 read-only SECSTRBERR strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR. 19 1 read-only SECINCERR inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR. 20 1 read-only NSCR NSCR FLASH Non Secure control register 0x28 0x20 0x00000001 0xFFFFFFFF LOCK configuration lock bit This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change. 0 1 read-write PG programming control bit PG can be programmed only when LOCK is cleared to 0. PG allows programming in Bank1 and Bank2. 1 1 read-write SER sector erase request Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. 2 1 read-write BER erase request Setting BER bit to 1 requests a bank erase operation (user Flash memory only). BER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. Note: Write protection error is triggered when a bank erase is required and some sectors are protected. 3 1 read-write FW write forcing control bit FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively). Since there is just one write buffer, FW can force a write in bank1 or bank2. 4 1 read-write STRT erase start control bit STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software. 5 1 read-write SNB sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0. ... 6 3 read-write MER Mass erase request Setting MER bit to 1 requests a mass erase operation (user Flash memory only). MER can be programmed only when LOCK is cleared to 0. If BER or SER are both set, a PGSERR is raised. Error is triggered when a mass erase is required and some sectors are protected. 15 1 read-write EOPIE end of operation interrupt control bit Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0. 16 1 read-write WRPERRIE write protection error interrupt enable bit When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0. 17 1 read-write PGSERRIE programming sequence error interrupt enable bit When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0. 18 1 read-write STRBERRIE strobe error interrupt enable bit When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0. 19 1 read-write INCERRIE inconsistency error interrupt enable bit When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0. 20 1 read-write OPTCHANGEERRIE Option byte change error interrupt enable bit OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs during an option byte change. This bit can be programmed only when LOCK bit is cleared to 0. 23 1 read-write BKSEL Bank selector bit BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored. 31 1 read-write NSCCR NSCCR FLASH non-secure clear control register 0x30 0x20 0x00000000 0xFFFFFFFF CLR_EOP EOP flag clear bit Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register. 16 1 write-only CLR_WRPERR WRPERR flag clear bit Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register. 17 1 write-only CLR_PGSERR PGSERR flag clear bit Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register. 18 1 write-only CLR_STRBERR STRBERR flag clear bit Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register. 19 1 write-only CLR_INCERR INCERR flag clear bit Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register. 20 1 write-only CLR_OPTCHANGEERR Clear the flag corresponding flag in FLASH_NSSR by writing this bit. 23 1 write-only PRIVCFGR PRIVCFGR FLASH privilege configuration register 0x3C 0x20 0x00000000 0xFFFFFFFF NSPRIV privilege attribute for non secure registers 1 1 write-only HDPEXTR HDPEXTR FLASH HDP extension register 0x48 0x20 0x00000000 0xFFFFFFFF HDP1_EXT HDP area extension in 8 Kbytes sectors in Bank1. Extension is added after the HDP1_END sector. 0 3 read-write HDP2_EXT HDP area extension in 8 Kbytes sectors in Bank2. Extension is added after the HDP2_END sector. 16 3 read-write OPTSR_CUR OPTSR_CUR FLASH option status register 0x50 0x20 0x00000000 0x00000000 BOR_LEV Brownout level option status bit These bits reflects the power level that generates a system reset. 0 2 read-only BORH_EN Brownout high enable status bit 2 1 read-only IWDG_SW IWDG control mode option status bit 3 1 read-only WWDG_SW WWDG control mode option status bit 4 1 read-only NRST_SHDW Core domain Shutdown entry reset option status bit 5 1 read-only NRST_STOP Core domain Stop entry reset option status bit 6 1 read-only NRST_STDBY Core domain Standby entry reset option status bit 7 1 read-only PRODUCT_STATE Life state code (based on Hamming 8,4). More information in . 8 8 read-only IO_VDD_HSLV High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V. 16 1 read-only IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V. 17 1 read-only IWDG_STOP IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode. 20 1 read-only IWDG_STDBY IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode. 21 1 read-only SWAP_BANK Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset. 31 1 read-only OPTSR_PRG OPTSR_PRG FLASH option status register 0x54 0x20 0x00000000 0x00000000 BOR_LEV Brownout level option configuration bit These bits reflects the power level that generates a system reset. 0 2 read-write BORH_EN Brownout high enable configuration bit 2 1 read-write IWDG_SW IWDG control mode option configuration bit 3 1 read-write WWDG_SW WWDG control mode option configuration bit 4 1 read-write NRST_SHDW Core domain Shutdown entry reset option configuration bit 5 1 read-write NRST_STOP Core domain Stop entry reset option configuration bit 6 1 read-write NRST_STDBY Core domain Standby entry reset option configuration bit 7 1 read-write PRODUCT_STATE Life state code (based on Hamming 8,4). More information in . 8 8 read-write IO_VDD_HSLV High-speed IO at low VDD voltage configuration bit. This bit can be set only with VDD below 2.5 V. 16 1 read-write IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit. This bit can be set only with VDDIO2 below 2.5 V. 17 1 read-write IWDG_STOP IWDG Stop mode freeze option configuration bit When set the independent watchdog IWDG is in system Stop mode. 20 1 read-write IWDG_STDBY IWDG Standby mode freeze option configuration bit When set the independent watchdog IWDG is frozen in system Standby mode. 21 1 read-write SWAP_BANK Bank swapping option configuration bit SWAP_BANK option bit is used to configure whether the Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register after a reset. 31 1 read-write OPTSR2_CUR OPTSR2_CUR FLASH option status register 2 0x70 0x20 0x00000000 0x00000000 SRAM2_RST SRAM2 erase when system reset 3 1 read-only BKPRAM_ECC Backup RAM ECC detection and correction disable 4 1 read-only SRAM2_ECC SRAM2 ECC detection and correction disable 6 1 read-only SRAM1_RST SRAM1 erase upon system reset 9 1 read-only SRAM1_ECC SRAM1 ECC detection and correction disable 10 1 read-only OPTSR2_PRG OPTSR2_PRG FLASH option status register 2 0x74 0x20 0x00000000 0x00000000 SRAM2_RST SRAM2 erase when system reset 3 1 read-write BKPRAM_ECC Backup RAM ECC detection and correction disable 4 1 read-write SRAM2_ECC SRAM2 ECC detection and correction disable 6 1 read-write SRAM1_RST SRAM1 erase upon system reset 9 1 read-write SRAM1_ECC SRAM1 ECC detection and correction disable 10 1 read-write NSBOOTR_CUR NSBOOTR_CUR FLASH non-secure unique boot entry register 0x80 0x20 0x00000000 0x00000000 NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings. 0 8 read-only NSBOOTADD unique boot entry address These bits reflect the UBE address 8 24 read-only NSBOOTR_PRG NSBOOTR_PRG FLASH non-secure unique boot entry address 0x84 0x20 0x00000000 0x00000000 NSBOOT_LOCK A field locking the values of SWAP_BANK, and NSBOOTADD settings. 0 8 read-write NSBOOTADD Unique boot entry address These bits allow configuring the BOOT address 8 24 read-write OTPBLR_CUR OTPBLR_CUR FLASH non-secure OTP block lock 0x90 0x20 0x00000000 0x00000000 LOCKBL OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it's not possible to remove the write protection. Also if not locked, it is not possible to erase OTP words. 0 32 read-only OTPBLR_PRG OTPBLR_PRG FLASH non-secure OTP block lock 0x94 0x20 0x00000000 0x00000000 LOCKBL OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it is not possible to remove the write protection. LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared. 0 32 read-write PRIVBB1R PRIVBB1R FLASH privilege register for bank 1 0xC0 0x20 0x00000000 0xFFFFFFFF PRIVBB1 Privileged / unprivileged 8 Kbytes Flash Bank1 sector attribute (y = 0 to 7) 0 8 read-write WRPSGN1R_CUR WRPSGN1R_CUR FLASH write sector protection for Bank1 0xE8 0x20 0x00000000 0x00000000 WRPSG1 Bank1 sector protection option status byte Setting WRPSG1 bits to 0 write protects the corresponding sectors in bank 1 (0: write protected; 1: not write protected) 0 8 read-only WRPSGN1R_PRG WRPSGN1R_PRG FLASH write sector protection for Bank1 0xEC 0x20 0x00000000 0x00000000 WRPSG1 Bank1 sector protection option status byte Setting WRPSG1 bits to 0 write protects the corresponding sectors in bank 1 (0: write protected; 1: not write protected) 0 8 read-write HDP1R_CUR HDP1R_CUR FLASH HDP Bank1 register 0xF8 0x20 0x00000000 0x00000000 HDP1_STRT HDPL barrier start set in number of 8 Kbytes sectors 0 3 read-only HDP1_END HDPL barrier end set in number of 8 Kbytes sectors 16 3 read-only HDP1R_PRG HDP1R_PRG FLASH HDP Bank1 register 0xFC 0x20 0x00000000 0x00000000 HDP1_STRT Bank 1 HDPL barrier start set in number of 8 Kbytes sectors 0 3 read-only HDP1_END Bank 1 HDPL barrier end set in number of 8 Kbytes sectors 16 3 read-only ECCCORR ECCCORR FLASH Flash ECC correction register 0x100 0x20 0x00000000 0xFFFFFFFF ADDR_ECC ECC error address When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area). 0 16 read-only BK_ECC ECC bank flag for corrected ECC error It indicates which bank is concerned by ECC error 22 1 read-only SYSF_ECC ECC flag for corrected ECC error in system FLASH It indicates if system Flash memory is concerned by ECC error. 23 1 read-only OTP_ECC OTP ECC error bit This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield. 24 1 read-only ECCCIE ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation. 25 1 read-write ECCC ECC correction set by hardware when single ECC error has been detected and corrected. Cleared by writing 1. 30 1 read-write ECCDETR ECCDETR FLASH ECC detection register 0x104 0x20 0x00000000 0xFFFFFFFF ADDR_ECC ECC error address When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved. The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area). 0 16 read-only BK_ECC ECC fail bank for double ECC Error It indicates which bank is concerned by ECC error 22 1 read-only SYSF_ECC ECC fail for double ECC error in system Flash memory It indicates if system Flash memory is concerned by ECC error. 23 1 read-only OTP_ECC OTP ECC error bit This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bit field. 24 1 read-only ECCD ECC detection set by hardware when two ECC error has been detected. When this bit is set, a NMI is generated. Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors. 31 1 read-write ECCDR ECCDR FLASH ECC data 0x108 0x20 0x00000000 0xFFFFFFFF DATA_ECC ECC error data When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit of data (data area, read-only/OTP area), the failing data is read to this register. By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory. 0 16 read-only WRPSGN2R_CUR WRPSGN2R_CUR FLASH write sector protection for Bank2 0x1E8 0x20 0x00000000 0x00000000 WRPSG2 Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected) 0 8 read-only WRPSGN2R_PRG WRPSGN2R_PRG FLASH write sector protection for Bank2 0x1EC 0x20 0x00000000 0x00000000 WRPSG2 Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected) 0 8 read-write HDP2R_CUR HDP2R_CUR FLASH HDP Bank2 register 0x1F8 0x20 0x00000000 0x00000000 HDP2_STRT Bank 2 HDPL barrier start set in number of 8 Kbytes sectors 0 3 read-only HDP2_END Bank 2 HDPL barrier end set in number of 8 Kbytes sectors 16 3 read-only HDP2R_PRG HDP2R_PRG FLASH HDP Bank2 register 0x1FC 0x20 0x00000000 0x00000000 HDP2_STRT Bank 2 HDPL barrier start set in number of 8 Kbytes sectors 0 3 read-write HDP2_END Bank 2 HDPL barrier end set in number of 8 Kbytes sectors 16 3 read-write GPIOA General-purpose I/Os GPIO 0x42020000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xABFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x64000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 0x00000000 0xFFFF0000 16 0x1 0-15 ID%s Port input data pin %s 0 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 OD%s Port output data pin %s 0 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 BS%s Port x set pin %s 0 1 write-only BitSet Set Sets the corresponding ODx bit 1 16 0x1 0-15 BR%s Port x reset pin %s 16 1 write-only BitReset Reset Resets the corresponding ODx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the LOCK. After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 AFSEL%s Alternate function selection for port x I/O pin y (y = 7 to 0) These bits are written by software to configure alternate function I/Os. Note: The bitfield is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 AFSEL%s Alternate function selection for port x I/O pin y (y = 15 to 8) These bits are written by software to configure alternate function I/Os. Note: The bitfield is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 4 read-write BRR BRR GPIO port bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 BR%s Port x reset pin %s 0 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 HSLV%s Port x high-speed low-voltage configuration (y = 15 to 0) These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write HighSpeedLowVoltage Disabled I/O speed optimization disabled 0 Enabled I/O speed optimization enabled 1 GPIOB General-purpose I/Os GPIO 0x42020400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xABFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x64000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C GPIOC General-purpose I/Os GPIO 0x42020800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xABFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x64000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C GPIOD 0x42020C00 GPIOH General-purpose I/Os GPIO 0x42021C00 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xABFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x64000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HSLVR HSLVR GPIO high-speed low-voltage register 0x2C GTZC1 Global privilege controller GTZC 0x40032400 0x0 0x800 registers TZSC_PRIVCFGR1 TZSC_PRIVCFGR1 GTZC1 TZSC privilege configuration register 1 0x20 0x20 0x00000000 0xFFFFFFFF TIM2PRIV privileged access mode for TIM2 0 1 read-write TIM3PRIV privileged access mode for TIM3 1 1 read-write TIM6PRIV privileged access mode for TIM6 4 1 read-write TIM7PRIV privileged access mode for TIM7 5 1 read-write WWDGPRIV privileged access mode for WWDG 9 1 read-write IWDGPRIV privileged access mode for IWDG 10 1 read-write SPI2PRIV privileged access mode for SPI2 11 1 read-write SPI3PRIV privileged access mode for SPI3 12 1 read-write USART2PRIV privileged access mode for USART2 13 1 read-write USART3PRIV privileged access mode for USART3 14 1 read-write I2C1PRIV privileged access mode for I2C1 17 1 read-write I2C2PRIV privileged access mode for I2C2 18 1 read-write I3C1PRIV privileged access mode for I3C1 19 1 read-write CRSPRIV privileged access mode for CRS 20 1 read-write DAC1PRIV privileged access mode for DAC1 25 1 read-write DTSPRIV privileged access mode for DTS 30 1 read-write LPTIM2PRIV privileged access mode for LPTIM2 31 1 read-write TZSC_PRIVCFGR2 TZSC_PRIVCFGR2 GTZC1 TZSC privilege configuration register 2 0x24 0x20 0x00000000 0xFFFFFFFF FDCAN1PRIV privileged access mode for FDCAN1 0 1 read-write OPAMPPRIV privileged access mode for OPAMP 3 1 read-write COMPPRIV privileged access mode for COMP 4 1 read-write TIM1PRIV privileged access mode for TIM1 8 1 read-write SPI1PRIV privileged access mode for SPI1 9 1 read-write USART1PRIV privileged access mode for USART1 11 1 read-write USBFSPRIV privileged access mode for USBSF 19 1 read-write LPUART1PRIV privileged access mode for LPUART 25 1 read-write LPTIM1PRIV privileged access mode for LPTIM1 28 1 read-write TZSC_PRIVCFGR3 TZSC_PRIVCFGR3 GTZC1 TZSC privilege configuration register 3 0x28 0x20 0x00000000 0xFFFFFFFF I3C2PRIV privileged access mode for I3C2 2 1 read-write CRCPRIV privileged access mode for CRC 8 1 read-write ICACHEPRIV privileged access mode for ICACHE 12 1 read-write ADC1PRIV privileged access mode for ADC1 14 1 read-write HASHPRIV privileged access mode for HASH 17 1 read-write RNGPRIV privileged access mode for RNG 18 1 read-write RAMCFGPRIV privileged access mode for RAMSCFG 26 1 read-write TZSC_MPCWM4ACFGR TZSC_MPCWM4ACFGR GTZC1 TZSC BKPSRAM sub-region A watermark configuration register 0x70 0x20 0x00000000 0xFFFFFFFF SREN Sub-region z enable 0 1 read-write SRLOCK Sub-region z lock This bit, once set, can be cleared only by a system reset. 1 1 read-write PRIV Privileged sub-region z This bit is taken into account only if SREN is set. 9 1 read-write TZSC_MPCWM4AR TZSC_MPCWM4AR GTZC1 TZSC BKPSRAM sub-region A watermark register 0x74 0x20 0x08000000 0xFFFFFFFF SUBA_START Start of sub-region A This field defines the address offset of the sub-region A, to be multiplied by the granularity defined in Table 16. 0 11 read-write SUBA_LENGTH Length of sub-region A This field defines the length of the sub-region A, to be multiplied by the granularity defined in Table 16. When SUBA_START + SUBA_LENGTH is higher than the maximum size allowed for the memory, a saturation of SUBA_LENGTH is applied automatically. If SUBA_LENGTH = 0, the sub-region A is disabled (SREN bit in GTZC1_TZSC_MPCMWACFGR is cleared). 16 12 read-write TZSC_MPCWM4BCFGR TZSC_MPCWM4BCFGR GTZC1 TZSC BKPSRAM sub-region B watermark configuration register 0x78 0x20 0x00000000 0xFFFFFFFF SREN Sub-region z enable 0 1 read-write SRLOCK Sub-region z lock This bit, once set, can be cleared only by a system reset. 1 1 read-write PRIV Privileged sub-region z This bit is taken into account only if SREN is set. 9 1 read-write TZSC_MPCWM4BR TZSC_MPCWM4BR GTZC1 TZSC BKPSRAM sub-region B watermark register 0x7C 0x20 0x08000000 0xFFFFFFFF SUBB_START Start of sub-region B This field defines the address offset of the sub-region B, to be multiplied by the granularity defined in Table 16. 0 11 read-write SUBB_LENGTH Length of sub-region B This field defines the length of the sub-region B, to be multiplied by the granularity defined in Table 16. When SUBB_START + SUBB_LENGTH is higher than the maximum size allowed for the memory, a saturation of SUBB_LENGTH is applied automatically. If SUBB_LENGTH = 0, the sub-region B is disabled (SREN bit in GTZC1_TZSC_MPCMWBCFGR is cleared). 16 12 read-write 32 0x4 0-31 MPCBB1_PRIVCFGR%s MPCBB1_PRIVCFGR%s SRAM1 MPCBB privileged configuration for super-block %s register 0x200 0x20 0x00000000 0xFFFFFFFF 32 0x1 0-31 PRIV%s Privileged configuration for block y, belonging to super-block x (y = 31 to 0). 0 1 read-write 32 0x4 0-31 MPCBB2_PRIVCFGR%s MPCBB2_PRIVCFGR%s SRAM2 MPCBB privileged configuration for super-block %s register 0x600 0x20 0x00000000 0xFFFFFFFF 32 0x1 0-31 PRIV%s Privileged configuration for block y, belonging to super-block x (y = 31 to 0). 0 1 read-write GPDMA1 General purpose direct memory access controller GPDMA 0x40020000 0x0 0x1000 registers GPDMA1_CH0 GPDMA1 channel 0 global interrupt 27 GPDMA1_CH1 GPDMA1 channel 1 global interrupt 28 GPDMA1_CH2 GPDMA1 channel 2 global interrupt 29 GPDMA1_CH3 GPDMA1 channel 3 global interrupt 30 GPDMA1_CH4 GPDMA1 channel 4 global interrupt 31 GPDMA1_CH5 GPDMA1 channel 5 global interrupt 32 GPDMA1_CH6 GPDMA1 channel 6 global interrupt 33 GPDMA1_CH7 GPDMA1 channel 7 global interrupt 34 PRIVCFGR PRIVCFGR GPDMA privileged configuration register 0x4 0x20 0x00000000 0xFFFFFFFF 8 0x1 0-7 PRIV%s privileged state of channel x 0 1 read-write PRIV0 Unprivileged Channel is unprivileged 0 Privileged Channel is privileged 1 MISR MISR GPDMA masked interrupt status register 0xC 0x20 0x00000000 0xFFFFFFFF 8 0x1 0-7 MIS%s masked interrupt status of channel x 0 1 read-only MIS0R NoTrigger No interrupt has occurred on channel 0 Trigger An interrupt has occurred on channel 1 6 0x80 0-5 CH%s Channel cluster 0x50 LBAR C0LBAR GPDMA channel 0 linked-list base address register 0x0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write 0 65535 FCR C0FCR GPDMA channel 0 flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only TCFW Clear Clear flag 1 HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only SR C0SR GPDMA channel 0 status register 0x10 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag This idle flag is deasserted by hardware when the channel is enabled (GPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). 0 1 read-only IDLEFR NoTrigger Event not triggered 0 Trigger Event triggered 1 TCF transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]). 8 1 read-only HTF half transfer flag A half transfer event is either a half block transfer or a half 2D/repeated block transfer, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]). A half block transfer occurs when half of the bytes of the source block size (rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. A half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2)) has been transferred to the destination. 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (see GPDMA_CxTR1.DDW_LOG2[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (GPDMA_CxSR.SUSPF = 1). 16 8 read-only 0 255 CR C0CR GPDMA channel 0 control register 0x14 0x20 0x00000000 0xFFFFFFFF EN enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is deasserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, for example if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 read-write EN Disabled Channel disabled 0 Enabled Channel enabled 1 RESET reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (GPDMA_CxSR.SUSPF = 1 and GPDMA_CxSR.IDLEF = GPDMA_CxCR.EN = 1) - channel in disabled state (GPDMA_CxSR.IDLEF = 1 and GPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR) before enabling again the channel (see the programming sequence in Figure 44). 1 1 write-only RESETW Reset Reset channel 1 SUSP suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel (channel with an ongoing GPDMA transfer over its master ports). The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in Figure 43. 2 1 read-write SUSP NotSuspended Channel operation not suspended 0 Suspended Channel operation suspended 1 TCIE transfer complete interrupt enable 8 1 read-write TCIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until GPDMA_CxBR1.BNDT[15:0] = 0 and GPDMA_CxBR1.BRC[10:0] = 0. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 read-write LSM FullLinkedList Channel executed for full linked list 0 Once Channel executed once for current linked list 1 LAP linked-list allocated port This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 read-write LAP Port0 Port 0 (AHB) allocated 0 Port1 Port 1 (AHB) allocated 1 PRIO priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 22 2 read-write PRIO LowPrioLowWeight Low priority, low weight 0 LowPrioMidWeight Low priority, mid weight 1 LowPrioHighWeight Low priority, high weight 2 HighPrio High priority 3 TR1 C0TR1 GPDMA channel 0 transfer register 1 0x40 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (GPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. Note: A source burst transfer must have an aligned address with its data width (start address GPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. 0 2 read-write SDW_LOG2R read Byte Byte 0 HalfWord Half-word (2 bytes) 1 Word Word (4 bytes) 2 Error User setting error 3 SDW_LOG2W write Byte Byte 0 HalfWord Half-word (2 bytes) 1 Word Word (4 bytes) 2 SINC source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 read-write SINC FixedBurst Fixed burst 0 Contiguous Contiguously incremented burst 1 SBL_1 source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. Note: If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower singles/bursts, but the data integrity is guaranteed. 4 6 read-write 0 63 PAM padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else, in the following enumerated values, the condition PAM_1 is when destination data width is higher that source data width, and the condition PAM_2 is when destination data width is higher than source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination Note: If the transfer from the source peripheral is configured with peripheral flow-control mode (SWREQ = 0 and PFREQ = 1 and DREQ = 0), and if the destination data width the source data width, packing is not supported. 11 2 read-write 0 3 SBX source byte exchange within the unaligned half-word of each source word If the source data width is shorter than a word, this bit is ignored. If the source data width is a word: 13 1 read-write SBX NotExchanged No byte-based exchanged within word 0 Exchanged The two consecutive (post PAM) bytes are exchanged in each destination half-word 1 SAP source allocated port This bit is used to allocate the master port for the source transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 14 1 read-write SAP Port0 Port 0 (AHB) allocated 0 Port1 Port 1 (AHB) allocated 1 DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. Note: A destination burst transfer must have an aligned address with its data width (start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0], versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and no transfer is issued. 16 2 read-write read write DINC destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. Note: If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower singles/bursts, but the data integrity is guaranteed. 20 6 read-write 0 63 DBX destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte: 26 1 read-write DHX destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word: 27 1 read-write DHX NotExchanged No halfword-based exchange within word 0 Exchanged The two consecutive (post PAM) half-words are exchanged in each destination word 1 DAP destination allocated port This bit is used to allocate the master port for the destination transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 30 1 read-write TR2 C0TR2 GPDMA channel 0 transfer register 2 0x44 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per Section 14.3.4. The user must not assign a same input hardware request (same REQSEL[7:0] value) to different active GPDMA channels (GPDMA_CxCR.EN = 1 and GPDMA_CxTR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 8 read-write REQSEL ADC1_DMA adc1_dma selected 0 DAC1_CH1_DMA dac1_ch1_dma selected 2 DAC1_CH2_DMA dac1_ch2_dma selected 3 TIM6_UPD_DMA tim6_upd_dma selected 4 TIM7_UPD_DMA tim7_upd_dma selected 5 SPI1_RX_DMA spi1_rx_dma selected 6 SPI1_TX_DMA spi1_tx_dma selected 7 SPI2_RX_DMA spi2_rx_dma selected 8 SPI2_TX_DMA spi2_tx_dma selected 9 SPI3_RX_DMA spi3_rx_dma selected 10 SPI3_TX_DMA spi3_tx_dma selected 11 I2C1_RX_DMA i2c1_rx_dma selected 12 I2C1_TX_DMA i2c1_tx_dma selected 13 I2C2_RX_DMA i2c2_rx_dma selected 15 I2C2_TX_DMA i2c2_tx_dma selected 16 I2C3_RX_DMA i2c3_rx_dma selected 18 I2C3_TX_DMA i2c3_tx_dma selected 19 USART1_RX_DMA usart1_rx_dma selected 21 USART1_TX_DMA usart1_tx_dma selected 22 USART2_RX_DMA usart2_rx_dma selected 23 USART2_TX_DMA usart2_tx_dma selected 24 USART3_RX_DMA usart3_rx_dma selected 25 USART3_TX_DMA usart3_tx_dma selected 26 UART4_RX_DMA uart4_rx_dma selected 27 UART4_TX_DMA uart4_tx_dma selected 28 UART5_RX_DMA uart5_rx_dma selected 29 UART5_TX_DMA uart5_tx_dma selected 30 USART6_RX_DMA usart6_rx_dma selected 31 USART6_TX_DMA usart6_tx_dma selected 32 UART7_RX_DMA uart7_rx_dma selected 33 UART7_TX_DMA uart7_tx_dma selected 34 UART8_RX_DMA uart8_rx_dma selected 35 UART8_TX_DMA uart8_tx_dma selected 36 UART9_RX_DMA uart9_rx_dma selected 37 UART9_TX_DMA uart9_tx_dma selected 38 UART10_RX_DMA uart10_rx_dma selected 39 UART10_TX_DMA uart10_tx_dma selected 40 UART11_RX_DMA uart11_rx_dma selected 41 UART11_TX_DMA uart11_tx_dma selected 42 UART12_RX_DMA uart12_rx_dma selected 43 UART12_TX_DMA uart12_tx_dma selected 44 LPUART1_RX_DMA lpuart1_rx_dma selected 45 LPUART1_TX_DMA lpuart1_tx_dma selected 46 SPI4_RX_DMA spi4_rx_dma selected 47 SPI4_TX_DMA spi4_tx_dma selected 48 SPI5_RX_DMA spi5_rx_dma selected 49 SPI5_TX_DMA spi5_tx_dma selected 50 SPI6_RX_DMA spi6_rx_dma selected 51 SPI6_TX_DMA spi6_tx_dma selected 52 SAI1_A_DMA sai1_a_dma selected 53 SAI1_B_DMA sai1_b_dma selected 54 SAI2_A_DMA sai2_a_dma selected 55 SAI2_B_DMA sai2_b_dma selected 56 OSPI1_DMA ospi1_dma selected 57 TIM1_CC1_DMA tim1_cc1_dma selected 58 TIM1_CC2_DMA tim1_cc2_dma selected 59 TIM1_CC3_DMA tim1_cc3_dma selected 60 TIM1_CC4_DMA tim1_cc4_dma selected 61 TIM1_UPD_DMA tim1_upd_dma selected 62 TIM1_TRG_DMA tim1_trg_dma selected 63 TIM1_COM_DMA tim1_com_dma selected 64 TIM8_CC1_DMA tim8_cc1_dma selected 65 TIM8_CC2_DMA tim8_cc2_dma selected 66 TIM8_CC3_DMA tim8_cc3_dma selected 67 TIM8_CC4_DMA tim8_cc4_dma selected 68 TIM8_UPD_DMA tim8_upd_dma selected 69 TIM8_TIG_DMA tim8_tig_dma selected 70 TIM8_COM_DMA tim8_com_dma selected 71 TIM2_CC1_DMA tim2_cc1_dma selected 72 TIM2_CC2_DMA tim2_cc2_dma selected 73 TIM2_CC3_DMA tim2_cc3_dma selected 74 TIM2_CC4_DMA tim2_cc4_dma selected 75 TIM2_UPD_DMA tim2_upd_dma selected 76 TIM3_CC1_DMA tim3_cc1_dma selected 77 TIM3_CC2_DMA tim3_cc2_dma selected 78 TIM3_CC3_DMA tim3_cc3_dma selected 79 TIM3_CC4_DMA tim3_cc4_dma selected 80 TIM3_UPD_DMA tim3_upd_dma selected 81 TIM3_TRG_DMA tim3_trg_dma selected 82 TIM4_CC1_DMA tim4_cc1_dma selected 83 TIM4_CC2_DMA tim4_cc2_dma selected 84 TIM4_CC3_DMA tim4_cc3_dma selected 85 TIM4_CC4_DMA tim4_cc4_dma selected 86 TIM4_UPD_DMA tim4_upd_dma selected 87 TIM5_CC1_DMA tim5_cc1_dma selected 88 TIM5_CC2_DMA tim5_cc2_dma selected 89 TIM5_CC3_DMA tim5_cc3_dma selected 90 TIM5_CC4_DMA tim5_cc4_dma selected 91 TIM5_UPD_DMA tim5_upd_dma selected 92 TIM5_TRG_DMA tim5_trg_dma selected 93 TIM15_CC1_DMA tim15_cc1_dma selected 94 TIM15_UPD_DMA tim15_upd_dma selected 95 TIM15_TRG_DMA tim15_trg_dma selected 96 TIM15_COM_DMA tim15_com_dma selected 97 TIM16_CC1_DMA tim16_cc1_dma selected 98 TIM16_UPD_DMA tim16_upd_dma selected 99 TIM17_CC1_DMA tim17_cc1_dma selected 100 TIM17_UPD_DMA tim17_upd_dma selected 101 LPTIM1_IC1_DMA lptim1_ic1_dma selected 102 LPTIM1_IC2_DMA lptim1_ic2_dma selected 103 LPTIM1_UE_DMA lptim1_ue_dma selected 104 LPTIM2_IC1_DMA lptim2_ic1_dma selected 105 LPTIM2_IC2_DMA lptim2_ic2_dma selected 106 LPTIM2_UE_DMA lptim2_ue_dma selected 107 DCMI_PSSI_DMA dcmi_dma or pssi_dma(1) selected 108 AES_OUT_DMA aes_out_dma selected 109 AES_IN_DMA aes_in_dma selected 110 HASH_IN_DMA hash_in_dma selected 111 UCPD1_RX_DMA ucpd1_rx_dma selected 112 UCPD1_TX_DMA ucpd1_tx_dma selected 113 CORDIC_READ_DMA cordic_read_dma selected 114 CORDIC_WRITE_DMA cordic_write_dma selected 115 FMAC_READ_DMA fmac_read_dma selected 116 FMAC_WRITE_DMA fmac_write_dma selected 117 SAES_OUT_DMA saes_out_dma selected 118 SAES_IN_DMA saes_in_dma selected 119 I3C1_RX_DMA i3c1_rx_dma selected 120 I3C1_TX_DMA i3c1_tx_dma selected 121 I3C1_TC_DMA i3c1_tc_dma selected 122 I3C1_RS_DMA i3c1_rs_dma selected 123 I2C4_RX_DMA i2c4_rx_dma selected 124 I2C4_TX_DMA i2c4_tx_dma selected 125 LPTIM3_IC1_DMA lptim3_ic1_dma selected 127 LPTIM3_IC2_DMA lptim3_ic2_dma selected 128 LPTIM3_UE_DMA lptim3_ue_dma selected 129 LPTIM5_IC1_DMA lptim5_ic1_dma selected 130 LPTIM5_IC2_DMA lptim5_ic2_dma selected 131 LPTIM5_UE_DMA lptim5_ue_dma selected 132 LPTIM6_IC1_DMA lptim6_ic1_dma selected 133 LPTIM6_IC2_DMA lptim6_ic2_dma selected 134 LPTIM6_UE_DMA lptim6_ue_dma selected 135 I3C2_RX i3c2_rx selected 136 I3C2_TX i3c2_tx selected 137 I3C2_TC i3c2_tc selected 138 I3C2_RS i3c2_rs selected 139 SWREQ software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted. 9 1 read-write SWREQ Hardware No software request. The selected hardware request REQSEL[7:0] is taken into account 0 Software Software request for memory-to-memory transfer 1 DREQ destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note: If the channel x is activated (GPDMA_CxCR.EN is asserted) with SWREQ = 0 and PFREQ = 1 (peripheral hardware request with peripheral flow-control mode), any software assertion to this DREQ bit is ignored: in peripheral flow-control mode, only a peripheral-to-memory transfer is supported. 10 1 read-write DREQ Source Selected hardware request driven by a source peripheral 0 Destination Selected hardware request driven by a destination peripheral 1 BREQ Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: 11 1 read-write BREQ Burst The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level 0 Block The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level 1 PFREQ Hardware request in peripheral flow control mode Important: If a given channel x is not implemented with this feature, this bit is reserved and PFREQ is not present (see Section 14.3.2 for the list of the implemented channels with this feature. If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: Note: In peripheral flow control mode, there are the following restrictions: Note: - no 2D/repeated block support (GPDMA_CxBR1.BRC[10:0] must be set to 0) Note: - the peripheral must be set as the source of the transfer (DREQ = 0). Note: - data packing to a wider destination width is not supported (if destination width source data width, GPDMA_CxTR1.PAM[1] must be set to 0). Note: - GPDMA_CxBR1.BNDT[15:0] must be programmed as a multiple of the source (peripheral) burst size. 12 1 read-write PFREQ GpdmaControlMode The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode 0 PeripheralControlMode The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. 1 TRIGM trigger mode These bits define the transfer granularity for its conditioning by the trigger. 14 2 read-write TRIGM BlockLevel At block level: the first burst read of each block transfer is conditioned by one hit trigger 0 LinkLevel At link level: a LLI link transfer is conditioned by one hit trigger 2 ProgrammedBurstLevel At programmed burst level: programmed burst read is conditioned by one hit trigger. 3 TRIGSEL trigger event input selection These bits select the trigger event input of the GPDMA transfer (as per Section 14.3.7), with an active trigger event if TRIGPOL[1:0] different 00. 16 6 read-write TRIGSEL EXTI0 exti0 is trigger input 0 EXTI1 exti1 is trigger input 1 EXTI2 exti2 is trigger input 2 EXTI3 exti3 is trigger input 3 EXTI4 exti4 is trigger input 4 EXTI5 exti5 is trigger input 5 EXTI6 exti6 is trigger input 6 EXTI7 exti7 is trigger input 7 TAMP_TRG1 tamp_trg1 is trigger input 8 TAMP_TRG2 tamp_trg2 is trigger input 9 LPTIM1_CH1 lptim1_ch1 is trigger input 11 LPTIM1_CH2 lptim1_ch2 is trigger input 12 LPTIM2_CH1 lptim2_ch1 is trigger input 13 LPTIM2_CH2 lptim2_ch2 is trigger input 14 RTC_ALRA_TRG rtc_alra_trg is trigger input 15 RTC_ALRB_TRG rtc_alrb_trg is trigger input 16 RTC_WUT_TRG rtc_wut_trg is trigger input 17 GPDMA1_CH0_TC gpdma1_ch0_tc is trigger input 18 GPDMA1_CH1_TC gpdma1_ch1_tc is trigger input 19 GPDMA1_CH2_TC gpdma1_ch2_tc is trigger input 20 GPDMA1_CH3_TC gpdma1_ch3_tc is trigger input 21 GPDMA1_CH4_TC gpdma1_ch4_tc is trigger input 22 GPDMA1_CH5_TC gpdma1_ch5_tc is trigger input 23 GPDMA1_CH6_TC gpdma1_ch6_tc is trigger input 24 GPDMA1_CH7_TC gpdma1_ch7_tc is trigger input 25 GPDMA2_CH0_TC gpdma2_ch0_tc is trigger input 26 GPDMA2_CH1_TC gpdma2_ch1_tc is trigger input 27 GPDMA2_CH2_TC gpdma2_ch2_tc is trigger input 28 GPDMA2_CH3_TC gpdma2_ch3_tc is trigger input 29 GPDMA2_CH4_TC gpdma2_ch4_tc is trigger input 30 GPDMA2_CH5_TC gpdma2_ch5_tc is trigger input 31 GPDMA2_CH6_TC gpdma2_ch6_tc is trigger input 32 GPDMA2_CH7_TC gpdma2_ch7_tc is trigger input 33 TIM2_TRG0 tim2_trgo is trigger input 34 COMP1_OUT comp1_out is trigger input 44 TRIGPOL trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. 24 2 read-write TRIGPOL NoTrigger No trigger 0 RisingEdge Trigger on rising edge 1 FallingEdge Trigger on falling edge 2 TCEM transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI 0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI 0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI 0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI 1 . 30 2 read-write TCEM BlockLevel At block level: the complete (and the half) transfer event is generated at the (respectively half of the) end of a block 0 LliLevel At LLI level: the complete transfer event is generated at the end of the LLI transfer. The half transfer event is generated at the half of the LLI data transfer 2 ChannelLevel At channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI 3 BR1 C0BR1 GPDMA channel 0 block register 1 0x48 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: When configured in packing mode (GPDMA_CxTR1.PAM[1] = 1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 0 16 read-write 0 65535 SAR C0SAR GPDMA channel 0 source address register 0x4C 0x20 0x00000000 0xFFFFFFFF SA source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (GPDMA_CxTR1.SINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.SDW_LOG2[1:0]) after each burst source data, reflecting the next address from which data is read. During the channel activity, this address is updated after each completed source burst, consequently to: the programmed source burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.SINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.SBL_1[5:0] and GPDMA_CxTR1.SDW_LOG2[21:0] the additional source incremented/decremented offset value as programmed by GPDMA_CxBR1.SDEC and GPDMA_CxTR3.SAO[12:0]. once/if completed source block transfer, for a channel x with 2D addressing capability (x = 12 to 15). additional block repeat source incremented/decremented offset value as programmed by GPDMA_CxBR1.BRSDEC and GPDMA_CxBR2.BRSAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source burst (SA[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. 0 32 read-write 0 4294967295 DAR C0DAR GPDMA channel 0 destination address register 0x50 0x20 0x00000000 0xFFFFFFFF DA destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (GPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.DDW_LOG2[21:0]) after each burst destination data, reflecting the next address from which data is written. During the channel activity, this address is updated after each completed destination burst, consequently to: the programmed destination burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.DINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.DBL_1[5:0] and GPDMA_CxTR1.DDW_LOG2[1:0] the additional destination incremented/decremented offset value as programmed by GPDMA_CxBR1.DDEC and GPDMA_CxTR3.DAO[12:0]. once/if completed destination block transfer, for a channel x with 2D addressing capability (x = 12 to 15), the additional block repeat destination incremented/decremented offset value as programmed by GPDMA_CxBR1.BRDDEC and GPDMA_CxBR2.BRDAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by the GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination burst (DA[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 0 32 read-write 0 4294967295 LLR C0LLR GPDMA channel 0 linked-list address register 0x7C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. 2 14 read-write 0 16383 ULL Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer. 16 1 read-write ULL NoUpdate No CxLLR update 0 Update CxLLR updated from memory during link transfer 1 UDA Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer. 27 1 read-write UDA NoUpdate No CxDAR update 0 Update CxDAR updated from memory during link transfer 1 USA update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer. 28 1 read-write USA NoUpdate No CxSAR update 0 Update CxSAR updated from memory during link transfer 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if GPDMA_CxLLR different 0, the linked-list is not completed. GPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 29 1 read-write UB1 NoUpdate No CxBR1 update 0 Update CxBR1 updated from memory during link transfer 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer. 30 1 read-write UT2 NoUpdate No CxTR2 update 0 Update CxTR2 updated from memory during link transfer 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer. 31 1 read-write UT1 NoUpdate No CxTR1 update 0 Update CxTR1 updated from memory during link transfer 1 2 0x80 6-7 CH2D%s 2D-addressing channel cluster 0x350 LBAR C6LBAR GPDMA channel 6 linked-list base address register 0x0 FCR C6FCR GPDMA channel 6 flag clear register 0xC SR C6SR GPDMA channel 6 status register 0x10 CR C6CR GPDMA channel 6 control register 0x14 TR1 C6TR1 GPDMA channel 6 transfer register 1 0x40 TR2 C6TR2 GPDMA channel 6 transfer register 2 0x44 BR1 C6BR1 GPDMA channel 6 alternate block register 1 0x48 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] different 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: When configured in packing mode (GPDMA_CxTR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 0 16 read-write BRC Block repeat counter This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If GPDMA_CxLLR.UB1 = 1, all GPDMA_CxBR1 fields are updated by the next LLI in the memory. If GPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] different 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI and data transfer. 16 11 read-write 0 2047 SDEC source address decrement 28 1 read-write SDEC Increment Source address incremented 0 Decrement Source address decremented 1 DDEC destination address decrement 29 1 read-write DDEC Increment Destination address incremented 0 Decrement Destination address decremented 1 BRSDEC Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDEC), GPDMA_CxSAR is in the same time also updated by the increment/decrement (depending on SDEC) of the GPDMA_CxTR3.SAO value, as it is done after any programmed burst transfer. 30 1 read-write BRSDEC Increment Block repeat source address incremented 0 Decrement Block repeat source address decremented 1 BRDDEC Block repeat destination address decrement Note: On top of this increment/decrement (depending on BRDDEC), GPDMA_CxDAR is in the same time also updated by the increment/decrement (depending on DDEC) of the GPDMA_CxTR3.DAO value, as it is usually done at the end of each programmed burst transfer. 31 1 read-write BRDDEC Increment Block repeat destination address incremented 0 Decrement Block repeat destination address decremented 1 SAR C6SAR GPDMA channel 6 source address register 0x4C DAR C6DAR GPDMA channel 6 destination address register 0x50 TR3 C6TR3 GPDMA channel 6 transfer register 3 0x54 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (GPDMA_CxTR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. 0 13 read-write 0 4095 DAO destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (GPDMA_CxTR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 16 13 read-write 0 4095 BR2 C6BR2 GPDMA channel 6 block register 2 0x58 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (GPDMA_CxSAR) at the end of a block transfer. A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: BRSAO[15:0] must be set to 0 in peripheral flow-control mode (if GPDMA_CxTR2.PFREQ = 1). 0 16 read-write 0 65535 BRDAO Block repeated destination address offset For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (GPDMA_CxDAR) at the end of a block transfer. A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: BRDAO[15:0] must be set to 0 in peripheral flow-control mode (if GPDMA_CxTR2.PFREQ = 1). 16 16 read-write 0 65535 LLR C6LLR GPDMA channel 6 alternate linked-list address register 0x7C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. 2 14 read-write ULL Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer. 16 1 read-write UB2 Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during the link transfer. 25 1 read-write UB2 NoUpdate No CxBR2 update 0 Update CxBR2 updated from memory during link transfer 1 UT3 Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during the link transfer. 26 1 read-write UT3 NoUpdate No CxTR3 update 0 Update CxTR3 updated from memory during link transfer 1 UDA Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer. 27 1 read-write USA update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer. 28 1 read-write UB1 Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if GPDMA_CxLLR different 0, the linked-list is not completed. GPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 29 1 read-write UT2 Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer. 30 1 read-write UT1 Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer. 31 1 read-write GPDMA2 0x40021000 GPDMA2_CH0 GPDMA2 channel 0 global interrupt 90 GPDMA2_CH1 GPDMA2 channel 1 global interrupt 91 GPDMA2_CH2 GPDMA2 channel 2 global interrupt 92 GPDMA2_CH3 GPDMA2 channel 3 global interrupt 93 GPDMA2_CH4 GPDMA2 channel 4 global interrupt 94 GPDMA2_CH5 GPDMA2 channel 5 global interrupt 95 GPDMA2_CH6 GPDMA2 channel 6 global interrupt 96 GPDMA2_CH7 GPDMA2 channel 7 global interrupt 97 HASH Hash processor HASH 0x420C0400 0x0 0x400 registers HASH HASH interrupt 117 CR CR HASH control register 0x0 0x20 0x00000000 0xFFFFFFFF INIT Initialize message digest calculation Writing this bit to 1 resets the hash processor core, so that the HASH is ready to compute the message digest of a new message. Writing this bit to 0 has no effect. Reading this bit always returns 0. 2 1 read-write DMAE DMA enable After this bit is set, it is cleared by hardware while the last data of the message is written into the hash processor. Setting this bit to 0 while a DMA transfer is ongoing does not abort the current transfer. Instead, the DMA interface of the HASH remains internally enabled until the transfer is completed or INIT is written to 1. Setting INIT bit to 1 does not clear DMAE bit. 3 1 read-write DATATYPE Data type selection This bitfield defines the format of the data entered into the HASH_DIN register: 4 2 read-write MODE Mode selection This bit selects the normal or the keyed HMAC mode for the selected algorithm: This selection is only taken into account when the INIT bit is set. Changing this bit during a computation has no effect. 6 1 read-write NBW Number of words already pushed Refer to NBWP[3:0] bitfield of HASH_SR for a description of NBW[3:0] bitfield. This bit is read-only. 8 4 read-only DINNE DIN not empty Refer to DINNE bit of HASH_SR for a description of DINNE bit. This bit is read-only. 12 1 read-only MDMAT Multiple DMA transfers This bit is set when hashing large files when multiple DMA transfers are needed. 13 1 read-write LKEY Long key selection The application must set this bit if the HMAC key is greater than the block size (64 bytes) This selection is only taken into account when the INIT and MODE bits are set (HMAC mode selected). Changing this bit during a computation has no effect. 16 1 read-write ALGO Algorithm selection These bits select the hash algorithm: This selection is only taken into account when the INIT bit is set. Changing this bitfield during a computation has no effect. When the ALGO bitfield is updated and INIT bit is set, NBWE in HASH_SR is automatically updated to 0x11. 17 2 read-write DIN DIN HASH data input register 0x4 0x20 0x00000000 0xFFFFFFFF DATAIN Data input Writing this register pushes the current register content into the FIFO, and the register takes the new value presented on the AHB bus. Reading this register returns zeros. 0 32 write-only STR STR HASH start register 0x8 0x20 0x00000000 0xFFFFFFFF NBLW Number of valid bits in the last word When the last word of the message bit string is written to HASH_DIN register, the hash processor takes only the valid bits, specified as below, after internal data swapping: ... The above mechanism is valid only if DCAL = 0. If NBLW bits are written while DCAL is set to 1, the NBLW bitfield remains unchanged. In other words it is not possible to configure NBLW and set DCAL at the same time. Reading NBLW bits returns the last value written to NBLW. 0 5 read-write DCAL Digest calculation Writing this bit to 1 starts the message padding using the previously written value of NBLW, and starts the calculation of the final message digest with all the data words written to the input FIFO since the INIT bit was last written to 1. Reading this bit returns 0. 8 1 read-write HRA0 HRA0 HASH aliased digest register 0 0xC 0x20 0x00000000 0xFFFFFFFF H0 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HRA1 HRA1 HASH aliased digest register 1 0x10 0x20 0x00000000 0xFFFFFFFF H1 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HRA2 HRA2 HASH aliased digest register 2 0x14 0x20 0x00000000 0xFFFFFFFF H2 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HRA3 HRA3 HASH aliased digest register 3 0x18 0x20 0x00000000 0xFFFFFFFF H3 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HRA4 HRA4 HASH aliased digest register 4 0x1C 0x20 0x00000000 0xFFFFFFFF H4 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only IMR IMR HASH interrupt enable register 0x20 0x20 0x00000000 0xFFFFFFFF DINIE Data input interrupt enable 0 1 read-write DCIE Digest calculation completion interrupt enable 1 1 read-write SR SR HASH status register 0x24 0x20 0x00110001 0xFFFFFFFF DINIS Data input interrupt status This bit is set by hardware when the FIFO is ready to get a new block (16 locations are free). It is cleared by writing it to 0 or by writing the HASH_DIN register. When DINIS = 0, HASH_CSRx registers reads as zero. 0 1 read-write DCIS Digest calculation completion interrupt status This bit is set by hardware when a digest becomes ready (the whole message has been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1 in the HASH_CR register. 1 1 read-write DMAS DMA Status This bit provides information on the DMA interface activity. It is set with DMAE and cleared when DMAE = 0 and no DMA transfer is ongoing. No interrupt is associated with this bit. 2 1 read-only BUSY Busy bit 3 1 read-only NBWP Number of words already pushed This bitfield is the exact number of words in the message that have already been pushed into the FIFO. NBWP is incremented by 1 when a write access is performed to the HASH_DIN register. When a digest calculation starts, NBWP is updated to NBWP- block size (in words), and NBWP goes to zero when the INIT bit is written to 1. 9 5 read-only DINNE DIN not empty This bit is set when the HASH_DIN register holds valid data (that is after being written at least once). It is cleared when either the INIT bit (initialization) or the DCAL bit (completion of the previous message processing) is written to 1. 15 1 read-only NBWE Number of words expected This bitfield reflects the number of words in the message that must be pushed into the FIFO to trigger a partial computation. NBWE is decremented by 1 when a write access is performed to the HASH_DIN register. NBWE is set to the expected block size +1 in words (0x11) when INIT bit is set in HASH_CR. It is set to the expected block size (0x10) when the partial digest calculation ends. 16 5 read-only CSR0 CSR0 HASH context swap register 0 0xF8 0x20 0x00000000 0xFFFFFFFF CS0 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR1 CSR1 HASH context swap register 1 0xFC 0x20 0x00000000 0xFFFFFFFF CS1 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR2 CSR2 HASH context swap register 2 0x100 0x20 0x00000000 0xFFFFFFFF CS2 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR3 CSR3 HASH context swap register 3 0x104 0x20 0x00000000 0xFFFFFFFF CS3 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR4 CSR4 HASH context swap register 4 0x108 0x20 0x00000000 0xFFFFFFFF CS4 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR5 CSR5 HASH context swap register 5 0x10C 0x20 0x00000000 0xFFFFFFFF CS5 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR6 CSR6 HASH context swap register 6 0x110 0x20 0x00000000 0xFFFFFFFF CS6 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR7 CSR7 HASH context swap register 7 0x114 0x20 0x00000000 0xFFFFFFFF CS7 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR8 CSR8 HASH context swap register 8 0x118 0x20 0x00000000 0xFFFFFFFF CS8 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR9 CSR9 HASH context swap register 9 0x11C 0x20 0x00000000 0xFFFFFFFF CS9 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR10 CSR10 HASH context swap register 10 0x120 0x20 0x00000000 0xFFFFFFFF CS10 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR11 CSR11 HASH context swap register 11 0x124 0x20 0x00000000 0xFFFFFFFF CS11 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR12 CSR12 HASH context swap register 12 0x128 0x20 0x00000000 0xFFFFFFFF CS12 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR13 CSR13 HASH context swap register 13 0x12C 0x20 0x00000000 0xFFFFFFFF CS13 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR14 CSR14 HASH context swap register 14 0x130 0x20 0x00000000 0xFFFFFFFF CS14 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR15 CSR15 HASH context swap register 15 0x134 0x20 0x00000000 0xFFFFFFFF CS15 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR16 CSR16 HASH context swap register 16 0x138 0x20 0x00000000 0xFFFFFFFF CS16 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR17 CSR17 HASH context swap register 17 0x13C 0x20 0x00000000 0xFFFFFFFF CS17 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR18 CSR18 HASH context swap register 18 0x140 0x20 0x00000000 0xFFFFFFFF CS18 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR19 CSR19 HASH context swap register 19 0x144 0x20 0x00000000 0xFFFFFFFF CS19 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR20 CSR20 HASH context swap register 20 0x148 0x20 0x00000000 0xFFFFFFFF CS20 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR21 CSR21 HASH context swap register 21 0x14C 0x20 0x00000000 0xFFFFFFFF CS21 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR22 CSR22 HASH context swap register 22 0x150 0x20 0x00000000 0xFFFFFFFF CS22 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR23 CSR23 HASH context swap register 23 0x154 0x20 0x00000000 0xFFFFFFFF CS23 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR24 CSR24 HASH context swap register 24 0x158 0x20 0x00000000 0xFFFFFFFF CS24 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR25 CSR25 HASH context swap register 25 0x15C 0x20 0x00000000 0xFFFFFFFF CS25 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR26 CSR26 HASH context swap register 26 0x160 0x20 0x00000000 0xFFFFFFFF CS26 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR27 CSR27 HASH context swap register 27 0x164 0x20 0x00000000 0xFFFFFFFF CS27 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR28 CSR28 HASH context swap register 28 0x168 0x20 0x00000000 0xFFFFFFFF CS28 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR29 CSR29 HASH context swap register 29 0x16C 0x20 0x00000000 0xFFFFFFFF CS29 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR30 CSR30 HASH context swap register 30 0x170 0x20 0x00000000 0xFFFFFFFF CS30 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR31 CSR31 HASH context swap register 31 0x174 0x20 0x00000000 0xFFFFFFFF CS31 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR32 CSR32 HASH context swap register 32 0x178 0x20 0x00000000 0xFFFFFFFF CS32 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR33 CSR33 HASH context swap register 33 0x17C 0x20 0x00000000 0xFFFFFFFF CS33 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR34 CSR34 HASH context swap register 34 0x180 0x20 0x00000000 0xFFFFFFFF CS34 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR35 CSR35 HASH context swap register 35 0x184 0x20 0x00000000 0xFFFFFFFF CS35 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR36 CSR36 HASH context swap register 36 0x188 0x20 0x00000000 0xFFFFFFFF CS36 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR37 CSR37 HASH context swap register 37 0x18C 0x20 0x00000000 0xFFFFFFFF CS37 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR38 CSR38 HASH context swap register 38 0x190 0x20 0x00000000 0xFFFFFFFF CS38 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR39 CSR39 HASH context swap register 39 0x194 0x20 0x00000000 0xFFFFFFFF CS39 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR40 CSR40 HASH context swap register 40 0x198 0x20 0x00000000 0xFFFFFFFF CS40 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR41 CSR41 HASH context swap register 41 0x19C 0x20 0x00000000 0xFFFFFFFF CS41 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR42 CSR42 HASH context swap register 42 0x1A0 0x20 0x00000000 0xFFFFFFFF CS42 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR43 CSR43 HASH context swap register 43 0x1A4 0x20 0x00000000 0xFFFFFFFF CS43 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR44 CSR44 HASH context swap register 44 0x1A8 0x20 0x00000000 0xFFFFFFFF CS44 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR45 CSR45 HASH context swap register 45 0x1AC 0x20 0x00000000 0xFFFFFFFF CS45 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR46 CSR46 HASH context swap register 46 0x1B0 0x20 0x00000000 0xFFFFFFFF CS46 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR47 CSR47 HASH context swap register 47 0x1B4 0x20 0x00000000 0xFFFFFFFF CS47 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR48 CSR48 HASH context swap register 48 0x1B8 0x20 0x00000000 0xFFFFFFFF CS48 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR49 CSR49 HASH context swap register 49 0x1BC 0x20 0x00000000 0xFFFFFFFF CS49 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR50 CSR50 HASH context swap register 50 0x1C0 0x20 0x00000000 0xFFFFFFFF CS50 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR51 CSR51 HASH context swap register 51 0x1C4 0x20 0x00000000 0xFFFFFFFF CS51 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR52 CSR52 HASH context swap register 52 0x1C8 0x20 0x00000000 0xFFFFFFFF CS52 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write CSR53 CSR53 HASH context swap register 53 0x1CC 0x20 0x00000000 0xFFFFFFFF CS53 Context swap x Refer to Section 24.7.7: HASH context swap registers introduction. 0 32 read-write HR0 HR0 HASH digest register 0 0x310 0x20 0x00000000 0xFFFFFFFF H0 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HR1 HR1 HASH digest register 1 0x314 0x20 0x00000000 0xFFFFFFFF H1 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HR2 HR2 HASH digest register 2 0x318 0x20 0x00000000 0xFFFFFFFF H2 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HR3 HR3 HASH digest register 3 0x31C 0x20 0x00000000 0xFFFFFFFF H3 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HR4 HR4 HASH digest register 4 0x320 0x20 0x00000000 0xFFFFFFFF H4 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HR5 HR5 HASH supplementary digest register 5 0x324 0x20 0x00000000 0xFFFFFFFF H5 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HR6 HR6 HASH supplementary digest register 6 0x328 0x20 0x00000000 0xFFFFFFFF H6 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only HR7 HR7 HASH supplementary digest register 7 0x32C 0x20 0x00000000 0xFFFFFFFF H7 Hash data x Refer to Section 24.7.4: HASH digest registers introduction. 0 32 read-only ICACHE Instruction cache ICACHE 0x40030400 0x0 0x400 registers ICACHE Instruction cache global interrupt 104 CR CR ICACHE control register 0x0 0x20 0x00000004 0xFFFFFFFF EN enable 0 1 read-write CACHEINV cache invalidation Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. 1 1 write-only WAYSEL cache associativity mode selection This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). 2 1 read-write HITMEN hit monitor enable 16 1 read-write MISSMEN miss monitor enable 17 1 read-write HITMRST hit monitor reset 18 1 read-write MISSMRST miss monitor reset 19 1 read-write SR SR ICACHE status register 0x4 0x20 0x00000001 0xFFFFFFFF BUSYF busy flag 0 1 read-only BSYENDF busy end flag 1 1 read-only ERRF cache error flag 2 1 read-only IER IER ICACHE interrupt enable register 0x8 0x20 0x00000000 0xFFFFFFFF BSYENDIE interrupt enable on busy end Set by software to enable an interrupt generation at the end of a cache invalidate operation. 1 1 read-write ERRIE interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (cacheable write access) 2 1 read-write FCR FCR ICACHE flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF CBSYENDF clear busy end flag Set by software. 1 1 write-only CERRF clear cache error flag Set by software. 2 1 write-only HMONR HMONR ICACHE hit monitor register 0x10 0x20 0x00000000 0xFFFFFFFF HITMON cache hit monitor counter 0 32 read-only MMONR MMONR ICACHE miss monitor register 0x14 0x20 0x00000000 0xFFFFFFFF MISSMON cache miss monitor counter 0 16 read-only IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers IWDG IWDG interrupt 35 KR KR IWDG key register 0x0 0x10 0x00000000 0x0000FFFF KEY Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see ) Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected) 0 16 write-only KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR IWDG prescaler register 0x4 0x10 0x00000000 0x0000FFFF PR Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Others: divider / 1024 Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset. 0 4 read-write PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 6 DivideBy512 Divider /512 7 DivideBy1024 Divider /1024 true RLR RLR IWDG reload register 0x8 0x10 0x00000FFF 0x0000FFFF RL Watchdog counter reload value These bits are write access protected see . They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the . The watchdog counter counts down from this value. The timeout period is a function of this value and the prescaler.clock. It is not recommended to set RL[11:0] to a value lower than 2. The RVU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on it. For this reason the value read from this register is valid only when the RVU bit in the status register (IWDG_SR) is reset. 0 12 read-write 0 4095 SR SR IWDG status register 0xC 0x10 0x00000000 0x0000FFFF PVU Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The prescaler value can be updated only when PVU bit is reset. 0 1 read-only PVU Idle No update on-going 0 Busy Update on-going 1 RVU Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The reload value can be updated only when RVU bit is reset. 1 1 read-only WVU Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The window value can be updated only when WVU bit is reset. This bit is generated only if generic 'window' = 1 2 1 read-only EWU Watchdog interrupt comparator value update This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset. 3 1 read-only EWIF Watchdog early interrupt flag This bit is set to '1' by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to '1'. 14 1 read-only EWIFR NotPending No pending interrupt 0 Pending Interrupt pending 1 ONF Watchdog enable status bit. Set to â1â by hardware as soon as the IWDG is started. In software mode, it remains to '1' until the IWDG is reset. In hardware mode, this bit is always set to '1'. 8 1 read-only ONFR NotActivated IWDG is not activated 0 Activated IWDG is activated 1 WINR WINR IWDG window register 0x10 0x10 0x00000FFF 0x0000FFFF WIN Watchdog counter window value These bits are write access protected, see , they contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the IWDCNT downcounter must be reloaded when its value is lower than WIN[11:0]+1 and greater than 1. The WVU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the (IWDG_SR) is reset. 0 12 read-write 0 4095 EWCR EWCR IWDG early wakeup interrupt register 0x14 0x10 0x00000000 0x0000FFFF EWIT Watchdog counter window value These bits are write access protected (see ). They are written by software to define at which position of the IWDCNT down-counter the early wakeup interrupt must be generated. The early interrupt is generated when the IWDCNT is lower or equal to EWIT[11:0] - 1. EWIT[11:0] must be bigger than 1. An interrupt is generated only if EWIE = 1. The EWU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the Early wakeup comparator value and the Interrupt enable bit from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the EWU bit in the is reset. 0 12 read-write EWIC Watchdog early interrupt acknowledge The software must write a 1 into this bit in order to acknowledge the early wakeup interrupt and to clear the EWIF flag. Writing 0 has not effect, reading this flag returns a 0. 14 1 write-only EWIE Watchdog early interrupt enable Set and reset by software. The EWU bit in the must be reset to be able to change the value of this bit. 15 1 read-write I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 51 I2C1_ER I2C1 error interrupt 52 CR1 CR1 I2C control register 1 0x0 0x20 0x00000000 0xFFFFFFFF PE Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. 0 1 read-write PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 read-write TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 read-write RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match Interrupt enable (slave only) 3 1 read-write ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received Interrupt enable 4 1 read-write NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE Stop detection Interrupt enable 5 1 read-write STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR) 6 1 read-write TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT) 7 1 read-write ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0). 8 4 read-write DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0). 12 1 read-write ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 read-write TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 read-write RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control This bit is used to enable hardware byte control in slave mode. 16 1 read-write SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0). 17 1 read-write NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . Note: WUPEN can be set only when DNF = '0000' 18 1 read-write WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 read-write GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 20 1 read-write SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 21 1 read-write SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 22 1 read-write ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 23 1 read-write PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 FMP Fast-mode Plus 20 mA drive enable 24 1 read-write FMP Disabled 20 mA I/O drive disabled 0 Enabled 20 mA I/O drive enabled 1 ADDRACLR Address match flag (ADDR) automatic clear 30 1 read-write ADDRACLR Disabled ADDR flag is set by hardware, cleared by software 0 Enabled ADDR flag remains cleared by hardware 1 STOPFACLR STOP detection flag (STOPF) automatic clear 31 1 read-write STOPFACLR Disabled STOPF flag is set by hardware, cleared by software 0 Enabled STOPF flag remains cleared by hardware 1 CR2 CR2 I2C control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SADD Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed. 0 10 read-write 0 1023 RD_WRN Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed. 10 1 read-write RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 ADD10 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed. 11 1 read-write ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 HEAD10R 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed. 12 1 read-write HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 START Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0' to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set. 13 1 read-write oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 STOP Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0' to this bit has no effect. 14 1 read-write oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 NACK NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0' to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. 15 1 read-write oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 NBYTES Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed. 16 8 read-write 0 255 RELOAD NBYTES reload mode This bit is set and cleared by software. 24 1 read-write RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 AUTOEND Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set. 25 1 read-write AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 PECBYTE Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0' to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 26 1 read-write oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 OAR1 OAR1 I2C own address 1 register 0x8 0x20 0x00000000 0xFFFFFFFF OA1 Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0. 0 10 read-write 0 1023 OA1MODE Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0. 10 1 read-write OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 read-write OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 I2C own address 2 register 0xC 0x20 0x00000000 0xFFFFFFFF OA2 Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0. 1 7 read-write 0 127 OA2MSK Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. 8 3 read-write OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and donât care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and donât care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and donât care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and donât care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and donât care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and donât care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and donât care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 read-write OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR I2C timing register 0x10 0x20 0x00000000 0xFFFFFFFF SCLL SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings. 0 8 read-write 0 255 SCLH SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing. 8 8 read-write 0 255 SDADEL Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing. 16 4 read-write 0 15 SCLDEL Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing. 20 4 read-write 0 15 PRESC Timing prescaler This field is used to prescale i2c_ker_ck in order to generate the clock period tPRESC used for data setup and hold counters (refer to ) and for SCL high and low level counters (refer to ). tPRESC = (PRESC+1) x tI2CCLK 28 4 read-write 0 15 TIMEOUTR TIMEOUTR I2C timeout register 0x14 0x20 0x00000000 0xFFFFFFFF TIMEOUTA Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0. 0 12 read-write 0 4095 TIDLE Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0. 12 1 read-write TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 read-write TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0. 16 12 read-write 0 4095 TEXTEN Extended clock timeout enable 31 1 read-write TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR I2C interrupt and status register 0x18 0x20 0x00000001 0xFFFFFFFF TXE Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to '1' by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0. 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 TXIS Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to '1' by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0. 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 RXNE Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0. 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 ADDR Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0. 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 NACKF Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0. 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 STOPF Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0. 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 TC Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0. 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TCR Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set. 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 BERR Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0. 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 ARLO Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0. 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 OVR Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0. 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 PECERR PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 TIMEOUT Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 ALERT SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 BUSY Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE=0. 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 DIR Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1). 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 ADDCODE Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. 17 7 read-only 0 127 ICR ICR I2C interrupt clear register 0x1C 0x20 0x00000000 0xFFFFFFFF ADDRCF Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. 3 1 write-only oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 NACKCF Not Acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register. 4 1 write-only oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 STOPCF STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. 5 1 write-only oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 BERRCF Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. 8 1 write-only oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 ARLOCF Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. 9 1 write-only oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 OVRCF Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register. 10 1 write-only oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 PECCF PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 11 1 write-only oneToClear PECCF Clear Clears the PEC flag in ISR register 1 TIMOUTCF Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 12 1 write-only oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 ALERTCF Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . 13 1 write-only oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 PECR PECR I2C PEC register 0x20 0x20 0x00000000 0xFFFFFFFF PEC Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0. 0 8 read-only 0 255 RXDR RXDR I2C receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RXDATA 8-bit receive data Data byte received from the I2C bus 0 8 read-only 0 255 TXDR TXDR I2C transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TXDATA 8-bit transmit data Data byte to be transmitted to the I2C bus Note: These bits can be written only when TXE=1. 0 8 read-write 0 255 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 53 I2C2_ER I2C2 error interrupt 54 I3C1 Improved inter-integrated circuit I3C 0x40005C00 0x0 0x400 registers I3C1_EV I3C1 event interrupt 123 I3C1_ER I3C1 error interrupt 124 CR CR I3C message control register 0x0 0x20 0x00000000 0xFFFFFFFF DCNT count of data to transfer during a read or write message, in bytes (whatever I3C is acting as controller/target) Linear encoding up to 64 Kbytes -1 ... 0 16 write-only RNW read / non-write message (when I3C is acting as controller) When I3C is acting as controller, this field is used if MTYPE[3:0]=0010 (private message) or MTYPE[3:0]=0011 (direct message) or MTYPE[3:0]=0100 (legacy I2C message), in order to emit the RnW bit on the I3C bus. 16 1 write-only ADD 7-bit I3C dynamic / I2C static target address (when I3C is acting as controller) When I3C is acting as controller, this field is used if MTYPE[3:0]=0010 (private message) or MTYPE[3:0]=0011 (direct message) or MTYPE[3:0]=0100 (legacy I2C message) 17 7 write-only MTYPE message type (whatever I3C is acting as controller/target) Bits[26:0] are ignored. After M2 error detection on an I3C SDR message, this is needed for SCL 'stuck at' recovery. Bits[26:0] are ignored. If I3C_CFGR.EXITPTRN=1, an HDR exit pattern is emitted on the bus to generate an escalation fault. Bits[23:17] (ADD[6:0]) is the emitted 7-bit dynamic address. Bit[16] (RNW) is the emitted RnW bit. The transferred private message is: {S / S+7'h7E+RnW=0+Sr / Sr+*} + 7-bit DynAddr + RnW + (8-bit Data + T)* + Sr/P. After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7'h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7'h7E+RnW=0) if needed, i.e. if it follows an I3C direct message without ending by a P (Stop). Bits[23:17] (ADD[6:0]) is the emitted 7-bit dynamic address. Bit[16] (RNW) is the emitted RnW bit. The transferred direct message is: Sr + 7-bit DynAddr + RnW + (8-bit Data + T)* + Sr/P Bits[23:17] (ADD[6:0]) is the emitted 7-bit static address. Bit[16] (RNW) is the emitted RnW bit. The transferred legacy I2C message is: {S / S+ 7'h7E+RnW=0 + Sr / Sr+*} + 7-bit StaAddr + RnW + (8-bit Data + T)* + Sr/P. After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7'h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7'h7E+RnW=0) if needed, i.e. if it follows an I3C direct message without ending by a P (Stop). 1xxx: reserved (when I3C is acting as I3C controller, used when target) 0xxx: reserved {S +} 7'h02 addr + RnW=0 {S +} 7-bit I3C_DEVR0.DA[6:0] + RnW=0 after a bus available condition (the target first emits a START request), or once the controller drives a START. {S +} 7-bit I3C_DEVR0.DA[6:0] + RnW=1 (+Ack/Nack from controller) When acknowledged from controller, the next (optional, depending on I3C_BCR.BCR2) transmitted IBI payload data is defined by I3C_CR.DCNT[15:0] and must be consistently programmed vs the maximum IBI payload data size which is defined by I3C_IBIDR.IBIP[2:0]. Others: reserved 27 4 write-only MEND message end type (when the I3C is acting as controller) 31 1 write-only CR_ALTERNATE CR_ALTERNATE I3C message control register alternate CR 0x0 0x20 0x00000000 0xFFFFFFFF DCNT count of data to transfer during a read or write message, in bytes (when I3C is acting as controller) Linear encoding up to 64 Kbytes -1. ... 0 16 write-only CCC 8-bit CCC code (when I3C is acting as controller) If Bit[23]=CCC[7]=1, this is the 1st part of an I3C SDR direct CCC command. If Bit[23]=CCC[7]=0, this is an I3C SDR broadcast CCC command (including ENTDAA and ENTHDR0). 16 8 write-only MTYPE message type (when I3C is acting as controller) Bits[23:16] (CCC[7:0]) is the emitted 8-bit CCC code If Bit[23]=CCC[7]=1: this is the 1st part of an I3C SDR direct CCC command The transferred direct CCC command message is: {S / S+7'h7E +RnW=0 / Sr+*} + (direct CCC + T) + (8-bit Data + T)* + Sr After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7'h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7'h7E+R/W). If Bit[23]=CCC[7]=0: this is an I3C SDR broadcast CCC command (including ENTDAA and ENTHDR0) The transferred broadcast CCC command message is: {S / S+7'h7E +RnW=0 / Sr+*} + (broadcast CCC + T) + (8-bit Data + T)* + Sr/P After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7'h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7'h7E+R/W). others: reserved 27 4 write-only MEND message end type (when I3C is acting as controller) 31 1 write-only CFGR CFGR I3C configuration register 0x4 0x20 0x00000000 0xFFFFFFFF EN I3C enable (whatever I3C is acting as controller/target) - Except registers, the peripheral is under reset (a.k.a. partial reset). - Before clearing EN, when I3C is acting as a controller, all the possible target requests must be disabled using DISEC CCC. - When I3C is acting as a target, software should not disable the I3C, unless a partial reset is needed. In this state, some register fields can not be modified (like CRINIT, HKSDAEN for the I3C_CFGR) 0 1 read-write CRINIT initial controller/target role This bit can be modified only when I3C_CFGR.EN = 0. Once enabled by setting I3C_CFGR.EN = 1, I3C peripheral initially acts as an I3C target. I3C does not drive SCL line and does not enable SDA pull-up, until it eventually acquires the controller role. Once enabled by setting I3C_CFGR.EN = 1, I3C peripheral initially acts as a controller. It has the I3C controller role, so drives SCL line and enables SDA pull-up, until it eventually offers the controller role to an I3C secondary controller. 1 1 read-write NOARBH no arbitrable header after a START (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. - The target address is emitted directly after a START in case of a legacy I2C message or an I3C SDR private read/write message. - This is a more performing option (when is useless the emission of the 0x7E arbitrable header), but this is to be used only when the controller is sure that the addressed target device can not emit concurrently an IBI or a controller-role request (to insure no misinterpretation and no potential conflict between the address emitted by the controller in open-drain mode and the same address a target device can emit after a START, for IBI or MR). 2 1 read-write RSTPTRN HDR reset pattern enable (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. 3 1 read-write EXITPTRN HDR Exit Pattern enable (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. This is used to send only the header to test ownership of the bus when there is a suspicion of problem after controller-role hand-off (new controller didn't assert its controller-role by accessing the previous one in less than Activity State time). The HDR Exit Pattern is sent even if the message header {S/Sr + 0x7E addr + W } is ACKed. 4 1 read-write HKSDAEN High-keeper enable on SDA line (when I3C is acting as a controller) This bit can be modified only when I3C_CFGR.EN=0. 5 1 read-write HJACK Hot Join request acknowledge (when I3C is acting as a controller) After the NACK, the message continues as initially programmed (the hot-joining target is aware of the NACK and surely emits another hot-join request later on). After the ACK, the message continues as initially programmed. The software is aware by the HJ interrupt (flag I3C_EVR.HJF is set) and initiates the ENTDAA sequence later on, potentially preventing others Hot Join requests with a Disable target events command (DISEC, with DISHJ=1). Independently of the HJACK configuration, further Hot Join request(s) are NACKed until the Hot Join flag, HJF, is cleared. However, a NACKed target can be assigned a dynamic address by the ENTDAA sequence initiated later on by the first HJ request, preventing this target to emit an HJ request again. 7 1 read-write RXDMAEN RX-FIFO DMA request enable (whatever I3C is acting as controller/target) - Software reads and pops a data byte/word from RX-FIFO i.e. reads I3C_RDR or I3C_RDWR register. - A next data byte/word is to be read by the software either via polling on the flag I3C_EVR.RXFNEF=1 or via interrupt notification (enabled by I3C_IER.RXFNEIE=1). - DMA reads and pops data byte(s)/word(s) from RX-FIFO i.e. reads I3C_RDR or I3C_RDWR register. - A next data byte/word is automatically read by the programmed hardware (i.e. via the asserted RX-FIFO DMA request from the I3C and the programmed DMA channel). 8 1 read-write RXFLUSH RX-FIFO flush (whatever I3C is acting as controller/target) This bit can only be written. 9 1 write-only RXTHRES RX-FIFO threshold (whatever I3C is acting as controller/target) This threshold defines, compared to the RX-FIFO level, when the I3C_EVR.RXFNEF flag is set (and consequently if RXDMAEN=1 when is asserted a DMA RX request). RXFNEF is set when 1 byte is to be read in RX-FIFO (i.e. in I3C_RDR). RXFNEF is set when 4 bytes are to be read in RX-FIFO (i.e. in I3C_RDWR). 10 1 read-write TXDMAEN TX-FIFO DMA request enable (whatever I3C is acting as controller/target) - Software writes and pushes a data byte/word into TX-FIFO i.e. writes I3C_TDR or I3C_TDWR register, to be transmitted over the I3C bus. - A next data byte/word is to be written by the software either via polling on the flag I3C_EVR.TXFNFF=1 or via interrupt notification (enabled by I3C_IER.TXFNFIE=1). - DMA writes and pushes data byte(s)/word(s) into TX-FIFO i.e. writes I3C_TDR or I3C_TDWR register. - A next data byte/word transfer is automatically pushed by the programmed hardware (i.e. via the asserted TX-FIFO DMA request from the I3C and the programmed DMA channel). 12 1 read-write TXFLUSH TX-FIFO flush (whatever I3C is acting as controller/target) This bit can only be written. When the I3C is acting as target, this bit can be used to flush the TX-FIFO on a private read if the controller has early ended the read data (i.e. driven low the T bit) and there is/are remaining data in the TX-FIFO (i.e. I3C_SR.ABT=1 and I3C_SR.XDCNT[15:0] I3C_TGTTDR.TGTTDCNT[15:0]). 13 1 write-only TXTHRES TX-FIFO threshold (whatever I3C is acting as controller/target) This threshold defines, compared to the TX-FIFO level, when the I3C_EVR.TXFNFF flag is set (and consequently if TXDMAEN=1 when is asserted a DMA TX request). TXFNFF is set when 1 byte is to be written in TX-FIFO (i.e. in I3C_TDR). TXFNFF is set when 4 bytes are to be written in TX-FIFO (i.e. in I3C_TDWR). 14 1 read-write SDMAEN S-FIFO DMA request enable (when I3C is acting as controller) Condition: When RMODE=1 (FIFO is enabled for the status): - Software reads and pops a status word from S-FIFO i.e. reads I3C_SR register after a completed frame (I3C_EVR.FCF=1) or an error (I3C_EVR.ERRF=1). - A status word can be read by the software either via polling on these register flags or via interrupt notification (enabled by I3C_IER.FCIE=1 and I3C_IER.ERRIE=1). - DMA reads and pops status word(s) from S-FIFO i.e. reads I3C_SR register. - Status word(s) are automatically read by the programmed hardware (i.e. via the asserted S-FIFO DMA request from the I3C and the programmed DMA channel). 16 1 read-write SFLUSH S-FIFO flush (when I3C is acting as controller) When I3C is acting as I3C controller, this bit can only be written (and is only used when I3C is acting as controller). 17 1 write-only RMODE S-FIFO enable / status receive mode (when I3C is acting as controller) When I3C is acting as I3C controller, this bit is used for the enabling the FIFO for the status (S-FIFO) vs the received status from the target on the I3C bus. When I3C is acting as target, this bit must be cleared. - Status register (i.e. I3C_SR) is used without FIFO mechanism. - There is no SCL stretch if a new status register content is not read. - Status register must be read before being lost/overwritten. All message status must be read. There is SCL stretch when there is no more space in the S-FIFO. 18 1 read-write TMODE transmit mode (when I3C is acting as controller) When I3C is acting as I3C controller, this bit is used for the C-FIFO and TX-FIFO management vs the emitted frame on the I3C bus. A frame transfer starts as soon as first control word is present in C-FIFO. 19 1 read-write CDMAEN C-FIFO DMA request enable (when I3C is acting as controller) When I3C is acting as controller: - Software writes and pushes control word(s) into C-FIFO i.e. writes I3C_CR register, as needed for a given frame. - A next control word transfer can be written by software either via polling on the flag I3C_EVR.CFNFF=1 or via interrupt notification (enabled by I3C_IER.CFNFIE=1). - DMA writes and pushes control word(s) into C-FIFO i.e. writes I3C_CR register, as needed for a given frame. - A next control word transfer is automatically written by the programmed hardware (i.e. via the asserted C-FIFO DMA request from the I3C and the programmed DMA channel). 20 1 read-write CFLUSH C-FIFO flush (when I3C is acting as controller) This bit can only be written. 21 1 write-only TSFSET frame transfer set (a.k.a. software trigger) (when I3C is acting as controller) This bit can only be written. When I3C is acting as I3C controller: Note: If this bit is not set, the other alternative for the software to initiate a frame transfer is to directly write the first control word register (i.e. I3C_CR) while C-FIFO is empty (i.e. I3C_EVR.CFEF=1). Then, if the first written control word is not tagged as a message end (i.e I3C_CR.MEND=0), it causes the hardware to assert the flag I3C_EVR.CFNFF (C-FIFO not full and a next control word is needed). 30 1 write-only RDR RDR I3C receive data byte register 0x10 0x20 0x00000000 0xFFFFFFFF RDB0 8-bit received data on I3C bus. 0 8 read-only RDWR RDWR I3C receive data word register 0x14 0x20 0x00000000 0xFFFFFFFF RDB0 8-bit received data (earliest byte on I3C bus). 0 8 read-only RDB1 8-bit received data (next byte after RDB0 on I3C bus). 8 8 read-only RDB2 8-bit received data (next byte after RDB1 on I3C bus). 16 8 read-only RDB3 8-bit received data (latest byte on I3C bus). 24 8 read-only TDR TDR I3C transmit data byte register 0x18 0x20 0x00000000 0xFFFFFFFF TDB0 8-bit data to transmit on I3C bus. 0 8 write-only TDWR TDWR I3C transmit data word register 0x1C 0x20 0x00000000 0xFFFFFFFF TDB0 8-bit transmit data (earliest byte on I3C bus) 0 8 write-only TDB1 8-bit transmit data (next byte after TDB0[7:0] on I3C bus). 8 8 write-only TDB2 8-bit transmit data (next byte after TDB1[7:0] on I3C bus). 16 8 write-only TDB3 8-bit transmit data (latest byte on I3C bus). 24 8 write-only IBIDR IBIDR I3C IBI payload data register 0x20 0x20 0x00000000 0xFFFFFFFF IBIDB0 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte). 0 8 read-write IBIDB1 8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0]). 8 8 read-write IBIDB2 8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0]). 16 8 read-write IBIDB3 8-bit IBI payload data (latest byte on I3C bus). 24 8 read-write TGTTDR TGTTDR I3C target transmit configuration register 0x24 0x20 0x00000000 0xFFFFFFFF TGTTDCNT transmit data counter, in bytes (when I3C is configured as target) This field must be written by software in the same access when is asserted PRELOAD, in order to define the number of bytes to preload and to transmit. This field is updated by hardware and reports, when read, the remaining number of bytes to be loaded into the TX-FIFO. 0 16 read-write PRELOAD preload of the TX-FIFO (when I3C is configured as target) This bit must be written and asserted by software in the same access when is written and defined the number of bytes to preload into the TX-FIFO and to transmit. This bit is cleared by hardware when all the data bytes to transmit are loaded into the TX-FIFO. 16 1 read-write SR SR I3C status register 0x30 0x20 0x00000000 0xFFFFFFFF XDCNT data counter - When the I3C is acting as controller: number of targets detected on the bus - When the I3C is acting as target: number of transmitted bytes - Whatever the I3C is acting as controller or target: number of data bytes read from or transmitted on the I3C bus during the MID[7:0] message 0 16 read-only ABT a private read message is completed/aborted prematurely by the target (when the I3C is acting as controller) When the I3C is acting as controller, this bit indicates if the private read data which is transmitted by the target early terminates (i.e. the target drives T bit low earlier vs what does expect the controller in terms of programmed number of read data bytes i.e. I3C_CR.DCNT[15:0]). 17 1 read-only DIR message direction Whatever the I3C is acting as controller or target, this bit indicates the direction of the related message on the I3C bus Note: ENTDAA CCC is considered as a write command. 18 1 read-only MID message identifier/counter of a given frame (when the I3C is acting as controller) When the I3C is acting as controller, this field identifies the control word message (i.e. I3C_CR) to which the I3C_SR status register refers. First message of a frame is identified with MID[7:0]=0. This field is incremented (by hardware) on the completion of a new message control word (i.e. I3C_CR) over I3C bus. This field is reset for every new frame start. 24 8 read-only SER SER I3C status error register 0x34 0x20 0x00000000 0xFFFFFFFF CODERR protocol error code/type controller detected an illegally formatted CCC controller detected that transmitted data on the bus is different from expected controller detected a not acknowledged broadcast address (7'hE) controller detected the new controller did not drive bus after controller-role hand-off target detected an invalid broadcast address 7'hE+W target detected a parity error on a CCC code via a parity check (vs T bit) target detected a parity error on a write data via a parity check (vs T bit) target detected a parity error on the assigned address during dynamic address arbitration via a parity check (vs PAR bit) target detected a 7'hE+R missing after Sr during dynamic address arbitration target detected an illegally formatted CCC target detected that transmitted data on the bus is different from expected others: reserved 0 4 read-only PERR protocol error 4 1 read-only STALL SCL stall error (when the I3C is acting as target) 5 1 read-only DOVR RX-FIFO overrun or TX-FIFO underrun i) a TX-FIFO underrun: TX-FIFO is empty and a write data byte has to be transmitted ii) a RX-FIFO overrun: RX-FIFO is full and a new data byte is received 6 1 read-only COVR C-FIFO underrun or S-FIFO overrun (when the I3C is acting as controller) i) a C-FIFO underrun: control FIFO is empty and a restart has to be emitted ii) a S-FIFO overrun: S-FIFO is full and a new message ends 7 1 read-only ANACK address not acknowledged (when the I3C is configured as controller) i) a legacy I2C read/write transfer ii) a direct CCC write transfer iii) the second trial of a direct CCC read transfer iv) a private read/write transfer 8 1 read-only DNACK data not acknowledged (when the I3C is acting as controller) i) a legacy I2C write transfer ii) the second trial when sending dynamic address during ENTDAA procedure 9 1 read-only DERR data error (when the I3C is acting as controller) 10 1 read-only RMR RMR I3C received message register 0x40 0x20 0x00000000 0xFFFFFFFF IBIRDCNT IBI received payload data count (when the I3C is configured as controller) When the I3C is configured as controller, this field logs the number of data bytes effectively received in the I3C_IBIDR register. 0 3 read-only RCODE received CCC code (when the I3C is configured as target) When the I3C is configured as target, this field logs the received CCC code. 8 8 read-only RADD received target address (when the I3C is configured as controller) When the I3C is configured as controller, this field logs the received dynamic address from the target during acknowledged IBI or controller-role request. 17 7 read-only EVR EVR I3C event register 0x50 0x20 0x00000003 0xFFFFFFFF CFEF C-FIFO empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the C-FIFO is empty when controller, and that the I3C_CR register contains no control word (i.e. none IBI/CR/HJ request) when target. This flag is de-asserted by hardware to indicate that the C-FIFO is not empty when controller, and that the I3C_CR register contains one control word (i.e. a pending IBI/CR/HJ request) when target. Note: When the I3C is acting as controller, if the C-FIFO and TX-FIFO preload is configured (i.e. I3C_CFGR.TMODE=1), the software must wait for TXFEF=1 and CFEF=1 before starting a new frame transfer. 0 1 read-only TXFEF TX-FIFO empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the TX-FIFO is empty. This flag is de-asserted by hardware to indicate that the TX-FIFO is not empty. Note: When the I3C is acting as controller, if the C-FIFO and TX-FIFO preload is configured (i.e. I3C_CFGR.TMODE=1), the software must wait for TXFEF=1 and CFEF=1 before starting a new frame transfer. 1 1 read-only CFNFF C-FIFO not full flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a control word is to be written to the C-FIFO. This flag is de-asserted by hardware to indicate that a control word is not to be written to the C-FIFO. Note: The software must wait for CFNFF=1 (by polling or via the enabled interrupt) before writing to C-FIFO (i.e. writing to I3C_CR). 2 1 read-only SFNEF S-FIFO not empty flag (when the I3C is acting as controller) When the I3C is acting as controller, if the S-FIFO is enabled (i.e. I3C_CFGR.RMODE=1), this flag is asserted by hardware to indicate that a status word is to be read from the S-FIFO. This flag is de-asserted by hardware to indicate that a status word is not to be read from the S-FIFO. 3 1 read-only TXFNFF TX-FIFO not full flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that a data byte/word is to be written to the TX-FIFO. This flag is de-asserted by hardware to indicate that a data byte/word is not to be written to the TX-FIFO. Note: The software must wait for TXFNFF=1 (by polling or via the enabled interrupt) before writing to TX-FIFO (i.e. writing to I3C_TDR or I3C_TDWR depending on I3C_CFGR.TXTHRES). Note: When the I3C is acting as target, if the software intends to use the TXFNFF flag for writing into I3C_TDR/I3C_TDWR, it must have configured and set the TX-FIFO preload (i.e. write I3C_TGTTDR.PRELOAD). 4 1 read-only RXFNEF RX-FIFO not empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that a data byte is to be read from the RX-FIFO. This flag is de-asserted by hardware to indicate that a data byte is not to be read from the RX-FIFO. Note: The software must wait for RXFNEF=1 (by polling or via the enabled interrupt) before reading from RX-FIFO (i.e. writing to I3C_RDR or I3C_RDWR depending on I3C_CFGR.RXTHRES). 5 1 read-only TXLASTF last written data byte/word flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the last data byte/word (depending on I3C_CFGR.TXTHRES) of a message is to be written to the TX-FIFO. This flag is de-asserted by hardware when the last data byte/word of a message is written. 6 1 read-only RXLASTF last read data byte/word flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the last data byte/word (depending on I3C_CFGR.RXTHRES) of a message is to be read from the RX-FIFO. This flag is de-asserted by hardware when the last data byte/word of a message is read. 7 1 read-only FCF frame complete flag (whatever the I3C is acting as controller/target) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a frame has been (normally) completed on the I3C bus, i.e when a stop is issued. When the I3C is acting as target, this flag is asserted by hardware to indicate that a message addressed to/by this target has been (normally) completed on the I3C bus, i.e when a next stop or repeated start is then issued by the controller. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CFCF bit. 9 1 read-only RXTGTENDF target-initiated read end flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that the target has prematurely ended a read transfer. Then, software should read I3C_SR to get more information on the prematurely read transfer. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CRXTGTENDF bit. 10 1 read-only ERRF flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that an error occurred.Then, software should read I3C_SER to get the error type. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CERRF bit. 11 1 read-only IBIF IBI flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that an IBI request has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CIBIF bit. 15 1 read-only IBIENDF IBI end flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a IBI transfer has been received and completed (IBI acknowledged and IBI data bytes read by controller if any). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CIBIENDF bit. 16 1 read-only CRF controller-role request flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a controller-role request has been acknowledged and completed (by hardware). The software should then issue a GETACCCR CCC (get accept controller role) for the controller-role hand-off procedure. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CCRF bit. 17 1 read-only CRUPDF controller-role update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that it has now gained the controller role after the completed controller-role hand-off procedure. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CCRUPDF bit. 18 1 read-only HJF hot-join flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that an hot join request has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CHJF bit. 19 1 read-only WKPF wakeup/missed start flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a start has been detected (i.e. a SDA falling edge followed by a SCL falling edge) but on the next SCL falling edge, the I3C kernel clock is (still) gated. Thus an I3C bus transaction may have been lost by the target. The corresponding interrupt may be used to wakeup the device from a low power mode (Sleep or Stop mode). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CWKPF bit. 21 1 read-only GETF get flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that any direct CCC of get type (GET*** CCC) has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CGETF bit. 22 1 read-only STAF get status flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct GETSTATUS CCC (get status) has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CSTAF bit. 23 1 read-only DAUPDF dynamic address update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a dynamic address update has been received via any of the broadcast ENTDAA, RSTDAA and direct SETNEWDA CCC. Then, software should read I3C_DEVR0.DA[6:0] to get the maximum write length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CDAUPDF bit. 24 1 read-only MWLUPDF maximum write length update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct SETMWL CCC (set max write length) has been received. Then, software should read I3C_MAXWLR.MWL[15:0] to get the maximum write length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CMWLUPDF bit. 25 1 read-only MRLUPDF maximum read length update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct SETMRL CCC (set max read length) has been received. Then, software should read I3C_MAXRLR.MRL[15:0] to get the maximum read length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CMRLUPDF bit. 26 1 read-only RSTF reset pattern flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a reset pattern has been detected (i.e. 14 SDA transitions while SCL is low, followed by repeated start, then stop). Then, software should read I3C_DEVR0.RSTACT[1:0] and I3C_DEVR0.RSTVAL, to know what reset level is required. If RSTVAL=1: when the RSTF is asserted (and/or the corresponding interrupt if enabled), I3C_DEVR0.RSTACT[1:0] dictates the reset action to be performed by the software if any. If RSTVAL=0: when the RSTF is asserted (and/or the corresponding interrupt if enabled), the software should issue an I3C reset after a first detected reset pattern, and a system reset on the second one. The corresponding interrupt may be used to wakeup the device from a low power mode (Sleep or Stop mode). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CRSTF bit. 27 1 read-only ASUPDF activity state update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that the direct or broadcast ENTASx CCC (with x=0...3) has been received. Then, software should read I3C_DEVR0.AS[1:0]. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CASUPDF bit. 28 1 read-only INTUPDF interrupt/controller-role/hot-join update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that the direct or broadcast ENEC/DISEC CCC (enable/disable target events) has been received, where a target event is either an interrupt/IBI request, a controller-role request, or an hot-join request. Then, software should read respectively I3C_DEVR0.IBIEN, I3C_DEVR0.CREN or I3C_DEVR0.HJEN. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CINTUPDF bit. 29 1 read-only DEFF DEFTGTS flag (when the I3C is acting as target) When the I3C is acting as target (and is typically controller capable), this flag is asserted by hardware to indicate that the broadcast DEFTGTS CCC (define list of targets) has been received. Then, software may store the received data for when getting the controller role. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CDEFF bit. 30 1 read-only GRPF group addressing flag (when the I3C is acting as target) When the I3C is acting as target (and is typically controller capable), this flag is asserted by hardware to indicate that the broadcast DEFGRPA CCC (define list of group addresses) has been received. Then, software may store the received data for when getting the controller role. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CGRPF bit. 31 1 read-only IER IER I3C interrupt enable register 0x54 0x20 0x00000000 0xFFFFFFFF CFNFIE C-FIFO not full interrupt enable (whatever the I3C is acting as controller/target) 2 1 read-only SFNEIE S-FIFO not empty interrupt enable (whatever the I3C is acting as controller/target) 3 1 read-only TXFNFIE TX-FIFO not full interrupt enable (whatever the I3C is acting as controller/target) 4 1 read-only RXFNEIE RX-FIFO not empty interrupt enable (whatever the I3C is acting as controller/target) 5 1 read-only FCIE frame complete interrupt enable (whatever the I3C is acting as controller/target) 9 1 read-only RXTGTENDIE target-initiated read end interrupt enable (when the I3C is acting as controller) 10 1 read-only ERRIE error interrupt enable (whatever the I3C is acting as controller/target) 11 1 read-only IBIIE IBI request interrupt enable (when the I3C is acting as controller) 15 1 read-only IBIENDIE IBI end interrupt enable (when the I3C is acting as target) 16 1 read-only CRIE controller-role request interrupt enable (when the I3C is acting as controller) 17 1 read-only CRUPDIE controller-role update interrupt enable (when the I3C is acting as target) 18 1 read-only HJIE hot-join interrupt enable (when the I3C is acting as controller) 19 1 read-only WKPIE wakeup interrupt enable (when the I3C is acting as target) 21 1 read-only GETIE GETxxx CCC interrupt enable (when the I3C is acting as target) 22 1 read-only STAIE GETSTATUS CCC interrupt enable (when the I3C is acting as target) 23 1 read-only DAUPDIE ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C is acting as target) 24 1 read-only MWLUPDIE SETMWL CCC interrupt enable (when the I3C is acting as target) 25 1 read-only MRLUPDIE SETMRL CCC interrupt enable (when the I3C is acting as target) 26 1 read-only RSTIE reset pattern interrupt enable (when the I3C is acting as target) 27 1 read-only ASUPDIE ENTASx CCC interrupt enable (when the I3C is acting as target) 28 1 read-only INTUPDIE ENEC/DISEC CCC interrupt enable (when the I3C is acting as target) 29 1 read-only DEFIE DEFTGTS CCC interrupt enable (when the I3C is acting as target) 30 1 read-only GRPIE DEFGRPA CCC interrupt enable (when the I3C is acting as target) 31 1 read-only CEVR CEVR I3C clear event register 0x58 0x20 0x00000000 0xFFFFFFFF CFCF clear frame complete flag (whatever the I3C is acting as controller/target) 9 1 write-only CRXTGTENDF clear target-initiated read end flag (when the I3C is acting as controller) 10 1 write-only CERRF clear error flag (whatever the I3C is acting as controller/target) 11 1 write-only CIBIF clear IBI request flag (when the I3C is acting as controller) 15 1 write-only CIBIENDF clear IBI end flag (when the I3C is acting as target) 16 1 write-only CCRF clear controller-role request flag (when the I3C is acting as controller) 17 1 write-only CCRUPDF clear controller-role update flag (when the I3C is acting as target) 18 1 write-only CHJF clear hot-join flag (when the I3C is acting as controller) 19 1 write-only CWKPF clear wakeup flag (when the I3C is acting as target) 21 1 write-only CGETF clear GETxxx CCC flag (when the I3C is acting as target) 22 1 write-only CSTAF clear GETSTATUS CCC flag (when the I3C is acting as target) 23 1 write-only CDAUPDF clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C is acting as target) 24 1 write-only CMWLUPDF clear SETMWL CCC flag (when the I3C is acting as target) 25 1 write-only CMRLUPDF clear SETMRL CCC flag (when the I3C is acting as target) 26 1 write-only CRSTF clear reset pattern flag (when the I3C is acting as target) 27 1 write-only CASUPDF clear ENTASx CCC flag (when the I3C is acting as target) 28 1 write-only CINTUPDF clear ENEC/DISEC CCC flag (when the I3C is acting as target) 29 1 write-only CDEFF clear DEFTGTS CCC flag (when the I3C is acting as target) 30 1 write-only CGRPF clear DEFGRPA CCC flag (when the I3C is acting as target) 31 1 write-only DEVR0 DEVR0 I3C own device characteristics register 0x60 0x20 0x00000000 0xFFFFFFFF DAVAL dynamic address is valid (when the I3C is acting as target) When the I3C is acting as controller, this field can be written by software, for validating its own dynamic address, for example before a controller-role hand-off. When the I3C is acting as target, this field is asserted by hardware on the acknowledge of the broadcast ENTDAA CCC or the direct SETNEWDA CCC, and this field is cleared by hardware on the acknowledge of the broadcast RSTDAA CCC. 0 1 read-write DA 7-bit dynamic address When the I3C is acting as controller, this field can be written by software, for defining its own dynamic address. When the I3C is acting as target, this field is updated by hardware on the reception of either the broadcast ENTDAA CCC or the direct SETNEWDA CCC. 1 7 read-write IBIEN IBI request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISINT=1 (i.e. cleared) and the reception of ENEC CCC with ENINT=1 (i.e. set). 16 1 read-write CREN controller-role request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISCR=1 (i.e. cleared) and the reception of ENEC CCC with ENCR=1 (i.e. set). 17 1 read-write HJEN hot-join request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISHJ=1 (i.e. cleared) and the reception of ENEC CCC with ENHJ=1 (i.e. set). 19 1 read-write AS activity state (when the I3C is acting as target) This read field is updated by hardware on the reception of a ENTASx CCC (enter activity state, with x=0-3): 20 2 read-only RSTACT reset action/level on received reset pattern (when the I3C is acting as target) This read field is used by hardware on the reception of a direct read RSTACT CCC in order to return the corresponding data byte on the I3C bus. This read field is updated by hardware on the reception of a broadcast or direct write RSTACT CCC (target reset action). 22 2 read-only RSTVAL reset action is valid (when the I3C is acting as target) This read bit is asserted by hardware to indicate that the RTSACT[1:0] field has been updated on the reception of a broadcast or direct write RSTACT CCC (target reset action) and is valid. This field is cleared by hardware when the target receives a frame start. If RSTVAL=1: when the RSTF is asserted (and/or the corresponding interrupt if enabled), I3C_DEVR0.RSTACT[1:0] dictates the reset action to be performed by the software if any. If RSTVAL=0: when the RSTF is asserted (and/or the corresponding interrupt if enabled), the software should issue an I3C reset after a first detected reset pattern, and a system reset on the second one. 24 1 read-only DEVR1 DEVR1 I3C device 1 characteristics register 0x64 0x20 0x00000000 0xFFFFFFFF DA assigned I3C dynamic address to target x (when the I3C is acting as controller) When the I3C is acting as controller, this field should be written by software to store the 7-bit dynamic address that the controller sends via a broadcast ENTDAA or a direct SETNEWDA CCC which has been acknowledged by the target x. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. 1 7 read-write IBIACK IBI request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a IBI request from target x: - After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another IBI request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the controller logs the IBI payload data, if any, depending on I3C_DEVRx.IBIDEN. - The software is notified by the IBI flag (i.e. I3C_EVR.IBIF=1) and/or the corresponding interrupt if enabled; - Independently from IBIACK configuration for this or other devices, further IBI request(s) are NACKed until IBI request flag (i.e. I3C_EVR.IBIF) and controller-role request flag (i.e. I3C_EVR.CRF) are both cleared. 16 1 read-write CRACK controller-role request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a controller-role request from target x: After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another controller-role request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the message continues as initially programmed. The software is notified by the controller-role request flag (i.e. I3C_EVR.CRF=1) and/or the corresponding interrupt if enabled; For effectively granting the controller-role to the requesting secondary controller, software should issue a GETACCCR (formerly known as GETACCMST), followed by a STOP. - Independently of CRACK configuration for this or other devices, further controller-role request(s) are NACKed until controller-role request flag (i.e. I3C_EVR.CRF) and IBI flag (i.e. I3C_EVR.IBIF) are both cleared. 17 1 read-write IBIDEN IBI data enable (when the I3C is acting as controller) When the I3C is acting as controller, this bit should be written by software to store the BCR[2] bit as received from the target x during broadcast ENTDAA or direct GETBCR CCC via the received I3C_RDR. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. 18 1 read-write SUSP suspend/stop I3C transfer on received IBI (when the I3C is acting as controller) When the I3C is acting as controller, this bit is used to receive an IBI from target x with pending read notification feature (i.e. with received MDB[7:5]=3'b101). If this bit is set, when an IBI is received (i.e. I3C_EVR.IBIF=1), a Stop is emitted on the I3C bus and the C-FIFO is automatically flushed by hardware; to avoid a next private read communication issue if a previous private read message to the target x was stored in the C-FIFO. 19 1 read-write DIS DA[6:0] write disabled (when the I3C is acting as controller) When the I3C is acting as controller, once that software set IBIACK=1 or CRACK=1, this read bit is set by hardware (i.e. DIS=1) to lock the configured DA[6:0] and IBIDEN values. Then, to be able to next modify DA[6:0] or IBIDEN, the software must wait for this field DIS to be de-asserted by hardware (i.e. polling on DIS=0) before modifying these two assigned values to the target x. Indeed, the target may be requesting an IBI or a controller-role meanwhile the controller intends to modify DA[6:0] or IBIDEN. 31 1 read-only DEVR2 DEVR2 I3C device 2 characteristics register 0x68 0x20 0x00000000 0xFFFFFFFF DA assigned I3C dynamic address to target x (when the I3C is acting as controller) When the I3C is acting as controller, this field should be written by software to store the 7-bit dynamic address that the controller sends via a broadcast ENTDAA or a direct SETNEWDA CCC which has been acknowledged by the target x. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. 1 7 read-write IBIACK IBI request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a IBI request from target x: - After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another IBI request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the controller logs the IBI payload data, if any, depending on I3C_DEVRx.IBIDEN. - The software is notified by the IBI flag (i.e. I3C_EVR.IBIF=1) and/or the corresponding interrupt if enabled; - Independently from IBIACK configuration for this or other devices, further IBI request(s) are NACKed until IBI request flag (i.e. I3C_EVR.IBIF) and controller-role request flag (i.e. I3C_EVR.CRF) are both cleared. 16 1 read-write CRACK controller-role request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a controller-role request from target x: After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another controller-role request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the message continues as initially programmed. The software is notified by the controller-role request flag (i.e. I3C_EVR.CRF=1) and/or the corresponding interrupt if enabled; For effectively granting the controller-role to the requesting secondary controller, software should issue a GETACCCR (formerly known as GETACCMST), followed by a STOP. - Independently of CRACK configuration for this or other devices, further controller-role request(s) are NACKed until controller-role request flag (i.e. I3C_EVR.CRF) and IBI flag (i.e. I3C_EVR.IBIF) are both cleared. 17 1 read-write IBIDEN IBI data enable (when the I3C is acting as controller) When the I3C is acting as controller, this bit should be written by software to store the BCR[2] bit as received from the target x during broadcast ENTDAA or direct GETBCR CCC via the received I3C_RDR. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. 18 1 read-write SUSP suspend/stop I3C transfer on received IBI (when the I3C is acting as controller) When the I3C is acting as controller, this bit is used to receive an IBI from target x with pending read notification feature (i.e. with received MDB[7:5]=3'b101). If this bit is set, when an IBI is received (i.e. I3C_EVR.IBIF=1), a Stop is emitted on the I3C bus and the C-FIFO is automatically flushed by hardware; to avoid a next private read communication issue if a previous private read message to the target x was stored in the C-FIFO. 19 1 read-write DIS DA[6:0] write disabled (when the I3C is acting as controller) When the I3C is acting as controller, once that software set IBIACK=1 or CRACK=1, this read bit is set by hardware (i.e. DIS=1) to lock the configured DA[6:0] and IBIDEN values. Then, to be able to next modify DA[6:0] or IBIDEN, the software must wait for this field DIS to be de-asserted by hardware (i.e. polling on DIS=0) before modifying these two assigned values to the target x. Indeed, the target may be requesting an IBI or a controller-role meanwhile the controller intends to modify DA[6:0] or IBIDEN. 31 1 read-only DEVR3 DEVR3 I3C device 3 characteristics register 0x6C 0x20 0x00000000 0xFFFFFFFF DA assigned I3C dynamic address to target x (when the I3C is acting as controller) When the I3C is acting as controller, this field should be written by software to store the 7-bit dynamic address that the controller sends via a broadcast ENTDAA or a direct SETNEWDA CCC which has been acknowledged by the target x. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. 1 7 read-write IBIACK IBI request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a IBI request from target x: - After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another IBI request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the controller logs the IBI payload data, if any, depending on I3C_DEVRx.IBIDEN. - The software is notified by the IBI flag (i.e. I3C_EVR.IBIF=1) and/or the corresponding interrupt if enabled; - Independently from IBIACK configuration for this or other devices, further IBI request(s) are NACKed until IBI request flag (i.e. I3C_EVR.IBIF) and controller-role request flag (i.e. I3C_EVR.CRF) are both cleared. 16 1 read-write CRACK controller-role request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a controller-role request from target x: After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another controller-role request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the message continues as initially programmed. The software is notified by the controller-role request flag (i.e. I3C_EVR.CRF=1) and/or the corresponding interrupt if enabled; For effectively granting the controller-role to the requesting secondary controller, software should issue a GETACCCR (formerly known as GETACCMST), followed by a STOP. - Independently of CRACK configuration for this or other devices, further controller-role request(s) are NACKed until controller-role request flag (i.e. I3C_EVR.CRF) and IBI flag (i.e. I3C_EVR.IBIF) are both cleared. 17 1 read-write IBIDEN IBI data enable (when the I3C is acting as controller) When the I3C is acting as controller, this bit should be written by software to store the BCR[2] bit as received from the target x during broadcast ENTDAA or direct GETBCR CCC via the received I3C_RDR. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. 18 1 read-write SUSP suspend/stop I3C transfer on received IBI (when the I3C is acting as controller) When the I3C is acting as controller, this bit is used to receive an IBI from target x with pending read notification feature (i.e. with received MDB[7:5]=3'b101). If this bit is set, when an IBI is received (i.e. I3C_EVR.IBIF=1), a Stop is emitted on the I3C bus and the C-FIFO is automatically flushed by hardware; to avoid a next private read communication issue if a previous private read message to the target x was stored in the C-FIFO. 19 1 read-write DIS DA[6:0] write disabled (when the I3C is acting as controller) When the I3C is acting as controller, once that software set IBIACK=1 or CRACK=1, this read bit is set by hardware (i.e. DIS=1) to lock the configured DA[6:0] and IBIDEN values. Then, to be able to next modify DA[6:0] or IBIDEN, the software must wait for this field DIS to be de-asserted by hardware (i.e. polling on DIS=0) before modifying these two assigned values to the target x. Indeed, the target may be requesting an IBI or a controller-role meanwhile the controller intends to modify DA[6:0] or IBIDEN. 31 1 read-only DEVR4 DEVR4 I3C device 4 characteristics register 0x70 0x20 0x00000000 0xFFFFFFFF DA assigned I3C dynamic address to target x (when the I3C is acting as controller) When the I3C is acting as controller, this field should be written by software to store the 7-bit dynamic address that the controller sends via a broadcast ENTDAA or a direct SETNEWDA CCC which has been acknowledged by the target x. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. 1 7 read-write IBIACK IBI request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a IBI request from target x: - After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another IBI request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the controller logs the IBI payload data, if any, depending on I3C_DEVRx.IBIDEN. - The software is notified by the IBI flag (i.e. I3C_EVR.IBIF=1) and/or the corresponding interrupt if enabled; - Independently from IBIACK configuration for this or other devices, further IBI request(s) are NACKed until IBI request flag (i.e. I3C_EVR.IBIF) and controller-role request flag (i.e. I3C_EVR.CRF) are both cleared. 16 1 read-write CRACK controller-role request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a controller-role request from target x: After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another controller-role request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the message continues as initially programmed. The software is notified by the controller-role request flag (i.e. I3C_EVR.CRF=1) and/or the corresponding interrupt if enabled; For effectively granting the controller-role to the requesting secondary controller, software should issue a GETACCCR (formerly known as GETACCMST), followed by a STOP. - Independently of CRACK configuration for this or other devices, further controller-role request(s) are NACKed until controller-role request flag (i.e. I3C_EVR.CRF) and IBI flag (i.e. I3C_EVR.IBIF) are both cleared. 17 1 read-write IBIDEN IBI data enable (when the I3C is acting as controller) When the I3C is acting as controller, this bit should be written by software to store the BCR[2] bit as received from the target x during broadcast ENTDAA or direct GETBCR CCC via the received I3C_RDR. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. 18 1 read-write SUSP suspend/stop I3C transfer on received IBI (when the I3C is acting as controller) When the I3C is acting as controller, this bit is used to receive an IBI from target x with pending read notification feature (i.e. with received MDB[7:5]=3'b101). If this bit is set, when an IBI is received (i.e. I3C_EVR.IBIF=1), a Stop is emitted on the I3C bus and the C-FIFO is automatically flushed by hardware; to avoid a next private read communication issue if a previous private read message to the target x was stored in the C-FIFO. 19 1 read-write DIS DA[6:0] write disabled (when the I3C is acting as controller) When the I3C is acting as controller, once that software set IBIACK=1 or CRACK=1, this read bit is set by hardware (i.e. DIS=1) to lock the configured DA[6:0] and IBIDEN values. Then, to be able to next modify DA[6:0] or IBIDEN, the software must wait for this field DIS to be de-asserted by hardware (i.e. polling on DIS=0) before modifying these two assigned values to the target x. Indeed, the target may be requesting an IBI or a controller-role meanwhile the controller intends to modify DA[6:0] or IBIDEN. 31 1 read-only MAXRLR MAXRLR I3C maximum read length register 0x90 0x20 0x00000000 0xFFFFFFFF MRL maximum data read length (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 and updated by hardware on the reception of SETMRL command (with potentially also updated IBIP[2:0]). Software is notified of a MRL update by the I3C_EVR.MRLUPF and the corresponding interrupt if enabled. This field is used by hardware to return the value on the I3C bus when the target receives a GETMRL CCC. 0 16 read-write IBIP IBI payload data size, in bytes (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 to set the number of data bytes to be sent to the controller after an IBI request has been acknowledged.This field may be updated by hardware on the reception of SETMRL command (which potentially also updated IBIP[2:0]). Software is notified of a MRL update by the I3C_EVR.MRLUPF and the corresponding interrupt if enabled. others: same as 100 16 3 read-write MAXWLR MAXWLR I3C maximum write length register 0x94 0x20 0x00000000 0xFFFFFFFF MWL maximum data write length (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 and updated by hardware on the reception of SETMWL command. Software is notified of a MWL update by the I3C_EVR.MWLUPF and the corresponding interrupt if enabled. This field is used by hardware to return the value on the I3C bus when the target receives a GETMWL CCC. 0 16 read-write TIMINGR0 TIMINGR0 I3C timing register 0 0xA0 0x20 0x00000000 0xFFFFFFFF SCLL_PP SCL low duration in I3C push-pull phases, in number of kernel clocks cycles: tSCLL_PP = (SCLL_PP + 1) x tI3CCLK SCLL_PP is used to generate tLOW (I3C) timing. 0 8 read-write SCLH_I3C SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles: tSCLH_I3C = (SCLH_I3C + 1) x tI3CCLK SCLH_I3C is used to generate both tHIGH (I3C) and tHIGH_MIXED timings. 8 8 read-write SCLL_OD SCL low duration in open-drain phases, used for legacy I2C commands and for I3C open-drain phases (address header phase following a START, not a Repeated START), in number of kernel clocks cycles: tSCLL_OD = (SCLL_OD + 1) x tI3CCLK SCLL_OD is used to generate both tLOW (I2C) and tLOW_OD timings (max. of the two). 16 8 read-write SCLH_I2C SCL high duration, used for legacy I2C commands, in number of kernel clocks cycles: tSCLH_I2C = (SCLH_I2C + 1) x tI3CCLK SCLH_I2C is used to generate tHIGH (I2C) timing. 24 8 read-write TIMINGR1 TIMINGR1 I3C timing register 1 0xA4 0x20 0x00000000 0xFFFFFFFF AVAL number of kernel clock cycles, that is used whatever I3C is acting as controller or target, to set the following MIPI I3C timings, like bus available condition time: When the I3C is acting as target: for bus available condition time: it must wait for (bus available condition) time to be elapsed after a stop and before issuing a start request for an IBI or a controller-role request (i.e. bus free condition is sustained for at least tAVAL). refer to MIPI timing tAVAL = 1 s. This timing is defined by: tAVAL = (AVAL[7:0] + 2) x tI3CCLK for bus idle condition time: it must wait for (bus idle condition) time to be elapsed after that both SDA and SCL are continuously high and stable before issuing a hot-join event. Refer to MIPI v1.1 timing tIDLE = 200 s . This timing is defined by: tIDLE = (AVAL[7:0] + 2) x 200 x tI3CCLK When the I3C is acting as controller, it can not stall the clock beyond a maximum stall time (i.e. stall the SCL clock low), as follows: on first bit of assigned address during dynamic address assignment: it can not stall the clock beyond the MIPI timing tSTALLDAA = 15 ms. This timing is defined by: tSTALLDAA = (AVAL[7:0] + 1) x 15000 x tI3CCLK on ACK/NACK phase of I3C/I2C transfer, on parity bit of write data transfer, on transition bit of I3C read transfer: it can not stall the clock beyond the MIPI timing tSTALL = 100 s. This timing is defined by: tSTALL = (AVAL[7:0] + 1) x 100 x tI3CCLK Whatever the I3C is acting as controller or as (controller-capable) target, during a controller-role hand-off procedure: The new controller must wait for a time (refer to MIPI timing tNEWCRLock) before pulling SDA low (i.e. issuing a start). And the active controller must wait for the same time while monitoring new controller and before testing the new controller by pulling SDA low. This time to wait is dependent on the defined I3C_TIMINGR1.ANSCR[1:0], as follows: If ASNCR[1:0]=00: tNEWCRLock = (AVAL[7:0] + 1) x tI3CCLK If ASNCR[1:0]=01: tNEWCRLock = (AVAL[7:0] + 1) x 100 x tI3CCLK If ASNCR[1:0]=10: tNEWCRLock = (AVAL[7:0] + 1) x 2000 x tI3CCLK If ASNCR[1:0]=11: tNEWCRLock = (AVAL[7:0] + 1) x 50000 x tI3CCLK 0 8 read-write ASNCR activity state of the new controller (when I3C is acting as active- controller) This field indicates the time to wait before being accessed as new target, refer to the other field AVAL[7:0]. This field can be modified only when the I3C is acting as controller. 8 2 read-write FREE number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C is acting as controller) 16 7 read-write SDA_HD SDA hold time (when the I3C is acting as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tHD_PP): 28 1 read-write TIMINGR2 TIMINGR2 I3C timing register 2 0xA8 0x20 0x00000000 0xFFFFFFFF STALLT Controller clock stall on T-bit phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to prepare data to be sent. 0 1 read-write STALLD controller clock stall on PAR phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to read received data. 1 1 read-write STALLC controller clock stall on PAR phase of CCC enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase of common command code (before 9th bit). This allows the target to decode the command. 2 1 read-write STALLA controller clock stall enable on ACK phase The SCL is stalled (during tSCLL_STALLas defined by STALL) in the address ACK/NACK phase (before 9th bit). This allows the target to prepare data or the controller to respond to target interrupt. 3 1 read-write STALL controller clock stall time, in number of kernel clock cycles tSCLL_STALL = STALL x tI3CCLK 8 8 read-write BCR BCR I3C bus characteristics register 0xC0 0x20 0x00000000 0xFFFFFFFF BCR0 max data speed limitation 0 1 read-write BCR2 in-band interrupt (IBI) payload 2 1 read-write BCR6 controller capable 6 1 read-write DCR DCR I3C device characteristics register 0xC4 0x20 0x00000000 0xFFFFFFFF DCR device characteristics ID others: ID to describe the type of the I3C sensor/device Note: The latest MIPI DCR ID assignments are available at: https://www.mipi.org/MIPI_I3C_device_characteristics_register 0 8 read-write GETCAPR GETCAPR I3C get capability register 0xC8 0x20 0x00000000 0xFFFFFFFF CAPPEND IBI MDB support for pending read notification This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates the support (or not) of the pending read notification via the IBI MDB[7:0] value. This bit is used to return the GETCAP3 byte in response to the GETCAPS CCC format 1. 14 1 read-write CRCAPR CRCAPR I3C controller-role capability register 0xCC 0x20 0x00000000 0xFFFFFFFF CAPDHOFF delayed controller-role hand-off This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates if this target I3C may need additional time to process a controller-role hand-off requested by the current controller. This bit is used to return the CRCAP2 byte in response to the GETCAPS CCC format 2. 3 1 read-write CAPGRP group management support (when acting as controller) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates if the I3C is able to support group management when it acts as a controller (after controller-role hand-off) via emitted DEFGRPA, RSTGRPA, and SETGRPA CCC. This bit is used to return the CRCAP1 byte in response to the GETCAPS CCC format 2. 9 1 read-write GETMXDSR GETMXDSR I3C get capability register 0xD0 0x20 0x00000000 0xFFFFFFFF HOFFAS controller hand-off activity state This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates in which initial activity state the (other) current controller should expect the I3C bus after a controller-role hand-off to this controller-capable I3C, when returning the defining byte CRHDLY (0x91) to a GETMXDS CCC. This 2-bit field is used to return the CRHDLY1 byte in response to the GETCAPS CCC format 3, in order to state which is the activity state of this I3C when becoming controller after a controller-role hand-off, and consequently the time the former controller should wait before testing this I3C to be confirmed its ownership. 0 2 read-write FMT GETMXDS CCC format This field is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates how is returned the GETMXDS format 1 (without MaxRdTurn) and format 2 (with MaxRdTurn). This bit is used to return the 2-byte format 1 (MaxWr, MaxRd) or 5-byte format 2 (MaxWr, MaxRd, 3-byte MaxRdTurn) byte in response to the GETCAPS CCC. - 3-byte MaxRdTurn is returned with MSB=0, middle byte=0 and LSB=RDTURN[7:0]. - Max read turnaround time is less than 256 s. - 3-byte MaxRdTurn is returned with MSB=0, middle byte=RDTURN[7:0] and LSB=0. - Max read turnaround time is between 256 s and 65535 s - 3-byte MaxRdTurn is returned with MSB=RDTURN[7:0], middle byte=0 and LSB=0. - Max read turnaround time is between 65535 s and 16 s. 8 2 read-write RDTURN programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and writes the value of the selected byte (via the FMT[1:0] field) of the 3-byte MaxRdTurn which is returned in response to the GETMXDS CCC format 2 to encode the maximum read turnaround time. 16 8 read-write TSCO clock-to-data turnaround time (tSCO) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and is used to specify the clock-to-data turnaround time tSCO (vs the value of 12 ns). This bit is used by the hardware in response to the GETMXDS CCC to return the encoded clock-to-data turnaround time via the returned MaxRd[5:3] bits. 24 1 read-write EPIDR EPIDR I3C extended provisioned ID register 0xD4 0x20 0x02080000 0xFFFFFFFF MIPIID 4-bit MIPI Instance ID This field is written by software to set and identify individually each instance of this I3C IP with a specific number on a single I3C bus. This field represents the bits[15:12] of the 48-bit provisioned ID. Note: The bits[11:0] of the provisioned ID may be 0. 12 4 read-write IDTSEL provisioned ID type selector This field is set as 0 i.e. vendor fixed value. This field represents the bit[32] of the 48-bit provisioned ID. Note: The bits[31:16] of the provisioned ID may be 0. 16 1 read-only MIPIMID 15-bit MIPI manufacturer ID This read field is the 15-bit STMicroelectronics MIPI ID i.e. 0x0104. This field represents the bits[47:33] of the 48-bit provisioned ID. 17 15 read-only I3C2 0x44003000 I3C2_EV I3C2 event interrupt 131 I3C2_ER I3C2 error interrupt 132 LPTIM1 Low power timer LPTIM 0x44004400 0x0 0x400 registers LPTIM1 LPTIM1 global interrupt 64 ISR_output ISR_output LPTIM1 interrupt and status register [alternate] 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF Compare 1 interrupt flag If channel CC1 is configured as output: The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. 0 1 read-only ARRM Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register's value reached the LPTIM_ARR register's value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. 1 1 read-only EXTTRIG External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. 2 1 read-only CMP1OK Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. 3 1 read-only ARROK Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. 4 1 read-only UP Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 5 1 read-only DOWN Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 6 1 read-only UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. 7 1 read-only REPOK Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. 8 1 read-only CC2IF Compare 2 interrupt flag If channel CC2 is configured as output: The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 9 1 read-only CMP2OK Compare register 2 update OK CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 19 1 read-only DIEROK Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. 24 1 read-only ISR_intput ISR_intput LPTIM1 interrupt and status register [alternate] ISR_output 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF capture 1 interrupt flag If channel CC1 is configured as input: CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. 0 1 read-only ARRM Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register's value reached the LPTIM_ARR register's value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. 1 1 read-only EXTTRIG External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. 2 1 read-only ARROK Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. 4 1 read-only UP Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 5 1 read-only DOWN Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 6 1 read-only UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. 7 1 read-only REPOK Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. 8 1 read-only CC2IF Capture 2 interrupt flag If channel CC2 is configured as input: CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 9 1 read-only CC1OF Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to . 12 1 read-only CC2OF Capture 2 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 13 1 read-only DIEROK Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. 24 1 read-only ICR_output ICR_output LPTIM1 interrupt clear register [alternate] 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. 0 1 write-only ARRMCF Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register 1 1 write-only EXTTRIGCF External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register 2 1 write-only CMP1OKCF Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. 3 1 write-only ARROKCF Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register 4 1 write-only UPCF Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 5 1 write-only DOWNCF Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 6 1 write-only UECF Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. 7 1 write-only REPOKCF Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. 8 1 write-only CC2CF Capture/compare 2 clear flag Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 9 1 write-only CMP2OKCF Compare register 2 update OK clear flag Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 19 1 write-only DIEROKCF Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. 24 1 write-only ICR_intput ICR_intput LPTIM interrupt clear register ICR_output 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. 0 1 write-only ARRMCF Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register 1 1 write-only EXTTRIGCF External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register 2 1 write-only ARROKCF Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register 4 1 write-only UPCF Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 5 1 write-only DOWNCF Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 6 1 write-only UECF Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. 7 1 write-only REPOKCF Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. 8 1 write-only CC2CF Capture/compare 2 clear flag Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 9 1 write-only CC1OCF Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to . 12 1 write-only CC2OCF Capture/compare 2 over-capture clear flag Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 13 1 write-only DIEROKCF Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. 24 1 write-only DIER_output DIER_output LPTIM1 interrupt enable register [alternate] 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write CMP1OKIE Compare register 1 update OK interrupt enable 3 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 5 1 read-write DOWNIE Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 9 1 read-write CMP2OKIE Compare register 2 update OK interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 19 1 read-write UEDE Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to . 23 1 read-write DIER_intput DIER_intput LPTIM interrupt enable register DIER_output 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 5 1 read-write DOWNIE Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 9 1 read-write CC1OIE Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to . 12 1 read-write CC2OIE Capture/compare 2 over-capture interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 13 1 read-write CC1DE Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to . 16 1 read-write UEDE Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to . 23 1 read-write CC2DE Capture/compare 2 DMA request enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to . 25 1 read-write CFGR CFGR LPTIM configuration register 0xC 0x20 0x00000000 0xFFFFFFFF CKSEL Clock selector The CKSEL bit selects which clock source the LPTIM uses: 0 1 read-write CKPOL Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. 1 2 read-write CKFLT Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 3 2 read-write TRGFLT Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 6 2 read-write PRESC Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 9 3 read-write TRIGSEL Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. 13 3 read-write TRIGEN Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 17 2 read-write TIMOUT Timeout enable The TIMOUT bit controls the Timeout feature 19 1 read-write WAVE Waveform shape The WAVE bit controls the output shape 20 1 read-write WAVPOL Waveform shape polarity The WAVPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to . 21 1 read-write PRELOAD Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality 22 1 read-write COUNTMODE counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: 23 1 read-write ENC Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . 24 1 read-write CR CR LPTIM control register 0x10 0x20 0x00000000 0xFFFFFFFF ENABLE LPTIM enable The ENABLE bit is set and cleared by software. 0 1 read-write SNGSTRT LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. 1 1 read-write CNTSTRT Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. 2 1 read-write COUNTRST Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. 3 1 read-write RSTARE Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. 4 1 read-write CCR1 CCR1 LPTIM compare register 1 0x14 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 becomes read-only, it contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. 0 16 read-write ARR ARR LPTIM autoreload register 0x18 0x20 0x00000001 0xFFFFFFFF ARR Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. 0 16 read-write CNT CNT LPTIM counter register 0x1C 0x20 0x00000000 0xFFFFFFFF CNT Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. 0 16 read-only RCR RCR LPTIM repetition register 0x28 0x20 0x00000000 0xFFFFFFFF REP Repetition register value REP is the repetition value for the LPTIM. 0 8 read-write CCMR1 CCMR1 LPTIM capture/compare mode register 1 0x2C 0x20 0x00000000 0xFFFFFFFF CC1SEL Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. 0 1 read-write CC1E Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. 1 1 read-write CC1P Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. 2 2 read-write IC1PSC Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). 8 2 read-write IC1F Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. 12 2 read-write CC2SEL Capture/compare 2 selection This bitfield defines the direction of the channel, input (capture) or output mode. 16 1 read-write CC2E Capture/compare 2 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM_CCR2) or not. 17 1 read-write CC2P Capture/compare 2 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC2 polarity for capture operations. 18 2 read-write IC2PSC Input capture 2 prescaler This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). 24 2 read-write IC2F Input capture 2 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. 28 2 read-write CCR2 CCR2 LPTIM compare register 2 0x34 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the capture/compare 2 register. Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 2 contains the value to be compared to the counter LPTIM_CNT and signaled on OC2 output. If channel CC2 is configured as input: CCR2 becomes read-only, it contains the counter value transferred by the last input capture 2 event. The LPTIM_CCR2 register is read-only and cannot be programmed. 0 16 read-write LPTIM2 0x40009400 LPTIM2 LPTIM2 global interrupt 70 LPUART Universal synchronous asynchronous receiver transmitter LPUART 0x44002400 0x0 0x400 registers LPUART1 LPUART1 global interrupt 63 CR1 CR1_enabled LPUART control register 1 [alternate] 0x0 0x20 0x00000000 0xFFFFFFFF UE LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM LPUART enable in low-power mode When this bit is cleared, the LPUART cannot wake up the MCU from low-power mode. When this bit is set, the LPUART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. 1 1 read-write UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable This bit is set and cleared by software. 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable This bit is set and cleared by software. 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the LPUART is disabled (UE=0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the LPUART is disabled (UE=0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wakeup method This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). This bit can only be written when the LPUART is disabled (UE=0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 DEDT Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UE=0). 16 5 read-write 0 31 DEAT Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer . This bitfield can only be written when the LPUART is disabled (UE=0). 21 5 read-write 0 31 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00': 1 Start bit, 8 Data bits, n Stop bit M[1:0] = '01': 1 Start bit, 9 Data bits, n Stop bit M[1:0] = '10': 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UE=0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable This bit is set and cleared by software. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable This bit is set and cleared by software. 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO Full interrupt enable This bit is set and cleared by software. 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 LPUART control register 2 0x4 0x20 0x00000000 0xFFFFFFFF ADDM7 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the LPUART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 STOP STOP bits These bits are used for programming the stop bits. This bitfield can only be written when the LPUART is disabled (UE=0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop2 2 stop bit 2 SWAP Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the LPUART is disabled (UE=0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the LPUART is disabled (UE=0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ADD Address of the LPUART node These bits give the address of the LPUART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0). 24 8 read-write 0 255 CR3 CR3 LPUART control register 3 0x8 0x20 0x00000000 0xFFFFFFFF EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NE=1 in the LPUART_ISR register). 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 HDSEL Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the LPUART is disabled (UE=0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 DMAR DMA enable receiver This bit is set/reset by software 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter This bit is set/reset by software 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable This bit can only be written when the LPUART is disabled (UE=0). 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable This bit can only be written when the LPUART is disabled (UE=0) 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 OVRDIS Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data. 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA Disable on Reception Error This bit can only be written when the LPUART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the LPUART is disabled (UE=0). 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection This bit can only be written when the LPUART is disabled (UE=0). 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 WUS Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the LPUART is disabled (UE=0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 2386. 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 WUFIE Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 2386. 22 1 read-write WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 TXFTIE TXFIFO threshold interrupt enable This bit is set and cleared by software. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 RXFTCFG Receive FIFO threshold configuration Remaining combinations: Reserved. 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration Remaining combinations: Reserved. 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR LPUART baud rate register 0xC 0x20 0x00000000 0xFFFFFFFF BRR LPUART baud rate division (LPUARTDIV) 0 20 read-write 0 1048575 RQR RQR LPUART request register 0x18 0x20 0x00000000 0xFFFFFFFF SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request Writing 1 to this bit clears the RXNE flag. This enables discarding the received data without reading it, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR_enabled LPUART interrupt and status register [alternate] 0x1C 0x20 0x008000C0 0xFFFFFFFF PE Parity error This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR. 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR. 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Start bit noise detection flag This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. This error is associated with the character in the LPUART_RDR. 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXFNEIE=1 or EIE = 1 in the LPUART_CR1 register. Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXFNEIE=1 in the LPUART_CR1 register. 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete This bit indicates that the last data written in the LPUART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXFE is set. When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. An interrupt is generated if TCIE=1 in the LPUART_CR1 register. TC bit is cleared by software by writing 1 to the TCCF in the LPUART_ICR register or by writing to the LPUART_TDR register. 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). An interrupt is generated if the TXFNFIE bit =1 in the LPUART_CR1 register. Note: This bit is used during single buffer transmission. 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 CTSIF CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIE=1 in the LPUART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIE=1in the LPUART_CR1 register. 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wakeup from Mute mode This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. 19 1 read-only RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 WUF Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIE=1 in the LPUART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 20 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the LPUART_CR1 register, in order to respect the TE=0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. 22 1 read-only TXFE TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the LPUART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the LPUART_CR1 register. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO Full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the LPUART_RDR register. An interrupt is generated if the RXFFIE bit =1 in the LPUART_CR1 register. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 RXFT RXFIFO threshold flag This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the LPUART_CR3 register. 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the LPUART_CR3 register. 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR LPUART interrupt flag clear register 0x20 0x20 0x00000000 0xFFFFFFFF PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the LPUART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the LPUART_ISR register. 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag Writing 1 to this bit clears the NE flag in the LPUART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag Writing 1 to this bit clears the ORE flag in the LPUART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TCCF Transmission complete clear flag Writing 1 to this bit clears the TC flag in the LPUART_ISR register. 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 CTSCF CTS clear flag Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register. 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 CMCF Character match clear flag Writing 1 to this bit clears the CMF flag in the LPUART_ISR register. 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 WUCF Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 2386. 20 1 write-only oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 RDR RDR LPUART receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RDR Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR LPUART transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TDR Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1. 0 9 read-write 0 511 PRESC PRESC LPUART prescaler register 0x2C 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler The LPUART input clock can be divided by a prescaler: Remaining combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. 0 4 read-write PRESCALER Div1 /1 0 Div2 /2 1 Div4 /4 2 Div6 /6 3 Div8 /8 4 Div10 /10 5 Div12 /12 6 Div16 /16 7 Div32 /32 8 Div64 /64 9 Div128 /128 10 Div256 /256 11 OPAMP1 Operational amplifiers OPAMP 0x40003400 0x0 0x400 registers OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 0x20 0x00000000 0xFFFFFFFF OPAEN Operational amplifier Enable Note: If OPAMP1 is unconnected in a specific package, it must remain disabled (keep OPAMP1_CSR register default value). 0 1 read-write FORCE_VP Force internal reference on VP (reserved for test) 1 1 read-write VP_SEL Non inverted input selection 2 2 read-write VM_SEL Inverting input selection 5 2 read-write OPAHSM Operational amplifier high-speed mode The operational amplifier must be disable to change this configuration. 8 1 read-write CALON Calibration mode enabled 11 1 read-write CALSEL Calibration selection It is used to select the offset calibration bus used to generate the internal reference voltage when CALON = 1 or FORCE_VP= 1. 12 2 read-write PGA_GAIN Operational amplifier Programmable amplifier gain value 14 4 read-write USERTRIM User trimming enable This bit allows to switch from 'factory' AOP offset trimmed values to 'user' AOP offset trimmed values This bit is active for both mode normal and high-power. 18 1 read-write TSTREF OPAMP calibration reference voltage output control (reserved for test) 29 1 read-write CALOUT Operational amplifier calibration output OPAMP output status flag. During the calibration mode, OPAMP is used as comparator. 30 1 read-only OPAMP1_OTR OPAMP1_OTR OPAMP1 trimming register in normal mode 0x4 0x20 0x00000000 0xFFFF0000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 read-write TRIMOFFSETP Trim for PMOS differential pairs 8 5 read-write OPAMP1_HSOTR OPAMP1_HSOTR OPAMP1 trimming register in high-speed mode 0x8 0x20 0x00000000 0xFFFF0000 TRIMHSOFFSETN High-speed mode trim for NMOS differential pairs 0 5 read-write TRIMHSOFFSETP High-speed mode trim for PMOS differential pairs 8 5 read-write OPAMP_OR OPAMP_OR OPAMP option register 0xC 0x20 0x00000000 0xFFFFFFFF PWR Power control PWR 0x44020800 0x0 0x400 registers PMCR PMCR PWR power mode control register 0x0 0x20 0x0000000C 0xFFFFFFFF LPMS low-power mode selection This bit defines the Deepsleep mode. 0 1 read-write LPMS StopMode Keeps Stop mode when entering DeepSleep 0 StandbyMode Allows Standby mode when entering DeepSleep 1 SVOS system Stop mode voltage scaling selection These bits control the V CORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. 2 2 read-write SVOS Scale5 SVOS5 scale 5 1 Scale4 SVOS4 scale 4 2 Scale3 SVOS3 scale 3 3 CSSF clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. 7 1 read-write CSSF Clear STOPF and SBF flags cleared 1 FLPS Flash memory low-power mode in Stop mode This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode. Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode. 9 1 read-write FLPS NormalMode Flash memory remains in normal mode when the system enters Stop mode 0 LowPowerMode Flash memory enters low-power mode when the system enters Stop mode 1 BOOSTE analog switch V BOOST control This bit enables the booster to guarantee the analog switch AC performance when the V DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V DD supply voltage can be monitored through the PVD and the PLS bits. 12 1 read-write BOOSTE Disabled Booster disabled 0 Enabled Booster enabled if analog voltage ready (AVD_READY = 1) 1 AVD_READY analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected V DDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored (ALS bits). 13 1 read-write AVD_READY NotReady Peripheral analog voltage VDDA not ready (default) 0 Ready Peripheral analog voltage VDDA ready 1 SRAM2SO AHB SRAM2 shut-off in Stop mode. 25 1 read-write SRAM2SO Kept AHB RAM2 content is kept in Stop mode 0 Lost AHB RAM2 content is lost in Stop mode 1 SRAM1SO AHB SRAM1 shut-off in Stop mode 26 1 read-write SRAM1SO Kept AHB RAM1 content is kept in Stop mode 0 Lost AHB RAM1 content is lost in Stop mode 1 PMSR PMSR PWR status register 0x4 0x20 0x00000000 0xFFFFFFFF STOPF Stop flag This bit is set by hardware and cleared only by any reset or by setting the CSSF bit. 5 1 read-only STOPFR NoStopMode System has not been in stop mode 0 StopModePreviouslyEntered System has been in Stop mode 1 SBF System standby flag This bit is set by hardware and cleared only by a POR or by setting the CSSF bit. 6 1 read-only SBFR NoStandbyMode System has not been in standby mode 0 StandbyModePreviouslyEntered System has been in Standby mode 1 VOSCR VOSCR PWR voltage scaling control register 0x10 0x20 0x00000000 0xFFFFFFFF VOS voltage scaling selection according to performance These bits control the V CORE voltage level and allow to obtain the best trade-off between power consumption and performance: - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance. - When increasing the performance, the voltage scaling must be changed before increasing the system frequency. - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. 4 2 read-write VOS VOS3 Scale 3 (default) 0 VOS1 Scale 1 1 VOS2 Scale 2 2 VOS0 Scale 0 3 VOSSR VOSSR PWR voltage scaling status register 0x14 0x20 0x00000008 0xFFFFFFFF VOSRDY Ready bit for V CORE voltage scaling output selection. 3 1 read-only VOSRDYR NotReady Not ready, voltage level below VOS selected level 0 Ready Ready, voltage level at or above VOS selected level 1 ACTVOSRDY Voltage level ready for currently used VOS 13 1 read-only ACTVOSRDYR NotReady VCORE is above or below the current voltage scaling provided by ACTVOS[1:0] 0 Ready VCORE is equal to the current voltage scaling provided by ACTVOS[1:0] 1 ACTVOS voltage output scaling currently applied to V CORE This field provides the last VOS value. 14 2 read-only ACTVOSR VOS3 VOS3 (lowest power) 0 VOS2 VOS2 1 VOS1 VOS1 2 VOS0 VOS0 (highest frequency) 3 BDCR BDCR PWR Backup domain control register 0x20 0x20 0x00000000 0xFFFFFFFF BREN Backup RAM retention in Standby and V BAT modes When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and V BAT modes) is enabled. If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However its content is lost in Standby and V BAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and V BAT modes. 0 1 read-write BREN Disabled Backup regulator enabled; backup RAM content lost in Standby and VBAT modes 0 Enabled Backup regulator disabled; backup RAM content preserved in Standby and VBAT modes 1 MONEN Backup domain voltage and temperature monitoring enable 1 1 read-write MONEN Disabled Backup domain voltage and temperature monitoring disabled 0 Enabled Backup domain voltage and temperature monitoring enabled 1 VBE V BAT charging enable Note: Reset only by POR,. 8 1 read-write VBE Disabled VBAT battery charging disabled 0 Enabled VBAT battery charging enabled 1 VBRS V BAT charging resistor selection 9 1 read-write VBRS Charge5k Charge VBAT through a 5 kâ¦ resistor 0 Charge1k5 Charge VBAT through a 1.5 kâ¦ resistor 1 DBPCR DBPCR PWR disable backup protection control register 0x24 0x20 0x00000000 0xFFFFFFFF DBP Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable write access to these registers. 0 1 read-write DBP Disabled Write access to backup domain disabled 0 Enabled Write access to backup domain enabled 1 BDSR BDSR PWR Backup domain status register 0x28 0x20 0x00000000 0xFFFFFFFF BRRDY backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready. 16 1 read-only BRRDYR NotReady Backup regulator not ready 0 Ready Backup regulator ready 1 VBATL V BAT level monitoring versus low threshold 20 1 read-only VBATLR AboveThreshold Above low threshold level 0 BelowThreshold Equal to or below low threshold level 1 VBATH V BAT level monitoring versus high threshold 21 1 read-only VBATHR BelowThreshold Below high threshold level 0 AboveThreshold Equal to or Above high threshold level 1 TEMPL temperature level monitoring versus low threshold 22 1 read-only TEMPH temperature level monitoring versus high threshold 23 1 read-only SCCR SCCR PWR supply configuration control register 0x30 0x20 0x00000100 0xFFFFFFFF BYPASS power management unit bypass 0 1 read-writeOnce BYPASS InternalRegulator Power management unit normal operation. Use the internal regulator. 0 Bypassed Power management unit bypassed. Use the external power. 1 LDOEN LDO enable The value is set by hardware when the package uses the LDO regulator. 8 1 read-only LDOENR Disabled Package does not use LDO regulator 0 Enabled Package uses LDO regulator 1 VMCR VMCR PWR voltage monitor control register 0x34 0x20 0x00000000 0xFFFFFFFF PVDE PVD enable 0 1 read-write PVDE Disabled PVD Disabled 0 Enabled PVD Enabled 1 PLS programmable voltage detector (PVD) level selection These bits select the voltage threshold detected by the PVD. 1 3 read-write PLS PvdLevel0 PVD level0 (VPVD0 around 1.95 V) 0 PvdLevel1 PVD level1 (VPVD1 around 2.1 V) 1 PvdLevel2 PVD level2 (VPVD2 around 2.25 V) 2 PvdLevel3 PVD level3 (VPVD3 around 2.4 V) 3 PvdLevel4 PVD level4 (VPVD4 around 2.55 V) 4 PvdLevel5 PVD level5 (VPVD5 around 2.7 V) 5 PvdLevel6 PVD level6 (VPVD6 around 2.85 V) 6 PvdIn PVD_IN pin 7 AVDEN peripheral voltage monitor on V DDA enable 8 1 read-write AVDEN Disabled Peripheral voltage monitor on VDDA disabled 0 Enabled Peripheral voltage monitor on VDDA enabled 1 ALS analog voltage detector (AVD) level selection These bits select the voltage threshold detected by the AVD. 9 2 read-write ALS AvdLevel0 AVD level0 (VAVD0 around 1.7 V) 0 AvdLevel1 AVD level1 (VAVD1 around 2.1 V) 1 AvdLevel2 AVD level2 (VAVD2 around 2.5 V) 2 AvdLevel3 AVD level3 (VAVD3 around 2.8 V) 3 VMSR VMSR PWR voltage monitor status register 0x3C 0x20 0x00000000 0xFFFFFFFF AVDO analog voltage detector output on V DDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set. 19 1 read-only AVDOR AboveThreshold VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits 0 BelowThreshold VDDA is lower than the AVD threshold selected with the ALS[2:0] bits 1 VDDIO2RDY voltage detector output on V DDIO2 This bit is set and cleared by hardware. 20 1 read-only VDDIO2RDYR BelowThreshold VDDIO2 is below the threshold of the VDDIO2 voltage monitor 0 AboveThreshold VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor 1 PVDO programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. 22 1 read-only PVDOR AboveThreshold VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits. 0 BelowThreshold VDD is lower than the PVD threshold selected through the PLS[2:0] bits 1 WUSCR WUSCR PWR wakeup status clear register 0x40 0x20 0x00000000 0xFFFFFFFF CWUF1 clear wakeup pin flag for WUFx These bits are always read as 0. 0 1 write-only CWUF1W Clear Writing 1 clears the WUFx wakeup pin flag (bit is cleared to 0 by hardware) 1 CWUF2 clear wakeup pin flag for WUFx These bits are always read as 0. 1 1 write-only CWUF3 clear wakeup pin flag for WUFx These bits are always read as 0. 2 1 write-only CWUF4 clear wakeup pin flag for WUFx These bits are always read as 0. 3 1 write-only CWUF5 clear wakeup pin flag for WUFx These bits are always read as 0. 4 1 write-only WUSR WUSR PWR wakeup status register 0x44 0x20 0x00000000 0xFFFFFFFF WUF1 wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. 0 1 read-only WUF1R NoEventOccurred No wakeup event occurred 0 EventOccurred A wakeup event received from WUFx pin 1 WUF2 wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. 1 1 read-only WUF3 wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. 2 1 read-only WUF4 wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. 3 1 read-only WUF5 wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. 4 1 read-only WUCR WUCR PWR wakeup configuration register 0x48 0x20 0x00000000 0xFFFFFFFF WUPEN1 enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. 0 1 read-write WUPEN1 Disabled An event on WUPx pin does not wakeup the system from Standby mode 0 Enabled A rising or falling edge on WUPx pin wakes up the system from Standby mode 1 WUPEN2 enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. 1 1 read-write WUPEN3 enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. 2 1 read-write WUPEN4 enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. 3 1 read-write WUPEN5 enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. 4 1 read-write WUPP1 wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. 8 1 read-write WUPP1 HighLevel Detection on high level 0 LowLevel Detection on low level 1 WUPP2 wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. 9 1 read-write WUPP3 wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. 10 1 read-write WUPP4 wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. 11 1 read-write WUPP5 wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. 12 1 read-write WUPPUPD1 wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. 16 2 read-write WUPPUPD1 NoPull No pull-up or pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 WUPPUPD2 wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. 18 2 read-write WUPPUPD3 wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. 20 2 read-write WUPPUPD4 wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. 22 2 read-write WUPPUPD5 wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. 24 2 read-write IORETR IORETR PWR I/O retention register 0x50 0x20 0x00000000 0xFFFFFFFF IORETEN IO retention enable: When entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode. Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register. 0 1 read-write IORETEN Disabled IO Retention mode is disabled 0 Enabled IO Retention mode is enabled 1 JTAGIORETEN IO retention enable for JTAG IOs when entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode 16 1 read-write JTAGIORETEN Disabled IO Retention mode is disabled 0 Enabled IO Retention mode is enabled 1 PRIVCFGR PRIVCFGR PWR privilege configuration register 0x104 0x20 0x00000000 0xFFFFFFFF NSPRIV PWR functions privilege configuration Set and reset by software. This bit can be written only by privileged access. 1 1 read-write NSPRIV Unprivileged Read and write to PWR functions can be done by privileged or unprivileged access 0 Privileged Read and write to PWR functions can be done by privileged access only 1 RAMCFG RAMs configuration controller RAMCFG 0x40026000 0x0 0x400 registers RAMCFG RAM configuration global interrupt 5 M1CR M1CR RAMCFG memory 1 control register 0x0 0x20 0x00000000 0xFFFFFFF0 ECCE ECC enable. This bit reset value is defined by the user option bit configuration. When set, it can be cleared by software only after writing the unlock sequence in the RAMCFG_MxECCKEYR register. Note: This bit is reserved and must be kept at reset value in SRAM1 control register. 0 1 read-write ALE Address latch enable Note: This bit is reserved and must be kept at reset value in SRAM1 control register. 4 1 read-write SRAMER SRAM erase This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_MxERKEYR register. Setting this bit starts the SRAM erase. This bit is automatically cleared by hardware at the end of the erase operation. 8 1 read-write M1ISR M1ISR RAMCFG memory interrupt status register 0x8 0x20 0x00000000 0xFFFFFFFF SEDC ECC single error detected and corrected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register. 0 1 read-only DED ECC double error detected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register. 1 1 read-only SRAMBUSY SRAM busy with erase operation Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or product state regression. Refer to Table 9: Internal SRAMs features. 8 1 read-only M1ERKEYR M1ERKEYR RAMCFG memory 1 erase key register 0x28 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection. 0 8 write-only M2CR M2CR RAMCFG memory 2 control register 0x40 0x20 0x00000000 0xFFFFFFF0 ECCE ECC enable. This bit reset value is defined by the user option bit configuration. When set, it can be cleared by software only after writing the unlock sequence in the RAMCFG_MxECCKEYR register. Note: This bit is reserved and must be kept at reset value in SRAM1 control register. 0 1 read-write ALE Address latch enable Note: This bit is reserved and must be kept at reset value in SRAM1 control register. 4 1 read-write SRAMER SRAM erase This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_MxERKEYR register. Setting this bit starts the SRAM erase. This bit is automatically cleared by hardware at the end of the erase operation. 8 1 read-write M2IER M2IER RAMCFG memory 2 interrupt enable register 0x44 0x20 0x00000000 0xFFFFFFFF SEIE ECC single error interrupt enable 0 1 read-write DEIE ECC double error interrupt enable 1 1 read-write ECCNMI Double error NMI This bit is set by software and cleared only by a global RAMCFG reset. Note: if ECCNMI is set, the RAMCFG maskable interrupt is not generated whatever DEIE bit value. 3 1 read-write M2ISR M2ISR RAMCFG memory interrupt status register 0x48 0x20 0x00000000 0xFFFFFFFF SEDC ECC single error detected and corrected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register. 0 1 read-only DED ECC double error detected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register. 1 1 read-only SRAMBUSY SRAM busy with erase operation Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or product state regression. Refer to Table 9: Internal SRAMs features. 8 1 read-only M2SEAR M2SEAR RAMCFG memory 2 ECC single error address register 0x4C 0x20 0x00000000 0xFFFFFFFF ESEA ECC single error address When the ALE bit is set in the RAMCFG_MxCR register, this field is updated with the address corresponding to the ECC single error. 0 32 read-only M2DEAR M2DEAR RAMCFG memory 2 ECC double error address register 0x50 0x20 0x00000000 0xFFFFFFFF EDEA ECC double error address When the ALE bit is set in the RAMCFG_MxCR register, this field is updated with the address corresponding to the ECC double error. 0 32 read-only M2ICR M2ICR RAMCFG memory 2 interrupt clear register 2 0x54 0x20 0x00000000 0xFFFFFFFF CSEDC Clear ECC single error detected and corrected Writing 1 to this flag clears the SEDC bit in the RAMCFG_MxISR register. Reading this flag returns the SEDC value. 0 1 read-write CDED Clear ECC double error detected Writing 1 to this flag clears the DED bit in the RAMCFG_MxISR register. Reading this flag returns the DED value. 1 1 read-write M2WPR1 M2WPR1 RAMCFG memory 2 write protection register 1 0x58 0x20 0x00000000 0xFFFFFFFF P0WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 0 1 read-write P1WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 1 1 read-write P2WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 2 1 read-write P3WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 3 1 read-write P4WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 4 1 read-write P5WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 5 1 read-write P6WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 6 1 read-write P7WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 7 1 read-write P8WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 8 1 read-write P9WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 9 1 read-write P10WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 10 1 read-write P11WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 11 1 read-write P12WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 12 1 read-write P13WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 13 1 read-write P14WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 14 1 read-write P15WP SRAM2 1-Kbyte page y write protection These bits are set by software and cleared only by a global RAMCFG reset. 15 1 read-write M2ECCKEYR M2ECCKEYR RAMCFG memory 2 ECC key register 0x64 0x20 0x00000000 0xFFFFFFFF ECCKEY ECC write protection key The following steps are required to unlock the write protection of the ECCE bit in the RAMCFG_MxCR register. 1) Write 0xAE into ECCKEY[7:0]. 2) Write 0x75 into ECCKEY[7:0]. Note: Writing a wrong key reactivates the write protection. 0 8 write-only M2ERKEYR M2ERKEYR RAMCFG memory 2 erase key register 0x68 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection. 0 8 write-only M3IER M3IER RAMCFG memory 3 interrupt enable register 0x84 0x20 0x00000000 0xFFFFFFFF SEIE ECC single error interrupt enable 0 1 read-write DEIE ECC double error interrupt enable 1 1 read-write ECCNMI Double error NMI This bit is set by software and cleared only by a global RAMCFG reset. Note: if ECCNMI is set, the RAMCFG maskable interrupt is not generated whatever DEIE bit value. 3 1 read-write M3ISR M3ISR RAMCFG memory interrupt status register 0x88 0x20 0x00000000 0xFFFFFFFF SEDC ECC single error detected and corrected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register. 0 1 read-only DED ECC double error detected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register. 1 1 read-only SRAMBUSY SRAM busy with erase operation Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or product state regression. Refer to Table 9: Internal SRAMs features. 8 1 read-only M3SEAR M3SEAR RAMCFG memory 3 ECC single error address register 0x8C 0x20 0x00000000 0xFFFFFFFF ESEA ECC single error address When the ALE bit is set in the RAMCFG_MxCR register, this field is updated with the address corresponding to the ECC single error. 0 32 read-only M3DEAR M3DEAR RAMCFG memory 3 ECC double error address register 0x90 0x20 0x00000000 0xFFFFFFFF EDEA ECC double error address When the ALE bit is set in the RAMCFG_MxCR register, this field is updated with the address corresponding to the ECC double error. 0 32 read-only M3ICR M3ICR RAMCFG memory 3 interrupt clear register 3 0x94 0x20 0x00000000 0xFFFFFFFF CSEDC Clear ECC single error detected and corrected Writing 1 to this flag clears the SEDC bit in the RAMCFG_MxISR register. Reading this flag returns the SEDC value. 0 1 read-write CDED Clear ECC double error detected Writing 1 to this flag clears the DED bit in the RAMCFG_MxISR register. Reading this flag returns the DED value. 1 1 read-write M3ECCKEYR M3ECCKEYR RAMCFG memory 3 ECC key register 0xA4 0x20 0x00000000 0xFFFFFFFF ECCKEY ECC write protection key The following steps are required to unlock the write protection of the ECCE bit in the RAMCFG_MxCR register. 1) Write 0xAE into ECCKEY[7:0]. 2) Write 0x75 into ECCKEY[7:0]. Note: Writing a wrong key reactivates the write protection. 0 8 write-only M3ERKEYR M3ERKEYR RAMCFG memory 3 erase key register 0xA8 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection. 0 8 write-only M4ERKEYR M4ERKEYR RAMCFG memory 4 erase key register 0xE8 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection. 0 8 write-only M5CR M5CR RAMCFG memory 5 control register 0x100 0x20 0x00000000 0xFFFFFFF0 ECCE ECC enable. This bit reset value is defined by the user option bit configuration. When set, it can be cleared by software only after writing the unlock sequence in the RAMCFG_MxECCKEYR register. Note: This bit is reserved and must be kept at reset value in SRAM1 control register. 0 1 read-write ALE Address latch enable Note: This bit is reserved and must be kept at reset value in SRAM1 control register. 4 1 read-write SRAMER SRAM erase This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_MxERKEYR register. Setting this bit starts the SRAM erase. This bit is automatically cleared by hardware at the end of the erase operation. 8 1 read-write M5IER M5IER RAMCFG memory 5 interrupt enable register 0x104 0x20 0x00000000 0xFFFFFFFF SEIE ECC single error interrupt enable 0 1 read-write DEIE ECC double error interrupt enable 1 1 read-write ECCNMI Double error NMI This bit is set by software and cleared only by a global RAMCFG reset. Note: if ECCNMI is set, the RAMCFG maskable interrupt is not generated whatever DEIE bit value. 3 1 read-write M5ISR M5ISR RAMCFG memory interrupt status register 0x108 0x20 0x00000000 0xFFFFFFFF SEDC ECC single error detected and corrected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register. 0 1 read-only DED ECC double error detected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register. 1 1 read-only SRAMBUSY SRAM busy with erase operation Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or product state regression. Refer to Table 9: Internal SRAMs features. 8 1 read-only M5SEAR M5SEAR RAMCFG memory 5 ECC single error address register 0x10C 0x20 0x00000000 0xFFFFFFFF ESEA ECC single error address When the ALE bit is set in the RAMCFG_MxCR register, this field is updated with the address corresponding to the ECC single error. 0 32 read-only M5DEAR M5DEAR RAMCFG memory 5 ECC double error address register 0x110 0x20 0x00000000 0xFFFFFFFF EDEA ECC double error address When the ALE bit is set in the RAMCFG_MxCR register, this field is updated with the address corresponding to the ECC double error. 0 32 read-only M5ICR M5ICR RAMCFG memory 5 interrupt clear register 5 0x114 0x20 0x00000000 0xFFFFFFFF CSEDC Clear ECC single error detected and corrected Writing 1 to this flag clears the SEDC bit in the RAMCFG_MxISR register. Reading this flag returns the SEDC value. 0 1 read-write CDED Clear ECC double error detected Writing 1 to this flag clears the DED bit in the RAMCFG_MxISR register. Reading this flag returns the DED value. 1 1 read-write M5ECCKEYR M5ECCKEYR RAMCFG memory 5 ECC key register 0x124 0x20 0x00000000 0xFFFFFFFF ECCKEY ECC write protection key The following steps are required to unlock the write protection of the ECCE bit in the RAMCFG_MxCR register. 1) Write 0xAE into ECCKEY[7:0]. 2) Write 0x75 into ECCKEY[7:0]. Note: Writing a wrong key reactivates the write protection. 0 8 write-only M5ERKEYR M5ERKEYR RAMCFG memory 5 erase key register 0x128 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection. 0 8 write-only RCC Reset and clock controller RCC 0x44020C00 0x0 0x400 registers RCC RCC global interrupt 9 CR CR RCC clock control register 0x0 0x20 0x00000023 0xFFFFFFFF HSION HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). 0 1 read-write HSION Off Clock Off 0 On Clock On 1 HSIRDY HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable. 1 1 read-only HSIRDYR NotReady Clock not ready 0 Ready Clock ready 1 HSIKERON HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION. 2 1 read-write HSIDIV HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored. 3 2 read-write HSIDIV Div1 No division 0 Div2 Division by 2 1 Div4 Division by 4 2 Div8 Division by 8 3 HSIDIVF HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. 5 1 read-only HSIDIVFR NotPropagated New HSIDIV ratio has not yet propagated to hsi_ck 0 Propagated HSIDIV ratio has propagated to hsi_ck 1 CSION CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). 8 1 read-write CSIRDY CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request). 9 1 read-only CSIKERON CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION. 10 1 read-write HSI48ON HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode. 12 1 read-write HSI48RDY HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable. 13 1 read-only HSEON HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). 16 1 read-write HSERDY HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. 17 1 read-only HSEBYP HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 18 1 read-write HSEBYP NotBypassed HSE crystal oscillator not bypassed 0 Bypassed HSE crystal oscillator bypassed with external clock 1 HSECSSON HSE clock security system enable Set by software to enable clock security system on HSE. This bit is 'set only' (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. 19 1 read-write HSEEXT external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. 20 1 read-write HSEEXT Analog HSE in analog mode 0 Digital HSE in digital mode 1 PLL1ON PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. 24 1 read-write PLL1RDY PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. 25 1 read-only PLL2ON PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode. 26 1 read-write PLL2RDY PLL2 clock ready flag Set by hardware to indicate that the PLL is locked. 27 1 read-only HSICFGR HSICFGR RCC HSI calibration register 0x10 0x20 0x00400000 0xFFFFF000 HSICAL HSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value. 0 12 read-only HSITRIM HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_OPT. After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated Note: The reset value of the field is 0x40. 16 7 read-write 0 127 CRRCR CRRCR RCC clock recovery RC register 0x14 0x20 0x00000000 0xFFFFF000 HSI48CAL Internal RC 48 MHz clock calibration Set by hardware by option-byte loading during system reset NRESET. Read-only. 0 10 read-only CSICFGR CSICFGR RCC CSI calibration register 0x18 0x20 0x00200000 0xFFFFF000 CSICAL CSI clock calibration Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value. 0 8 read-write CSITRIM CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_OPT. Note: The reset value of the field is 0x20. 16 6 read-write 0 63 CFGR1 CFGR1 RCC clock configuration register 0x1C 0x20 0x00000000 0xFFFFFFFF SW system clock and trace clock switch Set and reset by software to select system clock and trace clock sources (sys_ck). Set by hardware in order to: - force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode - force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock others: reserved 0 2 read-write SW HSI HSI selected as system clock 0 CSI CSI selected as system clock 1 HSE HSE selected as system clock 2 PLL1 PLL1 selected as system clock 3 SWS system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset). others: reserved 3 2 read-only SWSR HSI HSI oscillator used as system clock 0 CSI CSI oscillator used as system clock 1 HSE HSE oscillator used as system clock 2 PLL1 PLL1 used as system clock 3 STOPWUCK system clock selection after a wakeup from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset) STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10). 6 1 read-write STOPWUCK HSI HSI selected as wake up clock from system Stop 0 CSI CSI selected as wake up clock from system Stop 1 STOPKERWUCK kernel clock selection after a wakeup from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. 7 1 read-write RTCPRE HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ... 8 6 read-write 0 63 TIMPRE timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. 15 1 read-write TIMPRE DefaultX2 Timer kernel clock equal to 2x pclk by default 0 DefaultX4 Timer kernel clock equal to 4x pclk by default 1 MCO1PRE MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... 18 4 read-write 0 15 MCO1SEL Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved 22 3 read-write MCO1SEL HSI HSI clock selected (hsi_ck) 0 LSE LSE clock selected (lse_ck) 1 HSE HSE clock selected (hse_ck) 2 PLL1_Q PLL1 clock selected (pll1_q_ck) 3 HSI48 HSI48 clock selected (hsi48_ck) 4 MCO2PRE MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... 25 4 read-write 0 15 MCO2SEL microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved 29 3 read-write MCO2SEL SYSCLK System clock selected (sys_ck) 0 PLL2_P PLL2 oscillator clock selected (pll2_p_ck) 1 HSE HSE clock selected (hse_ck) 2 PLL1_P PLL1 clock selected (pll1_p_ck) 3 CSI CSI clock selected (csi_ck) 4 LSI LSI clock selected (lsi_ck) 5 CFGR2 CFGR2 RCC CPU domain clock configuration register 2 0x20 0x20 0x00000000 0xFFFFFFFF HPRE AHB prescaler Set and reset by software to control the division factor of rcc_hclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks 0xxx: rcc_hclk = sys_ck (default after reset) 0 4 read-write HPRE Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 Div1 SYSCLK not divided true PPRE1 APB low-speed prescaler (APB1) Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset) 4 3 read-write PPRE1 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true PPRE2 APB high-speed prescaler (APB2) Set and reset by software to control APB high-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1 8 3 read-write PPRE3 APB low-speed prescaler (APB3) Set and reset by software to control APB low-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write. 0xx: rcc_pclk3 = rcc_hclk1 12 3 read-write AHB1DIS AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals from RCC_AHB1ENR are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from RCC_AHB1ENR are off. enable control bits 16 1 read-write AHB1DIS Enabled The selected clock is enabled 0 Disabled The selected clock is disabled 1 AHB2DIS AHB2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR are used and when their clocks are disabled in RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR are off. enable control bits 17 1 read-write AHB4DIS AHB4 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB4 peripherals from RCC_AHB4ENR are used and when their clocks are disabled in RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from RCC_AHB4ENR are off. enable control bits 19 1 read-write APB1DIS APB1 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. control bits 20 1 read-write APB2DIS APB2 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off. control bits 21 1 read-write APB3DIS APB3 clock disable value.Set and cleared by software This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. control bits 22 1 read-write PLL1CFGR PLL1CFGR RCC PLL clock source selection register 0x28 0x20 0x00000000 0xFFFFFFFF PLL1SRC DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset). 0 2 read-write PLL1SRC None No clock sent to DIVMx dividers and PLLs 0 HSI HSI selected as PLL clock 1 CSI CSI selected as PLL clock 2 HSE HSE selected as PLL clock 3 PLL1RGE PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 2 2 read-write PLL1RGE Range1 Frequency is between 1 and 2 MHz 0 Range2 Frequency is between 2 and 4 MHz 1 Range4 Frequency is between 4 and 8 MHz 2 Range8 Frequency is between 8 and 16 MHz 3 PLL1FRACEN PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator. In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator. 4 1 read-write PLL1FRACEN Reset Reset latch to transfer FRACN to the Sigma-Delta modulator 0 Set Set latch to transfer FRACN to the Sigma-Delta modulator 1 PLL1VCOSEL PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. 5 1 read-write PLL1VCOSEL WideVCO VCO frequency range 192 to 836 MHz 0 MediumVCO VCO frequency range 150 to 420 MHz 1 PLL1M prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... 8 6 read-write PLL1PEN PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. 16 1 read-write PLL1PEN Disabled Clock output is disabled 0 Enabled Clock output is enabled 1 PLL1QEN PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 17 1 read-write PLL1REN PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 18 1 read-write PLL2CFGR PLL2CFGR RCC PLL clock source selection register 0x2C 0x20 0x00000000 0xFFFFFFFF PLL2SRC DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL2SRC must be set to '00'. 0 2 read-write PLL2SRC None No clock sent to DIVMx dividers and PLLs 0 HSI HSI selected as PLL clock 1 CSI CSI selected as PLL clock 2 HSE HSE selected as PLL clock 3 PLL2RGE PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. These bits must be written before enabling the PLL2. 2 2 read-write PLL2RGE Range1 Frequency is between 1 and 2 MHz 0 Range2 Frequency is between 2 and 4 MHz 1 Range4 Frequency is between 4 and 8 MHz 2 Range8 Frequency is between 8 and 16 MHz 3 PLL2FRACEN PLL2 fractional latch enable Set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, when the pll2_p_ck output of the PLL2 is not used, the pll2_p_ck must be disabled. 4 1 read-write PLL2FRACEN Reset Reset latch to transfer FRACN to the Sigma-Delta modulator 0 Set Set latch to transfer FRACN to the Sigma-Delta modulator 1 PLL2VCOSEL PLL2 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL2. This bit must be written before enabling the PLL2. 5 1 read-write PLL2VCOSEL WideVCO VCO frequency range 192 to 836 MHz 0 MediumVCO VCO frequency range 150 to 420 MHz 1 PLL2M prescaler for PLL2 Set and cleared by software to configure the prescaler of the PLL2. The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ON = 1 or PLL2RDY = 1). In order to save power when PLL2 is not used, the value of DIVM2 must be set to 0. ... ... 8 6 read-write PLL2PEN PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, when the pll2_p_ck output of the PLL2 is not used, the pll2_p_ck must be disabled. 16 1 read-write PLL2PEN Disabled Clock output is disabled 0 Enabled Clock output is enabled 1 PLL2QEN PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, when the pll2_q_ck output of the PLL2 is not used, the pll2_q_ck must be disabled. 17 1 read-write PLL2REN PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, DIVR2EN and DIVR2 bits must be set to 0 when the pll2_r_ck is not used. 18 1 read-write PLL1DIVR PLL1DIVR RCC PLL1 dividers register 0x34 0x20 0x01010280 0xFFFFFFFF PLL1N Multiplication factor for PLL1VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved 0 9 read-write 3 511 PLL1P PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... 9 7 read-write 0 127 PLL1Q PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 16 7 read-write 0 127 PLL1R PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 24 7 read-write 0 127 PLL1FRACR PLL1FRACR RCC PLL1 fractional divider register 0x38 0x20 0x00000000 0xFFFFFFFF PLL1FRACN fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: * 128 to 560 MHz if PLL1VCOSEL = 0 * 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with * PLL1N between 8 and 420 * PLL1FRACN can be between 0 and 213- 1 * The input frequency Fref1_ck must be between 1 and 16 MHz. To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: * Set the bit PLL1FRACEN to 0 * Write the new fractional value into PLL1FRACN * Set the bit PLL1FRACEN to 1 3 13 read-write 0 8191 PLL2DIVR PLL2DIVR RCC PLL1 dividers register 0x3C 0x20 0x01010280 0xFFFFFFFF PLL2N Multiplication factor for PLL2VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0). ... ... Others: reserved 0 9 read-write 3 511 PLL2P PLL2 DIVP division factor Set and reset by software to control the frequency of the pll2_p_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 9 7 read-write 0 127 PLL2Q PLL2 DIVQ division factor Set and reset by software to control the frequency of the pll2_q_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 16 7 read-write 0 127 PLL2R PLL2 DIVR division factor Set and reset by software to control the frequency of the pll2_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 24 7 read-write 0 127 PLL2FRACR PLL2FRACR RCC PLL2 fractional divider register 0x40 0x20 0x00000000 0xFFFFFFFF PLL2FRACN fractional part of the multiplication factor for PLL2 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: * 128 to 560 MHz if PLL2VCOSEL = 0 * 150 to 420 MHz if PLL2VCOSEL = 1 VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with * PLL2N between 8 and 420 * PLL2FRACN can be between 0 and 213- 1 * The input frequency Fref2_ck must be between 1 and 16 MHz. To change the PLL2FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: * Set the bit PLL2FRACEN to 0 * Write the new fractional value into PLL2FRACN * Set the bit PLL2FRACEN to 1 3 13 read-write 0 8191 CIER CIER RCC clock source interrupt enable register 0x50 0x20 0x00000000 0xFFFFFFFF LSIRDYIE LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0 1 read-write LSIRDYIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 LSERDYIE LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. 1 1 read-write CSIRDYIE CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. 2 1 read-write HSIRDYIE HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. 3 1 read-write HSERDYIE HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. 4 1 read-write HSI48RDYIE HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. 5 1 read-write PLL1RDYIE PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. 6 1 read-write PLL2RDYIE PLL2 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL2 lock. 7 1 read-write CIFR CIFR RCC clock source interrupt flag register 0x54 0x20 0x00000000 0xFFFFFFFF LSIRDYF LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. 0 1 read-only LSIRDYFR NotInterrupted No clock ready interrupt 0 Interrupted Clock ready interrupt 1 LSERDYF LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. 1 1 read-only CSIRDYF CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. 2 1 read-only HSIRDYF HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. 3 1 read-only HSERDYF HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. 4 1 read-only HSI48RDYF HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. 5 1 read-only PLL1RDYF PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. 6 1 read-only PLL2RDYF PLL2 ready interrupt flag Reset by software by writing PLL2RDYC bit. Set by hardware when the PLL2 locks and PLL2RDYIE is set. 7 1 read-only HSECSSF HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. 10 1 read-only HSECSSFR NoInterrupt No clock security interrupt caused by HSE clock failure 0 Interrupt Clock security interrupt caused by HSE clock failure 1 CICR CICR RCC clock source interrupt clear register 0x58 0x20 0x00000000 0xFFFFFFFF LSIRDYC LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done. 0 1 read-write LSIRDYC Clear Clear interrupt flag 1 LSERDYC LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done. 1 1 read-write CSIRDYC HSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done. 2 1 read-write HSIRDYC HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done. 3 1 read-write HSERDYC HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done. 4 1 read-write HSI48RDYC HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. 5 1 read-write PLL1RDYC PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. 6 1 read-write PLL2RDYC PLL2 ready interrupt clear Set by software to clear PLL2RDYF. Reset by hardware when clear done. 7 1 read-write HSECSSC HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. 10 1 read-write AHB1RSTR AHB1RSTR RCC AHB1 reset register 0x60 0x20 0x00000000 0xFFFFFFFF GPDMA1RST GPDMA1 block reset Set and reset by software. 0 1 read-write GPDMA1RST Reset Reset the selected module 1 GPDMA2RST GPDMA2 block reset Set and reset by software. 1 1 read-write CRCRST CRC block reset Set and reset by software. 12 1 read-write RAMCFGRST RAMCFG block reset Set and reset by software. 17 1 read-write AHB2RSTR AHB2RSTR RCC AHB2 peripheral reset register 0x64 0x20 0x00000000 0xFFFFFFFF GPIOARST GPIOA block reset Set and reset by software. 0 1 read-write GPIOARST Reset Reset the selected module 1 GPIOBRST GPIOB block reset Set and reset by software. 1 1 read-write GPIOCRST GPIOC block reset Set and reset by software. 2 1 read-write GPIODRST GPIOD block reset Set and reset by software. 3 1 read-write GPIOHRST GPIOH block reset Set and reset by software. 7 1 read-write ADCRST ADC block reset 10 1 read-write DAC12RST DAC block reset Set and reset by software. 11 1 read-write HASHRST HASH block reset Set and reset by software. 17 1 read-write RNGRST RNG block reset Set and reset by software. 18 1 read-write APB1LRSTR APB1LRSTR RCC APB1 peripheral low reset register 0x74 0x20 0x00000000 0xFFFFFFFF TIM2RST TIM2 block reset Set and reset by software. 0 1 read-write TIM2RST Reset Reset the selected module 1 TIM3RST TIM3 block reset Set and reset by software. 1 1 read-write TIM6RST TIM6 block reset Set and reset by software. 4 1 read-write TIM7RST TIM7 block reset Set and reset by software. 5 1 read-write OPAMPRST OPAMP block reset Set and reset by software. 13 1 read-write SPI2RST SPI2 block reset Set and reset by software. 14 1 read-write SPI3RST SPI3 block reset Set and reset by software. 15 1 read-write COMPRST COMP block reset Set and reset by software. 16 1 read-write USART2RST USART2 block reset Set and reset by software. 17 1 read-write USART3RST USART3 block reset Set and reset by software. 18 1 read-write I2C1RST I2C1 block reset Set and reset by software. 21 1 read-write I2C2RST I2C2 block reset Set and reset by software. 22 1 read-write I3C1RST I3C1 block reset Set and reset by software. 23 1 read-write CRSRST CRS block reset Set and reset by software. 24 1 read-write APB1HRSTR APB1HRSTR RCC APB1 peripheral high reset register 0x78 0x20 0x00000000 0xFFFFFFFF DTSRST DTS block reset Set and reset by software. 3 1 read-write DTSRST Reset Reset the selected module 1 LPTIM2RST LPTIM2 block reset Set and reset by software. 5 1 read-write FDCANRST FDCAN block reset 9 1 read-write APB2RSTR APB2RSTR RCC APB2 peripheral reset register 0x7C 0x20 0x00000000 0xFFFFFFFF TIM1RST TIM1 block reset Set and reset by software. 11 1 read-write TIM1RST Reset Reset the selected module 1 SPI1RST SPI1 block reset Set and reset by software. 12 1 read-write USART1RST USART1 block reset Set and reset by software. 14 1 read-write USBRST USB block reset 24 1 read-write APB3RSTR APB3RSTR RCC APB3 peripheral reset register 0x80 0x20 0x00000000 0xFFFFFFFF SBSRST SBS block reset Set and reset by software. 1 1 read-write SBSRST Reset Reset the selected module 1 LPUART1RST LPUART1 block reset Set and reset by software. 6 1 read-write I3C2RST I3C2RST block reset Set and reset by software. 9 1 read-write LPTIM1RST LPTIM1 block reset Set and reset by software. 11 1 read-write VREFRST VREF block reset Set and reset by software. 20 1 read-write AHB1ENR AHB1ENR RCC AHB1 peripherals clock register 0x88 0x20 0x90000100 0xFFFFFFFF GPDMA1EN GPDMA1 clock enable Set and reset by software. 0 1 read-write GPDMA1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 GPDMA2EN GPDMA2 clock enable Set and reset by software. 1 1 read-write FLITFEN Flash interface clock enable Set and reset by software. 8 1 read-write CRCEN CRC clock enable Set and reset by software. 12 1 read-write RAMCFGEN RAMCFG clock enable Set and reset by software. 17 1 read-write BKPRAMEN BKPRAM clock enable Set and reset by software 28 1 read-write SRAM1EN SRAM1 clock enable Set and reset by software. 31 1 read-write GTZC1EN GTZC1 clock enable 24 1 read-write AHB2ENR AHB2ENR RCC AHB2 peripheral clock register 0x8C 0x20 0x40000000 0xFFFFFFFF GPIOAEN GPIOA clock enable Set and reset by software. 0 1 read-write GPIOAEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 GPIOBEN GPIOB clock enable Set and reset by software. 1 1 read-write GPIOCEN GPIOC clock enable Set and reset by software. 2 1 read-write GPIODEN GPIOD clock enable Set and reset by software. 3 1 read-write GPIOHEN GPIOH clock enable Set and reset by software. 7 1 read-write ADCEN ADC peripherals clock enabled 10 1 read-write DAC12EN DAC clock enable Set and reset by software. 11 1 read-write HASHEN HASH clock enable Set and reset by software. 17 1 read-write RNGEN RNG clock enable Set and reset by software. 18 1 read-write SRAM2EN SRAM2 clock enable Set and reset by software. 30 1 read-write APB1LENR APB1LENR RCC APB1 peripheral clock register 0x9C 0x20 0x00000000 0xFFFFFFFF TIM2EN TIM2 clock enable Set and reset by software. 0 1 read-write TIM2EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM3EN TIM3 clock enable Set and reset by software. 1 1 read-write TIM6EN TIM6 clock enable Set and reset by software. 4 1 read-write TIM7EN TIM7 clock enable Set and reset by software. 5 1 read-write WWDGEN WWDG clock enable Set and reset by software. 11 1 read-write OPAMPEN OPAMP clock enable Set and reset by software. 13 1 read-write SPI2EN SPI2 clock enable Set and reset by software. 14 1 read-write SPI3EN SPI3 clock enable Set and reset by software. 15 1 read-write COMPEN COMP clock enable Set and reset by software. 16 1 read-write USART2EN USART2 clock enable Set and reset by software. 17 1 read-write USART3EN USART3 clock enable Set and reset by software. 18 1 read-write I2C1EN I2C1 clock enable Set and reset by software. 21 1 read-write I2C2EN I2C2 clock enable Set and reset by software. 22 1 read-write I3C1EN I3C1 clock enable Set and reset by software. 23 1 read-write CRSEN CRS clock enable Set and reset by software. 24 1 read-write APB1HENR APB1HENR RCC APB1 peripheral clock register 0xA0 0x20 0x00000000 0xFFFFFFFF DTSEN DTS clock enable Set and reset by software. 3 1 read-write DTSEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 LPTIM2EN LPTIM2 clock enable Set and reset by software. 5 1 read-write FDCANEN FDCAN peripheral clock enable 9 1 read-write APB2ENR APB2ENR RCC APB2 peripheral clock register 0xA4 0x20 0x00000000 0xFFFFFFFF TIM1EN TIM1 clock enable Set and reset by software. 11 1 read-write TIM1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 SPI1EN SPI1 clock enable Set and reset by software. 12 1 read-write USART1EN USART1 clock enable Set and reset by software. 14 1 read-write USBEN USB clock enable 24 1 read-write APB3ENR APB3ENR RCC APB3 peripheral clock register 0xA8 0x20 0x00000000 0xFFFFFFFF SBSEN SBS clock enable Set and reset by software. 1 1 read-write SBSEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 LPUART1EN LPUART1 clock enable Set and reset by software. 6 1 read-write I3C2EN I3C2EN clock enable Set and reset by software. 9 1 read-write LPTIM1EN LPTIM1 clock enable Set and reset by software. 11 1 read-write VREFEN VREF clock enable Set and reset by software. 20 1 read-write RTCAPBEN RTC APB interface clock enable Set and reset by software. 21 1 read-write AHB1LPENR AHB1LPENR RCC AHB1 sleep clock register 0xB0 0x20 0xFFFFFFFF 0xFFFFFFFF GPDMA1LPEN GPDMA1 clock enable during sleep mode Set and reset by software. 0 1 read-write GPDMA1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 GPDMA2LPEN GPDMA2 clock enable during sleep mode Set and reset by software. 1 1 read-write FLITFLPEN Flash interface (FLITF) clock enable during sleep mode Set and reset by software. 8 1 read-write CRCLPEN CRC clock enable during sleep mode Set and reset by software. 12 1 read-write RAMCFGLPEN RAMCFG clock enable during sleep mode Set and reset by software. 17 1 read-write BKPRAMLPEN BKPRAM clock enable during sleep mode Set and reset by software 28 1 read-write ICACHELPEN ICACHE clock enable during sleep mode Set and reset by software 29 1 read-write SRAM1LPEN SRAM1 clock enable during sleep mode Set and reset by software 31 1 read-write GTZC1LPEN GTZC1 clock enable during sleep mode 24 1 read-write AHB2LPENR AHB2LPENR RCC AHB2 sleep clock register 0xB4 0x20 0xFFFFFFFF 0xFFFFFFFF GPIOALPEN GPIOA clock enable during sleep mode Set and reset by software. 0 1 read-write GPIOALPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 GPIOBLPEN GPIOB clock enable during sleep mode Set and reset by software. 1 1 read-write GPIOCLPEN GPIOC clock enable during sleep mode Set and reset by software. 2 1 read-write GPIODLPEN GPIOD clock enable during sleep mode Set and reset by software. 3 1 read-write GPIOHLPEN GPIOH clock enable during sleep mode Set and reset by software. 7 1 read-write ADCLPEN ADC peripherals clock enable during sleep mode 10 1 read-write DAC12LPEN DAC clock enable during sleep mode Set and reset by software. 11 1 read-write HASHLPEN HASH clock enable during sleep mode Set and reset by software. 17 1 read-write RNGLPEN RNG clock enable during sleep mode Set and reset by software. 18 1 read-write SRAM2LPEN SRAM2 clock enable during sleep mode Set and reset by software. 30 1 read-write APB1LLPENR APB1LLPENR RCC APB1 sleep clock register 0xC4 0x20 0xFFFFFFFF 0xFFFFFFFF TIM2LPEN TIM2 clock enable during sleep mode Set and reset by software. 0 1 read-write TIM2LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 TIM3LPEN TIM3 clock enable during sleep mode Set and reset by software. 1 1 read-write TIM6LPEN TIM6 clock enable during sleep mode Set and reset by software. 4 1 read-write TIM7LPEN TIM7 clock enable during sleep mode Set and reset by software. 5 1 read-write WWDGLPEN WWDG clock enable during sleep mode Set and reset by software. 11 1 read-write OPAMPLPEN OPAMP clock enable during sleep mode Set and reset by software. 13 1 read-write SPI2LPEN SPI2 clock enable during sleep mode Set and reset by software. 14 1 read-write SPI3LPEN SPI3 clock enable during sleep mode Set and reset by software. 15 1 read-write COMPLPEN COMP clock enable during sleep mode Set and reset by software. 16 1 read-write USART2LPEN USART2 clock enable during sleep mode Set and reset by software. 17 1 read-write USART3LPEN USART3 clock enable during sleep mode Set and reset by software. 18 1 read-write I2C1LPEN I2C1 clock enable during sleep mode Set and reset by software. 21 1 read-write I2C2LPEN I2C2 clock enable during sleep mode Set and reset by software. 22 1 read-write I3C1LPEN I3C1 clock enable during sleep mode Set and reset by software. 23 1 read-write CRSLPEN CRS clock enable during sleep mode Set and reset by software. 24 1 read-write APB1HLPENR APB1HLPENR RCC APB1 sleep clock register 0xC8 0x20 0xFFFFFFFF 0xFFFFFFFF DTSLPEN DTS clock enable during sleep mode Set and reset by software. 3 1 read-write DTSLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 LPTIM2LPEN LPTIM2 clock enable during sleep mode Set and reset by software. 5 1 read-write FDCANLPEN FDCAN peripheral clock enable during sleep mode 9 1 read-write APB2LPENR APB2LPENR RCC APB2 sleep clock register 0xCC 0x20 0xFFFFFFFF 0xFFFFFFFF TIM1LPEN TIM1 clock enable during sleep mode Set and reset by software. 11 1 read-write TIM1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 SPI1LPEN SPI1 clock enable during sleep mode Set and reset by software. 12 1 read-write USART1LPEN USART1 clock enable during sleep mode Set and reset by software. 14 1 read-write USBLPEN USB clock enable during sleep mode 24 1 read-write APB3LPENR APB3LPENR RCC APB3 sleep clock register 0xD0 0x20 0xFFFFFFFF 0xFFFFFFFF SBSLPEN SBS clock enable during sleep mode Set and reset by software. 1 1 read-write SBSLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 LPUART1LPEN LPUART1 clock enable during sleep mode Set and reset by software. 6 1 read-write I3C2LPEN I3C2 clock enable during sleep mode Set and reset by software. 9 1 read-write LPTIM1LPEN LPTIM1 clock enable during sleep mode Set and reset by software. 11 1 read-write VREFLPEN VREF clock enable during sleep mode Set and reset by software. 20 1 read-write RTCAPBLPEN RTC APB interface clock enable during sleep mode Set and reset by software. 21 1 read-write CCIPR1 CCIPR1 RCC kernel clock configuration register 0xD8 0x20 0x00000000 0xFFFFFFFF USART1SEL USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 3 read-write USARTSEL PCLK Peripheral bus clock used as selected as clock source (rcc_pclk_x) 0 PLL2_Q PLL2 Q clock selected as clock source (pll2_q_ck) 1 HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 3 CSI_KER CSI kernel clock selected as clock source (csi_ker_ck) 4 LSE LSE clock selected as clock source (lse_ck) 5 USART2SEL USART2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 3 3 read-write USART3SEL USART3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 6 3 read-write TIMICSEL TIM2, TIM3 and LPTIM2 input capture source selection Set and reset by software. 31 1 read-write TIMICSEL Disabled No internal clock available for timers input capture 0 Enabled hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture 1 CCIPR2 CCIPR2 RCC kernel clock configuration register 0xDC 0x20 0x00000000 0xFFFFFFFF LPTIM1SEL LPTIM1 kernel clock source selection others: reserved, the kernel clock is disabled 8 3 read-write LPTIMSEL PCLK Peripheral bus clock used as selected as clock source (rcc_pclk_x) 0 PLL2_P PLL2 P clock selected as clock source (pll2_p_ck) 1 LSE_KER LSE kernel selected as clock source (lse_ck) 3 LSI_KER LSI kernel selected as clock source (lsi_ker_ck) 4 PER_CK per_ck clock selected as clock source 5 LPTIM2SEL LPTIM2 kernel clock source selection others: reserved, the kernel clock is disabled 12 3 read-write CCIPR3 CCIPR3 RCC kernel clock configuration register 0xE0 0x20 0x00000000 0xFFFFFFFF SPI1SEL SPI1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 3 read-write SPI123SEL PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 0 PLL2_P PLL2 P clock selected as clock source (pll2_p_ck) 1 AUDIOCLK AUDIOCLK clock selected as clock source 3 PER_CK per_ck clock selected as clock source 4 SPI2SEL SPI2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 3 3 read-write SPI3SEL SPI3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 6 3 read-write LPUART1SEL LPUART1 kernel clock source selection others: reserved, the kernel clock is disabled 24 3 read-write CCIPR4 CCIPR4 RCC kernel clock configuration register 0xE4 0x20 0x00000000 0xFFFFFFFF SYSTICKSEL SYSTICK clock source selection Note: rcc_hclk frequency must be four times higher than lsi_ker_ck/lse_ck (period (LSI/LSE) greater than or equal 4 * period (HCLK). 2 2 read-write SYSTICKSEL HCLK_DIV8 RCC HLCK divided by 8 selected as clock source (rcc_hclk / 8) 0 LSI_KER LSI kernel selected as clock source (lsi_ker_ck) 1 LSE LSE selected as clock source (lse_ck) 2 USBSEL USB kernel clock source selection 4 2 read-write USBSEL DISABLE Disable the clock 0 PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 1 PLL2_Q PLL2 Q clock selected as clock source (pll2_q_ck) 2 HSI48 HSI48 clock selected as clock source (hsi48_ker_ck) 3 I2C1SEL I2C1 kernel clock source selection 16 2 read-write I2CSEL PCLK Peripheral bus clock used as selected as clock source (rcc_pclk_x) 0 PLL2_R PLL2 R Clock selected as clock source (pll2_r_ck) 1 HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 2 CSI_KER CSI kernel clock selected as clock source (csi_ker_ck) 3 I2C2SEL I2C2 kernel clock source selection 18 2 read-write I3C1SEL I3C1 kernel clock source selection 24 2 read-write I3CSEL PCLK Peripheral bus clock used as selected as clock source (rcc_pclk_x) 0 PLL2_R PLL2 R clock selected as clock source (pll2_r_ck) 1 HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 2 I3C2SEL I3C2 kernel clock source selection 26 2 read-write CCIPR5 CCIPR5 RCC kernel clock configuration register 0xE8 0x20 0x00000000 0xFFFFFFFF ADCDACSEL ADC and DAC kernel clock source selection others: reserved, the kernel clock is disabled 0 3 read-write ADCDACSEL HCLK HLCK clock selected as clock source (rcc_hclk) 0 SYS System clock selected as pclock source (sys_ck) 1 PLL2_R PLL2 R clock selected as clock source (pll2_r_ck) 2 HSE HSE clock selected as clock source (hse_ck) 3 HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 4 CSI_KER CSI kernel clock selected as clock source (csi_ker_ck) 5 DAC1SEL DAC1 sample and hold clock source selection 3 1 read-write DAC1SEL LSE LSE selected as clock source (lse_ck) 0 LSI_KER LSI kernel selected as clock source (lsi_ker_ck) 1 RNGSEL RNG kernel clock source selection 4 2 read-write RNGSEL HSI48_KER HSI48 kernel clock selected as clock source (hsi48_ker_ck) 0 PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 1 LSE LSE clock selected as clock source (lse_ck) 2 LSI LSI kernel clock selected as clock source (lsi_ker_ck) 3 FDCANSEL FDCAN kernel clock source selection 8 2 read-write FDCANSEL HSE HSE clock selected as clock source (hse_ck) 0 PLL1_Q PLL1 Q clock selected as clock source (pll1_q_ck) 1 PLL2_Q PLL2 Q clock selected as clock source (pll2_q_ck) 2 CKPERSEL per_ck clock source selection 30 2 read-write CKPERSEL HSI_KER HSI kernel clock selected as clock source (hsi_ker_ck) 0 CSI_KER CSI kernel clock selected as clock source (csi_ker_ck) 1 HSE HSE clock selected as clock source (hse_ck) 2 BDCR BDCR RCC Backup domain control register 0xF0 0x20 0x00000000 0xFFFFFFFF LSEON LSE oscillator enabled Set and reset by software. 0 1 read-write LSEON Off LSE oscillator Off 0 On LSE oscillator On 1 LSERDY LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0. 1 1 read-write LSERDYR read NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEBYP LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1) 2 1 read-write LSEBYP NotBypassed LSE crystal oscillator not bypassed 0 Bypassed LSE crystal oscillator bypassed with external clock 1 LSEDRV LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0). 3 2 read-write LSEDRV Lowest Lowest LSE oscillator driving capability 0 MediumLow Medium low LSE oscillator driving capability 1 MediumHigh Medium high LSE oscillator driving capability 2 Highest Highest LSE oscillator driving capability 3 LSECSSON LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. 5 1 read-write LSECSSON SecurityOff Clock security system on 32 kHz oscillator off 0 SecurityOn Clock security system on 32 kHz oscillator on 1 LSECSSD LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator. 6 1 read-write LSECSSDR read NoFailure No failure detected on 32 kHz oscillator 0 Failure Failure detected on 32 kHz oscillator 1 LSEEXT low-speed external clock type in bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled. 7 1 read-write LSEEXT Analog HSE in analog mode 0 Digital HSE in digital mode 1 RTCSEL RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). 8 2 read-write RTCSEL NoClock No clock 0 LSE LSE oscillator clock used as RTC clock 1 LSI LSI oscillator clock used as RTC clock 2 HSE HSE oscillator clock divided by a prescaler used as RTC clock 3 RTCEN RTC clock enable Set and reset by software. 15 1 read-write RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 VSWRST VSwitch domain software reset Set and reset by software. 16 1 read-write VSWRST NotActivated Reset not activated 0 Reset Resets the entire VSW domain 1 LSCOEN Low-speed clock output (LSCO) enable Set and cleared by software. 24 1 read-write LSCOSEL Low-speed clock output selection Set and cleared by software. 25 1 read-write LSCOSEL LSI LSI clock selected 0 LSE LSE clock selected 1 LSION LSI oscillator enable Set and cleared by software. 26 1 read-write LSION Disabled Oscillator disabled 0 Enabled Oscillator enabled 1 LSIRDY LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. 27 1 read-write LSIRDYR read NotReady Clock not ready 0 Ready Clock ready 1 RSR RSR RCC reset status register 0xF4 0x20 0x0C000000 0xFFFFFFFF RMVF remove reset flag Set and reset by software to reset the value of the reset flags. 23 1 read-write RMVF NotActivated Reset not activated 0 Reset Reset the reset status flags 1 PINRSTF pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. 26 1 read-write PINRSTFR read NoResetOccurred No reset occurred for block 0 ResetOccurred Reset occurred for block 1 BORRSTF BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). 27 1 read-write SFTRSTF system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33. 28 1 read-write IWDGRSTF independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. 29 1 read-write WWDGRSTF window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. 30 1 read-write LPWRRSTF Low-power reset flag Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared. Cleared by writing to the RMVF bit. 31 1 read-write PRIVCFGR RCC privilege configuration register 0x114 read-write PRIV RCC functions privilege configuration 1 1 read-write PRIV Any RCC functions can be modified by privileged or unprivileged access 0 PrivilegedOnly RCC functions can only be modified by privileged access 1 RNG True random number generator RNG 0x420C0800 0x0 0x400 registers RNG RNG global interrupt 114 CR CR RNG control register 0x0 0x20 0x008000D0 0xFFFFFFFF RNGEN True random number generator enable 2 1 read-write RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 IE Interrupt Enable 3 1 read-write IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 CED Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 5 1 read-write CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 ARDIS Auto reset disable When auto-reset is enabled application still need to clear SEIS bit after a noise source error. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 7 1 read-write RNG_CONFIG3 RNG configuration 3 Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details. If NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by RNG. 8 4 read-write RNG_CONFIG3 ConfigB Recommended value for config B (not NIST certifiable) 0 ConfigA Recommended value for config A (NIST certifiable) 13 NISTC Non NIST compliant two conditioning loops are performed and 256 bits of noise source are used. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 12 1 read-write NISTC Default Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used 0 Custom Custom values for NIST compliant RNG 1 RNG_CONFIG2 RNG configuration 2 Reserved to the RNG configuration (bitfield 2). Refer to RNG_CONFIG1 bitfield for details. 13 3 read-write RNG_CONFIG2 ConfigA_B Recommended value for config A and B 0 CLKDIV Clock divider factor This value used to configure an internal programmable divider (from 1 to 16) acting on the incoming RNG clock. These bits can be written only when the core is disabled (RNGEN = 0). ... Writing these bits is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 16 4 read-write CLKDIV Div1 Internal RNG clock after divider is similar to incoming RNG clock 0 Div2 Divide RNG clock by 2^1 1 Div4 Divide RNG clock by 2^2 2 Div8 Divide RNG clock by 2^3 3 Div16 Divide RNG clock by 2^4 4 Div32 Divide RNG clock by 2^5 5 Div64 Divide RNG clock by 2^6 6 Div128 Divide RNG clock by 2^7 7 Div256 Divide RNG clock by 2^8 8 Div512 Divide RNG clock by 2^9 9 Div1024 Divide RNG clock by 2^10 10 Div2048 Divide RNG clock by 2^11 11 Div4096 Divide RNG clock by 2^12 12 Div8192 Divide RNG clock by 2^13 13 Div16384 Divide RNG clock by 2^14 14 Div32768 Divide RNG clock by 2^15 15 RNG_CONFIG1 RNG configuration 1 Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended value documented in Section 23.6: RNG entropy source validation. Writing any bit of RNG_CONFIG1 is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 20 6 read-write RNG_CONFIG1 ConfigA Recommended value for config A (NIST certifiable) 15 ConfigB Recommended value for config B (not NIST certifiable) 24 CONDRST Conditioning soft reset Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new RNG initialization process, with RNG_SR cleared. Registers RNG_CR and RNG_NSCR are not changed by CONDRST. This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be written. When CONDRST is set to 0 by software its value goes to 0 when the reset process is done. It takes about 2 AHB clock cycles + 2 RNG clock cycles. 30 1 read-write CONFIGLOCK RNG Config lock This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset. 31 1 read-write CONFIGLOCK Enabled Writes to the RNG_CR configuration bits [29:4] are allowed 0 Disabled Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset 1 SR SR RNG status register 0x4 0x20 0x00000000 0xFFFFFFFF DRDY Data Ready Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. Note: The DRDY bit can rise when the peripheral is disabled (RNGEN = 0 in the RNG_CR register). If IE=1 in the RNG_CR register, an interrupt is generated when DRDY = 1. 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 CECS Clock error current status Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0. 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 SECS Seed error current status Run-time repetition count test failed (noise source has provided more than 24 consecutive bits at a constant value 0 or 1, or more than 32 consecutive occurrence of two bits patterns 01 or 10) Start-up or continuous adaptive proportion test on noise source failed. Start-up post-processing/conditioning sanity check failed. 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CEIS Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register. 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing 0 (unless CONDRST is used). Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register. 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 DR DR RNG data register 0x8 0x20 0x00000000 0xFFFFFFFF RNDATA Random data 32-bit random data which are valid when DRDY = 1. When DRDY = 0 RNDATA value is zero. It is recommended to always verify that RNG_DR is different from zero. Because when it is the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare event). 0 32 read-only 0 4294967295 NSCR RNG noise source control register 0xC 0x0003FFFF EN_OSC1 Each bit drives one oscillator enable signal input of instance number 1, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 0 3 EN_OSC2 Each bit drives one oscillator enable signal input of instance number 2, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 3 3 EN_OSC3 Each bit drives one oscillator enable signal input of instance number 3, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 6 3 EN_OSC4 Each bit drives one oscillator enable signal input of instance number 4, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 9 3 EN_OSC5 Each bit drives one oscillator enable signal input of instance number 5, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 12 3 EN_OSC6 Each bit drives one oscillator enable signal input of instance number 6, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). 15 3 HTCR HTCR RNG health test control register 0x10 0x20 0x000072AC 0xFFFFFFFF HTCFG health test configuration This configuration is used by RNG to configure the health tests. See Section 23.6: RNG entropy source validation for the recommended value. Note: The RNG behavior, including the read to this register, is not guaranteed if a different value from the recommended value is written. 0 32 read-write HTCFG Recommended Recommended value for RNG certification (0x0000_AA74) 43636 Magic Magic number to be written before any write (0x1759_0ABC) 391711420 RTC Real-time clock RTC 0x44007800 0x0 0x400 registers RTC RTC global interrupt 2 TR TR RTC time register 0x0 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write 0 15 ST Second tens in BCD format 4 3 read-write 0 7 MNU Minute units in BCD format 8 4 read-write 0 15 MNT Minute tens in BCD format 12 3 read-write 0 7 HU Hour units in BCD format 16 4 read-write 0 15 HT Hour tens in BCD format 20 2 read-write 0 3 PM AM/PM notation 22 1 read-write PM AM AM or 24-hour format 0 PM PM 1 DR DR RTC date register 0x4 0x20 0x00002101 0xFFFFFFFF DU Date units in BCD format 0 4 read-write 0 15 DT Date tens in BCD format 4 2 read-write 0 3 MU Month units in BCD format 8 4 read-write 0 15 MT Month tens in BCD format 12 1 read-write 0 1 WDU Week day units ... 13 3 read-write 1 7 YU Year units in BCD format 16 4 read-write 0 15 YT Year tens in BCD format 20 4 read-write 0 15 SSR SSR RTC subsecond register 0x8 0x20 0x00000000 0xFFFFFFFF SS Synchronous binary counter SS[31:16]: Synchronous binary counter MSB values When Binary or Mixed mode is selected (BIN = 01 or 10 or 11): SS[31:16] are the 16 MSB of the SS[31:0] free-running down-counter. When BCD mode is selected (BIN=00): SS[31:16] are forced by hardware to 0x0000. SS[15:0]: Subsecond value/synchronous binary counter LSB values When Binary mode is selected (BIN = 01 or 10 or 11): SS[15:0] are the 16 LSB of the SS[31:0] free-running down-counter. When BCD mode is selected (BIN=00): SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. 0 32 read-only 0 65535 ICSR ICSR RTC initialization control and status register 0xC 0x20 0x00000007 0xFFFFFFFF WUTWF Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 BIN Binary mode 8 2 read-write BCDU BCD update (BIN = 10 or 11) In mixed mode when both BCD calendar and binary extended counter are used (BIN = 10 or 11), the calendar second is incremented using the SSR Least Significant Bits. 10 3 read-write RECALPF Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly. 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER RTC prescaler register 0x10 0x20 0x007F00FF 0xFFFFFFFF PREDIV_S Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) 0 15 read-write 0 32767 PREDIV_A Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) 16 7 read-write 0 127 WUTR WUTR RTC wakeup timer register 0x14 0x20 0x0000FFFF 0xFFFFFFFF WUT Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs between WUT and (WUT + 2) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden. 0 16 read-write 0 65535 WUTOCLR Wakeup auto-reload output clear value When WUTOCLR[15:0] is different from 0x0000, WUTF is set by hardware when the auto-reload down-counter reaches 0 and is cleared by hardware when the auto-reload downcounter reaches WUTOCLR[15:0]. When WUTOCLR[15:0] = 0x0000, WUTF is set by hardware when the WUT down-counter reaches 0 and is cleared by software. 16 16 read-write CR CR RTC control register 0x18 0x20 0x00000000 0xFFFFFFFF WUCKSEL ck_wut wakeup clock selection 10x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. 11x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. Furthermore, 2sup16/sup is added to the WUT counter value. 0 3 read-write WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. 3 1 read-write TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON RTC_REFIN reference clock detection enable (50 or 60 Hz) Note: BIN must be 0x00 and PREDIV_S must be 0x00FF. 4 1 read-write REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. 5 1 read-write BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT Hour format 6 1 read-write FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 SSRUIE SSR underflow interrupt enable 7 1 read-write 2 0x1 A,B ALR%sE Alarm %s enable 8 1 read-write ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF = 1 before enabling it again. 10 1 read-write WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE timestamp enable 11 1 read-write TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 read-write ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE Wakeup timer interrupt enable 14 1 read-write WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE Timestamp interrupt enable 15 1 read-write TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 16 1 write-only ADD1HW Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 17 1 write-only SUB1HW Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. 18 1 read-write BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 COSEL Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to Section 31.3.17: Calibration clock output. 19 1 read-write COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL Output polarity This bit is used to configure the polarity of TAMPALRM output. 20 1 read-write POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL Output selection These bits are used to select the flag to be routed to TAMPALRM output. 21 2 read-write OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE Calibration output enable This bit enables the CALIB output 23 1 read-write COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ITSE timestamp on internal event enable 24 1 read-write ITSE Disabled Internal event timestamp disabled 0 Enabled Internal event timestamp enabled 1 TAMPTS Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set up to 3 ck_apre cycles after the tamper flags. 25 1 read-write TAMPTS Disabled Tamper detection event does not cause a RTC timestamp to be saved 0 Enabled Save RTC timestamp on tamper detection event 1 TAMPOE Tamper detection output enable on TAMPALRM 26 1 read-write TAMPOE Disabled The tamper flag is not routed on TAMPALRM 0 Enabled The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL 1 ALRAFCLR Alarm A flag automatic clear 27 1 read-write ALRBFCLR Alarm B flag automatic clear 28 1 read-write TAMPALRM_PU TAMPALRM pull-up enable 29 1 read-write TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPALRM_TYPE TAMPALRM output type 30 1 read-write TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 OUT2EN RTC_OUT2 output enable With this bit set, the RTC outputs can be remapped on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL different 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1. 31 1 read-write OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 PRIVCFGR PRIVCFGR RTC privilege mode control register 0x1C 0x20 0x00000000 0xFFFFFFFF ALRAPRIV Alarm A and SSR underflow privilege protection 0 1 read-write ALRBPRIV Alarm B privilege protection 1 1 read-write WUTPRIV Wakeup timer privilege protection 2 1 read-write TSPRIV Timestamp privilege protection 3 1 read-write CALPRIV Shift register, Delight saving, calibration and reference clock privilege protection 13 1 read-write INITPRIV Initialization privilege protection 14 1 read-write PRIV RTC privilege protection 15 1 read-write WPR WPR RTC write protection register 0x24 0x20 0x00000000 0xFFFFFFFF KEY Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection. 0 8 write-only KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR RTC calibration register 0x28 0x20 0x00000000 0xFFFFFFFF CALM Calibration minus The frequency of the calendar is reduced by masking CALM out of 2sup20/sup RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section 31.3.15: RTC smooth digital calibration on page 1092. 0 9 read-write 0 511 LPCAL RTC low-power mode 12 1 read-write CALW16 Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section 31.3.15: RTC smooth digital calibration. 13 1 read-write CALW16 SixteenSeconds When CALW16 is set to â1â, the 16-second calibration cycle period is selected.This bit must not be set to â1â if CALW8=1 1 CALW8 Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section 31.3.15: RTC smooth digital calibration. 14 1 read-write CALW8 EightSeconds When CALW8 is set to â1â, the 8-second calibration cycle period is selected 1 CALP Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. Refer to Section 31.3.15: RTC smooth digital calibration. 15 1 read-write CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 SHIFTR SHIFTR RTC shift control register 0x2C 0x20 0x00000000 0xFFFFFFFF SUBFS Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). In mixed BCD-binary mode (BIN=10 or 11), the SUBFS[14:BCDU+8] must be written with 0. Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time. 0 15 write-only 0 32767 ADD1S Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. 31 1 write-only ADD1SW Add1 Add one second to the clock/calendar 1 TSTR TSTR RTC timestamp time register 0x30 TSDR TSDR RTC timestamp date register 0x34 TSSSR TSSSR RTC timestamp subsecond register 0x38 2 0x8 A,B ALRM%sR ALRM%sR Alarm %s register 0x40 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write 0 15 ST Second tens in BCD format 4 3 read-write 0 7 MSK1 Alarm seconds mask 7 1 read-write MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day donât care in Alarm comparison 1 MNU Minute units in BCD format 8 4 read-write 0 15 MNT Minute tens in BCD format 12 3 read-write 0 7 MSK2 Alarm minutes mask 15 1 read-write HU Hour units in BCD format 16 4 read-write 0 15 HT Hour tens in BCD format 20 2 read-write 0 3 PM AM/PM notation 22 1 read-write PM AM AM or 24-hour format 0 PM PM 1 MSK3 Alarm hours mask 23 1 read-write DU Date units or day in BCD format 24 4 read-write 0 15 DT Date tens in BCD format 28 2 read-write 0 3 WDSEL Week day selection 30 1 read-write WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is donât care. 1 MSK4 Alarm date mask 31 1 read-write 2 0x8 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 0x00000000 0xFFFFFFFF SS Subseconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. This field is the mirror of SS[14:0] in the RTC_ALRMABINR, and so can also be read or written through RTC_ALRMABINR. 0 15 read-write 0 32767 MASKSS Mask the most-significant bits starting at this bit ... From 32 to 63: All 32 SS bits are compared and must match to activate alarm. Note: In BCD mode (BIN=00) the overflow bits of the synchronous counter (bits 31:15) are never compared. These bits can be different from 0 only after a shift operation. 24 6 read-write SSCLR Clear synchronous counter on alarm (Binary mode only) Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). 31 1 read-write SR SR RTC status register 0x50 0x20 0x00000000 0xFFFFFFFF 2 0x1 A,B ALR%sF Alarm %s flag 0 1 read-only ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 WUTF Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. If WUTOCLR[15:0] is different from 0x0000, WUTF is cleared by hardware when the wakeup auto-reload counter reaches WUTOCLR value. If WUTOCLR[15:0] is 0x0000, WUTF must be cleared by software. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only WUTF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSF Timestamp flag This flag is set by hardware when a timestamp event occurs. If ITSF flag is set, TSF must be cleared together with ITSF. Note: TSF is not set if TAMPTS = 1 and the tamper flag is read during the 3 ck_apre cycles following tamper event. Refer to Timestamp on tamper event for more details. 3 1 read-only TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVF Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSF Internal timestamp flag This flag is set by hardware when a timestamp on the internal event occurs. 5 1 read-only ITSF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SSRUF SSR underflow flag This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1. 6 1 read-only MISR MISR RTC masked interrupt status register 0x54 0x20 0x00000000 0xFFFFFFFF 2 0x1 A,B ALR%sMF Alarm %s masked flag 0 1 read-only ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 WUTMF Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only WUTMF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSMF Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF. 3 1 read-only TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVMF Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSMF Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised. 5 1 read-only ITSMF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SSRUMF SSR underflow masked flag This flag is set by hardware when the SSR underflow interrupt occurs. 6 1 read-only SCR SCR RTC status clear register 0x5C 0x20 0x00000000 0xFFFFFFFF CALRAF Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register. 0 1 write-only CALRAF Clear Clear interrupt flag 1 CALRBF Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register. 1 1 write-only CWUTF Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register. 2 1 write-only CTSF Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF. 3 1 write-only CTSOVF Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 write-only CITSF Clear internal timestamp flag Writing 1 in this bit clears the ITSF bit in the RTC_SR register. 5 1 write-only CSSRUF Clear SSR underflow flag Writing '1' in this bit clears the SSRUF in the RTC_SR register. 6 1 write-only 2 0x4 A,B ALR%sBINR ALR%sBINR Alarm %s binary mode register 0x70 0x20 0x00000000 0xFFFFFFFF SS Synchronous counter alarm value in Binary mode This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR. 0 32 read-write SBS System configuration, boot and security SBS 0x44000400 0x0 0x150 registers HDPLCR HDPLCR SBS temporal isolation control register 0x10 0x20 0x000000B4 0xFFFFFFFF INCR_HDPL increment HDPL value Other: all other values allow a HDPL level increment. 0 8 read-write INCR_HDPL Increment Increment HDPL value 106 HDPLSR HDPLSR SBS temporal isolation status register 0x14 0x20 0x00000000 0x00000000 HDPL temporal isolation level This bitfield returns the current temporal isolation level. 0 8 read-only HDPLR HDPL1 Protection level to be used to execute and protect immutable Root of Trust (IROT) stage 81 HDPL3 Protection level to be used to execute the application 111 HDPL2 Protection level to be used to execute and protect an updatable Root of Trust (UROT) stage 138 HDPL0 Protection level reserved for ST code and data 180 DBGCR DBGCR SBS debug control register 0x20 0x20 0x00000000 0xFFFFFFFF AP_UNLOCK access port unlock Write 0xB4 to this bitfield to open the device access port. 0 8 read-write AP_UNLOCK Unlocked Device access port unlocked 180 DBG_UNLOCK debug unlock when DBG_AUTH_HDPL is reached Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register. 8 8 read-write DBG_UNLOCK Unlocked Debug unlocked when HDPLSR:HDPL is equal to DBG_AUTH_HDPL 180 DBG_AUTH_HDPL authenticated debug temporal isolation level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the debug never opens. 16 8 read-write DBG_AUTH_HDPL HDPL1 Protection level to be used to execute and protect immutable Root of Trust (IROT) stage 81 HDPL3 Protection level to be used to execute the application 111 HDPL2 Protection level to be used to execute and protect an updatable Root of Trust (UROT) stage 138 DBGLOCKR DBGLOCKR SBS debug lock register 0x24 0x20 0x000000B4 0xFFFFFFFF DBGCFG_LOCK debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. 0xC3 is the recommended value to lock the debug configuration using this bitfield. Other: Writes to SBS_DBGCR ignored 0 8 read-write DBGCFG_LOCKR read Locked Debug configuration register (DBGCR) locked 106 Unlocked Debug configuration register (DBGCR) unlocked 180 DBGCFG_LOCKW write Unlocked Debug configuration register (DBGCR) unlocked 180 Locked Debug configuration register (DBGCR) locked 195 PMCR PMCR SBS product mode and configuration register 0x100 0x20 0x00000000 0xFFFFFFFF BOOSTEN booster enable Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range. 8 1 read-write BOOSTVDDSEL booster V DD selection Note: Booster must not be used when V DDA 2.7 V, but V DD 2.7 V (add current consumption). Note: When both V DD 2.7 V and V DDA 2.7 V, booster is needed to get full AC performances from I/O analog switches. 9 1 read-write PB6_FMP Fast-mode Plus command on PB(6) 16 1 read-write PB6_FMP Disabled Fast-mode Plus mode on PB6 disabled 0 Enabled Fast-mode Plus mode on PB6 enabled 1 PB7_FMP Fast-mode Plus command on PB(7) 17 1 read-write PB7_FMP Disabled Fast-mode Plus mode on PB7 disabled 0 Enabled Fast-mode Plus mode on PB7 enabled 1 PB8_FMP Fast-mode Plus command on PB(8) 18 1 read-write PB8_FMP Disabled Fast-mode Plus mode on PB8 disabled 0 Enabled Fast-mode Plus mode on PB8 enabled 1 FPUIMR FPUIMR SBS FPU interrupt mask register 0x104 0x20 0x0000001F 0xFFFFFFFF FPU_IE0 FPU interrupt enable 0 1 FPU_IE0 Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 FPU_IE1 FPU interrupt enable 1 1 FPU_IE2 FPU interrupt enable 2 1 FPU_IE3 FPU interrupt enable 3 1 FPU_IE4 FPU interrupt enable 4 1 FPU_IE5 FPU interrupt enable 5 1 MESR MESR SBS memory erase status register 0x108 0x20 0x00000000 0xFFFFFFFF MCLR erase after reset status This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, ICACHE. It is set by hardware and reset by software 0 1 read-write oneToClear MCLRR read EraseInProgress Memory erase in progress 0 EraseComplete Memory erase complete 1 MCLRW write Clear Clear memory erase status flag 1 IPMEE end-of-erase status for ICACHE This bit shows the status of the protection for ICACHE. It is set by hardware and reset by software. 16 1 read-write oneToClear IPMEER read EraseInProgress ICACHE erase ongoing 0 EraseCompleted ICACHE erase completed 1 IPMEEW write Clear Clear ICACHE erase status flag 1 CCCSR CCCSR SBS compensation cell for I/Os control and status register 0x110 0x20 0x00000000 0xFFFFFFFF EN1 enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. 0 1 read-write EN1 Disabled I/O compensation cell disabled 0 Enabled I/O compensation cell enabled 1 CS1 code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. 1 1 read-write CS1 Cell Code from cell selected 0 CCSWCR Code from CCSWCR selected 1 EN2 enable compensation cell for VDDIO2 power rail This bit enables the I/O compensation cell. 2 1 read-write CS2 code selection for VDDIO2 power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. 3 1 read-write RDY1 VDDIO compensation cell ready flag This bit provides the status of the compensation cell. 8 1 read-only RDY1R NotReady VDDIO compensation cell not ready 0 Ready VDDIO compensation cell ready 1 RDY2 VDDIO2 compensation cell ready flag This bit provides the status of the VDDIO2 compensation cell. 9 1 read-only CCVALR CCVALR SBS compensation cell for I/Os value register 0x114 0x20 0x00000088 0xFFFFFFFF ANSRC1 compensation value for the NMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. 0 4 read-only APSRC1 compensation value for the PMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. 4 4 read-only ANSRC2 Compensation value for the NMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. 8 4 read-only APSRC2 compensation value for the PMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. 12 4 read-only CCSWCR CCSWCR SBS compensation cell for I/Os software code register 0x118 0x20 0x00007878 0xFFFFFFFF SW_ANSRC1 NMOS compensation code for VDD power rails This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR. 0 4 read-write 0 15 SW_APSRC1 PMOS compensation code for the VDD power rails This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR. 4 4 read-write 0 15 SW_ANSRC2 NMOS compensation code for VDDIO power rails This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR. 8 4 read-write 0 15 SW_APSRC2 PMOS compensation code for the V DDIO power rails This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR. 12 4 read-write 0 15 CFGR2 CFGR2 SBS Class B register 0x120 0x20 0x00000000 0xFFFFFFFF CLL core lockup lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1 break inputs. 0 1 read-write CLL Disconnected Flag/Interrupt disconnected from timer break inputs 0 Connected Flag/Interrupt connected to timer break inputs 1 SEL SRAM ECC error lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1. 1 1 read-write PVDL PVD lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1 break inputs. 2 1 read-write ECCL ECC lock This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1. 3 1 read-write CNSLCKR CNSLCKR SBS CPU lock register 0x144 0x20 0x00000000 0xFFFFFFFF LOCKNSVTOR VTOR_NS register lock This bit is set by software and cleared only by a system reset. 0 1 read-write LOCKNSVTOR Unlocked VTOR_NS register write enabled 0 Locked VTOR_NS register write disabled 1 LOCKNSMPU MPU register lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers. 1 1 read-write LOCKNSMPU Unlocked MPU registers write enabled 0 Locked MPU registers write disabled 1 ECCNMIR ECCNMIR SBS flift ECC NMI mask register 0x14C 0x20 0x00000000 0xFFFFFFFF ECCNMI_MASK_EN NMI behavior setup when a double ECC error occurs on flitf data part 0 1 read-write ECCNMI_MASK_EN Enabled NMI enabled 0 Disabled NMI disabled 1 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 55 CR1 CR1 SPI/I2S control register 1 0x0 0x20 0x00000000 0xFFFFFFFF SPE serial peripheral enable This bit is set by and cleared by software. When SPE=1, SPI data transfer is enabled, SPI_CFG1 and SPI_CFG2 configuration registers, CRCPOLY, UDRDR, IOLOCK bit in the SPI_CR1 register are write protected. They can be changed only when SPE=0. When SPE=0 any SPI operation is stopped and disabled, all the pending requests of the events with enabled interrupt are blocked except the MODF interrupt request (but their pending still propagates the request of the spi_plck clock), the SS output is deactivated at master, the RDY signal keeps not ready status at slave, the internal state machine is reseted, all the FIFOs content is flushed, CRC calculation initialized, receive data register is read zero. SPE is cleared and cannot be set when MODF error flag is active. 0 1 read-write SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 MASRX master automatic suspension in Receive mode This bit is set and cleared by software to control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. When SPI communication is suspended by hardware automatically, it could happen that few bits of next frame are already clocked out due to internal synchronization delay. This is why, the automatic suspension is not quite reliable when size of data drops below 8 bits. In this case, a safe suspension can be achieved by combination with delay inserted between data frames applied when MIDI parameter keeps a non zero value; sum of data size and the interleaved SPI cycles should always produce interval at length of 8 SPI clock periods at minimum. After software clearing of the SUSP bit, the communication resumes and continues by subsequent bits transaction without any next constraint. Prior the SUSP bit is cleared, the user must release the RxFIFO space as much as possible by reading out all the data packets available at RxFIFO based on the RXP flag indication to prevent any subsequent suspension. 8 1 read-write MASRX Disabled Automatic suspend in master receive-only mode disabled 0 Enabled Automatic suspend in master receive-only mode enabled 1 CSTART master transfer start This bit can be set by software if SPI is enabled only to start an SPI or I2S/PCM communication. In SPI mode, it is cleared by hardware when end of transfer (EOT) flag is set or when a transaction suspend request is accepted. In I2S/PCM mode, it is also cleared by hardware as described in the . In SPI mode, the bit is taken into account at master mode only. If transmission is enabled, communication starts or continues only if any data is available in the transmission FIFO. 9 1 read-write CSTART NotStarted Do not start master transfer 0 Started Start master transfer 1 CSUSP master SUSPend request This bit reads as zero. In Master mode, when this bit is set by software, the CSTART bit is reset at the end of the current frame and communication is suspended. The user has to check SUSP flag to check end of the frame transaction. The Master mode communication must be suspended (using this bit or keeping TXDR empty) before going to Low-power mode. Can be used in SPI or I2S mode. After software suspension, SUSP flag has to be cleared and SPI disabled and re-enabled before the next transaction starts. 10 1 write-only CSUSPW NotRequested Do not request master suspend 0 Requested Request master suspend 1 HDDIR Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/Tx direction of the data transfer. This bit is ignored in Full-Duplex or any Simplex configuration. 11 1 read-write HDDIR Receiver Receiver in half duplex mode 0 Transmitter Transmitter in half duplex mode 1 SSI internal SS signal input level This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the peripheral SS input internally and the I/O value of the SS pin is ignored. 12 1 read-write SSI SlaveSelected 0 is forced onto the SS signal and the I/O value of the SS pin is ignored 0 SlaveNotSelected 1 is forced onto the SS signal and the I/O value of the SS pin is ignored 1 CRC33_17 32-bit CRC polynomial configuration 13 1 read-write CRC33_17 Disabled Full size (33/17 bit) CRC polynomial is not used 0 Enabled Full size (33/17 bit) CRC polynomial is used 1 RCRCINI CRC calculation initialization pattern control for receiver 14 1 read-write RCRCINI AllZeros All zeros RX CRC initialization pattern 0 AllOnes All ones RX CRC initialization pattern 1 TCRCINI CRC calculation initialization pattern control for transmitter 15 1 read-write TCRCINI AllZeros All zeros TX CRC initialization pattern 0 AllOnes All ones TX CRC initialization pattern 1 IOLOCK locking the AF configuration of associated IOs This bit is set by software and cleared by hardware whenever the SPE bit is changed from 1 to 0. When this bit is set, SPI_CFG2 register content cannot be modified. This bit can be set when SPI is disabled only else it is write protected. It is cleared and cannot be set when MODF bit is set. 16 1 read-write IOLOCK Unlocked IO configuration unlocked 0 Locked IO configuration locked 1 CR2 CR2 SPI/I2S control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TSIZE number of data at current transfer When these bits are changed by software, the SPI has to be disabled. Endless transaction is initialized when CSTART is set while zero value is stored at TSIZE. TSIZE cannot be set to 0xFFFF respective 0x3FFF value when CRC is enabled. Note: TSIZE[15:10] bits are reserved at limited feature set instances and must be kept at reset value. 0 16 read-write 0 65535 CFG1 CFG1 SPI/I2S configuration register 1 0x8 0x20 0x00070007 0xFFFFFFFF DSIZE number of bits in at single SPI data frame ..... Note: Maximum data size can be limited up to 16-bits at some instances. At instances with limited set of features, DSIZE2:0] bits are reserved and must be kept at reset state. DSIZE[4:3] bits then control next settings of data size: 00xxx: 8-bits 01xxx: 16-bits 10xxx: 24-bits 11xxx: 32-bits. 0 5 read-write 0 31 FTHLV FIFO threshold level Defines number of data frames at single data packet. Size of the packet should not exceed 1/2 of FIFO space. 5 4 read-write FTHLV OneFrame 1 frame 0 TwoFrames 2 frames 1 ThreeFrames 3 frames 2 FourFrames 4 frames 3 FiveFrames 5 frames 4 SixFrames 6 frames 5 SevenFrames 7 frames 6 EightFrames 8 frames 7 NineFrames 9 frames 8 TenFrames 10 frames 9 ElevenFrames 11 frames 10 TwelveFrames 12 frames 11 ThirteenFrames 13 frames 12 FourteenFrames 14 frames 13 FifteenFrames 15 frames 14 SixteenFrames 16 frames 15 UDRCFG behavior of slave transmitter at underrun condition For more details see underrun condition. 9 1 read-write UDRCFG Constant Slave sends a constant underrun pattern 0 RepeatReceived Slave repeats last received data frame from master 1 RXDMAEN Rx DMA stream enable 14 1 read-write RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx DMA stream enable 15 1 read-write TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 CRCSIZE length of CRC frame to be transacted and compared Most significant bits are taken into account from polynomial calculation when CRC result is transacted or compared. The length of the polynomial is not affected by this setting. ..... The value must be set equal or multiply of data size (DSIZE[4:0]). Its maximum size corresponds to DSIZE maximum at the instance. Note: The most significant bit at CRCSIZE bit field is reserved at the peripheral instances where data size is limited to 16-bit. 16 5 read-write 0 31 CRCEN hardware CRC computation enable 22 1 read-write CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 MBR master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too (see mode). 28 3 read-write MBR Div2 f_spi_ker_ck / 2 0 Div4 f_spi_ker_ck / 4 1 Div8 f_spi_ker_ck / 8 2 Div16 f_spi_ker_ck / 16 3 Div32 f_spi_ker_ck / 32 4 Div64 f_spi_ker_ck / 64 5 Div128 f_spi_ker_ck / 128 6 Div256 f_spi_ker_ck / 256 7 BPASS bypass of the prescaler at master baud rate clock generator 31 1 read-write BPASS Disabled Bypass is disabled 0 Enabled Bypass is enabled 1 CFG2 CFG2 SPI/I2S configuration register 2 0xC 0x20 0x00000000 0xFFFFFFFF MSSI Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS opening a session and the beginning of the first data frame of the session in Master mode when SSOE is enabled. ... Note: This feature is not supported in TI mode. To include the delay, the SPI must be disabled and re-enabled between sessions. 0 4 read-write 0 15 MIDI master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in Master mode. ... Note: This feature is not supported in TI mode. 4 4 read-write 0 15 RDIOM RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero. 13 1 read-write RDIOM Active RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) 0 Pin RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) 1 RDIOP RDY signal input/output polarity 14 1 read-write RDIOP High high level of the signal means the slave is ready for communication 0 Low low level of the signal means the slave is ready for communication 1 IOSWP swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins alternate functions are inverted. Original MISO pin becomes MOSI and original MOSI pin becomes MISO. Note: This bit can be also used in PCM and I2S modes to swap SDO and SDI pins. 15 1 read-write IOSWP Disabled MISO and MOSI not swapped 0 Enabled MISO and MOSI swapped 1 COMM SPI Communication Mode 17 2 read-write COMM FullDuplex Full duplex 0 Transmitter Simplex transmitter only 1 Receiver Simplex receiver only 2 HalfDuplex Half duplex 3 SP serial protocol others: reserved, must not be used 19 3 read-write SP Motorola Motorola SPI protocol 0 TI TI SPI protocol 1 MASTER SPI Master 22 1 read-write MASTER Slave Slave configuration 0 Master Master configuration 1 LSBFRST data frame format Note: This bit can be also used in PCM and I2S modes. 23 1 read-write LSBFRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 CPHA clock phase 24 1 read-write CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CPOL clock polarity 25 1 read-write CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 SSM software management of SS signal input When master uses hardware SS output (SSM=0 and SSOE=1) the SS signal input is forced to not active state internally to prevent master mode fault error. 26 1 read-write SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSIOP SS input/output polarity 28 1 read-write SSIOP ActiveLow Low level is active for SS signal 0 ActiveHigh High level is active for SS signal 1 SSOE SS output enable This bit is taken into account in Master mode only 29 1 read-write SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 SSOM SS output management in Master mode This bit is taken into account in Master mode when SSOE is enabled. It allows the SS output to be configured between two consecutive data transfers. 30 1 read-write SSOM Asserted SS is asserted until data transfer complete 0 NotAsserted Data frames interleaved with SS not asserted during MIDI 1 AFCNTR alternate function GPIOs control This bit is taken into account when SPE=0 only When SPI has to be disabled temporary for a specific configuration reason (e.g. CRC reset, CPHA or HDDIR change) setting this bit prevents any glitches on the associated outputs configured at alternate function mode by keeping them forced at state corresponding the current SPI configuration. Note: This bit can be also used in PCM and I2S modes. Note: The bit AFCNTR must not be set to 1, when the block is in slave mode. 31 1 read-write AFCNTR NotControlled Peripheral takes no control of GPIOs while disabled 0 Controlled Peripheral controls GPIOs while disabled 1 IER IER SPI/I2S interrupt enable register 0x10 0x20 0x00000000 0xFFFFFFFF RXPIE RXP interrupt enable 0 1 read-write RXPIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TXPIE TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event. 1 1 read-write DXPIE DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event. 2 1 read-write EOTIE EOT, SUSP and TXC interrupt enable 3 1 read-write TXTFIE TXTFIE interrupt enable 4 1 read-write UDRIE UDR interrupt enable 5 1 read-write OVRIE OVR interrupt enable 6 1 read-write CRCEIE CRC error interrupt enable 7 1 read-write TIFREIE TIFRE interrupt enable 8 1 read-write MODFIE mode Fault interrupt enable 9 1 read-write SR SR SPI/I2S status register 0x14 0x20 0x00001002 0xFFFFFFFF RXP Rx-Packet available In I2S mode, it must be interpreted as follow: RxFIFO level is lower than FTHLV In I2S mode, it must be interpreted as follow: RxFIFO level is higher or equal to FTHLV RXP flag is changed by hardware. It monitors number of overall data currently available at RxFIFO if SPI is enabled. It has to be checked once a data packet is completely read out from RxFIFO. 0 1 read-only RXP Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXP Tx-Packet space available In I2S mode, it must be interpreted as follow: there is less than FTHLV free locations in the TxFIFO In I2S mode, it must be interpreted as follow: there is FTHLV or more than FTHLV free locations in the TxFIFO TXP flag is changed by hardware. It monitors overall space currently available at TxFIFO no matter if SPI is enabled or not. It has to be checked once a complete data packet is stored at TxFIFO. 1 1 read-only TXP Full Tx buffer full 0 NotFull Tx buffer not full 1 DXP duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode. 2 1 read-only DXP Unavailable Duplex packet unavailable: no space for transmission and/or no data received 0 Available Duplex packet available: space for transmission and data received 1 EOT end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when SPI is re-enabled or when TSIZE number of data have been transmitted and/or received on the SPI. EOT is cleared when SPI is re-enabled or by writing 1 to EOTC bit of SPI_IFCR optionally. EOT flag triggers an interrupt if EOTIE bit is set. If DXP flag is used until TXTF flag is set and DXPIE is cleared, EOT can be used to download the last packets contained into RxFIFO in one-shot. In master, EOT event terminates the data transaction and handles SS output optionally. When CRC is applied, the EOT event is extended over the CRC frame transaction. To restart the internal state machine properly, SPI is strongly suggested to be disabled and re-enabled before next transaction starts despite its setting is not changed. 3 1 read-only EOT NotCompleted Transfer ongoing or not started 0 Completed Transfer complete 1 TXTF transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transfer have been submitted for transmission by application software or DMA, that is when TSIZE number of data have been pushed into the TxFIFO. This bit is cleared by software write 1 to TXTFC bit of SPI_IFCR exclusively. TXTF flag triggers an interrupt if TXTFIE bit is set. TXTF setting clears the TXPIE and DXPIE masks so to off-load application software from calculating when to disable TXP and DXP interrupts. 4 1 read-only TXTF NotCompleted Transmission buffer incomplete 0 Completed Transmission buffer filled with at least one transfer 1 UDR underrun This bit is cleared when SPI is re-enabled or by writing 1 to UDRC bit of SPI_IFCR optionally. Note: In SPI mode, the UDR flag applies to Slave mode only. In I2S/PCM mode, (when available) this flag applies to Master and Slave mode 5 1 read-only UDR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 OVR overrun This bit is cleared when SPI is re-enabled or by writing 1 to OVRC bit of SPI_IFCR optionally. 6 1 read-only OVR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 CRCE CRC error This bit is cleared when SPI is re-enabled or by writing 1 to CRCEC bit of SPI_IFCR optionally. 7 1 read-only CRCE NoError No CRC error detected 0 Error CRC error detected 1 TIFRE TI frame format error This bit is cleared by writing 1 to TIFREC bit of SPI_IFCR exclusively. 8 1 read-only TIFRE NoError TI frame format error detected 0 Error TI frame format error detected 1 MODF mode fault This bit is cleared by writing 1 to MODFC bit of SPI_IFCR exclusively. 9 1 read-only MODF NoFault No mode fault detected 0 Fault Mode fault detected 1 SUSP suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is completed after CSUSP request is done or at master automatic suspend receive mode (MASRX bit is set at SPI_CR1 register) on RxFIFO full condition. SUSP generates an interrupt when EOTIE is set. This bit has to be cleared prior SPI is disabled and this is done by writing 1 to SUSPC bit of SPI_IFCR exclusively. 11 1 read-only SUSP NotSuspended Master not suspended 0 Suspended Master suspended 1 TXC TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE=0 the TXC is changed by hardware exclusively and it raises each time the TxFIFO becomes empty and there is no activity on the bus. If TSIZE 0 there is no specific reason to monitor TXC as it just copies the EOT flag value including its software clearing. The TXC generates an interrupt when EOTIE is set. 12 1 read-only TXC Ongoing Transmission ongoing 0 Completed Transmission completed 1 RXPLVL RxFIFO packing level When RXWNE=0 and data size is set up to 16-bit, the value gives number of remaining data frames persisting at RxFIFO. Note: (*): Optional value when data size is set up to 8-bit only. When data size is greater than 16-bit, these bits are always read as 00. In that consequence, the single data frame received at the FIFO cannot be detected neither by RWNE nor by RXPLVL bits if data size is set from 17 to 24 bits. The user then must apply other methods like TSIZE0 or FTHLV=0. 13 2 read-only RXPLVL ZeroFrames Zero frames beyond packing ratio available 0 OneFrame One frame beyond packing ratio available 1 TwoFrames Two frame beyond packing ratio available 2 ThreeFrames Three frame beyond packing ratio available 3 RXWNE RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with RXPLVL[1:0] information about RxFIFO occupancy by residual data. 15 1 read-only RXWNE LessThan32 Less than 32-bit data frame received 0 AtLeast32 At least 32-bit data frame received 1 CTSIZE number of data frames remaining in current TSIZE session The value is not quite reliable when traffic is ongoing on bus or during autonomous operation in low-power mode. Note: CTSIZE[15:0] bits are not available in instances with limited set of features. 16 16 read-only 0 65535 IFCR IFCR SPI/I2S interrupt/status flags clear register 0x18 0x20 0x00000000 0xFFFFFFFF EOTC end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register 3 1 write-only oneToClear EOTCW Clear Clear interrupt flag 1 TXTFC transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR register 4 1 write-only oneToClear UDRC underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register 5 1 write-only oneToClear OVRC overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register 6 1 write-only oneToClear CRCEC CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register 7 1 write-only oneToClear TIFREC TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register 8 1 write-only oneToClear MODFC mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register 9 1 write-only oneToClear SUSPC SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register 11 1 write-only oneToClear TXDR TXDR SPI/I2S transmit data register 0x20 0x20 0x00000000 0xFFFFFFFF TXDR transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFIFO. Note: In SPI mode, data is always right-aligned. Alignment of data at I2S mode depends on DATLEN and DATFMT setting. Unused bits are ignored when writing to the register, and read as zero when the register is read. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is written by single access. halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be written by single access. word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be written by single access. Write access of this register less than the configured data size is forbidden. 0 32 write-only 0 4294967295 TXDR16 Direct 16-bit access to transmit data register TXDR 0x20 0x10 write-only TXDR Transmit data register 0 16 0 65535 TXDR8 Direct 8-bit access to transmit data register TXDR 0x20 0x8 write-only TXDR Transmit data register 0 8 0 255 RXDR RXDR SPI/I2S receive data register 0x30 0x20 0x00000000 0xFFFFFFFF RXDR receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is accessed. Note: In SPI mode, data is always right-aligned. Alignment of data at I2S mode depends on DATLEN and DATFMT setting. Unused bits are read as zero when the register is read. Writing to the register is ignored. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is read by single access halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be read by single access word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be read by single access. Read access of this register less than the configured data size is forbidden. 0 32 read-only RXDR16 Direct 16-bit access to receive data register RXDR 0x30 0x10 read-only RXDR Receive data register 0 16 RXDR8 Direct 8-bit access to receive data register RXDR 0x30 0x8 read-only RXDR Receive data register 0 8 CRCPOLY CRCPOLY SPI/I2S polynomial register 0x40 0x20 0x00000107 0xFFFFFFFF CRCPOLY CRC polynomial register This register contains the polynomial for the CRC calculation. The default 9-bit polynomial setting 0x107 corresponds to default 8-bit setting of DSIZE. It is compatible with setting 0x07 used at some other ST products with fixed length of the polynomial string where the most significant bit of the string is always kept hidden. Length of the polynomial is given by the most significant bit of the value stored at this register. It has to be set greater than DSIZE. CRC33_17 bit has to be set additionally with CRCPOLY register when DSIZE is configured to maximum 32-bit or 16-bit size and CRC is enabled (to keep polynomial length grater than data size). Note: CRCPOLY[31:16] bits are reserved at instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 0 32 read-write 0 4294967295 TXCRC TXCRC SPI/I2S transmitter CRC register 0x44 0x20 0x00000000 0xFFFFFFFF TXCRC CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the computed CRC value of the subsequently transmitted bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. Note: a read to this register when the communication is ongoing could return an incorrect value. Note: not used for the I2S mode. Note: TXCRC[31-16] bits are reserved at instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. Note: The configuration of CRCSIZE bit field is not taken into account when the content of this register is read by software. No masking is applied for unused bits at this case. 0 32 read-only 0 4294967295 RXCRC RXCRC SPI/I2S receiver CRC register 0x48 0x20 0x00000000 0xFFFFFFFF RXCRC CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the computed CRC value of the subsequently received bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. Note: a read to this register when the communication is ongoing could return an incorrect value. Not used for the I2S mode. RXCRC[31-16] bits are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. Note: The configuration of CRCSIZE bit field is not taken into account when the content of this register is read by software. No masking is applied for unused bits at this case. 0 32 read-only 0 4294967295 UDRDR UDRDR SPI/I2S underrun data register 0x4C 0x20 0x00000000 0xFFFFFFFF UDRDR data at slave underrun condition The register is taken into account in Slave mode and at underrun condition only. The number of bits considered depends on DSIZE bit settings of the SPI_CFG1 register. Underrun condition handling depends on setting UDRCFG bit at SPI_CFG1 register. Note: UDRDR[31-16] bits are reserved at the peripheral instances with data size limited to 16-bit. There is no constraint when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 0 32 read-write 0 4294967295 I2SCFGR I2SCFGR SPI/I2S configuration register 0x50 0x20 0x00000000 0xFFFFFFFF I2SMOD I2S mode selection 0 1 read-write I2SMOD SPI SPI mode selected 0 I2S I2S/PCM mode selected 1 I2SCFG I2S configuration mode others, not used 1 3 read-write I2SCFG SlaveTransmit Slave, transmit 0 SlaveReceive Slave, recteive 1 MasterTransmit Master, transmit 2 MasterReceive Master, receive 3 SlaveFullDuplex Slave, full duplex 4 MasterFullDuplex Master, full duplex 5 I2SSTD I2S standard selection For more details on I2S standards, refer to 4 2 read-write I2SSTD Philips I2S Philips standard 0 LeftAligned MSB/left justified standard 1 RightAligned LSB/right justified standard 2 PCM PCM standard 3 PCMSYNC PCM frame synchronization 7 1 read-write PCMSYNC Short Short PCM frame synchronization 0 Long Long PCM frame synchronization 1 DATLEN data length to be transferred 8 2 read-write DATLEN Bits16 16 bit data length 0 Bits24 24 bit data length 1 Bits32 32 bit data length 2 CHLEN channel length (number of bits per audio channel) 10 1 read-write CHLEN Bits16 16 bit per channel 0 Bits32 32 bit per channel 1 CKPOL serial audio clock polarity 11 1 read-write CKPOL SampleOnRising Signals are sampled on rising and changed on falling clock edges 0 SampleOnFalling Signals are sampled on falling and changed on rising clock edges 1 FIXCH fixed channel length in slave 12 1 read-write FIXCH NotFixed The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account) 0 Fixed The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN) 1 WSINV word select inversion This bit is used to invert the default polarity of WS signal. WS is LOW. In PCM mode the start of frame is indicated by a rising edge. WS is HIGH. In PCM mode the start of frame is indicated by a falling edge. 13 1 read-write WSINV Disabled Word select inversion disabled 0 Enabled Word select inversion enabled 1 DATFMT data format 14 1 read-write DATFMT RightAligned The data inside RXDR and TXDR are right aligned 0 LeftAligned The data inside RXDR and TXDR are left aligned 1 I2SDIV I2S linear prescaler I2SDIV can take any values except the value 1, when ODD is also equal to 1. Refer to for details 16 8 read-write ODD odd factor for the prescaler Refer to for details 24 1 read-write ODD Even Real divider value is I2SDIV*2 0 Odd Real divider value is I2SDIV*2 + 1 1 MCKOE master clock output enable 25 1 read-write MCKOE Disabled Master clock output disabled 0 Enabled Master clock output enabled 1 SPI2 0x40003800 SPI2 SPI2 global interrupt 56 SPI3 0x40003C00 SPI3 SPI3 global interrupt 57 TAMP Tamper and backup registers TAMP 0x44007C00 0x0 0x400 registers TAMP TAMP global interrupt 4 CR1 CR1 TAMP control register 1 0x0 0x20 0x00000000 0xFFFFFFFF TAMP1E Tamper detection on TAMP_IN1 enable 0 1 read-write TAMP2E Tamper detection on TAMP_IN2 enable 1 1 read-write ITAMP1E Internal tamper 1 enable 16 1 read-write ITAMP2E Internal tamper 2 enable 17 1 read-write ITAMP3E Internal tamper 3 enable 18 1 read-write ITAMP4E Internal tamper 4 enable 19 1 read-write ITAMP5E Internal tamper 5 enable 20 1 read-write ITAMP6E Internal tamper 6 enable 21 1 read-write ITAMP7E Internal tamper 7 enable 22 1 read-write ITAMP8E Internal tamper 8 enable 23 1 read-write ITAMP9E Internal tamper 9 enable 24 1 read-write ITAMP11E Internal tamper 11 enable 26 1 read-write ITAMP12E Internal tamper 12 enable 27 1 read-write ITAMP13E Internal tamper 13 enable 28 1 read-write ITAMP15E Internal tamper 15 enable 30 1 read-write CR2 CR2 TAMP control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TAMP1NOER Tamper 1 no erase 0 1 read-write TAMP2NOER Tamper 2 no erase 1 1 read-write TAMP1MSK Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set. 16 1 read-write TAMP2MSK Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set. 17 1 read-write BKBLOCK Backup registers and device secretssup(1)/sup access blocked 22 1 read-write BKERASE Backup registers and device secretssup(1)/sup erase Writing '1' to this bit reset the backup registers and device secretssup(1)/sup. Writing 0 has no effect. This bit is always read as 0. 23 1 write-only TAMP1TRG Active level for tamper 1 input If TAMPFLT = 00 Tamper 1 input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper 1 input falling edge triggers a tamper detection event. 24 1 read-write TAMP2TRG Active level for tamper 2 input If TAMPFLT = 00 Tamper 2 input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper 2 input falling edge triggers a tamper detection event. 25 1 read-write CR3 CR3 TAMP control register 3 0x8 0x20 0x00000000 0xFFFFFFFF ITAMP1NOER Internal Tamper 1 no erase 0 1 read-write ITAMP2NOER Internal Tamper 2 no erase 1 1 read-write ITAMP3NOER Internal Tamper 3 no erase 2 1 read-write ITAMP4NOER Internal Tamper 4 no erase 3 1 read-write ITAMP5NOER Internal Tamper 5 no erase 4 1 read-write ITAMP6NOER Internal Tamper 6 no erase 5 1 read-write ITAMP7NOER Internal Tamper 7 no erase 6 1 read-write ITAMP8NOER Internal Tamper 8 no erase 7 1 read-write ITAMP9NOER Internal Tamper 9 no erase 8 1 read-write ITAMP11NOER Internal Tamper 11 no erase 10 1 read-write ITAMP12NOER Internal Tamper 12 no erase 11 1 read-write ITAMP13NOER Internal Tamper 13 no erase 12 1 read-write ITAMP15NOER Internal Tamper 15 no erase 14 1 read-write FLTCR FLTCR TAMP filter control register 0xC 0x20 0x00000000 0xFFFFFFFF TAMPFREQ Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled. 0 3 read-write TAMPFLT TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs. 3 2 read-write TAMPPRCH TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. 5 2 read-write TAMPPUDIS TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample. 7 1 read-write ATCR1 ATCR1 TAMP active tamper control register 1 0x10 0x20 0x00070000 0xFFFFFFFF TAMP1AM Tamper 1 active mode 0 1 read-write TAMP2AM Tamper 2 active mode 1 1 read-write ATOSEL1 Active tamper shared output 1 selection The selected output must be available in the package pinout 8 2 read-write ATOSEL2 Active tamper shared output 2 selection The selected output must be available in the package pinout 10 2 read-write ATOSEL3 Active tamper shared output 3 selection The selected output must be available in the package pinout 12 2 read-write ATCKSEL Active tamper RTC asynchronous prescaler clock selection These bits selects the RTC asynchronous prescaler stage output. The selected clock is CK_ATPRE. f CK_ATPRE = f RTCCLK / 2supATCKSEL /supwhen (PREDIV_A+1) = 128. ... Note: These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 CK_ATPRE cycles after all the active tampers are disable. 16 3 read-write ATPER Active tamper output change period The tamper output is changed every CK_ATPER = (2supATPER /supx CK_ATPRE) cycles. Refer to Table 239: Minimum ATPER value. 24 3 read-write ATOSHARE Active tamper output sharing TAMP_IN1 is compared with TAMPOUTSEL1 TAMP_IN2 is compared with TAMPOUTSEL2 TAMP_IN3 is compared with TAMPOUTSEL3 TAMP_IN4 is compared with TAMPOUTSEL4 TAMP_IN5 is compared with TAMPOUTSEL5 TAMP_IN6 is compared with TAMPOUTSEL6 TAMP_IN7 is compared with TAMPOUTSEL7 TAMP_IN8 is compared with TAMPOUTSEL8 30 1 read-write FLTEN Active tamper filter enable 31 1 read-write ATSEEDR ATSEEDR TAMP active tamper seed register 0x14 0x20 0x00000000 0xFFFFFFFF SEED Pseudo-random generator seed value This register must be written four times with 32-bit values to provide the 128-bit seed to the PRNG. Writing to this register automatically sends the seed value to the PRNG. 0 32 write-only ATOR ATOR TAMP active tamper output register 0x18 0x20 0x00000000 0xFFFFFFFF PRNG Pseudo-random generator value This field provides the values of the PRNG output. Because of potential inconsistencies due to synchronization delays, PRNG must be read at least twice. The read value is correct if it is equal to previous read value. 0 8 read-only SEEDF Seed running flag This flag is set by hardware when a new seed is written in the TAMP_ATSEEDR. It is cleared by hardware when the PRNG has absorbed this new seed, and by system reset. The TAMP APB cock must not be switched off as long as SEEDF is set. 14 1 read-only INITS Active tamper initialization status This flag is set by hardware when the PRNG has absorbed the first 128-bit seed, meaning that the enabled active tampers are functional. This flag is cleared when the active tampers are disabled. 15 1 read-only ATCR2 ATCR2 TAMP active tamper control register 2 0x1C 0x20 0x00000000 0xFFFFFFFF ATOSEL1 Active tamper shared output 1 selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 8 3 read-write ATOSEL2 Active tamper shared output 2 selection The selected output must be available in the package pinout. Bits 12:11 are the mirror of ATOSEL2[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 11 3 read-write ATOSEL3 Active tamper shared output 3 selection The selected output must be available in the package pinout. Bits 15:14 are the mirror of ATOSEL3[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 14 3 read-write ATOSEL4 Active tamper shared output 4 selection The selected output must be available in the package pinout. Bits 18:17 are the mirror of ATOSEL2[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 17 3 read-write ATOSEL5 Active tamper shared output 5 selection The selected output must be available in the package pinout. 20 3 read-write ATOSEL6 Active tamper shared output 6 selection The selected output must be available in the package pinout. 23 3 read-write ATOSEL7 Active tamper shared output 7 selection The selected output must be available in the package pinout. 26 3 read-write ATOSEL8 Active tamper shared output 8 selection The selected output must be available in the package pinout. 29 3 read-write CFGR CFGR TAMP configuration register 0x20 0x20 0x00000000 0xFFFFFFFF BKPRW Backup registers read/write protection offset Protection zone 1 is defined for backup registers from TAMP_BKP0R to TAMP_BKPxR (x = BKPRW-1, from 0 to 128). Note: If BKPRW = 0: there is no protection zone 1. Note: If BKPRWPRIV is set, BKPRW[7:0] can be written only in privileged mode. 0 8 read-write BKPW Backup registers write protection offset Protection zone 2 is defined for backup registers from TAMP_BKPyR (y = BKPRW, from 0 to 128) to TAMP_BKPzR (z = BKPW-1, from 0 to 128, BKPW greater than or equal BKPRW): Protection zone 3 defined for backup registers from TAMP_BKPtR (t = BKPW, from 0 to 127).. 16 8 read-write PRIVCFGR PRIVCFGR TAMP privilege configuration register 0x24 0x20 0x00000000 0xFFFFFFFF CNT1PRIV Monotonic counter 1 privilege protection 15 1 read-write BKPRWPRIV Backup registers zone 1 privilege protection 29 1 read-write BKPWPRIV Backup registers zone 2 privilege protection 30 1 read-write TAMPPRIV Tamper privilege protection (excluding backup registers) Note: Refer to Section 32.3.6: TAMP privilege protection modes for details on the read protection. 31 1 read-write IER IER TAMP interrupt enable register 0x2C 0x20 0x00000000 0xFFFFFFFF TAMP1IE Tamper 1 interrupt enable 0 1 read-write TAMP2IE Tamper 2 interrupt enable 1 1 read-write ITAMP1IE Internal tamper 1 interrupt enable 16 1 read-write ITAMP2IE Internal tamper 2 interrupt enable 17 1 read-write ITAMP3IE Internal tamper 3 interrupt enable 18 1 read-write ITAMP4IE Internal tamper 4 interrupt enable 19 1 read-write ITAMP5IE Internal tamper 5 interrupt enable 20 1 read-write ITAMP6IE Internal tamper 6 interrupt enable 21 1 read-write ITAMP7IE Internal tamper 7 interrupt enable 22 1 read-write ITAMP8IE Internal tamper 8 interrupt enable 23 1 read-write ITAMP9IE Internal tamper 9 interrupt enable 24 1 read-write ITAMP11IE Internal tamper 11 interrupt enable 26 1 read-write ITAMP12IE Internal tamper 12 interrupt enable 27 1 read-write ITAMP13IE Internal tamper 13 interrupt enable 28 1 read-write ITAMP15IE Internal tamper 15 interrupt enable 30 1 read-write SR SR TAMP status register 0x30 0x20 0x00000000 0xFFFFFFFF TAMP1F TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP1 input. 0 1 read-only TAMP2F TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP2 input. 1 1 read-only ITAMP1F Internal tamper 1 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 1. 16 1 read-only ITAMP2F Internal tamper 2 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 2. 17 1 read-only ITAMP3F Internal tamper 3 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3. 18 1 read-only ITAMP4F Internal tamper 4 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 4. 19 1 read-only ITAMP5F Internal tamper 5 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5. 20 1 read-only ITAMP6F Internal tamper 6 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. 21 1 read-only ITAMP7F Internal tamper 7 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 7. 22 1 read-only ITAMP8F Internal tamper 8 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 8. 23 1 read-only ITAMP9F Internal tamper 9 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 9. 24 1 read-only ITAMP11F Internal tamper 11 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 11. 26 1 read-only ITAMP12F Internal tamper 12 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 12. 27 1 read-only ITAMP13F Internal tamper 13 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 13. 28 1 read-only ITAMP15F Internal tamper 15 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 15. 30 1 read-write MISR MISR TAMP masked interrupt status register 0x34 0x20 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 interrupt masked flag This flag is set by hardware when the tamper 1 interrupt is raised. 0 1 read-only TAMP2MF TAMP2 interrupt masked flag This flag is set by hardware when the tamper 2 interrupt is raised. 1 1 read-only ITAMP1MF Internal tamper 1 interrupt masked flag This flag is set by hardware when the internal tamper 1 interrupt is raised. 16 1 read-only ITAMP2MF Internal tamper 2 interrupt masked flag This flag is set by hardware when the internal tamper 2 interrupt is raised. 17 1 read-only ITAMP3MF Internal tamper 3 interrupt masked flag This flag is set by hardware when the internal tamper 3 interrupt is raised. 18 1 read-only ITAMP4MF Internal tamper 4 interrupt masked flag This flag is set by hardware when the internal tamper 4 interrupt is raised. 19 1 read-only ITAMP5MF Internal tamper 5 interrupt masked flag This flag is set by hardware when the internal tamper 5 interrupt is raised. 20 1 read-only ITAMP6MF Internal tamper 6 interrupt masked flag This flag is set by hardware when the internal tamper 6 interrupt is raised. 21 1 read-only ITAMP7MF Internal tamper 7 tamper interrupt masked flag This flag is set by hardware when the internal tamper 7 interrupt is raised. 22 1 read-only ITAMP8MF Internal tamper 8 interrupt masked flag This flag is set by hardware when the internal tamper 8 interrupt is raised. 23 1 read-only ITAMP9MF internal tamper 9 interrupt masked flag This flag is set by hardware when the internal tamper 9 interrupt is raised. 24 1 read-only ITAMP11MF internal tamper 11 interrupt masked flag This flag is set by hardware when the internal tamper 11 interrupt is raised. 26 1 read-only ITAMP12MF internal tamper 12 interrupt masked flag This flag is set by hardware when the internal tamper 12 interrupt is raised. 27 1 read-only ITAMP13MF internal tamper 13 interrupt masked flag This flag is set by hardware when the internal tamper 13 interrupt is raised. 28 1 read-only ITAMP15MF internal tamper 15 interrupt masked flag This flag is set by hardware when the internal tamper 15 interrupt is raised. 30 1 read-only SCR SCR TAMP status clear register 0x3C 0x20 0x00000000 0xFFFFFFFF CTAMP1F Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register. 0 1 write-only CTAMP2F Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register. 1 1 write-only CITAMP1F Clear ITAMP1 detection flag Writing 1 in this bit clears the ITAMP1F bit in the TAMP_SR register. 16 1 write-only CITAMP2F Clear ITAMP2 detection flag Writing 1 in this bit clears the ITAMP2F bit in the TAMP_SR register. 17 1 write-only CITAMP3F Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register. 18 1 write-only CITAMP4F Clear ITAMP4 detection flag Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register. 19 1 write-only CITAMP5F Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register. 20 1 write-only CITAMP6F Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register. 21 1 write-only CITAMP7F Clear ITAMP7 detection flag Writing 1 in this bit clears the ITAMP7F bit in the TAMP_SR register. 22 1 write-only CITAMP8F Clear ITAMP8 detection flag Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register. 23 1 write-only CITAMP9F Clear ITAMP9 detection flag Writing 1 in this bit clears the ITAMP9F bit in the TAMP_SR register. 24 1 write-only CITAMP11F Clear ITAMP11 detection flag Writing 1 in this bit clears the ITAMP11F bit in the TAMP_SR register. 26 1 write-only CITAMP12F Clear ITAMP12 detection flag Writing 1 in this bit clears the ITAMP12F bit in the TAMP_SR register. 27 1 write-only CITAMP13F Clear ITAMP13 detection flag Writing 1 in this bit clears the ITAMP13F bit in the TAMP_SR register. 28 1 write-only CITAMP15F Clear ITAMP15 detection flag Writing 1 in this bit clears the ITAMP15F bit in the TAMP_SR register. 30 1 write-only COUNT1R COUNT1R TAMP monotonic counter 1 register 0x40 0x20 0x00000000 0xFFFFFFFF COUNT This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value. 0 32 read-only ERCFGR ERCFGR TAMP erase configuration register 0x54 0x20 0x00000000 0xFFFFFFFF ERCFG0 Configurable device secrets configuration 0 1 read-write 32 0x4 0-31 BKP%sR BKP%sR TAMP backup %s register 0x100 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. 0 32 read-write TIM1 Advanced-control timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_TERR_IERR TIM1 break/TIM1 transition error/TIM1 index error 41 TIM1_UP TIM1 Update 42 TIM1_TRG_COM_DIR_IDX TIM1 trigger and commutation/TIM1 direction change interrupt/TIM1 index 43 TIM1_CC TIM1 capture compare interrupt 44 CR1 CR1 TIM1 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and the dead-time and sampling clock (t DTS )used by the dead-time generators and the digital filters (tim_etr_in, tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM1 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS MMS[2:0]: Master mode selection These bits select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: Other codes reserved Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write 0 7 TI1S tim_ti1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 4 0x2 1-4 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 MMS2 Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (tim_trgo2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 20 4 read-write MMS_3 MMS[3] 25 1 read-write 0 1 SMCR SMCR TIM1 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection 0 3 read-write 0 7 OCCS OCREF clear selection This bit is used to select the OCREF clear source. 3 1 read-write TS TS[2:0]: Trigger selection This bitfield is combined with TS[4:3] bits. This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 605: TIMx internal trigger connection for more details on tim_itrx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write 0 7 MSM Master/slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be connected to tim_etrf in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 SMS[3] 16 1 read-write 0 1 TS2 TS[4:3] 20 2 read-write 0 3 SMSPE SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded 24 1 read-write SMSPE NotPreloaded SMSM[3:0] is not preloaded 0 PreloadEnabled SMSM[3:0] is preload is enabled 1 SMSPS SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active 25 1 read-write SMSPS Update SMSM[3:0] is preloaded from Update event 0 Index SMSM[3:0] is preloaded from Index event 1 DIER DIER TIM1 DMA/interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 read-write COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write IDXIE Disabled Index change interrupt disabled 0 Enabled Index change interrupt enabled 1 DIRIE Direction change interrupt enable 21 1 read-write DIRIE Disabled Direction change interrupt disabled 0 Enabled Direction change interrupt enabled 1 IERRIE Index error interrupt enable 22 1 read-write IERRIE Disabled Index error interrupt disabled 0 Enabled Index error interrupt enabled 1 TERRIE Transition error interrupt enable 23 1 read-write TERRIE Disabled Transition error interrupt disabled 0 Enabled Transition error interrupt enabled 1 SR SR TIM1 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to Section 65.6.3: TIM1 slave mode control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag This flag is set by hardware on COM event (when capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 B2IF Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 8 1 read-write zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 SBIF System break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 13 1 read-write zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 CC5IF Compare 5 interrupt flag Refer to CC1IF description Note: Channel 5 can only be configured as output. 16 1 read-write zeroToClear read write CC6IF Compare 6 interrupt flag Refer to CC1IF description Note: Channel 6 can only be configured as output. 17 1 read-write zeroToClear read write IDXF Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by software by writing it to '0'. 20 1 read-write zeroToClear IDXFR read NoTrigger No index event occurred 0 Trigger An index event has occurred 1 IDXFW write Clear Clear flag 0 DIRF Direction change interrupt flag This flag is set by hardware when the direction changes in encoder mode (DIR bit value in TIMx_CR is changing). It is cleared by software by writing it to '0'. 21 1 read-write zeroToClear DIRFR read NoTrigger No direction change has been detected 0 Trigger A direction change has been detected 1 DIRFW write Clear Clear flag 0 IERRF Index error interrupt flag This flag is set by hardware when an index error is detected. It is cleared by software by writing it to '0'. 22 1 read-write zeroToClear IERRFR read NoTrigger No index error has been detected 0 Trigger An index erorr has been detected 1 IERRFW write Clear Clear flag 0 TERRF Transition error interrupt flag This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to '0'. 23 1 read-write zeroToClear TERRFR read NoTrigger No encoder transition error has been detected 0 Trigger An encoder transition error has been detected 1 TERRFW write Clear Clear flag 0 EGR EGR TIM1 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 B2G Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 8 1 write-only B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Input CCMR1_Input TIM1 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM1 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM1 capture/compare mode register 2 [alternate] 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM1 capture/compare mode register 2 [alternate] CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM1 capture/compare enable register 0x20 0x20 0x00000000 0xFFFFFFFF 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM1 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM1 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (f tim_cnt_ck ) is equal to f tim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode'). 0 16 read-write 0 65535 ARR ARR TIM1 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 65.3.3: Time-base unit on page 4457 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 RCR RCR TIM1 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable. It also defines the update interrupt generation rate, if this interrupt is enable. When the repetition down-counter reaches zero, an update event is generated and it restarts counting from REP value. As the repetition counter is reloaded with REP value only at the repetition update event UEV, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode. 0 16 read-write 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 BDTR BDTR TIM1 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx = DT=DTG[7:0]x t dtg with t dtg =t DTS . DTG[7:5]=10x = DT=(64+DTG[5:0])xt dtg with T dtg =2xt DTS . DTG[7:5]=110 = DT=(32+DTG[4:0])xt dtg with T dtg =8xt DTS . DTG[7:5]=111 = DT=(32+DTG[4:0])xt dtg with T dtg =16xt DTS . Example if T DTS =125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 65.6.11: TIM1 capture/compare enable register (TIM1_CCER)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 65.6.11: TIM1 capture/compare enable register (TIM1_CCER)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per Figure 635: Break and Break2 circuitry overview). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (tim_brk or tim_brk2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (Section 65.6.11: TIM1 capture/compare enable register (TIM1_CCER)). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample tim_brk input and the length of the digital filter applied to tim_brk. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write BKF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 BK2F Break 2 filter This bit-field defines the frequency used to sample tim_brk2 input and the length of the digital filter applied to tim_brk2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 20 4 read-write BK2E Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per Figure 635: Break and Break2 circuitry overview). Note: The BRKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 24 1 read-write BK2P Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 25 1 read-write BKDSRM Break disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write BKDSRM Armed Break input BRK is armed 0 Disarmed Break input BRK is disarmed 1 BK2DSRM Break2 disarm Refer to BKDSRM description 27 1 read-write BK2DSRM Armed Break input BRK2 is armed 0 Disarmed Break input BRK2 is disarmed 1 BKBID Break bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write BKBID Input Break input BRK in input mode 0 Bidirectional Break input BRK in bidirectional mode 1 BK2BID Break2 bidirectional Refer to BKBID description 29 1 read-write BK2BID Input Break input BRK2 in input mode 0 Bidirectional Break input BRK2 in bidirectional mode 1 CCR5 CCR5 capture/compare register 0x48 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 GC5C1 Group channel 5 and channel 1 Distortion on channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 29 1 read-write GC5C2 Group channel 5 and channel 2 Distortion on channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 30 1 read-write GC5C3 Group channel 5 and channel 3 Distortion on channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. 31 1 read-write CCR6 CCR6 capture/compare register 0x4C 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 CCMR3_Output CCMR3_Output TIM1 capture/compare mode register 3 0x50 0x20 0x00000000 0xFFFFFFFF 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 5-6 OC%sM Output compare %s mode 4 3 read-write 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write DTR2 DTR2 TIM1 timer deadtime register 2 0x54 0x20 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs, on the falling edge. DTGF[7:5]=0xx = DTF=DTGF[7:0]x t dtg with t dtg =t DTS . DTGF[7:5]=10x = DTF=(64+DTGF[5:0])xt dtg with T dtg =2xt DTS . DTGF[7:5]=110 = DTF=(32+DTGF[4:0])xt dtg with T dtg =8xt DTS . DTGF[7:5]=111 = DTF=(32+DTGF[4:0])xt dtg with T dtg =16xt DTS . Example if T DTS =125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write DTAE Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 16 1 read-write DTPE Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 17 1 read-write ECR ECR TIM1 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable This bit indicates if the Index event resets the counter. 0 1 read-write IDIR Index direction This bit indicates in which direction the Index event resets the counter. Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled). 1 2 read-write IBLK Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input 3 2 read-write FIDX First index This bit indicates if the first index only is taken into account 5 1 read-write IPOS Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit indicates in which AB input configuration the Index event resets the counter. In directional clock mode or clock plus direction mode (SMS[3:0] = 1010, 1011, 1100, 1101), these bits indicates on which level the Index event resets the counter. In bidirectional clock mode, this applies for both clock inputs. x0: Index resets the counter when clock is 0 x1: Index resets the counter when clock is 1 Note: IPOS[1] bit is not significant 6 2 read-write PW Pulse width This bitfield defines the pulse duration, as following: t PW = PW[7:0] x t PWG 16 8 read-write PWPRSC Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following: t PWG = (2sup(PWPRSC[2:0])/sup) x t tim_ker_ck 24 3 read-write TISEL TISEL TIM1 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[0..15] input ... Refer to Section 65.3.2: TIM1 pins and internal signals for interconnects list. 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[0..15] input ... Refer to Section 65.3.2: TIM1 pins and internal signals for interconnects list. 8 4 read-write TI3SEL Selects tim_ti3[0..15] input ... Refer to Section 65.3.2: TIM1 pins and internal signals for interconnects list. 16 4 read-write TI4SEL Selects tim_ti4[0..15] input ... Refer to Section 65.3.2: TIM1 pins and internal signals for interconnects list. 24 4 read-write AF1 AF1 TIM1 alternate function option register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timer's tim_brk input. TIMx_BKIN input is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKINE Disabled BKIN input disabled 0 Enabled BKIN input enabled 1 BKCMP1E tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timer's tim_brk input. tim_brk_cmp1 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP1E Disabled Input disabled 0 Enabled Input enabled 1 BKCMP2E tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timer's tim_brk input. tim_brk_cmp2 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKCMP3E tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timer's tim_brk input. tim_brk_cmp3 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 3 1 read-write BKCMP4E tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timer's tim_brk input. tim_brk_cmp4 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 4 1 read-write BKCMP5E tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timer's tim_brk input. tim_brk_cmp5 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 5 1 read-write BKCMP6E tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timer's tim_brk input. tim_brk_cmp6 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 6 1 read-write BKCMP7E tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timer's tim_brk input. tim_brk_cmp7 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 7 1 read-write BKCMP8E tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timer's tim_brk input. tim_brk_cmp8 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BKINP TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKINP NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKCMP1P tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP1P NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKCMP2P tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 13 1 read-write ETRSEL etr_in source selection These bits select the etr_in input source. ... Refer to Section 65.3.2: TIM1 pins and internal signals for product specific implementation. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM1 alternate function register 2 0x64 0x20 0x00000001 0xFFFFFFFF BK2INE TIMx_BKIN2 input enable This bit enables the TIMx_BKIN2 alternate function input for the timer's tim_brk2 input. TIMx_BKIN2 input is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BK2INE Disabled BKIN input disabled 0 Enabled BKIN input enabled 1 BK2CMP1E tim_brk2_cmp1 enable This bit enables the tim_brk2_cmp1 for the timer's tim_brk2 input. tim_brk2_cmp1 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BK2CMP1E Disabled Input disabled 0 Enabled Input enabled 1 BK2CMP2E tim_brk2_cmp2 enable This bit enables the tim_brk2_cmp2 for the timer's tim_brk2 input. tim_brk2_cmp2 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BK2CMP3E tim_brk2_cmp3 enable This bit enables the tim_brk2_cmp3 for the timer's tim_brk2 input. tim_brk2_cmp3 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 3 1 read-write BK2CMP4E tim_brk2_cmp4 enable This bit enables the tim_brk2_cmp4 for the timer's tim_brk2 input. tim_brk2_cmp4 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 4 1 read-write BK2CMP5E tim_brk2_cmp5 enable This bit enables the tim_brk2_cmp5 for the timer's tim_brk2 input. tim_brk2_cmp5 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 5 1 read-write BK2CMP6E tim_brk2_cmp6 enable This bit enables the tim_brk2_cmp6 for the timer's tim_brk2 input. tim_brk2_cmp6 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 6 1 read-write BK2CMP7E tim_brk2_cmp7 enable This bit enables the tim_brk2_cmp7 for the timer's tim_brk2 input. tim_brk2_cmp7 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 7 1 read-write BK2CMP8E tim_brk2_cmp8 enable This bit enables the tim_brk2_cmp8 for the timer's tim_brk2 input. tim_brk2_cmp8 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BK2INP TIMx_BKIN2 input polarity This bit selects the TIMx_BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BK2INP NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BK2CMP1P tim_brk2_cmp1 input polarity This bit selects the tim_brk2_cmp1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BK2CMP1P NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BK2CMP2P tim_brk2_cmp2 input polarity This bit selects the tim_brk2_cmp2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write BK2CMP3P tim_brk2_cmp3 input polarity This bit selects the tim_brk2_cmp3 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 12 1 read-write BK2CMP4P tim_brk2_cmp4 input polarity This bit selects the tim_brk2_cmp4 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 13 1 read-write OCRSEL ocref_clr source selection These bits select the ocref_clr input source. ... Refer to Section 65.3.2: TIM1 pins and internal signals for product specific information. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 3 read-write 0 7 DCR DCR TIM1 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data are copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data are transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data are also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write 0 18 DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Others: reserved 16 4 read-write 0 7 DMAR DMAR TIM1 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write 0 65535 TIM2 General-purpose timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 45 CR1 CR1 TIM2 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and sampling clock used by the digital filters (tim_etr_in, tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering Enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM2 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Others: Reserved Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write 0 7 TI1S tim_ti1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS_3 Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Others: Reserved Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 25 1 read-write 0 1 SMCR SMCR TIM2 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write 0 7 OCCS OCREF clear selection This bit is used to select the OCREF clear source Note: If the OCREF clear selection feature is not supported, this bit is reserved and forced by hardware to '0'. . 3 1 read-write TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write 0 7 MSM Master/Slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of tim_ker_ck frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be connected to tim_etrf in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write 0 1 TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write 0 3 SMSPE SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded 24 1 read-write SMSPE NotPreloaded SMSM[3:0] is not preloaded 0 PreloadEnabled SMSM[3:0] is preload is enabled 1 SMSPS SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active 25 1 read-write SMSPS Update SMSM[3:0] is preloaded from Update event 0 Index SMSM[3:0] is preloaded from Index event 1 DIER DIER TIM2 DMA/Interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write IDXIE Disabled Index change interrupt disabled 0 Enabled Index change interrupt enabled 1 DIRIE Direction change interrupt enable 21 1 read-write DIRIE Disabled Direction change interrupt disabled 0 Enabled Direction change interrupt enabled 1 IERRIE Index error interrupt enable 22 1 read-write IERRIE Disabled Index error interrupt disabled 0 Enabled Index error interrupt enabled 1 TERRIE Transition error interrupt enable 23 1 read-write TERRIE Disabled Transition error interrupt disabled 0 Enabled Transition error interrupt enabled 1 SR SR TIM2 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 IDXF Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by software by writing it to '0'. 20 1 read-write zeroToClear IDXFR read NoTrigger No index event occurred 0 Trigger An index event has occurred 1 IDXFW write Clear Clear flag 0 DIRF Direction change interrupt flag This flag is set by hardware when the direction changes in encoder mode (DIR bit value in TIMx_CR is changing). It is cleared by software by writing it to '0'. 21 1 read-write zeroToClear DIRFR read NoTrigger No direction change has been detected 0 Trigger A direction change has been detected 1 DIRFW write Clear Clear flag 0 IERRF Index error interrupt flag This flag is set by hardware when an index error is detected. It is cleared by software by writing it to '0'. 22 1 read-write zeroToClear IERRFR read NoTrigger No index error has been detected 0 Trigger An index erorr has been detected 1 IERRFW write Clear Clear flag 0 TERRF Transition error interrupt flag This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to '0'. 23 1 read-write zeroToClear TERRFR read NoTrigger No encoder transition error has been detected 0 Trigger An encoder transition error has been detected 1 TERRFW write Clear Clear flag 0 EGR EGR TIM2 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM2 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM2 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM2 capture/compare mode register 2 [alternate] 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM2 capture/compare mode register 2 [alternate] CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM2 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM2 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register holds the non-dithered part. The fractional part is not available. 0 32 read-write 0 4294967295 UIFCPY Read-only copy of the UIF bit of the TIMx_ISR register 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM2 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency tim_cnt_ck is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode'). 0 16 read-write 0 65535 ARR ARR TIM2 auto-reload register 0x2C 0x20 0xFFFFFFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[31:4]. The ARR[3:0] bitfield contains the dithered part. 0 32 read-write 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 32 read-write 0 4294967295 ECR ECR TIM2 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable This bit indicates if the Index event resets the counter. 0 1 read-write IDIR Index direction This bit indicates in which direction the Index event resets the counter. Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled). 1 2 read-write IBLK Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input 3 2 read-write FIDX First index This bit indicates if the first index only is taken into account 5 1 read-write IPOS Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit indicates in which AB input configuration the Index event resets the counter. In directional clock mode or clock plus direction mode (SMS[3:0] = 1010, 1011, 1100, 1101), these bits indicates on which level the Index event resets the counter. In bidirectional clock mode, this applies for both clock inputs. x0: Index resets the counter when clock is 0 x1: Index resets the counter when clock is 1 Note: IPOS[1] bit is not significant 6 2 read-write PW Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG 16 8 read-write PWPRSC Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following: tPWG = (2(PWPRSC[2:0])) x ttim_ker_ck 24 3 read-write TISEL TISEL TIM2 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[0..15] input ... Refer to for product specific implementation. 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[0..15] input ... Refer to for product specific implementation. 8 4 read-write TI3SEL Selects tim_ti3[0..15] input ... Refer to for product specific implementation. 16 4 read-write TI4SEL Selects tim_ti4[0..15] input ... Refer to for product specific implementation. 24 4 read-write AF1 AF1 TIM2 alternate function register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection These bits select the etr_in input source. ... Refer to for product specific implementation. 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM2 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection These bits select the ocref_clr input source. ... Refer to for product specific implementation. 16 3 read-write 0 7 DCR DCR TIM2 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data are copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data are transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data are also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write 0 18 DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Others: reserved 16 4 read-write 0 7 DMAR DMAR TIM2 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write TIM3 General-purpose timers TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 global interrupt 46 CR1 CR1 TIM3 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and sampling clock used by the digital filters (tim_etr_in, tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering Enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM3 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Others: Reserved Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write 0 7 TI1S tim_ti1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS_3 Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Others: Reserved Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 25 1 read-write 0 1 SMCR SMCR TIM3 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write 0 7 OCCS OCREF clear selection This bit is used to select the OCREF clear source Note: If the OCREF clear selection feature is not supported, this bit is reserved and forced by hardware to '0'. . 3 1 read-write TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write 0 7 MSM Master/Slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of tim_ker_ck frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be connected to tim_etrf in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write 0 1 TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write 0 3 SMSPE SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded 24 1 read-write SMSPE NotPreloaded SMSM[3:0] is not preloaded 0 PreloadEnabled SMSM[3:0] is preload is enabled 1 SMSPS SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active 25 1 read-write SMSPS Update SMSM[3:0] is preloaded from Update event 0 Index SMSM[3:0] is preloaded from Index event 1 DIER DIER TIM3 DMA/Interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write IDXIE Disabled Index change interrupt disabled 0 Enabled Index change interrupt enabled 1 DIRIE Direction change interrupt enable 21 1 read-write DIRIE Disabled Direction change interrupt disabled 0 Enabled Direction change interrupt enabled 1 IERRIE Index error interrupt enable 22 1 read-write IERRIE Disabled Index error interrupt disabled 0 Enabled Index error interrupt enabled 1 TERRIE Transition error interrupt enable 23 1 read-write TERRIE Disabled Transition error interrupt disabled 0 Enabled Transition error interrupt enabled 1 SR SR TIM3 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 IDXF Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by software by writing it to '0'. 20 1 read-write zeroToClear IDXFR read NoTrigger No index event occurred 0 Trigger An index event has occurred 1 IDXFW write Clear Clear flag 0 DIRF Direction change interrupt flag This flag is set by hardware when the direction changes in encoder mode (DIR bit value in TIMx_CR is changing). It is cleared by software by writing it to '0'. 21 1 read-write zeroToClear DIRFR read NoTrigger No direction change has been detected 0 Trigger A direction change has been detected 1 DIRFW write Clear Clear flag 0 IERRF Index error interrupt flag This flag is set by hardware when an index error is detected. It is cleared by software by writing it to '0'. 22 1 read-write zeroToClear IERRFR read NoTrigger No index error has been detected 0 Trigger An index erorr has been detected 1 IERRFW write Clear Clear flag 0 TERRF Transition error interrupt flag This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to '0'. 23 1 read-write zeroToClear TERRFR read NoTrigger No encoder transition error has been detected 0 Trigger An encoder transition error has been detected 1 TERRFW write Clear Clear flag 0 EGR EGR TIM3 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM3 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM3 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM3 capture/compare mode register 2 [alternate] 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM3 capture/compare mode register 2 [alternate] CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM3 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM3 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value' Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY Value depends on IUFREMAP in TIMx_CR1. If UIFREMAP = 0 Reserved If UIFREMAP = 1 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register 31 1 read-write UIFCPYR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM3 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency tim_cnt_ck is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode'). 0 16 read-write 0 65535 ARR ARR TIM3 auto-reload register 0x2C 0x20 0xFFFFFFFF 0xFFFFFFFF ARR Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 ECR ECR TIM3 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable This bit indicates if the Index event resets the counter. 0 1 read-write IDIR Index direction This bit indicates in which direction the Index event resets the counter. Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled). 1 2 read-write IBLK Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input 3 2 read-write FIDX First index This bit indicates if the first index only is taken into account 5 1 read-write IPOS Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit indicates in which AB input configuration the Index event resets the counter. In directional clock mode or clock plus direction mode (SMS[3:0] = 1010, 1011, 1100, 1101), these bits indicates on which level the Index event resets the counter. In bidirectional clock mode, this applies for both clock inputs. x0: Index resets the counter when clock is 0 x1: Index resets the counter when clock is 1 Note: IPOS[1] bit is not significant 6 2 read-write PW Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG 16 8 read-write PWPRSC Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following: tPWG = (2(PWPRSC[2:0])) x ttim_ker_ck 24 3 read-write TISEL TISEL TIM3 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[0..15] input ... Refer to for product specific implementation. 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[0..15] input ... Refer to for product specific implementation. 8 4 read-write TI3SEL Selects tim_ti3[0..15] input ... Refer to for product specific implementation. 16 4 read-write TI4SEL Selects tim_ti4[0..15] input ... Refer to for product specific implementation. 24 4 read-write AF1 AF1 TIM3 alternate function register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection These bits select the etr_in input source. ... Refer to for product specific implementation. 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM3 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection These bits select the ocref_clr input source. ... Refer to for product specific implementation. 16 3 read-write 0 7 DCR DCR TIM3 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data are copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data are transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data are also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write 0 18 DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Others: reserved 16 4 read-write 0 7 DMAR DMAR TIM3 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write TIM6 Basic timers TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 global interrupt 49 CR1 CR1 TIM6 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM6 control register 2 0x4 0x10 0x00000000 0x0000FFFF MMS Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or he peripheral receiving the tim_trgo must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER TIM6 DMA/Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 SR SR TIM6 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. On counter overflow if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR TIM6 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT TIM6 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM6 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency ftim_cnt_ck is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register. 0 16 read-write 0 65535 ARR ARR TIM6 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded into the actual auto-reload register. Refer to for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reserved. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 TIM7 Basic timers TIM 0x40001400 TIM7 TIM7 global interrupt 50 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 58 CR1 CR1_enabled USART control register 1 [alternate] 0x0 0x20 0x00000000 0xFFFFFFFF UE USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value. 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. 1 1 read-write UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable This bit is set and cleared by software. 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable This bit is set and cleared by software. 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE=0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE=0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE=0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 OVER8 Oversampling mode This bit can only be written when the USART is disabled (UE=0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. 15 1 read-write OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 DEDT Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 16 5 read-write 0 31 DEAT Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 21 5 read-write 0 31 RTOIE Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. . 26 1 read-write RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 EOBIE End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 27 1 read-write EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). Note: FIFO mode can be used on standard UART communication, in SPI Master/Slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable This bit is set and cleared by software. 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO Full interrupt enable This bit is set and cleared by software. 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 USART control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SLVEN Synchronous Slave mode enable When the SLVEN bit is set, the Synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 0 1 read-write SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 DIS_NSS When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 3 1 read-write DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 ADDM7 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 LBDL LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 5 1 read-write LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 LBDIE LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 6 1 read-write LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBCL Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in Synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 1 read-write LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 CPHA Clock phase This bit is used to select the phase of the clock output on the SCLK pin in Synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 9 1 read-write CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 CPOL Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in Synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 10 1 read-write CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CLKEN Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UE=0). Note: If neither Synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1 11 1 read-write CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 STOP stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE=0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 LINEN LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to . 14 1 read-write LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 SWAP Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE=0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE=0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ABREN Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to . 20 1 read-write ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 ABRMOD Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to . 21 2 read-write ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 RTOEN Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to . 23 1 read-write RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ADD Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0). 24 8 read-write 0 255 CR3 CR3 USART control register 3 0x8 0x20 0x00000000 0xFFFFFFFF EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1or UDR = 1 in the USART_ISR register). 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 IREN IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 1 1 read-write IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 IRLP IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 2 1 read-write IRLP Normal Normal mode 0 LowPower Low-power mode 1 HDSEL Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE=0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 NACK Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 4 1 read-write NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 SCEN Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 5 1 read-write SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 DMAR DMA enable receiver This bit is set/reset by software 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter This bit is set/reset by software 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable This bit can only be written when the USART is disabled (UE=0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable This bit can only be written when the USART is disabled (UE=0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 ONEBIT One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE=0). 11 1 read-write ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 OVRDIS Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data are written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. . 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 SCARCNT Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In Transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In Reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE=0). When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 17 3 read-write 0 7 WUS Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 2297. 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 WUFIE Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 2297. 22 1 read-write WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 TXFTIE TXFIFO threshold interrupt enable This bit is set and cleared by software. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 TCBGTIE Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 24 1 read-write TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 RXFTCFG Receive FIFO threshold configuration Remaining combinations: Reserved 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration Remaining combinations: Reserved 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR USART baud rate register 0xC 0x20 0x00000000 0xFFFFFFFF BRR USART baud rate BRR[15:4] BRR[15:4] correspond to USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared. 0 16 read-write 0 65535 GTPR GTPR USART guard time and prescaler register 0x10 0x20 0x00000000 0xFFFFFFFF PSC Prescaler value PSC[7:0] = IrDA Normal and Low-power baud rate This bitfield is used for programming the prescaler for dividing the USART source clock to achieve the low-power frequency: The source clock is divided by the value given in the register (8 significant bits): ... PSC[4:0]: Prescaler value This bitfield is used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... This bitfield can only be written when the USART is disabled (UE=0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0' when the Smartcard and IrDA modes are not supported. Refer to . 0 8 read-write 0 255 GT Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE=0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 8 read-write 0 255 RTOR RTOR USART receiver timeout register 0x14 0x20 0x00000000 0xFFFFFFFF RTO Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bit duration. In Standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character. 0 24 read-write 0 16777215 BLEN Block Length This bitfield gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0 - 0 information characters + LEC BLEN = 1 - 0 information characters + CRC BLEN = 255 - 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. 24 8 read-write 0 255 RQR RQR USART request register 0x18 0x20 0x00000000 0xFFFFFFFF ABRRQ auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to . 0 1 write-only ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request When FIFO mode is disabled, writing '1' to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR_enabled USART interrupt and status register 0x1C 0x20 0x000000C0 0xF00FFFFF PE Parity error This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR. 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR. 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2317). This error is associated with the character in the USART_RDR. 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE=1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE=1 in the USART_CR1 register. 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXE/TXFE is set. When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. An interrupt is generated if TCIE=1 in the USART_CR1 register. TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE is set at the same time). This bit is used during single buffer transmission. 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 LBDF LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to . 8 1 read-only LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 CTSIF CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 RTOF Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. 11 1 read-only RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 EOBF End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to . 12 1 read-only EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 UDR SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to . 13 1 read-only UDR NoUnderrun No underrun error 0 Underrun underrun error 1 ABRE Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 14 1 read-only ABRF Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 15 1 read-only BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 19 1 read-only RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 WUF Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE=1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 20 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 22 1 read-only TXFE TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO Full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TCBGT Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1'. Refer to on page 2297. 25 1 read-only TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFT RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101', RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR USART interrupt flag clear register 0x20 0x20 0x00000000 0xFFFFFFFF PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register. 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TXFECF TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register. 5 1 write-only oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 TCCF Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register. 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TCBGTCF Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. 7 1 write-only oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 LBDCF LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 1 write-only oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 CTSCF CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 RTOCF Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 2297. 11 1 write-only oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 EOBCF End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 12 1 write-only oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 UDRCF SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to 13 1 write-only oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 CMCF Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register. 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 WUCF Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 2297. 20 1 write-only oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 RDR RDR USART receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RDR Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR USART transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TDR Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1. 0 9 read-write 0 511 PRESC PRESC USART prescaler register 0x2C 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to '1011' i.e. input clock divided by 256. 0 4 read-write PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 USART2 0x40004400 USART2 USART2 global interrupt 59 USART3 0x40004800 USART3 USART3 global interrupt 60 USB USB full speed USB 0x40016000 0x0 0x400 registers USB_FS USB OTG FS global interrupt 74 8 0x4 0-7 CHEP%sR CHEP%sR USB endpoint/channel %s register 0x0 0x20 0x00000000 0xFFFFFFFF EA endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. 0 4 read-write STATTX Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATTX bits to NAK, when a correct transfer has occurred (VTTX = 1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can only be 'VALID' or 'DISABLED'. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STATTX bits to 'STALL' or 'NAK' for an isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode The STATTX bits contain the information about the channel status. Refer to for the full descriptions ('Host mode' descriptions). Whereas in Device mode, these bits contain the status that are given out on the following transaction, in Host mode they capture the status last received from the device. If a NAK is received, STATTX contains the value indicating NAK. 4 2 read-write oneToToggle STATTXR read Disabled All transmission requests addressed to this endpoint/channel are ignored. 0 Stall Device mode: the endpoint is stalled and all transmission requests result in a STALL handshake. Host mode: this indicates that the device has STALLed the channel. 1 Nak Device mode: the endpoint is NAKed and all transmission requests result in a NAK handshake. Host mode: this indicates that the device has NAKed the transmission request. 2 Valid This endpoint/channel is enabled for transmission. 3 STATTXW write Keep Do not change bits 0 DTOGTX Data toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Device mode) If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. 6 1 write-only oneToToggle DTOGTXW Toggle Flip bit 1 VTTX Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written. Host mode Same as VTRX behavior but for USB OUT and SETUP transactions. 7 1 read-write zeroToClear VTTXW write Clear Clear flag 0 EPKIND endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints and usage in Device mode. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALL' instead of 'ACK'. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. 8 1 read-write UTYPE USB type of transaction These bits configure the behavior of this endpoint/channel as described in Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of isochronous channels/endpoints is explained in transfers in Device mode 9 2 read-write UTYPE Bulk Bulk endpoint 0 Control Control endpoint 1 Iso Isochronous endpoint 2 Interrupt Interrupt endpoint 3 SETUP Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. 11 1 read-only STATRX Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2492. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can be only 'VALID' or 'DISABLED', so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to 'STALL' or 'NAK' for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate. 12 2 read-write oneToToggle STATRXR read Disabled All reception requests addressed to this endpoint/channel are ignored. 0 Stall Device mode: the endpoint is stalled and all reception requests result in a STALL handshake. Host mode: this indicates that the device has STALLed the channel. 1 Nak Device mode: the endpoint is NAKed and all reception requests result in a NAK handshake. Host mode: this indicates that the device has NAKed the reception request. 2 Valid This endpoint/channel is enabled for reception. 3 STATRXW write Keep Do not change bits 0 DTOGRX Data Toggle, for reception transfers If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Device mode). If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. 14 1 write-only oneToToggle DTOGRXW Toggle Flip bit 1 VTRX USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. - A transaction ended with error sets this bit. Errors can be seen via the bits ERR_RX (host mode only). This bit is read/write but only 0 can be written, writing 1 has no effect. 15 1 read-write zeroToClear VTRXW write Clear Clear flag 0 DEVADDR Host mode Device address assigned to the endpoint during the enumeration process. 16 7 read-write NAK Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. 23 1 read-write zeroToClear NAKW write Clear Clear flag 0 LS_EP Low speed endpoint host with HUB only Host mode This bit is set by the software to send an LS transaction to the corresponding endpoint. 24 1 read-write ERR_TX Received error for an OUT/SETUP transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. 25 1 read-write zeroToClear ERR_TXW write Clear Clear flag 0 ERR_RX Received error for an IN transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. 26 1 read-write zeroToClear ERR_RXW write Clear Clear flag 0 THREE_ERR_TX Three errors for an OUT or SETUP transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error: 27 2 read-write THREE_ERR_RX Three errors for an IN transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error: 29 2 read-write CNTR CNTR 0x40 0x20 0x00000003 0xFFFFFFFF USBRST USB Reset Software can set this bit to reset the USB core, exactly as it happens when receiving a RESET signaling on the USB.The USB peripheral, in response to a RESET, resets its internal protocol state machine. Reception and transmission are disabled until the RST_DCON bit is cleared. All configuration registers do not reset: the microcontroller must explicitly clear these registers (this is to ensure that the RST_DCON interrupt can be safely delivered, and any transaction immediately followed by a RESET can be completed). The function address and endpoint registers are reset by an USB reset event. Software sets this bit to drive USB reset state on the bus and initialize the device. USB reset terminates as soon as this bit is cleared by software. 0 1 read-write USBRST NoEffect No effect 0 Reset USB core is under reset / USB reset driven 1 PDWN Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used. 1 1 read-write SUSPRDY Suspend state effective This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wakeup logic and single ended receiver is kept alive to detect remote wakeup or resume events. Software must poll this bit to confirm it to be set before any STOP mode entry. This bit is cleared by hardware simultaneously to the WAKEUP flag being set. 2 1 read-only SUSPEN Suspend state enable Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY = 1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Software can set this bit when host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. 3 1 read-write SUSPEN NoEffect No effect 0 Suspend Enter L1/L2 suspend 1 L2RES L2 remote wakeup / resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the host. It must be activated, according to USB specifications, for no less than 1 ms and no more than 15 ms after which the host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. 4 1 read-write L1RES L1 remote wakeup / resume driver Device mode Software sets this bit to send a LPM L1 50 us remote wakeup signaling to the host. After the signaling ends, this bit is cleared by hardware. 5 1 read-write L1RES NoEffect No effect 0 WakeupResume Send 50us remote-wakeup signaling to host / Send L1 resume signaling to device 1 L1REQM LPM L1 state request interrupt mask 7 1 read-write ESOFM Expected start of frame interrupt mask 8 1 read-write SOFM Start of frame interrupt mask 9 1 read-write RST_DCONM USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask 10 1 read-write SUSPM Suspend mode interrupt mask 11 1 read-write WKUPM Wakeup interrupt mask 12 1 read-write ERRM Error interrupt mask 13 1 read-write PMAOVRM Packet memory area over / underrun interrupt mask 14 1 read-write CTRM Correct transfer interrupt mask 15 1 read-write THR512M 512 byte threshold interrupt mask 16 1 read-write DDISCM Device disconnection mask Host mode 17 1 read-write HOST HOST mode HOST bit selects betweens host or device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit. 31 1 read-write ISTR ISTR USB interrupt status register 0x44 0x20 0x00000000 0xFFFFFFFF IDN Device Endpoint / host channel identification number These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: two levels are defined, in order of priority: isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only. 0 4 read-only DIR Direction of transaction This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. If DIR bit = 0, VTTX bit is set in the USB_CHEPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). If DIR bit = 1, VTRX bit or both VTTX/VTRX are set in the USB_CHEPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. This information can be used by the application software to access the USB_CHEPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only. 4 1 read-only DIR To Data transmitted by the USB peripheral to the host PC 0 From Data received by the USB peripheral from the host PC 1 L1REQ LPM L1 state request Device mode This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. This bit is read/write but only 0 can be written and writing 1 has no effect. 7 1 read-write zeroToClear L1REQR read NotL1State NotL1State 0 L1State LPM command to enter the L1 state is successfully received and acknowledged 1 L1REQW write Clear Clear flag 0 ESOF Expected start of frame Device mode This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 1 ms, but if the device does not receive it properly, the suspend timer issues this interrupt. If three consecutive ESOF interrupts are generated (for example three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the suspend timer is not yet locked. This bit is read/write but only 0 can be written and writing 1 has no effect. 8 1 read-write zeroToClear ESOFR read NotExpectedStartOfFrame NotExpectedStartOfFrame 0 ExpectedStartOfFrame An SOF packet is expected but not received 1 ESOFW write Clear Clear flag 0 SOF Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1 ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but only 0 can be written and writing 1 has no effect. 9 1 read-write zeroToClear SOFR read NotStartOfFrame NotStartOfFrame 0 StartOfFrame Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus 1 SOFW write Clear Clear flag 0 RST_DCON USB reset request (Device mode) or device connect/disconnect (Host mode) Device mode This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. Host mode This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22 cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is seen for 22 bit times consecutively from connected state. 10 1 read-write zeroToClear RST_DCONR read NotReset NotReset 0 Reset Peripheral detects an active USB RESET signal at its inputs 1 RST_DCONW write Clear Clear flag 0 SUSP Suspend mode request Device mode This bit is set by the hardware when no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only 0 can be written and writing 1 has no effect. 11 1 read-write zeroToClear SUSPR read NotSuspend NotSuspend 0 Suspend No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus 1 SUSPW write Clear Clear flag 0 WKUP Wakeup This bit is set to 1 by the hardware when, during suspend mode, activity is detected that wakes up the USB peripheral. This event asynchronously clears the SUSPRDY bit in the CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of the device (for example wakeup unit) about the start of the resume process. This bit is read/write but only 0 can be written and writing 1 has no effect. 12 1 read-write zeroToClear WKUPR read NotWakeup NotWakeup 0 Wakeup Activity is detected that wakes up the USB peripheral 1 WKUPW write Clear Clear flag 0 ERR Error This flag is set whenever one of the errors listed below has occurred: NANS: No ANSwer. The timeout for a host response has expired. CRC: Cyclic redundancy check error. One of the received CRCs, either in the token or in the data, was wrong. BST: Bit stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. FVIO: Framing format violation. A non-standard frame was received (EOP not in the right place, wrong token sequence, etc.). The USB software can usually ignore errors, since the USB peripheral and the PC host manage retransmission in case of errors in a fully transparent way. This interrupt can be useful during the software development phase, or to monitor the quality of transmission over the USB bus, to flag possible problems to the user (for example loose connector, too noisy environment, broken conductor in the USB cable and so on). This bit is read/write but only 0 can be written and writing 1 has no effect. 13 1 read-write zeroToClear ERRR read NotError Errors are not occurred 0 Error One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred 1 ERRW write Clear Clear flag 0 PMAOVR Packet memory area over / underrun This bit is set if the microcontroller has not been able to respond in time to an USB memory request. The USB peripheral handles this event in the following way: During reception an ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the transmitted stream; in both cases the host retries the transaction. The PMAOVR interrupt should never occur during normal operations. Since the failed transaction is retried by the host, the application software has the chance to speed-up device operations during this interrupt handling, to be ready for the next transaction retry; however this does not happen during isochronous transfers (no isochronous transaction is anyway retried) leading to a loss of data in this case. This bit is read/write but only 0 can be written and writing 1 has no effect. 14 1 read-write zeroToClear PMAOVRR read NotOverrun Overrun is not occurred 0 Overrun Microcontroller has not been able to respond in time to an USB memory request 1 PMAOVRW write Clear Clear flag 0 CTR Completed transfer in host mode This bit is set by the hardware to indicate that an endpoint/channel has successfully completed a transaction; using DIR and IDN bits software can determine which endpoint/channel requested the interrupt. This bit is read-only. 15 1 read-only CTR Completed Endpoint has successfully completed a transaction 1 THR512 512 byte threshold interrupt This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no effect. Note that no information is available to indicate the associated channel/endpoint, however in practice only one ISO endpoint/channel with such large packets can be supported, so that channel. 16 1 read-write zeroToClear THR512R read NotReached 512 bytes threshold not reached 0 Reached 512 bytes have been transmitted or received during isochronous transfers 1 THR512W write Clear Clear flag 0 DDISC Device connection Host mode This bit is set when a device connection is detected. This bit is read/write but only 0 can be written and writing 1 has no effect. 17 1 read-write DCON_STAT Device connection status Host mode: This bit contains information about device connection status. It is set by hardware when a LS/FS device is attached to the host while it is reset when the device is disconnected. 29 1 read-only LS_DCON Low speed device connected Host mode: This bit is set by hardware when an LS device connection is detected. Device connection is signaled after LS J-state is sampled for 22 consecutive cycles of the USB clock (48 MHz) from the unconnected state. 30 1 read-only FNR FNR USB frame number register 0x48 0x20 0x00000000 0xFFFFF000 FN Frame number This bit field contains the 11-bits frame number contained in the last received SOF packet. The frame number is incremented for every frame sent by the host and it is useful for isochronous transfers. This bit field is updated on the generation of an SOF interrupt. 0 11 read-only LSOF Lost SOF Device mode These bits are written by the hardware when an ESOF interrupt is generated, counting the number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are cleared. 11 2 read-only LCK Locked Device mode This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence. Once locked, the frame timer remains in this state until an USB reset or USB suspend event occurs. 13 1 read-only RXDM Receive data - line status This bit can be used to observe the status of received data minus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event. 14 1 read-only RXDP Receive data + line status This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event. 15 1 read-only DADDR DADDR USB_DADDR 0x4C 0x20 0x00000000 0xFFFFFFFF ADD Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel address (EA) field in the associated USB_CHEPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction 0 7 read-write EF Enable function This bit is set by the software to enable the USB Device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at 0 no transactions are handled, irrespective of the settings of USB_CHEPnR registers. 7 1 read-write LPMCSR LPMCSR USB_LPMCSR 0x54 0x20 0x00000000 0xFFFFFFFF LPMEN LPM support enable Device mode This bit is set by the software to enable the LPM support within the USB Device. If this bit is at 0 no LPM transactions are handled. 0 1 read-write LPMACK LPM token acknowledge enable Device mode: The NYET/ACK is returned only on a successful LPM transaction: No errors in both the EXT token and the LPM token (else ERROR) A valid bLinkState = 0001B (L1) is received (else STALL) 1 1 read-write LPMACK Nyet The valid LPM Token will be NYET / NYET answer 0 Ack The valid LPM Token will be ACK / ACK answer 1 REMWAKE bRemoteWake value Device mode This bit contains the bRemoteWake value received with last ACKed LPM Token 3 1 read-only BESL BESL value Device mode These bits contain the BESL value received with last ACKed LPM Token 4 4 read-only BCDR BCDR USB_BCDR 0x58 0x20 0x00000000 0xFFFFFFFF BCDEN Battery charging detector (BCD) enable Device mode This bit is set by the software to enable the BCD support within the USB Device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to 0 in order to allow the normal USB operation. 0 1 read-write DCDEN Data contact detection (DCD) mode enable Device mode This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. 1 1 read-write PDEN Primary detection (PD) mode enable Device mode This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. 2 1 read-write SDEN Secondary detection (SD) mode enable Device mode This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. 3 1 read-write DCDET Data contact detection (DCD) status Device mode This bit gives the result of DCD. 4 1 read-only PDET Primary detection (PD) status Device mode This bit gives the result of PD. 5 1 read-only SDET Secondary detection (SD) status Device mode This bit gives the result of SD. 6 1 read-only PS2DET DM pull-up detection status Device mode This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification. 7 1 read-only DPPU_DPD DP pull-up / DPDM pull-down Device mode This bit is set by software to enable the embedded pull-up on DP line. Clearing it to 0 can be used to signal disconnect to the host when needed by the user software. Host mode This bit is set by software to enable the embedded pull-down on DP and DM lines. 15 1 read-write WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR WWDG control register 0x0 0x10 0x0000007F 0x0000FFFF T 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[2:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). 0 7 read-write 0 127 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 7 1 read-write WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 CFR CFR WWDG configuration register 0x4 0x10 0x0000007F 0x0000FFFF W 7-bit window value These bits contain the window value to be compared with the down-counter. 0 7 read-write 0 127 EWI Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. 9 1 read-write EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base The timebase of the prescaler can be modified as follows: 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 Div16 Counter clock (PCLK1 div 4096) div 16 4 Div32 Counter clock (PCLK1 div 4096) div 32 5 Div64 Counter clock (PCLK1 div 4096) div 64 6 Div128 Counter clock (PCLK1 div 4096) div 128 7 SR SR WWDG status register 0x8 0x10 0x00000000 0x0000FFFF EWIF Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing '0'. Writing '1' has no effect. This bit is also set if the interrupt is not enabled. 0 1 read-write zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0

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