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Showing content from https://stm32-rs.github.io/stm32-rs/stm32g474.svd.patched below:

STM32G474 2.1 STM32G474 CM4 r0p1 little true true 4 false 8 32 0x20 0x00000000 0xFFFFFFFF CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 32 0 4294967295 CR CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 REV_IN Reverse input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 POLYSIZE Polynomial size 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 RESET RESET bit 0 1 write-only RESETW Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF INIT Programmable initial CRC value 0 32 0 4294967295 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 0 4294967295 IWDG WinWATCHDOG IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x10 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR Prescaler register 0x4 0x10 read-write 0x00000000 PR Prescaler divider 0 3 PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 true RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value 0 12 0 4095 SR SR Status register 0xC 0x10 read-only 0x00000000 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x10 read-write 0x00000FFF WIN Watchdog counter window value 0 12 0 4095 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers CR CR Control register 0x0 0x10 read-write 0x0000007F WDGA Activation bit 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 T 7-bit counter (MSB to LSB) 0 7 0 127 CFR CFR Configuration register 0x4 0x10 read-write 0x0000007F WDGTB Timer base 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 Div16 Counter clock (PCLK1 div 4096) div 16 4 Div32 Counter clock (PCLK1 div 4096) div 32 5 Div64 Counter clock (PCLK1 div 4096) div 64 6 Div128 Counter clock (PCLK1 div 4096) div 128 7 EWI Early wakeup interrupt 9 1 EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 W 7-bit window value 0 7 0 127 SR SR Status register 0x8 0x10 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1_EV 31 I2C1_ER I2C1_ER 32 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match interrupt enable (slave only) 3 1 ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received interrupt enable 4 1 NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE STOP detection Interrupt enable 5 1 STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable 6 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable 7 1 ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter 8 4 DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF 12 1 ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control 16 1 SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable 17 1 NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from STOP enable 18 1 WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus Host address enable 20 1 SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus Device Default address enable 21 1 SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBUS alert enable 22 1 ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable 23 1 PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 AUTOEND Automatic end mode (master mode) 25 1 AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 RELOAD NBYTES reload mode 24 1 RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 NBYTES Number of bytes 16 8 0 255 NACK NACK generation (slave mode) 15 1 oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 STOP Stop generation (master mode) 14 1 oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 START Start generation 13 1 oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 ADD10 10-bit addressing mode (master mode) 11 1 ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 RD_WRN Transfer direction (master mode) 10 1 RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 SADD Slave address bit (master mode) 0 10 0 1023 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 0 1023 OA1MODE Own Address 1 10-bit mode 10 1 OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 0 127 OA2MSK Own Address 2 masks 8 3 OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and donât care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and donât care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and donât care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and donât care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and donât care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and donât care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and donât care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 0 255 SCLH SCL high period (master mode) 8 8 0 255 SDADEL Data hold time 16 4 0 15 SCLDEL Data setup time 20 4 0 15 PRESC Timing prescaler 28 4 0 15 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 0 4095 TIDLE Idle clock timeout detection 12 1 TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B 16 12 0 4095 TEXTEN Extended clock timeout enable 31 1 TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only 0 127 DIR Transfer direction (Slave mode) 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 BUSY Bus busy 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 ALERT SMBus alert 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 TIMEOUT Timeout or t_low detection flag 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 PECERR PEC Error in reception 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 OVR Overrun/Underrun (slave mode) 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 ARLO Arbitration lost 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 BERR Bus error 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 TCR Transfer Complete Reload 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TC Transfer Complete (master mode) 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 STOPF Stop detection flag 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 NACKF Not acknowledge received flag 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 ADDR Address matched (slave mode) 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 RXNE Receive data register not empty (receivers) 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 TXIS Transmit interrupt status (transmitters) 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 TXE Transmit data register empty (transmitters) 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 TIMOUTCF Timeout detection flag clear 12 1 oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 PECCF PEC Error flag clear 11 1 oneToClear PECCF Clear Clears the PEC flag in ISR register 1 OVRCF Overrun/Underrun flag clear 10 1 oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 ARLOCF Arbitration lost flag clear 9 1 oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 BERRCF Bus error flag clear 8 1 oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 STOPCF Stop detection flag clear 5 1 oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 NACKCF Not Acknowledge flag clear 4 1 oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 ADDRCF Address Matched flag clear 3 1 oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 0 255 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 0 255 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 0 255 I2C2 0x40005800 WWDG Window Watchdog interrupt 0 I2C2_EV I2C2_EV 33 I2C2_ER I2C2_ER 34 I2C3 0x40007800 I2C3_EV I2C3_EV 92 I2C3_ER I2C3_ER 93 I2C4 0x40008400 I2C4_EV I2C4_EV 82 I2C4_ER I2C4_ER 83 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH FLASH 4 ACR ACR Access control register 0x0 0x20 read-write 0x00000600 LATENCY Latency 0 4 LATENCY Wait0 Zero Wait States (Vcore Boost 1 (<= 34MHz), Vcore Normal 1 (<= 30MHz), Vcore 2 (<= 12MHz) 0 Wait1 One Wait State (Vcore Boost 1 (<= 68MHz), Vcore Normal 1 (<= 60MHz), Vcore 2 (<= 24MHz) 1 Wait2 Two Wait States (Vcore Boost 1 (<= 102MHz), Vcore Normal 1 (<= 90MHz), Vcore 2 (<= 26MHz) 2 Wait3 Three Wait States (Vcore Boost 1 (<= 136MHz), Vcore Normal 1 (<= 120MHz) 3 Wait4 Four Wait States (Vcore Boost 1 (<= 170MHz), Vcore Normal 1 (<= 150MHz) 4 PRFTEN Prefetch enable 8 1 ICEN Instruction cache enable 9 1 DCEN Data cache enable 10 1 ICRST Instruction cache reset 11 1 DCRST Data cache reset 12 1 RUN_PD Flash Power-down mode during Low-power run mode 13 1 SLEEP_PD Flash Power-down mode during Low-power sleep mode 14 1 DBG_SWEN Debug software enable 18 1 PDKEYR PDKEYR Power down key register 0x4 0x20 write-only 0x00000000 PDKEYR RUN_PD in FLASH_ACR key 0 32 KEYR KEYR Flash key register 0x8 0x20 write-only 0x00000000 KEYR KEYR 0 32 OPTKEYR OPTKEYR Option byte key register 0xC 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 SR SR Status register 0x10 0x20 0x00000000 EOP End of operation 0 1 read-write OPERR Operation error 1 1 read-write PROGERR Programming error 3 1 read-write WRPERR Write protected error 4 1 read-write PGAERR Programming alignment error 5 1 read-write SIZERR Size error 6 1 read-write PGSERR Programming sequence error 7 1 read-write MISERR Fast programming data miss error 8 1 read-write FASTERR Fast programming error 9 1 read-write RDERR PCROP read error 14 1 read-write OPTVERR Option validity error 15 1 read-write BSY Busy 16 1 read-only CR CR Flash control register 0x14 0x20 read-write 0xC0000000 PG Programming 0 1 PER Page erase 1 1 MER1 Bank 1 Mass erase 2 1 PNB Page number 3 7 STRT Start 16 1 OPTSTRT Options modification start 17 1 FSTPG Fast programming 18 1 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 RDERRIE PCROP read error interrupt enable 26 1 OBL_LAUNCH Force the option byte loading 27 1 SEC_PROT1 SEC_PROT1 28 1 OPTLOCK Options Lock 30 1 LOCK FLASH_CR Lock 31 1 BKER Bank erase 11 1 BKER Bank1 Bank 1 is selected for page erase 0 Bank2 Bank 2 is selected for page erase 1 MER2 Bank 2 Mass erase 15 1 SEC_PROT2 Securable memory area protection bit for bank 2. 29 1 ECCR ECCR Flash ECC register 0x18 0x20 0x00000000 ADDR_ECC ECC fail address 0 19 read-only BK_ECC BK_ECC 21 1 read-only SYSF_ECC SYSF_ECC 22 1 read-only ECCIE ECCIE 24 1 read-write ECCC2 ECC correction 28 1 read-write ECCD2 ECC2 detection 29 1 read-write ECCC ECC correction 30 1 read-write ECCD ECC detection 31 1 read-write OPTR OPTR Flash option register 0x20 0x20 read-write 0xFFEFF8AA RDP Read protection level 0 8 BOR_LEV BOR reset Level 8 3 nRST_STOP nRST_STOP 12 1 nRST_STDBY nRST_STDBY 13 1 nRST_SHDW nRST_SHDW 14 1 IDWG_SW Independent watchdog selection 16 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 WWDG_SW Window watchdog selection 19 1 nBOOT1 Boot configuration 23 1 SRAM2_PE SRAM2 parity check enable 24 1 SRAM2_RST SRAM2 Erase when system reset 25 1 nSWBOOT0 nSWBOOT0 26 1 nBOOT0 nBOOT0 27 1 NRST_MODE NRST_MODE 28 2 IRHEN IRHEN 30 1 DBANK Single or dual bank mode 22 1 DBANK SingleBankMode Single-bank mode with 128 bits data read width 0 DualBankMode Dual-bank mode with 64 bits data 1 BFB2 Bank to boot from 20 1 BFB2 Disabled Boot from memory bank 1 0 Enabled Boot from memory bank 2 1 PCROP1SR PCROP1SR Flash Bank 1 PCROP Start address register 0x24 0x20 read-write 0xFFFF0000 PCROP1_STRT Bank 1 PCROP area start offset 0 15 PCROP1ER PCROP1ER Flash Bank 1 PCROP End address register 0x28 0x20 read-write 0x0FFF0000 PCROP1_END Bank 1 PCROP area end offset 0 15 PCROP_RDP PCROP area preserved when RDP level decreased 31 1 WRP1AR WRP1AR Flash Bank 1 WRP area A address register 0x2C 0x20 read-write 0x00000000 WRP1A_STRT Bank 1 WRP first area start offset 0 7 WRP1A_END Bank 1 WRP first area A end offset 16 7 WRP1BR WRP1BR Flash Bank 1 WRP area B address register 0x30 0x20 read-write 0x00000000 WRP1B_STRT Bank 1 WRP second area B end offset 0 7 WRP1B_END Bank 1 WRP second area B start offset 16 7 SEC1R SEC1R securable area bank1 register 0x70 0x20 read-write 0xFF00FF00 BOOT_LOCK BOOT_LOCK 16 1 SEC_SIZE1 SEC_SIZE1 0 8 DBGMCU Debug support DBGMCU 0xE0042000 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x00000000 DEV_ID Device Identifier 0 16 REV_ID Revision Identifier 16 16 CR CR Debug MCU Configuration Register 0x4 0x20 read-write 0x00000000 DBG_SLEEP Debug Sleep Mode 0 1 DBG_STOP Debug Stop Mode 1 1 DBG_STANDBY Debug Standby Mode 2 1 TRACE_IOEN Trace pin assignment control 5 1 TRACE_MODE Trace pin assignment control 6 2 APB1L_FZ APB1L_FZ APB Low Freeze Register 1 0x8 0x20 read-write 0x00000000 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_TIM3_STOP TIM3 counter stopped when core is halted 1 1 DBG_TIM4_STOP TIM4 counter stopped when core is halted 2 1 DBG_TIM5_STOP TIM5 counter stopped when core is halted 3 1 DBG_TIMER6_STOP Debug Timer 6 stopped when Core is halted 4 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_RTC_STOP Debug RTC stopped when Core is halted 10 1 DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted 11 1 DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted 12 1 DBG_I2C1_STOP I2C1 SMBUS timeout mode stopped when core is halted 21 1 DBG_I2C2_STOP I2C2 SMBUS timeout mode stopped when core is halted 22 1 DBG_I2C3_STOP I2C3 SMBUS timeout mode stopped when core is halted 30 1 DBG_LPTIMER_STOP LPTIM1 counter stopped when core is halted 31 1 APB1H_FZ APB1H_FZ APB Low Freeze Register 2 0xC 0x20 read-write 0x00000000 DBG_I2C4_STOP DBG_I2C4_STOP 1 1 APB2_FZ APB2_FZ APB High Freeze Register 0x10 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM8_STOP TIM8 counter stopped when core is halted 13 1 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM17_STOP TIM17 counter stopped when core is halted 18 1 DBG_TIM20_STOP TIM20counter stopped when core is halted 20 1 DBG_HRTIM0_STOP DBG_HRTIM0_STOP 26 1 DBG_HRTIM1_STOP DBG_HRTIM0_STOP 27 1 DBG_HRTIM2_STOP DBG_HRTIM0_STOP 28 1 DBG_HRTIM3_STOP DBG_HRTIM0_STOP 29 1 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 5 CR CR Clock control register 0x0 0x20 0x00000063 0xFFFFFFFF HSION HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. 8 1 read-write HSION Off Clock Off 0 On Clock On 1 HSIKERON HSI16 always enable for peripheral kernels. Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USARTs and I2Cs peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. 9 1 read-write HSIRDY HSI16 clock ready flag Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. 10 1 read-only HSIRDYR NotReady Clock not ready 0 Ready Clock ready 1 HSEON HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 16 1 read-write HSERDY HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. 17 1 read-only HSEBYP HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 18 1 read-write HSEBYP NotBypassed HSE crystal oscillator not bypassed 0 Bypassed HSE crystal oscillator bypassed with external clock 1 CSSON Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. 19 1 read-write CSSON Off Clock security system disabled (clock detector OFF) 0 On Clock security system enable (clock detector ON if the HSE is ready, OFF if not) 1 PLLON Main PLL enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. 24 1 read-write PLLRDY Main PLL clock ready flag Set by hardware to indicate that the main PLL is locked. 25 1 read-only ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x40000000 0xFFFFFFFF HSICAL HSI16 clock calibration These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. 16 8 read-only HSITRIM HSI16 clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16. The default value is 16, which, when added to the HSICAL value, should trim the HSI16 to 16 MHz 1 %. 24 7 read-write CFGR CFGR Clock configuration register 0x8 0x20 0x00000005 0xFFFFFFFF SW System clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by hardware to force HSI16 oscillator selection when exiting stop and standby modes or in case of failure of the HSE oscillator. 0 2 read-write SW MSI MSI selected as system clock 0 HSI HSI selected as system clock 1 HSE HSE selected as system clock 2 PLL PLL selected as system clock 3 SWS System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 2 2 read-only SWSR MSI MSI oscillator used as system clock 0 HSI HSI oscillator used as system clock 1 HSE HSE used as system clock 2 PLL PLL used as system clock 3 HPRE AHB prescaler Set and cleared by software to control the division factor of the AHB clock. Note: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to Section 6.1.5: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. 0xxx: SYSCLK not divided 4 4 read-write HPRE Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 Div1 SYSCLK not divided true PPRE1 APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided 8 3 read-write PPRE1 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true PPRE2 APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided 11 3 read-write MCOSEL Microcontroller clock output Set and cleared by software. Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. 24 4 read-write MCOSEL None MCO output disabled, no clock on MCO 0 SYSCLK SYSCLK system clock selected 1 MSI MSI clock selected 2 HSI HSI clock selected 3 HSE HSE clock selected 4 PLL Main PLL clock selected 5 LSI LSI clock selected 6 LSE LSE clock selected 7 HSI48 Internal HSI48 clock selected 8 MCOPRE Microcontroller clock output prescaler These bits are set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed 28 3 read-write MCOPRE Div1 MCO divided by 1 0 Div2 MCO divided by 2 1 Div4 MCO divided by 4 2 Div8 MCO divided by 8 3 Div16 MCO divided by 16 4 PLLCFGR PLLCFGR PLL configuration register 0xC 0x20 0x00001000 0xFFFFFFFF PLLSRC Main PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC should be 00. 0 2 read-write PLLSRC None No clock sent to PLL 0 HSI16 HSI16 sent to PLL input 2 HSE HSE sent to PLL input 3 PLLM Division factor for the main PLL input clock Set and cleared by software to divide the PLL input clock before the VCO. These bits can be written only when all PLLs are disabled. VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 16 ... Note: The software has to set these bits correctly to ensure that the VCO input frequency is within the range defined in the device datasheet. 4 4 read-write PLLM Div1 pll_p_ck = vco_ck / 1 0 Div2 pll_p_ck = vco_ck / 2 1 Div3 pll_p_ck = vco_ck / 3 2 Div4 pll_p_ck = vco_ck / 4 3 Div5 pll_p_ck = vco_ck / 5 4 Div6 pll_p_ck = vco_ck / 6 5 Div7 pll_p_ck = vco_ck / 7 6 Div8 pll_p_ck = vco_ck / 8 7 Div9 pll_p_ck = vco_ck / 9 8 Div10 pll_p_ck = vco_ck / 10 9 Div11 pll_p_ck = vco_ck / 11 10 Div12 pll_p_ck = vco_ck / 12 11 Div13 pll_p_ck = vco_ck / 13 12 Div14 pll_p_ck = vco_ck / 14 13 Div15 pll_p_ck = vco_ck / 15 14 Div16 pll_p_ck = vco_ck / 16 15 PLLN Main PLL multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled. VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 127 ... ... Note: The software has to set correctly these bits to assure that the VCO output frequency is within the range defined in the device datasheet. 8 7 read-write PLLN Div8 pll_n_ck = vco_ck / 8 8 Div9 pll_n_ck = vco_ck / 9 9 Div10 pll_n_ck = vco_ck / 10 10 Div11 pll_n_ck = vco_ck / 11 11 Div12 pll_n_ck = vco_ck / 12 12 Div13 pll_n_ck = vco_ck / 13 13 Div14 pll_n_ck = vco_ck / 14 14 Div15 pll_n_ck = vco_ck / 15 15 Div16 pll_n_ck = vco_ck / 16 16 Div17 pll_n_ck = vco_ck / 17 17 Div18 pll_n_ck = vco_ck / 18 18 Div19 pll_n_ck = vco_ck / 19 19 Div20 pll_n_ck = vco_ck / 20 20 Div21 pll_n_ck = vco_ck / 21 21 Div22 pll_n_ck = vco_ck / 22 22 Div23 pll_n_ck = vco_ck / 23 23 Div24 pll_n_ck = vco_ck / 24 24 Div25 pll_n_ck = vco_ck / 25 25 Div26 pll_n_ck = vco_ck / 26 26 Div27 pll_n_ck = vco_ck / 27 27 Div28 pll_n_ck = vco_ck / 28 28 Div29 pll_n_ck = vco_ck / 29 29 Div30 pll_n_ck = vco_ck / 30 30 Div31 pll_n_ck = vco_ck / 31 31 Div32 pll_n_ck = vco_ck / 32 32 Div33 pll_n_ck = vco_ck / 33 33 Div34 pll_n_ck = vco_ck / 34 34 Div35 pll_n_ck = vco_ck / 35 35 Div36 pll_n_ck = vco_ck / 36 36 Div37 pll_n_ck = vco_ck / 37 37 Div38 pll_n_ck = vco_ck / 38 38 Div39 pll_n_ck = vco_ck / 39 39 Div40 pll_n_ck = vco_ck / 40 40 Div41 pll_n_ck = vco_ck / 41 41 Div42 pll_n_ck = vco_ck / 42 42 Div43 pll_n_ck = vco_ck / 43 43 Div44 pll_n_ck = vco_ck / 44 44 Div45 pll_n_ck = vco_ck / 45 45 Div46 pll_n_ck = vco_ck / 46 46 Div47 pll_n_ck = vco_ck / 47 47 Div48 pll_n_ck = vco_ck / 48 48 Div49 pll_n_ck = vco_ck / 49 49 Div50 pll_n_ck = vco_ck / 50 50 Div51 pll_n_ck = vco_ck / 51 51 Div52 pll_n_ck = vco_ck / 52 52 Div53 pll_n_ck = vco_ck / 53 53 Div54 pll_n_ck = vco_ck / 54 54 Div55 pll_n_ck = vco_ck / 55 55 Div56 pll_n_ck = vco_ck / 56 56 Div57 pll_n_ck = vco_ck / 57 57 Div58 pll_n_ck = vco_ck / 58 58 Div59 pll_n_ck = vco_ck / 59 59 Div60 pll_n_ck = vco_ck / 60 60 Div61 pll_n_ck = vco_ck / 61 61 Div62 pll_n_ck = vco_ck / 62 62 Div63 pll_n_ck = vco_ck / 63 63 Div64 pll_n_ck = vco_ck / 64 64 Div65 pll_n_ck = vco_ck / 65 65 Div66 pll_n_ck = vco_ck / 66 66 Div67 pll_n_ck = vco_ck / 67 67 Div68 pll_n_ck = vco_ck / 68 68 Div69 pll_n_ck = vco_ck / 69 69 Div70 pll_n_ck = vco_ck / 70 70 Div71 pll_n_ck = vco_ck / 71 71 Div72 pll_n_ck = vco_ck / 72 72 Div73 pll_n_ck = vco_ck / 73 73 Div74 pll_n_ck = vco_ck / 74 74 Div75 pll_n_ck = vco_ck / 75 75 Div76 pll_n_ck = vco_ck / 76 76 Div77 pll_n_ck = vco_ck / 77 77 Div78 pll_n_ck = vco_ck / 78 78 Div79 pll_n_ck = vco_ck / 79 79 Div80 pll_n_ck = vco_ck / 80 80 Div81 pll_n_ck = vco_ck / 81 81 Div82 pll_n_ck = vco_ck / 82 82 Div83 pll_n_ck = vco_ck / 83 83 Div84 pll_n_ck = vco_ck / 84 84 Div85 pll_n_ck = vco_ck / 85 85 Div86 pll_n_ck = vco_ck / 86 86 Div87 pll_n_ck = vco_ck / 87 87 Div88 pll_n_ck = vco_ck / 88 88 Div89 pll_n_ck = vco_ck / 89 89 Div90 pll_n_ck = vco_ck / 90 90 Div91 pll_n_ck = vco_ck / 91 91 Div92 pll_n_ck = vco_ck / 92 92 Div93 pll_n_ck = vco_ck / 93 93 Div94 pll_n_ck = vco_ck / 94 94 Div95 pll_n_ck = vco_ck / 95 95 Div96 pll_n_ck = vco_ck / 96 96 Div97 pll_n_ck = vco_ck / 97 97 Div98 pll_n_ck = vco_ck / 98 98 Div99 pll_n_ck = vco_ck / 99 99 Div100 pll_n_ck = vco_ck / 100 100 Div101 pll_n_ck = vco_ck / 101 101 Div102 pll_n_ck = vco_ck / 102 102 Div103 pll_n_ck = vco_ck / 103 103 Div104 pll_n_ck = vco_ck / 104 104 Div105 pll_n_ck = vco_ck / 105 105 Div106 pll_n_ck = vco_ck / 106 106 Div107 pll_n_ck = vco_ck / 107 107 Div108 pll_n_ck = vco_ck / 108 108 Div109 pll_n_ck = vco_ck / 109 109 Div110 pll_n_ck = vco_ck / 110 110 Div111 pll_n_ck = vco_ck / 111 111 Div112 pll_n_ck = vco_ck / 112 112 Div113 pll_n_ck = vco_ck / 113 113 Div114 pll_n_ck = vco_ck / 114 114 Div115 pll_n_ck = vco_ck / 115 115 Div116 pll_n_ck = vco_ck / 116 116 Div117 pll_n_ck = vco_ck / 117 117 Div118 pll_n_ck = vco_ck / 118 118 Div119 pll_n_ck = vco_ck / 119 119 Div120 pll_n_ck = vco_ck / 120 120 Div121 pll_n_ck = vco_ck / 121 121 Div122 pll_n_ck = vco_ck / 122 122 Div123 pll_n_ck = vco_ck / 123 123 Div124 pll_n_ck = vco_ck / 124 124 Div125 pll_n_ck = vco_ck / 125 125 Div126 pll_n_ck = vco_ck / 126 126 Div127 pll_n_ck = vco_ck / 127 127 PLLPEN Main PLL PLL P clock output enable Set and reset by software to enable the PLL P clock output of the PLL. In order to save power, when the PLL P clock output of the PLL is not used, the value of PLLPEN should be 0. 16 1 read-write PLLP Main PLL division factor for PLL P clock. Set and cleared by software to control the frequency of the main PLL output clock PLL P clock. These bits can be written only if PLL is disabled. When the PLLPDIV[4:0] is set to 00000PLL P output clock frequency = VCO frequency / PLLP with PLLP =7, or 17 Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. 17 1 read-write PLLP Div7 pll_p_ck = vco_ck / 7 0 Div17 pll_p_ck = vco_ck / 17 1 PLLQEN Main PLL Q clock output enable Set and reset by software to enable the PLL Q clock output of the PLL. In order to save power, when the PLL Q clock output of the PLL is not used, the value of PLLQEN should be 0. 20 1 read-write PLLQ Main PLL division factor for PLL Q clock. Set and cleared by software to control the frequency of the main PLL output clock PLL Q clock. This output can be selected for USB, RNG, SAI (48 MHz clock). These bits can be written only if PLL is disabled. PLL Q output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8 Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. 21 2 read-write PLLQ Div2 pll_q_ck = vco_ck / 2 0 Div4 pll_q_ck = vco_ck / 4 1 Div6 pll_q_ck = vco_ck / 6 2 Div8 pll_q_ck = vco_ck / 8 3 PLLREN PLL R clock output enable Set and reset by software to enable the PLL R clock output of the PLL (used as system clock). This bit cannot be written when PLL R clock output of the PLL is used as System Clock. In order to save power, when the PLL R clock output of the PLL is not used, the value of PLLREN should be 0. 24 1 read-write PLLR Main PLL division factor for PLL R clock (system clock) Set and cleared by software to control the frequency of the main PLL output clock PLLCLK. This output can be selected as system clock. These bits can be written only if PLL is disabled. PLL R output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8 Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. 25 2 read-write PLLR Div2 pll_r_ck = vco_ck / 2 0 Div4 pll_r_ck = vco_ck / 4 1 Div6 pll_r_ck = vco_ck / 6 2 Div8 pll_r_ck = vco_ck / 8 3 PLLPDIV Main PLLP division factor Set and cleared by software to control the PLL P frequency. PLL P output clock frequency = VCO frequency / PLLPDIV. .... 27 5 read-write PLLPDIV PLLP pll_p_ck is controlled by PLLP 0 Div2 pll_p_ck = vco_ck / 2 2 Div3 pll_p_ck = vco_ck / 3 3 Div4 pll_p_ck = vco_ck / 4 4 Div5 pll_p_ck = vco_ck / 5 5 Div6 pll_p_ck = vco_ck / 6 6 Div7 pll_p_ck = vco_ck / 7 7 Div8 pll_p_ck = vco_ck / 8 8 Div9 pll_p_ck = vco_ck / 9 9 Div10 pll_p_ck = vco_ck / 10 10 Div11 pll_p_ck = vco_ck / 11 11 Div12 pll_p_ck = vco_ck / 12 12 Div13 pll_p_ck = vco_ck / 13 13 Div14 pll_p_ck = vco_ck / 14 14 Div15 pll_p_ck = vco_ck / 15 15 Div16 pll_p_ck = vco_ck / 16 16 Div17 pll_p_ck = vco_ck / 17 17 Div18 pll_p_ck = vco_ck / 18 18 Div19 pll_p_ck = vco_ck / 19 19 Div20 pll_p_ck = vco_ck / 20 20 Div21 pll_p_ck = vco_ck / 21 21 Div22 pll_p_ck = vco_ck / 22 22 Div23 pll_p_ck = vco_ck / 23 23 Div24 pll_p_ck = vco_ck / 24 24 Div25 pll_p_ck = vco_ck / 25 25 Div26 pll_p_ck = vco_ck / 26 26 Div27 pll_p_ck = vco_ck / 27 27 Div28 pll_p_ck = vco_ck / 28 28 Div29 pll_p_ck = vco_ck / 29 29 Div30 pll_p_ck = vco_ck / 30 30 Div31 pll_p_ck = vco_ck / 31 31 CIER CIER Clock interrupt enable register 0x18 0x20 0x00000000 0xFFFFFFFF LSIRDYIE LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0 1 read-write LSERDYIE LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. 1 1 read-write HSIRDYIE HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. 3 1 read-write HSERDYIE HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. 4 1 read-write PLLRDYIE PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 5 1 read-write LSECSSIE LSE clock security system interrupt enable Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. 9 1 read-write HSI48RDYIE HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. 10 1 read-write CIFR CIFR Clock interrupt flag register 0x1C 0x20 0x00000000 0xFFFFFFFF LSIRDYF LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0 1 read-only LSERDYF LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 1 1 read-only HSIRDYF HSI16 ready interrupt flag Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. 3 1 read-only HSERDYF HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 4 1 read-only PLLRDYF PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 5 1 read-only CSSF Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. 8 1 read-only LSECSSF LSE Clock security system interrupt flag Set by hardware when a failure is detected in the LSE oscillator. Cleared by software setting the LSECSSC bit. 9 1 read-only HSI48RDYF HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to Clock recovery RC register (RCC_CRRCR)). Cleared by software setting the HSI48RDYC bit. 10 1 read-only CICR CICR Clock interrupt clear register 0x20 0x20 0x00000000 0xFFFFFFFF LSIRDYC LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0 1 write-only LSERDYC LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 1 1 write-only HSIRDYC HSI16 ready interrupt clear This bit is set software to clear the HSIRDYF flag. 3 1 write-only HSERDYC HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 4 1 write-only PLLRDYC PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 5 1 write-only CSSC Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 8 1 write-only LSECSSC LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. 9 1 write-only HSI48RDYC HSI48 oscillator ready interrupt clear This bit is set by software to clear the HSI48RDYF flag. 10 1 write-only AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x28 0x20 0x00000000 0xFFFFFFFF DMA1RST DMA1 reset Set and cleared by software. 0 1 read-write DMA1RST Reset Reset the selected module 1 DMA2RST DMA2 reset Set and cleared by software. 1 1 read-write DMAMUX1RST Set and cleared by software. 2 1 read-write CORDICRST Set and cleared by software 3 1 read-write FMACRST Set and cleared by software 4 1 read-write FLASHRST Flash memory interface reset Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. 8 1 read-write CRCRST CRC reset Set and cleared by software. 12 1 read-write AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x2C 0x20 0x00000000 0xFFFFFFFF GPIOARST IO port A reset Set and cleared by software. 0 1 read-write GPIOARST Reset Reset the selected module 1 GPIOBRST IO port B reset Set and cleared by software. 1 1 read-write GPIOCRST IO port C reset Set and cleared by software. 2 1 read-write GPIODRST IO port D reset Set and cleared by software. 3 1 read-write GPIOERST IO port E reset Set and cleared by software. 4 1 read-write GPIOFRST IO port F reset Set and cleared by software. 5 1 read-write GPIOGRST IO port G reset Set and cleared by software. 6 1 read-write ADC12RST ADC12 reset Set and cleared by software. 13 1 read-write ADC345RST ADC345 reset Set and cleared by software. 14 1 read-write DAC1RST DAC1 reset Set and cleared by software. 16 1 read-write DAC2RST DAC2 reset Set and cleared by software. 17 1 read-write DAC3RST DAC3 reset Set and cleared by software. 18 1 read-write DAC4RST DAC4 reset Set and cleared by software. 19 1 read-write AESRST AESRST reset Set and cleared by software. 24 1 read-write RNGRST RNG reset Set and cleared by software. 26 1 read-write AHB3RSTR AHB3RSTR AHB3 peripheral reset register 0x30 0x20 0x00000000 0xFFFFFFFF FMCRST Flexible static memory controller reset Set and cleared by software. 0 1 read-write FMCRST Reset Reset the selected module 1 QSPIRST QUADSPI reset Set and cleared by software. 8 1 read-write APB1RSTR1 APB1RSTR1 APB1 peripheral reset register 1 0x38 0x20 0x00000000 0xFFFFFFFF TIM2RST TIM2 timer reset Set and cleared by software. 0 1 read-write TIM2RST Reset Reset the selected module 1 TIM3RST TIM3 timer reset Set and cleared by software. 1 1 read-write TIM4RST TIM3 timer reset Set and cleared by software. 2 1 read-write TIM5RST TIM5 timer reset Set and cleared by software. 3 1 read-write TIM6RST TIM6 timer reset Set and cleared by software. 4 1 read-write TIM7RST TIM7 timer reset Set and cleared by software. 5 1 read-write CRSRST CRS reset Set and cleared by software. 8 1 read-write SPI2RST SPI2 reset Set and cleared by software. 14 1 read-write SPI3RST SPI3 reset Set and cleared by software. 15 1 read-write USART2RST USART2 reset Set and cleared by software. 17 1 read-write USART3RST USART3 reset Set and cleared by software. 18 1 read-write UART4RST UART4 reset Set and cleared by software. 19 1 read-write UART5RST UART5 reset Set and cleared by software. 20 1 read-write I2C1RST I2C1 reset Set and cleared by software. 21 1 read-write I2C2RST I2C2 reset Set and cleared by software. 22 1 read-write USBRST USB device reset Set and reset by software. 23 1 read-write FDCANRST FDCAN reset Set and reset by software. 25 1 read-write PWRRST Power interface reset Set and cleared by software. 28 1 read-write I2C3RST I2C3 reset Set and cleared by software. 30 1 read-write LPTIM1RST Low Power Timer 1 reset Set and cleared by software. 31 1 read-write APB1RSTR2 APB1RSTR2 APB1 peripheral reset register 2 0x3C 0x20 0x00000000 0xFFFFFFFF LPUART1RST Low-power UART 1 reset Set and cleared by software. 0 1 read-write LPUART1RST Reset Reset the selected module 1 I2C4RST I2C4 reset Set and cleared by software 1 1 read-write UCPD1RST UCPD1 reset Set and cleared by software. 8 1 read-write APB2RSTR APB2RSTR APB2 peripheral reset register 0x40 0x20 0x00000000 0xFFFFFFFF SYSCFGRST SYSCFG + COMP + OPAMP + VREFBUF reset 0 1 read-write SYSCFGRST Reset Reset the selected module 1 TIM1RST TIM1 timer reset Set and cleared by software. 11 1 read-write SPI1RST SPI1 reset Set and cleared by software. 12 1 read-write TIM8RST TIM8 timer reset Set and cleared by software. 13 1 read-write USART1RST USART1 reset Set and cleared by software. 14 1 read-write SPI4RST SPI4 reset Set and cleared by software. 15 1 read-write TIM15RST TIM15 timer reset Set and cleared by software. 16 1 read-write TIM16RST TIM16 timer reset Set and cleared by software. 17 1 read-write TIM17RST TIM17 timer reset Set and cleared by software. 18 1 read-write TIM20RST TIM20 reset Set and cleared by software. 20 1 read-write SAI1RST Serial audio interface 1 (SAI1) reset Set and cleared by software. 21 1 read-write HRTIM1RST HRTIM1 reset Set and cleared by software. 26 1 read-write AHB1ENR AHB1ENR AHB1 peripheral clock enable register 0x48 0x20 0x00000100 0xFFFFFFFF DMA1EN DMA1 clock enable Set and cleared by software. 0 1 read-write DMA1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 DMA2EN DMA2 clock enable Set and cleared by software. 1 1 read-write DMAMUX1EN DMAMUX1 clock enable Set and reset by software. 2 1 read-write CORDICEN CORDIC clock enable Set and reset by software. 3 1 read-write FMACEN FMAC enable Set and reset by software. 4 1 read-write FLASHEN Flash memory interface clock enable Set and cleared by software. This bit can be disabled only when the Flash is in power down mode. 8 1 read-write CRCEN CRC clock enable Set and cleared by software. 12 1 read-write AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x4C 0x20 0x00000000 0xFFFFFFFF GPIOAEN IO port A clock enable Set and cleared by software. 0 1 read-write GPIOAEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 GPIOBEN IO port B clock enable Set and cleared by software. 1 1 read-write GPIOCEN IO port C clock enable Set and cleared by software. 2 1 read-write GPIODEN IO port D clock enable Set and cleared by software. 3 1 read-write GPIOEEN IO port E clock enable Set and cleared by software. 4 1 read-write GPIOFEN IO port F clock enable Set and cleared by software. 5 1 read-write GPIOGEN IO port G clock enable Set and cleared by software. 6 1 read-write ADC12EN ADC12 clock enable Set and cleared by software. 13 1 read-write ADC345EN ADC345 clock enable Set and cleared by software 14 1 read-write DAC1EN DAC1 clock enable Set and cleared by software. 16 1 read-write DAC2EN DAC2 clock enable Set and cleared by software. 17 1 read-write DAC3EN DAC3 clock enable Set and cleared by software. 18 1 read-write DAC4EN DAC4 clock enable Set and cleared by software. 19 1 read-write AESEN AES clock enable Set and cleared by software. 24 1 read-write RNGEN RNG enable Set and cleared by software. 26 1 read-write AHB3ENR AHB3ENR AHB3 peripheral clock enable register 0x50 0x20 0x00000000 0xFFFFFFFF FMCEN Flexible static memory controller clock enable Set and cleared by software. 0 1 read-write FMCEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 QSPIEN QUADSPI memory interface clock enable Set and cleared by software. 8 1 read-write APB1ENR1 APB1ENR1 APB1 peripheral clock enable register 1 0x58 0x20 0x00000400 0xFFFFFFFF TIM2EN TIM2 timer clock enable Set and cleared by software. 0 1 read-write TIM2EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM3EN TIM3 timer clock enable Set and cleared by software. 1 1 read-write TIM4EN TIM4 timer clock enable Set and cleared by software. 2 1 read-write TIM5EN TIM5 timer clock enable Set and cleared by software. 3 1 read-write TIM6EN TIM6 timer clock enable Set and cleared by software. 4 1 read-write TIM7EN TIM7 timer clock enable Set and cleared by software. 5 1 read-write CRSEN CRS Recovery System clock enable Set and cleared by software. 8 1 read-write RTCAPBEN RTC APB clock enable Set and cleared by software 10 1 read-write WWDGEN Window watchdog clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. 11 1 read-write SPI2EN SPI2 clock enable Set and cleared by software. 14 1 read-write SPI3EN SPI3 clock enable Set and cleared by software. 15 1 read-write USART2EN USART2 clock enable Set and cleared by software. 17 1 read-write USART3EN USART3 clock enable Set and cleared by software. 18 1 read-write UART4EN UART4 clock enable Set and cleared by software. 19 1 read-write UART5EN UART5 clock enable Set and cleared by software. 20 1 read-write I2C1EN I2C1 clock enable Set and cleared by software. 21 1 read-write I2C2EN I2C2 clock enable Set and cleared by software. 22 1 read-write USBEN USB device clock enable Set and cleared by software. 23 1 read-write FDCANEN FDCAN clock enable Set and cleared by software. 25 1 read-write PWREN Power interface clock enable Set and cleared by software. 28 1 read-write I2C3EN I2C3 clock enable Set and cleared by software. 30 1 read-write LPTIM1EN Low power timer 1 clock enable Set and cleared by software. 31 1 read-write APB1ENR2 APB1ENR2 APB1 peripheral clock enable register 2 0x5C 0x20 0x00000000 0xFFFFFFFF LPUART1EN Low power UART 1 clock enable Set and cleared by software. 0 1 read-write LPUART1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 I2C4EN I2C4 clock enable Set and cleared by software 1 1 read-write UCPD1EN UCPD1 clock enable Set and cleared by software. 8 1 read-write APB2ENR APB2ENR APB2 peripheral clock enable register 0x60 0x20 0x00000000 0xFFFFFFFF SYSCFGEN SYSCFG + COMP + VREFBUF + OPAMP clock enable Set and cleared by software. 0 1 read-write SYSCFGEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM1EN TIM1 timer clock enable Set and cleared by software. 11 1 read-write SPI1EN SPI1 clock enable Set and cleared by software. 12 1 read-write TIM8EN TIM8 timer clock enable Set and cleared by software. 13 1 read-write USART1EN USART1clock enable Set and cleared by software. 14 1 read-write SPI4EN SPI4 clock enable Set and cleared by software. 15 1 read-write TIM15EN TIM15 timer clock enable Set and cleared by software. 16 1 read-write TIM16EN TIM16 timer clock enable Set and cleared by software. 17 1 read-write TIM17EN TIM17 timer clock enable Set and cleared by software. 18 1 read-write TIM20EN TIM20 timer clock enable Set and cleared by software. 20 1 read-write SAI1EN SAI1 clock enable Set and cleared by software. 21 1 read-write HRTIM1EN HRTIM1 clock enable Set and cleared by software. 26 1 read-write AHB1SMENR AHB1SMENR AHB1 peripheral clocks enable in Sleep and Stop modes register 0x68 0x20 0x0000130F 0xFFFFFFFF DMA1SMEN DMA1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write DMA2SMEN DMA2 clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode. 1 1 read-write DMAMUX1SMEN DMAMUX1 clock enable during Sleep and Stop modes. Set and cleared by software. 2 1 read-write CORDICSMEN CORDICSM clock enable. Set and cleared by software. 3 1 read-write FMACSMEN FMACSM clock enable. Set and cleared by software. 4 1 read-write FLASHSMEN Flash memory interface clocks enable during Sleep and Stop modes Set and cleared by software. 8 1 read-write SRAM1SMEN SRAM1 interface clocks enable during Sleep and Stop modes Set and cleared by software. 9 1 read-write CRCSMEN CRC clocks enable during Sleep and Stop modes Set and cleared by software. 12 1 read-write AHB2SMENR AHB2SMENR AHB2 peripheral clocks enable in Sleep and Stop modes register 0x6C 0x20 0x050F667F 0xFFFFFFFF GPIOASMEN IO port A clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write GPIOBSMEN IO port B clocks enable during Sleep and Stop modes Set and cleared by software. 1 1 read-write GPIOCSMEN IO port C clocks enable during Sleep and Stop modes Set and cleared by software. 2 1 read-write GPIODSMEN IO port D clocks enable during Sleep and Stop modes Set and cleared by software. 3 1 read-write GPIOESMEN IO port E clocks enable during Sleep and Stop modes Set and cleared by software. 4 1 read-write GPIOFSMEN IO port F clocks enable during Sleep and Stop modes Set and cleared by software. 5 1 read-write GPIOGSMEN IO port G clocks enable during Sleep and Stop modes Set and cleared by software. 6 1 read-write CCMSRAMSMEN CCM SRAM interface clocks enable during Sleep and Stop modes Set and cleared by software. 9 1 read-write SRAM2SMEN SRAM2 interface clocks enable during Sleep and Stop modes Set and cleared by software. 10 1 read-write ADC12SMEN ADC12 clocks enable during Sleep and Stop modes Set and cleared by software. 13 1 read-write ADC345SMEN ADC345 clock enable Set and cleared by software. 14 1 read-write DAC1SMEN DAC1 clock enable Set and cleared by software. 16 1 read-write DAC2SMEN DAC2 clock enable Set and cleared by software. 17 1 read-write DAC3SMEN DAC3 clock enable Set and cleared by software. 18 1 read-write DAC4SMEN DAC4 clock enable Set and cleared by software. 19 1 read-write AESSMEN AESM clocks enable Set and cleared by software. 24 1 read-write RNGEN RNG enable Set and cleared by software. 26 1 read-write AHB3SMENR AHB3SMENR AHB3 peripheral clocks enable in Sleep and Stop modes register 0x70 0x20 0x00000101 0xFFFFFFFF FMCSMEN Flexible static memory controller clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write QSPISMEN QUADSPI memory interface clock enable during Sleep and Stop modes Set and cleared by software. 8 1 read-write APB1SMENR1 APB1SMENR1 APB1 peripheral clocks enable in Sleep and Stop modes register 1 0x78 0x20 0xD2FECD3F 0xFFFFFFFF TIM2SMEN TIM2 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write TIM3SMEN TIM3 timer clocks enable during Sleep and Stop modes Set and cleared by software. 1 1 read-write TIM4SMEN TIM4 timer clocks enable during Sleep and Stop modes Set and cleared by software. 2 1 read-write TIM5SMEN TIM5 timer clocks enable during Sleep and Stop modes Set and cleared by software. 3 1 read-write TIM6SMEN TIM6 timer clocks enable during Sleep and Stop modes Set and cleared by software. 4 1 read-write TIM7SMEN TIM7 timer clocks enable during Sleep and Stop modes Set and cleared by software. 5 1 read-write CRSSMEN CRS timer clocks enable during Sleep and Stop modes Set and cleared by software. 8 1 read-write RTCAPBSMEN RTC APB clock enable during Sleep and Stop modes Set and cleared by software 10 1 read-write WWDGSMEN Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated. 11 1 read-write SPI2SMEN SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. 14 1 read-write SPI3SMEN SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. 15 1 read-write USART2SMEN USART2 clocks enable during Sleep and Stop modes Set and cleared by software. 17 1 read-write USART3SMEN USART3 clocks enable during Sleep and Stop modes Set and cleared by software. 18 1 read-write UART4SMEN UART4 clocks enable during Sleep and Stop modes Set and cleared by software. 19 1 read-write UART5SMEN UART5 clocks enable during Sleep and Stop modes Set and cleared by software. 20 1 read-write I2C1SMEN I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. 21 1 read-write I2C2SMEN I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. 22 1 read-write USBSMEN USB device clocks enable during Sleep and Stop modes Set and cleared by software. 23 1 read-write FDCANSMEN FDCAN clocks enable during Sleep and Stop modes Set and cleared by software. 25 1 read-write PWRSMEN Power interface clocks enable during Sleep and Stop modes Set and cleared by software. 28 1 read-write I2C3SMEN I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. 30 1 read-write LPTIM1SMEN Low power timer 1 clocks enable during Sleep and Stop modes Set and cleared by software. 31 1 read-write APB1SMENR2 APB1SMENR2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x7C 0x20 0x00000103 0xFFFFFFFF LPUART1SMEN Low power UART 1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write I2C4SMEN I2C4 clocks enable during Sleep and Stop modes Set and cleared by software 1 1 read-write UCPD1SMEN UCPD1 clocks enable during Sleep and Stop modes Set and cleared by software. 8 1 read-write APB2SMENR APB2SMENR APB2 peripheral clocks enable in Sleep and Stop modes register 0x80 0x20 0x0437F801 0xFFFFFFFF SYSCFGSMEN SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write TIM1SMEN TIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software. 11 1 read-write SPI1SMEN SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. 12 1 read-write TIM8SMEN TIM8 timer clocks enable during Sleep and Stop modes Set and cleared by software. 13 1 read-write USART1SMEN USART1clocks enable during Sleep and Stop modes Set and cleared by software. 14 1 read-write SPI4SMEN SPI4 timer clocks enable during Sleep and Stop modes Set and cleared by software. 15 1 read-write TIM15SMEN TIM15 timer clocks enable during Sleep and Stop modes Set and cleared by software. 16 1 read-write TIM16SMEN TIM16 timer clocks enable during Sleep and Stop modes Set and cleared by software. 17 1 read-write TIM17SMEN TIM17 timer clocks enable during Sleep and Stop modes Set and cleared by software. 18 1 read-write TIM20SMEN TIM20 timer clocks enable during Sleep and Stop modes Set and cleared by software. 20 1 read-write SAI1SMEN SAI1 clocks enable during Sleep and Stop modes Set and cleared by software. 21 1 read-write HRTIM1SMEN HRTIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software. 26 1 read-write CCIPR CCIPR Peripherals independent clock configuration register 0x88 0x20 0x00000000 0xFFFFFFFF USART1SEL USART1 clock source selection This bit is set and cleared by software to select the USART1 clock source. 0 2 read-write USART2SEL USART2 clock source selection This bit is set and cleared by software to select the USART2 clock source. 2 2 read-write USART3SEL USART3 clock source selection This bit is set and cleared by software to select the USART3 clock source. 4 2 read-write UART4SEL UART4 clock source selection This bit is set and cleared by software to select the UART4 clock source. 6 2 read-write UART4SEL PCLK PCLK clock selected as UART clock 0 System System clock (SYSCLK) selected as UART clock 1 HSI16 HSI16 clock selected as UART clock 2 LSE LSE clock selected as UART clock 3 UART5SEL UART5 clock source selection These bits are set and cleared by software to select the UART5 clock source. 8 2 read-write LPUART1SEL LPUART1 clock source selection These bits are set and cleared by software to select the LPUART1 clock source. 10 2 read-write I2C1SEL I2C1 clock source selection These bits are set and cleared by software to select the I2C1 clock source. 12 2 read-write I2C1SEL PCLK PCLK clock selected as I2C clock 0 System System clock (SYSCLK) selected as I2C clock 1 HSI16 HSI16 clock selected as I2C clock 2 I2C2SEL I2C2 clock source selection These bits are set and cleared by software to select the I2C2 clock source. 14 2 read-write I2C3SEL I2C3 clock source selection These bits are set and cleared by software to select the I2C3 clock source. 16 2 read-write LPTIM1SEL Low power timer 1 clock source selection These bits are set and cleared by software to select the LPTIM1 clock source. 18 2 read-write LPTIM1SEL PCLK PCLK clock selected as LPTIM1 clock 0 LSI LSI clock selected as LPTIM1 clock 1 HSI16 HSI16 clock selected as LPTIM1 clock 2 LSE LSE clock selected as LPTIM1 clock 3 SAI1SEL clock source selection These bits are set and cleared by software to select the SAI clock source. 20 2 read-write SAI1SEL System System clock selected as SAI clock 0 PLLQ PLL 'Q' clock selected as SAI clock 1 I2S_CKIN Clock provided on I2S_CKIN pin is selected as SAI clock 2 HSI16 HSI16 clock selected as SAI clock 3 I2S23SEL clock source selection These bits are set and cleared by software to select the I2S23 clock source. 22 2 read-write I2S23SEL System System clock selected as I2S23 clock 0 PLLQ PLL 'Q' clock selected as I2S23 clock 1 I2S_CKIN Clock provided on I2S_CKIN pin is selected as I2S23 clock 2 HSI16 HSI16 clock selected as I2S23 clock 3 FDCANSEL None 24 2 read-write FDCANSEL HSE HSE clock selected as FDCAN clock 0 PLLQ PLL 'Q' clock selected as FDCAN clock 1 PCLK PCLK clock selected as FDCAN clock 2 CLK48SEL 48 MHz clock source selection These bits are set and cleared by software to select the 48 MHz clock source used by USB device FS and RNG. 26 2 read-write CLK48SEL HSI48 HSI48 clock selected as 48MHz clock 0 PLLQ PLL 'Q' (PLL48M1CLK) clock selected as 48MHz clock 2 ADC12SEL ADC1/2 clock source selection These bits are set and cleared by software to select the clock source used by the ADC interface. 28 2 read-write ADC12SEL None No clock selected for ADC 0 PLLP PLL 'P' clock selected for ADC 1 System System clock selected for ADC 2 ADC345SEL ADC3/4/5 clock source selection These bits are set and cleared by software to select the clock source used by the ADC345 interface. 30 2 read-write BDCR BDCR RTC domain control register 0x90 0x20 0x00000000 0xFFFFFFFF LSEON LSE oscillator enable Set and cleared by software. 0 1 read-write LSEON Off LSE only enabled when requested by a peripheral or system function 0 On LSE enabled always generated by RCC 1 LSERDY LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. 1 1 read-only LSERDYR NotReady LSE clock not ready 0 Ready LSE clock ready 1 LSEBYP LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). 2 1 read-write LSEBYP NotBypassed LSE crystal oscillator not bypassed 0 Bypassed LSE crystal oscillator bypassed with external clock 1 LSEDRV LSE oscillator drive capability Set by software to modulate the LSE oscillators drive capability. The oscillator is in Xtal mode when it is not in bypass mode. 3 2 read-write LSEDRV Lower 'Xtal mode' lower driving capability 0 MediumLow 'Xtal mode' medium low driving capability 1 MediumHigh 'Xtal mode' medium high driving capability 2 Higher 'Xtal mode' higher driving capability 3 LSECSSON CSS on LSE enable Set by software to enable the Clock Security System on LSE (32 kHz oscillator). LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software MUST disable the LSECSSON bit. 5 1 read-write LSECSSON Off CSS on LSE (32 kHz external oscillator) OFF 0 On CSS on LSE (32 kHz external oscillator) ON 1 LSECSSD CSS on LSE failure Detection Set by hardware to indicate when a failure has been detected by the Clock Security System on the external 32 kHz oscillator (LSE). 6 1 read-only LSECSSDR NoFailure No failure detected on LSE (32 kHz oscillator) 0 Failure Failure detected on LSE (32 kHz oscillator) 1 RTCSEL RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them. 8 2 read-write RTCSEL NoClock No clock 0 LSE LSE oscillator clock used as RTC clock 1 LSI LSI oscillator clock used as RTC clock 2 HSE HSE oscillator clock divided by a prescaler used as RTC clock 3 RTCEN RTC clock enable Set and cleared by software. 15 1 read-write RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 BDRST RTC domain software reset Set and cleared by software. 16 1 read-write BDRST Disabled Reset not activated 0 Enabled Reset the entire RTC domain 1 LSCOEN Low speed clock output enable Set and cleared by software. 24 1 read-write LSCOEN Disabled LSCO disabled 0 Enabled LSCO enabled 1 LSCOSEL Low speed clock output selection Set and cleared by software. 25 1 read-write LSCOSEL LSI LSI clock selected 0 LSE LSE clock selected 1 CSR CSR Control/status register 0x94 0x20 0x0C000000 0xFFFFFFFF LSION LSI oscillator enable Set and cleared by software. 0 1 read-write LSION Off LSI oscillator Off 0 On LSI oscillator On 1 LSIRDY LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. 1 1 read-only LSIRDYR NotReady LSI oscillator not ready 0 Ready LSI oscillator ready 1 RMVF Remove reset flag Set by software to clear the reset flags. 23 1 read-write RMVFW write Clear Clears the reset flag 1 OBLRSTF Option byte loader reset flag Set by hardware when a reset from the Option Byte loading occurs. Cleared by writing to the RMVF bit. 25 1 read-only OBLRSTFR NoReset No reset has occured 0 Reset A reset has occured 1 PINRSTF Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 26 1 read-only BORRSTF BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit. 27 1 read-only SFTRSTF Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 28 1 read-only IWDGRSTF Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit. 29 1 read-only WWDGRSTF Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. 30 1 read-only LPWRRSTF Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry. Cleared by writing to the RMVF bit. 31 1 read-only CRRCR CRRCR Clock recovery RC register 0x98 0x20 0x00000000 0xFFFFFFFF HSI48ON HSI48 clock enable Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes. 0 1 read-write HSI48RDY HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON. 1 1 read-only HSI48CAL HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. They are ready only. 7 9 read-only CCIPR2 CCIPR2 Peripherals independent clock configuration register 0x9C 0x20 0x00000000 0xFFFFFFFF I2C4SEL I2C4 clock source selection These bits are set and cleared by software to select the I2C4 clock source. 0 2 read-write I2C4SEL PCLK PCLK clock selected as I2C clock 0 System System clock (SYSCLK) selected as I2C clock 1 HSI16 HSI16 clock selected as I2C clock 2 QSPISEL QUADSPI clock source selection Set and reset by software. 20 2 read-write QSPISEL System System clock selected as QUADSPI kernel clock 0 HSI16 HSI16 clock selected as QUADSPI kernel clock 1 PLLQ PLL 'Q' clock selected as QUADSPI kernel clock 2 PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x20 0x00000200 0xFFFFFFFF LPMS Low-power mode selection These bits select the low-power mode entered when CPU enters the deepsleep mode. 1xx: Shutdown mode Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. 0 3 read-write FPD_STOP FPD_STOP 3 1 read-write DBP Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 8 1 read-write VOS Voltage scaling range selection 9 2 read-write LPR Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). 14 1 read-write CR2 CR2 Power control register 2 0x4 0x20 0x00000000 0xFFFFFFFF PVDE Programmable voltage detector enable Note: This bit is write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset. 0 1 read-write PVDLS Programmable voltage detector level selection. These bits select the PVD falling threshold: Note: These bits are write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset. 1 3 read-write PVMEN1 Peripheral voltage monitoring 3 enable: VDDA vs. ADC/COMP min voltage 1.62V 6 1 read-write PVMEN2 Peripheral voltage monitoring 4 enable: VDDA vs. DAC 1MSPS /DAC 15MSPS min voltage. 7 1 read-write CR3 CR3 Power control register 3 0x8 0x20 0x00008000 0xFFFFFFFF EWUP1 Enable Wakeup pin WKUP1 When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. 0 1 read-write EWUP2 Enable Wakeup pin WKUP2 When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. 1 1 read-write EWUP3 Enable Wakeup pin WKUP3 When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. 2 1 read-write EWUP4 Enable Wakeup pin WKUP4 When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. 3 1 read-write EWUP5 Enable Wakeup pin WKUP5 When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. 4 1 read-write RRS SRAM2 retention in Standby mode 8 1 read-write APC Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os. 10 1 read-write UCPD1_STDBY UCPD1_STDBY USB Type-C and Power Delivery standby mode. 13 1 read-write UCPD1_DBDIS USB Type-C and Power Delivery Dead Battery disable. After exiting reset, the USB Type-C dead battery behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to hand over control to the UCPD1 (which should therefore be initialized before doing the disable). 14 1 read-write EIWUL Enable internal wakeup line 15 1 read-write CR4 CR4 Power control register 4 0xC 0x20 0x00000000 0xFFFFFFFF WP1 Wakeup pin WKUP1 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 0 1 read-write WP2 Wakeup pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 1 1 read-write WP3 Wakeup pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 2 1 read-write WP4 Wakeup pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 3 1 read-write WP5 Wakeup pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 4 1 read-write VBE VBAT battery charging enable 8 1 read-write VBRS VBAT battery charging resistor selection 9 1 read-write SR1 SR1 Power status register 1 0x10 0x20 0x00000000 0xFFFFFFFF WUF1 Wakeup flag 1 This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register. 0 1 read-only WUF2 Wakeup flag 2 This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register. 1 1 read-only WUF3 Wakeup flag 3 This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register. 2 1 read-only WUF4 Wakeup flag 4 This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register. 3 1 read-only WUF5 Wakeup flag 5 This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register. 4 1 read-only SBF Standby flag This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. 8 1 read-only WUFI Wakeup flag internal This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. 15 1 read-only SR2 SR2 Power status register 2 0x14 0x20 0x00000000 0xFFFFFFFF REGLPS Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased. 8 1 read-only REGLPF Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready. 9 1 read-only VOSF Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. 10 1 read-only PVDO Programmable voltage detector output 11 1 read-only PVMO1 Peripheral voltage monitoring output: VDDA vs. 1.62 V Note: PVMO1 is cleared when PVM1 is disabled (PVME = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wakeup time. 14 1 read-only PVMO2 Peripheral voltage monitoring output: VDDA vs. 1.8 V Note: PVMO2 is cleared when PVM2 is disabled (PVME = 0). After enabling PVM2, the PVM2 output is valid after the PVM2 wakeup time. 15 1 read-only SCR SCR Power status clear register 0x18 0x20 0x00000000 0xFFFFFFFF CWUF1 Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register. 0 1 write-only CWUF2 Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register. 1 1 write-only CWUF3 Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register. 2 1 write-only CWUF4 Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register. 3 1 write-only CWUF5 Clear wakeup flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register. 4 1 write-only CSBF Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. 8 1 write-only PUCRA PUCRA Power Port A pull-up control register 0x20 0x20 0x00000000 0xFFFFFFFF PU0 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU15 Port A pull-up bit 15 When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PD15 bit is also set. 15 1 read-write PDCRA PDCRA Power Port A pull-down control register 0x24 0x20 0x00000000 0xFFFFFFFF PD0 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD14 Port A pull-down bit 14 When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register. 14 1 read-write PUCRB PUCRB Power Port B pull-up control register 0x28 0x20 0x00000000 0xFFFFFFFF PU0 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRB PDCRB Power Port B pull-down control register 0x2C 0x20 0x00000000 0xFFFFFFFF PD0 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD5 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRC PUCRC Power Port C pull-up control register 0x30 0x20 0x00000000 0xFFFFFFFF PU0 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRC PDCRC Power Port C pull-down control register 0x34 0x20 0x00000000 0xFFFFFFFF PD0 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRD PUCRD Power Port D pull-up control register 0x38 0x20 0x00000000 0xFFFFFFFF PU0 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRD PDCRD Power Port D pull-down control register 0x3C 0x20 0x00000000 0xFFFFFFFF PD0 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRE PUCRE Power Port E pull-up control register 0x40 0x20 0x00000000 0xFFFFFFFF PU0 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRE PDCRE Power Port E pull-down control register 0x44 0x20 0x00000000 0xFFFFFFFF PD0 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRF PUCRF Power Port F pull-up control register 0x48 0x20 0x00000000 0xFFFFFFFF PU0 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PDCRF PDCRF Power Port F pull-down control register 0x4C 0x20 0x00000000 0xFFFFFFFF PD0 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PUCRG PUCRG Power Port G pull-up control register 0x50 0x20 0x00000000 0xFFFFFFFF PU0 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PDCRG PDCRG Power Port G pull-down control register 0x54 0x20 0x00000000 0xFFFFFFFF PD0 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 10 1 read-write CR5 CR5 Power control register 0x80 0x20 0x00000100 0xFFFFFFFF R1MODE Main regular range 1 mode This bit is only valid for the main regulator in range 1 and has no effect on range 2. It is recommended to reset this bit when the system frequency is greater than 150 MHz. Refer to 8 1 read-write RNG Random number generator RNG 0x50060800 0x0 0x400 registers RNG RNG 90 CR CR control register 0x0 0x20 read-write 0x00000000 CED Clock error detection 5 1 CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 IE Interrupt enable 3 1 IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 RNGEN Random number generator enable 2 1 RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 SR SR status register 0x4 0x20 0x00000000 CEIS Clock error interrupt status 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 SECS Seed error current status 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CECS Clock error current status 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 DRDY Data ready 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 DR DR data register 0x8 0x20 read-only 0x00000000 RNDATA Random data 0 32 0 4294967295 GPIOA General-purpose I/Os GPIO 0x48000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xABFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 IDR%s Port input data pin %s 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 ODR%s Port output data pin %s 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 16 1 BitReset Reset Resets the corresponding ODRx bit 1 16 0x1 0-15 BS%s Port x set pin %s 0 1 BitSet Set Sets the corresponding ODRx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 8 0x4 L0,L1,L2,L3,L4,L5,L6,L7 AFR%s Alternate function selection for port x bit y (y = 0..7) 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 8 0x4 H8,H9,H10,H11,H12,H13,H14,H15 AFR%s Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 0 1 BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 GPIOB General-purpose I/Os GPIO 0x48000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFEBF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 GPIOC General-purpose I/Os GPIO 0x48000800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 GPIOD 0x48000C00 GPIOE 0x48001000 GPIOF 0x48001400 GPIOG 0x48001800 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering Enable 12 1 DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 2 0x2 1-2 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 TS2 Trigger selection - bit 4:3 20 2 SMS_3 Slave mode selection - bit 3 16 1 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 2 0x1 1-2 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S CC2S 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF Copy 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 20 0 1048575 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 8 0 255 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 20 0 1048575 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 0 255 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter 16 4 BKDSRM BKDSRM 26 1 BKBID BKBID 28 1 DTR2 DTR2 timer Deadtime Register 2 0x54 0x20 read-write 0x00000000 DTGF Dead-time generator setup 0 8 DTAE Deadtime Asymmetric Enable 16 1 DTPE Deadtime Preload Enable 17 1 TISEL TISEL TIM timer input selection register 0x5C 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKCMP7E BRK COMP7 enable 7 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 AF2 AF2 TIM alternate function option register 2 0x64 0x20 read-write 0x00000000 OCRSEL OCREF_CLR source selection 16 3 DCR DCR DMA control register 0x3DC 0x20 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering Enable 12 1 DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 COMDE COM DMA request enable 13 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 1 0x0 1-1 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF Copy 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 20 0 1048575 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 8 0 255 1 0x4 1-1 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 20 0 1048575 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 0 255 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter 16 4 BKDSRM BKDSRM 26 1 BKBID BKBID 28 1 DTR2 DTR2 timer Deadtime Register 2 0x54 0x20 read-write 0x00000000 DTGF Dead-time generator setup 0 8 DTAE Deadtime Asymmetric Enable 16 1 DTPE Deadtime Preload Enable 17 1 TISEL TISEL TIM timer input selection register 0x5C 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKCMP7E BRK COMP7 enable 7 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 AF2 AF2 TIM alternate function option register 2 0x64 0x20 read-write 0x00000000 OCRSEL OCREF_CLR source selection 16 3 OR1 OR1 TIM option register 1 0x68 0x20 read-write 0x00000000 HSE32EN HSE Divided by 32 enable 0 1 DCR DCR DMA control register 0x3DC 0x20 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 TIM17 TIM 0x40014800 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_TIM15 TIM1_BRK_TIM15 24 TIM1_UP_TIM16 TIM1_UP_TIM16 25 TIM1_TRG_COM TIM1_TRG_COM/ 26 TIM1_CC TIM1 capture compare interrupt 27 TIM8_CC TIM8_CC 46 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 DITHEN Dithering Enable 12 1 DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS_3 Master mode selection - bit 3 25 1 MMS2 Master mode selection 2 20 4 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 4 0x2 1-4 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMSPS SMS Preload Source 25 1 SMSPE SMS Preload Enable 24 1 TS2 Trigger selection - bit 4:3 20 2 SMS_3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TERRIE Transition Error interrupt enable 23 1 IERRIE Index Error interrupt enable 22 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 TERRF Transition Error interrupt flag 23 1 IERRF Index Error interrupt flag 22 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 CC6IF Compare 6 interrupt flag 17 1 zeroToClear read write CC5IF Compare 5 interrupt flag 16 1 zeroToClear read write SBIF System Break interrupt flag 13 1 zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 B2IF Break 2 interrupt flag 8 1 zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 B2G Break 2 generation 8 1 B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 4 0x4 1-4 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 CNT CNT counter 0x24 0x20 0x00000000 UIFCPY UIFCPY 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 20 0 1048575 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 20 0 1048575 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 BK2ID BK2ID 29 1 BKBID BKBID 28 1 BK2DSRM BK2DSRM 27 1 BKDSRM BKDSRM 26 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 BK2P Break 2 polarity 25 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BKF Break filter 16 4 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 DTG Dead-time generator setup 0 8 0 255 CCR5 CCR5 capture/compare register 0x48 0x20 read-write 0x00000000 CCR Capture/Compare value 0 20 0 1048575 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 0x4C 0x20 read-write 0x00000000 CCR Capture/Compare value 0 20 0 1048575 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 0x20 read-write 0x00000000 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 2 0x8 5-6 OC%sM Output compare %s mode 4 3 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 DTR2 DTR2 timer Deadtime Register 2 0x54 0x20 read-write 0x00000000 DTPE Deadtime Preload Enable 17 1 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 ECR ECR DMA control register 0x58 0x20 read-write 0x00000000 IE Index Enable 0 1 IDIR Index Direction 1 2 IBLK Index Blanking 3 2 FIDX First Index 5 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 TISEL TISEL TIM timer input selection register 0x5C 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 ETRSEL ETR source selection 14 4 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKCMP7E BRK COMP7 enable 7 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 AF2 AF2 TIM alternate function option register 2 0x64 0x20 read-write 0x00000000 OCRSEL OCREF_CLR source selection 16 3 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP1E BRK2 COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 DCR DCR control register 0x3DC 0x20 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 TIM20 TIM 0x40015000 TIM20_BRK TIM20_BRK 77 TIM20_UP TIM20_UP 78 TIM20_TRG_COM TIM20_TRG_COM 79 TIM20_CC TIM20_CC 80 TIM8 TIM 0x40013400 TIM8_BRK TIM8_BRK 43 TIM8_UP TIM8_UP 44 TIM8_TRG_COM TIM8_TRG_COM 45 TIM2 Advanced-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 28 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 DITHEN Dithering Enable 12 1 DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS_3 Master mode selection - bit 3 25 1 MMS2 Master mode selection 2 20 4 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 4 0x2 1-4 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMSPS SMS Preload Source 25 1 SMSPE SMS Preload Enable 24 1 TS2 Trigger selection - bit 4:3 20 2 SMS_3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TERRIE Transition Error interrupt enable 23 1 IERRIE Index Error interrupt enable 22 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 COMDE COM DMA request enable 13 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 SR SR status register 0x10 0x20 read-write 0x00000000 TERRF Transition Error interrupt flag 23 1 IERRF Index Error interrupt flag 22 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 CC6IF Compare 6 interrupt flag 17 1 zeroToClear read write CC5IF Compare 5 interrupt flag 16 1 zeroToClear read write SBIF System Break interrupt flag 13 1 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 B2G Break 2 generation 8 1 BG Break generation 7 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 4 0x4 1-4 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 UIFCPY UIFCPY 31 1 UIFCPYR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 CNT counter value 0 32 0 4294967295 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR Auto-reload value 0 32 0 4294967295 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 16 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare 1 value 0 32 0 4294967295 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 BK2ID BK2ID 29 1 BKBID BKBID 28 1 BK2DSRM BK2DSRM 27 1 BKDSRM BKDSRM 26 1 BK2P Break 2 polarity 25 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BKF Break filter 16 4 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 CCR5 CCR5 capture/compare register 0x48 0x20 read-write 0x00000000 CCR Capture/Compare value 0 32 0 4294967295 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 0x4C 0x20 read-write 0x00000000 CCR Capture/Compare value 0 32 0 4294967295 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 0x20 read-write 0x00000000 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 2 0x8 5-6 OC%sM Output compare %s mode 4 3 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 DTR2 DTR2 timer Deadtime Register 2 0x54 0x20 read-write 0x00000000 DTPE Deadtime Preload Enable 17 1 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 ECR ECR DMA control register 0x58 0x20 read-write 0x00000000 IE Index Enable 0 1 IDIR Index Direction 1 2 IBLK Index Blanking 3 2 FIDX First Index 5 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 TISEL TISEL TIM timer input selection register 0x5C 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 ETRSEL ETR source selection 14 4 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKCMP7E BRK COMP7 enable 7 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 AF2 AF2 TIM alternate function option register 2 0x64 0x20 read-write 0x00000000 OCRSEL OCREF_CLR source selection 16 3 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP1E BRK2 COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 DCR DCR control register 0x3DC 0x20 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 TIM3 Advanced-timers TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 29 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 DITHEN Dithering Enable 12 1 DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 Ã t_CK_INT 1 Div4 t_DTS = 4 Ã t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS_3 Master mode selection - bit 3 25 1 MMS2 Master mode selection 2 20 4 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 4 0x2 1-4 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMSPS SMS Preload Source 25 1 SMSPE SMS Preload Enable 24 1 TS2 Trigger selection - bit 4:3 20 2 SMS_3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TERRIE Transition Error interrupt enable 23 1 IERRIE Index Error interrupt enable 22 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 COMDE COM DMA request enable 13 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 SR SR status register 0x10 0x20 read-write 0x00000000 TERRF Transition Error interrupt flag 23 1 IERRF Index Error interrupt flag 22 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 CC6IF Compare 6 interrupt flag 17 1 zeroToClear read write CC5IF Compare 5 interrupt flag 16 1 zeroToClear read write SBIF System Break interrupt flag 13 1 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 B2G Break 2 generation 8 1 BG Break generation 7 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 4 0x4 1-4 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 UIFCPY UIFCPY 31 1 UIFCPYR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 CNT counter value 0 16 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR Auto-reload value 0 20 0 1048575 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 16 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 20 0 1048575 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 BK2ID BK2ID 29 1 BKBID BKBID 28 1 BK2DSRM BK2DSRM 27 1 BKDSRM BKDSRM 26 1 BK2P Break 2 polarity 25 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BKF Break filter 16 4 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 CCR5 CCR5 capture/compare register 0x48 0x20 read-write 0x00000000 CCR Capture/Compare value 0 20 0 1048575 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 0x4C 0x20 read-write 0x00000000 CCR Capture/Compare value 0 20 0 1048575 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 0x20 read-write 0x00000000 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 2 0x8 5-6 OC%sM Output compare %s mode 4 3 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 DTR2 DTR2 timer Deadtime Register 2 0x54 0x20 read-write 0x00000000 DTPE Deadtime Preload Enable 17 1 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 ECR ECR DMA control register 0x58 0x20 read-write 0x00000000 IE Index Enable 0 1 IDIR Index Direction 1 2 IBLK Index Blanking 3 2 FIDX First Index 5 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 TISEL TISEL TIM timer input selection register 0x5C 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 ETRSEL ETR source selection 14 4 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKCMP7E BRK COMP7 enable 7 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 AF2 AF2 TIM alternate function option register 2 0x64 0x20 read-write 0x00000000 OCRSEL OCREF_CLR source selection 16 3 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP1E BRK2 COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 DCR DCR control register 0x3DC 0x20 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 TIM4 TIM 0x40000800 TIM4 TIM4 30 TIM5 TIM 0x40000C00 TIM5 TIM5 50 TIM6 Basic-timers TIM 0x40001000 0x0 0x400 registers TIM6_DACUNDER TIM6_DACUNDER 54 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 DITHEN Dithering Enable 12 1 DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS Master mode selection 4 3 MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT counter 0x24 0x20 0x00000000 UIFCPY UIF Copy 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 CNT Low counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Low Auto-reload value 0 20 0 1048575 TIM7 TIM 0x40001400 TIM7 TIM7 55 LPTIMER1 Low power timer LPTIM 0x40007C00 0x0 0x400 registers ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DOWN Counter direction change up to down 6 1 DOWNR Set Counter direction change up to down 1 UP Counter direction change down to up 5 1 UPR Set Counter direction change down to up 1 ARROK Autoreload register update OK 4 1 ARROKR Set Autoreload register update OK 1 CMPOK Compare register update OK 3 1 CMPOKR Set Compare register update OK 1 EXTTRIG External trigger edge event 2 1 EXTTRIGR Set External trigger edge event 1 ARRM Autoreload match 1 1 ARRMR Set Autoreload match 1 CMPM Compare match 0 1 CMPMR Set Compare match 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DOWNCF Direction change to down Clear Flag 6 1 DOWNCFW Clear Direction change to down Clear Flag 1 UPCF Direction change to UP Clear Flag 5 1 UPCFW Clear Direction change to up Clear Flag 1 ARROKCF Autoreload register update OK Clear Flag 4 1 ARROKCFW Clear Autoreload register update OK Clear Flag 1 CMPOKCF Compare register update OK Clear Flag 3 1 CMPOKCFW Clear Compare register update OK Clear Flag 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 EXTTRIGCFW Clear External trigger valid edge Clear Flag 1 ARRMCF Autoreload match Clear Flag 1 1 ARRMCFW Clear Autoreload match Clear Flag 1 CMPMCF compare match Clear Flag 0 1 CMPMCFW Clear Compare match Clear Flag 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 DOWNIE Direction change to down Interrupt Enable 6 1 DOWNIE Disabled DOWN interrupt disabled 0 Enabled DOWN interrupt enabled 1 UPIE Direction change to UP Interrupt Enable 5 1 UPIE Disabled UP interrupt disabled 0 Enabled UP interrupt enabled 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 ARROKIE Disabled ARROK interrupt disabled 0 Enabled ARROK interrupt enabled 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 CMPOKIE Disabled CMPOK interrupt disabled 0 Enabled CMPOK interrupt enabled 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 EXTTRIGIE Disabled EXTTRIG interrupt disabled 0 Enabled EXTTRIG interrupt enabled 1 ARRMIE Autoreload match Interrupt Enable 1 1 ARRMIE Disabled ARRM interrupt disabled 0 Enabled ARRM interrupt enabled 1 CMPMIE Compare match Interrupt Enable 0 1 CMPMIE Disabled CMPM interrupt disabled 0 Enabled CMPM interrupt enabled 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 ENC Disabled Encoder mode disabled 0 Enabled Encoder mode enabled 1 COUNTMODE counter mode enabled 23 1 COUNTMODE Internal The counter is incremented following each internal clock pulse 0 External The counter is incremented following each valid clock pulse on the LPTIM external Input1 1 PRELOAD Registers update mode 22 1 PRELOAD Immediate Registers are updated after each APB bus write access 0 EndOfPeriod Registers are updated at the end of the current LPTIM period 1 WAVPOL Waveform shape polarity 21 1 WAVPOL Positive The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 0 Negative The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 1 WAVE Waveform shape 20 1 WAVE Inactive Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit) 0 Active Activate the Set-once mode 1 TIMOUT Timeout enable 19 1 TIMOUT Disabled A trigger event arriving when the timer is already started will be ignored 0 Enabled A trigger event arriving when the timer is already started will reset and restart the counter 1 TRIGEN Trigger enable and polarity 17 2 TRIGEN SW Software trigger (counting start is initiated by software) 0 RisingEdge Rising edge is the active edge 1 FallingEdge Falling edge is the active edge 2 BothEdges Both edges are active edges 3 TRIGSEL Trigger selector 13 4 TRIGSEL Trig0 lptim_ext_trig0 0 Trig1 lptim_ext_trig1 1 Trig2 lptim_ext_trig2 2 Trig3 lptim_ext_trig3 3 Trig4 lptim_ext_trig4 4 Trig5 lptim_ext_trig5 5 Trig6 lptim_ext_trig6 6 Trig7 lptim_ext_trig7 7 PRESC Clock prescaler 9 3 PRESC Div1 /1 0 Div2 /2 1 Div4 /4 2 Div8 /8 3 Div16 /16 4 Div32 /32 5 Div64 /64 6 Div128 /128 7 TRGFLT Configurable digital filter for trigger 6 2 TRGFLT Immediate Any trigger active level change is considered as a valid trigger 0 Clocks2 Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger 1 Clocks4 Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger 2 Clocks8 Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger 3 CKFLT Configurable digital filter for external clock 3 2 CKFLT Immediate Any external clock signal level change is considered as a valid transition 0 Clocks2 External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition 1 Clocks4 External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition 2 Clocks8 External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition 3 CKPOL Clock Polarity 1 2 CKPOL RisingEdge The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active. 0 FallingEdge The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active. 1 BothEdges Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active. 2 CKSEL Clock selector 0 1 CKSEL Internal LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 0 External LPTIM is clocked by an external clock source through the LPTIM external Input1 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 RSTARE RSTARE 4 1 RSTARE Disabled CNT Register reads do not trigger reset 0 Enabled CNT Register reads trigger reset of LPTIM 1 COUNTRST COUNTRST 3 1 COUNTRSTR read Idle Triggering of reset is possible 0 Busy Reset in progress, do not write 1 to this field 1 COUNTRSTW write Reset Trigger synchronous reset of CNT (3 LPTimer core clock cycles) 1 CNTSTRT Timer start in continuous mode 2 1 CNTSTRTW write Start Timer start in Continuous mode 1 SNGSTRT LPTIM start in single mode 1 1 SNGSTRTW write Start LPTIM start in Single mode 1 ENABLE LPTIM Enable 0 1 ENABLE Disabled LPTIM is disabled 0 Enabled LPTIM is enabled 1 CMP CMP Compare Register 0x14 0x20 read-write 0x00000000 CMP Compare value 0 16 0 65535 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 0 65535 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 0 65535 OR OR option register 0x20 0x20 read-write 0x00000000 IN1 IN1 0 1 IN2 IN2 1 1 IN1_2_1 IN1_2_1 2 2 IN2_2_1 IN2_2_1 4 2 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 37 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFFIE 31 1 RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 TXFEIE TXFEIE 30 1 TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 FIFOEN FIFOEN 29 1 FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 M1 M1 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 EOBIE End of Block interrupt enable 27 1 EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 RTOIE Receiver timeout interrupt enable 26 1 RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 DEAT Driver Enable assertion time 21 5 0 31 DEDT Driver Enable de-assertion time 16 5 0 31 OVER8 Oversampling mode 15 1 OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 RTOEN Receiver timeout enable 23 1 RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ABRMOD Auto baud rate mode 21 2 ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 ABREN Auto baud rate enable 20 1 ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 LINEN LIN mode enable 14 1 LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 CPOL Clock polarity 10 1 CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CPHA Clock phase 9 1 CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 LBCL Last bit clock pulse 8 1 LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 LBDIE LIN break detection interrupt enable 6 1 LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBDL LIN break detection length 5 1 LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 DIS_NSS DIS_NSS 3 1 DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 SLVEN SLVEN 0 1 SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFTCFG 29 3 TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 RXFTIE RXFTIE 28 1 RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 RXFTCFG RXFTCFG 25 3 RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 TCBGTIE TCBGTIE 24 1 TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 TXFTIE TXFTIE 23 1 TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 SCARCNT Smartcard auto-retry count 17 3 0 7 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 ONEBIT One sample bit method enable 11 1 ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 SCEN Smartcard mode enable 5 1 SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 NACK Smartcard NACK enable 4 1 NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 IRLP Ir low-power 2 1 IRLP Normal Normal mode 0 LowPower Low-power mode 1 IREN Ir mode enable 1 1 IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR DIV_Mantissa 0 16 0 65535 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 0 255 PSC Prescaler value 0 8 0 255 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 0 255 RTO Receiver timeout value 0 24 0 16777215 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ABRRQ Auto baud rate request 0 1 ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 TXFT TXFT 27 1 TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 RXFT RXFT 26 1 RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TCBGT TCBGT 25 1 TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFF RXFF 24 1 RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TXFE TXFE 23 1 TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 ABRF ABRF 15 1 ABRE ABRE 14 1 UDR UDR 13 1 UDR NoUnderrun No underrun error 0 Underrun underrun error 1 EOBF EOBF 12 1 EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 RTOF RTOF 11 1 RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 LBDF LBDF 8 1 LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 TXE TXE 7 1 TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXNE RXNE 5 1 RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NF NF 2 1 NF NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 UDRCF UDRCF 13 1 oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 EOBCF End of block clear flag 12 1 oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 RTOCF Receiver timeout clear flag 11 1 oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 LBDCF LIN break detection clear flag 8 1 oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 TCBGTCF TCBGTCF 7 1 oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TXFECF TXFECF 5 1 oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 PRESC PRESC USART prescaler register 0x2C 0x20 read-write 0x00000000 PRESCALER PRESCALER 0 4 PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 USART2 0x40004400 USART2 USART2 38 USART3 0x40004800 USART3 USART3 39 UART4 Universal synchronous asynchronous receiver transmitter USART 0x40004C00 0x0 0x400 registers UART4 UART4 52 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFFIE 31 1 TXFEIE TXFEIE 30 1 FIFOEN FIFOEN 29 1 M1 M1 28 1 RTOIE Receiver timeout interrupt enable 26 1 DEAT Driver Enable assertion time 21 5 DEDT Driver Enable de-assertion time 16 5 OVER8 Oversampling mode 15 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 RTOEN Receiver timeout enable 23 1 ABRMOD Auto baud rate mode 21 2 ABREN Auto baud rate enable 20 1 MSBFIRST Most significant bit first 19 1 DATAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFTCFG 29 3 RXFTIE RXFTIE 28 1 RXFTCFG RXFTCFG 25 3 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 HDSEL Half-duplex selection 3 1 IRLP Ir low-power 2 1 IREN Ir mode enable 1 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 RQR RQR Request register 0x18 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 TXFT TXFT 27 1 RXFT RXFT 26 1 RXFF RXFF 24 1 TXFE TXFE 23 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 ABRF ABRF 15 1 ABRE ABRE 14 1 RTOF RTOF 11 1 CTS CTS 10 1 CTSIF CTSIF 9 1 LBDF LBDF 8 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 RTOCF Receiver timeout clear flag 11 1 CTSCF CTS clear flag 9 1 LBDCF LIN break detection clear flag 8 1 TCBGTCF TCBGTCF 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFECF 5 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 TDR TDR Transmit data register 0x28 PRESC PRESC USART prescaler register 0x2C UART5 0x40005000 UART5 UART5 53 LPUART1 Universal synchronous asynchronous receiver transmitter USART 0x40008000 0x0 0x400 registers LPTIM1 LPTIM1 49 LPUART LPUART 91 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFFIE 31 1 TXFEIE TXFEIE 30 1 FIFOEN FIFOEN 29 1 M1 Word length 28 1 DEAT Driver Enable assertion time 21 5 DEDT Driver Enable de-assertion time 16 5 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 MSBFIRST Most significant bit first 19 1 DATAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop2 2 stop bit 2 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFTCFG 29 3 RXFTIE RXFTIE 28 1 RXFTCFG RXFTCFG 25 3 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 HDSEL Half-duplex selection 3 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR BRR 0 20 0 1048575 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ TXFRQ 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 TXFT TXFT 27 1 RXFT RXFT 26 1 RXFF RXFF 24 1 TXFE TXFE 23 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 CTS CTS 10 1 CTSIF CTSIF 9 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 TDR TDR Transmit data register 0x28 PRESC PRESC Prescaler register 0x2C SPI1 Serial peripheral interface/Inter-IC sound SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 35 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 CRCL CRC length 11 1 CRCL EightBit 8-bit CRC length 0 SixteenBit 16-bit CRC length 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000700 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 NSSP NSS pulse management 3 1 NSSP NoPulse No NSS pulse 0 PulseGenerated NSS pulse generated 1 FRF Frame format 4 1 FRF Motorola SPI Motorola mode 0 TI SPI TI mode 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 DS Data size 8 4 DS FourBit 4-bit 3 FiveBit 5-bit 4 SixBit 6-bit 5 SevenBit 7-bit 6 EightBit 8-bit 7 NineBit 9-bit 8 TenBit 10-bit 9 ElevenBit 11-bit 10 TwelveBit 12-bit 11 ThirteenBit 13-bit 12 FourteenBit 14-bit 13 FifteenBit 15-bit 14 SixteenBit 16-bit 15 FRXTH FIFO reception threshold 12 1 FRXTH Half RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 0 Quarter RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_RX Even Number of data to transfer for receive is even 0 Odd Number of data to transfer for receive is odd 1 LDMA_TX Last DMA transfer for transmission 14 1 LDMA_TX Even Number of data to transfer for transmit is even 0 Odd Number of data to transfer for transmit is odd 1 SR SR status register 0x8 0x10 0x00000002 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 FRE Frame format error 8 1 read-only FRER NoError No frame format error 0 Error A frame format error occurred 1 FRLVL FIFO reception level 9 2 read-only FRLVLR Empty Rx FIFO Empty 0 Quarter Rx 1/4 FIFO 1 Half Rx 1/2 FIFO 2 Full Rx FIFO full 3 FTLVL FIFO transmission level 11 2 read-only FTLVLR Empty Tx FIFO Empty 0 Quarter Tx 1/4 FIFO 1 Half Tx 1/2 FIFO 2 Full Tx FIFO full 3 DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 I2SCFGR I2SCFGR configuration register 0x1C 0x10 read-write 0x00000000 CHLEN CHLEN 0 1 CHLEN SixteenBit 16-bit wide 0 ThirtyTwoBit 32-bit wide 1 DATLEN DATLEN 1 2 DATLEN SixteenBit 16-bit data length 0 TwentyFourBit 24-bit data length 1 ThirtyTwoBit 32-bit data length 2 CKPOL CKPOL 3 1 CKPOL IdleLow I2S clock inactive state is low level 0 IdleHigh I2S clock inactive state is high level 1 I2SSTD I2SSTD 4 2 I2SSTD Philips I2S Philips standard 0 MSB MSB justified standard 1 LSB LSB justified standard 2 PCM PCM standard 3 PCMSYNC PCMSYNC 7 1 PCMSYNC Short Short frame synchronisation 0 Long Long frame synchronisation 1 I2SCFG I2SCFG 8 2 I2SCFG SlaveTx Slave - transmit 0 SlaveRx Slave - receive 1 MasterTx Master - transmit 2 MasterRx Master - receive 3 I2SE I2SE 10 1 I2SE Disabled I2S peripheral is disabled 0 Enabled I2S peripheral is enabled 1 I2SMOD I2SMOD 11 1 I2SMOD SPIMode SPI mode is selected 0 I2SMode I2S mode is selected 1 I2SPR I2SPR prescaler register 0x20 0x10 read-write 0x00000002 I2SDIV I2SDIV 0 8 2 255 ODD ODD 8 1 ODD Even Real divider value is I2SDIV * 2 0 Odd Real divider value is (I2SDIV * 2) + 1 1 MCKOE MCKOE 9 1 MCKOE Disabled Master clock output is disabled 0 Enabled Master clock output is enabled 1 SPI4 Serial peripheral interface/Inter-IC sound SPI 0x40013C00 SPI4 SPI4 84 SPI3 0x40003C00 SPI3 SPI3 51 SPI2 0x40003800 SPI2 SPI2 36 EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers PVD_PVM PVD through EXTI line detection 1 EXTI0 EXTI Line0 interrupt 6 EXTI1 EXTI Line1 interrupt 7 EXTI2 EXTI Line2 interrupt 8 EXTI3 EXTI Line3 interrupt 9 EXTI4 EXTI Line4 interrupt 10 USB_HP USB_HP 19 USB_LP USB_LP 20 EXTI9_5 EXTI9_5 23 EXTI15_10 EXTI15_10 40 USBWakeUP USBWakeUP 42 CRS CRS 75 FPU Floating point unit interrupt 81 IMR1 IMR1 Interrupt mask register 0x0 0x20 read-write 0xFF820000 IM0 Interrupt Mask on line 0 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 IM1 Interrupt Mask on line 1 1 1 IM2 Interrupt Mask on line 2 2 1 IM3 Interrupt Mask on line 3 3 1 IM4 Interrupt Mask on line 4 4 1 IM5 Interrupt Mask on line 5 5 1 IM6 Interrupt Mask on line 6 6 1 IM7 Interrupt Mask on line 7 7 1 IM8 Interrupt Mask on line 8 8 1 IM9 Interrupt Mask on line 9 9 1 IM10 Interrupt Mask on line 10 10 1 IM11 Interrupt Mask on line 11 11 1 IM12 Interrupt Mask on line 12 12 1 IM13 Interrupt Mask on line 13 13 1 IM14 Interrupt Mask on line 14 14 1 IM15 Interrupt Mask on line 15 15 1 IM16 Interrupt Mask on line 16 16 1 IM17 Interrupt Mask on line 17 17 1 IM18 Interrupt Mask on line 18 18 1 IM19 Interrupt Mask on line 19 19 1 IM20 Interrupt Mask on line 20 20 1 IM21 Interrupt Mask on line 21 21 1 IM22 Interrupt Mask on line 22 22 1 IM23 Interrupt Mask on line 23 23 1 IM24 Interrupt Mask on line 24 24 1 IM25 Interrupt Mask on line 25 25 1 IM26 Interrupt Mask on line 26 26 1 IM27 Interrupt Mask on line 27 27 1 IM28 Interrupt Mask on line 28 28 1 IM29 Interrupt Mask on line 29 29 1 IM30 Interrupt Mask on line 30 30 1 IM31 Interrupt Mask on line 31 31 1 EMR1 EMR1 Event mask register 0x4 0x20 read-write 0x00000000 EM0 Event Mask on line 0 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM1 Event Mask on line 1 1 1 EM2 Event Mask on line 2 2 1 EM3 Event Mask on line 3 3 1 EM4 Event Mask on line 4 4 1 EM5 Event Mask on line 5 5 1 EM6 Event Mask on line 6 6 1 EM7 Event Mask on line 7 7 1 EM8 Event Mask on line 8 8 1 EM9 Event Mask on line 9 9 1 EM10 Event Mask on line 10 10 1 EM11 Event Mask on line 11 11 1 EM12 Event Mask on line 12 12 1 EM13 Event Mask on line 13 13 1 EM14 Event Mask on line 14 14 1 EM15 Event Mask on line 15 15 1 EM16 Event Mask on line 16 16 1 EM17 Event Mask on line 17 17 1 EM18 Event Mask on line 18 18 1 EM19 Event Mask on line 19 19 1 EM20 Event Mask on line 20 20 1 EM21 Event Mask on line 21 21 1 EM22 Event Mask on line 22 22 1 EM23 Event Mask on line 23 23 1 EM24 Event Mask on line 24 24 1 EM25 Event Mask on line 25 25 1 EM26 Event Mask on line 26 26 1 EM27 Event Mask on line 27 27 1 EM28 Event Mask on line 28 28 1 EM29 Event Mask on line 29 29 1 EM30 Event Mask on line 30 30 1 EM31 Event Mask on line 31 31 1 RTSR1 RTSR1 Rising Trigger selection register 0x8 0x20 read-write 0x00000000 RT0 Rising trigger event configuration of line 0 0 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT1 Rising trigger event configuration of line 1 1 1 RT2 Rising trigger event configuration of line 2 2 1 RT3 Rising trigger event configuration of line 3 3 1 RT4 Rising trigger event configuration of line 4 4 1 RT5 Rising trigger event configuration of line 5 5 1 RT6 Rising trigger event configuration of line 6 6 1 RT7 Rising trigger event configuration of line 7 7 1 RT8 Rising trigger event configuration of line 8 8 1 RT9 Rising trigger event configuration of line 9 9 1 RT10 Rising trigger event configuration of line 10 10 1 RT11 Rising trigger event configuration of line 11 11 1 RT12 Rising trigger event configuration of line 12 12 1 RT13 Rising trigger event configuration of line 13 13 1 RT14 Rising trigger event configuration of line 14 14 1 RT15 Rising trigger event configuration of line 15 15 1 RT16 Rising trigger event configuration of line 16 16 1 RT19 Rising trigger event configuration of line 19 19 1 RT20 Rising trigger event configuration of line 20 20 1 RT21 Rising trigger event configuration of line 21 21 1 RT22 Rising trigger event configuration of line 22 22 1 RT29 Rising trigger event configuration of line 29 29 1 RT17 Rising trigger event configuration of line 17 17 1 RT30 Rising trigger event configuration of line 30 30 1 RT31 Rising trigger event configuration of line 31 31 1 FTSR1 FTSR1 Falling Trigger selection register 0xC 0x20 read-write 0x00000000 FT0 Falling trigger event configuration of line 0 0 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT1 Falling trigger event configuration of line 1 1 1 FT2 Falling trigger event configuration of line 2 2 1 FT3 Falling trigger event configuration of line 3 3 1 FT4 Falling trigger event configuration of line 4 4 1 FT5 Falling trigger event configuration of line 5 5 1 FT6 Falling trigger event configuration of line 6 6 1 FT7 Falling trigger event configuration of line 7 7 1 FT8 Falling trigger event configuration of line 8 8 1 FT9 Falling trigger event configuration of line 9 9 1 FT10 Falling trigger event configuration of line 10 10 1 FT11 Falling trigger event configuration of line 11 11 1 FT12 Falling trigger event configuration of line 12 12 1 FT13 Falling trigger event configuration of line 13 13 1 FT14 Falling trigger event configuration of line 14 14 1 FT15 Falling trigger event configuration of line 15 15 1 FT16 Falling trigger event configuration of line 16 16 1 FT19 Falling trigger event configuration of line 19 19 1 FT20 Falling trigger event configuration of line 20 20 1 FT21 Falling trigger event configuration of line 21 21 1 FT22 Falling trigger event configuration of line 22 22 1 FT17 Falling trigger event configuration of line 17 17 1 FT29 Falling trigger event configuration of line 29 29 1 FT30 Falling trigger event configuration of line 30 30 1 FT31 Falling trigger event configuration of line 31 31 1 SWIER1 SWIER1 Software interrupt event register 0x10 0x20 read-write 0x00000000 SWI0 Software Interrupt on line 0 0 1 SoftwareInterrupt write Pend Generates an interrupt request 1 SWI1 Software Interrupt on line 1 1 1 SWI2 Software Interrupt on line 2 2 1 SWI3 Software Interrupt on line 3 3 1 SWI4 Software Interrupt on line 4 4 1 SWI5 Software Interrupt on line 5 5 1 SWI6 Software Interrupt on line 6 6 1 SWI7 Software Interrupt on line 7 7 1 SWI8 Software Interrupt on line 8 8 1 SWI9 Software Interrupt on line 9 9 1 SWI10 Software Interrupt on line 10 10 1 SWI11 Software Interrupt on line 11 11 1 SWI12 Software Interrupt on line 12 12 1 SWI13 Software Interrupt on line 13 13 1 SWI14 Software Interrupt on line 14 14 1 SWI15 Software Interrupt on line 15 15 1 SWI16 Software Interrupt on line 16 16 1 SWI19 Software Interrupt on line 19 19 1 SWI20 Software Interrupt on line 20 20 1 SWI21 Software Interrupt on line 21 21 1 SWI22 Software Interrupt on line 22 22 1 SWI17 Software Interrupt on line 17 17 1 PR1 PR1 Pending register 0x14 0x20 read-write 0x00000000 PIF0 Pending bit 0 0 1 oneToClear PIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PIF0W write Clear Clears pending bit 1 PIF1 Pending bit 1 1 1 oneToClear read write PIF2 Pending bit 2 2 1 oneToClear read write PIF3 Pending bit 3 3 1 oneToClear read write PIF4 Pending bit 4 4 1 oneToClear read write PIF5 Pending bit 5 5 1 oneToClear read write PIF6 Pending bit 6 6 1 oneToClear read write PIF7 Pending bit 7 7 1 oneToClear read write PIF8 Pending bit 8 8 1 oneToClear read write PIF9 Pending bit 9 9 1 oneToClear read write PIF10 Pending bit 10 10 1 oneToClear read write PIF11 Pending bit 11 11 1 oneToClear read write PIF12 Pending bit 12 12 1 oneToClear read write PIF13 Pending bit 13 13 1 oneToClear read write PIF14 Pending bit 14 14 1 oneToClear read write PIF15 Pending bit 15 15 1 oneToClear read write PIF16 Pending bit 16 16 1 oneToClear read write PIF19 Pending bit 19 19 1 oneToClear read write PIF20 Pending bit 20 20 1 oneToClear read write PIF21 Pending bit 21 21 1 oneToClear read write PIF22 Pending bit 22 22 1 oneToClear read write PIF17 Pending bit 17 17 1 oneToClear read write IMR2 IMR2 Interrupt mask register 0x20 0x20 read-write 0xFFFFFF87 IM32 Interrupt Mask on external/internal line 32 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 IM33 Interrupt Mask on external/internal line 33 1 1 IM34 Interrupt Mask on external/internal line 34 2 1 IM35 Interrupt Mask on external/internal line 35 3 1 IM36 Interrupt Mask on external/internal line 36 4 1 IM37 Interrupt Mask on external/internal line 37 5 1 IM40 Interrupt Mask on external/internal line 40 8 1 IM41 Interrupt Mask on external/internal line 41 9 1 IM42 Interrupt Mask on external/internal line 42 10 1 IM43 Interrupt Mask on external/internal line 43 11 1 EMR2 EMR2 Event mask register 0x24 0x20 read-write 0x00000000 EM32 Event mask on external/internal line 32 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM33 Event mask on external/internal line 33 1 1 EM34 Event mask on external/internal line 34 2 1 EM35 Event mask on external/internal line 35 3 1 EM36 Event mask on external/internal line 36 4 1 EM37 Event mask on external/internal line 37 5 1 EM40 Event mask on external/internal line 40 8 1 EM41 Event mask on external/internal line 41 9 1 EM42 Event mask on external/internal line 42 10 1 EM43 Event mask on external/internal line 43 11 1 RTSR2 RTSR2 Rising Trigger selection register 0x28 0x20 read-write 0x00000000 RT32 Rising trigger event configuration bit of line 32 0 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT33 Rising trigger event configuration bit of line 32 1 1 RT40 Rising trigger event configuration bit of line 40 8 1 RT41 Rising trigger event configuration bit of line 41 9 1 FTSR2 FTSR2 Falling Trigger selection register 0x2C 0x20 read-write 0x00000000 FT32 Falling trigger event configuration of line 32 0 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT33 Falling trigger event configuration of line 33 1 1 FT40 Falling trigger event configuration of line 40 8 1 FT41 Falling trigger event configuration of line 41 9 1 SWIER2 SWIER2 Software interrupt event register 0x30 0x20 read-write 0x00000000 SWI32 Software interrupt on line 32 0 1 SoftwareInterrupt write Pend Generates an interrupt request 1 SWI33 Software interrupt on line 33 1 1 SWI40 Software interrupt on line 40 8 1 SWI41 Software interrupt on line 41 9 1 PR2 PR2 Pending register 0x34 0x20 read-write 0x00000000 PIF32 Pending bit 32 0 1 oneToClear PIF32R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PIF32W write Clear Clears pending bit 1 PIF33 Pending bit 33 1 1 oneToClear read write PIF40 Pending bit 40 8 1 oneToClear read write PIF41 Pending bit 41 9 1 oneToClear read write RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC_TAMP_CSS_LSE RTC_TAMP_CSS_LSE 2 RTC_WKUP RTC Wakeup timer 3 RTC_ALARM RTC_ALARM 41 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 0 15 YU Year units in BCD format 16 4 0 15 WDU Week day units 13 3 1 7 MT Month tens in BCD format 12 1 0 1 MU Month units in BCD format 8 4 0 15 DT Date tens in BCD format 4 2 0 3 DU Date units in BCD format 0 4 0 15 SSR SSR sub second register 0x8 0x20 read-only 0x00000000 SS Sub second value 0 16 0 65535 ICSR ICSR initialization and status register 0xC 0x20 0x00000007 2 0x1 A,B ALR%sWF Alarm %s write flag 0 1 read-only WUTWF Wakeup timer write flag 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending 3 1 read-write SHPFR read NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 RECALPF Recalibration pending Flag 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 0 127 PREDIV_S Synchronous prescaler factor 0 15 0 32767 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 0 65535 CR CR control register 0x18 0x20 read-write 0x00000000 WUCKSEL Wakeup clock selection 0 3 WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE Time-stamp event active edge 3 1 TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON Reference clock detection enable (50 or 60 Hz) 4 1 REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD Bypass the shadow registers 5 1 BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT Hour format 6 1 FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 2 0x1 A,B ALR%sE Alarm %s enable 8 1 ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE Wakeup timer enable 10 1 WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE Time stamp enable 11 1 TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE Wakeup timer interrupt enable 14 1 WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE Time-stamp interrupt enable 15 1 TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H Add 1 hour (summer time change) 16 1 ADD1HW write Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H Subtract 1 hour (winter time change) 17 1 SUB1HW write Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP Backup 18 1 BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 COSEL Calibration output selection 19 1 COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL Output polarity 20 1 POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL Output selection 21 2 OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE Calibration output enable 23 1 COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ITSE timestamp on internal event enable 24 1 ITSE Disabled Internal event timestamp disabled 0 Enabled Internal event timestamp enabled 1 TAMPTS TAMPTS 25 1 TAMPTS Disabled Tamper detection event does not cause a RTC timestamp to be saved 0 Enabled Save RTC timestamp on tamper detection event 1 TAMPOE TAMPOE 26 1 TAMPOE Disabled The tamper flag is not routed on TAMPALRM 0 Enabled The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL 1 TAMPALRM_PU TAMPALRM_PU 29 1 TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPALRM_TYPE TAMPALRM_TYPE 30 1 TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 OUT2EN OUT2EN 31 1 OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR calibration register 0x28 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW8 EightSeconds When CALW8 is set to â1â, the 8-second calibration cycle period is selected 1 CALW16 Use a 16-second calibration cycle period 13 1 CALW16 SixteenSeconds When CALW16 is set to â1â, the 16-second calibration cycle period is selected.This bit must not be set to â1â if CALW8=1 1 CALM Calibration minus 0 9 0 511 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 SUBFS Subtract a fraction of a second 0 15 0 32767 TSTR TSTR time stamp time register 0x30 TSDR TSDR time stamp date register 0x34 TSSSR TSSSR timestamp sub second register 0x38 2 0x8 A,B ALRM%sR ALRM%sR Alarm %s register 0x40 0x20 read-write 0x00000000 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day donât care in Alarm comparison 1 MSK4 Alarm date mask 31 1 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is donât care. 1 DT Date tens in BCD format 28 2 0 3 DU Date units or day in BCD format 24 4 0 15 MSK3 Alarm hours mask 23 1 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MSK2 Alarm minutes mask 15 1 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 2 0x8 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 0 32767 SR SR status register 0x50 0x20 read-only 0x00000000 2 0x1 A,B ALR%sF Alarm %s flag 0 1 ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 WUTF WUTF 2 1 WUTF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSF TSF 3 1 TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVF TSOVF 4 1 TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSF ITSF 5 1 ITSF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 MISR MISR status register 0x54 0x20 read-only 0x00000000 2 0x1 A,B ALR%sMF Alarm %s masked flag 0 1 ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 WUTMF WUTMF 2 1 WUTMF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSMF TSMF 3 1 TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVMF TSOVMF 4 1 TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSMF ITSMF 5 1 ITSMF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SCR SCR status register 0x5C 0x20 write-only 0x00000000 CALRAF CALRAF 0 1 CALRAF Clear Clear interrupt flag 1 CALRBF CALRBF 1 1 CWUTF CWUTF 2 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CITSF CITSF 5 1 FMC Flexible memory controller FMC 0xA0000000 0x0 0x400 registers FMC FMC 48 BCR1 BCR1 SRAM/NOR-Flash chip-select control register 1 0x0 0x20 read-write 0x000030D0 MBKEN MBKEN 0 1 MBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 MUXEN MUXEN 1 1 MUXEN Disabled Address/Data non-multiplexed 0 Enabled Address/Data multiplexed on databus 1 MTYP MTYP 2 2 MTYP SRAM SRAM memory type 0 PSRAM PSRAM (CRAM) memory type 1 Flash NOR Flash/OneNAND Flash 2 MWID MWID 4 2 MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 FACCEN FACCEN 6 1 FACCEN Disabled Corresponding NOR Flash memory access is disabled 0 Enabled Corresponding NOR Flash memory access is enabled 1 BURSTEN BURSTEN 8 1 BURSTEN Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 WAITPOL WAITPOL 9 1 WAITPOL ActiveLow NWAIT active low 0 ActiveHigh NWAIT active high 1 WAITCFG WAITCFG 11 1 WAITCFG BeforeWaitState NWAIT signal is active one data cycle before wait state 0 DuringWaitState NWAIT signal is active during wait state 1 WREN WREN 12 1 WREN Disabled Write operations disabled for the bank by the FMC 0 Enabled Write operations enabled for the bank by the FMC 1 WAITEN WAITEN 13 1 WAITEN Disabled Values inside the FMC_BWTR are taken into account 0 Enabled NWAIT signal enabled 1 EXTMOD EXTMOD 14 1 EXTMOD Disabled Values inside the FMC_BWTR are not taken into account 0 Enabled Values inside the FMC_BWTR are taken into account 1 ASYNCWAIT ASYNCWAIT 15 1 ASYNCWAIT Disabled Wait signal not used in asynchronous mode 0 Enabled Wait signal used even in asynchronous mode 1 CPSIZE CPSIZE 16 3 CPSIZE NoBurstSplit No burst split when crossing page boundary 0 Bytes128 128 bytes CRAM page size 1 Bytes256 256 bytes CRAM page size 2 Bytes512 512 bytes CRAM page size 3 Bytes1024 1024 bytes CRAM page size 4 CBURSTRW CBURSTRW 19 1 CBURSTRW Disabled Write operations are always performed in asynchronous mode 0 Enabled Write operations are performed in synchronous mode 1 CCLKEN CCLKEN 20 1 CCLKEN Disabled The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set 0 Enabled The FMC_CLK is only generated during the synchronous memory access (read/write transaction) 1 WFDIS WFDIS 21 1 WFDIS Enabled Write FIFO enabled 0 Disabled Write FIFO disabled 1 NBLSET NBLSET 22 2 4 0x8 1-4 BTR%s BTR%s SRAM/NOR-Flash chip-select timing register %s 0x4 0x20 read-write 0xFFFFFFFF DATAHLD DATAHLD 30 2 ACCMOD ACCMOD 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATLAT DATLAT 24 4 0 15 CLKDIV CLKDIV 20 4 1 15 BUSTURN BUSTURN 16 4 0 15 DATAST DATAST 8 8 1 255 ADDHLD ADDHLD 4 4 1 15 ADDSET ADDSET 0 4 0 15 3 0x8 2-4 BCR%s BCR%s SRAM/NOR-Flash chip-select control register %s 0x8 0x20 read-write 0x000030D0 MBKEN MBKEN 0 1 MUXEN MUXEN 1 1 MTYP MTYP 2 2 MWID MWID 4 2 FACCEN FACCEN 6 1 BURSTEN BURSTEN 8 1 WAITPOL WAITPOL 9 1 WAITCFG WAITCFG 11 1 WREN WREN 12 1 WAITEN WAITEN 13 1 EXTMOD EXTMOD 14 1 ASYNCWAIT ASYNCWAIT 15 1 CPSIZE CPSIZE 16 3 CBURSTRW CBURSTRW 19 1 NBLSET NBLSET 22 2 PCSCNTR PCSCNTR PSRAM chip select counter register 0x20 0x20 read-write 0x00000000 CSCOUNT CSCOUNT 0 16 4 0x1 1-4 CNTB%sEN Counter Bank %s enable 16 1 PCR PCR PC Card/NAND Flash control register 3 0x80 0x20 read-write 0x00000018 ECCPS ECCPS 17 3 ECCPS Bytes256 ECC page size 256 bytes 0 Bytes512 ECC page size 512 bytes 1 Bytes1024 ECC page size 1024 bytes 2 Bytes2048 ECC page size 2048 bytes 3 Bytes4096 ECC page size 4096 bytes 4 Bytes8192 ECC page size 8192 bytes 5 TAR TAR 13 4 0 15 TCLR TCLR 9 4 0 15 ECCEN ECCEN 6 1 ECCEN Disabled ECC logic is disabled and reset 0 Enabled ECC logic is enabled 1 PWID PWID 4 2 PWID Bits8 External memory device width 8 bits 0 Bits16 External memory device width 16 bits 1 PTYP PTYP 3 1 PTYP NANDFlash NAND Flash 1 PBKEN PBKEN 2 1 PBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 PWAITEN PWAITEN 1 1 PWAITEN Disabled Wait feature disabled 0 Enabled Wait feature enabled 1 SR SR FIFO status and interrupt register 3 0x84 0x20 0x00000040 FEMPT FEMPT 6 1 read-only FEMPT NotEmpty FIFO not empty 0 Empty FIFO empty 1 IFEN IFEN 5 1 read-write IFEN Disabled Interrupt falling edge detection request disabled 0 Enabled Interrupt falling edge detection request enabled 1 ILEN ILEN 4 1 read-write ILEN Disabled Interrupt high-level detection request disabled 0 Enabled Interrupt high-level detection request enabled 1 IREN IREN 3 1 read-write IREN Disabled Interrupt rising edge detection request disabled 0 Enabled Interrupt rising edge detection request enabled 1 IFS IFS 2 1 read-write IFS DidNotOccur Interrupt falling edge did not occur 0 Occurred Interrupt falling edge occurred 1 ILS ILS 1 1 read-write ILS DidNotOccur Interrupt high-level did not occur 0 Occurred Interrupt high-level occurred 1 IRS IRS 0 1 read-write IRS DidNotOccur Interrupt rising edge did not occur 0 Occurred Interrupt rising edge occurred 1 PMEM PMEM Common memory space timing register 3 0x88 0x20 read-write 0xFCFCFCFC MEMHIZ MEMHIZx 24 8 0 254 MEMHOLD MEMHOLDx 16 8 1 254 MEMWAIT MEMWAITx 8 8 1 254 MEMSET MEMSETx 0 8 0 254 PATT PATT Attribute memory space timing register 3 0x8C 0x20 read-write 0xFCFCFCFC ATTHIZ ATTHIZx 24 8 0 254 ATTHOLD ATTHOLDx 16 8 1 254 ATTWAIT ATTWAITx 8 8 1 254 ATTSET ATTSETx 0 8 0 254 ECCR ECCR ECC result register 3 0x94 0x20 read-only 0x00000000 ECC ECCx 0 32 0 4294967295 4 0x8 1-4 BWTR%s BWTR%s SRAM/NOR-Flash write timing registers %s 0x104 0x20 read-write 0x0FFFFFFF DATAHLD DATAHLD 30 2 ACCMOD ACCMOD 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 BUSTURN BUSTURN 16 4 0 15 DATAST DATAST 8 8 1 255 ADDHLD ADDHLD 4 4 1 15 ADDSET ADDSET 0 4 0 15 DMA1 DMA controller DMA 0x40020000 0x0 0x400 registers DMA1_CH1 DMA1 channel 1 interrupt 11 DMA1_CH2 DMA1 channel 2 interrupt 12 DMA1_CH3 DMA1 channel 3 interrupt 13 DMA1_CH4 DMA1 channel 4 interrupt 14 DMA1_CH5 DMA1 channel 5 interrupt 15 DMA1_CH6 DMA1 channel 6 interrupt 16 DMA1_CH8 DMA1_CH8 96 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 8 0x4 1-8 TEIF%s Channel %s Transfer Error flag 3 1 TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 8 0x4 1-8 HTIF%s Channel %s Half Transfer Complete flag 2 1 HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 8 0x4 1-8 TCIF%s Channel %s Transfer Complete flag 1 1 TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 8 0x4 1-8 GIF%s Channel %s Global interrupt flag 0 1 GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 IFCR IFCR DMA interrupt flag clear register 0x4 0x20 write-only 0x00000000 8 0x4 1-8 CTEIF%s Channel %s Transfer Error clear 3 1 CTEIF1 Clear Clears the TEIF flag in the ISR register 1 8 0x4 1-8 CHTIF%s Channel %s Half Transfer clear 2 1 CHTIF1 Clear Clears the HTIF flag in the ISR register 1 8 0x4 1-8 CTCIF%s Channel %s Transfer Complete clear 1 1 CTCIF1 Clear Clears the TCIF flag in the ISR register 1 8 0x4 1-8 CGIF%s Channel %s Global interrupt clear 0 1 CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 8 0x14 1-8 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8 CR CCR1 DMA channel 1 configuration register 0x0 0x20 read-write 0x00000000 EN channel enable 0 1 EN Disabled Channel disabled 0 Enabled Channel enabled 1 TCIE TCIE 1 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 HTIE HTIE 2 1 HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TEIE TEIE 3 1 TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 DIR DIR 4 1 DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 CIRC CIRC 5 1 CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 PINC PINC 6 1 PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC MINC 7 1 PSIZE PSIZE 8 2 PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE MSIZE 10 2 PL PL 12 2 PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 MEM2MEM MEM2MEM 14 1 MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 NDTR CNDTR1 channel x number of data to transfer register 0x4 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 0 65535 PAR CPAR1 DMA channel x peripheral address register 0x8 0x20 read-write 0x00000000 PA Peripheral address 0 32 MAR CMAR1 DMA channel x memory address register 0xC 0x20 read-write 0x00000000 MA Memory 1 address (used in case of Double buffer mode) 0 32 DMA2 0x40020400 DMA1_CH7 DMA1 channel 7 interrupt 17 DMA2_CH1 DMA2_CH1 56 DMA2_CH2 DMA2_CH2 57 DMA2_CH3 DMA2_CH3 58 DMA2_CH4 DMA2_CH4 59 DMA2_CH5 DMA2_CH5 60 DMA2_CH6 DMA2_CH6 97 DMA2_CH7 DMA2_CH7 98 DMA2_CH8 DMA2_CH8 99 DMAMUX DMAMUX DMAMUX 0x40020800 0x0 0x400 registers DMAMUX_OVR DMAMUX_OVR 94 16 0x4 0-15 CCR%s C%sCR DMA Multiplexer Channel %s Control register 0x0 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 SOIE Disabled Synchronization overrun interrupt disabled 0 Enabled Synchronization overrun interrupt enabled 1 EGE Event generation enable/disable 9 1 EGE Disabled Event generation disabled 0 Enabled Event generation enabled 1 SE Synchronous operating mode enable/disable 16 1 SE Disabled Synchronization disabled 0 Enabled Synchronization enabled 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SPOL NoEdge No event, i.e. no synchronization nor detection 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 0 31 SYNC_ID Synchronization input selected 24 5 4 0x4 0-3 RGCR%s RG%sCR DMAMux - DMA request generator channel x control register 0x100 0x20 read-write 0x00000000 SIG_ID DMA request trigger input selected 0 5 OIE Interrupt enable at trigger event overrun 8 1 OIE Disabled Trigger overrun interrupt disabled 0 Enabled Trigger overrun interrupt enabled 1 GE DMA request generator channel enable/disable 16 1 GE Disabled DMA request generation disabled 0 Enabled DMA request enabled 1 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 GPOL NoEdge No event, i.e. no detection nor generation 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 0 31 RGSR RGSR DMAMux - DMA request generator status register 0x140 0x20 read-only 0x00000000 4 0x1 0-3 OF%s Generator Overrun Flag %s 0 1 OF0 NoTrigger No new trigger event occured on DMA request generator channel x, before the request counter underrun 0 Trigger New trigger event occured on DMA request generator channel x, before the request counter underrun 1 RGCFR RGCFR DMAMux - DMA request generator clear flag register 0x144 0x20 write-only 0x00000000 4 0x1 0-3 COF%s Generator Clear Overrun Flag %s 0 1 oneToClear COF0W Clear Clear overrun flag 1 CSR CSR DMAMUX request line multiplexer interrupt channel status register 0x80 0x20 read-only 0x00000000 16 0x1 0-15 SOF%s Synchronization Overrun Flag %s 0 1 SOF0 NoSyncEvent No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 0 SyncEvent Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 1 CFR CFR DMAMUX request line multiplexer interrupt clear flag register 0x84 0x20 write-only 0x00000000 16 0x1 0-15 CSOF%s Synchronization Clear Overrun Flag %s 0 1 oneToClear CSOF0W Clear Clear synchronization flag 1 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x2A registers MEMRMP MEMRMP Remap Memory register 0x0 0x20 read-write 0x00000000 MEM_MODE Memory mapping selection 0 3 FB_mode User Flash Bank mode 8 1 CFGR1 CFGR1 peripheral mode configuration register 0x4 0x20 read-write 0x7C000001 BOOSTEN BOOSTEN 8 1 ANASWVDD GPIO analog switch control voltage selection 9 1 I2C_PB6_FMP FM+ drive capability on PB6 16 1 I2C_PB7_FMP FM+ drive capability on PB6 17 1 I2C_PB8_FMP FM+ drive capability on PB6 18 1 I2C_PB9_FMP FM+ drive capability on PB6 19 1 I2C1_FMP I2C1 FM+ drive capability enable 20 1 I2C2_FMP I2C1 FM+ drive capability enable 21 1 I2C3_FMP I2C1 FM+ drive capability enable 22 1 I2C4_FMP I2C1 FM+ drive capability enable 23 1 FPU_IE FPU Interrupts Enable 26 6 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x00000000 EXTI3 EXTI x configuration (x = 0 to 3) 12 4 EXTI2 EXTI x configuration (x = 0 to 3) 8 4 EXTI1 EXTI x configuration (x = 0 to 3) 4 4 EXTI0 EXTI x configuration (x = 0 to 3) 0 4 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x00000000 EXTI7 EXTI x configuration (x = 4 to 7) 12 4 EXTI6 EXTI x configuration (x = 4 to 7) 8 4 EXTI5 EXTI x configuration (x = 4 to 7) 4 4 EXTI4 EXTI x configuration (x = 4 to 7) 0 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x00000000 EXTI11 EXTI x configuration (x = 8 to 11) 12 4 EXTI10 EXTI10 8 4 EXTI9 EXTI x configuration (x = 8 to 11) 4 4 EXTI8 EXTI x configuration (x = 8 to 11) 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x00000000 EXTI15 EXTI x configuration (x = 12 to 15) 12 4 EXTI14 EXTI x configuration (x = 12 to 15) 8 4 EXTI13 EXTI x configuration (x = 12 to 15) 4 4 EXTI12 EXTI x configuration (x = 12 to 15) 0 4 SCSR SCSR CCM SRAM control and status register 0x18 0x20 0x00000000 CCMER CCM SRAM Erase 0 1 read-write CCMBSY CCM SRAM busy by erase operation 1 1 read-only CFGR2 CFGR2 configuration register 2 0x1C 0x20 read-write 0x00000000 CLL Core Lockup Lock 0 1 SPL SRAM Parity Lock 1 1 PVDL PVD Lock 2 1 ECCL ECC Lock 3 1 SPF SRAM Parity Flag 8 1 SWPR SWPR SRAM Write protection register 1 0x20 0x20 read-write 0x00000000 Page0_WP Write protection 0 1 Page1_WP Write protection 1 1 Page2_WP Write protection 2 1 Page3_WP Write protection 3 1 Page4_WP Write protection 4 1 Page5_WP Write protection 5 1 Page6_WP Write protection 6 1 Page7_WP Write protection 7 1 Page8_WP Write protection 8 1 Page9_WP Write protection 9 1 Page10_WP Write protection 10 1 Page11_WP Write protection 11 1 Page12_WP Write protection 12 1 Page13_WP Write protection 13 1 Page14_WP Write protection 14 1 Page15_WP Write protection 15 1 Page16_WP Write protection 16 1 Page17_WP Write protection 17 1 Page18_WP Write protection 18 1 Page19_WP Write protection 19 1 Page20_WP Write protection 20 1 Page21_WP Write protection 21 1 Page22_WP Write protection 22 1 Page23_WP Write protection 23 1 Page24_WP Write protection 24 1 Page25_WP Write protection 25 1 Page26_WP Write protection 26 1 Page27_WP Write protection 27 1 Page28_WP Write protection 28 1 Page29_WP Write protection 29 1 Page30_WP Write protection 30 1 Page31_WP Write protection 31 1 SKR SKR SRAM2 Key Register 0x24 0x20 write-only 0x00000000 KEY SRAM2 Key for software erase 0 8 VREFBUF Voltage reference buffer VREFBUF 0x40010030 0x0 0x1D0 registers CSR CSR VREF_BUF Control and Status Register 0x0 0x20 0x00000002 ENVR Enable Voltage Reference 0 1 read-write HIZ High impedence mode for the VREF_BUF 1 1 read-write VRR Voltage reference buffer ready 3 1 read-only VRS Voltage reference scale 4 2 read-write CCR CCR VREF_BUF Calibration Control Register 0x4 0x20 read-write 0x00000000 TRIM Trimming code 0 6 COMP Comparator control and status register COMP 0x40010200 0x0 0x100 registers COMP1_2_3 COMP1_2_3 64 COMP4_5_6 COMP4_5_6 65 COMP7 COMP7 66 7 0x4 1-7 C%sCSR C%sCSR Comparator control/status register 0x0 0x20 0x00000000 EN EN 0 1 read-write INMSEL INMSEL 4 3 read-write INPSEL INPSEL 8 1 read-write POL POL 15 1 read-write HYST HYST 16 3 read-write BLANKSEL BLANKSEL 19 3 read-write BRGEN BRGEN 22 1 read-write SCALEN SCALEN 23 1 read-write VALUE VALUE 30 1 read-only LOCK LOCK 31 1 read-write OPAMP Operational amplifiers OPAMP 0x40010300 0x0 0x100 registers OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 OPAEN Disabled OpAmp disabled 0 Enabled OpAmp enabled 1 FORCE_VP FORCE_VP 1 1 FORCE_VP Normal Non-inverting input connected configured inputs 0 CalibrationVerification Non-inverting input connected to calibration reference voltage 1 VP_SEL VP_SEL 2 2 VP_SEL VINP0 VINP0 connected to VINP input 0 VINP1 VINP1 connected to VINP input 1 VINP2 VINP2 connected to VINP input 2 DAC3_CH1 DAC3_CH1 connected to VINP input 3 USERTRIM USERTRIM 4 1 USERTRIM Factory Factory trim used 0 User User trim used 1 VM_SEL VM_SEL 5 2 VM_SEL VINM0 VINM0 connected to VINM input 0 VINM1 VINM1 connected to VINM input 1 PGA Feedback resistor connected to VINM (PGA mode) 2 Output OpAmp output connected to VINM (Follower mode) 3 OPAHSM OPAHSM 7 1 OPAHSM Normal OpAmp in normal mode 0 HighSpeed OpAmp in high speed mode 1 OPAINTOEN OPAINTOEN 8 1 OPAINTOEN OutputPin Output is connected to the output Pin 0 ADCChannel Output is connected internally to ADC channel 1 CALON CALON 11 1 CALON Disabled Calibration mode disabled 0 Enabled Calibration mode enabled 1 CALSEL CALSEL 12 2 CALSEL Percent3_3 0.033*VDDA applied to OPAMP inputs during calibration 0 Percent10 0.1*VDDA applied to OPAMP inputs during calibration 1 Percent50 0.5*VDDA applied to OPAMP inputs during calibration 2 Percent90 0.9*VDDA applied to OPAMP inputs during calibration 3 PGA_GAIN PGA_GAIN 14 5 PGA_GAIN Gain2 Gain 2 0 Gain4 Gain 4 1 Gain8 Gain 8 2 Gain16 Gain 16 3 Gain32 Gain 32 4 Gain64 Gain 64 5 Gain2_InputVINM0 Gain 2, input/bias connected to VINM0 or inverting gain 8 Gain4_InputVINM0 Gain 4, input/bias connected to VINM0 or inverting gain 9 Gain8_InputVINM0 Gain 8, input/bias connected to VINM0 or inverting gain 10 Gain16_InputVINM0 Gain 16, input/bias connected to VINM0 or inverting gain 11 Gain32_InputVINM0 Gain 32, input/bias connected to VINM0 or inverting gain 12 Gain64_InputVINM0 Gain 64, input/bias connected to VINM0 or inverting gain 13 Gain2_FilteringVINM0 Gain 2, with filtering on VINM0 16 Gain4_FilteringVINM0 Gain 4, with filtering on VINM0 17 Gain8_FilteringVINM0 Gain 8, with filtering on VINM0 18 Gain16_FilteringVINM0 Gain 16, with filtering on VINM0 19 Gain32_FilteringVINM0 Gain 32, with filtering on VINM0 20 Gain64_FilteringVINM0 Gain 64, with filtering on VINM0 21 Gain2_InputVINM0FilteringVINM1 Gain 2, input/bias connected to VINM0 with filtering on VINM1 or inverting gain 24 Gain4_InputVINM0FilteringVINM1 Gain 4, input/bias connected to VINM0 with filtering on VINM1 or inverting gain 25 Gain8_InputVINM0FilteringVINM1 Gain 8, input/bias connected to VINM0 with filtering on VINM1 or inverting gain 26 Gain16_InputVINM0FilteringVINM1 Gain 16, input/bias connected to VINM0 with filtering on VINM1 or inverting gain 27 Gain32_InputVINM0FilteringVINM1 Gain 32, input/bias connected to VINM0 with filtering on VINM1 or inverting gain 28 Gain64_InputVINM0FilteringVINM1 Gain 64, input/bias connected to VINM0 with filtering on VINM1 or inverting gain 29 TRIMOFFSETP TRIMOFFSETP 19 5 0 31 TRIMOFFSETN TRIMOFFSETN 24 5 0 31 CALOUT CALOUT 30 1 0 1 LOCK LOCK 31 1 LOCK ReadWrite CSR is read-write 0 ReadOnly CSR is read-only, can only be cleared by system reset 1 OPAMP2_CSR OPAMP2_CSR OPAMP2 control/status register 0x4 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 FORCE_VP FORCE_VP 1 1 VP_SEL VP_SEL 2 2 VP_SEL VINP0 VINP0 connected to VINP input 0 VINP1 VINP1 connected to VINP input 1 VINP2 VINP2 connected to VINP input 2 VINP3 VINP3 connected to VINP input 3 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 CALON CALON 11 1 CALSEL CALSEL 12 2 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETP TRIMOFFSETP 19 5 TRIMOFFSETN TRIMOFFSETN 24 5 CALOUT CALOUT 30 1 LOCK LOCK 31 1 OPAMP3_CSR OPAMP3_CSR OPAMP3 control/status register 0x8 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 FORCE_VP FORCE_VP 1 1 VP_SEL VP_SEL 2 2 VP_SEL VINP0 VINP0 connected to VINP input 0 VINP1 VINP1 connected to VINP input 1 VINP2 VINP2 connected to VINP input 2 DAC3_CH2 DAC3_CH2 connected to VINP input 3 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 CALON CALON 11 1 CALSEL CALSEL 12 2 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETP TRIMOFFSETP 19 5 TRIMOFFSETN TRIMOFFSETN 24 5 CALOUT CALOUT 30 1 LOCK LOCK 31 1 OPAMP4_CSR OPAMP4_CSR OPAMP4 control/status register 0xC 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 FORCE_VP FORCE_VP 1 1 VP_SEL VP_SEL 2 2 VP_SEL VINP0 VINP0 connected to VINP input 0 VINP1 VINP1 connected to VINP input 1 VINP2 VINP2 connected to VINP input 2 DAC4_CH1 DAC4_CH1 connected to VINP input 3 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 CALON CALON 11 1 CALSEL CALSEL 12 2 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETP TRIMOFFSETP 19 5 TRIMOFFSETN TRIMOFFSETN 24 5 CALOUT CALOUT 30 1 LOCK LOCK 31 1 OPAMP5_CSR OPAMP5_CSR OPAMP5 control/status register 0x10 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 FORCE_VP FORCE_VP 1 1 VP_SEL VP_SEL 2 2 VP_SEL VINP0 VINP0 connected to VINP input 0 VINP1 VINP1 connected to VINP input 1 VINP2 VINP2 connected to VINP input 2 DAC4_CH2 DAC4_CH2 connected to VINP input 3 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 CALON CALON 11 1 CALSEL CALSEL 12 2 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETP TRIMOFFSETP 19 5 TRIMOFFSETN TRIMOFFSETN 24 5 CALOUT CALOUT 30 1 LOCK LOCK 31 1 OPAMP6_CSR OPAMP6_CSR OPAMP6 control/status register 0x14 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 FORCE_VP FORCE_VP 1 1 VP_SEL VP_SEL 2 2 VP_SEL VINP0 VINP0 connected to VINP input 0 VINP1 VINP1 connected to VINP input 1 VINP2 VINP2 connected to VINP input 2 DAC3_CH1 DAC3_CH1 connected to VINP input 3 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 CALON CALON 11 1 CALSEL CALSEL 12 2 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETP TRIMOFFSETP 19 5 TRIMOFFSETN TRIMOFFSETN 24 5 CALOUT CALOUT 30 1 LOCK LOCK 31 1 OPAMP1_TCMR OPAMP1_TCMR OPAMP1 control/status register 0x18 0x20 read-write 0x00000000 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 T1CM_EN T1CM_EN 3 1 T1CM_EN Disabled Automatic input switch triggered by TIM1 disabled 0 Enabled Automatic input switch triggered by TIM1 enabled 1 T8CM_EN T8CM_EN 4 1 T8CM_EN Disabled Automatic input switch triggered by TIM8 disabled 0 Enabled Automatic input switch triggered by TIM8 enabled 1 T20CM_EN T20CM_EN 5 1 T20CM_EN Disabled Automatic input switch triggered by TIM20 disabled 0 Enabled Automatic input switch triggered by TIM20 enabled 1 LOCK LOCK 31 1 LOCK ReadWrite TCMR is read-write 0 ReadOnly TCMR is read-only, can only be cleared by system reset 1 OPAMP2_TCMR OPAMP2_TCMR OPAMP2 control/status register 0x1C 0x20 read-write 0x00000000 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 T1CM_EN T1CM_EN 3 1 T8CM_EN T8CM_EN 4 1 T20CM_EN T20CM_EN 5 1 LOCK LOCK 31 1 OPAMP3_TCMR OPAMP3_TCMR OPAMP3 control/status register 0x20 0x20 read-write 0x00000000 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 T1CM_EN T1CM_EN 3 1 T8CM_EN T8CM_EN 4 1 T20CM_EN T20CM_EN 5 1 LOCK LOCK 31 1 OPAMP4_TCMR OPAMP4_TCMR OPAMP4 control/status register 0x24 0x20 read-write 0x00000000 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 T1CM_EN T1CM_EN 3 1 T8CM_EN T8CM_EN 4 1 T20CM_EN T20CM_EN 5 1 LOCK LOCK 31 1 OPAMP5_TCMR OPAMP5_TCMR OPAMP5 control/status register 0x28 0x20 read-write 0x00000000 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 T1CM_EN T1CM_EN 3 1 T8CM_EN T8CM_EN 4 1 T20CM_EN T20CM_EN 5 1 LOCK LOCK 31 1 OPAMP6_TCMR OPAMP6_TCMR OPAMP6 control/status register 0x2C 0x20 read-write 0x00000000 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 T1CM_EN T1CM_EN 3 1 T8CM_EN T8CM_EN 4 1 T20CM_EN T20CM_EN 5 1 LOCK LOCK 31 1 HRTIM_Master High Resolution Timer: Master Timers HRTIM 0x40016800 0x0 0x80 registers HRTIM_Master_IRQn HRTIM_Master_IRQn 67 CR CR Master Timer Control Register 0x0 0x20 read-write 0x00000000 BRSTDMA Burst DMA Update 30 2 BRSTDMA Independent Update done independently from the DMA burst transfer completion 0 Completion Update done when the DMA burst transfer is completed 1 Rollover Update done on master timer roll-over following a DMA burst transfer completion 2 MREPU Master Timer Repetition update 29 1 MREPU Disabled Update on repetition disabled 0 Enabled Update on repetition enabled 1 PREEN Preload enable 27 1 PREEN Disabled Preload disabled: the write access is directly done into the active register 0 Enabled Preload enabled: the write access is done into the preload register 1 DACSYNC AC Synchronization 25 2 DACSYNC Disabled No DAC trigger generated 0 DACSync1 Trigger generated on DACSync1 1 DACSync2 Trigger generated on DACSync2 2 DACSync3 Trigger generated on DACSync3 3 6 0x1 A,B,C,D,E,F T%sCEN Timer %s counter enable 17 1 TACEN Disabled Timer counter disabled 0 Enabled Timer counter enabled 1 MCEN Master Counter enable 16 1 MCEN Disabled Master timer counter disabled 0 Enabled Master timer counter enabled 1 SYNCSRC Synchronization source 14 2 SYNCSRC MasterStart Master timer Start 0 MasterCompare1 Master timer Compare 1 event 1 TimerAStart Timer A start/reset 2 TimerACompare1 Timer A Compare 1 event 3 SYNCOUT Synchronization output 12 2 SYNCOUT Disabled Disabled 0 PositivePulse Positive pulse on SCOUT output (16x f_HRTIM clock cycles) 2 NegativePulse Negative pulse on SCOUT output (16x f_HRTIM clock cycles) 3 SYNCSTRT Synchronization Starts Master 11 1 SYNCSTRT Disabled No effect on the master timer 0 Start A synchroniation input event starts the master timer 1 SYNCRST Synchronization Resets Master 10 1 SYNCRST Disabled No effect on the master timer 0 Reset A synchroniation input event resets the master timer 1 SYNCIN synchronization input 8 2 SYNCIN Disabled Disabled. HRTIM is not synchronized and runs in standalone mode 0 Internal Internal event: the HRTIM is synchronized with the on-chip timer 2 External External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM 3 INTLVD Interleaved mode 6 2 HALF Half mode enable 5 1 HALF Disabled Half mode disabled 0 Enabled Half mode enabled 1 RETRIG Master Re-triggerable mode 4 1 RETRIG Disabled The timer is not re-triggerable: a counter reset can be done only if the counter is stopped 0 Enabled The timer is retriggerable: a counter reset is done whatever the counter state 1 CONT Master Continuous mode 3 1 CONT SingleShot The timer operates in single-shot mode and stops when it reaches the MPER value 0 Continuous The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value 1 CKPSC HRTIM Master Clock prescaler 0 3 0 7 ISR ISR Master Timer Interrupt Status Register 0x4 0x20 read-only 0x00000000 UPD Master Update Interrupt Flag 6 1 UPD NoEvent No timer update interrupt occurred 0 Event Timer update interrupt occurred 1 SYNC Sync Input Interrupt Flag 5 1 SYNC NoEvent No sync input interrupt occurred 0 Event Sync input interrupt occurred 1 REP Master Repetition Interrupt Flag 4 1 REP NoEvent No timer repetition interrupt occurred 0 Event Timer repetition interrupt occurred 1 4 0x1 1-4 CMP%s Master Compare %s Interrupt Flag 0 1 CMP1 NoEvent No compare interrupt occurred 0 Event Compare interrupt occurred 1 ICR ICR Master Timer Interrupt Clear Register 0x8 0x20 write-only 0x00000000 4 0x1 1-4 CMP%sC Master Compare %s Interrupt flag clear 0 1 oneToClear CMP1CW Clear Clears associated flag in ISR register 1 UPDC Master update Interrupt flag clear 6 1 oneToClear SYNCC Sync Input Interrupt flag clear 5 1 oneToClear REPC Repetition Interrupt flag clear 4 1 oneToClear DIER DIER HRTIM Master Timer DMA / Interrupt Enable Register 0xC 0x20 read-write 0x00000000 4 0x1 1-4 CMP%sDE MCMP%sDE 16 1 CMP1DE Disabled DMA request disabled 0 Enabled DMA request enabled 1 UPDDE MUPDDE 22 1 SYNCDE SYNCDE 21 1 REPDE MREPDE 20 1 4 0x1 1-4 CMP%sIE MCMP%sIE 0 1 CMP1IE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 UPDIE MUPDIE 6 1 SYNCIE SYNCIE 5 1 REPIE MREPIE 4 1 CNTR CNTR Master Timer Counter Register 0x10 0x20 read-write 0x00000000 CNT Counter value 0 16 0 65535 PERR PER Master Timer Period Register 0x14 0x20 read-write 0x0000FFFF PER Master Timer Period value 0 16 0 65535 REPR REP Master Timer Repetition Register 0x18 0x20 read-write 0x00000000 REP Master Timer Repetition counter value 0 8 0 255 CMP1R CMP1R Master Timer Compare 1 Register 0x1C 0x20 read-write 0x00000000 CMP Master Timer Compare 1 value 0 16 0 65535 CMP2R CMP2R Master Timer Compare 2 Register 0x24 CMP3R CMP3R Master Timer Compare 3 Register 0x28 CMP4R CMP4R Master Timer Compare 4 Register 0x2C HRTIM_TIMA High Resolution Timer: TIMA HRTIM 0x40016880 0x0 0x80 registers HRTIM_TIMA_IRQn HRTIM_TIMA_IRQn 68 CR ACR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 UPDGAT Independent Update occurs independently from the DMA burst transfer 0 DMABurst Update occurs when the DMA burst transfer is completed 1 DMABurst_Update Update occurs on the update event following DMA burst transfer completion 2 Input1 Update occurs on a rising edge of HRTIM update enable input 1 3 Input2 Update occurs on a rising edge of HRTIM update enable input 2 4 Input3 Update occurs on a rising edge of HRTIM update enable input 3 5 Input1_Update Update occurs on the update event following a rising edge of HRTIM update enable input 1 6 Input2_Update Update occurs on the update event following a rising edge of HRTIM update enable input 2 7 Input3_Update Update occurs on the update event following a rising edge of HRTIM update enable input 3 8 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 MSTU Disabled Update by master timer disabled 0 Enabled Update by master timer enabled 1 TFU TFU 16 1 TFU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TBU TBU 20 1 TRSTU Timerx reset update 18 1 TRSTU Disabled Update by timer x reset/roll-over disabled 0 Enabled Update by timer x reset/roll-over enabled 1 TREPU Timer x Repetition update 17 1 TREPU Disabled Update by timer x repetition disabled 0 Enabled Update by timer x repetition enabled 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP4 Standard CMP4 register is always active (standard compare mode) 0 Capture2 CMP4 is recomputed and is active following a capture 2 event 1 Capture2_Compare1 CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match 2 Capture_Compare3 CMP4 is recomputed and is active following a capture event or a Compare 3 match 3 DELCMP2 Delayed CMP2 mode 12 2 DELCMP2 Standard CMP2 register is always active (standard compare mode) 0 Capture1 CMP2 is recomputed and is active following a capture 1 event 1 Capture1_Compare1 CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match 2 Capture1_Compare3 CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match 3 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 RSYNCU Re-Synchronized Update 9 1 INTLVD Interleaved mode 7 2 PSHPLL Push-Pull mode enable 6 1 PSHPLL Disabled Push-pull mode disabled 0 Enabled Push-pull mode enabled 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR AISR Timerx Interrupt Status Register 0x4 0x20 read-only 0x00000000 O1CPY Output 1 Copy 20 1 O1CPY Inactive Output is inactive 0 Active Output is active 1 O2CPY Output 2 Copy 21 1 O1STAT Output 1 State 18 1 O1STAT Inactive Output was inactive 0 Active Output was active 1 O2STAT Output 2 State 19 1 IPPSTAT Idle Push Pull Status 17 1 IPPSTAT Output1Active Protection occurred when the output 1 was active and output 2 forced inactive 0 Output2Active Protection occurred when the output 2 was active and output 1 forced inactive 1 CPPSTAT Current Push Pull Status 16 1 CPPSTAT Output1Active Signal applied on output 1 and output 2 forced inactive 0 Output2Active Signal applied on output 2 and output 1 forced inactive 1 DLYPRT Delayed Protection Flag 14 1 DLYPRT Inactive Not in delayed idle or balanced idle mode 0 Active Delayed idle or balanced idle mode entry 1 RST Reset Interrupt Flag 13 1 RST NoEvent No TIMx counter reset/roll-over interrupt occurred 0 Event TIMx counter reset/roll-over interrupt occurred 1 RST1 Output 1 Reset Interrupt Flag 10 1 RST1 NoEvent No Tx output reset interrupt occurred 0 Event Tx output reset interrupt occurred 1 RST2 Output 2 Reset Interrupt Flag 12 1 2 0x2 1-2 SET%s Output %s Set Interrupt Flag 9 1 SET1 NoEvent No Tx output set interrupt occurred 0 Event Tx output set interrupt occurred 1 2 0x1 1-2 CPT%s Capture%s Interrupt Flag 7 1 CPT1 NoEvent No timer x capture reset interrupt occurred 0 Event Timer x capture reset interrupt occurred 1 UPD Update Interrupt Flag 6 1 REP Repetition Interrupt Flag 4 1 4 0x1 1-4 CMP%s Compare %s Interrupt Flag 0 1 ICR AICR Timerx Interrupt Clear Register 0x8 0x20 write-only 0x00000000 4 0x1 1-4 CMP%sC Compare %s Interrupt flag Clear 0 1 DLYPRTC Delayed Protection Flag Clear 14 1 RSTC Reset Interrupt flag Clear 13 1 RST2C Output 2 Reset flag Clear 12 1 2 0x2 1-2 SET%sC Output %s Set flag Clear 9 1 RST1C Output 1 Reset flag Clear 10 1 2 0x1 1-2 CPT%sC Capture%s Interrupt flag Clear 7 1 UPDC Update Interrupt flag Clear 6 1 REPC Repetition Interrupt flag Clear 4 1 DIER ADIER TIMxDIER 0xC 0x20 read-write 0x00000000 4 0x1 1-4 CMP%sDE CMP%sDE 16 1 DLYPRTDE DLYPRTDE 30 1 RSTDE RSTDE 29 1 RST2DE RSTx2DE 28 1 2 0x2 1-2 SET%sDE Output %s set DMA request enable 25 1 RST1DE RSTx1DE 26 1 2 0x1 1-2 CPT%sDE CPT%sDE 23 1 UPDDE UPDDE 22 1 REPDE REPDE 20 1 4 0x1 1-4 CMP%sIE CMP%sIE 0 1 DLYPRTIE DLYPRTIE 14 1 RSTIE RSTIE 13 1 RST2IE RSTx2IE 12 1 2 0x2 1-2 SET%sIE Output %s set interrupt enable 9 1 RST1IE RSTx1IE 10 1 2 0x1 1-2 CPT%sIE CPT%sIE 7 1 UPDIE UPDIE 6 1 REPIE REPIE 4 1 CNTR CNTAR Timerx Counter Register 0x10 PERR PERAR Timerx Period Register 0x14 REPR REPAR Timerx Repetition Register 0x18 CMP1R CMP1AR Timerx Compare 1 Register 0x1C CMP1CR CMP1CAR Timerx Compare 1 Compound Register 0x20 0x20 read-write 0x00000000 REP Timerx Repetition value (aliased from HRTIM_REPx register) 16 8 0 255 CMP1 Timerx Compare 1 value 0 16 0 65535 CMP2R CMP2AR Timerx Compare 2 Register 0x24 CMP3R CMP3AR Timerx Compare 3 Register 0x28 CMP4R CMP4AR Timerx Compare 4 Register 0x2C CPT1R CPT1AR Timerx Capture 1 Register 0x30 0x20 read-only 0x00000000 CPT Timerx Capture 1 value 0 16 0 65535 DIR Timerx Capture 1 Direction status 16 1 CPT2R CPT2AR Timerx Capture 2 Register 0x34 DTR DTAR Timerx Deadtime Register 0x38 0x20 read-write 0x00000000 DTFLK Deadtime Falling Lock 31 1 DTFLK Unlocked Deadtime falling value and sign is writable 0 Locked Deadtime falling value and sign is read-only 1 DTFSLK Deadtime Falling Sign Lock 30 1 DTFSLK Unlocked Deadtime falling sign is writable 0 Locked Deadtime falling sign is read-only 1 SDTF Sign Deadtime Falling value 25 1 SDTF Positive Positive deadtime on falling edge 0 Negative Negative deadtime on falling edge 1 DTF Deadtime Falling value 16 9 0 511 DTRLK Deadtime Rising Lock 15 1 DTRLK Unlocked Deadtime rising value and sign is writable 0 Locked Deadtime rising value and sign is read-only 1 DTRSLK Deadtime Rising Sign Lock 14 1 DTRSLK Unlocked Deadtime rising sign is writable 0 Locked Deadtime rising sign is read-only 1 DTPRSC Deadtime Prescaler 10 3 0 7 SDTR Sign Deadtime Rising value 9 1 SDTR Positive Positive deadtime on rising edge 0 Negative Negative deadtime on rising edge 1 DTR Deadtime Rising value 0 9 0 511 SET1R SETA1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 UPDATE NoEffect Register update event has no effect 0 SetActive Register update event forces the output to its active state 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 EXTEVNT1 NoEffect External event has no effect 0 SetActive External event forces the output to its active state 1 TIMBCMP1 Timer B Compare 1 12 1 TIMBCMP1 NoEffect Timer event has no effect 0 SetActive Timer event forces the output to its active state 1 TIMFCMP4 Timer F Compare 4 20 1 TIMECMP4 Timer E Compare 4 19 1 TIMECMP3 Timer E Compare 3 18 1 TIMDCMP2 Timer D Compare 2 17 1 TIMDCMP1 Timer D Compare 1 16 1 TIMCCMP3 Timer C Compare 3 15 1 TIMCCMP2 Timer C Compare 2 14 1 TIMBCMP2 Timer B Compare 2 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTCMP1 NoEffect Master timer compare event has no effect 0 SetActive Master timer compare event forces the output to its active state 1 MSTPER Master Period 7 1 MSTPER NoEffect Master timer counter roll-over/reset has no effect 0 SetActive Master timer counter roll-over/reset forces the output to its active state 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 CMP1 NoEffect Timer compare event has no effect 0 SetActive Timer compare event forces the output to its active state 1 PER Timer A Period 2 1 PER NoEffect Timer period event has no effect 0 SetActive Timer period event forces the output to its active state 1 RESYNC Timer A resynchronizaton 1 1 RESYNC NoEffect Timer reset event coming solely from software or SYNC input event has no effect 0 SetActive Timer reset event coming solely from software or SYNC input event forces the output to its active state 1 SST Software Set trigger 0 1 SST NoEffect No effect 0 SetActive Force output to its active state 1 RST1R RSTA1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 UPDATE NoEffect Register update event has no effect 0 SetInactive Register update event forces the output to its inactive state 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 EXTEVNT1 NoEffect External event has no effect 0 SetInactive External event forces the output to its inactive state 1 TIMBCMP1 Timer B Compare 1 12 1 TIMBCMP1 NoEffect Timer event has no effect 0 SetInactive Timer event forces the output to its inactive state 1 TIMFCMP4 Timer F Compare 4 20 1 TIMECMP4 Timer E Compare 4 19 1 TIMECMP3 Timer E Compare 3 18 1 TIMDCMP2 Timer D Compare 2 17 1 TIMDCMP1 Timer D Compare 1 16 1 TIMCCMP3 Timer C Compare 3 15 1 TIMCCMP2 Timer C Compare 2 14 1 TIMBCMP2 Timer B Compare 2 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTCMP1 NoEffect Master timer compare event has no effect 0 SetInactive Master timer compare event forces the output to its inactive state 1 MSTPER MSTPER 7 1 MSTPER NoEffect Master timer counter roll-over/reset has no effect 0 SetInactive Master timer counter roll-over/reset forces the output to its inactive state 1 4 0x1 1-4 CMP%s CMP%s 3 1 CMP1 NoEffect Timer compare event has no effect 0 SetInactive Timer compare event forces the output to its inactive state 1 PER PER 2 1 PER NoEffect Timer period event has no effect 0 SetInactive Timer period event forces the output to its inactive state 1 RESYNC RESYNC 1 1 RESYNC NoEffect Timer reset event coming solely from software or SYNC input event has no effect 0 SetInactive Timer reset event coming solely from software or SYNC input event forces the output to its inactive state 1 SRT SRT 0 1 SRT NoEffect No effect 0 SetInactive Force output to its inactive state 1 SET2R SETA2R Timerx Output2 Set Register 0x44 RST2R RSTA2R Timerx Output2 Reset Register 0x48 EEFR1 EEFAR1 Timerx External Event Filtering Register 1 0x4C 0x20 read-write 0x00000000 5 0x6 1-5 EE%sFLTR External Event %s filter 1 4 EE1FLTR Disabled No filtering 0 BlankResetToCompare1 Blanking from counter reset/roll-over to Compare 1 1 BlankResetToCompare2 Blanking from counter reset/roll-over to Compare 2 2 BlankResetToCompare3 Blanking from counter reset/roll-over to Compare 3 3 BlankResetToCompare4 Blanking from counter reset/roll-over to Compare 4 4 BlankTIMFLTR1 Blanking from another timing unit: TIMFLTR1 source 5 BlankTIMFLTR2 Blanking from another timing unit: TIMFLTR2 source 6 BlankTIMFLTR3 Blanking from another timing unit: TIMFLTR3 source 7 BlankTIMFLTR4 Blanking from another timing unit: TIMFLTR4 source 8 BlankTIMFLTR5 Blanking from another timing unit: TIMFLTR5 source 9 BlankTIMFLTR6 Blanking from another timing unit: TIMFLTR6 source 10 BlankTIMFLTR7 Blanking from another timing unit: TIMFLTR7 source 11 BlankTIMFLTR8 Blanking from another timing unit: TIMFLTR8 source 12 WindowResetToCompare2 Windowing from counter reset/roll-over to compare 2 13 WindowResetToCompare3 Windowing from counter reset/roll-over to compare 3 14 WindowTIMWIN Windowing from another timing unit: TIMWIN source 15 5 0x6 1-5 EE%sLTCH External Event %s latch 0 1 EE1LTCH Disabled Event is ignored if it happens during a blank, or passed through during a window 0 Enabled Event is latched and delayed till the end of the blanking or windowing period 1 EEFR2 EEFAR2 Timerx External Event Filtering Register 2 0x50 0x20 read-write 0x00000000 5 0x6 6-10 EE%sFLTR External Event %s filter 1 4 EE6FLTR Disabled No filtering 0 BlankResetToCompare1 Blanking from counter reset/roll-over to Compare 1 1 BlankResetToCompare2 Blanking from counter reset/roll-over to Compare 2 2 BlankResetToCompare3 Blanking from counter reset/roll-over to Compare 3 3 BlankResetToCompare4 Blanking from counter reset/roll-over to Compare 4 4 BlankTIMFLTR1 Blanking from another timing unit: TIMFLTR1 source 5 BlankTIMFLTR2 Blanking from another timing unit: TIMFLTR2 source 6 BlankTIMFLTR3 Blanking from another timing unit: TIMFLTR3 source 7 BlankTIMFLTR4 Blanking from another timing unit: TIMFLTR4 source 8 BlankTIMFLTR5 Blanking from another timing unit: TIMFLTR5 source 9 BlankTIMFLTR6 Blanking from another timing unit: TIMFLTR6 source 10 BlankTIMFLTR7 Blanking from another timing unit: TIMFLTR7 source 11 BlankTIMFLTR8 Blanking from another timing unit: TIMFLTR8 source 12 WindowResetToCompare2 Windowing from counter reset/roll-over to compare 2 13 WindowResetToCompare3 Windowing from counter reset/roll-over to compare 3 14 WindowTIMWIN Windowing from another timing unit: TIMWIN source 15 5 0x6 6-10 EE%sLTCH External Event %s latch 0 1 EE6LTCH Disabled Event is ignored if it happens during a blank, or passed through during a window 0 Enabled Event is latched and delayed till the end of the blanking or windowing period 1 RSTR RSTAR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMFCMP1 Timer A Update reset 0 1 TIMFCMP1 NoEffect Timer Y compare Z event has no effect 0 ResetCounter Timer X counter is reset upon timer Y compare Z event 1 TIMFCMP2 Timer F Compare 2 31 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMDCMP4 Timer D Compare 4 27 1 TIMDCMP2 Timer D Compare 2 26 1 TIMDCMP1 Timer D Compare 1 25 1 TIMCCMP4 Timer C Compare 4 24 1 TIMCCMP2 Timer C Compare 2 23 1 TIMCCMP1 Timer C Compare 1 22 1 TIMBCMP4 Timer B Compare 4 21 1 TIMBCMP2 Timer B Compare 2 20 1 TIMBCMP1 Timer B Compare 1 19 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 EXTEVNT1 NoEffect External event Z has no effect 0 ResetCounter Timer X counter is reset upon external event Z 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTCMP1 NoEffect Master timer compare Z event has no effect 0 ResetCounter Timer X counter is reset upon master timer compare Z event 1 MSTPER Master timer Period 4 1 MSTPER NoEffect Master timer period event has no effect 0 ResetCounter Timer X counter is reset upon master timer period event 1 CMP2 Timer A compare 2 reset 2 1 CMP2 NoEffect Timer X compare Z event has no effect 0 ResetCounter Timer X counter is reset upon timer X compare Z event 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 UPDT NoEffect Update event has no effect 0 ResetCounter Timer X counter is reset upon update event 1 CHPR CHPAR Timerx Chopper Register 0x58 0x20 read-write 0x00000000 STRTPW STRTPW 7 4 0 15 CARDTY Timerx chopper duty cycle value 4 3 0 7 CARFRQ Timerx carrier frequency value 0 4 0 15 CPT1CR CPT1ACR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TFCMP1 TFCMP1 14 1 TFCMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TF1RST TF1RST 13 1 TF1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TF1SET TF1SET 12 1 TF1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TFCMP2 TFCMP2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2ACR CPT2xCR 0x60 OUTR OUTAR Timerx Output Register 0x64 0x20 read-write 0x00000000 DIDL1 Output 1 Deadtime upon burst mode Idle entry 7 1 DIDL1 Disabled The programmed idle state is applied immediately to the output 0 Enabled Deadtime (inactive level) is inserted on output before entering the idle mode 1 DIDL2 Output 2 Deadtime upon burst mode Idle entry 23 1 CHP1 Output 1 Chopper enable 6 1 CHP1 Disabled Output signal not altered 0 Enabled Output signal is chopped by a carrier signal 1 CHP2 Output 2 Chopper enable 22 1 FAULT1 Output 1 Fault state 4 2 FAULT1 Disabled No action: the output is not affected by the fault input and stays in run mode 0 SetActive Output goes to active state after a fault event 1 SetInactive Output goes to inactive state after a fault event 2 SetHighZ Output goes to high-z state after a fault event 3 FAULT2 Output 2 Fault state 20 2 IDLES1 Output 1 Idle State 3 1 IDLES1 Inactive Output idle state is inactive 0 Active Output idle state is active 1 IDLES2 Output 2 Idle State 19 1 IDLEM1 Output 1 Idle mode 2 1 IDLEM1 NoEffect No action: the output is not affected by the burst mode operation 0 SetIdle The output is in idle state when requested by the burst mode controller 1 IDLEM2 Output 2 Idle mode 18 1 POL1 Output 1 polarity 1 1 POL1 ActiveHigh Positive polarity (output active high) 0 ActiveLow Negative polarity (output active low) 1 POL2 Output 2 polarity 17 1 BIAR Balanced Idle Automatic Resume 14 1 DLYPRT Delayed Protection 10 3 DLYPRT Output1_EE6 Output 1 delayed idle on external event 6 0 Output2_EE6 Output 2 delayed idle on external event 6 1 Output1_2_EE6 Output 1 and 2 delayed idle on external event 6 2 Balanced_EE6 Balanced idle on external event 6 3 Output1_EE7 Output 1 delayed idle on external event 7 4 Output2_EE7 Output 2 delayed idle on external event 7 5 Output1_2_EE7 Output 1 and 2 delayed idle on external event 7 6 Balanced_EE7 Balanced idle on external event 7 7 DLYPRTEN Delayed Protection Enable 9 1 DLYPRTEN Disabled No action 0 Enabled Delayed protection is enabled, as per DLYPRT bits 1 DTEN Deadtime enable 8 1 DTEN Disabled Output 1 and 2 signals are independent 0 Enabled Deadtime is inserted between output 1 and output 2 1 FLTR FLTAR Timerx Fault Register 0x68 0x20 read-write 0x00000000 FLTLCK Fault sources Lock 31 1 FLTLCK Unlocked FLT1EN..FLT5EN bits are read/write 0 Locked FLT1EN..FLT5EN bits are read only 1 6 0x1 1-6 FLT%sEN Fault %s enable 0 1 FLT1EN Ignored Fault input ignored 0 Active Fault input is active and can disable HRTIM outputs 1 CR2 ACR2 HRTIM Timerx Control Register 2 0x6C 0x20 read-write 0x00000000 TRGHLF Triggered-half mode 20 1 GTCMP3 Greater than Compare 3 PWM mode 17 1 GTCMP1 Greater than Compare 1 PWM mode 16 1 FEROM Fault and Event Roll-Over Mode 14 2 BMROM Burst Mode Roll-Over Mode 12 2 ADROM ADC Roll-Over Mode 10 2 OUTROM Output Roll-Over Mode 8 2 ROM Roll-Over Mode 6 2 UDM Up-Down Mode 4 1 DCDR Dual Channel DAC Reset trigger 2 1 DCDS Dual Channel DAC Step trigger 1 1 DCDE Dual Channel DAC trigger enable 0 1 EEFR3 AEEFR3 HRTIM Timerx External Event Filtering Register 3 0x70 0x20 read-write 0x00000000 EEVACNT External Event A counter 8 6 EEVASEL External Event A Selection 4 4 EEVARSTM External Event A Reset Mode 2 1 EEVACRES External Event A Counter Reset 1 1 EEVACE External Event A Counter Enable 0 1 HRTIM_TIMB High Resolution Timer: TIMB HRTIM 0x40016900 0x0 0x80 registers HRTIM_TIMB_IRQn HRTIM_TIMB_IRQn 69 CR BCR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TFU TFU 16 1 TFU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TAU TAU 19 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 RSYNCU Re-Synchronized Update 9 1 INTLVD Interleaved mode 7 2 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR BISR Timerx Interrupt Status Register 0x4 ICR BICR Timerx Interrupt Clear Register 0x8 DIER BDIER TIMxDIER 0xC CNTR CNTR Timerx Counter Register 0x10 PERR PERBR Timerx Period Register 0x14 REPR REPBR Timerx Repetition Register 0x18 CMP1R CMP1BR Timerx Compare 1 Register 0x1C CMP1CR CMP1CBR Timerx Compare 1 Compound Register 0x20 CMP2R CMP2BR Timerx Compare 2 Register 0x24 CMP3R CMP3BR Timerx Compare 3 Register 0x28 CMP4R CMP4BR Timerx Compare 4 Register 0x2C CPT1R CPT1BR Timerx Capture 1 Register 0x30 CPT2R CPT2BR Timerx Capture 2 Register 0x34 DTR DTBR Timerx Deadtime Register 0x38 SET1R SETB1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMFCMP3 Timer F Compare 3 20 1 TIMECMP2 Timer E Compare 2 19 1 TIMECMP1 Timer E Compare 1 18 1 TIMDCMP4 Timer D Compare 4 17 1 TIMDCMP3 Timer D Compare 3 16 1 TIMCCMP4 Timer C Compare 4 15 1 TIMCCMP3 Timer C Compare 3 14 1 TIMACMP2 Timer A Compare 2 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTB1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMFCMP3 Timer F Compare 3 20 1 TIMECMP2 Timer E Compare 2 19 1 TIMECMP1 Timer E Compare 1 18 1 TIMDCMP4 Timer D Compare 4 17 1 TIMDCMP3 Timer D Compare 3 16 1 TIMCCMP4 Timer C Compare 4 15 1 TIMCCMP3 Timer C Compare 3 14 1 TIMACMP2 Timer A Compare 2 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETB2R Timerx Output2 Set Register 0x44 RST2R RSTB2R Timerx Output2 Reset Register 0x48 EEFR1 EEFBR1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFBR2 Timerx External Event Filtering Register 2 0x50 RSTR RSTBR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMFCMP1 Timer A Update reset 0 1 TIMFCMP2 Timer F Compare 2 31 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMDCMP4 Timer D Compare 4 27 1 TIMDCMP2 Timer D Compare 2 26 1 TIMDCMP1 Timer D Compare 1 25 1 TIMCCMP4 Timer C Compare 4 24 1 TIMCCMP2 Timer C Compare 2 23 1 TIMCCMP1 Timer C Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 TIMACMP1 Timer A Compare 1 19 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPBR Timerx Chopper Register 0x58 CPT1CR CPT1BCR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TFCMP2 TFCMP2 19 1 TFCMP1 TFCMP1 18 1 TF1RST TF1RST 17 1 TF1SET TF1SET 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2BCR CPT2xCR 0x60 OUTR OUTBR Timerx Output Register 0x64 FLTR FLTBR Timerx Fault Register 0x68 CR2 BCR2 HRTIM Timerx Control Register 2 0x6C EEFR3 BEEFR3 HRTIM Timerx External Event Filtering Register 3 0x70 HRTIM_TIMC High Resolution Timer: TIMC HRTIM 0x40016980 0x0 0x80 registers HRTIM_TIMC_IRQn HRTIM_TIMC_IRQn 70 CR CCR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TFU TFU 16 1 TFU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TBU TBU 20 1 TAU TAU 19 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 RSYNCU Re-Synchronized Update 9 1 INTLVD Interleaved mode 7 2 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR CISR Timerx Interrupt Status Register 0x4 ICR CICR Timerx Interrupt Clear Register 0x8 DIER CDIER TIMxDIER 0xC CNTR CNTCR Timerx Counter Register 0x10 PERR PERCR Timerx Period Register 0x14 REPR REPCR Timerx Repetition Register 0x18 CMP1R CMP1CR Timerx Compare 1 Register 0x1C CMP1CR CMP1CCR Timerx Compare 1 Compound Register 0x20 CMP2R CMP2CR Timerx Compare 2 Register 0x24 CMP3R CMP3CR Timerx Compare 3 Register 0x28 CMP4R CMP4CR Timerx Compare 4 Register 0x2C CPT1R CPT1CR Timerx Capture 1 Register 0x30 CPT2R CPT2CR Timerx Capture 2 Register 0x34 DTR DTCR Timerx Deadtime Register 0x38 SET1R SETC1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP2 Timer A Compare 2 12 1 TIMFCMP2 Timer F Compare 2 20 1 TIMECMP4 Timer E Compare 4 19 1 TIMECMP3 Timer E Compare 3 18 1 TIMDCMP4 Timer D Compare 4 17 1 TIMDCMP2 Timer D Compare 2 16 1 TIMBCMP3 Timer B Compare 3 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP3 Timer A Compare 3 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTC1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP2 Timer A Compare 2 12 1 TIMFCMP2 Timer F Compare 2 20 1 TIMECMP4 Timer E Compare 4 19 1 TIMECMP3 Timer E Compare 3 18 1 TIMDCMP4 Timer D Compare 4 17 1 TIMDCMP2 Timer D Compare 2 16 1 TIMBCMP3 Timer B Compare 3 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP3 Timer A Compare 3 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETC2R Timerx Output2 Set Register 0x44 RST2R RSTC2R Timerx Output2 Reset Register 0x48 EEFR1 EEFCR1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFCR2 Timerx External Event Filtering Register 2 0x50 RSTR RSTCR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMFCMP1 Timer A Update reset 0 1 TIMFCMP2 Timer F Compare 2 31 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMDCMP4 Timer D Compare 4 27 1 TIMDCMP2 Timer D Compare 2 26 1 TIMDCMP1 Timer D Compare 1 25 1 TIMBCMP4 Timer B Compare 4 24 1 TIMBCMP2 Timer B Compare 2 23 1 TIMBCMP1 Timer B Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 TIMACMP1 Timer A Compare 1 19 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPCR Timerx Chopper Register 0x58 CPT1CR CPT1CCR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TFCMP2 TFCMP2 23 1 TFCMP1 TFCMP1 22 1 TF1RST TF1RST 21 1 TF1SET TF1SET 20 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2CCR CPT2xCR 0x60 OUTR OUTCR Timerx Output Register 0x64 FLTR FLTCR Timerx Fault Register 0x68 CR2 CCR2 HRTIM Timerx Control Register 2 0x6C EEFR3 CEEFR3 HRTIM Timerx External Event Filtering Register 3 0x70 HRTIM_TIMD High Resolution Timer: TIMD HRTIM 0x40016A00 0x0 0x80 registers HRTIM_TIMD_IRQn HRTIM_TIMD_IRQn 71 CR DCR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TFU TFU 16 1 TFU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TCU TCU 21 1 TBU TBU 20 1 TAU TAU 19 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 RSYNCU Re-Synchronized Update 9 1 INTLVD Interleaved mode 7 2 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR DISR Timerx Interrupt Status Register 0x4 ICR DICR Timerx Interrupt Clear Register 0x8 DIER DDIER TIMxDIER 0xC CNTR CNTDR Timerx Counter Register 0x10 PERR PERDR Timerx Period Register 0x14 REPR REPDR Timerx Repetition Register 0x18 CMP1R CMP1DR Timerx Compare 1 Register 0x1C CMP1CR CMP1CDR Timerx Compare 1 Compound Register 0x20 CMP2R CMP2DR Timerx Compare 2 Register 0x24 CMP3R CMP3DR Timerx Compare 3 Register 0x28 CMP4R CMP4DR Timerx Compare 4 Register 0x2C CPT1R CPT1DR Timerx Capture 1 Register 0x30 CPT2R CPT2DR Timerx Capture 2 Register 0x34 DTR DTDR Timerx Deadtime Register 0x38 SET1R SETD1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMFCMP3 Timer F Compare 3 20 1 TIMFCMP1 Timer F Compare 1 19 1 TIMECMP4 Timer E Compare 4 18 1 TIMECMP1 Timer E Compare 1 17 1 TIMCCMP4 Timer C Compare 4 16 1 TIMBCMP4 Timer B Compare 4 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP4 Timer A Compare 4 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTD1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMFCMP3 Timer F Compare 3 20 1 TIMFCMP1 Timer F Compare 1 19 1 TIMECMP4 Timer E Compare 4 18 1 TIMECMP1 Timer E Compare 1 17 1 TIMCCMP4 Timer C Compare 4 16 1 TIMBCMP4 Timer B Compare 4 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP4 Timer A Compare 4 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETD2R Timerx Output2 Set Register 0x44 RST2R RSTD2R Timerx Output2 Reset Register 0x48 EEFR1 EEFDR1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFDR2 Timerx External Event Filtering Register 2 0x50 RSTR RSTDR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMFCMP1 Timer A Update reset 0 1 TIMFCMP2 Timer F Compare 2 31 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMCCMP4 Timer C Compare 4 27 1 TIMCCMP2 Timer C Compare 2 26 1 TIMCCMP1 Timer C Compare 1 25 1 TIMBCMP4 Timer B Compare 4 24 1 TIMBCMP2 Timer B Compare 2 23 1 TIMBCMP1 Timer B Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 TIMACMP1 Timer A Compare 1 19 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPDR Timerx Chopper Register 0x58 CPT1CR CPT1DCR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TFCMP2 TFCMP2 27 1 TFCMP1 TFCMP1 26 1 TF1RST TF1RST 25 1 TF1SET TF1SET 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2DCR CPT2xCR 0x60 OUTR OUTDR Timerx Output Register 0x64 FLTR FLTDR Timerx Fault Register 0x68 CR2 DCR2 HRTIM Timerx Control Register 2 0x6C EEFR3 DEEFR3 HRTIM Timerx External Event Filtering Register 3 0x70 HRTIM_TIME High Resolution Timer: TIME HRTIM 0x40016A80 0x0 0x80 registers CR ECR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TFU TFU 16 1 TFU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TDU TDU 22 1 TCU TCU 21 1 TBU TBU 20 1 TAU TAU 19 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 RSYNCU Re-Synchronized Update 9 1 INTLVD Interleaved mode 7 2 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR EISR Timerx Interrupt Status Register 0x4 ICR EICR Timerx Interrupt Clear Register 0x8 DIER EDIER TIMxDIER 0xC CNTR CNTER Timerx Counter Register 0x10 PERR PERER Timerx Period Register 0x14 REPR REPER Timerx Repetition Register 0x18 CMP1R CMP1ER Timerx Compare 1 Register 0x1C CMP1CR CMP1CER Timerx Compare 1 Compound Register 0x20 CMP2R CMP2ER Timerx Compare 2 Register 0x24 CMP3R CMP3ER Timerx Compare 3 Register 0x28 CMP4R CMP4ER Timerx Compare 4 Register 0x2C CPT1R CPT1ER Timerx Capture 1 Register 0x30 CPT2R CPT2ER Timerx Capture 2 Register 0x34 DTR DTER Timerx Deadtime Register 0x38 SET1R SETE1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP4 Timer A Compare 4 12 1 TIMFCMP4 Timer F Compare 4 20 1 TIMFCMP3 Timer F Compare 3 19 1 TIMDCMP2 Timer D Compare 2 18 1 TIMDCMP1 Timer D Compare 1 17 1 TIMCCMP2 Timer C Compare 2 16 1 TIMCCMP1 Timer C Compare 1 15 1 TIMBCMP4 Timer B Compare 4 14 1 TIMBCMP3 Timer B Compare 3 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTE1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP4 Timer A Compare 4 12 1 TIMFCMP4 Timer F Compare 4 20 1 TIMFCMP3 Timer F Compare 3 19 1 TIMDCMP2 Timer D Compare 2 18 1 TIMDCMP1 Timer D Compare 1 17 1 TIMCCMP2 Timer C Compare 2 16 1 TIMCCMP1 Timer C Compare 1 15 1 TIMBCMP4 Timer B Compare 4 14 1 TIMBCMP3 Timer B Compare 3 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETE2R Timerx Output2 Set Register 0x44 RST2R RSTE2R Timerx Output2 Reset Register 0x48 EEFR1 EEFER1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFER2 Timerx External Event Filtering Register 2 0x50 RSTR RSTER TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMFCMP1 Timer A Update reset 0 1 TIMFCMP2 Timer F Compare 2 31 1 TIMDCMP4 Timer D Compare 4 30 1 TIMDCMP2 Timer D Compare 2 29 1 TIMDCMP1 Timer D Compare 1 28 1 TIMCCMP4 Timer C Compare 4 27 1 TIMCCMP2 Timer C Compare 2 26 1 TIMCCMP1 Timer C Compare 1 25 1 TIMBCMP4 Timer B Compare 4 24 1 TIMBCMP2 Timer B Compare 2 23 1 TIMBCMP1 Timer B Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 TIMACMP1 Timer A Compare 1 19 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPER Timerx Chopper Register 0x58 CPT1CR CPT1ECR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TFCMP2 TFCMP2 31 1 TFCMP1 TFCMP1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TF1RST TF1RST 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TF1SET TF1SET 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2ECR CPT2xCR 0x60 OUTR OUTER Timerx Output Register 0x64 FLTR FLTER Timerx Fault Register 0x68 CR2 ECR2 HRTIM Timerx Control Register 2 0x6C EEFR3 EEEFR3 HRTIM Timerx External Event Filtering Register 3 0x70 HRTIM_TIMF High Resolution Timer: TIMF HRTIM 0x40016B00 0x0 0x80 registers HRTIM_TIME_IRQn HRTIM_TIME_IRQn 72 HRTIM_TIMF_IRQn HRTIM_TIMF_IRQn 74 CR FCR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TAU TAU 19 1 TAU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TDU TDU 22 1 TCU TCU 21 1 TBU TBU 20 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 RSYNCU Re-Synchronized Update 9 1 INTLVD Interleaved mode 7 2 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR FISR Timerx Interrupt Status Register 0x4 ICR FICR Timerx Interrupt Clear Register 0x8 DIER FDIER TIMxDIER 0xC CNTR CNTFR Timerx Counter Register 0x10 PERR PERFR Timerx Period Register 0x14 REPR REPFR Timerx Repetition Register 0x18 CMP1R CMP1FR Timerx Compare 1 Register 0x1C CMP1CR CMP1CFR Timerx Compare 1 Compound Register 0x20 CMP2R CMP2FR Timerx Compare 2 Register 0x24 CMP3R CMP3FR Timerx Compare 3 Register 0x28 CMP4R CMP4FR Timerx Compare 4 Register 0x2C CPT1R CPT1FR Timerx Capture 1 Register 0x30 CPT2R CPT2FR Timerx Capture 2 Register 0x34 DTR DTFR Timerx Deadtime Register 0x38 SET1R SETF1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP3 Timer A Compare 3 12 1 TIMECMP3 Timer E Compare 3 20 1 TIMECMP2 Timer E Compare 2 19 1 TIMDCMP4 Timer D Compare 4 18 1 TIMDCMP3 Timer D Compare 3 17 1 TIMCCMP4 Timer C Compare 4 16 1 TIMCCMP1 Timer C Compare 1 15 1 TIMBCMP4 Timer B Compare 4 14 1 TIMBCMP1 Timer B Compare 1 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTE1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP3 Timer A Compare 3 12 1 TIMECMP3 Timer E Compare 3 20 1 TIMECMP2 Timer E Compare 2 19 1 TIMDCMP4 Timer D Compare 4 18 1 TIMDCMP3 Timer D Compare 3 17 1 TIMCCMP4 Timer C Compare 4 16 1 TIMCCMP1 Timer C Compare 1 15 1 TIMBCMP4 Timer B Compare 4 14 1 TIMBCMP1 Timer B Compare 1 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETF2R Timerx Output2 Set Register 0x44 RST2R RSTF2R Timerx Output2 Reset Register 0x48 EEFR1 EEFFR1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFFR2 Timerx External Event Filtering Register 2 0x50 RSTR RSTFR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMECMP1 Timer A Update reset 0 1 TIMECMP2 Timer F Compare 2 31 1 TIMDCMP4 Timer D Compare 4 30 1 TIMDCMP2 Timer D Compare 2 29 1 TIMDCMP1 Timer D Compare 1 28 1 TIMCCMP4 Timer C Compare 4 27 1 TIMCCMP2 Timer C Compare 2 26 1 TIMCCMP1 Timer C Compare 1 25 1 TIMBCMP4 Timer B Compare 4 24 1 TIMBCMP2 Timer B Compare 2 23 1 TIMBCMP1 Timer B Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 TIMACMP1 Timer A Compare 1 19 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPFR Timerx Chopper Register 0x58 CPT1CR CPT1FCR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 TECMP2 31 1 TECMP1 TECMP1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST TE1RST 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET TE1SET 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2FCR CPT2xCR 0x60 OUTR OUTFR Timerx Output Register 0x64 FLTR FLTFR Timerx Fault Register 0x68 CR2 FCR2 HRTIM Timerx Control Register 2 0x6C EEFR3 FEEFR3 HRTIM Timerx External Event Filtering Register 3 0x70 HRTIM_Common High Resolution Timer: Common functions HRTIM 0x40016B80 0x0 0x91 registers HRTIM_TIM_FLT_IRQn HRTIM_TIM_FLT_IRQn 73 CR1 CR1 Control Register 1 0x0 0x20 read-write 0x00000000 4 0x3 1-4 AD%sUSRC ADC Trigger %s Update Source 16 3 AD1USRC Master ADC trigger update from master timer 0 TimerA ADC trigger update from timer A 1 TimerB ADC trigger update from timer B 2 TimerC ADC trigger update from timer C 3 TimerD ADC trigger update from timer D 4 TimerE ADC trigger update from timer E 5 TimerF ADC trigger update from timer F 6 MUDIS Master Update Disable 0 1 MUDIS Enabled Timer update enabled 0 Disabled Timer update disabled 1 6 0x1 A,B,C,D,E,F T%sUDIS Timer %s Update Disable 1 1 CR2 CR2 Control Register 2 0x4 0x20 read-write 0x00000000 6 0x1 A,B,C,D,E,F SWP%s Swap Timer %s outputs 16 1 MRST Master Counter software reset 8 1 MRST Reset Reset timer 1 6 0x1 A,B,C,D,E,F T%sRST Timer %s counter software reset 9 1 MSWU Master Timer Software update 0 1 MSWU Update Force immediate update 1 6 0x1 A,B,C,D,E,F T%sSWU Timer %s Software Update 1 1 ISR ISR Interrupt Status Register 0x8 0x20 read-only 0x00000000 BMPER Burst mode Period Interrupt Flag 17 1 BMPERR NoEvent No burst mode period interrupt occurred 0 Event Burst mode period interrupt occured 1 DLLRDY DLL Ready Interrupt Flag 16 1 DLLRDYR NoEvent No DLL calibration ready interrupt occurred 0 Event DLL calibration ready interrupt occurred 1 FLT1 Fault 1 Interrupt Flag 0 1 FLT1R NoEvent No fault interrupt occurred 0 Event Fault interrupt occurred 1 FLT6 Fault 6 Interrupt Flag 6 1 SYSFLT System Fault Interrupt Flag 5 1 SYSFLTR NoEvent No fault interrupt occurred 0 Event Fault interrupt occurred 1 FLT5 Fault 5 Interrupt Flag 4 1 FLT4 Fault 4 Interrupt Flag 3 1 FLT3 Fault 3 Interrupt Flag 2 1 FLT2 Fault 2 Interrupt Flag 1 1 ICR ICR Interrupt Clear Register 0xC 0x20 write-only 0x00000000 FLT1C Fault 1 Interrupt Flag Clear 0 1 oneToClear FLT1CW Clear Clears associated flag in ISR register 1 BMPERC Burst mode period flag Clear 17 1 oneToClear DLLRDYC DLL Ready Interrupt flag Clear 16 1 oneToClear FLT6C Fault 6 Interrupt Flag Clear 6 1 oneToClear SYSFLTC System Fault Interrupt Flag Clear 5 1 oneToClear FLT5C Fault 5 Interrupt Flag Clear 4 1 oneToClear FLT4C Fault 4 Interrupt Flag Clear 3 1 oneToClear FLT3C Fault 3 Interrupt Flag Clear 2 1 oneToClear FLT2C Fault 2 Interrupt Flag Clear 1 1 oneToClear IER IER Interrupt Enable Register 0x10 0x20 read-write 0x00000000 BMPERIE Burst mode period Interrupt Enable 17 1 BMPERIE Disabled Burst mode period interrupt disabled 0 Enabled Burst mode period interrupt enabled 1 DLLRDYIE DLL Ready Interrupt Enable 16 1 DLLRDYIE Disabled DLL ready interrupt disabled 0 Enabled DLL Ready interrupt enabled 1 FLT1IE Fault 1 Interrupt Enable 0 1 FLT1IE Disabled Fault interrupt disabled 0 Enabled Fault interrupt enabled 1 FLT6IE Fault 6 Interrupt Enable 6 1 SYSFLTIE System Fault Interrupt Enable 5 1 FLT5IE Fault 5 Interrupt Enable 4 1 FLT4IE Fault 4 Interrupt Enable 3 1 FLT3IE Fault 3 Interrupt Enable 2 1 FLT2IE Fault 2 Interrupt Enable 1 1 OENR OENR Output Enable Register 0x14 0x20 read-write 0x00000000 6 0x2 A,B,C,D,E,F T%s1OEN Timer %s Output 1 Enable 0 1 oneToSet TOENR read Disabled Output disabled 0 Enabled Output enabled 1 TORNW write Enable Enable output 1 6 0x2 A,B,C,D,E,F T%s2OEN Timer %s Output 2 Enable 1 1 oneToSet read write ODISR ODISR ODISR 0x18 0x20 write-only 0x00000000 6 0x2 A,B,C,D,E,F T%s1ODIS T%s1ODIS 0 1 oneToSet TODIS Disable Disable output 1 6 0x2 A,B,C,D,E,F T%s2ODIS T%s2ODIS 1 1 oneToSet ODSR ODSR Output Disable Status Register 0x1C 0x20 read-only 0x00000000 6 0x2 A,B,C,D,E,F T%s1ODS Timer %s Output 1 disable status 0 1 TODS Idle Output disabled in idle state 0 Fault Output disabled in fault state 1 6 0x2 A,B,C,D,E,F T%s2ODS Timer %s Output 2 disable status 1 1 BMCR BMCR Burst Mode Control Register 0x20 0x20 read-write 0x00000000 BMSTAT Burst Mode Status 31 1 zeroToClear BMSTATR read Normal Normal operation 0 Burst Burst operation ongoing 1 BMSTATW write Cancel Terminate burst mode 0 MTBM Master Timer Burst Mode 16 1 MTBM Normal Counter clock is maintained and timer operates normally 0 Stopped Counter clock is stopped and counter is reset 1 6 0x1 A,B,C,D,E,F T%sBM Timer %s Burst Mode 17 1 BMPREN Burst Mode Preload Enable 10 1 BMPREN Disabled Preload disabled: the write access is directly done into active registers 0 Enabled Preload enabled: the write access is done into preload registers 1 BMPRSC Burst Mode Prescaler 6 4 BMPRSC Div1 Clock not divided 0 Div2 Division by 2 1 Div4 Division by 4 2 Div8 Division by 8 3 Div16 Division by 16 4 Div32 Division by 32 5 Div64 Division by 64 6 Div128 Division by 128 7 Div256 Division by 256 8 Div512 Division by 512 9 Div1024 Division by 1024 10 Div2048 Division by 2048 11 Div4096 Division by 4096 12 Div8192 Division by 8192 13 Div16384 Division by 16384 14 Div32768 Division by 32768 15 BMCLK Burst Mode Clock source 2 4 BMCLK Master Master timer reset/roll-over 0 TimerA Timer A counter reset/roll-over 1 TimerB Timer B counter reset/roll-over 2 TimerC Timer C counter reset/roll-over 3 TimerD Timer D counter reset/roll-over 4 TimerE Timer E counter reset/roll-over 5 Event1 On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock 6 Event2 On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock 7 Event3 On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock 8 Event4 On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock 9 Clock Prescaled f_HRTIM clock (as per BMPRSC[3:0] setting 10 BMOM Burst Mode operating mode 1 1 BMOM SingleShot Single-shot mode 0 Continuous Continuous operation 1 BME Burst Mode enable 0 1 BME Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 BMTRGR BMTRG BMTRG 0x24 0x20 read-write 0x00000000 OCHPEV OCHPEV 31 1 OCHPEV NoEffect Rising edge on an on-chip event has no effect 0 Trigger Rising edge on an on-chip event triggers a burst mode entry 1 EEV7 EEV7 29 1 EEV7 NoEffect External event X has no effect 0 Trigger External event X triggers a burst mode entry 1 EEV8 EEV8 30 1 TAEEV7 Timer A period following external event 7 27 1 TAEEV7 NoEffect Timer X period following external event Y has no effect 0 Trigger Timer X period following external event Y triggers a burst mode entry 1 TDEEV8 TDEEV8 28 1 TACMP1 TACMP1 9 1 TACMP1 NoEffect Timer X compare Y event has no effect 0 Trigger Timer X compare Y event triggers a burst mode entry 1 TECMP2 TECMP2 26 1 TECMP1 TECMP1 25 1 TAREP TAREP 8 1 TAREP NoEffect Timer X repetition event has no effect 0 Trigger Timer X repetition event triggers a burst mode entry 1 TEREP TEREP 24 1 TFCMP1 Timer F compare 1 event 23 1 TDCMP2 TDCMP2 22 1 TFREP Timer F repetition 21 1 TDREP TDREP 20 1 TARST TARST 7 1 TARST NoEffect Timer X reset/roll-over event has no effect 0 Trigger Timer X reset/roll-over event triggers a burst mode entry 1 TDRST TDRST 19 1 TFRST Timer F reset 18 1 TCCMP1 TCCMP1 17 1 TCREP TCREP 16 1 TCRST TCRST 15 1 TBCMP2 TBCMP2 14 1 TBCMP1 TBCMP1 13 1 TBREP TBREP 12 1 TBRST TBRST 11 1 TACMP2 TACMP2 10 1 MSTCMP1 MSTCMP1 3 1 MSTCMP1 NoEffect Master timer compare X event has no effect 0 Trigger Master timer compare X event triggers a burst mode entry 1 MSTCMP4 MSTCMP4 6 1 MSTCMP3 MSTCMP3 5 1 MSTCMP2 MSTCMP2 4 1 MSTREP MSTREP 2 1 MSTREP NoEffect Master timer repetition event has no effect 0 Trigger Master timer repetition event triggers a burst mode entry 1 MSTRST MSTRST 1 1 MSTRST NoEffect Master timer reset/roll-over event has no effect 0 Trigger Master timer reset/roll-over event triggers a burst mode entry 1 SW SW 0 1 SW NoEffect No effect 0 Trigger Trigger immediate burst mode operation 1 BMCMPR BMCMPR BMCMPR 0x28 0x20 read-write 0x00000000 BMCMP BMCMP 0 16 0 65535 BMPER BMPER Burst Mode Period Register 0x2C 0x20 read-write 0x00000000 BMPER Burst mode Period 0 16 0 65535 EECR1 EECR1 Timer External Event Control Register 1 0x30 0x20 read-write 0x00000000 5 0x6 1-5 EE%sFAST External Event %s Fast mode 5 1 EE1FAST Resynchronized External event is re-synchronised by the HRTIM logic before acting on outputs 0 Asynchronous External event is acting asynchronously on outputs (low-latency mode) 1 5 0x6 1-5 EE%sSNS External Event %s Sensitivity 3 2 EE1SNS Active On active level defined by EExPOL bit 0 Rising Rising edge 1 Falling Falling edge 2 Both Both edges 3 5 0x6 1-5 EE%sPOL External Event %s Polarity 2 1 EE1POL ActiveHigh External event is active high 0 ActiveLow External event is active low 1 5 0x6 1-5 EE%sSRC External Event %s Source 0 2 EE1SRC Src1 Source 1 0 Src2 Source 2 1 Src3 Source 3 2 Src4 Source 4 3 EECR2 EECR2 Timer External Event Control Register 2 0x34 0x20 read-write 0x00000000 5 0x6 6-10 EE%sSRC EE%sSRC 0 2 EE6SRC Src1 Source 1 0 Src2 Source 2 1 Src3 Source 3 2 Src4 Source 4 3 5 0x6 6-10 EE%sPOL EE%sPOL 2 1 EE6POL ActiveHigh External event is active high 0 ActiveLow External event is active low 1 5 0x6 6-10 EE%sSNS EE%sSNS 3 2 EE6SNS Active On active level defined by EExPOL bit 0 Rising Rising edge 1 Falling Falling edge 2 Both Both edges 3 EECR3 EECR3 Timer External Event Control Register 3 0x38 0x20 read-write 0x00000000 5 0x6 6-10 EE%sF EE%sF 0 4 EE6F Disabled Filter disabled 0 Div1_N2 f_SAMPLING=f_HRTIM, N=2 1 Div1_N4 f_SAMPLING=f_HRTIM, N=4 2 Div1_N8 f_SAMPLING=f_HRTIM, N=8 3 Div2_N6 f_SAMPLING=f_EEVS/2, N=6 4 Div2_N8 f_SAMPLING=f_EEVS/2, N=8 5 Div4_N6 f_SAMPLING=f_EEVS/4, N=6 6 Div4_N8 f_SAMPLING=f_EEVS/4, N=8 7 Div8_N6 f_SAMPLING=f_EEVS/8, N=6 8 Div8_N8 f_SAMPLING=f_EEVS/8, N=8 9 Div16_N5 f_SAMPLING=f_EEVS/16, N=5 10 Div16_N6 f_SAMPLING=f_EEVS/16, N=6 11 Div16_N8 f_SAMPLING=f_EEVS/16, N=8 12 Div32_N5 f_SAMPLING=f_EEVS/32, N=5 13 Div32_N6 f_SAMPLING=f_EEVS/32, N=6 14 Div32_N8 f_SAMPLING=f_EEVS/32, N=8 15 EEVSD EEVSD 30 2 EEVSD Div1 f_EEVS=f_HRTIM 0 Div2 f_EEVS=f_HRTIM/2 1 Div4 f_EEVS=f_HRTIM/4 2 Div8 f_EEVS=f_HRTIM/8 3 ADC1R ADC1R ADC Trigger 1 Register 0x3C 0x20 read-write 0x00000000 MPER ADC trigger 1 on Master Period 4 1 MPER Disabled No generation of ADC trigger on timer period event 0 Enabled Generation of ADC trigger on timer period event 1 EPER ADC trigger 1 on Timer E Period 31 1 FC2 Bit 10 - ADC trigger 1 on timer F compare 2 10 1 FC2 Disabled No generation of ADC trigger on timer compare event 0 Enabled Generation of ADC trigger on timer compare event 1 EC4 ADC trigger 1 on Timer E compare 4 30 1 EC3 ADC trigger 1 on Timer E compare 3 29 1 ARST ADC trigger 1 on Timer A Reset 14 1 ARST Disabled No generation of ADC trigger on timer reset and roll-over 0 Enabled Generation of ADC trigger on timer reset and roll-over 1 FRST Bit 28 - ADC trigger 1 on timer F reset and counter roll-over 28 1 DPER ADC trigger 1 on Timer D Period 27 1 DC4 ADC trigger 1 on Timer D compare 4 26 1 DC3 ADC trigger 1 on Timer D compare 3 25 1 FPER Bit 24 - ADC trigger 1 on timer F period 24 1 CPER ADC trigger 1 on Timer C Period 23 1 CC4 ADC trigger 1 on Timer C compare 4 22 1 CC3 ADC trigger 1 on Timer C compare 3 21 1 FC4 Bit 20 - ADC trigger 1 on timer F compare 4 20 1 BRST ADC trigger 1 on Timer B Reset 19 1 BPER ADC trigger 1 on Timer B Period 18 1 BC4 ADC trigger 1 on Timer B compare 4 17 1 BC3 ADC trigger 1 on Timer B compare 3 16 1 FC3 Bit 15 - ADC trigger 1 on timer F compare 3 15 1 APER ADC trigger 1 on Timer A Period 13 1 AC4 ADC trigger 1 on Timer A compare 4 12 1 AC3 ADC trigger 1 on Timer A compare 3 11 1 5 0x1 1-5 EEV%s ADC trigger 1 on External Event %s 5 1 EEV1 Disabled No generation of ADC trigger on external event 0 Enabled Generation of ADC trigger on external event 1 4 0x1 1-4 MC%s ADC trigger 1 on Master Compare %s 0 1 MC1 Disabled No generation of ADC trigger on master compare event 0 Enabled Generation of ADC trigger on master compare event 1 ADC2R ADC2R ADC Trigger 2 Register 0x40 0x20 read-write 0x00000000 CRST ADC trigger 2 on Timer C Reset 22 1 CRST Disabled No generation of ADC trigger on timer reset and roll-over 0 Enabled Generation of ADC trigger on timer reset and roll-over 1 ERST ADC trigger 2 on Timer E Reset 31 1 AC2 ADC trigger 2 on Timer A compare 2 10 1 AC2 Disabled No generation of ADC trigger on timer compare event 0 Enabled Generation of ADC trigger on timer compare event 1 EC4 ADC trigger 2 on Timer E compare 4 30 1 EC3 ADC trigger 2 on Timer E compare 3 29 1 EC2 ADC trigger 2 on Timer E compare 2 28 1 DRST ADC trigger 2 on Timer D Reset 27 1 MPER ADC trigger 2 on Master Period 4 1 MPER Disabled No generation of ADC trigger on timer period event 0 Enabled Generation of ADC trigger on timer period event 1 DPER ADC trigger 2 on Timer D Period 26 1 DC4 ADC trigger 2 on Timer D compare 4 25 1 FPER Bit 24 - ADC trigger 2 on timer F period 24 1 DC2 ADC trigger 2 on Timer D compare 2 23 1 CPER ADC trigger 2 on Timer C Period 21 1 CC4 ADC trigger 2 on Timer C compare 4 20 1 FC4 Bit 19 - ADC trigger 2 on timer F compare 4 19 1 CC2 ADC trigger 2 on Timer C compare 2 18 1 BPER ADC trigger 2 on Timer B Period 17 1 BC4 ADC trigger 2 on Timer B compare 4 16 1 FC3 Bit 15 - ADC trigger 2 on timer F compare 3 15 1 BC2 ADC trigger 2 on Timer B compare 2 14 1 APER ADC trigger 2 on Timer A Period 13 1 AC4 ADC trigger 2 on Timer A compare 4 12 1 FC2 Bit 11 - ADC trigger 3 on timer F compare 2 11 1 5 0x1 6-10 EEV%s ADC trigger 2 on External Event %s 5 1 EEV6 Disabled No generation of ADC trigger on external event 0 Enabled Generation of ADC trigger on external event 1 4 0x1 1-4 MC%s ADC trigger 2 on Master Compare %s 0 1 MC1 Disabled No generation of ADC trigger on master compare event 0 Enabled Generation of ADC trigger on master compare event 1 ADC3R ADC3R ADC Trigger 3 Register 0x44 ADC4R ADC4R ADC Trigger 4 Register 0x48 DLLCR DLLCR DLL Control Register 0x4C 0x20 read-write 0x00000000 CALRTE DLL Calibration rate 2 2 CALRTE Clk1048576 1048576*t_HRTIM (6.168 ms for fHRTIM = 170 MHz) 0 Clk131072 131072*t_HRTIM (771 Âµs for f_HRTIM = 170 MHz) 1 Clk16384 16384*t_HRTIM (96 Âµs for f_HRTIM = 170 MHz) 2 Clk2048 2048*t_HRTIM (12 Âµs for f_HRTIM = 170 MHz) 3 CALEN DLL Calibration Enable 1 1 CALEN Disabled Periodic calibration disabled 0 Enabled Calibration is performed periodically, as per CALRTE setting 1 CAL DLL Calibration Start 0 1 CAL Start Calibration start 1 FLTINR1 FLTINR1 HRTIM Fault Input Register 1 0x50 0x20 read-write 0x00000000 FLT1LCK FLT1LCK 7 1 FLT1LCKR read Unlocked Fault bits are read/write 0 Locked Fault bits are read-only 1 FLT1LCKW write Lock Lock corresponding fault bits 1 FLT4LCK FLT4LCK 31 1 read write 4 0x8 1-4 FLT%sF FLT%sF 3 4 FLT1F Disabled No filter, FLTx acts asynchronously 0 Div1_N2 f_SAMPLING=f_HRTIM, N=2 1 Div1_N4 f_SAMPLING=f_HRTIM, N=4 2 Div1_N8 f_SAMPLING=f_HRTIM, N=8 3 Div2_N6 f_SAMPLING=f_HRTIM/2, N=6 4 Div2_N8 f_SAMPLING=f_HRTIM/2, N=8 5 Div4_N6 f_SAMPLING=f_HRTIM/4, N=6 6 Div4_N8 f_SAMPLING=f_HRTIM/4, N=8 7 Div8_N6 f_SAMPLING=f_HRTIM/8, N=6 8 Div8_N8 f_SAMPLING=f_HRTIM/8, N=8 9 Div16_N5 f_SAMPLING=f_HRTIM/16, N=5 10 Div16_N6 f_SAMPLING=f_HRTIM/16, N=6 11 Div16_N8 f_SAMPLING=f_HRTIM/16, N=8 12 Div32_N5 f_SAMPLING=f_HRTIM/32, N=5 13 Div32_N6 f_SAMPLING=f_HRTIM/32, N=6 14 Div32_N8 f_SAMPLING=f_HRTIM/32, N=8 15 4 0x8 1-4 FLT%sSRC Fault %s source 2 1 FLT1SRC Input Fault input is FLTx input pin 0 CompOutput Fault input is connected to a COMPx output 1 4 0x8 1-4 FLT%sP FLT%sP 1 1 FLT1P ActiveLow Fault input is active low 0 ActiveHigh Fault input is active high 1 4 0x8 1-4 FLT%sE FLT%sE 0 1 FLT1E Disabled Fault input disabled 0 Enabled Fault input enabled 1 FLT3LCK FLT3LCK 23 1 read write FLT2LCK FLT2LCK 15 1 read write FLTINR2 FLTINR2 HRTIM Fault Input Register 2 0x54 0x20 read-write 0x00000000 FLTSD FLTSD 24 2 FLTSD Div1 f_FLTS=f_HRTIM 0 Div2 f_FLTS=f_HRTIM/2 1 Div4 f_FLTS=f_HRTIM/4 2 Div8 f_FLTS=f_HRTIM/8 3 6 0x1 1-6 FLT%sSRC_1 Fault %s source bit 1 16 1 FLT1SRC_1 Default As described in FLTxSRC 0 Eev Fault input is EEV5_muxout input pin (when FLTxSRC == 0) / reserved 1 FLT5LCK FLT5LCK 7 1 FLT5LCKR read Unlocked Fault bits are read/write 0 Locked Fault bits are read-only 1 FLT5LCKW write Lock Lock corresponding fault bits 1 FLT6LCK FLT6LCK 15 1 read write 2 0x8 5-6 FLT%sF FLT%sF 3 4 FLT5F Disabled No filter, FLTx acts asynchronously 0 Div1_N2 f_SAMPLING=f_HRTIM, N=2 1 Div1_N4 f_SAMPLING=f_HRTIM, N=4 2 Div1_N8 f_SAMPLING=f_HRTIM, N=8 3 Div2_N6 f_SAMPLING=f_HRTIM/2, N=6 4 Div2_N8 f_SAMPLING=f_HRTIM/2, N=8 5 Div4_N6 f_SAMPLING=f_HRTIM/4, N=6 6 Div4_N8 f_SAMPLING=f_HRTIM/4, N=8 7 Div8_N6 f_SAMPLING=f_HRTIM/8, N=6 8 Div8_N8 f_SAMPLING=f_HRTIM/8, N=8 9 Div16_N5 f_SAMPLING=f_HRTIM/16, N=5 10 Div16_N6 f_SAMPLING=f_HRTIM/16, N=6 11 Div16_N8 f_SAMPLING=f_HRTIM/16, N=8 12 Div32_N5 f_SAMPLING=f_HRTIM/32, N=5 13 Div32_N6 f_SAMPLING=f_HRTIM/32, N=6 14 Div32_N8 f_SAMPLING=f_HRTIM/32, N=8 15 2 0x8 5-6 FLT%sSRC Fault %s source 2 1 FLT5SRC Input Fault input is FLTx input pin 0 CompOutput Fault input is connected to a COMPx output 1 2 0x8 5-6 FLT%sP FLT%sP 1 1 FLT5P ActiveLow Fault input is active low 0 ActiveHigh Fault input is active high 1 2 0x8 5-6 FLT%sE FLT%sE 0 1 FLT5E Disabled Fault input disabled 0 Enabled Fault input enabled 1 BDMUPR BDMUPDR BDMUPDR 0x58 0x20 read-write 0x00000000 MCR MCR 0 1 MCR NotUpdated Register not updated by burst DMA access 0 Updated Register updated by burst DMA access 1 MCMP4 MCMP4 9 1 MCMP3 MCMP3 8 1 MCMP2 MCMP2 7 1 MCMP1 MCMP1 6 1 MREP MREP 5 1 MPER MPER 4 1 MCNT MCNT 3 1 MDIER MDIER 2 1 MICR MICR 1 1 BDTAUPR BDTAUPR Burst DMA Timerx update Register 0x5C 0x20 read-write 0x00000000 CR HRTIM_TIMxCR register update enable 0 1 CR NotUpdated Register not updated by burst DMA access 0 Updated Register updated by burst DMA access 1 EEFR3 TIMxEEFR3 22 1 CR2 TIMxCR2 21 1 FLTR HRTIM_FLTxR register update enable 20 1 OUTR HRTIM_OUTxR register update enable 19 1 CHPR HRTIM_CHPxR register update enable 18 1 RSTR HRTIM_RSTxR register update enable 17 1 EEFR2 HRTIM_EEFxR2 register update enable 16 1 EEFR1 HRTIM_EEFxR1 register update enable 15 1 RST2R HRTIM_RST2xR register update enable 14 1 SET2R HRTIM_SET2xR register update enable 13 1 RST1R HRTIM_RST1xR register update enable 12 1 SET1R HRTIM_SET1xR register update enable 11 1 _DTxR HRTIM_DTxR register update enable 10 1 CMP4 HRTIM_CMP4xR register update enable 9 1 CMP3 HRTIM_CMP3xR register update enable 8 1 CMP2 HRTIM_CMP2xR register update enable 7 1 CMP1 HRTIM_CMP1xR register update enable 6 1 REP HRTIM_REPxR register update enable 5 1 PER HRTIM_PERxR register update enable 4 1 CNT HRTIM_CNTxR register update enable 3 1 DIER HRTIM_TIMxDIER register update enable 2 1 ICR HRTIM_TIMxICR register update enable 1 1 BDTBUPR BDTBUPR Burst DMA Timerx update Register 0x60 BDTCUPR BDTCUPR Burst DMA Timerx update Register 0x64 BDTDUPR BDTDUPR Burst DMA Timerx update Register 0x68 BDTEUPR BDTEUPR Burst DMA Timerx update Register 0x6C BDTFUPR BDTFUPR Burst DMA Timerx update Register 0x74 BDMADR BDMADR Burst DMA Data Register 0x70 0x20 write-only 0x00000000 BDMADR Burst DMA Data register 0 32 0 4294967295 ADCER ADCER HRTIM ADC Extended Trigger Register 0x78 0x20 read-write 0x00000000 ADC10TRG ADC10TRG 26 5 ADC9TRG ADC9TRG 21 5 ADC8TRG ADC8TRG 16 5 ADC7TRG ADC7TRG 10 5 ADC6TRG ADC6TRG 5 5 ADC5TRG ADC5TRG 0 5 ADCUR ADCUR HRTIM ADC Trigger Update Register 0x7C 0x20 read-write 0x00000000 AD10USRC AD10USRC 20 3 AD9USRC AD9USRC 16 3 AD8USRC AD8USRC 12 3 AD7USRC AD7USRC 8 3 AD6USRC AD6USRC 4 3 AD5USRC AD5USRC 0 3 ADCPS1 ADCPS1 HRTIM ADC Post Scaler Register 1 0x80 0x20 read-write 0x00000000 ADC5PSC ADC5PSC 24 5 ADC4PSC ADC4PSC 18 5 ADC3PSC ADC3PSC 12 5 ADC2PSC ADC2PSC 6 5 ADC1PSC ADC1PSC 0 5 ADCPS2 ADCPS2 HRTIM ADC Post Scaler Register 2 0x84 0x20 read-write 0x00000000 ADC10PSC ADC10PSC 24 5 ADC9PSC ADC9PSC 18 5 ADC8PSC ADC8PSC 12 5 ADC7PSC ADC7PSC 6 5 ADC6PSC ADC6PSC 0 5 FLTINR3 FLTINR3 HRTIM Fault Input Register 3 0x88 0x20 read-write 0x00000000 FLT4RSTM FLT4RSTM 31 1 4 0x8 1-4 FLT%sCRES FLT%sCRES 6 1 4 0x8 1-4 FLT%sCNT FLT%sCNT 2 4 4 0x8 1-4 FLT%sBLKS FLT%sBLKS 1 1 4 0x8 1-4 FLT%sBLKE FLT%sBLKE 0 1 FLT3RSTM FLT3RSTM 23 1 FLT2RSTM FLT2RSTM 15 1 FLT1RSTM FLT1RSTM 7 1 FLTINR4 FLTINR4 HRTIM Fault Input Register 4 0x8C 0x20 read-write 0x00000000 FLT6RSTM FLT6RSTM 15 1 2 0x8 5-6 FLT%sCRES FLT%sCRES 6 1 2 0x8 5-6 FLT%sCNT FLT%sCNT 2 4 2 0x8 5-6 FLT%sBLKS FLT%sBLKS 1 1 2 0x8 5-6 FLT%sBLKE FLT%sBLKE 0 1 FLT5RSTM FLT5RSTM 7 1 QUADSPI QuadSPI interface QUADSPI 0xA0001000 0x0 0x400 registers QUADSPI QUADSPI 95 CR CR control register 0x0 0x20 read-write 0x00000000 PRESCALER Clock prescaler 24 8 0 255 PMM Polling match mode 23 1 PMM AndMatch AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register. 0 OrMatch OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register. 1 APMS Automatic poll mode stop 22 1 APMS NotStopOnMatch Automatic polling mode is stopped only by abort or by disabling the QUADSPI. 0 StopOnMatch Automatic polling mode stops as soon as there is a match. 1 TEIE Transfer error interrupt enable 16 1 TEIE Disabled Interrupt disable 0 Enabled Interrupt enabled 1 TOIE TimeOut interrupt enable 20 1 SMIE Status match interrupt enable 19 1 FTIE FIFO threshold interrupt enable 18 1 TCIE Transfer complete interrupt enable 17 1 FTHRES IFO threshold level 8 5 FSEL FSEL 7 1 FSEL SelectFlash1 FLASH 1 selected 0 SelectFlash2 FLASH 2 selected 1 DFM DFM 6 1 DFM Disabled Dual-flash mode disabled 0 Enabled Dual-flash mode enabled 1 SSHIFT Sample shift 4 1 SSHIFT NoShift No shift 0 OneHalfCycleShift 1/2 cycle shift 1 TCEN Timeout counter enable 3 1 TCEN Disabled Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode. 0 Enabled Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT[15:0] cycles of Flash memory inactivity. 1 DMAEN DMA enable 2 1 DMAEN Disabled DMA is disabled for indirect mode 0 Enabled DMA is enabled for indirect mode 1 ABORT Abort request 1 1 ABORT NoAbortRequested No abort requested 0 AbortRequested Abort requested 1 EN Enable 0 1 EN Disabled QUADSPI is disabled 0 Enabled QUADSPI is enabled 1 DCR DCR device configuration register 0x4 0x20 read-write 0x00000000 FSIZE FLASH memory size 16 5 0 31 CSHT Chip select high time 8 3 0 7 CKMODE Mode 0 / mode 3 0 1 CKMODE Mode0 CLK must stay low while nCS is high (chip select released). This is referred to as mode 0. 0 Mode3 CLK must stay high while nCS is high (chip select released). This is referred to as mode 3. 1 SR SR status register 0x8 0x20 read-only 0x00000000 FLEVEL FIFO level 8 5 0 31 BUSY Busy 5 1 BUSY NotBusy 0 Busy 1 TOF Timeout flag 4 1 TOF NotTimeout 0 Timeout 1 SMF Status match flag 3 1 SMF NotMatched 0 Matched 1 FTF FIFO threshold flag 2 1 FTF NotReached 0 Reached 1 TCF Transfer complete flag 1 1 TCF NotComplete 0 Complete 1 TEF Transfer error flag 0 1 TEF NoError 0 Error 1 FCR FCR flag clear register 0xC 0x20 read-write 0x00000000 CTOF Clear timeout flag 4 1 CTOF Clear clears the TOF flag in the QUADSPI_SR register 1 CSMF Clear status match flag 3 1 CSMF Clear clears the SMF flag in the QUADSPI_SR register 1 CTCF Clear transfer complete flag 1 1 CTCF Clear clears the TCF flag in the QUADSPI_SR register 1 CTEF Clear transfer error flag 0 1 CTEF Clear clears the TEF flag in the QUADSPI_SR register 1 DLR DLR data length register 0x10 0x20 read-write 0x00000000 DL Data length 0 32 0 4294967295 CCR CCR communication configuration register 0x14 0x20 read-write 0x00000000 DDRM Double data rate mode 31 1 DDRM Disabled DDR Mode disabled 0 Enabled DDR Mode enabled 1 SIOO Send instruction only once mode 28 1 SIOO SendEveryTransaction Send instruction on every transaction 0 SendFirstCommand Send instruction only for the first command 1 FMODE Functional mode 26 2 FMODE IndirectWrite Indirect write mode 0 IndirectRead Indirect read mode 1 AutomaticPolling Automatic polling mode 2 MemoryMapped Memory-mapped mode 3 DMODE Data mode 24 2 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 DCYC Number of dummy cycles 18 5 0 31 ABSIZE Alternate bytes size 16 2 ABSIZE Bit8 8-bit alternate byte 0 Bit16 16-bit alternate bytes 1 Bit24 24-bit alternate bytes 2 Bit32 32-bit alternate bytes 3 ABMODE Alternate bytes mode 14 2 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 ADSIZE Address size 12 2 ADSIZE Bit8 8-bit address 0 Bit16 16-bit address 1 Bit24 24-bit address 2 Bit32 32-bit address 3 ADMODE Address mode 10 2 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 IMODE Instruction mode 8 2 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 INSTRUCTION Instruction 0 8 0 255 DHHC DDR hold 30 1 DHHC NoDelay Delay the data output using analog delay 0 Delayed Delay the data output by 1/4 of a QUADSPI output clock cycle. 1 AR AR address register 0x18 0x20 read-write 0x00000000 ADDRESS Address 0 32 0 4294967295 ABR ABR ABR 0x1C 0x20 read-write 0x00000000 ALTERNATE ALTERNATE 0 32 0 4294967295 DR DR Data register: full word (32 bit) access 0x20 0x20 read-write 0x00000000 DATA Data 0 32 0 4294967295 DR16 Data register: half word (16 bit) access DR 0x20 0x10 DATA Data 0 16 0 65535 DR8 Data register: one byte (8 bit) access DR 0x20 0x8 DATA Data 0 8 0 255 PSMKR PSMKR polling status mask register 0x24 0x20 read-write 0x00000000 MASK Status mask 0 32 0 4294967295 PSMAR PSMAR polling status match register 0x28 0x20 read-write 0x00000000 MATCH Status match 0 32 0 4294967295 PIR PIR polling interval register 0x2C 0x20 read-write 0x00000000 INTERVAL Polling interval 0 16 0 65535 LPTR LPTR low-power timeout register 0x30 0x20 read-write 0x00000000 TIMEOUT Timeout period 0 16 0 65535 DAC1 Digital-to-analog converter DAC 0x50000800 0x0 0x400 registers CR CR DAC control register 0x0 0x20 read-write 0x00000000 2 0x10 1-2 EN%s DAC channel%s enable 0 1 EN1 Disabled DAC Channel X disabled 0 Enabled DAC Channel X enabled 1 2 0x10 1-2 TEN%s DAC channel%s trigger enable 1 1 TEN1 Disabled DAC Channel X trigger disabled 0 Enabled DAC Channel X trigger enabled 1 TSEL1 DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 2 4 TSEL1 Swtrig Software trigger 0 Tim1or8Trgo Timer 8 (DAC1 1 Tim7Trgo Timer 7 TRGO event 2 Tim15Trgo Timer 15 TRGO event 3 Tim2Trgo Timer 2 TRGO event 4 Tim4Trgo Timer 4 TRGO event 5 Exti9 EXTI line 9 6 Tim6Trgo Timer 6 TRGO event 7 Tim3Trgo Timer 3 TRGO event 8 HrtimDacReset1 hrtim_dac_reset_trg1 9 HrtimDacReset2 hrtim_dac_reset_trg2 10 HrtimDacReset3 hrtim_dac_reset_trg3 11 HrtimDacReset4 hrtim_dac_reset_trg4 12 HrtimDacReset5 hrtim_dac_reset_trg5 13 HrtimDacReset6 hrtim_dac_reset_trg6 14 HrtimDacX hrtim_dac_trg1 (DAC1 15 2 0x10 1-2 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true 2 0x10 1-2 MAMP%s DAC channel%s mask/amplitude selector 8 4 MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 2 0x10 1-2 DMAEN%s DAC channel%s DMA enable 12 1 DMAEN1 Disabled DAC Channel X DMA mode disabled 0 Enabled DAC Channel X DMA mode enabled 1 2 0x10 1-2 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 2 0x10 1-2 CEN%s DAC channel%s calibration enable 14 1 CEN1 Normal DAC Channel X Normal operating mode 0 Calibration DAC Channel X calibration mode 1 TSEL2 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). 18 4 SWTRGR SWTRGR DAC software trigger register 0x4 0x20 write-only 0x00000000 2 0x1 1-2 SWTRIG%s DAC channel%s software trigger 0 1 SWTRIG1 NoTrigger No trigger 0 Trigger Trigger 1 2 0x1 1-2 SWTRIGB%s DAC channel%s software trigger B 16 1 SWTRIGB1 NoTrigger No trigger 0 Trigger Trigger for sawtooth increment 1 2 0xC 1-2 DHR12R%s DHR12R%s channel%s 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 0 4095 DACC1DHRB DAC channel1 12-bit right-aligned data B 16 12 0 4095 2 0xC 1-2 DHR12L%s DHR12L%s channel%s 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 0 4095 DACC1DHRB DAC channel1 12-bit left-aligned data B 20 12 0 4095 2 0xC 1-2 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACCDHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 0 255 DACC1DHRB DAC channel1 8-bit right-aligned data 8 8 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 0 4095 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 0 4095 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 2 0x8 1-2 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 0 255 2 0x4 1-2 DOR%s DOR%s channel%s data output register 0x2C 0x20 read-only 0x00000000 DACCDOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 0 4095 DACC1DORB DAC channel1 data output 16 12 0 4095 SR SR DAC status register 0x34 0x20 0x00000000 2 0x10 1-2 DAC%sRDY DAC channel%s ready status bit 11 1 read-write DAC1RDY NotReady DAC channelX is not yet ready to accept the trigger nor output data 0 Ready DAC channelX is ready to accept the trigger or output data 1 2 0x10 1-2 DORSTAT%s DAC channel%s output register status bit 12 1 read-write DORSTAT1 Dor DOR[11:0] is used actual DAC output 0 Dorb DORB[11:0] is used actual DAC output 1 2 0x10 1-2 DMAUDR%s DAC channel%s DMA underrun flag 13 1 read-write DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 2 0x10 1-2 CAL_FLAG%s DAC channel%s calibration offset status 14 1 read-only CAL_FLAG1 Lower Calibration trimming value is lower than the offset correction value 0 Equal_Higher Calibration trimming value is equal or greater than the offset correction value 1 2 0x10 1-2 BWST%s DAC channel%s busy writing sample time flag 15 1 read-only BWST1 Idle There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written 0 Busy There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written 1 CCR CCR DAC calibration control register 0x38 0x20 read-write 0x00000000 2 0x10 1-2 OTRIM%s DAC channel%s offset trimming value 0 5 0 31 MCR MCR DAC mode control register 0x3C 0x20 read-write 0x00000000 2 0x10 1-2 MODE%s DAC channel%s mode 0 3 MODE1 NormalPinBuffer Normal mode - DAC channelx is connected to external pin with Buffer enabled 0 NormalPinChipBuffer Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 1 NormalPinNoBuffer Normal mode - DAC channelx is connected to external pin with Buffer disabled 2 NormalChipNoBuffer Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled 3 SHPinBuffer S&H mode - DAC channelx is connected to external pin with Buffer enabled 4 SHPinChipBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 5 SHPinNoBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled 6 SHChipNoBuffer S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled 7 2 0x10 1-2 DMADOUBLE%s DAC channel%s DMA double data mode 8 1 DMADOUBLE1 Normal DMA Normal mode selected 0 DoubleData DMA Double data mode selected 1 2 0x10 1-2 SINFORMAT%s Enable signed format for DAC channel%s 9 1 SINFORMAT1 Unsigned Input data is in unsigned format 0 Signed Input data is in signed format (2's complement). The MSB bit represents the sign. 1 HFSEL High frequency interface mode selection 14 2 HFSEL Disabled High frequency interface mode disabled 0 More80Mhz High frequency interface mode enabled for AHB clock frequency > 80 MHz 1 More160Mhz High frequency interface mode enabled for AHB clock frequency >160 MHz 2 2 0x4 1-2 SHSR%s SHSR%s DAC channel%s sample and hold sample time register 0x40 0x20 read-write 0x00000000 TSAMPLE DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 0 1023 SHHR SHHR DAC Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 2 0x10 1-2 THOLD%s DAC channel%s hold time (only valid in Sample and hold mode) 0 10 0 1023 SHRR SHRR DAC Sample and Hold refresh time register 0x4C 0x20 read-write 0x00010001 2 0x10 1-2 TREFRESH%s DAC channel%s refresh time (only valid in Sample and hold mode) 0 8 0 255 2 0x4 1-2 STR%s STR%s Sawtooth register 0x58 0x20 read-write 0x00000000 STRSTDATA DAC Channel 1 Sawtooth reset value 0 12 0 4095 STDIR DAC Channel1 Sawtooth direction setting 12 1 STDIR1 Decrement Decrement 0 Increment Increment 1 STINCDATA DAC CH1 Sawtooth increment value (12.4 bit format) 16 16 0 65535 STMODR STMODR Sawtooth Mode register 0x60 0x20 read-write 0x00000000 2 0x10 1-2 STRSTTRIGSEL%s DAC Channel 1 Sawtooth Reset trigger selection 0 4 STRSTTRIGSEL1 Swtrig Software trigger 0 Tim1or8Trgo Timer 8 (DAC1 1 Tim7Trgo Timer 7 TRGO event 2 Tim15Trgo Timer 15 TRGO event 3 Tim2Trgo Timer 2 TRGO event 4 Tim4Trgo Timer 4 TRGO event 5 Exti9 EXTI line 9 6 Tim6Trgo Timer 6 TRGO event 7 Tim3Trgo Timer 3 TRGO event 8 HrtimDacReset1 hrtim_dac_reset_trg1 9 HrtimDacReset2 hrtim_dac_reset_trg2 10 HrtimDacReset3 hrtim_dac_reset_trg3 11 HrtimDacReset4 hrtim_dac_reset_trg4 12 HrtimDacReset5 hrtim_dac_reset_trg5 13 HrtimDacReset6 hrtim_dac_reset_trg6 14 HrtimDacX hrtim_dac_trg1 (DAC1 15 2 0x10 1-2 STINCTRIGSEL%s DAC Channel %s Sawtooth Increment trigger selection 8 4 STINCTRIGSEL1 Swtrig Software sawtooth increment trigger 0 Tim1or8Trgo Timer 8 (DAC1 1 Tim7Trgo Timer 7 TRGO event 2 Tim15Trgo Timer 15 TRGO event 3 Tim2Trgo Timer 2 TRGO event 4 Tim4Trgo Timer 4 TRGO event 5 Exti10 EXTI line 10 6 Tim6Trgo Timer 6 TRGO event 7 Tim3Trgo Timer 3 TRGO event 8 HrtimDacStep1 hrtim_dac_step_trg1 9 HrtimDacStep2 hrtim_dac_step_trg2 10 HrtimDacStep3 hrtim_dac_step_trg3 11 HrtimDacStep4 hrtim_dac_step_trg4 12 HrtimDacStep5 hrtim_dac_step_trg5 13 HrtimDacStep6 hrtim_dac_step_trg6 14 DAC2 0x50000C00 DAC3 0x50001000 DAC4 0x50001400 ADC1 Analog-to-Digital Converter ADC 0x50000000 0x0 0xD0 registers ADC1_2 ADC1 and ADC2 global interrupt 18 ISR ISR interrupt and status register 0x0 0x20 read-write 0x00000000 JQOVF Injected context queue overflow 10 1 oneToClear JQOVFR read NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 JQOVFW write Clear Clear injected context queue overflow flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 oneToClear AWD1R read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD1W write Clear Clear analog watchdog event occurred flag 1 JEOS Injected channel end of sequence flag 6 1 oneToClear JEOSR read NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 JEOSW write Clear Clear Injected sequence complete flag 1 JEOC Injected channel end of conversion flag 5 1 oneToClear JEOCR read NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOCW write Clear Clear injected conversion complete flag 1 OVR ADC overrun 4 1 oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear overrun occurred flag 1 EOS End of regular sequence flag 3 1 oneToClear EOSR read NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 EOSW write Clear Clear regular sequence complete flag 1 EOC End of conversion flag 2 1 oneToClear EOCR read NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOCW write Clear Clear regular conversion complete flag 1 EOSMP End of sampling flag 1 1 oneToClear EOSMPR read NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOSMPW write Clear Clear end of sampling phase reached flag 1 ADRDY ADC ready 0 1 oneToClear ADRDYR read NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 ADRDYW write Clear Clear ADC is ready to start conversion flag 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 JQOVFIE Injected context queue overflow interrupt enable 10 1 JQOVFIE Disabled Injected context queue overflow interrupt disabled 0 Enabled Injected context queue overflow interrupt enabled 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 AWD1IE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 JEOSIE End of injected sequence of conversions interrupt enable 6 1 JEOSIE Disabled End of injected sequence interrupt disabled 0 Enabled End of injected sequence interrupt enabled 1 JEOCIE End of injected conversion interrupt enable 5 1 JEOCIE Disabled End of injected conversion interrupt disabled 0 Enabled End of injected conversion interrupt enabled 1 OVRIE Overrun interrupt enable 4 1 OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled 1 EOSIE End of regular sequence of conversions interrupt enable 3 1 EOSIE Disabled End of regular sequence interrupt disabled 0 Enabled End of regular sequence interrupt enabled 1 EOCIE End of regular conversion interrupt enable 2 1 EOCIE Disabled End of regular conversion interrupt disabled 0 Enabled End of regular conversion interrupt enabled 1 EOSMPIE End of sampling flag interrupt enable for regular conversions 1 1 EOSMPIE Disabled End of regular conversion sampling phase interrupt disabled 0 Enabled End of regular conversion sampling phase interrupt enabled 1 ADRDYIE ADC ready interrupt enable 0 1 ADRDYIE Disabled ADC ready interrupt disabled 0 Enabled ADC ready interrupt enabled 1 CR CR control register 0x8 0x20 read-write 0x20000000 ADCAL ADC calibration 31 1 oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 ADCALDIF Differential mode for calibration 30 1 ADCALDIF SingleEnded Calibration for single-ended mode 0 Differential Calibration for differential mode 1 DEEPPWD Deep-power-down enable 29 1 DEEPPWD Disabled ADC not in Deep-power down 0 Enabled ADC in Deep-power-down (default reset state) 1 ADVREGEN ADC voltage regulator enable 28 1 ADVREGEN Disabled ADC voltage regulator disabled 0 Enabled ADC voltage regulator enabled 1 ADSTP ADC stop of regular conversion command 4 1 oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 JADSTP ADC stop of injected conversion command 5 1 oneToSet read write ADSTART ADC start of regular conversion 2 1 oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 JADSTART ADC start of injected conversion 3 1 oneToSet read write ADDIS ADC disable command 1 1 oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADEN ADC enable control 0 1 oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 CFGR CFGR configuration register 0xC 0x20 read-write 0x80000000 JQDIS Injected Queue disable 31 1 JQDIS Enabled Injected Queue enabled 0 Disabled Injected Queue disabled 1 AWD1CH Analog watchdog 1 channel selection 26 5 0 18 JAUTO Automatic injected group conversion 25 1 JAUTO Disabled Automatic injected group conversion disabled 0 Enabled Automatic injected group conversion enabled 1 JAWD1EN Analog watchdog 1 enable on injected channels 24 1 JAWD1EN Disabled Analog watchdog 1 disabled on injected channels 0 Enabled Analog watchdog 1 enabled on injected channels 1 AWD1EN Analog watchdog 1 enable on regular channels 23 1 AWD1EN Disabled Analog watchdog 1 disabled on regular channels 0 Enabled Analog watchdog 1 enabled on regular channels 1 AWD1SGL Enable the watchdog 1 on a single channel or on all channels 22 1 AWD1SGL All Analog watchdog 1 enabled on all channels 0 Single Analog watchdog 1 enabled on single channel selected in AWD1CH 1 JQM JSQR queue mode 21 1 JQM Mode0 JSQR Mode 0: Queue maintains the last written configuration into JSQR 0 Mode1 JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence 1 JDISCEN Discontinuous mode on injected channels 20 1 JDISCEN Disabled Discontinuous mode on injected channels disabled 0 Enabled Discontinuous mode on injected channels enabled 1 DISCNUM Discontinuous mode channel count 17 3 0 7 DISCEN Discontinuous mode for regular channels 16 1 DISCEN Disabled Discontinuous mode on regular channels disabled 0 Enabled Discontinuous mode on regular channels enabled 1 ALIGN Data alignment 15 1 ALIGN Right Right alignment 0 Left Left alignment 1 AUTDLY Delayed conversion mode 14 1 AUTDLY Off Auto delayed conversion mode off 0 On Auto delayed conversion mode on 1 CONT Single / continuous conversion mode for regular conversions 13 1 CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 OVRMOD Overrun mode 12 1 OVRMOD Preserve Preserve DR register when an overrun is detected 0 Overwrite Overwrite DR register when an overrun is detected 1 EXTEN External trigger enable and polarity selection for regular channels 10 2 EXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 EXTSEL External trigger selection for regular group 5 5 EXTSEL TIM1_CC1 Timer 1 CC1 event 0 TIM1_CC2 Timer 1 CC2 event 1 TIM1_CC3 Timer 1 CC3 event 2 TIM2_CC2 Timer 2 CC2 event 3 TIM3_TRGO Timer 3 TRGO event 4 EXTI11 EXTI line 11 6 HRTIM_ADCTRG1 HRTIM_ADCTRG1 event 7 HRTIM_ADCTRG3 HRTIM_ADCTRG3 event 8 TIM1_TRGO Timer 1 TRGO event 9 TIM1_TRGO2 Timer 1 TRGO2 event 10 TIM2_TRGO Timer 2 TRGO event 11 TIM6_TRGO Timer 6 TRGO event 13 TIM15_TRGO Timer 15 TRGO event 14 TIM3_CC4 Timer 3 CC4 event 15 RES Data resolution 3 2 RES Bits12 12-bit 0 Bits10 10-bit 1 Bits8 8-bit 2 Bits6 6-bit 3 DMACFG Direct memory access configuration 1 1 DMACFG OneShot DMA One Shot Mode selected 0 Circular DMA circular mode selected 1 DMAEN Direct memory access enable 0 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 CFGR2 CFGR2 configuration register 0x10 0x20 read-write 0x00000000 SMPTRIG Sampling time control trigger mode 27 1 SMPTRIG Disabled Sampling time control trigger mode disabled 0 Enabled Sampling time control trigger mode enabled 1 BULB Bulb sampling mode 26 1 BULB Disabled Bulb sampling mode disabled 0 Enabled Bulb sampling mode enabled. Immediately start sampling after last conversion finishes. 1 SWTRIG Software trigger bit for sampling time control trigger mode 25 1 SWTRIG Disabled End sampling period and start conversion 0 Enabled Start sampling period 1 GCOMP Gain compensation mode 16 1 GCOMP Disabled Regular ADC operating mode 0 Enabled Gain compensation enabled and applies to all channels 1 ROVSM Regular Oversampling mode 10 1 ROVSM Continued Oversampling is temporary stopped and continued after injection sequence 0 Resumed Oversampling is aborted and resumed from start after injection sequence 1 TROVS Triggered Regular Oversampling 9 1 TROVS Automatic All oversampled conversions for a channel are run following a trigger 0 Triggered Each oversampled conversion for a channel needs a new trigger 1 OVSS Oversampling shift 5 4 OVSS NoShift No right shift applied to oversampling result 0 Shift1 Shift oversampling result right by 1 bit 1 Shift2 Shift oversampling result right by 2 bits 2 Shift3 Shift oversampling result right by 3 bits 3 Shift4 Shift oversampling result right by 4 bits 4 Shift5 Shift oversampling result right by 5 bits 5 Shift6 Shift oversampling result right by 6 bits 6 Shift7 Shift oversampling result right by 7 bits 7 Shift8 Shift oversampling result right by 8 bits 8 OVSR Oversampling ratio 2 3 OVSR OS2 Oversampling ratio of 2 0 OS4 Oversampling ratio of 4 1 OS8 Oversampling ratio of 8 2 OS16 Oversampling ratio of 16 3 OS32 Oversampling ratio of 32 4 OS64 Oversampling ratio of 64 5 OS128 Oversampling ratio of 128 6 OS256 Oversampling ratio of 256 7 JOVSE Injected Oversampling Enable 1 1 JOVSE Disabled Injected oversampling disabled 0 Enabled Injected oversampling enabled 1 ROVSE Regular Oversampling Enable 0 1 ROVSE Disabled Regular oversampling disabled 0 Enabled Regular oversampling enabled 1 SMPR1 SMPR1 sample time register 1 0x14 0x20 read-write 0x00000000 10 0x3 0-9 SMP%s Channel %s sample time selection 0 3 SMP0 Cycles2_5 2.5 ADC clock cycles 0 Cycles6_5 6.5 ADC clock cycles 1 Cycles12_5 12.5 ADC clock cycles 2 Cycles24_5 24.5 ADC clock cycles 3 Cycles47_5 47.5 ADC clock cycles 4 Cycles92_5 92.5 ADC clock cycles 5 Cycles247_5 247.5 ADC clock cycles 6 Cycles640_5 640.5 ADC clock cycles 7 SMPPLUS Addition of one clock cycle to the sampling time 31 1 SMPPLUS KeepCycles The sampling time remains set to 2.5 ADC clock cycles remains 0 Add1Cycle 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers 1 SMPR2 SMPR2 sample time register 2 0x18 0x20 read-write 0x00000000 9 0x3 10-18 SMP%s Channel %s sample time selection 0 3 TR1 TR1 watchdog threshold register 1 0x20 0x20 read-write 0x0FFF0000 HT1 Analog watchdog 1 higher threshold 16 12 0 4095 AWDFILT Analog watchdog filtering parameter 12 3 LT1 Analog watchdog 1 lower threshold 0 12 0 4095 TR2 TR2 watchdog threshold register 0x24 0x20 read-write 0x00FF0000 HT2 Analog watchdog 2 higher threshold 16 8 0 255 LT2 Analog watchdog 2 lower threshold 0 8 0 255 TR3 TR3 watchdog threshold register 3 0x28 0x20 read-write 0x00FF0000 HT3 Analog watchdog 3 higher threshold 16 8 0 255 LT3 Analog watchdog 3 lower threshold 0 8 0 255 SQR1 SQR1 regular sequence register 1 0x30 0x20 read-write 0x00000000 4 0x6 1-4 SQ%s %s conversion in regular sequence 6 5 0 18 L Regular channel sequence length 0 4 0 15 SQR2 SQR2 regular sequence register 2 0x34 0x20 read-write 0x00000000 5 0x6 5-9 SQ%s %s conversion in regular sequence 0 5 SQR3 SQR3 regular sequence register 3 0x38 0x20 read-write 0x00000000 5 0x6 10-14 SQ%s %s conversion in regular sequence 0 5 SQR4 SQR4 regular sequence register 4 0x3C 0x20 read-write 0x00000000 2 0x6 15-16 SQ%s %s conversion in regular sequence 0 5 DR DR regular Data Register 0x40 0x20 read-only 0x00000000 RDATA Regular Data converted 0 16 JSQR JSQR injected sequence register 0x4C 0x20 read-write 0x00000000 4 0x6 1-4 JSQ%s %s conversion in injected sequence 9 5 0 19 JEXTEN External Trigger Enable and Polarity Selection for injected channels 7 2 JEXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 JEXTSEL External Trigger Selection for injected group 2 5 JEXTSEL TIM1_TRGO Timer 1 TRGO event 0 TIM1_CC4 Timer 1 CC4 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM2_CC1 Timer 2 CC1 event 3 TIM3_CC4 Timer 3 CC4 event 4 EXTI15 EXTI line 15 6 TIM1_TRGO2 Timer 1 TRGO2 event 8 TIM3_CC3 Timer 3 CC3 event 11 TIM3_TRGO Timer 3 TRGO event 12 TIM3_CC1 Timer 3 CC1 event 13 TIM6_TRGO Timer 6 TRGO event 14 TIM15_TRGO Timer 15 TRGO event 15 JL Injected channel sequence length 0 2 0 3 4 0x4 1-4 OFR%s OFR%s offset register %s 0x60 0x20 read-write 0x00000000 OFFSET_EN Offset X Enable 31 1 OFFSET_EN Disabled Offset disabled 0 Enabled Offset enabled 1 OFFSET_CH Channel selection for the data offset X 26 5 0 31 SATEN Saturation enable 25 1 OFFSETPOS Positive offset 24 1 OFFSET Data offset X for the channel programmed into bits OFFSET_CH 0 12 0 4095 4 0x4 1-4 JDR%s JDR%s injected data register %s 0x80 0x20 read-only 0x00000000 JDATA Injected data 0 16 AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 0x20 read-write 0x00000000 19 0x1 0-18 AWD2CH%s Analog watchdog 2 channel selection 0 1 AWD2CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 0x20 read-write 0x00000000 19 0x1 0-18 AWD3CH%s Analog watchdog 3 channel selection 0 1 AWD3CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 0x20 0x00000000 19 0x1 0-18 DIFSEL%s Differential mode for channel %s 0 1 DIFSEL0 SingleEnded Input channel is configured in single-ended mode 0 Differential Input channel is configured in differential mode 1 CALFACT CALFACT Calibration Factors 0xB4 0x20 read-write 0x00000000 CALFACT_D Calibration Factors in differential mode 16 7 0 127 CALFACT_S Calibration Factors In single-ended mode 0 7 0 127 GCOMP GCOMP Gain compensation Register 0xC0 0x20 read-write 0x00000000 GCOMPCOEFF Gain compensation coefficient 0 14 ADC2 0x50000100 ADC3 Analog-to-Digital Converter ADC 0x50000400 ADC3 ADC3 47 ADC4 0x50000500 ADC4 ADC4 61 ADC5 0x50000600 ADC5 ADC5 62 ADC12_Common Analog-to-Digital Converter ADC 0x50000300 0x0 0x11 registers CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 ADDRDY_MST ADDRDY_MST 0 1 EOSMP_MST EOSMP_MST 1 1 EOSMP_MST NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOC_MST EOC_MST 2 1 EOC_MST NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOS_MST EOS_MST 3 1 EOS_MST NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 OVR_MST OVR_MST 4 1 OVR_MST NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 JEOC_MST JEOC_MST 5 1 JEOC_MST NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOS_MST JEOS_MST 6 1 JEOS_MST NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 AWD1_MST AWD1_MST 7 1 AWD1_MST NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD2_MST AWD2_MST 8 1 AWD3_MST AWD3_MST 9 1 JQOVF_MST JQOVF_MST 10 1 JQOVF_MST NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 ADRDY_SLV ADRDY_SLV 16 1 ADRDY_SLV NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 EOSMP_SLV EOSMP_SLV 17 1 EOC_SLV End of regular conversion of the slave ADC 18 1 EOS_SLV End of regular sequence flag of the slave ADC 19 1 OVR_SLV Overrun flag of the slave ADC 20 1 JEOC_SLV End of injected conversion flag of the slave ADC 21 1 JEOS_SLV End of injected sequence flag of the slave ADC 22 1 AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC 26 1 CCR CCR ADC common control register 0x8 0x20 read-write 0x00000000 DUAL Dual ADC mode selection 0 5 DUAL Independent Independent mode 0 DualRJ Dual, combined regular simultaneous + injected simultaneous mode 1 DualRA Dual, combined regular simultaneous + alternate trigger mode 2 DualIJ Dual, combined interleaved mode + injected simultaneous mode 3 DualJ Dual, injected simultaneous mode only 5 DualR Dual, regular simultaneous mode only 6 DualI Dual, interleaved mode only 7 DualA Dual, alternate trigger mode only 9 DELAY Delay between 2 sampling phases 8 4 0 15 DMACFG DMA configuration (for multi-ADC mode) 13 1 MDMA Direct memory access mode for multi ADC mode 14 2 CKMODE ADC clock mode 16 2 CKMODE Asynchronous Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock 0 SyncDiv1 Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck 1 SyncDiv2 Use AHB clock rcc_hclk3 divided by 2 2 SyncDiv4 Use AHB clock rcc_hclk3 divided by 4 3 VREFEN VREFINT enable 22 1 VREFEN Disabled V_REFINT channel disabled 0 Enabled V_REFINT channel enabled 1 VSENSESEL VTS selection 23 1 VSENSESEL Disabled Temperature sensor channel disabled 0 Enabled Temperature sensor channel enabled 1 VBATSEL VBAT selection 24 1 VBATSEL Disabled V_BAT channel disabled 0 Enabled V_BAT channel enabled 1 PRESC ADC prescaler 18 4 CDR CDR ADC common regular data register for dual and triple modes 0xC 0x20 read-only 0x00000000 RDATA_SLV Regular data of the slave ADC 16 16 RDATA_MST Regular data of the master ADC 0 16 ADC345_Common 0x50000700 FMAC Filter Math Accelerator FMAC 0x40021400 0x0 0xC00 registers FMAC FMAC 101 X1BUFCFG X1BUFCFG FMAC X1 Buffer Configuration register 0x0 0x20 read-write 0x00000000 X1_BASE X1_BASE 0 8 X1_BUF_SIZE X1_BUF_SIZE 8 8 FULL_WM FULL_WM 24 2 X2BUFCFG X2BUFCFG FMAC X2 Buffer Configuration register 0x4 0x20 read-write 0x00000000 X2_BASE X1_BASE 0 8 X2_BUF_SIZE X1_BUF_SIZE 8 8 YBUFCFG YBUFCFG FMAC Y Buffer Configuration register 0x8 0x20 read-write 0x00000000 Y_BASE X1_BASE 0 8 Y_BUF_SIZE X1_BUF_SIZE 8 8 EMPTY_WM EMPTY_WM 24 2 PARAM PARAM FMAC Parameter register 0xC 0x20 read-write 0x00000000 START START 31 1 FUNC FUNC 24 7 R R 16 8 Q Q 8 8 P P 0 8 CR CR FMAC Control register 0x10 0x20 read-write 0x00000000 RESET RESET 16 1 CLIPEN CLIPEN 15 1 DMAWEN DMAWEN 9 1 DMAREN DMAREN 8 1 SATIEN SATIEN 4 1 UNFLIEN UNFLIEN 3 1 OVFLIEN OVFLIEN 2 1 WIEN WIEN 1 1 RIEN RIEN 0 1 SR SR FMAC Status register 0x14 0x20 read-only 0x00000000 YEMPTY YEMPTY 0 1 X1FULL X1FULL 1 1 OVFL OVFL 8 1 UNFL UNFL 9 1 SAT SAT 10 1 WDATA WDATA FMAC Write Data register 0x18 0x20 write-only 0x00000000 WDATA WDATA 0 16 RDATA RDATA FMAC Read Data register 0x1C 0x20 read-only 0x00000000 RDATA RDATA 0 16 CORDIC CORDIC Co-processor CORDIC 0x40020C00 0x0 0x400 registers Cordic Cordic 100 CSR CSR CORDIC Control Status register 0x0 0x20 read-write 0x00000000 FUNC FUNC 0 4 FUNC Cosine Cosine function 0 Sine Sine function 1 Phase Phase function 2 Modulus Modulus function 3 Arctangent Arctangent function 4 HyperbolicCosine Hyperbolic Cosine function 5 HyperbolicSine Hyperbolic Sine function 6 Arctanh Arctanh function 7 NaturalLogarithm Natural Logarithm function 8 SquareRoot Square Root function 9 PRECISION Precision (number of iterations/cycles) required 4 4 PRECISION Iters4 4 iterations 1 Iters8 8 iterations 2 Iters12 12 iterations 3 Iters16 16 iterations 4 Iters20 20 iterations 5 Iters24 24 iterations 6 Iters28 28 iterations 7 Iters32 32 iterations 8 Iters36 36 iterations 9 Iters40 40 iterations 10 Iters44 44 iterations 11 Iters48 48 iterations 12 Iters52 52 iterations 13 Iters56 56 iterations 14 Iters60 60 iterations 15 SCALE Scaling factor (2^-n for arguments, 2^n for results) 8 3 0 7 IEN IEN 16 1 IEN Disabled Disable interrupt request generation 0 Enabled Enable interrupt request generation 1 DMAREN DMAREN 17 1 DMAREN Disabled No DMA channel reads are generated 0 Enabled Read requests are generated on the DMA channel when RRDY flag is set 1 DMAWEN DMAWEN 18 1 DMAWEN Disabled No DMA channel writes are generated 0 Enabled Write requests are generated on the DMA channel when no operation is pending 1 NRES NRES 19 1 NRES Num1 Only single result value will be returned. After a single read RRDY will be automatically cleared 0 Num2 Two return reads need to be performed. After two reads RRDY will be automatically cleared 1 NARGS NARGS 20 1 NARGS Num1 Only single argument write is needed for next calculation 0 Num2 Two argument writes need to be performed for next calculation 1 RESSIZE RESSIZE 21 1 RESSIZE Bits32 Use 32 bit output values 0 Bits16 Use 16 bit output values 1 ARGSIZE ARGSIZE 22 1 ARGSIZE Bits32 Use 32 bit input values 0 Bits16 Use 16 bit input values 1 RRDY RRDY 31 1 RRDYR read NotReady Results from computation are not read 0 Ready Results are ready, this flag will be automatically cleared once value is read 1 WDATA WDATA CORDIC argument register 0x4 0x20 read-write 0x00000000 ARG ARG 0 32 0 4294967295 RDATA RDATA CORDIC result register 0x8 0x20 read-only 0x00000000 RES RES 0 32 0 4294967295 SAI Serial audio interface SAI 0x40015400 0x0 0x400 registers SAI SAI 76 2 0x20 A,B CH%s Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR 0x4 CR1 ACR1 AConfiguration register 1 0x0 0x20 read-write 0x00000040 MCKEN MCKEN 27 1 OSR OSR 26 1 MCKDIV Master clock divider 20 6 NODIV No divider 19 1 NODIV MasterClock MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value 0 NoDiv MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. 1 DMAEN DMA enable 17 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 SAIEN Audio block A enable 16 1 SAIEN Disabled SAI audio block disabled 0 Enabled SAI audio block enabled 1 OUTDRIV Output drive 13 1 OUTDRIV OnStart Audio block output driven when SAIEN is set 0 Immediately Audio block output driven immediately after the setting of this bit 1 MONO Mono mode 12 1 MONO Stereo Stereo mode 0 Mono Mono mode 1 SYNCEN Synchronization enable 10 2 SYNCEN Asynchronous audio sub-block in asynchronous mode 0 Internal audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode 1 External audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode 2 CKSTR Clock strobing edge 9 1 CKSTR FallingEdge Data strobing edge is falling edge of SCK 0 RisingEdge Data strobing edge is rising edge of SCK 1 LSBFIRST Least significant bit first 8 1 LSBFIRST MsbFirst Data are transferred with MSB first 0 LsbFirst Data are transferred with LSB first 1 DS Data size 5 3 DS Bit8 8 bits 2 Bit10 10 bits 3 Bit16 16 bits 4 Bit20 20 bits 5 Bit24 24 bits 6 Bit32 32 bits 7 PRTCFG Protocol configuration 2 2 PRTCFG Free Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol 0 Spdif SPDIF protocol 1 Ac97 ACâ97 protocol 2 MODE Audio block mode 0 2 MODE MasterTx Master transmitter 0 MasterRx Master receiver 1 SlaveTx Slave transmitter 2 SlaveRx Slave receiver 3 CR2 ACR2 AConfiguration register 2 0x4 0x20 read-write 0x00000000 COMP Companding mode 14 2 read-write COMP NoCompanding No companding algorithm 0 MuLaw Î¼-Law algorithm 2 ALaw A-Law algorithm 3 CPL Complement bit 13 1 read-write CPL OnesComplement 1âs complement representation 0 TwosComplement 2âs complement representation 1 MUTECNT Mute counter 7 6 read-write MUTEVAL Mute value 6 1 read-write MUTEVAL SendZero Bit value 0 is sent during the mute mode 0 SendLast Last values are sent during the mute mode 1 MUTE Mute 5 1 read-write MUTE Disabled No mute mode 0 Enabled Mute mode enabled 1 TRIS Tristate management on data line 4 1 read-write FFLUSH FIFO flush 3 1 write-only FFLUSH NoFlush No FIFO flush 0 Flush FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared 1 FTH FIFO threshold 0 3 read-write FTH Empty FIFO empty 0 Quarter1 1â4 FIFO 1 Quarter2 1â2 FIFO 2 Quarter3 3â4 FIFO 3 Full FIFO full 4 FRCR AFRCR AFRCR 0x8 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 read-write FSOFF OnFirst FS is asserted on the first bit of the slot 0 0 BeforeFirst FS is asserted one bit before the first bit of the slot 0 1 FSPOL Frame synchronization polarity 17 1 read-write FSPOL FallingEdge FS is active low (falling edge) 0 RisingEdge FS is active high (rising edge) 1 FSDEF Frame synchronization definition 16 1 read-write FSALL Frame synchronization active level length 8 7 read-write FRL Frame length 0 8 read-write SLOTR ASLOTR ASlot register 0xC 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 SLOTEN Inactive Inactive slot 0 Active Active slot 1 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 SLOTSZ DataSize The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) 0 Bit16 16-bit 1 Bit32 32-bit 2 FBOFF First bit offset 0 5 IM AIM AInterrupt mask register2 0x10 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 LFSDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 AFSDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 CNRDYIE Codec not ready interrupt enable 4 1 CNRDYIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 FREQIE FIFO request interrupt enable 3 1 FREQIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 WCKCFGIE Wrong clock configuration interrupt enable 2 1 WCKCFGIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 MUTEDETIE Mute detection interrupt enable 1 1 MUTEDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 OVRUDRIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 SR ASR AStatus register 0x14 0x20 read-only 0x00000008 FLVL FIFO level threshold 16 3 FLVLR Empty FIFO empty 0 Quarter1 FIFO <= 1â4 but not empty 1 Quarter2 1â4 < FIFO <= 1â2 2 Quarter3 1â2 < FIFO <= 3â4 3 Quarter4 3â4 < FIFO but not full 4 Full FIFO full 5 LFSDET Late frame synchronization detection 6 1 LFSDETR NoError No error 0 NoSync Frame synchronization signal is not present at the right time 1 AFSDET Anticipated frame synchronization detection 5 1 AFSDETR NoError No error 0 EarlySync Frame synchronization signal is detected earlier than expected 1 CNRDY Codec not ready 4 1 CNRDYR Ready External ACâ97 Codec is ready 0 NotReady External ACâ97 Codec is not ready 1 FREQ FIFO request 3 1 FREQR NoRequest No FIFO request 0 Request FIFO request to read or to write the SAI_xDR 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 WCKCFGR Correct Clock configuration is correct 0 Wrong Clock configuration does not respect the rule concerning the frame length specification 1 MUTEDET Mute detection 1 1 MUTEDETR NoMute No MUTE detection on the SD input line 0 Mute MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame 1 OVRUDR Overrun / underrun 0 1 OVRUDRR NoError No overrun/underrun error 0 Overrun Overrun/underrun error detection 1 CLRFR ACLRFR AClear flag register 0x18 0x20 write-only 0x00000000 CLFSDET Clear late frame synchronization detection flag 6 1 CLFSDETW Clear Clears the LFSDET flag 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CAFSDETW Clear Clears the AFSDET flag 1 CCNRDY Clear codec not ready flag 4 1 CCNRDYW Clear Clears the CNRDY flag 1 CWCKCFG Clear wrong clock configuration flag 2 1 CWCKCFGW Clear Clears the WCKCFG flag 1 CMUTEDET Mute detection flag 1 1 CMUTEDETW Clear Clears the MUTEDET flag 1 COVRUDR Clear overrun / underrun 0 1 COVRUDRW Clear Clears the OVRUDR flag 1 DR ADR AData register 0x1C 0x20 read-write 0x00000000 DATA Data 0 32 PDMCR PDMCR PDM control register 0x44 0x20 read-write 0x00000000 PDMEN PDMEN 0 1 MICNBR MICNBR 4 2 4 0x1 1-4 CKEN%s Clock enable of bitstream clock number %s 8 1 PDMDLY PDMDLY PDM delay register 0x48 0x20 read-write 0x00000000 4 0x8 1-4 DLYM%sL Delay line adjust for first microphone of pair %s 0 3 4 0x8 1-4 DLYM%sR Delay line adjust for second microphone of pair %s 4 3 TAMP Tamper and backup registers TAMP 0x40002400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0xFFFF0000 TAMP1E TAMP1E 0 1 TAMP2E TAMP2E 1 1 TAMP3E TAMP2E 2 1 ITAMP3E ITAMP3E 18 1 ITAMP4E ITAMP4E 19 1 ITAMP5E ITAMP5E 20 1 ITAMP6E ITAMP6E 21 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 TAMP1NOER TAMP1NOER 0 1 TAMP2NOER TAMP2NOER 1 1 TAMP3NOER TAMP3NOER 2 1 TAMP1MSK TAMP1MSK 16 1 TAMP2MSK TAMP2MSK 17 1 TAMP3MSK TAMP3MSK 18 1 TAMP1TRG TAMP1TRG 24 1 TAMP2TRG TAMP2TRG 25 1 TAMP3TRG TAMP3TRG 26 1 FLTCR FLTCR TAMP filter control register 0xC 0x20 read-write 0x00000000 TAMPFREQ TAMPFREQ 0 3 TAMPFLT TAMPFLT 3 2 TAMPPRCH TAMPPRCH 5 2 TAMPPUDIS TAMPPUDIS 7 1 IER IER TAMP interrupt enable register 0x2C 0x20 read-write 0x00000000 TAMP1IE TAMP1IE 0 1 TAMP2IE TAMP2IE 1 1 TAMP3IE TAMP3IE 2 1 ITAMP3IE ITAMP3IE 18 1 ITAMP4IE ITAMP4IE 19 1 ITAMP5IE ITAMP5IE 20 1 ITAMP6IE ITAMP6IE 21 1 SR SR TAMP status register 0x30 0x20 read-only 0x00000000 TAMP1F TAMP1F 0 1 TAMP2F TAMP2F 1 1 TAMP3F TAMP3F 2 1 ITAMP3F ITAMP3F 18 1 ITAMP4F ITAMP4F 19 1 ITAMP5F ITAMP5F 20 1 ITAMP6F ITAMP6F 21 1 MISR MISR TAMP masked interrupt status register 0x34 0x20 read-only 0x00000000 TAMP1MF TAMP1MF: 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 ITAMP3MF ITAMP3MF 18 1 ITAMP4MF ITAMP4MF 19 1 ITAMP5MF ITAMP5MF 20 1 ITAMP6MF ITAMP6MF 21 1 SCR SCR TAMP status clear register 0x3C 0x20 read-write 0x00000000 CTAMP1F CTAMP1F 0 1 CTAMP2F CTAMP2F 1 1 CTAMP3F CTAMP3F 2 1 CITAMP3F CITAMP3F 18 1 CITAMP4F CITAMP4F 19 1 CITAMP5F CITAMP5F 20 1 CITAMP6F CITAMP6F 21 1 32 0x4 0-31 BKP%sR BKP%sR TAMP backup register 0x100 0x20 read-write 0x00000000 BKP BKP 0 32 FDCAN FDCAN FDCAN 0x4000A400 0x0 0x400 registers CREL CREL FDCAN core release register 0x0 0x20 0x32141218 0xFFFFFFFF DAY 18 0 8 read-only MON 12 8 8 read-only YEAR 4 16 4 read-only SUBSTEP 1 20 4 read-only STEP 2 24 4 read-only REL 3 28 4 read-only ENDN ENDN FDCAN endian register 0x4 0x20 0x87654321 0xFFFFFFFF ETV Endianness test value The endianness test value is 0x8765 4321. 0 32 read-only DBTP DBTP FDCAN data bit timing and prescaler register 0xC 0x20 0x00000A33 0xFFFFFFFF DSJW Synchronization jump width Must always be smaller than DTSEG2, valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1: tSJW = (DSJW + 1) x tq. 0 4 read-write DTSEG2 Data time segment after sample point Valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS2 = (DTSEG2 + 1) x tq. 4 4 read-write DTSEG1 Data time segment before sample point Valid values are 0 to 31. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS1 = (DTSEG1 + 1) x tq. 8 5 read-write DBRP Data bit rate prescaler The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1. 16 5 read-write TDC Transceiver delay compensation 23 1 read-write TEST TEST FDCAN test register 0x10 0x20 0x00000000 0xFFFFFFFF LBCK Loop back mode 4 1 read-write TX Control of transmit pin 5 2 read-write RX Receive pin Monitors the actual value of pin FDCANx_RX 7 1 read-only RWD RWD FDCAN RAM watchdog register 0x14 0x20 0x00000000 0xFFFFFFFF WDC Watchdog configuration Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of FDCAN_CCCR register are set to 1. 0 8 read-write WDV Watchdog value Actual message RAM watchdog counter value. 8 8 read-only CCCR CCCR FDCAN CC control register 0x18 0x20 0x00000001 0xFFFFFFFF INIT Initialization 0 1 read-write CCE Configuration change enable 1 1 read-write ASM ASM restricted operation mode The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted operation Mode after it has received a valid frame. In the optional Restricted operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time. 2 1 read-write CSA Clock stop acknowledge 3 1 read-only CSR Clock stop request 4 1 read-write MON Bus monitoring mode Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time. 5 1 read-write DAR Disable automatic retransmission 6 1 read-write TEST Test mode enable 7 1 read-write FDOE FD operation enable 8 1 read-write BRSE FDCAN bit rate switching 9 1 read-write PXHD Protocol exception handling disable 12 1 read-write EFBI Edge filtering during bus integration 13 1 read-write TXP If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. 14 1 read-write NISO Non ISO operation If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 15 1 read-write NBTP NBTP FDCAN nominal bit timing and prescaler register 0x1C 0x20 0x06000A03 0xFFFFFFFF NTSEG2 Nominal time segment after sample point Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. 0 7 read-write NTSEG1 Nominal time segment before sample point Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 8 8 read-write NBRP Bit rate prescaler Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 16 9 read-write NSJW Nominal (re)synchronization jump width Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 25 7 read-write TSCC TSCC FDCAN timestamp counter configuration register 0x20 0x20 0x00000000 0xFFFFFFFF TSS Timestamp select These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 2 read-write TCP Timestamp counter prescaler 16 4 read-write TSCV TSCV FDCAN timestamp counter value register 0x24 0x20 0x00000000 0xFFFFFFFF TSC Timestamp counter 0 16 read-write TOCC TOCC FDCAN timeout counter configuration register 0x28 0x20 0xFFFF0000 0xFFFFFFFF ETOC Timeout counter enable This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 1 read-write TOS Timeout select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 1 2 read-write TOP Timeout period Start value of the timeout counter (down-counter). Configures the timeout period. 16 16 read-write TOCV TOCV FDCAN timeout counter value register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF TOC Timeout counter 0 16 read-write ECR ECR FDCAN error counter register 0x40 0x20 0x00000000 0xFFFFFFFF TEC Transmit error counter Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 0 8 read-only REC Receive error counter Actual state of the receive error counter, values between 0 and 127. 8 7 read-only RP Receive error passive 15 1 read-only CEL CAN error logging The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read. 16 8 read-write PSR PSR FDCAN protocol status register 0x44 0x20 0x00000707 0xFFFFFFFF LEC Last error code The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. Access type is RS: set on read. 0 3 read-write ACT Activity Monitors the modules CAN communication state. 3 2 read-only EP Error passive 5 1 read-only EW Warning Sstatus 6 1 read-only BO Bus_Off status 7 1 read-only DLEC Data last error code Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read. 8 3 read-write RESI ESI flag of last received FDCAN message This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read. 11 1 read-write RBRS BRS flag of last received FDCAN message This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read. 12 1 read-write REDL Received FDCAN message This bit is set independent of acceptance filtering. Access type is RX: reset on read. 13 1 read-write PXE Protocol exception event 14 1 read-write TDCV Transmitter delay compensation value Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. 16 7 read-only TDCR TDCR FDCAN transmitter delay compensation register 0x48 0x20 0x00000000 0xFFFFFFFF TDCF Transmitter delay compensation filter window length Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 7 read-write TDCO Transmitter delay compensation offset Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 8 7 read-write IR IR FDCAN interrupt register 0x50 0x20 0x00000000 0xFFFFFFFF RF0N Rx FIFO 0 new message 0 1 read-write RF0F Rx FIFO 0 full 1 1 read-write RF0L Rx FIFO 0 message lost 2 1 read-write RF1N Rx FIFO 1 new message 3 1 read-write RF1F Rx FIFO 1 full 4 1 read-write RF1L Rx FIFO 1 message lost 5 1 read-write HPM High-priority message 6 1 read-write TC Transmission completed 7 1 read-write TCF Transmission cancellation finished 8 1 read-write TFE Tx FIFO empty 9 1 read-write TEFN Tx event FIFO New Entry 10 1 read-write TEFF Tx event FIFO full 11 1 read-write TEFL Tx event FIFO element lost 12 1 read-write TSW Timestamp wraparound 13 1 read-write MRAF Message RAM access failure The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted operation Mode (see Restricted operation mode). To leave Restricted operation Mode, the Host CPU has to reset CCCR.ASM. 14 1 read-write TOO Timeout occurred 15 1 read-write ELO Error logging overflow 16 1 read-write EP Error passive 17 1 read-write EW Warning status 18 1 read-write BO Bus_Off status 19 1 read-write WDI Watchdog interrupt 20 1 read-write PEA Protocol error in arbitration phase (nominal bit time is used) 21 1 read-write PED Protocol error in data phase (data bit time is used) 22 1 read-write ARA Access to reserved address 23 1 read-write IE IE FDCAN interrupt enable register 0x54 0x20 0x00000000 0xFFFFFFFF RF0NE Rx FIFO 0 new message interrupt enable 0 1 read-write RF0FE Rx FIFO 0 full interrupt enable 1 1 read-write RF0LE Rx FIFO 0 message lost interrupt enable 2 1 read-write RF1NE Rx FIFO 1 new message interrupt enable 3 1 read-write RF1FE Rx FIFO 1 full interrupt enable 4 1 read-write RF1LE Rx FIFO 1 message lost interrupt enable 5 1 read-write HPME High-priority message interrupt enable 6 1 read-write TCE Transmission completed interrupt enable 7 1 read-write TCFE Transmission cancellation finished interrupt enable 8 1 read-write TFEE Tx FIFO empty interrupt enable 9 1 read-write TEFNE Tx event FIFO new entry interrupt enable 10 1 read-write TEFFE Tx event FIFO full interrupt enable 11 1 read-write TEFLE Tx event FIFO element lost interrupt enable 12 1 read-write TSWE Timestamp wraparound interrupt enable 13 1 read-write MRAFE Message RAM access failure interrupt enable 14 1 read-write TOOE Timeout occurred interrupt enable 15 1 read-write ELOE Error logging overflow interrupt enable 16 1 read-write EPE Error passive interrupt enable 17 1 read-write EWE Warning status interrupt enable 18 1 read-write BOE Bus_Off status 19 1 read-write WDIE Watchdog interrupt enable 20 1 read-write PEAE Protocol error in arbitration phase enable 21 1 read-write PEDE Protocol error in data phase enable 22 1 read-write ARAE Access to reserved address enable 23 1 read-write ILS ILS FDCAN interrupt line select register 0x58 0x20 0x00000000 0xFFFFFFFF RXFIFO0 RX FIFO bit grouping the following interruption RF0LL: Rx FIFO 0 message lost interrupt line RF0FL: Rx FIFO 0 full interrupt line RF0NL: Rx FIFO 0 new message interrupt line 0 1 read-write RXFIFO1 RX FIFO bit grouping the following interruption RF1LL: Rx FIFO 1 message lost interrupt line RF1FL: Rx FIFO 1 full interrupt line RF1NL: Rx FIFO 1 new message interrupt line 1 1 read-write SMSG Status message bit grouping the following interruption TCFL: Transmission cancellation finished interrupt line TCL: Transmission completed interrupt line HPML: High-priority message interrupt line 2 1 read-write TFERR Tx FIFO ERROR grouping the following interruption TEFLL: Tx event FIFO element lost interrupt line TEFFL: Tx event FIFO full interrupt line TEFNL: Tx event FIFO new entry interrupt line TFEL: Tx FIFO empty interrupt line 3 1 read-write MISC Interrupt regrouping the following interruption TOOL: Timeout occurred interrupt line MRAFL: Message RAM access failure interrupt line TSWL: Timestamp wraparound interrupt line 4 1 read-write BERR Bit and line error grouping the following interruption EPL Error passive interrupt line ELOL: Error logging overflow interrupt line 5 1 read-write PERR Protocol error grouping the following interruption ARAL: Access to reserved address line PEDL: Protocol error in data phase line PEAL: Protocol error in arbitration phase line WDIL: Watchdog interrupt line BOL: Bus_Off status EWL: Warning status interrupt line 6 1 read-write ILE ILE FDCAN interrupt line enable register 0x5C 0x20 0x00000000 0xFFFFFFFF EINT0 Enable interrupt line 0 0 1 read-write EINT1 Enable interrupt line 1 1 1 read-write RXGFC RXGFC FDCAN global filter configuration register 0x80 0x20 0x00000000 0xFFFFFFFF RRFE Reject remote frames extended These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 1 read-write RRFS Reject remote frames standard These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 1 1 read-write ANFE Accept non-matching frames extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 2 2 read-write ANFS Accept Non-matching frames standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 4 2 read-write F1OM FIFO 1 operation mode (overwrite or blocking) This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 8 1 read-write F0OM FIFO 0 operation mode (overwrite or blocking) This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 9 1 read-write LSS List size standard 1 to 28: Number of standard message ID filter elements >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 16 5 read-write LSE List size extended 1 to 8: Number of extended message ID filter elements >8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 24 4 read-write XIDAM XIDAM FDCAN extended ID and mask register 0x84 0x20 0x1FFFFFFF 0xFFFFFFFF EIDM Extended ID mask For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 29 read-write HPMS HPMS FDCAN high-priority message status register 0x88 0x20 0x00000000 0xFFFFFFFF BIDX Buffer index Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1. 0 3 read-only MSI Message storage indicator 6 2 read-only FIDX Filter index Index of matching filter element. Range is 0 to RXGFC[LSS] - 1 or RXGFC[LSE] - 1. 8 5 read-only FLST Filter list Indicates the filter list of the matching filter element. 15 1 read-only RXF0S RXF0S FDCAN Rx FIFO 0 status register 0x90 0x20 0x00000000 0xFFFFFFFF F0FL Rx FIFO 0 fill level Number of elements stored in Rx FIFO 0, range 0 to 3. 0 4 read-only F0GI Rx FIFO 0 get index Rx FIFO 0 read index pointer, range 0 to 2. 8 2 read-only F0PI Rx FIFO 0 put index Rx FIFO 0 write index pointer, range 0 to 2. 16 2 read-only F0F Rx FIFO 0 full 24 1 read-only RF0L Rx FIFO 0 message lost This bit is a copy of interrupt flag IR[RF0L]. When IR[RF0L] is reset, this bit is also reset. 25 1 read-only RXF0A RXF0A CAN Rx FIFO 0 acknowledge register 0x94 0x20 0x00000000 0xFFFFFFFF F0AI Rx FIFO 0 acknowledge index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This sets the Rx FIFO 0 get index RXF0S[F0GI] to F0AI + 1 and update the FIFO 0 fill level RXF0S[F0FL]. 0 3 read-write RXF1S RXF1S FDCAN Rx FIFO 1 status register 0x98 0x20 0x00000000 0xFFFFFFFF F1FL Rx FIFO 1 fill level Number of elements stored in Rx FIFO 1, range 0 to 3. 0 4 read-only F1GI Rx FIFO 1 get index Rx FIFO 1 read index pointer, range 0 to 2. 8 2 read-only F1PI Rx FIFO 1 put index Rx FIFO 1 write index pointer, range 0 to 2. 16 2 read-only F1F Rx FIFO 1 full 24 1 read-only RF1L Rx FIFO 1 message lost This bit is a copy of interrupt flag IR[RF1L]. When IR[RF1L] is reset, this bit is also reset. 25 1 read-only RXF1A RXF1A FDCAN Rx FIFO 1 acknowledge register 0x9C 0x20 0x00000000 0xFFFFFFFF F1AI Rx FIFO 1 acknowledge index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This sets the Rx FIFO 1 get index RXF1S[F1GI] to F1AI + 1 and update the FIFO 1 Fill Level RXF1S[F1FL]. 0 3 read-write TXBC TXBC FDCAN Tx buffer configuration register 0xC0 0x20 0x00000000 0xFFFFFFFF TFQM Tx FIFO/queue mode This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 24 1 read-write TXFQS TXFQS FDCAN Tx FIFO/queue status register 0xC4 0x20 0x00000003 0xFFFFFFFF TFFL Tx FIFO free level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC[TFQM] = 1). 0 3 read-only TFGI Tx FIFO get index Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC.TFQM = 1) 8 2 read-only TFQPI Tx FIFO/queue put index Tx FIFO/queue write index pointer, range 0 to 3 16 2 read-only TFQF Tx FIFO/queue full 21 1 read-only TXBRP TXBRP FDCAN Tx buffer request pending register 0xC8 0x20 0x00000000 0xFFFFFFFF TRP Transmission request pending Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0 3 read-only TXBAR TXBAR FDCAN Tx buffer add request register 0xCC 0x20 0x00000000 0xFFFFFFFF AR Add request Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0 3 read-write TXBCR TXBCR FDCAN Tx buffer cancellation request register 0xD0 0x20 0x00000000 0xFFFFFFFF CR Cancellation request Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset. 0 3 read-write TXBTO TXBTO FDCAN Tx buffer transmission occurred register 0xD4 0x20 0x00000000 0xFFFFFFFF TO Transmission occurred. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR. 0 3 read-only TXBCF TXBCF FDCAN Tx buffer cancellation finished register 0xD8 0x20 0x00000000 0xFFFFFFFF CF Cancellation finished Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR. 0 3 read-only TXBTIE TXBTIE FDCAN Tx buffer transmission interrupt enable register 0xDC 0x20 0x00000000 0xFFFFFFFF TIE Transmission interrupt enable Each Tx buffer has its own TIE bit. 0 3 read-write TXBCIE TXBCIE FDCAN Tx buffer cancellation finished interrupt enable register 0xE0 0x20 0x00000000 0xFFFFFFFF CFIE Cancellation finished interrupt enable. Each Tx buffer has its own CFIE bit. 0 3 read-write TXEFS TXEFS FDCAN Tx event FIFO status register 0xE4 0x20 0x00000000 0xFFFFFFFF EFFL Event FIFO fill level Number of elements stored in Tx event FIFO, range 0 to 3. 0 3 read-only EFGI Event FIFO get index Tx event FIFO read index pointer, range 0 to 3. 8 2 read-only EFPI Event FIFO put index Tx event FIFO write index pointer, range 0 to 3. 16 2 read-only EFF Event FIFO full 24 1 read-only TEFL Tx event FIFO element lost This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset. 0 No Tx event FIFO element lost 1 Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0. 25 1 read-only TXEFA TXEFA FDCAN Tx event FIFO acknowledge register 0xE8 0x20 0x00000000 0xFFFFFFFF EFAI Event FIFO acknowledge index After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS[EFGI] to EFAI + 1 and updates the FIFO 0 fill level TXEFS[EFFL]. 0 2 read-write CKDIV CKDIV FDCAN CFG clock divider register 0x100 0x20 0x00000000 0xFFFFFFFF PDIV input clock divider The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 4 read-write FDCAN1 0x40006400 FDCAN1_IT0 FDCAN1 interrupt 0 21 FDCAN1_IT1 FDCAN1 interrupt 1 22 FDCAN2 0x40006800 FDCAN2_IT0 FDCAN2 interrupt 0 86 FDCAN2_IT1 FDCAN2 interrupt 1 87 FDCAN3 0x40006C00 FDCAN3_IT0 FDCAN3 interrupt 0 88 FDCAN3_IT1 FDCAN3 interrupt 1 89 UCPD1 UCPD1 UCPD 0x4000A000 0x0 0x400 registers UCPD1 UCPD1 63 CFGR1 CFG1 UCPD configuration register 1 0x0 0x20 read-write 0x00000000 HBITCLKDIV HBITCLKDIV 0 6 0 63 IFRGAP IFRGAP 6 5 1 31 TRANSWIN TRANSWIN 11 5 1 31 PSC_USBPDCLK PSC_USBPDCLK 17 3 PSC_USBPDCLK Div1 Divide by 1 0 Div2 Divide by 2 1 Div4 Divide by 4 2 Div8 Divide by 8 3 Div16 Divide by 16 4 TXDMAEN TXDMAEN 29 1 TXDMAEN Disabled DMA mode for transmission disabled 0 Enabled DMA mode for transmission enabled 1 RXDMAEN RXDMAEN 30 1 RXDMAEN Disabled DMA mode for reception disabled 0 Enabled DMA mode for reception enabled 1 UCPDEN UCPDEN 31 1 UCPDEN Disabled UCPD peripheral disabled 0 Enabled UCPD peripheral enabled 1 RXORDSETEN0 SOP detection 20 1 RXORDSETEN0 Disabled Flag disabled 0 Enabled Flag enabled 1 RXORDSETEN1 SOP' detection 21 1 RXORDSETEN2 SOP'' detection 22 1 RXORDSETEN3 Hard Reset detection 23 1 RXORDSETEN4 Cable Detect reset 24 1 RXORDSETEN5 SOP'_Debug 25 1 RXORDSETEN6 SOP'' Debug 26 1 RXORDSETEN7 SOP extension #1 27 1 RXORDSETEN8 SOP extension #2 28 1 CFGR2 CFG2 UCPD configuration register 2 0x4 0x20 read-write 0x00000000 RXFILTDIS RXFILTDIS 0 1 RXFILTDIS Enabled Rx pre-filter enabled 0 Disabled Rx pre-filter disabled 1 RXFILT2N3 RXFILT2N3 1 1 RXFILT2N3 Samp3 3 samples 0 Samp2 2 samples 1 FORCECLK FORCECLK 2 1 FORCECLK NoForce Do not force clock request 0 Force Force clock request 1 WUPEN WUPEN 3 1 WUPEN Disabled Disabled 0 Enabled Enabled 1 CR CR UCPD configuration register 2 0xC 0x20 read-write 0x00000000 TXMODE TXMODE 0 2 TXMODE RegisterSet Transmission of Tx packet previously defined in other registers 0 CableReset Cable Reset sequence 1 BISTTest BIST test sequence (BIST Carrier Mode 2) 2 TXSEND TXSEND 2 1 TXSEND NoEffect No effect 0 Start Start Tx packet transmission 1 TXHRST TXHRST 3 1 TXHRST NoEffect No effect 0 Start Start Tx Hard Reset message 1 RXMODE RXMODE 4 1 RXMODE Normal Normal receive mode 0 BIST BIST receive mode (BIST test data mode) 1 PHYRXEN PHYRXEN 5 1 PHYRXEN Disabled USB Power Delivery receiver disabled 0 Enabled USB Power Delivery receiver enabled 1 PHYCCSEL PHYCCSEL 6 1 PHYCCSEL CC1 Use CC1 IO for Power Delivery communication 0 CC2 Use CC2 IO for Power Delivery communication 1 ANASUBMODE ANASUBMODE 7 2 ANASUBMODE Disabled Disabled 0 Rp_DefaultUSB Default USB Rp 1 Rp_1_5A 1.5A Rp 2 Rp_3A 3A Rp 3 ANAMODE ANAMODE 9 1 ANAMODE Source Source 0 Sink Sink 1 CCENABLE CCENABLE 10 2 CCENABLE Disabled Both PHYs disabled 0 CC1Enabled CC1 PHY enabled 1 CC2Enabled CC2 PHY enabled 2 BothEnabled CC1 and CC2 PHYs enabled 3 FRSRXEN FRSRXEN 16 1 FRSRXEN Disabled FRS Rx event detection disabled 0 Enabled FRS Rx event detection enabled 1 FRSTX FRSTX 17 1 FRSTX NoEffect No effect 0 Enabled FRS Tx signaling enabled 1 RDCH RDCH 18 1 RDCH NoEffect No effect 0 ConditionDrive Rdch condition drive 1 CC1TCDIS CC1TCDIS 20 1 CC1TCDIS Enabled Type-C detector on the CCx line enabled 0 Disabled Type-C detector on the CCx line disabled 1 CC2TCDIS CC2TCDIS 21 1 IMR IMR UCPD Interrupt Mask Register 0x10 0x20 read-write 0x00000000 TXISIE TXISIE 0 1 TXISIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TXMSGDISCIE TXMSGDISCIE 1 1 TXMSGSENTIE TXMSGSENTIE 2 1 TXMSGABTIE TXMSGABTIE 3 1 HRSTDISCIE HRSTDISCIE 4 1 HRSTSENTIE HRSTSENTIE 5 1 TXUNDIE TXUNDIE 6 1 RXNEIE RXNEIE 8 1 RXORDDETIE RXORDDETIE 9 1 RXHRSTDETIE RXHRSTDETIE 10 1 RXOVRIE RXOVRIE 11 1 RXMSGENDIE RXMSGENDIE 12 1 TYPECEVT1IE TYPECEVT1IE 14 1 TYPECEVT2IE TYPECEVT2IE 15 1 FRSEVTIE FRSEVTIE 20 1 SR SR UCPD Status Register 0x14 0x20 read-write 0x00000000 TXIS TXIS 0 1 TXIS NotRequired New Tx data write not required 0 Required New Tx data write required 1 TXMSGDISC TXMSGDISC 1 1 TXMSGDISC NotDiscarded No Tx message discarded 0 Discarded Tx message discarded 1 TXMSGSENT TXMSGSENT 2 1 TXMSGSENT NotCompleted No Tx message completed 0 Completed Tx message completed 1 TXMSGABT TXMSGABT 3 1 TXMSGABT NoAbort No transmit message abort 0 Abort Transmit message abort 1 HRSTDISC HRSTDISC 4 1 HRSTDISC NotDiscarded No Hard Reset discarded 0 Discarded Hard Reset discarded 1 HRSTSENT HRSTSENT 5 1 HRSTSENT NotSent No Hard Reset message sent 0 Sent Hard Reset message sent 1 TXUND TXUND 6 1 TXUND NoUnderrun No Tx data underrun detected 0 Underrun Tx data underrun detected 1 RXNE RXNE 8 1 RXNE Empty Rx data register empty 0 NotEmpty Rx data register not empty 1 RXORDDET RXORDDET 9 1 RXORDDET NoOrderedSet No ordered set detected 0 OrderedSet Ordered set detected 1 RXHRSTDET RXHRSTDET 10 1 RXHRSTDET NoHardReset Hard Reset not received 0 HardReset Hard Reset received 1 RXOVR RXOVR 11 1 RXOVR NoOverflow No overflow 0 Overflow Overflow 1 RXMSGEND RXMSGEND 12 1 RXMSGEND NoNewMessage No new Rx message received 0 NewMessage A new Rx message received 1 RXERR RXERR 13 1 RXERR NoError No error detected 0 Error Error(s) detected 1 TYPECEVT1 TYPECEVT1 14 1 TYPECEVT1 NoNewEvent No new event 0 NewEvent A new Type-C event occurred 1 TYPECEVT2 TYPECEVT2 15 1 TYPEC_VSTATE_CC1 TYPEC_VSTATE_CC1 16 2 TYPEC_VSTATE_CC1 Lowest Lowest 0 Low Low 1 High High 2 Highest Highest 3 TYPEC_VSTATE_CC2 TYPEC_VSTATE_CC2 18 2 FRSEVT FRSEVT 20 1 FRSEVT NoNewEvent No new event 0 NewEvent New FRS receive event occurred 1 ICR ICR UCPD Interrupt Clear Register 0x18 0x20 read-write 0x00000000 TXMSGDISCCF TXMSGDISCCF 1 1 TXMSGDISCCFW write Clear Clear flag in UCPD_SR 1 TXMSGSENTCF TXMSGSENTCF 2 1 TXMSGABTCF TXMSGABTCF 3 1 HRSTDISCCF HRSTDISCCF 4 1 HRSTSENTCF HRSTSENTCF 5 1 TXUNDCF TXUNDCF 6 1 RXORDDETCF RXORDDETCF 9 1 RXHRSTDETCF RXHRSTDETCF 10 1 RXOVRCF RXOVRCF 11 1 RXMSGENDCF RXMSGENDCF 12 1 TYPECEVT1CF TYPECEVT1CF 14 1 TYPECEVT2CF TYPECEVT2CF 15 1 FRSEVTCF FRSEVTCF 20 1 TX_ORDSETR TX_ORDSET UCPD Tx Ordered Set Type Register 0x1C 0x20 read-write 0x00000000 TXORDSET TXORDSET 0 20 0 1048575 TX_PAYSZR TX_PAYSZ UCPD Tx Paysize Register 0x20 0x20 read-write 0x00000000 TXPAYSZ TXPAYSZ 0 10 0 1023 TXDR TXDR UCPD Tx Data Register 0x24 0x20 read-write 0x00000000 TXDATA TXDATA 0 8 0 255 RX_ORDSETR RX_ORDSET UCPD Rx Ordered Set Register 0x28 0x20 read-only 0x00000000 RXORDSET RXORDSET 0 3 RXORDSET SOP SOP code detected in receiver 0 SOPPrime SOP' code detected in receiver 1 SOPDoublePrime SOP'' code detected in receiver 2 SOPPrimeDebug SOP'_Debug detected in receiver 3 SOPDoublePrimeDebug SOP''_Debug detected in receiver 4 CableReset Cable Reset detected in receiver 5 SOPExtension1 SOP extension #1 detected in receiver 6 SOPExtension2 SOP extension #2 detected in receiver 7 RXSOP3OF4 RXSOP3OF4 3 1 RXSOP3OF4 AllCorrect 4 correct K-codes out of 4 0 OneIncorrect 3 correct K-codes out of 4 1 RXSOPKINVALID RXSOPKINVALID 4 3 RXSOPKINVALID Valid No K-code corrupted 0 FirstCorrupted First K-code corrupted 1 SecondCorrupted Second K-code corrupted 2 ThirdCorrupted Third K-code corrupted 3 FourthCorrupted Fourth K-code corrupted 4 RX_PAYSZR RX_PAYSZ UCPD Rx Paysize Register 0x2C 0x20 read-only 0x00000000 RXPAYSZ RXPAYSZ 0 10 0 1023 RXDR RXDR UCPD Rx Data Register 0x30 0x20 read-only 0x00000000 RXDATA RXDATA 0 8 0 255 RX_ORDEXTR1 RX_ORDEXT1 UCPD Rx Ordered Set Extension Register 1 0x34 0x20 read-write 0x00000000 RXSOPX1 RXSOPX1 0 20 0 1048575 RX_ORDEXTR2 RX_ORDEXT2 UCPD Rx Ordered Set Extension Register 2 0x38 0x20 read-write 0x00000000 RXSOPX2 RXSOPX2 0 20 0 1048575 USB USB_FS_device USB 0x40005C00 0x0 0x400 registers 8 0x4 0-7 EP%sR EP%sR USB endpoint n register 0x0 0x20 read-write 0x00000000 EA EA 0 4 0 15 STAT_TX STAT_TX 4 2 read-write oneToToggle STAT_TXR read Disabled all transmission requests addressed to this endpoint are ignored 0 Stall the endpoint is stalled and all transmission requests result in a STALL handshake 1 Nak the endpoint is naked and all transmission requests result in a NAK handshake 2 Valid this endpoint is enabled for transmission 3 DTOG_TX DTOG_TX 6 1 oneToToggle CTR_TX CTR_TX 7 1 zeroToClear EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 EP_TYPE Bulk Bulk endpoint 0 Control Control endpoint 1 Iso Iso endpoint 2 Interrupt Interrupt endpoint 3 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 read-write oneToToggle STAT_RXR read Disabled all reception requests addressed to this endpoint are ignored 0 Stall the endpoint is stalled and all reception requests result in a STALL handshake 1 Nak the endpoint is naked and all reception requests result in a NAK handshake 2 Valid this endpoint is enabled for reception 3 DTOG_RX DTOG_RX 14 1 oneToToggle CTR_RX CTR_RX 15 1 zeroToClear CNTR CNTR USB control register 0x40 0x20 read-write 0x00000000 FRES FRES 0 1 FRES NoReset Clear USB reset 0 Reset Force a reset of the USB peripheral, exactly like a RESET signaling on the USB 1 PDWN PDWN 1 1 PDWN Disabled No power down 0 Enabled Enter power down mode 1 LP_MODE LP_MODE 2 1 LP_MODE Disabled No low-power mode 0 Enabled Enter low-power mode 1 FSUSP FSUSP 3 1 FSUSP NoEffect No effect 0 Suspend Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected 1 RESUME RESUME 4 1 RESUME Requested Resume requested 1 L1RESUME L1RESUME 5 1 L1RESUME Requested LPM L1 request requested 1 L1REQM L1REQM 7 1 L1REQM Disabled L1REQ Interrupt disabled 0 Enabled L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ESOFM ESOFM 8 1 ESOFM Disabled ESOF Interrupt disabled 0 Enabled ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 SOFM SOFM 9 1 SOFM Disabled SOF Interrupt disabled 0 Enabled SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 RESETM RESETM 10 1 RESETM Disabled RESET Interrupt disabled 0 Enabled RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 SUSPM SUSPM 11 1 SUSPM Disabled Suspend Mode Request SUSP Interrupt disabled 0 Enabled SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 WKUPM WKUPM 12 1 WKUPM Disabled WKUP Interrupt disabled 0 Enabled WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ERRM ERRM 13 1 ERRM Disabled ERR Interrupt disabled 0 Enabled ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 PMAOVRM PMAOVRM 14 1 PMAOVRM Disabled PMAOVR Interrupt disabled 0 Enabled PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 CTRM CTRM 15 1 CTRM Disabled Correct Transfer (CTR) Interrupt disabled 0 Enabled CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ISTR ISTR USB interrupt status register 0x44 0x20 read-write 0x00000000 EP_ID EP_ID 0 4 0 15 DIR DIR 4 1 DIR To Data transmitted by the USB peripheral to the host PC 0 From Data received by the USB peripheral from the host PC 1 L1REQ L1REQ 7 1 zeroToClear L1REQR read NotReceived LPM command to enter the L1 state is not received 0 Received LPM command to enter the L1 state is successfully received and acknowledged 1 L1REQW write Clear Clear flag 0 ESOF ESOF 8 1 zeroToClear ESOFR read NotExpectedStartOfFrame NotExpectedStartOfFrame 0 ExpectedStartOfFrame An SOF packet is expected but not received 1 ESOFW write Clear Clear flag 0 SOF SOF 9 1 zeroToClear SOFR read NotStartOfFrame NotStartOfFrame 0 StartOfFrame Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus 1 SOFW write Clear Clear flag 0 RESET RESET 10 1 zeroToClear RESETR read NotReset NotReset 0 Reset Peripheral detects an active USB RESET signal at its inputs 1 RESETW write Clear Clear flag 0 SUSP SUSP 11 1 zeroToClear SUSPR read NotSuspend NotSuspend 0 Suspend No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus 1 SUSPW write Clear Clear flag 0 WKUP WKUP 12 1 zeroToClear WKUPR read NotWakeup NotWakeup 0 Wakeup Activity is detected that wakes up the USB peripheral 1 WKUPW write Clear Clear flag 0 ERR ERR 13 1 zeroToClear ERRR read NotOverrun Errors are not occurred 0 Error One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred 1 ERRW write Clear Clear flag 0 PMAOVR PMAOVR 14 1 zeroToClear PMAOVRR read NotOverrun Overrun is not occurred 0 Overrun Microcontroller has not been able to respond in time to an USB memory request 1 PMAOVRW write Clear Clear flag 0 CTR CTR 15 1 CTR Completed Endpoint has successfully completed a transaction 1 FNR FNR USB frame number register 0x48 0x20 read-only 0x00000000 FN FN 0 11 0 2047 LSOF LSOF 11 2 0 3 LCK LCK 13 1 LCK Locked the frame timer remains in this state until an USB reset or USB suspend event occurs 1 RXDM RXDM 14 1 RXDM Received received data minus upstream port data line 1 RXDP RXDP 15 1 RXDP Received received data plus upstream port data line 1 DADDR DADDR USB device address 0x4C 0x20 read-write 0x00000000 ADD ADD 0 7 0 127 EF EF 7 1 EF Disabled USB device disabled 0 Enabled USB device enabled 1 BTABLE BTABLE Buffer table address 0x50 0x20 read-write 0x00000000 BTABLE BTABLE 3 13 0 8191 BCDR Battery Charging Detector 0x58 0x00000000 DPPU DP pull-up control 15 1 read-write DPPU Disabled signalize disconnect to the host when needed by the user software 0 Enabled enable the embedded pull-up on the DP line 1 PS2DET DM pull-up detection status 7 1 read-only PS2DET Normal Normal port detected 0 PS2 PS2 port or proprietary charger detected 1 SDET Secondary detection status 6 1 read-only SDET CDP CDP detected 0 DCP DCP detected 1 PDET Primary detection status 5 1 read-only PDET NoBCD no BCD support detected 0 BCD BCD support detected 1 DCDET Data contact detection status 4 1 read-only DCDET NotDetected data lines contact not detected 0 Detected data lines contact detected 1 SDEN Secondary detection mode enable 3 1 read-write SDEN Disabled Secondary detection (SD) mode disabled 0 Enabled Secondary detection (SD) mode enabled 1 PDEN Primary detection mode enable 2 1 read-write PDEN Disabled Primary detection (PD) mode disabled 0 Enabled Primary detection (PD) mode enabled 1 DCDEN Data contact detection mode enable 1 1 read-write DCDEN Disabled Data contact detection (DCD) mode disabled 0 Enabled Data contact detection (DCD) mode enabled 1 BCDEN Battery charging detector mode enable 0 1 read-write BCDEN Disabled disable the BCD support 0 Enabled enable the BCD support within the USB device 1 CRS CRS CRS 0x40002000 0x0 0x400 registers CR CR CRS control register 0x0 0x20 0x00004000 SYNCOKIE SYNC event OK interrupt enable 0 1 read-write SYNCOKIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 SYNCWARNIE SYNC warning interrupt enable 1 1 read-write ERRIE Synchronization or trimming error interrupt enable 2 1 read-write ESYNCIE Expected SYNC interrupt enable 3 1 read-write CEN Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. 5 1 read-write CEN Disabled Frequency error counter disabled 0 Enabled Frequency error counter enabled 1 AUTOTRIMEN Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details. 6 1 read-write AUTOTRIMEN Disabled Automatic trimming disabled 0 Enabled Automatic trimming enabled 1 SWSYNC Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. 7 1 read-write SWSYNC Sync A software sync is generated 1 TRIM HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. 8 7 read-write 0 63 CFGR CFGR This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected. 0x4 0x20 read-write 0x2022BB7F RELOAD Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior. 0 16 0 65535 FELIM Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation. 16 8 0 255 SYNCDIV SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 24 3 SYNCDIV Div1 SYNC not divided 0 Div2 SYNC divided by 2 1 Div4 SYNC divided by 4 2 Div8 SYNC divided by 8 3 Div16 SYNC divided by 16 4 Div32 SYNC divided by 32 5 Div64 SYNC divided by 64 6 Div128 SYNC divided by 128 7 SYNCSRC SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. 28 2 SYNCSRC GPIO_AF GPIO AF (crs_sync_in_1) selected as SYNC signal source 0 LSE LSE (crs_sync_in_2) selected as SYNC signal source 1 USB_SOF USB SOF (crs_sync_in_3) selected as SYNC signal source 2 SYNCPOL SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. 31 1 SYNCPOL RisingEdge SYNC active on rising edge 0 FallingEdge SYNC active on falling edge 1 ISR ISR CRS interrupt and status register 0x8 0x20 read-only 0x00000000 SYNCOKF SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. 0 1 SYNCOKF NotSignaled Signal not set 0 Signaled Signal set 1 SYNCWARNF SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. 1 1 ERRF Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. 2 1 ESYNCF Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. 3 1 SYNCERR SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 8 1 SYNCMISS SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 9 1 TRIMOVF Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 10 1 FEDIR Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. 15 1 FEDIR UpCounting Error in up-counting direction 0 DownCounting Error in down-counting direction 1 FECAP Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage. 16 16 0 65535 ICR ICR CRS interrupt flag clear register 0xC 0x20 read-write 0x00000000 SYNCOKC SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. 0 1 SYNCOKC Clear Clear flag 1 SYNCWARNC SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. 1 1 ERRC Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. 2 1 ESYNCC Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. 3 1

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