Showing content from https://stm32-rs.github.io/stm32-rs/stm32f102.svd.patched below:
STM32F102 1.1 STM32F102 CM3 r1p1 little false false 4 false 8 32 0x20 0x00000000 0xFFFFFFFF PWR Power control PWR 0x40007000 0x0 0x400 registers PVD PVD through EXTI line detection interrupt 1 CR CR Power control register (PWR_CR) 0x0 0x20 read-write 0x00000000 LPDS Low Power Deep Sleep 0 1 PDDS Power Down Deep Sleep 1 1 PDDS STOP_MODE Enter Stop mode when the CPU enters deepsleep 0 STANDBY_MODE Enter Standby mode when the CPU enters deepsleep 1 CWUF Clear Wake-up Flag 2 1 CSBF Clear STANDBY Flag 3 1 PVDE Power Voltage Detector Enable 4 1 PLS PVD Level Selection 5 3 DBP Disable Backup Domain write protection 8 1 CSR CSR Power control register (PWR_CR) 0x4 0x20 0x00000000 WUF Wake-Up Flag 0 1 read-only SBF STANDBY Flag 1 1 read-only PVDO PVD Output 2 1 read-only EWUP Enable WKUP pin 8 1 read-write RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 5 CR CR Clock control register 0x0 0x20 0x00000083 HSION Internal High Speed clock enable 0 1 read-write HSION Off Clock Off 0 On Clock On 1 HSIRDY Internal High Speed clock ready flag 1 1 read-only HSIRDYR NotReady Clock not ready 0 Ready Clock ready 1 HSITRIM Internal High Speed clock trimming 3 5 read-write 0 31 HSICAL Internal High Speed clock Calibration 8 8 read-only 0 255 HSEON External High Speed clock enable 16 1 read-write HSERDY External High Speed clock ready flag 17 1 read-only HSEBYP External High Speed clock Bypass 18 1 read-write HSEBYP NotBypassed HSE crystal oscillator not bypassed 0 Bypassed HSE crystal oscillator bypassed with external clock 1 CSSON Clock Security System enable 19 1 read-write CSSON Off Clock security system disabled (clock detector OFF) 0 On Clock security system enable (clock detector ON if the HSE is ready, OFF if not) 1 PLLON PLL enable 24 1 read-write PLLRDY PLL clock ready flag 25 1 read-only CFGR CFGR Clock configuration register (RCC_CFGR) 0x4 0x20 0x00000000 SW System clock Switch 0 2 read-write SW HSI HSI selected as system clock 0 HSE HSE selected as system clock 1 PLL PLL selected as system clock 2 SWS System Clock Switch Status 2 2 read-only SWSR HSI HSI oscillator used as system clock 0 HSE HSE oscillator used as system clock 1 PLL PLL used as system clock 2 HPRE AHB prescaler 4 4 read-write HPRE Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 Div1 SYSCLK not divided true PPRE1 APB Low speed prescaler (APB1) 8 3 read-write PPRE1 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true PPRE2 APB High speed prescaler (APB2) 11 3 read-write ADCPRE ADC prescaler 14 2 read-write ADCPRE Div2 PCLK2 divided by 2 0 Div4 PCLK2 divided by 4 1 Div6 PCLK2 divided by 8 2 Div8 PCLK2 divided by 16 3 PLLSRC PLL entry clock source 16 1 read-write PLLSRC HSI_Div2 HSI divided by 2 selected as PLL input clock 0 HSE_Div_PREDIV HSE divided by PREDIV selected as PLL input clock 1 PLLXTPRE HSE divider for PLL entry 17 1 read-write PLLXTPRE Div1 HSE clock not divided 0 Div2 HSE clock divided by 2 1 PLLMUL PLL Multiplication Factor 18 4 read-write PLLMUL Mul2 PLL input clock x2 0 Mul3 PLL input clock x3 1 Mul4 PLL input clock x4 2 Mul5 PLL input clock x5 3 Mul6 PLL input clock x6 4 Mul7 PLL input clock x7 5 Mul8 PLL input clock x8 6 Mul9 PLL input clock x9 7 Mul10 PLL input clock x10 8 Mul11 PLL input clock x11 9 Mul12 PLL input clock x12 10 Mul13 PLL input clock x13 11 Mul14 PLL input clock x14 12 Mul15 PLL input clock x15 13 Mul16 PLL input clock x16 14 Mul16x PLL input clock x16 15 MCO Microcontroller clock output 24 3 read-write MCO NoMCO MCO output disabled, no clock on MCO 0 SYSCLK System clock selected 4 HSI HSI oscillator clock selected 5 HSE HSE oscillator clock selected 6 PLL PLL clock selected (divided by 1 or 2, depending en PLLNODIV) 7 CIR CIR Clock interrupt register (RCC_CIR) 0x8 0x20 0x00000000 LSIRDYF LSI Ready Interrupt flag 0 1 read-only LSIRDYFR NotInterrupted No clock ready interrupt 0 Interrupted Clock ready interrupt 1 LSERDYF LSE Ready Interrupt flag 1 1 read-only HSIRDYF HSI Ready Interrupt flag 2 1 read-only HSERDYF HSE Ready Interrupt flag 3 1 read-only PLLRDYF PLL Ready Interrupt flag 4 1 read-only CSSF Clock Security System Interrupt flag 7 1 read-only CSSFR NotInterrupted No clock security interrupt caused by HSE clock failure 0 Interrupted Clock security interrupt caused by HSE clock failure 1 LSIRDYIE LSI Ready Interrupt Enable 8 1 read-write LSIRDYIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 LSERDYIE LSE Ready Interrupt Enable 9 1 read-write HSIRDYIE HSI Ready Interrupt Enable 10 1 read-write HSERDYIE HSE Ready Interrupt Enable 11 1 read-write PLLRDYIE PLL Ready Interrupt Enable 12 1 read-write LSIRDYC LSI Ready Interrupt Clear 16 1 write-only LSIRDYCW Clear Clear interrupt flag 1 LSERDYC LSE Ready Interrupt Clear 17 1 write-only HSIRDYC HSI Ready Interrupt Clear 18 1 write-only HSERDYC HSE Ready Interrupt Clear 19 1 write-only PLLRDYC PLL Ready Interrupt Clear 20 1 write-only CSSC Clock security system interrupt clear 23 1 write-only CSSCW Clear Clear CSSF flag 1 APB2RSTR APB2RSTR APB2 peripheral reset register (RCC_APB2RSTR) 0xC 0x20 read-write 0x00000000 AFIORST Alternate function I/O reset 0 1 AFIORST Reset Reset the selected module 1 IOPARST IO port A reset 2 1 IOPBRST IO port B reset 3 1 IOPCRST IO port C reset 4 1 IOPDRST IO port D reset 5 1 ADC1RST ADC 1 interface reset 9 1 SPI1RST SPI 1 reset 12 1 USART1RST USART1 reset 14 1 APB1RSTR APB1RSTR APB1 peripheral reset register (RCC_APB1RSTR) 0x10 0x20 read-write 0x00000000 TIM2RST Timer 2 reset 0 1 TIM2RST Reset Reset the selected module 1 TIM3RST Timer 3 reset 1 1 WWDGRST Window watchdog reset 11 1 USART2RST USART 2 reset 17 1 I2C1RST I2C1 reset 21 1 BKPRST Backup interface reset 27 1 PWRRST Power interface reset 28 1 USBRST USB reset 23 1 I2C2RST I2C2 reset 22 1 USART3RST USART3 reset 18 1 SPI2RST SPI2 reset 14 1 TIM4RST TIM4 timer reset 2 1 AHBENR AHBENR AHB Peripheral Clock enable register (RCC_AHBENR) 0x14 0x20 read-write 0x00000014 DMA1EN DMA1 clock enable 0 1 DMA1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 DMA2EN DMA2 clock enable 1 1 SRAMEN SRAM interface clock enable 2 1 FLITFEN FLITF clock enable 4 1 CRCEN CRC clock enable 6 1 APB2ENR APB2ENR APB2 peripheral clock enable register (RCC_APB2ENR) 0x18 0x20 read-write 0x00000000 AFIOEN Alternate function I/O clock enable 0 1 AFIOEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 IOPAEN I/O port A clock enable 2 1 IOPBEN I/O port B clock enable 3 1 IOPCEN I/O port C clock enable 4 1 IOPDEN I/O port D clock enable 5 1 ADC1EN ADC 1 interface clock enable 9 1 SPI1EN SPI 1 clock enable 12 1 USART1EN USART1 clock enable 14 1 APB1ENR APB1ENR APB1 peripheral clock enable register (RCC_APB1ENR) 0x1C 0x20 read-write 0x00000000 TIM2EN Timer 2 clock enable 0 1 TIM2EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM3EN Timer 3 clock enable 1 1 WWDGEN Window watchdog clock enable 11 1 USART2EN USART 2 clock enable 17 1 I2C1EN I2C 1 clock enable 21 1 BKPEN Backup interface clock enable 27 1 PWREN Power interface clock enable 28 1 USBEN USB clock enable 23 1 I2C2EN I2C2 clock enable 22 1 USART3EN USART3 clock enable 18 1 SPI2EN SPI2 clock enable 14 1 TIM4EN TIM4 Timer clock enable 2 1 BDCR BDCR Backup domain control register (RCC_BDCR) 0x20 0x20 0x00000000 LSEON External Low Speed oscillator enable 0 1 read-write LSEON Off LSE oscillator Off 0 On LSE oscillator On 1 LSERDY External Low Speed oscillator ready 1 1 read-only LSERDYR NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEBYP External Low Speed oscillator bypass 2 1 read-write LSEBYP NotBypassed LSE crystal oscillator not bypassed 0 Bypassed LSE crystal oscillator bypassed with external clock 1 RTCSEL RTC clock source selection 8 2 read-write RTCSEL NoClock No clock 0 LSE LSE oscillator clock used as RTC clock 1 LSI LSI oscillator clock used as RTC clock 2 HSE HSE oscillator clock divided by a prescaler used as RTC clock 3 RTCEN RTC clock enable 15 1 read-write RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 BDRST Backup domain software reset 16 1 read-write BDRST Disabled Reset not activated 0 Enabled Reset the entire RTC domain 1 CSR CSR Control/status register (RCC_CSR) 0x24 0x20 0x0C000000 LSION Internal low speed oscillator enable 0 1 read-write LSION Off LSI oscillator Off 0 On LSI oscillator On 1 LSIRDY Internal low speed oscillator ready 1 1 read-only LSIRDYR NotReady LSI oscillator not ready 0 Ready LSI oscillator ready 1 RMVF Remove reset flag 24 1 read-write RMVFW write Clear Clears the reset flag 1 PINRSTF PIN reset flag 26 1 read-write PINRSTFR read NoReset No reset has occured 0 Reset A reset has occured 1 PORRSTF POR/PDR reset flag 27 1 read-write SFTRSTF Software reset flag 28 1 read-write IWDGRSTF Independent watchdog reset flag 29 1 read-write WWDGRSTF Window watchdog reset flag 30 1 read-write LPWRRSTF Low-power reset flag 31 1 read-write GPIOA General purpose I/O GPIO 0x40010800 0x0 0x400 registers CRL CRL Port configuration register low (GPIOn_CRL) 0x0 0x20 read-write 0x44444444 8 0x4 0-7 MODE%s Port n.%s mode bits 0 2 Mode Input Input mode (reset state) 0 Output Output mode 10 MHz 1 Output2 Output mode 2 MHz 2 Output50 Output mode 50 MHz 3 8 0x4 0-7 CNF%s Port n.%s configuration bits 2 2 Config PushPull Analog mode / Push-Pull mode 0 OpenDrain Floating input (reset state) / Open Drain-Mode 1 AltPushPull Input with pull-up/pull-down / Alternate Function Push-Pull Mode 2 AltOpenDrain Alternate Function Open-Drain Mode 3 CRH CRH Port configuration register high (GPIOn_CRL) 0x4 0x20 read-write 0x44444444 8 0x4 8-15 MODE%s Port n.%s mode bits 0 2 8 0x4 8-15 CNF%s Port n.%s configuration bits 2 2 IDR IDR Port input data register (GPIOn_IDR) 0x8 0x20 read-only 0x00000000 16 0x1 0-15 IDR%s Port input data 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR Port output data register (GPIOn_ODR) 0xC 0x20 read-write 0x00000000 16 0x1 0-15 ODR%s Port output data 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR Port bit set/reset register (GPIOn_BSRR) 0x10 0x20 write-only 0x00000000 16 0x1 0-15 BS%s Set bit %s 0 1 BitSet Set Sets the corresponding ODRx bit 1 16 0x1 0-15 BR%s Reset bit %s 16 1 BitReset Reset Resets the corresponding ODRx bit 1 BRR BRR Port bit reset register (GPIOn_BRR) 0x14 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Reset bit %s 0 1 BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 LCKR LCKR Port configuration lock register 0x18 0x20 read-write 0x00000000 16 0x1 0-15 LCK%s Port A Lock bit %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK Lock key 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 GPIOB 0x40010C00 GPIOC 0x40011000 GPIOD 0x40011400 GPIOE 0x40011800 GPIOF 0x40011C00 GPIOG 0x40012000 AFIO Alternate function I/O AFIO 0x40010000 0x0 0x400 registers EVCR EVCR Event Control Register (AFIO_EVCR) 0x0 0x20 read-write 0x00000000 PIN Pin selection 0 4 PORT Port selection 4 3 EVOE Event Output Enable 7 1 MAPR MAPR AF remap and debug I/O configuration register (AFIO_MAPR) 0x4 0x20 0x00000000 SPI1_REMAP SPI1 remapping 0 1 read-write I2C1_REMAP I2C1 remapping 1 1 read-write USART1_REMAP USART1 remapping 2 1 read-write USART2_REMAP USART2 remapping 3 1 read-write USART3_REMAP USART3 remapping 4 2 read-write TIM1_REMAP TIM1 remapping 6 2 read-write TIM2_REMAP TIM2 remapping 8 2 read-write TIM3_REMAP TIM3 remapping 10 2 read-write TIM4_REMAP TIM4 remapping 12 1 read-write CAN_REMAP CAN1 remapping 13 2 read-write PD01_REMAP Port D0/Port D1 mapping on OSCIN/OSCOUT 15 1 read-write TIM5CH4_IREMAP Set and cleared by software 16 1 read-write ADC1_ETRGINJ_REMAP ADC 1 External trigger injected conversion remapping 17 1 read-write ADC1_ETRGREG_REMAP ADC 1 external trigger regular conversion remapping 18 1 read-write ADC2_ETRGINJ_REMAP ADC 2 external trigger injected conversion remapping 19 1 read-write ADC2_ETRGREG_REMAP ADC 2 external trigger regular conversion remapping 20 1 read-write SWJ_CFG Serial wire JTAG configuration 24 3 write-only EXTICR1 EXTICR1 External interrupt configuration register 1 (AFIO_EXTICR1) 0x8 0x20 read-write 0x00000000 EXTI0 EXTI0 configuration 0 4 EXTI0 PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 PE Select PEx as the source input for the EXTIx external interrupt 4 PF Select PFx as the source input for the EXTIx external interrupt 5 PG Select PGx as the source input for the EXTIx external interrupt 6 EXTI1 EXTI1 configuration 4 4 EXTI2 EXTI2 configuration 8 4 EXTI3 EXTI3 configuration 12 4 EXTICR2 EXTICR2 External interrupt configuration register 2 (AFIO_EXTICR2) 0xC 0x20 read-write 0x00000000 EXTI4 EXTI4 configuration 0 4 EXTI5 EXTI5 configuration 4 4 EXTI6 EXTI6 configuration 8 4 EXTI7 EXTI7 configuration 12 4 EXTICR3 EXTICR3 External interrupt configuration register 3 (AFIO_EXTICR3) 0x10 0x20 read-write 0x00000000 EXTI8 EXTI8 configuration 0 4 EXTI9 EXTI9 configuration 4 4 EXTI10 EXTI10 configuration 8 4 EXTI11 EXTI11 configuration 12 4 EXTICR4 EXTICR4 External interrupt configuration register 4 (AFIO_EXTICR4) 0x14 0x20 read-write 0x00000000 EXTI12 EXTI12 configuration 0 4 EXTI13 EXTI13 configuration 4 4 EXTI14 EXTI14 configuration 8 4 EXTI15 EXTI15 configuration 12 4 MAPR2 MAPR2 AF remap and debug I/O configuration register 0x1C 0x20 read-write 0x00000000 TIM9_REMAP TIM9 remapping 5 1 TIM10_REMAP TIM10 remapping 6 1 TIM11_REMAP TIM11 remapping 7 1 TIM13_REMAP TIM13 remapping 8 1 TIM14_REMAP TIM14 remapping 9 1 FSMC_NADV NADV connect/disconnect 10 1 EXTI EXTI EXTI 0x40010400 0x0 0x400 registers TAMPER Tamper interrupt 2 EXTI0 EXTI Line0 interrupt 6 EXTI1 EXTI Line1 interrupt 7 EXTI2 EXTI Line2 interrupt 8 EXTI3 EXTI Line3 interrupt 9 EXTI4 EXTI Line4 interrupt 10 EXTI9_5 EXTI Line[9:5] interrupts 23 EXTI15_10 EXTI Line[15:10] interrupts 40 USBWakeup USB wakeup from suspend through EXTI line interrupt 42 IMR IMR Interrupt mask register (EXTI_IMR) 0x0 0x20 read-write 0x00000000 19 0x1 0-18 MR%s Interrupt Mask on line %s 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 EMR EMR Event mask register (EXTI_EMR) 0x4 0x20 read-write 0x00000000 19 0x1 0-18 MR%s Event Mask on line %s 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 RTSR RTSR Rising Trigger selection register (EXTI_RTSR) 0x8 0x20 read-write 0x00000000 19 0x1 0-18 TR%s Rising trigger event configuration of line %s 0 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 FTSR FTSR Falling Trigger selection register (EXTI_FTSR) 0xC 0x20 read-write 0x00000000 19 0x1 0-18 TR%s Falling trigger event configuration of line %s 0 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 SWIER SWIER Software interrupt event register (EXTI_SWIER) 0x10 0x20 read-write 0x00000000 19 0x1 0-18 SWIER%s Software Interrupt on line %s 0 1 SoftwareInterrupt write Pend Generates an interrupt request 1 PR PR Pending register (EXTI_PR) 0x14 0x20 read-write 0x00000000 19 0x1 0-18 PR%s Pending bit %s 0 1 oneToClear PR0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PR0W write Clear Clears pending bit 1 DMA1 DMA controller DMA 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel1 global interrupt 11 DMA1_Channel2 DMA1 Channel2 global interrupt 12 DMA1_Channel3 DMA1 Channel3 global interrupt 13 DMA1_Channel4 DMA1 Channel4 global interrupt 14 DMA1_Channel5 DMA1 Channel5 global interrupt 15 DMA1_Channel6 DMA1 Channel6 global interrupt 16 DMA1_Channel7 DMA1 Channel7 global interrupt 17 ISR ISR DMA interrupt status register (DMA_ISR) 0x0 0x20 read-only 0x00000000 7 0x4 1-7 GIF%s Channel %s Global interrupt flag 0 1 GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 7 0x4 1-7 TCIF%s Channel %s Transfer Complete flag 1 1 TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 7 0x4 1-7 HTIF%s Channel %s Half Transfer Complete flag 2 1 HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 7 0x4 1-7 TEIF%s Channel %s Transfer Error flag 3 1 TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 IFCR IFCR DMA interrupt flag clear register (DMA_IFCR) 0x4 0x20 write-only 0x00000000 7 0x4 1-7 CGIF%s Channel %s Global interrupt clear 0 1 CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 7 0x4 1-7 CTCIF%s Channel %s Transfer Complete clear 1 1 CTCIF1 Clear Clears the TCIF flag in the ISR register 1 7 0x4 1-7 CHTIF%s Channel %s Half Transfer clear 2 1 CHTIF1 Clear Clears the HTIF flag in the ISR register 1 7 0x4 1-7 CTEIF%s Channel %s Transfer Error clear 3 1 CTEIF1 Clear Clears the TEIF flag in the ISR register 1 7 0x14 1-7 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8 CR CCR1 DMA channel configuration register (DMA_CCR) 0x0 0x20 read-write 0x00000000 EN Channel enable 0 1 EN Disabled Channel disabled 0 Enabled Channel enabled 1 TCIE Transfer complete interrupt enable 1 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 HTIE Half Transfer interrupt enable 2 1 HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TEIE Transfer error interrupt enable 3 1 TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 DIR Data transfer direction 4 1 DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 CIRC Circular mode 5 1 CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 PINC Peripheral increment mode 6 1 PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 MEM2MEM Memory to memory mode 14 1 MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 NDTR CNDTR1 DMA channel 1 number of data register 0x4 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 0 65535 PAR CPAR1 DMA channel 1 peripheral address register 0x8 0x20 read-write 0x00000000 PA Peripheral address 0 32 MAR CMAR1 DMA channel 1 memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 DMA2 0x40020400 DMA2_Channel1 DMA2 Channel1 global interrupt 56 DMA2_Channel2 DMA2 Channel2 global interrupt 57 DMA2_Channel3 DMA2 Channel3 global interrupt 58 DMA2_Channel4_5 DMA2 Channel4 and DMA2 Channel5 global interrupt 59 RTC Real time clock RTC 0x40002800 0x0 0x400 registers RTC RTC global interrupt 3 RTCAlarm RTC Alarms through EXTI line interrupt 41 CRH CRH RTC Control Register High 0x0 0x20 read-write 0x00000000 SECIE Second interrupt Enable 0 1 SECIE Disabled Second interrupt is masked 0 Enabled Second interrupt is enabled 1 ALRIE Alarm interrupt Enable 1 1 ALRIE Disabled Alarm interrupt is masked 0 Enabled Alarm interrupt is enabled 1 OWIE Overflow interrupt Enable 2 1 OWIE Disabled Overflow interrupt is masked 0 Enabled Overflow interrupt is enabled 1 CRL CRL RTC Control Register Low 0x4 0x20 0x00000020 SECF Second Flag 0 1 read-write zeroToClear SECFR read NoPrescalerOverflow Second flag condition not met 0 PrescalerOverflow Second flag condition met 1 Clear write Clear Clear flag 0 ALRF Alarm Flag 1 1 read-write zeroToClear ALRFR read NoAlarm Alarm not detected 0 Alarm Alarm detected 1 OWF Overflow Flag 2 1 read-write zeroToClear OWFR read NoOverflow Overflow not detected 0 Overflow 32-bit programmable counter overflow occurred 1 RSF Registers Synchronized Flag 3 1 read-write zeroToClear RSFR read NotSynchronized Registers not yet synchronized 0 Synchronized Registers synchronized 1 CNF Configuration Flag 4 1 read-write CNF Exit Exit configuration mode (start update of RTC registers) 0 Enter Enter configuration mode 1 RTOFF RTC operation OFF 5 1 read-only RTOFF Enabled Last write operation on RTC registers is still ongoing 0 Disabled Last write operation on RTC registers terminated 1 PRLH PRLH RTC Prescaler Load Register High 0x8 0x20 write-only 0x00000000 PRLH RTC Prescaler Load Register High 0 4 0 15 PRLL PRLL RTC Prescaler Load Register Low 0xC 0x20 write-only 0x00008000 PRLL RTC Prescaler Divider Register Low 0 16 0 65535 DIVH DIVH RTC Prescaler Divider Register High 0x10 0x20 read-only 0x00000000 DIVH RTC prescaler divider register high 0 4 0 15 DIVL DIVL RTC Prescaler Divider Register Low 0x14 0x20 read-only 0x00008000 DIVL RTC prescaler divider register Low 0 16 0 65535 CNTH CNTH RTC Counter Register High 0x18 0x20 read-write 0x00000000 CNTH RTC counter register high 0 16 0 65535 CNTL CNTL RTC Counter Register Low 0x1C 0x20 read-write 0x00000000 CNTL RTC counter register Low 0 16 0 65535 ALRH ALRH RTC Alarm Register High 0x20 0x20 write-only 0x0000FFFF ALRH RTC alarm register high 0 16 0 65535 ALRL ALRL RTC Alarm Register Low 0x24 0x20 write-only 0x0000FFFF ALRL RTC alarm register low 0 16 0 65535 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register (IWDG_KR) 0x0 0x10 write-only 0x00000000 KEY Key value 0 16 KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR Prescaler register (IWDG_PR) 0x4 0x10 read-write 0x00000000 PR Prescaler divider 0 3 PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 true RLR RLR Reload register (IWDG_RLR) 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value 0 12 0 4095 SR SR Status register (IWDG_SR) 0xC 0x10 read-only 0x00000000 PVU Watchdog prescaler value update 0 1 RVU Watchdog counter reload value update 1 1 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR Control register (WWDG_CR) 0x0 0x10 read-write 0x0000007F T 7-bit counter (MSB to LSB) 0 7 0 127 WDGA Activation bit 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 CFR CFR Configuration register (WWDG_CFR) 0x4 0x10 read-write 0x0000007F W 7-bit window value 0 7 0 127 WDGTB Timer Base 7 2 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 EWI Early Wakeup Interrupt 9 1 EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 SR SR Status register (WWDG_SR) 0x8 0x10 read-write 0x00000000 EWIF Early Wakeup Interrupt 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 TIM2 General purpose timer TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 à t_CK_INT 1 Div4 t_DTS = 4 à t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = â1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 DCR DCR DMA control register 0x48 0x20 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 TIM3 TIM 0x40000400 TIM3 TIM3 global interrupt 29 I2C1 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C event interrupt 31 I2C1_ER I2C errot interrupt 32 CR1 CR1 Control register 1 0x0 0x10 read-write 0x00000000 SWRST Software reset 15 1 SWRST NotReset I2C peripheral not under reset 0 Reset I2C peripheral under reset 1 ALERT SMBus alert 13 1 ALERT Release SMBA pin released high 0 Drive SMBA pin driven low 1 PEC Packet error checking 12 1 PEC Disabled No PEC transfer 0 Enabled PEC transfer 1 POS Acknowledge/PEC Position (for data reception) 11 1 POS Current ACK bit controls the (N)ACK of the current byte being received 0 Next ACK bit controls the (N)ACK of the next byte to be received 1 ACK Acknowledge enable 10 1 ACK NAK No acknowledge returned 0 ACK Acknowledge returned after a byte is received 1 STOP Stop generation 9 1 STOP NoStop No Stop generation 0 Stop In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte 1 START Start generation 8 1 START NoStart No Start generation 0 Start In master mode: repeated start generation, in slave mode: start generation when bus is free 1 NOSTRETCH Clock stretching disable (Slave mode) 7 1 NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 ENGC General call enable 6 1 ENGC Disabled General call disabled 0 Enabled General call enabled 1 ENPEC PEC enable 5 1 ENPEC Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 ENARP ARP enable 4 1 ENARP Disabled ARP disabled 0 Enabled ARP enabled 1 SMBTYPE SMBus type 3 1 SMBTYPE Device SMBus Device 0 Host SMBus Host 1 SMBUS SMBus mode 1 1 SMBUS I2C I2C Mode 0 SMBus SMBus 1 PE Peripheral enable 0 1 PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 CR2 CR2 Control register 2 0x4 0x10 read-write 0x00000000 LAST DMA last transfer 12 1 LAST NotLast Next DMA EOT is not the last transfer 0 Last Next DMA EOT is the last transfer 1 DMAEN DMA requests enable 11 1 DMAEN Disabled DMA requests disabled 0 Enabled DMA request enabled when TxE=1 or RxNE=1 1 ITBUFEN Buffer interrupt enable 10 1 ITBUFEN Disabled TxE=1 or RxNE=1 does not generate any interrupt 0 Enabled TxE=1 or RxNE=1 generates Event interrupt 1 ITEVTEN Event interrupt enable 9 1 ITEVTEN Disabled Event interrupt disabled 0 Enabled Event interrupt enabled 1 ITERREN Error interrupt enable 8 1 ITERREN Disabled Error interrupt disabled 0 Enabled Error interrupt enabled 1 FREQ Peripheral clock frequency 0 6 2 50 OAR1 OAR1 Own address register 1 0x8 0x10 read-write 0x00000000 ADDMODE Addressing mode (slave mode) 15 1 ADDMODE ADD7 7-bit slave address 0 ADD10 10-bit slave address 1 ADD Interface address 0 10 0 1023 OAR2 OAR2 Own address register 2 0xC 0x10 read-write 0x00000000 ADD2 Interface address 1 7 0 127 ENDUAL Dual addressing mode enable 0 1 ENDUAL Single Single addressing mode 0 Dual Dual addressing mode 1 DR DR Data register 0x10 0x10 read-write 0x00000000 DR 8-bit data register 0 8 0 255 SR1 SR1 Status register 1 0x14 0x10 0x00000000 SMBALERT SMBus alert 15 1 read-write zeroToClear SMBALERTR read NoAlert No SMBALERT occured 0 Alert SMBALERT occurred 1 SMBALERTW write Clear Clear flag 0 TIMEOUT Timeout or Tlow error 14 1 read-write zeroToClear TIMEOUTR read NoTimeout No Timeout error 0 Timeout SCL remained LOW for 25 ms 1 TIMEOUTW write Clear Clear flag 0 PECERR PEC Error in reception 12 1 read-write zeroToClear PECERRR read NoError no PEC error: receiver returns ACK after PEC reception (if ACK=1) 0 Error PEC error: receiver returns NACK after PEC reception (whatever ACK) 1 PECERRW write Clear Clear flag 0 OVR Overrun/Underrun 11 1 read-write zeroToClear OVRR read NoOverrun No overrun/underrun occured 0 Overrun Overrun/underrun occured 1 OVRW write Clear Clear flag 0 AF Acknowledge failure 10 1 read-write zeroToClear AFR read NoFailure No acknowledge failure 0 Failure Acknowledge failure 1 AFW write Clear Clear flag 0 ARLO Arbitration lost (master mode) 9 1 read-write zeroToClear ARLOR read NoLost No Arbitration Lost detected 0 Lost Arbitration Lost detected 1 ARLOW write Clear Clear flag 0 BERR Bus error 8 1 read-write zeroToClear BERRR read NoError No misplaced Start or Stop condition 0 Error Misplaced Start or Stop condition 1 BERRW write Clear Clear flag 0 TxE Data register empty (transmitters) 7 1 read-only TxE NotEmpty Data register not empty 0 Empty Data register empty 1 RxNE Data register not empty (receivers) 6 1 read-only RxNE Empty Data register empty 0 NotEmpty Data register not empty 1 STOPF Stop detection (slave mode) 4 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 ADD10 10-bit header sent (Master mode) 3 1 read-only BTF Byte transfer finished 2 1 read-only BTF NotFinished Data byte transfer not done 0 Finished Data byte transfer successful 1 ADDR Address sent (master mode)/matched (slave mode) 1 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 SB Start bit (Master mode) 0 1 read-only SB NoStart No Start condition 0 Start Start condition generated 1 SR2 SR2 Status register 2 0x18 0x10 read-only 0x00000000 PEC acket error checking register 8 8 DUALF Dual flag (Slave mode) 7 1 SMBHOST SMBus host header (Slave mode) 6 1 SMBDEFAULT SMBus device default address (Slave mode) 5 1 GENCALL General call address (Slave mode) 4 1 TRA Transmitter/receiver 2 1 BUSY Bus busy 1 1 MSL Master/slave 0 1 CCR CCR Clock control register 0x1C 0x10 read-write 0x00000000 F_S I2C master mode selection 15 1 F_S Standard Standard mode I2C 0 Fast Fast mode I2C 1 DUTY Fast mode duty cycle 14 1 DUTY Duty2_1 Duty cycle t_low/t_high = 2/1 0 Duty16_9 Duty cycle t_low/t_high = 16/9 1 CCR Clock control register in Fast/Standard mode (Master mode) 0 12 1 4095 TRISE TRISE TRISE register 0x20 0x10 read-write 0x00000002 TRISE Maximum rise time in Fast/Standard mode (Master mode) 0 6 0 63 I2C2 0x40005800 I2C2_EV I2C event interrupt 33 I2C2_ER I2C errot interrupt 34 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 DFF Data frame format 11 1 DFF EightBit 8-bit data frame format is selected for transmission/reception 0 SixteenBit 16-bit data frame format is selected for transmission/reception 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 SR SR status register 0x8 0x10 0x00000002 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 UDR Underrun flag 3 1 read-only CHSIDE Channel side 2 1 read-only TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 I2SCFGR I2SCFGR I2S configuration register 0x1C 0x10 read-write 0x00000000 I2SMOD I2S mode selection 11 1 I2SE I2S Enable 10 1 I2SCFG I2S configuration mode 8 2 PCMSYNC PCM frame synchronization 7 1 I2SSTD I2S standard selection 4 2 CKPOL Steady state clock polarity 3 1 DATLEN Data length to be transferred 1 2 CHLEN Channel length (number of bits per audio channel) 0 1 I2SPR I2SPR I2S prescaler register 0x20 0x10 read-write 0x0000000A MCKOE Master clock output enable 9 1 ODD Odd factor for the prescaler 8 1 I2SDIV I2S Linear prescaler 0 8 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 37 SR SR Status register 0x0 0x10 0x000000C0 CTS CTS flag 9 1 read-write zeroToClear CTSR read NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTSW write Clear Clear CTS toggle detection flag 0 LBD LIN break detection flag 8 1 read-write zeroToClear LBDR read NotDetected LIN break not detected 0 Detected LIN break detected 1 LBDW write Clear Clear LIN break detection flag 0 TXE Transmit data register empty 7 1 read-only TXE TxNotEmpty Data is not transferred to the shift register 0 TxEmpty Data is transferred to the shift register 1 TC Transmission complete 6 1 read-write zeroToClear TCR read TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TCW write Clear Clear transmission complete flag 0 RXNE Read data register not empty 5 1 read-write zeroToClear RXNER read NoData Data is not received 0 DataReady Received data is ready to be read 1 RXNEW write Clear Clear received data ready flag 0 IDLE IDLE line detected 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE Overrun error 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NE Noise error flag 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 FE Framing error 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE Parity error 0 1 read-only PE NoError No parity error 0 Error Parity error 1 DR DR Data register 0x4 0x10 read-write 0x00000000 DR Data value 0 9 0 511 BRR BRR Baud rate register 0x8 0x10 read-write 0x00000000 DIV_Mantissa mantissa of USARTDIV 4 12 0 4095 DIV_Fraction fraction of USARTDIV 0 4 0 15 CR1 CR1 Control register 1 0xC 0x10 read-write 0x00000000 UE USART enable 13 1 UE Disabled USART prescaler and outputs disabled 0 Enabled USART enabled 1 M Word length 12 1 M M8 8 data bits 0 M9 9 data bits 1 WAKE Wakeup method 11 1 WAKE IdleLine USART wakeup on idle line 0 AddressMark USART wakeup on address mark 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled PE interrupt disabled 0 Enabled PE interrupt enabled 1 TXEIE TXE interrupt enable 7 1 TXEIE Disabled TXE interrupt disabled 0 Enabled TXE interrupt enabled 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled TC interrupt disabled 0 Enabled TC interrupt enabled 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled RXNE interrupt disabled 0 Enabled RXNE interrupt enabled 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled IDLE interrupt disabled 0 Enabled IDLE interrupt enabled 1 TE Transmitter enable 3 1 TE Disabled Transmitter disabled 0 Enabled Transmitter enabled 1 RE Receiver enable 2 1 RE Disabled Receiver disabled 0 Enabled Receiver enabled 1 RWU Receiver wakeup 1 1 RWU Active Receiver in active mode 0 Mute Receiver in mute mode 1 SBK Send break 0 1 SBK NoBreak No break character is transmitted 0 Break Break character transmitted 1 CR2 CR2 Control register 2 0x10 0x10 read-write 0x00000000 LINEN LIN mode enable 14 1 LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bits 1 Stop2 2 stop bits 2 Stop1p5 1.5 stop bits 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 CPOL Clock polarity 10 1 CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CPHA Clock phase 9 1 CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 LBCL Last bit clock pulse 8 1 LBCL Disabled The clock pulse of the last data bit is not output to the CK pin 0 Enabled The clock pulse of the last data bit is output to the CK pin 1 LBDIE LIN break detection interrupt enable 6 1 LBDIE Disabled LIN break detection interrupt disabled 0 Enabled LIN break detection interrupt enabled 1 LBDL lin break detection length 5 1 LBDL LBDL10 10-bit break detection 0 LBDL11 11-bit break detection 1 ADD Address of the USART node 0 4 0 15 CR3 CR3 Control register 3 0x14 0x10 read-write 0x00000000 CTSIE CTS interrupt enable 10 1 CTSIE Disabled CTS interrupt disabled 0 Enabled CTS interrupt enabled 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS hardware flow control enabled 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS hardware flow control enabled 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 SCEN Smartcard mode enable 5 1 SCEN Disabled Smartcard mode disabled 0 Enabled Smartcard mode enabled 1 NACK Smartcard NACK enable 4 1 NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 HDSEL Half-duplex selection 3 1 HDSEL FullDuplex Half duplex mode is not selected 0 HalfDuplex Half duplex mode is selected 1 IRLP IrDA low-power 2 1 IRLP Normal Normal mode 0 LowPower Low-power mode 1 IREN IrDA mode enable 1 1 IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 EIE Error interrupt enable 0 1 EIE Disabled Error interrupt disabled 0 Enabled Error interrupt enabled 1 GTPR GTPR Guard time and prescaler register 0x18 0x10 read-write 0x00000000 GT Guard time value 8 8 0 255 PSC Prescaler value 0 8 1 255 USART2 0x40004400 USART2 USART2 global interrupt 38 USART3 0x40004800 USART3 USART3 global interrupt 39 ADC1 Analog to digital converter ADC 0x40012400 0x0 0x400 registers SR SR status register 0x0 0x20 read-write 0x00000000 STRT Regular channel start flag 4 1 zeroToClear STRTR read NotStarted No regular channel conversion started 0 Started Regular channel conversion has started 1 STRTW write Clear Clear the Regular channel Start flag 0 JSTRT Injected channel start flag 3 1 zeroToClear JSTRTR read NotStarted No injected group conversion started 0 Started Injected group conversion has started 1 JSTRTW write Clear Clear Injected channel Start flag 0 JEOC Injected channel end of conversion 2 1 zeroToClear JEOCR read NotComplete Conversion is not complete 0 Complete Conversion complete 1 JEOCW write Clear Clear Injected channel end of conversion flag 0 EOC Regular channel end of conversion 1 1 zeroToClear EOCR read NotComplete Conversion is not complete 0 Complete Conversion complete 1 EOCW write Clear Clear End of conversion flag 0 AWD Analog watchdog flag 0 1 zeroToClear AWDR read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWDW write Clear Clear the analog watchdog event flag 0 CR1 CR1 control register 1 0x4 0x20 read-write 0x00000000 AWDEN Analog watchdog enable on regular channels 23 1 AWDEN Disabled Analog watchdog disabled on regular channels 0 Enabled Analog watchdog enabled on regular channels 1 JAWDEN Analog watchdog enable on injected channels 22 1 JAWDEN Disabled Analog watchdog disabled on injected channels 0 Enabled Analog watchdog enabled on injected channels 1 DUALMOD Dual mode selection 16 4 DUALMOD Independent Independent mode 0 RegularInjected Combined regular simultaneous + injected simultaneous mode 1 RegularAlternateTrigger Combined regular simultaneous + alternate trigger mode 2 InjectedFastInterleaved Combined injected simultaneous + fast interleaved mode 3 InjectedSlowInterleaved Combined injected simultaneous + slow interleaved mode 4 Injected Injected simultaneous mode only 5 Regular Regular simultaneous mode only 6 FastInterleaved Fast interleaved mode only 7 SlowInterleaved Slow interleaved mode only 8 AlternateTrigger Alternate trigger mode only 9 DISCNUM Discontinuous mode channel count 13 3 0 7 JDISCEN Discontinuous mode on injected channels 12 1 JDISCEN Disabled Discontinuous mode on injected channels disabled 0 Enabled Discontinuous mode on injected channels enabled 1 DISCEN Discontinuous mode on regular channels 11 1 DISCEN Disabled Discontinuous mode on regular channels disabled 0 Enabled Discontinuous mode on regular channels enabled 1 JAUTO Automatic injected group conversion 10 1 JAUTO Disabled Automatic injected group conversion disabled 0 Enabled Automatic injected group conversion enabled 1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 AWDSGL All Analog watchdog enabled on all channels 0 Single Analog watchdog enabled on a single channel 1 SCAN Scan mode 8 1 SCAN Disabled Scan mode disabled 0 Enabled Scan mode enabled 1 JEOCIE Interrupt enable for injected channels 7 1 JEOCIE Disabled JEOC interrupt disabled 0 Enabled JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set 1 AWDIE Analog watchdog interrupt enable 6 1 AWDIE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 EOCIE Interrupt enable for EOC 5 1 EOCIE Disabled EOC interrupt disabled 0 Enabled EOC interrupt enabled. An interrupt is generated when the EOC bit is set 1 AWDCH Analog watchdog channel select bits 0 5 0 17 CR2 CR2 control register 2 0x8 0x20 read-write 0x00000000 TSVREFE Temperature sensor and VREFINT enable 23 1 TSVREFE Disabled Temperature sensor and V_REFINT channel disabled 0 Enabled Temperature sensor and V_REFINT channel enabled 1 SWSTART Start conversion of regular channels 22 1 SWSTARTR read Started Reset state 0 NotStarted Starting conversion of regular channels 1 SWSTARTW write Start Start conversion of regular channels 1 JSWSTART Start conversion of injected channels 21 1 JSWSTARTR read Started Reset state 0 NotStarted Starting conversion of injected channels 1 JSWSTARTW write Start Start conversion of injected channels 1 EXTTRIG External trigger conversion mode for regular channels 20 1 EXTTRIG Disabled Conversion on external event disabled 0 Enabled Conversion on external event enabled 1 EXTSEL External event select for regular group 17 3 EXTSEL Tim1Cc1 Timer 1 CC1 event 0 Tim1Cc2 Timer 1 CC2 event 1 Tim1Cc3 Timer 1 CC3 event 2 Tim2Cc2 Timer 2 CC2 event 3 Tim3Trgo Timer 3 TRGO event 4 Tim4Cc4 Timer 4 CC4 event 5 Exti11 EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices) 6 Swstart SWSTART 7 JEXTTRIG External trigger conversion mode for injected channels 15 1 JEXTTRIG Disabled Conversion on external event disabled 0 Enabled Conversion on external event enabled 1 JEXTSEL External event select for injected group 12 3 JEXTSEL Tim1Trgo Timer 1 TRGO event 0 Tim1Cc4 Timer 1 CC4 event 1 Tim2Trgo Timer 2 TRGO event 2 Tim2Cc1 Timer 2 CC1 event 3 Tim3Cc4 Timer 3 CC4 event 4 Tim4Trgo Timer 4 TRGO event 5 Exti15 EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices) 6 Jswstart JSWSTART 7 ALIGN Data alignment 11 1 ALIGN Right Right Alignment 0 Left Left Alignment 1 DMA Direct memory access mode 8 1 DMA Disabled DMA mode disabled 0 Enabled DMA mode enabled 1 RSTCAL Reset calibration 3 1 RSTCALR read Initialized Calibration register initialized 0 NotInitialized Initializing calibration register 1 RSTCALW write Initialize Initialize calibration register 1 CAL A/D calibration 2 1 CALR read Complete Calibration completed 0 NotComplete Calibrating 1 CALW write Start Enable calibration 1 CONT Continuous conversion 1 1 CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 ADON A/D converter ON / OFF 0 1 ADON Disabled Disable ADC conversion/calibration and go to power down mode 0 Enabled Enable ADC and to start conversion 1 SMPR1 SMPR1 sample time register 1 0xC 0x20 read-write 0x00000000 8 0x3 10-17 SMP%s Channel %s sample time selection 0 3 SMP10 Cycles1_5 1.5 ADC clock cycles 0 Cycles7_5 7.5 ADC clock cycles 1 Cycles13_5 13.5 ADC clock cycles 2 Cycles28_5 28.5 ADC clock cycles 3 Cycles41_5 41.5 ADC clock cycles 4 Cycles55_5 55.5 ADC clock cycles 5 Cycles71_5 71.5 ADC clock cycles 6 Cycles239_5 239.5 ADC clock cycles 7 SMPR2 SMPR2 sample time register 2 0x10 0x20 read-write 0x00000000 10 0x3 0-9 SMP%s Channel %s sample time selection 0 3 4 0x4 1-4 JOFR%s JOFR%s injected channel data offset register %s 0x14 0x20 read-write 0x00000000 JOFFSET Data offset for injected channel 0 12 0 4095 HTR HTR watchdog higher threshold register 0x24 0x20 read-write 0x00000FFF HT Analog watchdog higher threshold 0 12 0 4095 LTR LTR watchdog lower threshold register 0x28 0x20 read-write 0x00000000 LT Analog watchdog lower threshold 0 12 0 4095 SQR1 SQR1 regular sequence register 1 0x2C 0x20 read-write 0x00000000 L Regular channel sequence length 20 4 0 15 4 0x5 13-16 SQ%s %s conversion in regular sequence 0 5 0 17 SQR2 SQR2 regular sequence register 2 0x30 0x20 read-write 0x00000000 6 0x5 7-12 SQ%s %s conversion in regular sequence 0 5 SQR3 SQR3 regular sequence register 3 0x34 0x20 read-write 0x00000000 6 0x5 1-6 SQ%s %s conversion in regular sequence 0 5 JSQR JSQR injected sequence register 0x38 0x20 read-write 0x00000000 JL Injected sequence length 20 2 0 3 4 0x5 1-4 JSQ%s %s conversion in injected sequence 0 5 0 17 4 0x4 1-4 JDR%s JDR%s injected data register x 0x3C 0x20 read-only 0x00000000 JDATA Injected data 0 16 DR DR regular data register 0x4C 0x20 read-only 0x00000000 DATA Regular data 0 16 ADC2DATA ADC2 data 16 16 ADC3 Analog to digital converter ADC 0x40013C00 0x0 0x400 registers ADC1_2 ADC1 and ADC2 global interrupt 18 ADC3 ADC3 global interrupt 47 SR SR status register 0x0 CR1 CR1 control register 1 0x4 0x20 read-write 0x00000000 AWDEN Analog watchdog enable on regular channels 23 1 JAWDEN Analog watchdog enable on injected channels 22 1 DISCNUM Discontinuous mode channel count 13 3 JDISCEN Discontinuous mode on injected channels 12 1 DISCEN Discontinuous mode on regular channels 11 1 JAUTO Automatic injected group conversion 10 1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 SCAN Scan mode 8 1 JEOCIE Interrupt enable for injected channels 7 1 AWDIE Analog watchdog interrupt enable 6 1 EOCIE Interrupt enable for EOC 5 1 AWDCH Analog watchdog channel select bits 0 5 CR2 CR2 control register 2 0x8 0x20 read-write 0x00000000 TSVREFE Temperature sensor and VREFINT enable 23 1 SWSTART Start conversion of regular channels 22 1 JSWSTART Start conversion of injected channels 21 1 EXTTRIG External trigger conversion mode for regular channels 20 1 EXTSEL External event select for regular group 17 3 EXTSEL Tim3Cc1 Timer 3 CC1 event 0 Tim2Cc3 Timer 2 CC3 event 1 Tim1Cc3 Timer 1 CC3 event 2 Tim8Cc1 Timer 8 CC1 event 3 Tim8Trgo Timer 8 TRGO event 4 Tim5Cc1 Timer 5 CC1 event 5 Tim5Cc3 Timer 5 CC3 event 6 Swstart SWSTART 7 JEXTTRIG External trigger conversion mode for injected channels 15 1 JEXTSEL External event select for injected group 12 3 JEXTSEL Tim1Trgo Timer 1 TRGO event 0 Tim1Cc4 Timer 1 CC4 event 1 Tim4Cc3 Timer 4 CC3 event 2 Tim8Cc2 Timer 8 CC2 event 3 Tim8Cc4 Timer 8 CC4 event 4 Tim5Trgo Timer 5 TRGO event 5 Tim5Cc4 Timer 5 CC4 event 6 Jswstart JSWSTART 7 ALIGN Data alignment 11 1 DMA Direct memory access mode 8 1 RSTCAL Reset calibration 3 1 CAL A/D calibration 2 1 CONT Continuous conversion 1 1 ADON A/D converter ON / OFF 0 1 SMPR1 SMPR1 sample time register 1 0xC SMPR2 SMPR2 sample time register 2 0x10 4 0x4 1-4 JOFR%s JOFR%s injected channel data offset register %s 0x14 HTR HTR watchdog higher threshold register 0x24 LTR LTR watchdog lower threshold register 0x28 SQR1 SQR1 regular sequence register 1 0x2C SQR2 SQR2 regular sequence register 2 0x30 SQR3 SQR3 regular sequence register 3 0x34 JSQR JSQR injected sequence register 0x38 4 0x4 1-4 JDR%s JDR%s injected data register x 0x3C DR DR regular data register 0x4C 0x20 read-only 0x00000000 DATA Regular data 0 16 CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data Register 0 32 0 4294967295 IDR IDR Independent Data register 0x4 0x20 read-write 0x00000000 IDR Independent Data register 0 8 0 255 CR CR Control register 0x8 0x20 write-only 0x00000000 RESET Reset bit 0 1 RESETW Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 FLASH FLASH FLASH 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 4 ACR ACR Flash access control register 0x0 0x20 0x00000030 LATENCY Latency 0 3 read-write LATENCY WS0 Zero wait state, if 0 < SYSCLK⤠24 MHz 0 WS1 One wait state, if 24 MHz < SYSCLK ⤠48 MHz 1 WS2 Two wait states, if 48 MHz < SYSCLK ⤠72 MHz 2 HLFCYA Flash half cycle access enable 3 1 read-write PRFTBE Prefetch buffer enable 4 1 read-write PRFTBS Prefetch buffer status 5 1 read-only KEYR KEYR Flash key register 0x4 0x20 write-only 0x00000000 KEY FPEC key 0 32 OPTKEYR OPTKEYR Flash option key register 0x8 0x20 write-only 0x00000000 OPTKEY Option byte key 0 32 SR SR Status register 0xC 0x20 0x00000000 EOP End of operation 5 1 read-write WRPRTERR Write protection error 4 1 read-write PGERR Programming error 2 1 read-write BSY Busy 0 1 read-only CR CR Control register 0x10 0x20 read-write 0x00000080 PG Programming 0 1 PER Page Erase 1 1 MER Mass Erase 2 1 OPTPG Option byte programming 4 1 OPTER Option byte erase 5 1 STRT Start 6 1 LOCK Lock 7 1 OPTWRE Option bytes write enable 9 1 ERRIE Error interrupt enable 10 1 EOPIE End of operation interrupt enable 12 1 AR AR Flash address register 0x14 0x20 write-only 0x00000000 FAR Flash Address 0 32 OBR OBR Option byte register 0x1C 0x20 read-only 0x03FFFFFC OPTERR Option byte error 0 1 RDPRT Read protection 1 1 WDG_SW WDG_SW 2 1 nRST_STOP nRST_STOP 3 1 nRST_STDBY nRST_STDBY 4 1 Data0 Data0 10 8 Data1 Data1 18 8 WRPR WRPR Write protection register 0x20 0x20 read-only 0xFFFFFFFF WRP Write protect 0 32 DBGMCU Debug support DBG 0xE0042000 0x0 0x400 registers IDCODE IDCODE DBGMCU_IDCODE 0x0 0x20 read-only 0x00000000 DEV_ID DEV_ID 0 12 REV_ID REV_ID 16 16 CR CR DBGMCU_CR 0x4 0x20 read-write 0x00000000 DBG_SLEEP DBG_SLEEP 0 1 DBG_STOP DBG_STOP 1 1 DBG_STANDBY DBG_STANDBY 2 1 TRACE_IOEN TRACE_IOEN 5 1 TRACE_MODE TRACE_MODE 6 2 DBG_IWDG_STOP DBG_IWDG_STOP 8 1 DBG_WWDG_STOP DBG_WWDG_STOP 9 1 DBG_TIM2_STOP DBG_TIM2_STOP 11 1 DBG_TIM3_STOP DBG_TIM3_STOP 12 1 DBG_I2C1_SMBUS_TIMEOUT DBG_I2C1_SMBUS_TIMEOUT 15 1 BKP Backup registers BKP 0x40006C04 0x0 0x400 registers 10 0x4 1-10 DR%s DR%s Backup data register (BKP_DR) 0x0 0x20 read-write 0x00000000 D Backup data 0 16 0 65535 32 0x4 11-42 BKP_DR%s BKP_DR%s Backup data register (BKP_DR) 0x3C 0x20 read-write 0x00000000 D Backup data 0 16 0 65535 RTCCR RTCCR RTC clock calibration register (BKP_RTCCR) 0x28 0x20 read-write 0x00000000 CAL Calibration value 0 7 0 121 CCO Calibration Clock Output 7 1 ASOE Alarm or second output enable 8 1 ASOE Disabled Disabled 0 Enabled Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit 1 ASOS Alarm or second output selection 9 1 ASOS Alarm RTC Alarm pulse output selected 0 Second RTC Second pulse output selected 1 CR CR Backup control register (BKP_CR) 0x2C 0x20 read-write 0x00000000 TPE Tamper pin enable 0 1 TPE General The TAMPER pin is free for general purpose I/O 0 Alternate Tamper alternate I/O function is activated 1 TPAL Tamper pin active level 1 1 TPAL High A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) 0 Low A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) 1 CSR CSR BKP_CSR control/status register (BKP_CSR) 0x30 0x20 0x00000000 CTE Clear Tamper event 0 1 write-only CTEW Reset Reset the TEF Tamper event flag (and the Tamper detector) 1 CTI Clear Tamper Interrupt 1 1 write-only CTIW Clear Clear the Tamper interrupt and the TIF Tamper interrupt flag 1 TPIE Tamper Pin interrupt enable 2 1 read-write TPIE Disabled Tamper interrupt disabled 0 Enabled Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register 1 TEF Tamper Event Flag 8 1 read-only TIF Tamper Interrupt Flag 9 1 read-only FSMC Flexible static memory controller FSMC 0xA0000000 0x0 0x1000 registers FSMC FSMC global interrupt 48 BCR1 BCR1 SRAM/NOR-Flash chip-select control register 1 0x0 0x20 read-write 0x000030D0 CBURSTRW CBURSTRW 19 1 CBURSTRW Disabled Write operations are always performed in asynchronous mode 0 Enabled Write operations are performed in synchronous mode 1 ASYNCWAIT ASYNCWAIT 15 1 ASYNCWAIT Disabled Wait signal not used in asynchronous mode 0 Enabled Wait signal used even in asynchronous mode 1 EXTMOD EXTMOD 14 1 EXTMOD Disabled Values inside the FMC_BWTR are not taken into account 0 Enabled Values inside the FMC_BWTR are taken into account 1 WAITEN WAITEN 13 1 WAITEN Disabled Values inside the FMC_BWTR are taken into account 0 Enabled NWAIT signal enabled 1 WREN WREN 12 1 WREN Disabled Write operations disabled for the bank by the FMC 0 Enabled Write operations enabled for the bank by the FMC 1 WAITCFG WAITCFG 11 1 WAITCFG BeforeWaitState NWAIT signal is active one data cycle before wait state 0 DuringWaitState NWAIT signal is active during wait state 1 WAITPOL WAITPOL 9 1 WAITPOL ActiveLow NWAIT active low 0 ActiveHigh NWAIT active high 1 BURSTEN BURSTEN 8 1 BURSTEN Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 FACCEN FACCEN 6 1 FACCEN Disabled Corresponding NOR Flash memory access is disabled 0 Enabled Corresponding NOR Flash memory access is enabled 1 MWID MWID 4 2 MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 MTYP MTYP 2 2 MTYP SRAM SRAM memory type 0 PSRAM PSRAM (CRAM) memory type 1 Flash NOR Flash/OneNAND Flash 2 MUXEN MUXEN 1 1 MUXEN Disabled Address/Data non-multiplexed 0 Enabled Address/Data multiplexed on databus 1 MBKEN MBKEN 0 1 MBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 WRAPMOD WRAPMOD 10 1 WRAPMOD Disabled Direct wrapped burst is not enabled 0 Enabled Direct wrapped burst is enabled 1 CPSIZE CRAM page size 16 3 read-write CPSIZE NoBurstSplit No burst split when crossing page boundary 0 Bytes128 128 bytes CRAM page size 1 Bytes256 256 bytes CRAM page size 2 Bytes512 512 bytes CRAM page size 3 Bytes1024 1024 bytes CRAM page size 4 4 0x8 1-4 BTR%s BTR%s SRAM/NOR-Flash chip-select timing register %s 0x4 0x20 read-write 0xFFFFFFFF ACCMOD ACCMOD 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATLAT DATLAT 24 4 0 15 CLKDIV CLKDIV 20 4 1 15 BUSTURN BUSTURN 16 4 0 15 DATAST DATAST 8 8 1 255 ADDHLD ADDHLD 4 4 1 15 ADDSET ADDSET 0 4 0 15 3 0x8 2-4 BCR%s BCR%s SRAM/NOR-Flash chip-select control register %s 0x8 0x20 read-write 0x000030D0 CBURSTRW CBURSTRW 19 1 ASYNCWAIT ASYNCWAIT 15 1 EXTMOD EXTMOD 14 1 WAITEN WAITEN 13 1 WREN WREN 12 1 WAITCFG WAITCFG 11 1 WRAPMOD WRAPMOD 10 1 WAITPOL WAITPOL 9 1 BURSTEN BURSTEN 8 1 FACCEN FACCEN 6 1 MWID MWID 4 2 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MBKEN MBKEN 0 1 CPSIZE CRAM page size 16 3 read-write 4 0x8 1-4 BWTR%s BWTR%s SRAM/NOR-Flash write timing registers %s 0x104 0x20 read-write 0x0FFFFFFF ACCMOD ACCMOD 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATAST DATAST 8 8 1 255 ADDHLD ADDHLD 4 4 1 15 ADDSET ADDSET 0 4 0 15 BUSTURN Bus turnaround phase duration 16 4 read-write 0 15 OTG_FS_DEVICE USB on the go full speed USB_OTG_FS 0x50000800 0x0 0x400 registers DCFG DCFG OTG_FS device configuration register (OTG_FS_DCFG) 0x0 0x20 read-write 0x02200000 DSPD Device speed 0 2 NZLSOHSK Non-zero-length status OUT handshake 2 1 DAD Device address 4 7 PFIVL Periodic frame interval 11 2 DCTL DCTL OTG_FS device control register (OTG_FS_DCTL) 0x4 0x20 0x00000000 RWUSIG Remote wakeup signaling 0 1 read-write SDIS Soft disconnect 1 1 read-write GINSTS Global IN NAK status 2 1 read-only GONSTS Global OUT NAK status 3 1 read-only TCTL Test control 4 3 read-write SGINAK Set global IN NAK 7 1 read-write CGINAK Clear global IN NAK 8 1 read-write SGONAK Set global OUT NAK 9 1 read-write CGONAK Clear global OUT NAK 10 1 read-write POPRGDNE Power-on programming done 11 1 read-write DSTS DSTS OTG_FS device status register (OTG_FS_DSTS) 0x8 0x20 read-only 0x00000010 SUSPSTS Suspend status 0 1 ENUMSPD Enumerated speed 1 2 EERR Erratic error 3 1 FNSOF Frame number of the received SOF 8 14 DIEPMSK DIEPMSK OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) 0x10 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 TOM Timeout condition mask (Non-isochronous endpoints) 3 1 ITTXFEMSK IN token received when TxFIFO empty mask 4 1 INEPNMM IN token received with EP mismatch mask 5 1 INEPNEM IN endpoint NAK effective mask 6 1 DOEPMSK DOEPMSK OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) 0x14 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 STUPM SETUP phase done mask 3 1 OTEPDM OUT token received when endpoint disabled mask 4 1 DAINT DAINT OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) 0x18 0x20 read-only 0x00000000 IEPINT IN endpoint interrupt bits 0 16 OEPINT OUT endpoint interrupt bits 16 16 DAINTMSK DAINTMSK OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) 0x1C 0x20 read-write 0x00000000 IEPM IN EP interrupt mask bits 0 16 OEPM OUT EP interrupt mask bits 16 16 DVBUSDIS DVBUSDIS OTG_FS device VBUS discharge time register 0x28 0x20 read-write 0x000017D7 VBUSDT Device VBUS discharge time 0 16 DVBUSPULSE DVBUSPULSE OTG_FS device VBUS pulsing time register 0x2C 0x20 read-write 0x000005B8 DVBUSP Device VBUS pulsing time 0 12 DIEPEMPMSK DIEPEMPMSK OTG_FS device IN endpoint FIFO empty interrupt mask register 0x34 0x20 read-write 0x00000000 INEPTXFEM IN EP Tx FIFO empty interrupt mask bits 0 16 DIEP0 Device IN endpoint 0 0x100 CTL DIEPCTL0 OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) 0x0 0x20 0x00000000 MPSIZ Maximum packet size 0 2 read-write USBAEP USB active endpoint 15 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-only STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPDIS Endpoint disable 30 1 read-only EPENA Endpoint enable 31 1 read-write INT DIEPINT0 device endpoint-x interrupt register 0x8 0x20 0x00000080 TXFE TXFE 7 1 read-only INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write EPDISD EPDISD 1 1 read-write XFRC XFRC 0 1 read-write TSIZ DIEPTSIZ0 device endpoint-0 transfer size register 0x10 0x20 read-write 0x00000000 PKTCNT Packet count 19 2 XFRSIZ Transfer size 0 7 TXFSTS DTXFSTS0 OTG_FS device IN endpoint transmit FIFO status register 0x18 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space available 0 16 3 0x20 1-3 DIEP%s Device IN endpoint X 0x120 CTL DIEPCTL1 OTG device endpoint-1 control register 0x0 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM_SD1PID SODDFRM/SD1PID 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only TXFNUM TXFNUM 22 4 read-write STALL STALL handshake 21 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write INT DIEPINT1 device endpoint-1 interrupt register 0x8 TSIZ DIEPTSIZ1 device endpoint-1 transfer size register 0x10 0x20 read-write 0x00000000 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 TXFSTS DTXFSTS1 OTG_FS device IN endpoint transmit FIFO status register 0x18 DOEP0 Device OUT endpoint 0 0x300 CTL DOEPCTL0 device endpoint-0 control register 0x0 0x20 0x00008000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only STALL STALL handshake 21 1 read-write SNPM SNPM 20 1 read-write EPTYP EPTYP 18 2 read-only NAKSTS NAKSTS 17 1 read-only USBAEP USBAEP 15 1 read-only MPSIZ MPSIZ 0 2 read-only INT DOEPINT0 device endpoint-0 interrupt register 0x8 0x20 read-write 0x00000080 B2BSTUP B2BSTUP 6 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 EPDISD EPDISD 1 1 XFRC XFRC 0 1 TSIZ DOEPTSIZ0 device OUT endpoint-0 transfer size register 0x10 0x20 read-write 0x00000000 STUPCNT SETUP packet count 29 2 PKTCNT Packet count 19 1 XFRSIZ Transfer size 0 7 3 0x20 1-3 DOEP%s Device IN endpoint X 0x320 CTL DOEPCTL1 device endpoint-1 control register 0x0 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM SODDFRM 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only STALL STALL handshake 21 1 read-write SNPM SNPM 20 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write INT DOEPINT1 device endpoint-1 interrupt register 0x8 TSIZ DOEPTSIZ1 device OUT endpoint-1 transfer size register 0x10 0x20 read-write 0x00000000 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 OTG_FS_GLOBAL USB on the go full speed USB_OTG_FS 0x50000000 0x0 0x400 registers GOTGCTL GOTGCTL OTG_FS control and status register (OTG_FS_GOTGCTL) 0x0 0x20 0x00000800 SRQSCS Session request success 0 1 read-only SRQ Session request 1 1 read-write HNGSCS Host negotiation success 8 1 read-only HNPRQ HNP request 9 1 read-write HSHNPEN Host set HNP enable 10 1 read-write DHNPEN Device HNP enabled 11 1 read-write CIDSTS Connector ID status 16 1 read-only DBCT Long/short debounce time 17 1 read-only ASVLD A-session valid 18 1 read-only BSVLD B-session valid 19 1 read-only GOTGINT GOTGINT OTG_FS interrupt register (OTG_FS_GOTGINT) 0x4 0x20 read-write 0x00000000 SEDET Session end detected 2 1 SRSSCHG Session request success status change 8 1 HNSSCHG Host negotiation success status change 9 1 HNGDET Host negotiation detected 17 1 ADTOCHG A-device timeout change 18 1 DBCDNE Debounce done 19 1 GAHBCFG GAHBCFG OTG_FS AHB configuration register (OTG_FS_GAHBCFG) 0x8 0x20 read-write 0x00000000 GINT Global interrupt mask 0 1 TXFELVL TxFIFO empty level 7 1 PTXFELVL Periodic TxFIFO empty level 8 1 GUSBCFG GUSBCFG OTG_FS USB configuration register (OTG_FS_GUSBCFG) 0xC 0x20 0x00000A00 TOCAL FS timeout calibration 0 3 read-write PHYSEL Full Speed serial transceiver select 6 1 write-only SRPCAP SRP-capable 8 1 read-write HNPCAP HNP-capable 9 1 read-write TRDT USB turnaround time 10 4 read-write FHMOD Force host mode 29 1 read-write FDMOD Force device mode 30 1 read-write CTXPKT Corrupt Tx packet 31 1 read-write GRSTCTL GRSTCTL OTG_FS reset register (OTG_FS_GRSTCTL) 0x10 0x20 0x20000000 CSRST Core soft reset 0 1 read-write HSRST HCLK soft reset 1 1 read-write FCRST Host frame counter reset 2 1 read-write RXFFLSH RxFIFO flush 4 1 read-write TXFFLSH TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write AHBIDL AHB master idle 31 1 read-only GINTSTS GINTSTS OTG_FS core interrupt register (OTG_FS_GINTSTS) 0x14 0x20 0x04000020 CMOD Current mode of operation 0 1 read-only MMIS Mode mismatch interrupt 1 1 read-write OTGINT OTG interrupt 2 1 read-only SOF Start of frame 3 1 read-write RXFLVL RxFIFO non-empty 4 1 read-only NPTXFE Non-periodic TxFIFO empty 5 1 read-only GINAKEFF Global IN non-periodic NAK effective 6 1 read-only GOUTNAKEFF Global OUT NAK effective 7 1 read-only ESUSP Early suspend 10 1 read-write USBSUSP USB suspend 11 1 read-write USBRST USB reset 12 1 read-write ENUMDNE Enumeration done 13 1 read-write ISOODRP Isochronous OUT packet dropped interrupt 14 1 read-write EOPF End of periodic frame interrupt 15 1 read-write IEPINT IN endpoint interrupt 18 1 read-only OEPINT OUT endpoint interrupt 19 1 read-only IISOIXFR Incomplete isochronous IN transfer 20 1 read-write IPXFR_INCOMPISOOUT Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) 21 1 read-write HPRTINT Host port interrupt 24 1 read-only HCINT Host channels interrupt 25 1 read-only PTXFE Periodic TxFIFO empty 26 1 read-only CIDSCHG Connector ID status change 28 1 read-write DISCINT Disconnect detected interrupt 29 1 read-write SRQINT Session request/new session detected interrupt 30 1 read-write WKUPINT Resume/remote wakeup detected interrupt 31 1 read-write GINTMSK GINTMSK OTG_FS interrupt mask register (OTG_FS_GINTMSK) 0x18 0x20 0x00000000 MMISM Mode mismatch interrupt mask 1 1 read-write OTGINT OTG interrupt mask 2 1 read-write SOFM Start of frame mask 3 1 read-write RXFLVLM Receive FIFO non-empty mask 4 1 read-write NPTXFEM Non-periodic TxFIFO empty mask 5 1 read-write GINAKEFFM Global non-periodic IN NAK effective mask 6 1 read-write GONAKEFFM Global OUT NAK effective mask 7 1 read-write ESUSPM Early suspend mask 10 1 read-write USBSUSPM USB suspend mask 11 1 read-write USBRST USB reset mask 12 1 read-write ENUMDNEM Enumeration done mask 13 1 read-write ISOODRPM Isochronous OUT packet dropped interrupt mask 14 1 read-write EOPFM End of periodic frame interrupt mask 15 1 read-write EPMISM Endpoint mismatch interrupt mask 17 1 read-write IEPINT IN endpoints interrupt mask 18 1 read-write OEPINT OUT endpoints interrupt mask 19 1 read-write IISOIXFRM Incomplete isochronous IN transfer mask 20 1 read-write IPXFRM_IISOOXFRM Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) 21 1 read-write PRTIM Host port interrupt mask 24 1 read-write HCIM Host channels interrupt mask 25 1 read-write PTXFEM Periodic TxFIFO empty mask 26 1 read-write CIDSCHGM Connector ID status change mask 28 1 read-write DISCINT Disconnect detected interrupt mask 29 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write WUIM Resume/remote wakeup detected interrupt mask 31 1 read-write GRXSTSR_Device GRXSTSR_Device OTG_FS Receive status debug read(Device mode) 0x1C 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FRMNUM Frame number 21 4 GRXSTSR_Host GRXSTSR_Host OTG status debug read (host mode) GRXSTSR_Device 0x1C 0x20 read-only 0x00000000 CHNUM Channel number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 GRXSTSP_Device OTG status read and pop (device mode) 0x20 0x20 read-only 0x00000000 FRMNUM Frame number 21 4 PKTSTS Packet status 17 4 DPID Data PID 15 2 BCNT Byte count 4 11 EPNUM Endpoint number 0 4 GRXSTSP_Host OTG status read and pop (host mode) GRXSTSP_Device 0x20 0x20 read-only 0x00000000 PKTSTS Packet status 17 4 DPID Data PID 15 2 BCNT Byte count 4 11 CHNUM Channel number 0 4 GRXFSIZ GRXFSIZ OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) 0x24 0x20 read-write 0x00000200 RXFD RxFIFO depth 0 16 DIEPTXF0 DIEPTXF0 OTG_FS non-periodic transmit FIFO size register (Device mode) 0x28 0x20 read-write 0x00000200 TX0FSA Endpoint 0 transmit RAM start address 0 16 TX0FD Endpoint 0 TxFIFO depth 16 16 HNPTXFSIZ HNPTXFSIZ OTG_FS non-periodic transmit FIFO size register (Host mode) DIEPTXF0 0x28 0x20 read-write 0x00000200 NPTXFSA Non-periodic transmit RAM start address 0 16 NPTXFD Non-periodic TxFIFO depth 16 16 GNPTXSTS GNPTXSTS OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) 0x2C 0x20 read-only 0x00080200 NPTXFSAV Non-periodic TxFIFO space available 0 16 NPTQXSAV Non-periodic transmit request queue space available 16 8 NPTXQTOP Top of the non-periodic transmit request queue 24 7 GCCFG GCCFG OTG_FS general core configuration register (OTG_FS_GCCFG) 0x38 0x20 read-write 0x00000000 PWRDWN Power down 16 1 VBUSASEN Enable the VBUS sensing device 18 1 VBUSBSEN Enable the VBUS sensing device 19 1 SOFOUTEN SOF output enable 20 1 CID CID core ID register 0x3C 0x20 read-write 0x00001000 PRODUCT_ID Product ID field 0 32 HPTXFSIZ HPTXFSIZ OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) 0x100 0x20 read-write 0x02000600 PTXSA Host periodic TxFIFO start address 0 16 PTXFSIZ Host periodic TxFIFO depth 16 16 3 0x4 1-3 DIEPTXF%s DIEPTXF%s OTG_FS device IN endpoint transmit FIFO size register 0x104 0x20 read-write 0x02000400 INEPTXSA IN endpoint FIFO2 transmit RAM start address 0 16 INEPTXFD IN endpoint TxFIFO depth 16 16 OTG_FS_HOST USB on the go full speed USB_OTG_FS 0x50000400 0x0 0x400 registers HCFG HCFG OTG_FS host configuration register (OTG_FS_HCFG) 0x0 0x20 0x00000000 FSLSPCS FS/LS PHY clock select 0 2 read-write FSLSS FS- and LS-only support 2 1 read-write HFIR HFIR OTG_FS Host frame interval register 0x4 0x20 read-write 0x0000EA60 FRIVL Frame interval 0 16 HFNUM HFNUM OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) 0x8 0x20 read-only 0x00003FFF FRNUM Frame number 0 16 FTREM Frame time remaining 16 16 HPTXSTS HPTXSTS OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) 0x10 0x20 0x00080100 PTXFSAVL Periodic transmit data FIFO space available 0 16 read-write PTXQSAV Periodic transmit request queue space available 16 8 read-only PTXQTOP Top of the periodic transmit request queue 24 8 read-only HAINT HAINT OTG_FS Host all channels interrupt register 0x14 0x20 read-only 0x00000000 HAINT Channel interrupts 0 16 HAINTMSK HAINTMSK OTG_FS host all channels interrupt mask register 0x18 0x20 read-write 0x00000000 HAINTM Channel interrupt mask 0 16 HPRT HPRT OTG_FS host port control and status register (OTG_FS_HPRT) 0x40 0x20 0x00000000 PCSTS Port connect status 0 1 read-only PCDET Port connect detected 1 1 read-write PENA Port enable 2 1 read-write PENCHNG Port enable/disable change 3 1 read-write POCA Port overcurrent active 4 1 read-only POCCHNG Port overcurrent change 5 1 read-write PRES Port resume 6 1 read-write PSUSP Port suspend 7 1 read-write PRST Port reset 8 1 read-write PLSTS Port line status 10 2 read-only PPWR Port power 12 1 read-write PTCTL Port test control 13 4 read-write PSPD Port speed 17 2 read-only 8 0x20 0-7 HC%s Host channel 0x100 CHAR HCCHAR0 OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) 0x0 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 INT HCINT0 OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) 0x8 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 INTMSK HCINTMSK0 OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) 0xC 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 TSIZ HCTSIZ0 OTG_FS host channel-0 transfer size register 0x10 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 OTG_FS_PWRCLK USB on the go full speed USB_OTG_FS 0x50000E00 0x0 0x400 registers PCGCCTL PCGCCTL OTG_FS power and clock gating control register 0x0 0x20 read-write 0x00000000 STPPCLK Stop PHY clock 0 1 GATEHCLK Gate HCLK 1 1 PHYSUSP PHY Suspended 4 1 SDIO Secure digital input/output interface SDIO 0x40018000 0x0 0x400 registers SDIO SDIO global interrupt 49 POWER POWER power control register 0x0 0x20 read-write 0x00000000 PWRCTRL PWRCTRL 0 2 PWRCTRL PowerOff Power off 0 PowerOn Power on 3 CLKCR CLKCR SDI clock control register 0x4 0x20 read-write 0x00000000 HWFC_EN HW Flow Control enable 14 1 HWFC_EN Disabled HW Flow Control is disabled 0 Enabled HW Flow Control is enabled 1 NEGEDGE SDIO_CK dephasing selection bit 13 1 NEGEDGE Rising SDIO_CK generated on the rising edge 0 Falling SDIO_CK generated on the falling edge 1 WIDBUS Wide bus mode enable bit 11 2 WIDBUS BusWidth1 1 lane wide bus 0 BusWidth4 4 lane wide bus 1 BusWidth8 8 lane wide bus 2 BYPASS Clock divider bypass enable bit 10 1 BYPASS Disabled SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal. 0 Enabled SDIOCLK directly drives the SDIO_CK output signal 1 PWRSAV Power saving configuration bit 9 1 PWRSAV Enabled SDIO_CK clock is always enabled 0 Disabled SDIO_CK is only enabled when the bus is active 1 CLKEN Clock enable bit 8 1 CLKEN Disabled Disable clock 0 Enabled Enable clock 1 CLKDIV Clock divide factor 0 8 0 255 ARG ARG argument register 0x8 0x20 read-write 0x00000000 CMDARG Command argument 0 32 0 4294967295 CMD CMD command register 0xC 0x20 read-write 0x00000000 CE_ATACMD CE-ATA command 14 1 CE_ATACMD Disabled CE-ATA command disabled 0 Enabled CE-ATA command enabled 1 nIEN not Interrupt Enable 13 1 nIEN Disabled Interrupts to the CE-ATA not disabled 0 Enabled Interrupt to the CE-ATA are disabled 1 ENCMDcompl Enable CMD completion 12 1 ENCMDcompl Disabled Command complete signal disabled 0 Enabled Command complete signal enabled 1 SDIOSuspend SD I/O suspend command 11 1 SDIOSuspend Disabled Next command is not a SDIO suspend command 0 Enabled Next command send is a SDIO suspend command 1 CPSMEN Command path state machine (CPSM) Enable bit 10 1 CPSMEN Disabled Command path state machine disabled 0 Enabled Command path state machine enabled 1 WAITPEND CPSM Waits for ends of data transfer (CmdPend internal signal). 9 1 WAITPEND Disabled Don't wait for data end 0 Enabled Wait for end of data transfer signal before sending command 1 WAITINT CPSM waits for interrupt request 8 1 WAITINT Disabled Don't wait for interrupt request 0 Enabled Wait for interrupt request 1 WAITRESP Wait for response bits 6 2 WAITRESP NoResponse No response 0 ShortResponse Short response 1 NoResponse2 No reponse 2 LongResponse Long reponse 3 CMDINDEX Command index 0 6 0 63 RESPCMD RESPCMD command response register 0x10 0x20 read-only 0x00000000 RESPCMD Response command index 0 6 0 63 4 0x4 1-4 RESP%s RESP%s SDIO response %s register 0x14 0x20 read-only 0x00000000 CARDSTATUS Status of a card, which is part of the received response 0 32 0 4294967295 DTIMER DTIMER data timer register 0x24 0x20 read-write 0x00000000 DATATIME Data timeout period 0 32 0 4294967295 DLEN DLEN data length register 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value 0 25 0 33554431 DCTRL DCTRL data control register 0x2C 0x20 read-write 0x00000000 SDIOEN SD I/O enable functions 11 1 SDIOEN Disabled SDIO operations disabled 0 Enabled SDIO operations enabled 1 RWMOD Read wait mode 10 1 RWMOD D2 Read wait control stopping using SDIO_D2 0 Ck Read wait control using SDIO_CK 1 RWSTOP Read wait stop 9 1 RWSTOP Disabled Read wait in progress if RWSTART is enabled 0 Enabled Enable for read wait stop if RWSTART is enabled 1 RWSTART Read wait start 8 1 RWSTART Disabled Don't start read wait operation 0 Enabled Read wait operation starts 1 DBLOCKSIZE Data block size 4 4 0 15 DMAEN DMA enable bit 3 1 DMAEN Disabled Dma disabled 0 Enabled Dma enabled 1 DTMODE Data transfer mode selection 1: Stream or SDIO multibyte data transfer. 2 1 DTMODE BlockMode Bloack data transfer 0 StreamMode Stream or SDIO multibyte data transfer 1 DTDIR Data transfer direction selection 1 1 DTDIR ControllerToCard From controller to card 0 CardToController From card to controller 1 DTEN DTEN 0 1 DTEN Disabled Disabled 0 Enabled Start transfer 1 DCOUNT DCOUNT data counter register 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value 0 25 0 33554431 STA STA status register 0x34 0x20 read-only 0x00000000 CEATAEND CE-ATA command completion signal received for CMD61 23 1 CEATAEND NotReceived Completion signal not received 0 Received CE-ATA command completion signal received for CMD61 1 SDIOIT SDIO interrupt received 22 1 SDIOIT NotReceived SDIO interrupt not receieved 0 Received SDIO interrupt received 1 RXDAVL Data available in receive FIFO 21 1 RXDAVL NotAvailable Data not available in receive FIFO 0 Available Data available in receive FIFO 1 TXDAVL Data available in transmit FIFO 20 1 TXDAVL NotAvailable Data not available in transmit FIFO 0 Available Data available in transmit FIFO 1 RXFIFOE Receive FIFO empty 19 1 RXFIFOE NotEmpty Receive FIFO not empty 0 Empty Receive FIFO empty 1 TXFIFOE Transmit FIFO empty 18 1 TXFIFOE NotEmpty Transmit FIFO not empty 0 Empty Transmit FIFO empty. When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words. 1 RXFIFOF Receive FIFO full 17 1 RXFIFOF NotFull Transmit FIFO not full 0 Full Receive FIFO full. When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full. 1 TXFIFOF Transmit FIFO full 16 1 TXFIFOF NotFull Transmit FIFO not full 0 Full Transmit FIFO full 1 RXFIFOHF Receive FIFO half full: there are at least 8 words in the FIFO 15 1 RXFIFOHF NotHalfFull Receive FIFO not half full 0 HalfFull Receive FIFO half full. At least 8 words in the FIFO 1 TXFIFOHE Transmit FIFO half empty: at least 8 words can be written into the FIFO 14 1 TXFIFOHE NotHalfEmpty Transmit FIFO not half empty 0 HalfEmpty Transmit FIFO half empty. At least 8 words can be written into the FIFO 1 RXACT Data receive in progress 13 1 RXACT NotInProgress Data receive not in progress 0 InProgress Data receive in progress 1 TXACT Data transmit in progress 12 1 TXACT NotInProgress Data transmit is not in progress 0 InProgress Data transmit in progress 1 CMDACT Command transfer in progress 11 1 CMDACT NotInProgress Command transfer not in progress 0 InProgress Command tranfer in progress 1 DBCKEND Data block sent/received (CRC check passed) 10 1 DBCKEND NotTransferred Data block not sent/received (CRC check failed) 0 Transferred Data block sent/received (CRC check passed) 1 STBITERR Start bit not detected on all data signals in wide bus mode 9 1 STBITERR Detected No start bit detected error 0 NotDetected Start bit not detected error 1 DATAEND Data end (data counter, SDIDCOUNT, is zero) 8 1 DATAEND NotDone Not done 0 Done Data end (DCOUNT, is zero) 1 CMDSENT Command sent (no response required) 7 1 CMDSENT NotSent Command not sent 0 Sent Command sent (no response required) 1 CMDREND Command response received (CRC check passed) 6 1 CMDREND NotDone Command not done 0 Done Command response received (CRC check passed) 1 RXOVERR Received FIFO overrun error 5 1 RXOVERR NoOverrun No FIFO overrun error 0 Overrun Receive FIFO overrun error 1 TXUNDERR Transmit FIFO underrun error 4 1 TXUNDERR NoUnderrun No transmit FIFO underrun error 0 Underrun Transmit FIFO underrun error 1 DTIMEOUT Data timeout 3 1 DTIMEOUT NoTimeout No data timeout 0 Timeout Data timeout 1 CTIMEOUT Command response timeout 2 1 CTIMEOUT NoTimeout No Command timeout 0 Timeout Command timeout 1 DCRCFAIL Data block sent/received (CRC check failed) 1 1 DCRCFAIL NotFailed No Data block sent/received crc check fail 0 Failed Data block sent/received crc failed 1 CCRCFAIL Command response received (CRC check failed) 0 1 CCRCFAIL NotFailed Command response received, crc check passed 0 Failed Command response received, crc check failed 1 ICR ICR interrupt clear register 0x38 0x20 read-write 0x00000000 CCRCFAILC CCRCFAIL flag clear bit 0 1 CCRCFAILCW write Clear Clear flag 1 CEATAENDC CEATAEND flag clear bit 23 1 SDIOITC SDIOIT flag clear bit 22 1 DBCKENDC DBCKEND flag clear bit 10 1 STBITERRC STBITERR flag clear bit 9 1 DATAENDC DATAEND flag clear bit 8 1 CMDSENTC CMDSENT flag clear bit 7 1 CMDRENDC CMDREND flag clear bit 6 1 RXOVERRC RXOVERR flag clear bit 5 1 TXUNDERRC TXUNDERR flag clear bit 4 1 DTIMEOUTC DTIMEOUT flag clear bit 3 1 CTIMEOUTC CTIMEOUT flag clear bit 2 1 DCRCFAILC DCRCFAIL flag clear bit 1 1 MASK MASK mask register 0x3C 0x20 read-write 0x00000000 CCRCFAILIE Command CRC fail interrupt enable 0 1 CCRCFAILIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 CEATAENDIE CE-ATA command completion signal received interrupt enable 23 1 SDIOITIE SDIO mode interrupt received interrupt enable 22 1 RXDAVLIE Data available in Rx FIFO interrupt enable 21 1 TXDAVLIE Data available in Tx FIFO interrupt enable 20 1 RXFIFOEIE Rx FIFO empty interrupt enable 19 1 TXFIFOEIE Tx FIFO empty interrupt enable 18 1 RXFIFOFIE Rx FIFO full interrupt enable 17 1 TXFIFOFIE Tx FIFO full interrupt enable 16 1 RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 RXACTIE Data receive acting interrupt enable 13 1 TXACTIE Data transmit acting interrupt enable 12 1 CMDACTIE Command acting interrupt enable 11 1 DBCKENDIE Data block end interrupt enable 10 1 STBITERRIE Start bit error interrupt enable 9 1 DATAENDIE Data end interrupt enable 8 1 CMDSENTIE Command sent interrupt enable 7 1 CMDRENDIE Command response received interrupt enable 6 1 RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 DTIMEOUTIE Data timeout interrupt enable 3 1 CTIMEOUTIE Command timeout interrupt enable 2 1 DCRCFAILIE Data CRC fail interrupt enable 1 1 FIFOCNT FIFOCNT FIFO counter register 0x48 0x20 read-only 0x00000000 FIFOCOUNT Remaining number of words to be written to or read from the FIFO. 0 24 0 16777215 FIFO FIFO data FIFO register 0x80 0x20 read-write 0x00000000 FIFOData Receive and transmit FIFO data 0 32 0 4294967295 TIM13 General purpose timer TIM 0x40001C00 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 à t_CK_INT 1 Div4 t_DTS = 4 à t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 CCMR1_Input CCMR1_Input capture/compare mode register (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 1 0x0 1-1 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 0 65535 1 0x4 1-1 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 TIM10 General purpose timer TIM 0x40015000 TIM11 TIM 0x40015400 TIM1_TRG_COM TIM1 Trigger and Commutation interrupts 26 TIM9 General purpose timer TIM 0x40014C00 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 à t_CK_INT 1 Div4 t_DTS = 4 à t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS Master mode selection 4 3 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = â1 then the prescaler is clocked directly by the internal clock. 0 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 0 65535 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 TIM12 TIM 0x40001800 TIM8 Advanced timer TIM 0x40013400 0x0 0x400 registers TIM8_BRK TIM8 Break interrupt 43 TIM8_UP TIM8 Update interrupt 44 TIM8_TRG_COM TIM8 Trigger and Commutation interrupts 45 TIM8_CC TIM8 Capture Compare interrupt 46 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 à t_CK_INT 1 Div4 t_DTS = 4 à t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 4 0x2 1-4 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 3 0x2 1-3 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = â1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 3 0x4 1-3 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 3 0x4 1-3 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 DCR DCR DMA control register 0x48 0x20 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 8 0 255 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 DTG Dead-time generator setup 0 8 0 255 TIM1 TIM 0x40012C00 TIM1_BRK TIM1 Break interrupt 24 TIM1_UP TIM1 Update interrupt 25 TIM1_CC TIM1 Capture Compare interrupt 27 ADC2 Analog to digital converter ADC 0x40012800 0x0 0x400 registers SR SR status register 0x0 CR1 CR1 control register 1 0x4 0x20 read-write 0x00000000 AWDEN Analog watchdog enable on regular channels 23 1 JAWDEN Analog watchdog enable on injected channels 22 1 DISCNUM Discontinuous mode channel count 13 3 JDISCEN Discontinuous mode on injected channels 12 1 DISCEN Discontinuous mode on regular channels 11 1 JAUTO Automatic injected group conversion 10 1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 SCAN Scan mode 8 1 JEOCIE Interrupt enable for injected channels 7 1 AWDIE Analog watchdog interrupt enable 6 1 EOCIE Interrupt enable for EOC 5 1 AWDCH Analog watchdog channel select bits 0 5 CR2 CR2 control register 2 0x8 SMPR1 SMPR1 sample time register 1 0xC SMPR2 SMPR2 sample time register 2 0x10 4 0x4 1-4 JOFR%s JOFR%s injected channel data offset register %s 0x14 HTR HTR watchdog higher threshold register 0x24 LTR LTR watchdog lower threshold register 0x28 SQR1 SQR1 regular sequence register 1 0x2C SQR2 SQR2 regular sequence register 2 0x30 SQR3 SQR3 regular sequence register 3 0x34 JSQR JSQR injected sequence register 0x38 4 0x4 1-4 JDR%s JDR%s injected data register x 0x3C DR DR regular data register 0x4C 0x20 read-only 0x00000000 DATA Regular data 0 16 DAC Digital to analog converter DAC 0x40007400 0x0 0x400 registers CR CR Control register (DAC_CR) 0x0 0x20 read-write 0x00000000 2 0x10 1-2 EN%s DAC channel%s enable 0 1 EN1 Disabled DAC channel X disabled 0 Enabled DAC channel X enabled 1 2 0x10 1-2 BOFF%s DAC channel%s output buffer disable 1 1 BOFF1 Enabled DAC channel X output buffer enabled 0 Disabled DAC channel X output buffer disabled 1 2 0x10 1-2 TEN%s DAC channel%s trigger enable 2 1 TEN1 Disabled DAC channel X trigger disabled 0 Enabled DAC channel X trigger enabled 1 TSEL1 DAC channel1 trigger selection 3 3 TSEL1 Tim6Trgo Timer 6 TRGO event 0 Tim8Trgo Timer 8 TRGO event 1 Tim7Trgo Timer 7 TRGO event 2 Tim5Trgo Timer 5 TRGO event 3 Tim2Trgo Timer 2 TRGO event 4 Tim4Trgo Timer 4 TRGO event 5 Exti9 EXTI line 9 6 Swtrig Software trigger 7 2 0x10 1-2 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true 2 0x10 1-2 MAMP%s DAC channel%s mask/amplitude selector 8 4 MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 2 0x10 1-2 DMAEN%s DAC channel%s DMA enable 12 1 DMAEN1 Disabled DAC channel X DMA mode disabled 0 Enabled DAC channel X DMA mode enabled 1 TSEL2 DAC channel2 trigger selection 19 3 2 0x10 1-2 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 SWTRIGR SWTRIGR DAC software trigger register (DAC_SWTRIGR) 0x4 0x20 write-only 0x00000000 2 0x1 1-2 SWTRIG%s DAC channel%s software trigger 0 1 SWTRIG1 Disabled DAC channel X software trigger disabled 0 Enabled DAC channel X software trigger enabled 1 2 0xC 1-2 DHR12R%s DHR12R%s channel%s 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit right-aligned data 0 12 0 4095 2 0xC 1-2 DHR12L%s DHR12L%s channel%s 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit left-aligned data 4 12 0 4095 2 0xC 1-2 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACCDHR DAC channel1 8-bit right-aligned data 0 8 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved 0x20 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 0 4095 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved 0x24 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 0 4095 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved 0x28 0x20 read-write 0x00000000 2 0x8 1-2 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 0 255 2 0x4 1-2 DOR%s DOR%s channel%s data output register 0x2C 0x20 read-only 0x00000000 DACCDOR DAC channel1 data output 0 12 SR SR DAC status register 0x34 0x20 read-write 0x00000000 2 0x10 1-2 DMAUDR%s DAC channel%s DMA underrun flag 13 1 DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 USB Universal serial bus full-speed device interface USB 0x40005C00 0x0 0x400 registers USB_HP_CAN_TX USB High Priority or CAN TX interrupts 19 USB_LP_CAN_RX0 USB Low Priority or CAN RX0 interrupts 20 8 0x4 0-7 EP%sR EP%sR endpoint %s register 0x0 0x20 read-write 0x00000000 EA Endpoint address 0 4 0 15 STAT_TX Status bits, for transmission transfers 4 2 read-write oneToToggle STAT_TXR read Disabled all transmission requests addressed to this endpoint are ignored 0 Stall the endpoint is stalled and all transmission requests result in a STALL handshake 1 Nak the endpoint is naked and all transmission requests result in a NAK handshake 2 Valid this endpoint is enabled for transmission 3 DTOG_TX Data Toggle, for transmission transfers 6 1 oneToToggle CTR_TX Correct Transfer for transmission 7 1 zeroToClear EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 EP_TYPE Bulk Bulk endpoint 0 Control Control endpoint 1 Iso Iso endpoint 2 Interrupt Interrupt endpoint 3 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 read-write oneToToggle STAT_RXR read Disabled all reception requests addressed to this endpoint are ignored 0 Stall the endpoint is stalled and all reception requests result in a STALL handshake 1 Nak the endpoint is naked and all reception requests result in a NAK handshake 2 Valid this endpoint is enabled for reception 3 DTOG_RX Data Toggle, for reception transfers 14 1 oneToToggle CTR_RX Correct transfer for reception 15 1 zeroToClear CNTR CNTR control register 0x40 0x20 read-write 0x00000003 FRES Force USB Reset 0 1 FRES NoReset Clear USB reset 0 Reset Force a reset of the USB peripheral, exactly like a RESET signaling on the USB 1 PDWN Power down 1 1 PDWN Disabled No power down 0 Enabled Enter power down mode 1 LPMODE Low-power mode 2 1 LPMODE Disabled No low-power mode 0 Enabled Enter low-power mode 1 FSUSP Force suspend 3 1 FSUSP NoEffect No effect 0 Suspend Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected 1 RESUME Resume request 4 1 RESUME Requested Resume requested 1 ESOFM Expected start of frame interrupt mask 8 1 ESOFM Disabled ESOF Interrupt disabled 0 Enabled ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 SOFM Start of frame interrupt mask 9 1 SOFM Disabled SOF Interrupt disabled 0 Enabled SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 RESETM USB reset interrupt mask 10 1 RESETM Disabled RESET Interrupt disabled 0 Enabled RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 SUSPM Suspend mode interrupt mask 11 1 SUSPM Disabled Suspend Mode Request SUSP Interrupt disabled 0 Enabled SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 WKUPM Wakeup interrupt mask 12 1 WKUPM Disabled WKUP Interrupt disabled 0 Enabled WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ERRM Error interrupt mask 13 1 ERRM Disabled ERR Interrupt disabled 0 Enabled ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 PMAOVRM Packet memory area over / underrun interrupt mask 14 1 PMAOVRM Disabled PMAOVR Interrupt disabled 0 Enabled PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 CTRM Correct transfer interrupt mask 15 1 CTRM Disabled Correct Transfer (CTR) Interrupt disabled 0 Enabled CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ISTR ISTR interrupt status register 0x44 0x20 read-write 0x00000000 EP_ID Endpoint Identifier 0 4 0 15 DIR Direction of transaction 4 1 DIR To Data transmitted by the USB peripheral to the host PC 0 From Data received by the USB peripheral from the host PC 1 ESOF Expected start frame 8 1 zeroToClear ESOFR read NotExpectedStartOfFrame NotExpectedStartOfFrame 0 ExpectedStartOfFrame An SOF packet is expected but not received 1 ESOFW write Clear Clear flag 0 SOF start of frame 9 1 zeroToClear SOFR read NotStartOfFrame NotStartOfFrame 0 StartOfFrame Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus 1 SOFW write Clear Clear flag 0 RESET reset request 10 1 zeroToClear RESETR read NotReset NotReset 0 Reset Peripheral detects an active USB RESET signal at its inputs 1 RESETW write Clear Clear flag 0 SUSP Suspend mode request 11 1 zeroToClear SUSPR read NotSuspend NotSuspend 0 Suspend No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus 1 SUSPW write Clear Clear flag 0 WKUP Wakeup 12 1 zeroToClear WKUPR read NotWakeup NotWakeup 0 Wakeup Activity is detected that wakes up the USB peripheral 1 WKUPW write Clear Clear flag 0 ERR Error 13 1 zeroToClear ERRR read NotOverrun Errors are not occurred 0 Error One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred 1 ERRW write Clear Clear flag 0 PMAOVR Packet memory area over / underrun 14 1 zeroToClear PMAOVRR read NotOverrun Overrun is not occurred 0 Overrun Microcontroller has not been able to respond in time to an USB memory request 1 PMAOVRW write Clear Clear flag 0 CTR Correct transfer 15 1 CTR Completed Endpoint has successfully completed a transaction 1 FNR FNR frame number register 0x48 0x20 read-only 0x00000000 FN Frame number 0 11 0 2047 LSOF Lost SOF 11 2 0 3 LCK Locked 13 1 LCK Locked the frame timer remains in this state until an USB reset or USB suspend event occurs 1 RXDM Receive data - line status 14 1 RXDM Received received data minus upstream port data line 1 RXDP Receive data + line status 15 1 RXDP Received received data plus upstream port data line 1 DADDR DADDR device address 0x4C 0x20 read-write 0x00000000 ADD Device address 0 7 0 127 EF Enable function 7 1 EF Disabled USB device disabled 0 Enabled USB device enabled 1 BTABLE BTABLE Buffer table address 0x50 0x20 read-write 0x00000000 BTABLE Buffer table 3 13 0 8191 UART4 Universal asynchronous receiver transmitter USART 0x40004C00 0x0 0x400 registers SR SR Status register 0x0 0x10 0x000000C0 PE Parity error 0 1 read-only FE Framing error 1 1 read-only NE Noise error flag 2 1 read-only ORE Overrun error 3 1 read-only IDLE IDLE line detected 4 1 read-only RXNE Read data register not empty 5 1 read-write TC Transmission complete 6 1 read-write TXE Transmit data register empty 7 1 read-only LBD LIN break detection flag 8 1 read-write DR DR Data register 0x4 BRR BRR Baud rate register 0x8 CR1 CR1 Control register 1 0xC CR2 CR2 Control register 2 0x10 0x10 read-write 0x00000000 ADD Address of the USART node 0 4 LBDL lin break detection length 5 1 LBDIE LIN break detection interrupt enable 6 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop2 2 stop bits 2 LINEN LIN mode enable 14 1 CR3 CR3 Control register 3 0x14 0x10 read-write 0x00000000 EIE Error interrupt enable 0 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 HDSEL Half-duplex selection 3 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 GTPR Guard Time and Prescaler Register 0x18 0x10 read-write PSC IrDA Low-Power pulse width peripheral clock prescaler 0 8 UART5 0x40005000 UART4 UART4 global interrupt 52 UART5 UART5 global interrupt 53 SPI2 Serial peripheral interface SPI 0x40003800 0x0 0x400 registers SPI2 SPI2 global interrupt 36 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 DFF Data frame format 11 1 DFF EightBit 8-bit data frame format is selected for transmission/reception 0 SixteenBit 16-bit data frame format is selected for transmission/reception 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 SR SR status register 0x8 0x10 0x00000002 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 SPI3 0x40003C00 SPI3 SPI3 global interrupt 51 TIM4 General purpose timer TIM 0x40000800 TIM4 TIM4 global interrupt 30 TIM5 TIM 0x40000C00 TIM5 TIM5 global interrupt 50 TIM6 Basic timer TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 global interrupt 54 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS Master mode selection 4 3 MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Low counter value 0 16 0 65535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Low Auto-reload value 0 16 0 65535 TIM7 TIM 0x40001400 TIM7 TIM7 global interrupt 55 TIM14 TIM 0x40002000 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0x33D registers ISER0 ISER0 Interrupt Set-Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x200 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x300 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x30C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 MPU Memory protection unit MPU 0xE000ED90 0x0 0x15 registers TYPER TYPER MPU type register 0x0 0x20 read-only 0x00000800 SEPARATE Separate flag 0 1 DREGION Number of MPU data regions 8 8 IREGION Number of MPU instruction regions 16 8 CTRL CTRL MPU control register 0x4 0x20 read-only 0x00000000 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault 1 1 PRIVDEFENA Enable priviliged software access to default memory map 2 1 RNR RNR MPU region number register 0x8 0x20 read-write 0x00000000 REGION MPU region 0 8 RBAR RBAR MPU region base address register 0xC 0x20 read-write 0x00000000 REGION MPU region field 0 4 VALID MPU region number valid 4 1 ADDR Region base address field 5 27 RASR RASR MPU region attribute and size register 0x10 0x20 read-write 0x00000000 ENABLE Region enable bit. 0 1 SIZE Size of the MPU protection region 1 5 SRD Subregion disable bits 8 8 B memory attribute 16 1 C memory attribute 17 1 S Shareable memory attribute 18 1 TEX memory attribute 19 3 AP Access permission 24 3 XN Instruction access disable bit 28 1 SCB_ACTRL System control block ACTLR SCB 0xE000E008 0x0 0x5 registers ACTRL ACTRL Auxiliary control register 0x0 0x20 read-write 0x00000000 DISFOLD DISFOLD 2 1 FPEXCODIS FPEXCODIS 10 1 DISRAMODE DISRAMODE 11 1 DISITMATBFLUSH DISITMATBFLUSH 12 1 NVIC_STIR Nested vectored interrupt controller NVIC 0xE000EF00 0x0 0x5 registers STIR STIR Software trigger interrupt register 0x0 0x20 read-write 0x00000000 INTID Software generated interrupt ID 0 9 SCB System control block SCB 0xE000ED00 0x0 0x41 registers CPUID CPUID CPUID base register 0x0 0x20 read-only 0x410FC241 Revision Revision number 0 4 PartNo Part number of the processor 4 12 Constant Reads as 0xF 16 4 Variant Variant number 20 4 Implementer Implementer code 24 8 ICSR ICSR Interrupt control and state register 0x4 0x20 read-write 0x00000000 VECTACTIVE Active vector 0 9 RETTOBASE Return to base level 11 1 VECTPENDING Pending vector 12 7 ISRPENDING Interrupt pending flag 22 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVSET PendSV set-pending bit 28 1 NMIPENDSET NMI set-pending bit. 31 1 VTOR VTOR Vector table offset register 0x8 0x20 read-write 0x00000000 TBLOFF Vector table base offset field 9 21 AIRCR AIRCR Application interrupt and reset control register 0xC 0x20 read-write 0x00000000 VECTRESET VECTRESET 0 1 VECTCLRACTIVE VECTCLRACTIVE 1 1 SYSRESETREQ SYSRESETREQ 2 1 PRIGROUP PRIGROUP 8 3 ENDIANESS ENDIANESS 15 1 VECTKEYSTAT Register key 16 16 SCR SCR System control register 0x10 0x20 read-write 0x00000000 SLEEPONEXIT SLEEPONEXIT 1 1 SLEEPDEEP SLEEPDEEP 2 1 SEVEONPEND Send Event on Pending bit 4 1 CCR CCR Configuration and control register 0x14 0x20 read-write 0x00000000 NONBASETHRDENA Configures how the processor enters Thread mode 0 1 USERSETMPEND USERSETMPEND 1 1 UNALIGN__TRP UNALIGN_ TRP 3 1 DIV_0_TRP DIV_0_TRP 4 1 BFHFNMIGN BFHFNMIGN 8 1 STKALIGN STKALIGN 9 1 SHPR1 SHPR1 System handler priority registers 0x18 0x20 read-write 0x00000000 PRI_4 Priority of system handler 4 0 8 PRI_5 Priority of system handler 5 8 8 PRI_6 Priority of system handler 6 16 8 SHPR2 SHPR2 System handler priority registers 0x1C 0x20 read-write 0x00000000 PRI_11 Priority of system handler 11 24 8 SHPR3 SHPR3 System handler priority registers 0x20 0x20 read-write 0x00000000 PRI_14 Priority of system handler 14 16 8 PRI_15 Priority of system handler 15 24 8 SHCRS SHCRS System handler control and state register 0x24 0x20 read-write 0x00000000 MEMFAULTACT Memory management fault exception active bit 0 1 BUSFAULTACT Bus fault exception active bit 1 1 USGFAULTACT Usage fault exception active bit 3 1 SVCALLACT SVC call active bit 7 1 MONITORACT Debug monitor active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTPENDED Usage fault exception pending bit 12 1 MEMFAULTPENDED Memory management fault exception pending bit 13 1 BUSFAULTPENDED Bus fault exception pending bit 14 1 SVCALLPENDED SVC call pending bit 15 1 MEMFAULTENA Memory management fault enable bit 16 1 BUSFAULTENA Bus fault enable bit 17 1 USGFAULTENA Usage fault enable bit 18 1 CFSR_UFSR_BFSR_MMFSR CFSR_UFSR_BFSR_MMFSR Configurable fault status register 0x28 0x20 read-write 0x00000000 IACCVIOL IACCVIOL 0 1 DACCVIOL DACCVIOL 1 1 MUNSTKERR MUNSTKERR 3 1 MSTKERR MSTKERR 4 1 MLSPERR MLSPERR 5 1 MMARVALID MMARVALID 7 1 IBUSERR Instruction bus error 8 1 PRECISERR Precise data bus error 9 1 IMPRECISERR Imprecise data bus error 10 1 UNSTKERR Bus fault on unstacking for a return from exception 11 1 STKERR Bus fault on stacking for exception entry 12 1 LSPERR Bus fault on floating-point lazy state preservation 13 1 BFARVALID Bus Fault Address Register (BFAR) valid flag 15 1 UNDEFINSTR Undefined instruction usage fault 16 1 INVSTATE Invalid state usage fault 17 1 INVPC Invalid PC load usage fault 18 1 NOCP No coprocessor usage fault. 19 1 UNALIGNED Unaligned access usage fault 24 1 DIVBYZERO Divide by zero usage fault 25 1 HFSR HFSR Hard fault status register 0x2C 0x20 read-write 0x00000000 VECTTBL Vector table hard fault 1 1 FORCED Forced hard fault 30 1 DEBUG_VT Reserved for Debug use 31 1 MMFAR MMFAR Memory management fault address register 0x34 0x20 read-write 0x00000000 MMFAR Memory management fault address 0 32 BFAR BFAR Bus fault address register 0x38 0x20 read-write 0x00000000 BFAR Bus fault address 0 32 STK SysTick timer STK 0xE000E010 0x0 0x11 registers CTRL CTRL SysTick control and status register 0x0 0x20 read-write 0x00000000 ENABLE Counter enable 0 1 TICKINT SysTick exception request enable 1 1 CLKSOURCE Clock source selection 2 1 COUNTFLAG COUNTFLAG 16 1 LOAD_ LOAD_ SysTick reload value register 0x4 0x20 read-write 0x00000000 RELOAD RELOAD value 0 24 VAL VAL SysTick current value register 0x8 0x20 read-write 0x00000000 CURRENT Current counter value 0 24 CALIB CALIB SysTick calibration value register 0xC 0x20 read-write 0x00000000 TENMS Calibration value 0 24
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