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Showing content from https://stm32-rs.github.io/stm32-rs/STM32WL5X_CM0P.html below:

STM32WL5X_CM0P Peripheral Coverage

245/274 fields covered.

Clock control register

Offset: 0x0, size: 32, reset: 0x00000061, access: Unspecified

17/17 fields covered.

Bit 0: MSI clock enable.

Allowed values:
0: Disabled: MSI oscillator off
1: Enabled: MSI oscillator on

Bit 1: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready).

Allowed values:
0: NotReady: MSI oscillator not ready
1: Ready: MSI oscillator ready

Bit 2: MSI clock PLL enable.

Allowed values:
0: Off: MSI PLL Off
1: On: MSI PLL On

Bit 3: MSI range control selection.

Allowed values:
0: CSR: MSI frequency range defined by MSISRANGE[3:0] in the RCC_CSR register
1: CR: MSI frequency range defined by MSIRANGE[3:0] in the RCC_CR register

Bits 4-7: MSI clock ranges.

Allowed values:
0: Range100K: range 0 around 100 kHz
1: Range200K: range 1 around 200 kHz
2: Range400K: range 2 around 400 kHz
3: Range800K: range 3 around 800 kHz
4: Range1M: range 4 around 1 MHz
5: Range2M: range 5 around 2 MHz
6: Range4M: range 6 around 4 MHz (reset value)
7: Range8M: range 7 around 8 MHz
8: Range16M: range 8 around 16 MHz
9: Range24M: range 9 around 24 MHz
10: Range32M: range 10 around 32 MHz
11: Range48M: range 11 around 48 MHz

Bit 8: HSI16 clock enable.

Allowed values:
0: Disabled: HSI16 oscillator off
1: Enabled: HSI16 oscillator on

Bit 9: HSI16 always enable for peripheral kernel clocks..

Allowed values:
0: NotForced: No effect on HSI16 oscillator
1: Forced: HSI16 oscillator forced on even in Stop modes

Bit 10: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready).

Allowed values:
0: NotReady: HSI16 oscillator not ready
1: Ready: HSI16 oscillator ready

Bit 11: HSI16 automatic start from Stop.

Allowed values:
0: Disabled: HSI16 not enabled by hardware when exiting Stop modes with MSI as wakeup clock
1: Enabled: HSI16 enabled by hardware when exiting Stop mode with MSI as wakeup clock

Bit 12: HSI16 kernel clock ready flag for peripherals requests..

Allowed values:
0: NotReady: HSI16 oscillator not ready
1: Ready: HSI16 oscillator ready

Bit 16: HSE32 clock enable.

Allowed values:
0: Disabled: HSE32 oscillator for CPU disabled
1: Enabled: HSE32 oscillator for CPU enabled

Bit 17: HSE32 clock ready flag.

Allowed values:
0: NotReady: HSE32 oscillator not ready
1: Ready: HSE32 oscillator ready

Bit 19: HSE32 Clock security system enable.

Allowed values:
0: Disabled: HSE32 CSS off
1: Enabled: HSE32 CSS on if the HSE32 oscillator is stable and off if not

Bit 20: HSE32 sysclk prescaler.

Allowed values:
0: Div1: SYSCLK not divided (HSE32)
1: Div2: SYSCLK divided by two (HSE32/2)

Bit 21: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO..

Allowed values:
0: PB0: PB0 selected
1: VDDTCXO: VDDTCXO selected

Bit 24: Main PLL enable.

Allowed values:
0: Off: Main PLL Off
1: On: Main PLL On

Bit 25: Main PLL clock ready flag.

Allowed values:
0: Unlocked: PLL unlocked
1: Locked: PLL Locked

Internal clock sources calibration register

Offset: 0x4, size: 32, reset: 0x40000000, access: Unspecified

4/4 fields covered.

Bits 0-7: MSI clock calibration.

Allowed values: 0x0-0xff

Bits 8-15: MSI clock trimming.

Allowed values: 0x0-0xff

Bits 16-23: HSI16 clock calibration.

Allowed values: 0x0-0xff

Bits 24-30: HSI16 clock trimming.

Allowed values: 0x0-0x3f

Clock configuration register

Offset: 0x8, size: 32, reset: 0x00070000, access: Unspecified

11/11 fields covered.

Bits 0-1: System clock switch.

Allowed values:
0: MSI: MSI oscillator used as system clock
1: HSI16: HSI16 oscillator used as system clock
2: HSE32: HSE32 oscillator used as system clock
3: PLLR: PLLRCLK used as system clock

Bits 2-3: System clock switch status.

Allowed values:
0: MSI: MSI oscillator used as system clock
1: HSI16: HSI16 oscillator used as system clock
2: HSE32: HSE32 oscillator used as system clock
3: PLLR: PLLRCLK used as system clock

Bits 4-7: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.).

Allowed values:
1: Div3: SYSCLK divided by 3
2: Div5: SYSCLK divided by 5
5: Div6: SYSCLK divided by 6
6: Div10: SYSCLK divided by 10
7: Div32: SYSCLK divided by 32
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
0 (+): Div1: SYSCLK not divided

Bits 8-10: PCLK1 low-speed prescaler (APB1).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

Bits 11-13: PCLK2 high-speed prescaler (APB2).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

Bit 15: Wakeup from Stop and CSS backup clock selection.

Allowed values:
0: MSI: MSI oscillator selected as wakeup from stop clock and CSS backup clock
1: HSI16: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock

Bit 16: HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1).

Allowed values:
0: NotApplied: HCLK1 prescaler value not yet applied
1: Applied: HCLK1 prescaler value applied

Bit 17: PCLK1 prescaler flag (APB1).

Allowed values:
0: NotApplied: PCLK1 prescaler value not yet applied
1: Applied: PCLK1 prescaler value applied

Bit 18: PCLK2 prescaler flag (APB2).

Allowed values:
0: NotApplied: PCLK2 prescaler value not yet applied
1: Applied: PCLK2 prescaler value applied

Bits 24-27: Microcontroller clock output.

Allowed values:
0: NoClock: No clock
1: SYSCLK: SYSCLK clock selected
2: MSI: MSI oscillator clock selected
3: HSI16: HSI16 oscillator clock selected
4: HSE32: HSE32 oscillator clock selected
5: PLLR: Main PLLRCLK clock selected
6: LSI: LSI oscillator clock selected
8: LSE: LSE oscillator clock selected
13: PLLP: Main PLLPCLK clock selected
14: PLLQ: Main PLLQCLK clock selected

Bits 28-30: Microcontroller clock output prescaler.

Allowed values:
0: Div1: No division
1: Div2: Division by 2
2: Div4: Division by 4
3: Div8: Division by 8
4: Div16: Division by 16

PLL configuration register

Offset: 0xc, size: 32, reset: 0x22040100, access: read-write

9/9 fields covered.

Bits 0-1: Main PLL entry clock source.

Allowed values:
0: NoClock: No clock sent to PLL
1: MSI: MSI clock selected as PLL clock entry
2: HSI16: HSI16 clock selected as PLL clock entry
3: HSE32: HSE32 clock selected as PLL clock entry

Bits 4-6: Division factor for the main PLL input clock.

Allowed values:
0: Div1: VCO input = PLL input / PLLM
1: Div2: VCO input = PLL input / PLLM
2: Div3: VCO input = PLL input / PLLM
3: Div4: VCO input = PLL input / PLLM
4: Div5: VCO input = PLL input / PLLM
5: Div6: VCO input = PLL input / PLLM
6: Div7: VCO input = PLL input / PLLM
7: Div8: VCO input = PLL input / PLLM

Bits 8-14: Main PLL multiplication factor for VCO.

Allowed values: 0x6-0x7f

Bit 16: Main PLL PLLPCLK output enable.

Allowed values:
0: Disabled: PLLCLK output disabled
1: Enabled: PLLCLK output enabled

Bits 17-21: Main PLL division factor for PLLPCLK..

Allowed values:
1: Div2: PLL = VCO/(N+1)
2: Div3: PLL = VCO/(N+1)
3: Div4: PLL = VCO/(N+1)
4: Div5: PLL = VCO/(N+1)
5: Div6: PLL = VCO/(N+1)
6: Div7: PLL = VCO/(N+1)
7: Div8: PLL = VCO/(N+1)
8: Div9: PLL = VCO/(N+1)
9: Div10: PLL = VCO/(N+1)
10: Div11: PLL = VCO/(N+1)
11: Div12: PLL = VCO/(N+1)
12: Div13: PLL = VCO/(N+1)
13: Div14: PLL = VCO/(N+1)
14: Div15: PLL = VCO/(N+1)
15: Div16: PLL = VCO/(N+1)
16: Div17: PLL = VCO/(N+1)
17: Div18: PLL = VCO/(N+1)
18: Div19: PLL = VCO/(N+1)
19: Div20: PLL = VCO/(N+1)
20: Div21: PLL = VCO/(N+1)
21: Div22: PLL = VCO/(N+1)
22: Div23: PLL = VCO/(N+1)
23: Div24: PLL = VCO/(N+1)
24: Div25: PLL = VCO/(N+1)
25: Div26: PLL = VCO/(N+1)
26: Div27: PLL = VCO/(N+1)
27: Div28: PLL = VCO/(N+1)
28: Div29: PLL = VCO/(N+1)
29: Div30: PLL = VCO/(N+1)
30: Div31: PLL = VCO/(N+1)
31: Div32: PLL = VCO/(N+1)

Bit 24: Main PLL PLLQCLK output enable.

Allowed values:
0: Disabled: PLLCLK output disabled
1: Enabled: PLLCLK output enabled

Bits 25-27: Main PLL division factor for PLLQCLK.

Allowed values:
1: Div2: PLL = VCO/(N+1)
2: Div3: PLL = VCO/(N+1)
3: Div4: PLL = VCO/(N+1)
4: Div5: PLL = VCO/(N+1)
5: Div6: PLL = VCO/(N+1)
6: Div7: PLL = VCO/(N+1)
7: Div8: PLL = VCO/(N+1)

Bit 28: Main PLL PLLRCLK output enable.

Allowed values:
0: Disabled: PLLCLK output disabled
1: Enabled: PLLCLK output enabled

Bits 29-31: Main PLL division factor for PLLRCLK.

Allowed values:
1: Div2: PLL = VCO/(N+1)
2: Div3: PLL = VCO/(N+1)
3: Div4: PLL = VCO/(N+1)
4: Div5: PLL = VCO/(N+1)
5: Div6: PLL = VCO/(N+1)
6: Div7: PLL = VCO/(N+1)
7: Div8: PLL = VCO/(N+1)

Clock interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

Bit 0: LSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Bit 1: LSE ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Bit 2: MSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Bit 3: HSI16 ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Bit 4: HSE32 ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Bit 5: PLL ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Bit 9: LSE clock security system interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Clock interrupt flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

Bit 0: LSI ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

Bit 1: LSE ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

Bit 2: MSI ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

Bit 3: HSI16 ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

Bit 4: HSE32 ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

Bit 5: PLL ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

Bit 8: HSE32 Clock security system interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

Bit 9: LSE Clock security system interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

Clock interrupt clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

8/8 fields covered.

Bit 0: LSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

Bit 1: LSE ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

Bit 2: MSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

Bit 3: HSI16 ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

Bit 4: HSE32 ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

Bit 5: PLL ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

Bit 8: HSE32 Clock security system interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

Bit 9: LSE Clock security system interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

AHB1 peripheral reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 0: DMA1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 1: DMA2 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 2: DMAMUX1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 12: CRC reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

AHB2 peripheral reset register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 0: IO port A reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 1: IO port B reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 2: IO port C reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 7: IO port H reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

AHB3 peripheral reset register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bit 16: PKARST.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 17: AESRST.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 18: RNGRST.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 19: HSEMRST.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 20: IPCCRST.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 25: Flash interface reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

APB1 peripheral reset register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

Bit 0: TIM2 timer reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 14: SPI2S2 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 17: USART2 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 21: I2C1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 22: I2C2 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 23: I2C3 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 29: DAC1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 31: Low Power Timer 1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

APB1 peripheral reset register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bit 0: Low-power UART 1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 5: Low-power timer 2 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

Bit 6: Low-power timer 3 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

APB2 peripheral reset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

Bit 9: ADC reset.

Bit 11: TIM1 timer reset.

Bit 12: SPI1 reset.

Bit 14: USART1 reset.

Bit 17: TIM16 timer reset.

Bit 18: TIM17 timer reset.

APB3 peripheral reset register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bit 0: Sub-GHz radio SPI reset.

AHB1 peripheral clock enable register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 0: CPU1 DMA1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 1: CPU1 DMA2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 2: CPU1 DMAMUX1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 12: CPU1 CRC clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

AHB2 peripheral clock enable register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 0: CPU1 IO port A clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 1: CPU1 IO port B clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 2: CPU1 IO port C clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 7: CPU1 IO port H clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

AHB3 peripheral clock enable register

Offset: 0x50, size: 32, reset: 0x02080000, access: read-write

6/6 fields covered.

Bit 16: PKAEN.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 17: AESEN.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 18: RNGEN.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 19: HSEMEN.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 20: IPCCEN.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 25: CPU1 Flash interface clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB1 peripheral clock enable register 1

Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

Bit 0: CPU1 TIM2 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 10: CPU1 RTC APB clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 11: CPU1 Window watchdog clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 14: CPU1 SPI2S2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 17: CPU1 USART2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 21: CPU1 I2C1 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 22: CPU1 I2C2 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 23: CPU1 I2C3 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 29: CPU1 DAC1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 31: CPU1 Low power timer 1 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB1 peripheral clock enable register 2

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bit 0: CPU1 Low power UART 1 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 5: CPU1 Low power timer 2 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 6: CPU1 Low power timer 3 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB2 peripheral clock enable register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bit 9: CPU1 ADC clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 11: CPU1 TIM1 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 12: CPU1 SPI1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 14: CPU1 USART1clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 17: CPU1 TIM16 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 18: CPU1 TIM17 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB3 peripheral clock enable register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bit 0: sub-GHz radio SPI clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

AHB1 peripheral clocks enable in Sleep modes register

Offset: 0x68, size: 32, reset: 0x00001007, access: read-write

0/4 fields covered.

Bit 0: DMA1 clock enable during CPU1 CSleep mode..

Bit 1: DMA2 clock enable during CPU1 CSleep mode.

Bit 2: DMAMUX1 clock enable during CPU1 CSleep mode..

Bit 12: CRC clock enable during CPU1 CSleep mode..

AHB2 peripheral clocks enable in Sleep modes register

Offset: 0x6c, size: 32, reset: 0x00000087, access: read-write

0/4 fields covered.

Bit 0: IO port A clock enable during CPU1 CSleep mode..

Bit 1: IO port B clock enable during CPU1 CSleep mode..

Bit 2: IO port C clock enable during CPU1 CSleep mode..

Bit 7: IO port H clock enable during CPU1 CSleep mode..

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, size: 32, reset: 0x03870000, access: read-write

0/6 fields covered.

Bit 16: PKA accelerator clock enable during CPU1 CSleep mode..

Bit 17: AES accelerator clock enable during CPU1 CSleep mode..

Bit 18: True RNG clocks enable during CPU1 Csleep and CStop modes.

Bit 23: SRAM1 interface clock enable during CPU1 CSleep mode..

Bit 24: SRAM2 memory interface clock enable during CPU1 CSleep mode.

Bit 25: Flash interface clock enable during CPU1 CSleep mode..

APB1 peripheral clocks enable in Sleep mode register 1

Offset: 0x78, size: 32, reset: 0xA0E24C01, access: read-write

10/10 fields covered.

Bit 0: TIM2 timer clock enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 10: RTC bus clock enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 11: Window watchdog clocks enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 14: SPI2S2 clock enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 17: USART2 clock enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 21: I2C1 clock enable during CPU1 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 22: I2C2 clock enable during CPU1 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 23: I2C3 clock enable during CPU1 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 29: DAC1 clock enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 31: Low power timer 1 clock enable during CPU1 Csleep and CStop mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB1 peripheral clocks enable in Sleep mode register 2

Offset: 0x7c, size: 32, reset: 0x00000061, access: read-write

3/3 fields covered.

Bit 0: Low power UART 1 clock enable during CPU1 Csleep and CStop modes..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 5: Low power timer 2 clock enable during CPU1 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 6: Low power timer 3 clock enable during CPU1 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB2 peripheral clocks enable in Sleep mode register

Offset: 0x80, size: 32, reset: 0x00065A00, access: read-write

0/6 fields covered.

Bit 9: ADC clocks enable during CPU1 Csleep and CStop modes.

Bit 11: TIM1 timer clock enable during CPU1 CSleep mode..

Bit 12: SPI1 clock enable during CPU1 CSleep mode..

Bit 14: USART1 clock enable during CPU1 Csleep and CStop modes..

Bit 17: TIM16 timer clock enable during CPU1 CSleep mode..

Bit 18: TIM17 timer clock enable during CPU1 CSleep mode..

APB3 peripheral clock enable in Sleep mode register

Offset: 0x84, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

Bit 0: Sub-GHz radio SPI clock enable during Sleep and Stop modes.

Peripherals independent clock configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bits 0-1: USART1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

Bits 2-3: USART2 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

Bits 8-9: SPI2S2 I2S clock source selection.

Allowed values:
1: PLLQ: PLLQ clock selected
2: HSI16: HSI16 clock selected
3: I2S: External input I2S_CKIN selected

Bits 10-11: LPUART1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

Bits 12-13: I2C1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected

Bits 14-15: I2C2 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected

Bits 16-17: I2C3 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected

Bits 18-19: Low power timer 1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: LSI: LSI clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

Bits 20-21: Low power timer 2 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: LSI: LSI clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

Bits 22-23: Low power timer 3 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: LSI: LSI clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

Bits 28-29: ADC clock source selection.

Allowed values:
0: NoClock: No clock selected
1: HSI16: HSI16 clock selected
2: PLLP: PLLP clock selected
3: SYSCLK: SYSCLK clock selected

Bits 30-31: RNG clock source selection.

Allowed values:
0: PLLQ: PLLQ clock selected
1: LSI: LSI clock selected
2: LSE: LSE clock selected
3: MSI: MSI clock selected

Backup domain control register

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

13/13 fields covered.

Bit 0: LSE oscillator enable.

Allowed values:
0: Off: LSE oscillator off
1: On: LSE oscillator on

Bit 1: LSE oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

Bit 2: LSE oscillator bypass.

Allowed values:
0: Disabled: LSE oscillator not bypassed
1: Enabled: LSE oscillator bypassed

Bits 3-4: LSE oscillator drive capability.

Allowed values:
0: Low: Xtal mode lower driving capability
1: MedLow: Xtal mode medium-low driving capability
2: MedHigh: Xtal mode medium-high driving capability
3: High: Xtal mode higher driving capability

Bit 5: CSS on LSE enable.

Allowed values:
0: Disabled: CSS on LSE disabled
1: Enabled: CSS on LSE enabled

Bit 6: CSS on LSE failure Detection.

Allowed values:
0: NoFailure: No failure detected on LSE
1: Failure: Failure detected on LSE

Bit 7: LSE system clock enable.

Allowed values:
0: Disabled: LSE system clock disabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode
1: Enabled: LSE system clock enabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock selected
2: LSI: LSI oscillator clock selected
3: HSE32: HSE32 oscillator clock divided by 32 selected

Bit 11: LSE system clock ready.

Allowed values:
0: NotReady: LSE system clock not ready
1: Ready: LSE system clock ready

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC kernel clock disabled
1: Enabled: RTC kernel clock enabled

Bit 16: Backup domain software reset.

Allowed values:
0: NotActive: Reset not activated
1: Reset: Entire Backup domain reset

Bit 24: Low speed clock output enable.

Allowed values:
0: Disabled: LSCO disabled
1: Enabled: LSCO enabled

Bit 25: Low speed clock output selection.

Allowed values:
0: LSI: LSI clock selected
1: LSE: LSE clock selected

Control/status register

Offset: 0x94, size: 32, reset: 0x0C01C600, access: Unspecified

15/15 fields covered.

Bit 0: LSI oscillator enable.

Allowed values:
0: Off: LSI oscillator off
1: On: LSI oscillator on

Bit 1: LSI oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

Bit 4: LSI frequency prescaler.

Allowed values:
0: Div1: LSI clock not divided
1: Div128: LSI clock divided by 128

Bits 8-11: MSI clock ranges.

Allowed values:
4: f_1MHz: Range 4 around 1 MHz
5: f_2MHz: Range 5 around 2 MHz
6: f_4MHz: Range 6 around 4 MHz (reset value)
7: f_8MHz: Range 7 around 8 MHz

Bit 14: Radio in reset status flag.

Allowed values:
0: NoReset: Sub-GHz radio out of reset
1: Reset: Sub-GHz radio in reset

Bit 15: Radio reset.

Allowed values:
0: Removed: Sub-GHz radio software reset removed
1: Reset: Sub-GHz radio software reset active

Bit 23: Remove reset flag.

Allowed values:
0: NoEffect: No effect
1: Clear: Reset flags reset

Bit 24: Radio illegal access flag.

Allowed values:
0: NoIllegalCommand: No SUBGHZ radio illegal command occurred
1: IllegalCommand: SUBGHZ radio illegal command occurred

Bit 25: Option byte loader reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

Bit 26: Pin reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

Bit 27: BOR flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

Bit 29: Independent window watchdog reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

Extended clock recovery register

Offset: 0x108, size: 32, reset: 0x00030000, access: Unspecified

3/4 fields covered.

Bits 0-3: HCLK3 shared prescaler (AHB3, Flash, and SRAM2).

Allowed values:
1: Div3: SYSCLK divided by 3
2: Div5: SYSCLK divided by 5
5: Div6: SYSCLK divided by 6
6: Div10: SYSCLK divided by 10
7: Div32: SYSCLK divided by 32
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
0 (+): Div1: SYSCLK not divided

Bits 4-7: [dual core device only] HCLK2 prescaler (CPU2).

Bit 16: HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2).

Allowed values:
0: NotApplied: HCLK3 prescaler value not yet applied
1: Applied: HCLK3 prescaler value applied

Bit 17: CLK2 prescaler flag (CPU2).

CPU2 AHB1 peripheral clock enable register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 0: CPU2 DMA1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 1: CPU2 DMA2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 2: CPU2 DMAMUX1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 12: CPU2 CRC clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 AHB2 peripheral clock enable register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 0: CPU2 IO port A clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 1: CPU2 IO port B clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 2: CPU2 IO port C clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 7: CPU2 IO port H clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 AHB3 peripheral clock enable register [dual core device only]

Offset: 0x150, size: 32, reset: 0x02080000, access: read-write

6/6 fields covered.

Bit 16: CPU2 PKA accelerator clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 17: CPU2 AES accelerator clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 18: CPU2 True RNG clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 19: CPU2 HSEM clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 20: CPU2 IPCC interface clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 25: CPU2 Flash interface clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 APB1 peripheral clock enable register 1 [dual core device only]

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bit 0: CPU2 TIM2 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 10: CPU2 RTC APB clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 14: CPU2 SPI2S2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 17: CPU2 USART2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 21: CPU2 I2C1 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 22: CPU2 I2C2 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 23: CPU2 I2C3 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 29: CPU2 DAC1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 31: CPU2 Low power timer 1 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 APB1 peripheral clock enable register 2 [dual core device only]

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bit 0: CPU2 Low power UART 1 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 5: CPU2 Low power timer 2 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 6: CPU2 Low power timer 3 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 APB2 peripheral clock enable register [dual core device only]

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bit 9: ADC clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 11: CPU2 TIM1 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 12: CPU2 SPI1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 14: CPU2 USART1clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 17: CPU2 TIM16 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 18: CPU2 TIM17 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 APB3 peripheral clock enable register [dual core device only]

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bit 0: CPU2 sub-GHz radio SPI clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]

Offset: 0x168, size: 32, reset: 0x00001007, access: read-write

4/4 fields covered.

Bit 0: DMA1 clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 1: DMA2 clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 2: DMAMUX1 clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 12: CRC clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]

Offset: 0x16c, size: 32, reset: 0x00000087, access: read-write

4/4 fields covered.

Bit 0: IO port A clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 1: IO port B clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 2: IO port C clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 7: IO port H clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]

Offset: 0x170, size: 32, reset: 0x03870000, access: read-write

6/6 fields covered.

Bit 16: PKA accelerator clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 17: AES accelerator clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 18: True RNG clock enable during CPU2 CSleep and CStop mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 23: SRAM1 interface clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 24: SRAM2 memory interface clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 25: Flash interface clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]

Offset: 0x178, size: 32, reset: 0xA0E24401, access: read-write

9/9 fields covered.

Bit 0: TIM2 timer clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 10: RTC bus clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 14: SPI2S2 clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 17: USART2 clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 21: I2C1 clock enable during CPU2 CSleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 22: I2C2 clock enable during CPU2 CSleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 23: I2C3 clock enable during CPU2 CSleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 29: DAC1 clock enable during CPU2 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 31: Low power timer 1 clock enable during CPU2 CSleep and CStop mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]

Offset: 0x17c, size: 32, reset: 0x00000061, access: read-write

3/3 fields covered.

Bit 0: Low power UART 1 clock enable during CPU2 CSleep and CStop mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 5: Low power timer 2 clocks enable during CPU2 CSleep and CStop modes..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 6: Low power timer 3 clocks enable during CPU2 CSleep and CStop modes..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]

Offset: 0x180, size: 32, reset: 0x00065A00, access: read-write

6/6 fields covered.

Bit 9: ADC clocks enable during CPU2 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 11: TIM1 timer clock enable during CPU2 CSleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 12: SPI1 clock enable during CPU2 CSleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 14: USART1clock enable during CPU2 CSleep and CStop mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 17: TIM16 timer clock enable during CPU2 CSleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

Bit 18: TIM17 timer clock enable during CPU2 CSleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]

Offset: 0x184, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

Bit 0: sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

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