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Showing content from https://stm32-rs.github.io/stm32-rs/STM32WB05.html below:

STM32WB05 Peripheral Coverage

168/184 fields covered.

DMA_ISR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 28: Channel 8 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 29: Channel 8 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 30: Channel 8 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 31: Channel 8 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

DMA_IFCR register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 28: Channel 8 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 29: Channel 8 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 30: Channel 8 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 31: Channel 8 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

DMA_CCRx register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA_CNDTRx register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

DMA_CPARx register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CMARx register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CCRx register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA_CNDTRx register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

DMA_CPARx register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CMARx register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CCRx register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA_CNDTRx register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

DMA_CPARx register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CMARx register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CCRx register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA_CNDTRx register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

DMA_CPARx register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CMARx register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CCRx register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA_CNDTRx register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

DMA_CPARx register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CMARx register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CCRx register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA_CNDTRx register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

DMA_CPARx register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CMARx register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CCRx register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA_CNDTRx register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

DMA_CPARx register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CMARx register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CCRx register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA_CNDTRx register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

DMA_CPARx register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

DMA_CMARx register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

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