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Showing content from https://stm32-rs.github.io/stm32-rs/STM32L4x3.html below:

STM32L4x3 Peripheral Coverage

Overall: 4307/5376 fields covered

0x50040000: Analog-to-Digital Converter

181/182 fields covered.

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

Bit 1: EOSMP.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 2: EOC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 3: EOS.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 5: JEOC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 6: JEOS.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 10: JQOVF.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

Bit 2: EOCIE.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

Bit 3: EOSIE.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

Bit 5: JEOCIE.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

Bit 6: JEOSIE.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 10: JQOVFIE.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

Bit 1: ADDIS.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

Bit 2: ADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

Bit 3: JADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

Bit 5: JADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

Bit 28: ADVREGEN.

Allowed values:
0: Disabled: ADC Voltage regulator disabled
1: Enabled: ADC Voltage regulator enabled

Bit 29: DEEPPWD.

Allowed values:
0: NotDeepPowerDown: ADC not in Deep-power down
1: DeepPowerDown: ADC in Deep-power-down (default reset state)

Bit 30: ADCALDIF.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

Bit 31: ADCAL.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

18/19 fields covered.

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

Bit 1: DMACFG.

Allowed values:
0: OneShot: DMA One Shot mode selected
1: Circular: DMA Circular mode selected

Bits 3-4: RES.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

Bits 6-9: EXTSEL.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 12: OVRMOD.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 14: AUTDLY.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bits 17-19: DISCNUM.

Allowed values: 0x0-0x7

Bit 20: JDISCEN.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bit 21: JQM.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

Bit 22: AWD1SGL.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

Bit 24: JAWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

Bit 25: JAUTO.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bits 26-30: AWDCH1CH.

Allowed values: 0x0-0x12

Bit 31: JQDIS.

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bit 0: DMAEN.

Allowed values:
0: Disabled: Regular Oversampling disabled
1: Enabled: Regular Oversampling enabled

Bit 1: DMACFG.

Allowed values:
0: Disabled: Injected Oversampling disabled
1: Enabled: Injected Oversampling enabled

Bits 2-4: RES.

Allowed values:
0: Ratio2: 2x
1: Ratio4: 4x
2: Ratio8: 8x
3: Ratio16: 16x
4: Ratio32: 32x
5: Ratio64: 64x
6: Ratio128: 128x
7: Ratio256: 256x

Bits 5-8: ALIGN.

Allowed values:
0: NoShift: No Shift
1: Shift1Bit: Shift 1-bit
2: Shift2Bit: Shift 2-bit
3: Shift3Bit: Shift 3-bit
4: Shift4Bit: Shift 4-bit
5: Shift5Bit: Shift 5-bit
6: Shift6Bit: Shift 6-bit
7: Shift7Bit: Shift 7-bit
8: Shift8Bit: Shift 8-bit

Bit 9: EXTSEL.

Allowed values:
0: All: All oversampled conversions for a channel are done consecutively following a trigger
1: Single: Each oversampled conversion for a channel needs a new trigger

Bit 10: EXTEN.

Allowed values:
0: ContinuedMode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: ResumedMode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

Bits 0-7: LT2.

Allowed values: 0x0-0xff

Bits 16-23: HT2.

Allowed values: 0x0-0xff

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

Bits 0-7: LT3.

Allowed values: 0x0-0xff

Bits 16-23: HT3.

Allowed values: 0x0-0xff

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-3: L.

Allowed values: 0x0-0xf

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Regular data.

Allowed values: 0x0-0xffff

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

Bits 0-1: JL.

Allowed values: 0x0-0x3

Bits 2-5: JEXTSEL.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

Bits 6-7: JEXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bits 8-12: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 14-18: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 20-24: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 26-30: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 1: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 2: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 3: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 4: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 5: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 6: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 7: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 8: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 9: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 10: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 11: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 12: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 13: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 14: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 15: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 16: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 17: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 18: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 1: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 2: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 3: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 4: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 5: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 6: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 7: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 8: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 9: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 10: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 11: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 12: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 13: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 14: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 15: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 16: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 17: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 18: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

19/19 fields covered.

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-6: CALFACT_S.

Allowed values: 0x0-0x7f

Bits 16-22: CALFACT_D.

Allowed values: 0x0-0x7f

0x50040300: Analog-to-Digital Converter

28/33 fields covered.

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

Bit 0: ADDRDY_MST.

Bit 1: EOSMP_MST.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 2: EOC_MST.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 3: EOS_MST.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 4: OVR_MST.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 5: JEOC_MST.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 6: JEOS_MST.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 7: AWD1_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 8: AWD2_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 9: AWD3_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 10: JQOVF_MST.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

Bit 16: ADRDY_SLV.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

Bit 17: EOSMP_SLV.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 18: End of regular conversion of the slave ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 19: End of regular sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 20: Overrun flag of the slave ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 21: End of injected conversion flag of the slave ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 22: End of injected sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 23: Analog watchdog 1 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 24: Analog watchdog 2 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 25: Analog watchdog 3 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 26: Injected Context Queue Overflow flag of the slave ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/9 fields covered.

Bits 0-4: Dual ADC mode selection.

Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only

Bits 8-11: Delay between 2 sampling phases.

Allowed values: 0x0-0xf

Bit 13: DMA configuration (for multi-ADC mode).

Bits 14-15: Direct memory access mode for multi ADC mode.

Bits 16-17: ADC clock mode.

Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4

Bits 18-21: ADC prescaler.

Bit 22: VREFINT enable.

Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled

Bit 23: CH17SEL.

Bit 24: CH18SEL.

ADC common regular data register for dual and triple modes

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-15: Regular data of the master ADC.

Bits 16-31: Regular data of the slave ADC.

0x50040100: Analog-to-Digital Converter

181/182 fields covered.

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

Bit 1: EOSMP.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 2: EOC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 3: EOS.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 5: JEOC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 6: JEOS.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 10: JQOVF.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

Bit 2: EOCIE.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

Bit 3: EOSIE.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

Bit 5: JEOCIE.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

Bit 6: JEOSIE.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 10: JQOVFIE.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

Bit 1: ADDIS.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

Bit 2: ADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

Bit 3: JADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

Bit 5: JADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

Bit 28: ADVREGEN.

Allowed values:
0: Disabled: ADC Voltage regulator disabled
1: Enabled: ADC Voltage regulator enabled

Bit 29: DEEPPWD.

Allowed values:
0: NotDeepPowerDown: ADC not in Deep-power down
1: DeepPowerDown: ADC in Deep-power-down (default reset state)

Bit 30: ADCALDIF.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

Bit 31: ADCAL.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

18/19 fields covered.

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

Bit 1: DMACFG.

Allowed values:
0: OneShot: DMA One Shot mode selected
1: Circular: DMA Circular mode selected

Bits 3-4: RES.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

Bits 6-9: EXTSEL.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 12: OVRMOD.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 14: AUTDLY.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bits 17-19: DISCNUM.

Allowed values: 0x0-0x7

Bit 20: JDISCEN.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bit 21: JQM.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

Bit 22: AWD1SGL.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

Bit 24: JAWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

Bit 25: JAUTO.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bits 26-30: AWDCH1CH.

Allowed values: 0x0-0x12

Bit 31: JQDIS.

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bit 0: DMAEN.

Allowed values:
0: Disabled: Regular Oversampling disabled
1: Enabled: Regular Oversampling enabled

Bit 1: DMACFG.

Allowed values:
0: Disabled: Injected Oversampling disabled
1: Enabled: Injected Oversampling enabled

Bits 2-4: RES.

Allowed values:
0: Ratio2: 2x
1: Ratio4: 4x
2: Ratio8: 8x
3: Ratio16: 16x
4: Ratio32: 32x
5: Ratio64: 64x
6: Ratio128: 128x
7: Ratio256: 256x

Bits 5-8: ALIGN.

Allowed values:
0: NoShift: No Shift
1: Shift1Bit: Shift 1-bit
2: Shift2Bit: Shift 2-bit
3: Shift3Bit: Shift 3-bit
4: Shift4Bit: Shift 4-bit
5: Shift5Bit: Shift 5-bit
6: Shift6Bit: Shift 6-bit
7: Shift7Bit: Shift 7-bit
8: Shift8Bit: Shift 8-bit

Bit 9: EXTSEL.

Allowed values:
0: All: All oversampled conversions for a channel are done consecutively following a trigger
1: Single: Each oversampled conversion for a channel needs a new trigger

Bit 10: EXTEN.

Allowed values:
0: ContinuedMode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: ResumedMode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

Bits 0-7: LT2.

Allowed values: 0x0-0xff

Bits 16-23: HT2.

Allowed values: 0x0-0xff

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

Bits 0-7: LT3.

Allowed values: 0x0-0xff

Bits 16-23: HT3.

Allowed values: 0x0-0xff

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-3: L.

Allowed values: 0x0-0xf

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Regular data.

Allowed values: 0x0-0xffff

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

Bits 0-1: JL.

Allowed values: 0x0-0x3

Bits 2-5: JEXTSEL.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

Bits 6-7: JEXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bits 8-12: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 14-18: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 20-24: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 26-30: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 1: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 2: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 3: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 4: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 5: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 6: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 7: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 8: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 9: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 10: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 11: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 12: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 13: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 14: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 15: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 16: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 17: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 18: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 1: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 2: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 3: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 4: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 5: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 6: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 7: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 8: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 9: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 10: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 11: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 12: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 13: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 14: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 15: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 16: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 17: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 18: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

19/19 fields covered.

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-6: CALFACT_S.

Allowed values: 0x0-0x7f

Bits 16-22: CALFACT_D.

Allowed values: 0x0-0x7f

0x50040200: Analog-to-Digital Converter

181/182 fields covered.

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

Bit 1: EOSMP.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 2: EOC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 3: EOS.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 5: JEOC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 6: JEOS.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 10: JQOVF.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

Bit 2: EOCIE.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

Bit 3: EOSIE.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

Bit 5: JEOCIE.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

Bit 6: JEOSIE.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 10: JQOVFIE.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

Bit 1: ADDIS.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

Bit 2: ADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

Bit 3: JADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

Bit 5: JADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

Bit 28: ADVREGEN.

Allowed values:
0: Disabled: ADC Voltage regulator disabled
1: Enabled: ADC Voltage regulator enabled

Bit 29: DEEPPWD.

Allowed values:
0: NotDeepPowerDown: ADC not in Deep-power down
1: DeepPowerDown: ADC in Deep-power-down (default reset state)

Bit 30: ADCALDIF.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

Bit 31: ADCAL.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

18/19 fields covered.

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

Bit 1: DMACFG.

Allowed values:
0: OneShot: DMA One Shot mode selected
1: Circular: DMA Circular mode selected

Bits 3-4: RES.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

Bits 6-9: EXTSEL.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 12: OVRMOD.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 14: AUTDLY.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bits 17-19: DISCNUM.

Allowed values: 0x0-0x7

Bit 20: JDISCEN.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bit 21: JQM.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

Bit 22: AWD1SGL.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

Bit 24: JAWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

Bit 25: JAUTO.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bits 26-30: AWDCH1CH.

Allowed values: 0x0-0x12

Bit 31: JQDIS.

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bit 0: DMAEN.

Allowed values:
0: Disabled: Regular Oversampling disabled
1: Enabled: Regular Oversampling enabled

Bit 1: DMACFG.

Allowed values:
0: Disabled: Injected Oversampling disabled
1: Enabled: Injected Oversampling enabled

Bits 2-4: RES.

Allowed values:
0: Ratio2: 2x
1: Ratio4: 4x
2: Ratio8: 8x
3: Ratio16: 16x
4: Ratio32: 32x
5: Ratio64: 64x
6: Ratio128: 128x
7: Ratio256: 256x

Bits 5-8: ALIGN.

Allowed values:
0: NoShift: No Shift
1: Shift1Bit: Shift 1-bit
2: Shift2Bit: Shift 2-bit
3: Shift3Bit: Shift 3-bit
4: Shift4Bit: Shift 4-bit
5: Shift5Bit: Shift 5-bit
6: Shift6Bit: Shift 6-bit
7: Shift7Bit: Shift 7-bit
8: Shift8Bit: Shift 8-bit

Bit 9: EXTSEL.

Allowed values:
0: All: All oversampled conversions for a channel are done consecutively following a trigger
1: Single: Each oversampled conversion for a channel needs a new trigger

Bit 10: EXTEN.

Allowed values:
0: ContinuedMode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: ResumedMode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

Bits 0-7: LT2.

Allowed values: 0x0-0xff

Bits 16-23: HT2.

Allowed values: 0x0-0xff

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

Bits 0-7: LT3.

Allowed values: 0x0-0xff

Bits 16-23: HT3.

Allowed values: 0x0-0xff

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-3: L.

Allowed values: 0x0-0xf

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Regular data.

Allowed values: 0x0-0xffff

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

Bits 0-1: JL.

Allowed values: 0x0-0x3

Bits 2-5: JEXTSEL.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

Bits 6-7: JEXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bits 8-12: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 14-18: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 20-24: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 26-30: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Allowed values: 0x0-0xffff

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 1: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 2: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 3: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 4: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 5: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 6: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 7: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 8: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 9: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 10: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 11: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 12: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 13: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 14: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 15: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 16: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 17: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 18: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 1: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 2: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 3: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 4: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 5: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 6: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 7: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 8: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 9: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 10: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 11: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 12: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 13: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 14: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 15: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 16: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 17: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 18: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

19/19 fields covered.

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-6: CALFACT_S.

Allowed values: 0x0-0x7f

Bits 16-22: CALFACT_D.

Allowed values: 0x0-0x7f

0x50040300: ADC common registers

33/33 fields covered.

ADC common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

Bit 0: master ADC ready.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

Bit 1: End of Sampling phase flag of the master ADC.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 2: End of regular conversion flag of the master ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 3: End of regular sequence flag of the master ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 4: Overrun flag of the master ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 5: End of injected conversion flag of the master ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 6: End of injected sequence flag of the master ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 7: Analog watchdog 1 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 8: Analog watchdog 2 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 9: Analog watchdog 3 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 10: Injected Context Queue Overflow flag of the master ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

Bit 16: Slave ADC ready.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

Bit 17: End of Sampling phase flag of the slave ADC.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 18: End of regular conversion flag of the slave ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 19: End of regular sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 20: Overrun flag of the slave ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 21: End of injected conversion flag of the slave ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 22: End of injected sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 23: Analog watchdog 1 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 24: Analog watchdog 2 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 25: Analog watchdog 3 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 26: Injected Context Queue Overflow flag of the slave ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bits 0-4: Dual ADC mode selection.

Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only

Bits 8-11: Delay between 2 sampling phases.

Allowed values: 0x0-0xf

Bit 13: DMA configuration (for dual ADC mode).

Allowed values:
0: OneShotMode: DMA One Shot mode selected
1: CircularMode: DMA Circular mode selected

Bits 14-15: Direct memory access mode for dual ADC mode.

Allowed values:
0: Disabled: MDMA mode disabled
1: Interleaved: Enable dual interleaved mode to output to the master channel of DFSDM interface both Master and the Slave result (16-bit data width)
2: Bits12_10: MDMA mode enabled for 12 and 10-bit resolution
3: Bits8_6: MDMA mode enabled for 8 and 6-bit resolution

Bits 16-17: ADC clock mode.

Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4

Bits 18-21: ADC prescaler.

Allowed values:
0: Div1: Input ADC clock not divided
1: Div2: Input ADC clock divided by 2
2: Div4: Input ADC clock divided by 4
3: Div6: Input ADC clock divided by 6
4: Div8: Input ADC clock divided by 8
5: Div10: Input ADC clock divided by 10
6: Div12: Input ADC clock divided by 12
7: Div16: Input ADC clock divided by 16
8: Div32: Input ADC clock divided by 32
9: Div64: Input ADC clock divided by 64
10: Div128: Input ADC clock divided by 128
11: Div256: Input ADC clock divided by 256

Bit 22: Vrefint enable.

Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled

Bit 23: Temperature sensor selection.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

Bit 24: VBAT selection.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

ADC common regular data register for dual mode

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-15: Regular data of the master ADC.

Allowed values: 0x0-0xffff

Bits 16-31: Regular data of the slave ADC.

Allowed values: 0x0-0xffff

0x50060000: Advanced encryption standard hardware accelerator

39/39 fields covered.

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

Bit 0: AES enable.

Allowed values:
0: Disabled: Disable AES
1: Enabled: Enable AES

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

Allowed values:
0: None: Word
1: HalfWord: Half-word (16-bit)
2: Byte: Byte (8-bit)
3: Bit: Bit

Bits 3-4: AES operating mode.

Allowed values:
0: Mode1: Mode 1: encryption
1: Mode2: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
2: Mode3: Mode 3: decryption
3: Mode4: Mode 4: key derivation then single decryption

Bits 5-6: AES chaining mode.

Allowed values:
0: ECB: Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1
1: CBC: Cipher-block chaining (CBC)
2: CTR: Counter mode (CTR)
3: GCM: Galois counter mode (GCM) and Galois message authentication code (GMAC)

Bit 7: Computation Complete Flag Clear.

Allowed values:
1: Clear: Clear computation complete flag

Bit 8: Error clear.

Allowed values:
1: Clear: Clear RDERR and WRERR flags

Bit 9: CCF flag interrupt enable.

Allowed values:
0: Disabled: Disable (mask) CCF interrupt
1: Enabled: Enable CCF interrupt

Bit 10: Error interrupt enable.

Allowed values:
0: Disabled: Disable (mask) error interrupt
1: Enabled: Enable error interrupt

Bit 11: Enable DMA management of data input phase.

Allowed values:
0: Disabled: Disable DMA Input
1: Enabled: Enable DMA Input

Bit 12: Enable DMA management of data output phase.

Allowed values:
0: Disabled: Disable DMA Output
1: Enabled: Enabled DMA Output

Bits 13-14: GCM or CCM phase selection.

Allowed values:
0: Init: Init phase
1: Header: Header phase
2: Payload: Payload phase
3: Final: Final Phase

Bit 16: Chaining mode selection, bit [2].

Allowed values:
0: CHMOD: Mode as per CHMOD (ECB, CBC, CTR, GCM)
1: CCM: Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB)

Bit 18: Key size selection.

Allowed values:
0: AES128: 128
1: AES256: 256

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bit 0: Computation complete flag.

Allowed values:
0: Complete: Computation complete
1: NotComplete: Computation not complete

Bit 1: Read error flag.

Allowed values:
0: NoError: Read error not detected
1: Error: Read error detected

Bit 2: Write error flag.

Allowed values:
0: NoError: Write error not detected
1: Error: Write error detected

Bit 3: Busy.

Allowed values:
0: Idle: Idle
1: Busy: Busy

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Data Input Register.

Allowed values: 0x0-0xffffffff

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-31: Data output register.

Allowed values: 0x0-0xffffffff

key register 0

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Data Output Register (LSB key [31:0]).

Allowed values: 0x0-0xffffffff

key register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES key register (key [63:32]).

Allowed values: 0x0-0xffffffff

key register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES key register (key [95:64]).

Allowed values: 0x0-0xffffffff

key register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES key register (MSB key [127:96]).

Allowed values: 0x0-0xffffffff

initialization vector register 0

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: initialization vector register (LSB IVR [31:0]).

Allowed values: 0x0-0xffffffff

initialization vector register 1

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Initialization Vector Register (IVR [63:32]).

Allowed values: 0x0-0xffffffff

initialization vector register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Initialization Vector Register (IVR [95:64]).

Allowed values: 0x0-0xffffffff

initialization vector register 3

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

Allowed values: 0x0-0xffffffff

key register 4

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Cryptographic key, bits [159:128].

Allowed values: 0x0-0xffffffff

key register 5

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Cryptographic key, bits [191:160].

Allowed values: 0x0-0xffffffff

key register 6

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Cryptographic key, bits [223:192].

Allowed values: 0x0-0xffffffff

key register 7

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Cryptographic key, bits [255:224].

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

0x40006400: Controller area network

82/266 fields covered.

master control register

Offset: 0x0, size: 32, reset: 0x00010002, access: read-write

0/10 fields covered.

Bit 0: INRQ.

Bit 1: SLEEP.

Bit 2: TXFP.

Bit 3: RFLM.

Bit 4: NART.

Bit 5: AWUM.

Bit 6: ABOM.

Bit 7: TTCM.

Bit 15: RESET.

Bit 16: DBF.

master status register

Offset: 0x4, size: 32, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

Bit 0: INAK.

Bit 1: SLAK.

Bit 2: ERRI.

Bit 3: WKUI.

Bit 4: SLAKI.

Bit 8: TXM.

Bit 9: RXM.

Bit 10: SAMP.

Bit 11: RX.

transmit status register

Offset: 0x8, size: 32, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

Bit 0: RQCP0.

Bit 1: TXOK0.

Bit 2: ALST0.

Bit 3: TERR0.

Bit 7: ABRQ0.

Bit 8: RQCP1.

Bit 9: TXOK1.

Bit 10: ALST1.

Bit 11: TERR1.

Bit 15: ABRQ1.

Bit 16: RQCP2.

Bit 17: TXOK2.

Bit 18: ALST2.

Bit 19: TERR2.

Bit 23: ABRQ2.

Bits 24-25: CODE.

Bit 26: Lowest priority flag for mailbox 0.

Bit 27: Lowest priority flag for mailbox 1.

Bit 28: Lowest priority flag for mailbox 2.

Bit 29: Lowest priority flag for mailbox 0.

Bit 30: Lowest priority flag for mailbox 1.

Bit 31: Lowest priority flag for mailbox 2.

receive FIFO 0 register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

Bits 0-1: FMP0.

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

receive FIFO 1 register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

Bits 0-1: FMP0.

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

interrupt enable register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

Bit 0: TMEIE.

Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set

Bit 1: FMPIE0.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

Bit 2: FFIE0.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

Bit 3: FOVIE0.

Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set

Bit 4: FMPIE1.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

Bit 5: FFIE1.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

Bit 6: FOVIE1.

Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set

Bit 8: EWGIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set

Bit 9: EPVIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set

Bit 10: BOFIE.

Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set

Bit 11: LECIE.

Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection

Bit 15: ERRIE.

Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR

Bit 16: WKUIE.

Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set

Bit 17: SLKIE.

Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set

interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

Bit 0: EWGF.

Bit 1: EPVF.

Bit 2: BOFF.

Bits 4-6: LEC.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

Bits 16-23: TEC.

Bits 24-31: REC.

bit timing register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

2/6 fields covered.

Bits 0-9: BRP.

Bits 16-19: TS1.

Bits 20-22: TS2.

Bits 24-25: SJW.

Bit 30: LBKM.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

Bit 31: SILM.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

TX mailbox identifier register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

Bit 0: TXRQ.

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

Bits 3-20: EXID.

Bits 21-31: STID.

mailbox data length control and time stamp register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

Bits 0-3: DLC.

Allowed values: 0x0-0x8

Bit 8: TGT.

Bits 16-31: TIME.

mailbox data low register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA0.

Bits 8-15: DATA1.

Bits 16-23: DATA2.

Bits 24-31: DATA3.

mailbox data high register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA4.

Bits 8-15: DATA5.

Bits 16-23: DATA6.

Bits 24-31: DATA7.

TX mailbox identifier register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

Bit 0: TXRQ.

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

Bits 3-20: EXID.

Bits 21-31: STID.

mailbox data length control and time stamp register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

Bits 0-3: DLC.

Allowed values: 0x0-0x8

Bit 8: TGT.

Bits 16-31: TIME.

mailbox data low register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA0.

Bits 8-15: DATA1.

Bits 16-23: DATA2.

Bits 24-31: DATA3.

mailbox data high register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA4.

Bits 8-15: DATA5.

Bits 16-23: DATA6.

Bits 24-31: DATA7.

TX mailbox identifier register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

Bit 0: TXRQ.

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

Bits 3-20: EXID.

Bits 21-31: STID.

mailbox data length control and time stamp register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

Bits 0-3: DLC.

Allowed values: 0x0-0x8

Bit 8: TGT.

Bits 16-31: TIME.

mailbox data low register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA0.

Bits 8-15: DATA1.

Bits 16-23: DATA2.

Bits 24-31: DATA3.

mailbox data high register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA4.

Bits 8-15: DATA5.

Bits 16-23: DATA6.

Bits 24-31: DATA7.

receive FIFO mailbox identifier register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

Bits 3-20: EXID.

Bits 21-31: STID.

mailbox data high register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

Bits 0-3: DLC.

Allowed values: 0x0-0x8

Bits 8-15: FMI.

Bits 16-31: TIME.

mailbox data high register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bits 0-7: DATA0.

Bits 8-15: DATA1.

Bits 16-23: DATA2.

Bits 24-31: DATA3.

receive FIFO mailbox data high register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only