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STM32L4x1 Peripheral Coverage

532/536 fields covered.

channel configuration y register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-1: SITP.

Allowed values:
0: SPIRisingEdge: SPI with rising edge to strobe data
1: SPIFallingEdge: SPI with falling edge to strobe data
2: Manchester: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
3: ManchesterInverted: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

Bits 2-3: SPICKSEL.

Allowed values:
0: CKIN: Clock coming from external CKINy input - sampling point according SITP[1:0]
1: CKOUT: Clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: CKOUTSecondFalling: Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
3: CKOUTSecondRising: Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)

Bit 5: SCDEN.

Allowed values:
0: Disabled: Input channel y will not be guarded by the short-circuit detector
1: Enabled: Input channel y will be continuously guarded by the short-circuit detector

Bit 6: CKABEN.

Allowed values:
0: Disabled: Clock absence detector disabled on channel y
1: Enabled: Clock absence detector enabled on channel y

Bit 7: CHEN.

Allowed values:
0: Disabled: Channel y disabled
1: Enabled: Channel y enabled

Bit 8: CHINSEL.

Allowed values:
0: SameChannel: Channel inputs are taken from pins of the same channel y
1: FollowingChannel: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)

Bits 12-13: DATMPX.

Allowed values:
0: External: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
1: ADC: Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register
2: Internal: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting

Bits 14-15: DATPACK.

Allowed values:
0: Standard: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
1: Interleaved: : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)
2: Dual: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)

Bits 16-23: CKOUTDIV.

Allowed values: 0x0-0xff

Bit 30: CKOUTSRC.

Allowed values:
0: SYSCLK: Source for output clock is from system clock
1: AUDCLK: Source for output clock is from audio clock

Bit 31: DFSDMEN.

Allowed values:
0: Disabled: DFSDM interface disabled
1: Enabled: DFSDM interface enabled

channel configuration y register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 3-7: DTRBS.

Allowed values: 0x0-0x1f

Bits 8-31: OFFSET.

Allowed values: 0x0-0xffffff

analog watchdog and short-circuit detector register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-7: SCDT.

Allowed values: 0x0-0xff

Bits 12-15: BKSCD.

Allowed values: 0x0-0xf

Bits 16-20: AWFOSR.

Allowed values: 0x0-0x1f

Bits 22-23: AWFORD.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type

channel watchdog filter data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: WDATA.

Allowed values: 0x0-0xffff

channel data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-15: INDAT0.

Allowed values: 0x0-0xffff

Bits 16-31: INDAT1.

Allowed values: 0x0-0xffff

channel y delay register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-5: PLSSKP.

Allowed values: 0x0-0x3f

channel configuration y register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-1: SITP.

Allowed values:
0: SPIRisingEdge: SPI with rising edge to strobe data
1: SPIFallingEdge: SPI with falling edge to strobe data
2: Manchester: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
3: ManchesterInverted: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

Bits 2-3: SPICKSEL.

Allowed values:
0: CKIN: Clock coming from external CKINy input - sampling point according SITP[1:0]
1: CKOUT: Clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: CKOUTSecondFalling: Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
3: CKOUTSecondRising: Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)

Bit 5: SCDEN.

Allowed values:
0: Disabled: Input channel y will not be guarded by the short-circuit detector
1: Enabled: Input channel y will be continuously guarded by the short-circuit detector

Bit 6: CKABEN.

Allowed values:
0: Disabled: Clock absence detector disabled on channel y
1: Enabled: Clock absence detector enabled on channel y

Bit 7: CHEN.

Allowed values:
0: Disabled: Channel y disabled
1: Enabled: Channel y enabled

Bit 8: CHINSEL.

Allowed values:
0: SameChannel: Channel inputs are taken from pins of the same channel y
1: FollowingChannel: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)

Bits 12-13: DATMPX.

Allowed values:
0: External: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
1: ADC: Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register
2: Internal: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting

Bits 14-15: DATPACK.

Allowed values:
0: Standard: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
1: Interleaved: : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)
2: Dual: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)

Bits 16-23: CKOUTDIV.

Allowed values: 0x0-0xff

Bit 30: CKOUTSRC.

Allowed values:
0: SYSCLK: Source for output clock is from system clock
1: AUDCLK: Source for output clock is from audio clock

Bit 31: DFSDMEN.

Allowed values:
0: Disabled: DFSDM interface disabled
1: Enabled: DFSDM interface enabled

channel configuration y register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 3-7: DTRBS.

Allowed values: 0x0-0x1f

Bits 8-31: OFFSET.

Allowed values: 0x0-0xffffff

analog watchdog and short-circuit detector register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-7: SCDT.

Allowed values: 0x0-0xff

Bits 12-15: BKSCD.

Allowed values: 0x0-0xf

Bits 16-20: AWFOSR.

Allowed values: 0x0-0x1f

Bits 22-23: AWFORD.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type

channel watchdog filter data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: WDATA.

Allowed values: 0x0-0xffff

channel data input register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-15: INDAT0.

Allowed values: 0x0-0xffff

Bits 16-31: INDAT1.

Allowed values: 0x0-0xffff

channel y delay register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-5: PLSSKP.

Allowed values: 0x0-0x3f

channel configuration y register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-1: SITP.

Allowed values:
0: SPIRisingEdge: SPI with rising edge to strobe data
1: SPIFallingEdge: SPI with falling edge to strobe data
2: Manchester: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
3: ManchesterInverted: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

Bits 2-3: SPICKSEL.

Allowed values:
0: CKIN: Clock coming from external CKINy input - sampling point according SITP[1:0]
1: CKOUT: Clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: CKOUTSecondFalling: Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
3: CKOUTSecondRising: Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)

Bit 5: SCDEN.

Allowed values:
0: Disabled: Input channel y will not be guarded by the short-circuit detector
1: Enabled: Input channel y will be continuously guarded by the short-circuit detector

Bit 6: CKABEN.

Allowed values:
0: Disabled: Clock absence detector disabled on channel y
1: Enabled: Clock absence detector enabled on channel y

Bit 7: CHEN.

Allowed values:
0: Disabled: Channel y disabled
1: Enabled: Channel y enabled

Bit 8: CHINSEL.

Allowed values:
0: SameChannel: Channel inputs are taken from pins of the same channel y
1: FollowingChannel: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)

Bits 12-13: DATMPX.

Allowed values:
0: External: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
1: ADC: Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register
2: Internal: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting

Bits 14-15: DATPACK.

Allowed values:
0: Standard: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
1: Interleaved: : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)
2: Dual: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)

Bits 16-23: CKOUTDIV.

Allowed values: 0x0-0xff

Bit 30: CKOUTSRC.

Allowed values:
0: SYSCLK: Source for output clock is from system clock
1: AUDCLK: Source for output clock is from audio clock

Bit 31: DFSDMEN.

Allowed values:
0: Disabled: DFSDM interface disabled
1: Enabled: DFSDM interface enabled

channel configuration y register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 3-7: DTRBS.

Allowed values: 0x0-0x1f

Bits 8-31: OFFSET.

Allowed values: 0x0-0xffffff

analog watchdog and short-circuit detector register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-7: SCDT.

Allowed values: 0x0-0xff

Bits 12-15: BKSCD.

Allowed values: 0x0-0xf

Bits 16-20: AWFOSR.

Allowed values: 0x0-0x1f

Bits 22-23: AWFORD.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type

channel watchdog filter data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: WDATA.

Allowed values: 0x0-0xffff

channel data input register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-15: INDAT0.

Allowed values: 0x0-0xffff

Bits 16-31: INDAT1.

Allowed values: 0x0-0xffff

channel y delay register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-5: PLSSKP.

Allowed values: 0x0-0x3f

channel configuration y register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-1: SITP.

Allowed values:
0: SPIRisingEdge: SPI with rising edge to strobe data
1: SPIFallingEdge: SPI with falling edge to strobe data
2: Manchester: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
3: ManchesterInverted: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

Bits 2-3: SPICKSEL.

Allowed values:
0: CKIN: Clock coming from external CKINy input - sampling point according SITP[1:0]
1: CKOUT: Clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: CKOUTSecondFalling: Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
3: CKOUTSecondRising: Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)

Bit 5: SCDEN.

Allowed values:
0: Disabled: Input channel y will not be guarded by the short-circuit detector
1: Enabled: Input channel y will be continuously guarded by the short-circuit detector

Bit 6: CKABEN.

Allowed values:
0: Disabled: Clock absence detector disabled on channel y
1: Enabled: Clock absence detector enabled on channel y

Bit 7: CHEN.

Allowed values:
0: Disabled: Channel y disabled
1: Enabled: Channel y enabled

Bit 8: CHINSEL.

Allowed values:
0: SameChannel: Channel inputs are taken from pins of the same channel y
1: FollowingChannel: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)

Bits 12-13: DATMPX.

Allowed values:
0: External: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
1: ADC: Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register
2: Internal: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting

Bits 14-15: DATPACK.

Allowed values:
0: Standard: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
1: Interleaved: : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)
2: Dual: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)

Bits 16-23: CKOUTDIV.

Allowed values: 0x0-0xff

Bit 30: CKOUTSRC.

Allowed values:
0: SYSCLK: Source for output clock is from system clock
1: AUDCLK: Source for output clock is from audio clock

Bit 31: DFSDMEN.

Allowed values:
0: Disabled: DFSDM interface disabled
1: Enabled: DFSDM interface enabled

channel configuration y register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 3-7: DTRBS.

Allowed values: 0x0-0x1f

Bits 8-31: OFFSET.

Allowed values: 0x0-0xffffff

analog watchdog and short-circuit detector register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-7: SCDT.

Allowed values: 0x0-0xff

Bits 12-15: BKSCD.

Allowed values: 0x0-0xf

Bits 16-20: AWFOSR.

Allowed values: 0x0-0x1f

Bits 22-23: AWFORD.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type

channel watchdog filter data register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: WDATA.

Allowed values: 0x0-0xffff

channel data input register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-15: INDAT0.

Allowed values: 0x0-0xffff

Bits 16-31: INDAT1.

Allowed values: 0x0-0xffff

channel y delay register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-5: PLSSKP.

Allowed values: 0x0-0x3f

channel configuration y register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-1: SITP.

Allowed values:
0: SPIRisingEdge: SPI with rising edge to strobe data
1: SPIFallingEdge: SPI with falling edge to strobe data
2: Manchester: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
3: ManchesterInverted: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

Bits 2-3: SPICKSEL.

Allowed values:
0: CKIN: Clock coming from external CKINy input - sampling point according SITP[1:0]
1: CKOUT: Clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: CKOUTSecondFalling: Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
3: CKOUTSecondRising: Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)

Bit 5: SCDEN.

Allowed values:
0: Disabled: Input channel y will not be guarded by the short-circuit detector
1: Enabled: Input channel y will be continuously guarded by the short-circuit detector

Bit 6: CKABEN.

Allowed values:
0: Disabled: Clock absence detector disabled on channel y
1: Enabled: Clock absence detector enabled on channel y

Bit 7: CHEN.

Allowed values:
0: Disabled: Channel y disabled
1: Enabled: Channel y enabled

Bit 8: CHINSEL.

Allowed values:
0: SameChannel: Channel inputs are taken from pins of the same channel y
1: FollowingChannel: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)

Bits 12-13: DATMPX.

Allowed values:
0: External: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
1: ADC: Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register
2: Internal: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting

Bits 14-15: DATPACK.

Allowed values:
0: Standard: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
1: Interleaved: : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)
2: Dual: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)

Bits 16-23: CKOUTDIV.

Allowed values: 0x0-0xff

Bit 30: CKOUTSRC.

Allowed values:
0: SYSCLK: Source for output clock is from system clock
1: AUDCLK: Source for output clock is from audio clock

Bit 31: DFSDMEN.

Allowed values:
0: Disabled: DFSDM interface disabled
1: Enabled: DFSDM interface enabled

channel configuration y register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 3-7: DTRBS.

Allowed values: 0x0-0x1f

Bits 8-31: OFFSET.

Allowed values: 0x0-0xffffff

analog watchdog and short-circuit detector register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-7: SCDT.

Allowed values: 0x0-0xff

Bits 12-15: BKSCD.

Allowed values: 0x0-0xf

Bits 16-20: AWFOSR.

Allowed values: 0x0-0x1f

Bits 22-23: AWFORD.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type

channel watchdog filter data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: WDATA.

Allowed values: 0x0-0xffff

channel data input register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-15: INDAT0.

Allowed values: 0x0-0xffff

Bits 16-31: INDAT1.

Allowed values: 0x0-0xffff

channel y delay register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-5: PLSSKP.

Allowed values: 0x0-0x3f

channel configuration y register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-1: SITP.

Allowed values:
0: SPIRisingEdge: SPI with rising edge to strobe data
1: SPIFallingEdge: SPI with falling edge to strobe data
2: Manchester: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
3: ManchesterInverted: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

Bits 2-3: SPICKSEL.

Allowed values:
0: CKIN: Clock coming from external CKINy input - sampling point according SITP[1:0]
1: CKOUT: Clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: CKOUTSecondFalling: Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
3: CKOUTSecondRising: Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)

Bit 5: SCDEN.

Allowed values:
0: Disabled: Input channel y will not be guarded by the short-circuit detector
1: Enabled: Input channel y will be continuously guarded by the short-circuit detector

Bit 6: CKABEN.

Allowed values:
0: Disabled: Clock absence detector disabled on channel y
1: Enabled: Clock absence detector enabled on channel y

Bit 7: CHEN.

Allowed values:
0: Disabled: Channel y disabled
1: Enabled: Channel y enabled

Bit 8: CHINSEL.

Allowed values:
0: SameChannel: Channel inputs are taken from pins of the same channel y
1: FollowingChannel: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)

Bits 12-13: DATMPX.

Allowed values:
0: External: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
1: ADC: Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register
2: Internal: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting

Bits 14-15: DATPACK.

Allowed values:
0: Standard: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
1: Interleaved: : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)
2: Dual: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)

Bits 16-23: CKOUTDIV.

Allowed values: 0x0-0xff

Bit 30: CKOUTSRC.

Allowed values:
0: SYSCLK: Source for output clock is from system clock
1: AUDCLK: Source for output clock is from audio clock

Bit 31: DFSDMEN.

Allowed values:
0: Disabled: DFSDM interface disabled
1: Enabled: DFSDM interface enabled

channel configuration y register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 3-7: DTRBS.

Allowed values: 0x0-0x1f

Bits 8-31: OFFSET.

Allowed values: 0x0-0xffffff

analog watchdog and short-circuit detector register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-7: SCDT.

Allowed values: 0x0-0xff

Bits 12-15: BKSCD.

Allowed values: 0x0-0xf

Bits 16-20: AWFOSR.

Allowed values: 0x0-0x1f

Bits 22-23: AWFORD.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type

channel watchdog filter data register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: WDATA.

Allowed values: 0x0-0xffff

channel data input register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-15: INDAT0.

Allowed values: 0x0-0xffff

Bits 16-31: INDAT1.

Allowed values: 0x0-0xffff

channel y delay register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-5: PLSSKP.

Allowed values: 0x0-0x3f

channel configuration y register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-1: SITP.

Allowed values:
0: SPIRisingEdge: SPI with rising edge to strobe data
1: SPIFallingEdge: SPI with falling edge to strobe data
2: Manchester: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
3: ManchesterInverted: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

Bits 2-3: SPICKSEL.

Allowed values:
0: CKIN: Clock coming from external CKINy input - sampling point according SITP[1:0]
1: CKOUT: Clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: CKOUTSecondFalling: Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
3: CKOUTSecondRising: Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)

Bit 5: SCDEN.

Allowed values:
0: Disabled: Input channel y will not be guarded by the short-circuit detector
1: Enabled: Input channel y will be continuously guarded by the short-circuit detector

Bit 6: CKABEN.

Allowed values:
0: Disabled: Clock absence detector disabled on channel y
1: Enabled: Clock absence detector enabled on channel y

Bit 7: CHEN.

Allowed values:
0: Disabled: Channel y disabled
1: Enabled: Channel y enabled

Bit 8: CHINSEL.

Allowed values:
0: SameChannel: Channel inputs are taken from pins of the same channel y
1: FollowingChannel: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)

Bits 12-13: DATMPX.

Allowed values:
0: External: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
1: ADC: Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register
2: Internal: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting

Bits 14-15: DATPACK.

Allowed values:
0: Standard: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
1: Interleaved: : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)
2: Dual: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)

Bits 16-23: CKOUTDIV.

Allowed values: 0x0-0xff

Bit 30: CKOUTSRC.

Allowed values:
0: SYSCLK: Source for output clock is from system clock
1: AUDCLK: Source for output clock is from audio clock

Bit 31: DFSDMEN.

Allowed values:
0: Disabled: DFSDM interface disabled
1: Enabled: DFSDM interface enabled

channel configuration y register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 3-7: DTRBS.

Allowed values: 0x0-0x1f

Bits 8-31: OFFSET.

Allowed values: 0x0-0xffffff

analog watchdog and short-circuit detector register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-7: SCDT.

Allowed values: 0x0-0xff

Bits 12-15: BKSCD.

Allowed values: 0x0-0xf

Bits 16-20: AWFOSR.

Allowed values: 0x0-0x1f

Bits 22-23: AWFORD.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type

channel watchdog filter data register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: WDATA.

Allowed values: 0x0-0xffff

channel data input register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-15: INDAT0.

Allowed values: 0x0-0xffff

Bits 16-31: INDAT1.

Allowed values: 0x0-0xffff

channel y delay register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-5: PLSSKP.

Allowed values: 0x0-0x3f

channel configuration y register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-1: SITP.

Allowed values:
0: SPIRisingEdge: SPI with rising edge to strobe data
1: SPIFallingEdge: SPI with falling edge to strobe data
2: Manchester: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
3: ManchesterInverted: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

Bits 2-3: SPICKSEL.

Allowed values:
0: CKIN: Clock coming from external CKINy input - sampling point according SITP[1:0]
1: CKOUT: Clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: CKOUTSecondFalling: Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
3: CKOUTSecondRising: Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)

Bit 5: SCDEN.

Allowed values:
0: Disabled: Input channel y will not be guarded by the short-circuit detector
1: Enabled: Input channel y will be continuously guarded by the short-circuit detector

Bit 6: CKABEN.

Allowed values:
0: Disabled: Clock absence detector disabled on channel y
1: Enabled: Clock absence detector enabled on channel y

Bit 7: CHEN.

Allowed values:
0: Disabled: Channel y disabled
1: Enabled: Channel y enabled

Bit 8: CHINSEL.

Allowed values:
0: SameChannel: Channel inputs are taken from pins of the same channel y
1: FollowingChannel: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)

Bits 12-13: DATMPX.

Allowed values:
0: External: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
1: ADC: Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register
2: Internal: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting

Bits 14-15: DATPACK.

Allowed values:
0: Standard: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
1: Interleaved: : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)
2: Dual: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)

Bits 16-23: CKOUTDIV.

Allowed values: 0x0-0xff

Bit 30: CKOUTSRC.

Allowed values:
0: SYSCLK: Source for output clock is from system clock
1: AUDCLK: Source for output clock is from audio clock

Bit 31: DFSDMEN.

Allowed values:
0: Disabled: DFSDM interface disabled
1: Enabled: DFSDM interface enabled

channel configuration y register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 3-7: DTRBS.

Allowed values: 0x0-0x1f

Bits 8-31: OFFSET.

Allowed values: 0x0-0xffffff

analog watchdog and short-circuit detector register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-7: SCDT.

Allowed values: 0x0-0xff

Bits 12-15: BKSCD.

Allowed values: 0x0-0xf

Bits 16-20: AWFOSR.

Allowed values: 0x0-0x1f

Bits 22-23: AWFORD.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type

channel watchdog filter data register

Offset: 0xec, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: WDATA.

Allowed values: 0x0-0xffff

channel data input register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-15: INDAT0.

Allowed values: 0x0-0xffff

Bits 16-31: INDAT1.

Allowed values: 0x0-0xffff

channel y delay register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-5: PLSSKP.

Allowed values: 0x0-0x3f

control register 1

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

13/14 fields covered.

Bit 0: DFSDM enable.

Allowed values:
0: Disabled: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped
1: Enabled: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting

Bit 1: Start a conversion of the injected group of channels.

Allowed values:
1: Start: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

Allowed values:
0: Disabled: Do not launch an injected conversion synchronously with DFSDM_FLT0
1: Enabled: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger

Bit 4: Scanning conversion mode for injected conversions.

Allowed values:
0: Single: One channel conversion is performed from the injected channel group and next the selected channel from this group is selected
1: Series: The series of conversions for the injected group channels is executed, starting over with the lowest selected channel

Bit 5: DMA channel enabled to read data for the injected channel group.

Allowed values:
0: Disabled: The DMA channel is not enabled to read injected data
1: Enabled: The DMA channel is enabled to read injected data

Bits 8-10: Trigger signal selection for launching injected conversions.

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

Allowed values:
0: Disabled: Trigger detection is disabled
1: RisingEdge: Each rising edge on the selected trigger makes a request to launch an injected conversion
2: FallingEdge: Each falling edge on the selected trigger makes a request to launch an injected conversion
3: BothEdges: Both rising edges and falling edges on the selected trigger make requests to launch injected conversions

Bit 17: Software start of a conversion on the regular channel.

Allowed values:
1: Start: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1

Bit 18: Continuous mode selection for regular conversions.

Allowed values:
0: Once: The regular channel is converted just once for each conversion request
1: Continuous: The regular channel is converted repeatedly after each conversion request

Bit 19: Launch regular conversion synchronously with DFSDM0.

Allowed values:
0: NoLaunch: Do not launch a regular conversion synchronously with DFSDM_FLT0
1: Launch: Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0

Bit 21: DMA channel enabled to read data for the regular conversion.

Allowed values:
0: Disabled: The DMA channel is not enabled to read regular data
1: Enabled: The DMA channel is enabled to read regular data

Bits 24-26: Regular channel selection.

Allowed values:
0: Channel0: Channel 0 is selected as regular channel
1: Channel1: Channel 1 is selected as regular channel
2: Channel2: Channel 2 is selected as regular channel
3: Channel3: Channel 3 is selected as regular channel
4: Channel4: Channel 4 is selected as regular channel
5: Channel5: Channel 5 is selected as regular channel
6: Channel6: Channel 6 is selected as regular channel
7: Channel7: Channel 7 is selected as regular channel

Bit 29: Fast conversion mode selection for regular conversions.

Allowed values:
0: Disabled: Fast conversion mode disabled
1: Enabled: Fast conversion mode enabled

Bit 30: Analog watchdog fast mode select.

Allowed values:
0: Output: Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
1: Transceiver: Analog watchdog on channel transceivers value (after watchdog filter)

control register 2

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bit 0: Injected end of conversion interrupt enable.

Allowed values:
0: Disabled: Injected end of conversion interrupt is disabled
1: Enabled: Injected end of conversion interrupt is enabled

Bit 1: Regular end of conversion interrupt enable.

Allowed values:
0: Disabled: Regular end of conversion interrupt is disabled
1: Enabled: Regular end of conversion interrupt is enabled

Bit 2: Injected data overrun interrupt enable.

Allowed values:
0: Disabled: Injected data overrun interrupt is disabled
1: Enabled: Injected data overrun interrupt is enabled

Bit 3: Regular data overrun interrupt enable.

Allowed values:
0: Disabled: Regular data overrun interrupt is disabled
1: Enabled: Regular data overrun interrupt is enabled

Bit 4: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt is disabled
1: Enabled: Analog watchdog interrupt is enabled

Bit 5: Short-circuit detector interrupt enable.

Allowed values:
0: Disabled: Short-circuit detector interrupt is disabled
1: Enabled: Short-circuit detector interrupt is enabled

Bit 6: Clock absence interrupt enable.

Allowed values:
0: Disabled: Detection of channel input clock absence interrupt is disabled
1: Enabled: Detection of channel input clock absence interrupt is enabled

Bits 8-15: Extremes detector channel selection.

Allowed values:
0: Disabled: Extremes detector does not accept data from channel y
1: Enabled: Extremes detector accepts data from channel y

Bits 16-23: Analog watchdog channel selection.

Allowed values:
0: Disabled: Analog watchdog is disabled on channel y
1: Enabled: Analog watchdog is enabled on channel y

interrupt and status register

Offset: 0x108, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

Bit 0: End of injected conversion flag.

Allowed values:
0: Clear: No injected conversion has completed
1: Set: An injected conversion has completed and its data may be read

Bit 1: End of regular conversion flag.

Allowed values:
0: Clear: No regular conversion has completed
1: Set: A regular conversion has completed and its data may be read

Bit 2: Injected conversion overrun flag.

Allowed values:
0: Clear: No injected conversion overrun has occurred
1: Set: An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns

Bit 3: Regular conversion overrun flag.

Allowed values:
0: Clear: No regular conversion overrun has occurred
1: Set: A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns

Bit 4: Analog watchdog.

Allowed values:
0: Clear: No Analog watchdog event occurred
1: Set: The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers

Bit 13: Injected conversion in progress status.

Allowed values:
0: NotInProgress: No request to convert the injected channel group (neither by software nor by trigger) has been issued
1: InProgress: The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection

Bit 14: Regular conversion in progress status.

Allowed values:
0: NotInProgress: No request to convert the regular channel has been issued
1: InProgress: The conversion of the regular channel is in progress or a request for a regular conversion is pending

Bits 16-23: Clock absence flag.

Allowed values:
0: Clear: Clock signal on channel y is present.
1: Set: Clock signal on channel y is not present

Bits 24-31: short-circuit detector flag.

Allowed values:
0: Clear: No short-circuit detector event occurred on channel y
1: Set: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers

interrupt flag clear register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 2: Clear the injected conversion overrun flag.

Allowed values:
1: Clear: Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register

Bit 3: Clear the regular conversion overrun flag.

Allowed values:
1: Clear: Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register

Bits 16-23: Clear the clock absence flag.

Allowed values: 0x0-0xff

Bits 24-31: Clear the short-circuit detector flag.

Allowed values: 0x0-0xff

injected channel group selection register

Offset: 0x110, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

Bits 0-7: Injected channel group selection.

Allowed values: 0x0-0xff

filter control register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-7: Integrator oversampling ratio (averaging length).

Allowed values: 0x0-0xff

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

Allowed values: 0x0-0x3ff

Bits 29-31: Sinc filter order.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type
4: Sinc4: Sinc4 filter type
5: Sinc5: Sinc5 filter type

data register for injected group

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-2: Injected channel most recently converted.

Allowed values: 0x0-0x7

Bits 8-31: Injected group conversion data.

Allowed values: 0x0-0xffffff

data register for the regular channel

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

Bits 0-2: Regular channel most recently converted.

Allowed values: 0x0-0x7

Bit 4: Regular channel pending data.

Bits 8-31: Regular channel conversion data.

Allowed values: 0x0-0xffffff

analog watchdog high threshold register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 1: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 2: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 3: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bits 8-31: Analog watchdog high threshold.

Allowed values: 0x0-0xffffff

analog watchdog low threshold register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 1: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 2: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 3: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bits 8-31: Analog watchdog low threshold.

Allowed values: 0x0-0xffffff

analog watchdog status register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Bit 0: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 1: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 2: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 3: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 4: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 5: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 6: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 7: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 8: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 9: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 10: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 11: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 12: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 13: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 14: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 15: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

analog watchdog clear flag register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Bit 0: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 1: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 2: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 3: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 4: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 5: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 6: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 7: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 8: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 9: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 10: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 11: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 12: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 13: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 14: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 15: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Extremes detector maximum register

Offset: 0x130, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

Bits 0-2: Extremes detector maximum data channel.

Allowed values: 0x0-0x7

Bits 8-31: Extremes detector maximum value.

Allowed values: 0x0-0xffffff

Extremes detector minimum register

Offset: 0x134, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

Bits 0-2: Extremes detector minimum data channel.

Allowed values: 0x0-0x7

Bits 8-31: EXMIN.

Allowed values: 0x0-0xffffff

conversion timer register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

Allowed values: 0x0-0xfffffff

control register 1

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

13/14 fields covered.

Bit 0: DFSDM enable.

Allowed values:
0: Disabled: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped
1: Enabled: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting

Bit 1: Start a conversion of the injected group of channels.

Allowed values:
1: Start: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

Allowed values:
0: Disabled: Do not launch an injected conversion synchronously with DFSDM_FLT0
1: Enabled: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger

Bit 4: Scanning conversion mode for injected conversions.

Allowed values:
0: Single: One channel conversion is performed from the injected channel group and next the selected channel from this group is selected
1: Series: The series of conversions for the injected group channels is executed, starting over with the lowest selected channel

Bit 5: DMA channel enabled to read data for the injected channel group.

Allowed values:
0: Disabled: The DMA channel is not enabled to read injected data
1: Enabled: The DMA channel is enabled to read injected data

Bits 8-10: Trigger signal selection for launching injected conversions.

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

Allowed values:
0: Disabled: Trigger detection is disabled
1: RisingEdge: Each rising edge on the selected trigger makes a request to launch an injected conversion
2: FallingEdge: Each falling edge on the selected trigger makes a request to launch an injected conversion
3: BothEdges: Both rising edges and falling edges on the selected trigger make requests to launch injected conversions

Bit 17: Software start of a conversion on the regular channel.

Allowed values:
1: Start: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1

Bit 18: Continuous mode selection for regular conversions.

Allowed values:
0: Once: The regular channel is converted just once for each conversion request
1: Continuous: The regular channel is converted repeatedly after each conversion request

Bit 19: Launch regular conversion synchronously with DFSDM0.

Allowed values:
0: NoLaunch: Do not launch a regular conversion synchronously with DFSDM_FLT0
1: Launch: Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0

Bit 21: DMA channel enabled to read data for the regular conversion.

Allowed values:
0: Disabled: The DMA channel is not enabled to read regular data
1: Enabled: The DMA channel is enabled to read regular data

Bits 24-26: Regular channel selection.

Allowed values:
0: Channel0: Channel 0 is selected as regular channel
1: Channel1: Channel 1 is selected as regular channel
2: Channel2: Channel 2 is selected as regular channel
3: Channel3: Channel 3 is selected as regular channel
4: Channel4: Channel 4 is selected as regular channel
5: Channel5: Channel 5 is selected as regular channel
6: Channel6: Channel 6 is selected as regular channel
7: Channel7: Channel 7 is selected as regular channel

Bit 29: Fast conversion mode selection for regular conversions.

Allowed values:
0: Disabled: Fast conversion mode disabled
1: Enabled: Fast conversion mode enabled

Bit 30: Analog watchdog fast mode select.

Allowed values:
0: Output: Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
1: Transceiver: Analog watchdog on channel transceivers value (after watchdog filter)

control register 2

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bit 0: Injected end of conversion interrupt enable.

Allowed values:
0: Disabled: Injected end of conversion interrupt is disabled
1: Enabled: Injected end of conversion interrupt is enabled

Bit 1: Regular end of conversion interrupt enable.

Allowed values:
0: Disabled: Regular end of conversion interrupt is disabled
1: Enabled: Regular end of conversion interrupt is enabled

Bit 2: Injected data overrun interrupt enable.

Allowed values:
0: Disabled: Injected data overrun interrupt is disabled
1: Enabled: Injected data overrun interrupt is enabled

Bit 3: Regular data overrun interrupt enable.

Allowed values:
0: Disabled: Regular data overrun interrupt is disabled
1: Enabled: Regular data overrun interrupt is enabled

Bit 4: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt is disabled
1: Enabled: Analog watchdog interrupt is enabled

Bit 5: Short-circuit detector interrupt enable.

Allowed values:
0: Disabled: Short-circuit detector interrupt is disabled
1: Enabled: Short-circuit detector interrupt is enabled

Bit 6: Clock absence interrupt enable.

Allowed values:
0: Disabled: Detection of channel input clock absence interrupt is disabled
1: Enabled: Detection of channel input clock absence interrupt is enabled

Bits 8-15: Extremes detector channel selection.

Allowed values:
0: Disabled: Extremes detector does not accept data from channel y
1: Enabled: Extremes detector accepts data from channel y

Bits 16-23: Analog watchdog channel selection.

Allowed values:
0: Disabled: Analog watchdog is disabled on channel y
1: Enabled: Analog watchdog is enabled on channel y

interrupt and status register

Offset: 0x188, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

Bit 0: End of injected conversion flag.

Allowed values:
0: Clear: No injected conversion has completed
1: Set: An injected conversion has completed and its data may be read

Bit 1: End of regular conversion flag.

Allowed values:
0: Clear: No regular conversion has completed
1: Set: A regular conversion has completed and its data may be read

Bit 2: Injected conversion overrun flag.

Allowed values:
0: Clear: No injected conversion overrun has occurred
1: Set: An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns

Bit 3: Regular conversion overrun flag.

Allowed values:
0: Clear: No regular conversion overrun has occurred
1: Set: A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns

Bit 4: Analog watchdog.

Allowed values:
0: Clear: No Analog watchdog event occurred
1: Set: The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers

Bit 13: Injected conversion in progress status.

Allowed values:
0: NotInProgress: No request to convert the injected channel group (neither by software nor by trigger) has been issued
1: InProgress: The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection

Bit 14: Regular conversion in progress status.

Allowed values:
0: NotInProgress: No request to convert the regular channel has been issued
1: InProgress: The conversion of the regular channel is in progress or a request for a regular conversion is pending

Bits 16-23: Clock absence flag.

Allowed values:
0: Clear: Clock signal on channel y is present.
1: Set: Clock signal on channel y is not present

Bits 24-31: short-circuit detector flag.

Allowed values:
0: Clear: No short-circuit detector event occurred on channel y
1: Set: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers

interrupt flag clear register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 2: Clear the injected conversion overrun flag.

Allowed values:
1: Clear: Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register

Bit 3: Clear the regular conversion overrun flag.

Allowed values:
1: Clear: Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register

Bits 16-23: Clear the clock absence flag.

Allowed values: 0x0-0xff

Bits 24-31: Clear the short-circuit detector flag.

Allowed values: 0x0-0xff

injected channel group selection register

Offset: 0x190, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

Bits 0-7: Injected channel group selection.

Allowed values: 0x0-0xff

filter control register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-7: Integrator oversampling ratio (averaging length).

Allowed values: 0x0-0xff

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

Allowed values: 0x0-0x3ff

Bits 29-31: Sinc filter order.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type
4: Sinc4: Sinc4 filter type
5: Sinc5: Sinc5 filter type

data register for injected group

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-2: Injected channel most recently converted.

Allowed values: 0x0-0x7

Bits 8-31: Injected group conversion data.

Allowed values: 0x0-0xffffff

data register for the regular channel

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

Bits 0-2: Regular channel most recently converted.

Allowed values: 0x0-0x7

Bit 4: Regular channel pending data.

Bits 8-31: Regular channel conversion data.

Allowed values: 0x0-0xffffff

analog watchdog high threshold register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 1: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 2: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 3: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bits 8-31: Analog watchdog high threshold.

Allowed values: 0x0-0xffffff

analog watchdog low threshold register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 1: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 2: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 3: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bits 8-31: Analog watchdog low threshold.

Allowed values: 0x0-0xffffff

analog watchdog status register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Bit 0: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 1: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 2: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 3: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 4: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 5: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 6: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 7: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 8: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 9: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 10: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 11: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 12: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 13: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 14: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 15: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

analog watchdog clear flag register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Bit 0: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 1: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 2: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 3: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 4: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 5: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 6: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 7: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 8: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 9: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 10: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 11: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 12: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 13: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 14: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 15: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Extremes detector maximum register

Offset: 0x1b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

Bits 0-2: Extremes detector maximum data channel.

Allowed values: 0x0-0x7

Bits 8-31: Extremes detector maximum value.

Allowed values: 0x0-0xffffff

Extremes detector minimum register

Offset: 0x1b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

Bits 0-2: Extremes detector minimum data channel.

Allowed values: 0x0-0x7

Bits 8-31: EXMIN.

Allowed values: 0x0-0xffffff

conversion timer register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

Allowed values: 0x0-0xfffffff

control register 1

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

13/14 fields covered.

Bit 0: DFSDM enable.

Allowed values:
0: Disabled: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped
1: Enabled: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting

Bit 1: Start a conversion of the injected group of channels.

Allowed values:
1: Start: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

Allowed values:
0: Disabled: Do not launch an injected conversion synchronously with DFSDM_FLT0
1: Enabled: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger

Bit 4: Scanning conversion mode for injected conversions.

Allowed values:
0: Single: One channel conversion is performed from the injected channel group and next the selected channel from this group is selected
1: Series: The series of conversions for the injected group channels is executed, starting over with the lowest selected channel

Bit 5: DMA channel enabled to read data for the injected channel group.

Allowed values:
0: Disabled: The DMA channel is not enabled to read injected data
1: Enabled: The DMA channel is enabled to read injected data

Bits 8-10: Trigger signal selection for launching injected conversions.

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

Allowed values:
0: Disabled: Trigger detection is disabled
1: RisingEdge: Each rising edge on the selected trigger makes a request to launch an injected conversion
2: FallingEdge: Each falling edge on the selected trigger makes a request to launch an injected conversion
3: BothEdges: Both rising edges and falling edges on the selected trigger make requests to launch injected conversions

Bit 17: Software start of a conversion on the regular channel.

Allowed values:
1: Start: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1

Bit 18: Continuous mode selection for regular conversions.

Allowed values:
0: Once: The regular channel is converted just once for each conversion request
1: Continuous: The regular channel is converted repeatedly after each conversion request

Bit 19: Launch regular conversion synchronously with DFSDM0.

Allowed values:
0: NoLaunch: Do not launch a regular conversion synchronously with DFSDM_FLT0
1: Launch: Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0

Bit 21: DMA channel enabled to read data for the regular conversion.

Allowed values:
0: Disabled: The DMA channel is not enabled to read regular data
1: Enabled: The DMA channel is enabled to read regular data

Bits 24-26: Regular channel selection.

Allowed values:
0: Channel0: Channel 0 is selected as regular channel
1: Channel1: Channel 1 is selected as regular channel
2: Channel2: Channel 2 is selected as regular channel
3: Channel3: Channel 3 is selected as regular channel
4: Channel4: Channel 4 is selected as regular channel
5: Channel5: Channel 5 is selected as regular channel
6: Channel6: Channel 6 is selected as regular channel
7: Channel7: Channel 7 is selected as regular channel

Bit 29: Fast conversion mode selection for regular conversions.

Allowed values:
0: Disabled: Fast conversion mode disabled
1: Enabled: Fast conversion mode enabled

Bit 30: Analog watchdog fast mode select.

Allowed values:
0: Output: Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
1: Transceiver: Analog watchdog on channel transceivers value (after watchdog filter)

control register 2

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bit 0: Injected end of conversion interrupt enable.

Allowed values:
0: Disabled: Injected end of conversion interrupt is disabled
1: Enabled: Injected end of conversion interrupt is enabled

Bit 1: Regular end of conversion interrupt enable.

Allowed values:
0: Disabled: Regular end of conversion interrupt is disabled
1: Enabled: Regular end of conversion interrupt is enabled

Bit 2: Injected data overrun interrupt enable.

Allowed values:
0: Disabled: Injected data overrun interrupt is disabled
1: Enabled: Injected data overrun interrupt is enabled

Bit 3: Regular data overrun interrupt enable.

Allowed values:
0: Disabled: Regular data overrun interrupt is disabled
1: Enabled: Regular data overrun interrupt is enabled

Bit 4: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt is disabled
1: Enabled: Analog watchdog interrupt is enabled

Bit 5: Short-circuit detector interrupt enable.

Allowed values:
0: Disabled: Short-circuit detector interrupt is disabled
1: Enabled: Short-circuit detector interrupt is enabled

Bit 6: Clock absence interrupt enable.

Allowed values:
0: Disabled: Detection of channel input clock absence interrupt is disabled
1: Enabled: Detection of channel input clock absence interrupt is enabled

Bits 8-15: Extremes detector channel selection.

Allowed values:
0: Disabled: Extremes detector does not accept data from channel y
1: Enabled: Extremes detector accepts data from channel y

Bits 16-23: Analog watchdog channel selection.

Allowed values:
0: Disabled: Analog watchdog is disabled on channel y
1: Enabled: Analog watchdog is enabled on channel y

interrupt and status register

Offset: 0x208, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

Bit 0: End of injected conversion flag.

Allowed values:
0: Clear: No injected conversion has completed
1: Set: An injected conversion has completed and its data may be read

Bit 1: End of regular conversion flag.

Allowed values:
0: Clear: No regular conversion has completed
1: Set: A regular conversion has completed and its data may be read

Bit 2: Injected conversion overrun flag.

Allowed values:
0: Clear: No injected conversion overrun has occurred
1: Set: An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns

Bit 3: Regular conversion overrun flag.

Allowed values:
0: Clear: No regular conversion overrun has occurred
1: Set: A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns

Bit 4: Analog watchdog.

Allowed values:
0: Clear: No Analog watchdog event occurred
1: Set: The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers

Bit 13: Injected conversion in progress status.

Allowed values:
0: NotInProgress: No request to convert the injected channel group (neither by software nor by trigger) has been issued
1: InProgress: The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection

Bit 14: Regular conversion in progress status.

Allowed values:
0: NotInProgress: No request to convert the regular channel has been issued
1: InProgress: The conversion of the regular channel is in progress or a request for a regular conversion is pending

Bits 16-23: Clock absence flag.

Allowed values:
0: Clear: Clock signal on channel y is present.
1: Set: Clock signal on channel y is not present

Bits 24-31: short-circuit detector flag.

Allowed values:
0: Clear: No short-circuit detector event occurred on channel y
1: Set: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers

interrupt flag clear register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 2: Clear the injected conversion overrun flag.

Allowed values:
1: Clear: Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register

Bit 3: Clear the regular conversion overrun flag.

Allowed values:
1: Clear: Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register

Bits 16-23: Clear the clock absence flag.

Allowed values: 0x0-0xff

Bits 24-31: Clear the short-circuit detector flag.

Allowed values: 0x0-0xff

injected channel group selection register

Offset: 0x210, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

Bits 0-7: Injected channel group selection.

Allowed values: 0x0-0xff

filter control register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-7: Integrator oversampling ratio (averaging length).

Allowed values: 0x0-0xff

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

Allowed values: 0x0-0x3ff

Bits 29-31: Sinc filter order.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type
4: Sinc4: Sinc4 filter type
5: Sinc5: Sinc5 filter type

data register for injected group

Offset: 0x218, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-2: Injected channel most recently converted.

Allowed values: 0x0-0x7

Bits 8-31: Injected group conversion data.

Allowed values: 0x0-0xffffff

data register for the regular channel

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

Bits 0-2: Regular channel most recently converted.

Allowed values: 0x0-0x7

Bit 4: Regular channel pending data.

Bits 8-31: Regular channel conversion data.

Allowed values: 0x0-0xffffff

analog watchdog high threshold register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 1: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 2: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 3: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bits 8-31: Analog watchdog high threshold.

Allowed values: 0x0-0xffffff

analog watchdog low threshold register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 1: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 2: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 3: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bits 8-31: Analog watchdog low threshold.

Allowed values: 0x0-0xffffff

analog watchdog status register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Bit 0: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 1: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 2: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 3: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 4: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 5: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 6: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 7: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 8: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 9: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 10: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 11: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 12: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 13: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 14: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 15: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

analog watchdog clear flag register

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Bit 0: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 1: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 2: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 3: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 4: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 5: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 6: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 7: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 8: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 9: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 10: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 11: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 12: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 13: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 14: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 15: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Extremes detector maximum register

Offset: 0x230, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

Bits 0-2: Extremes detector maximum data channel.

Allowed values: 0x0-0x7

Bits 8-31: Extremes detector maximum value.

Allowed values: 0x0-0xffffff

Extremes detector minimum register

Offset: 0x234, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

Bits 0-2: Extremes detector minimum data channel.

Allowed values: 0x0-0x7

Bits 8-31: EXMIN.

Allowed values: 0x0-0xffffff

conversion timer register

Offset: 0x238, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

Allowed values: 0x0-0xfffffff

control register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

13/14 fields covered.

Bit 0: DFSDM enable.

Allowed values:
0: Disabled: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped
1: Enabled: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting

Bit 1: Start a conversion of the injected group of channels.

Allowed values:
1: Start: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

Allowed values:
0: Disabled: Do not launch an injected conversion synchronously with DFSDM_FLT0
1: Enabled: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger

Bit 4: Scanning conversion mode for injected conversions.

Allowed values:
0: Single: One channel conversion is performed from the injected channel group and next the selected channel from this group is selected
1: Series: The series of conversions for the injected group channels is executed, starting over with the lowest selected channel

Bit 5: DMA channel enabled to read data for the injected channel group.

Allowed values:
0: Disabled: The DMA channel is not enabled to read injected data
1: Enabled: The DMA channel is enabled to read injected data

Bits 8-10: Trigger signal selection for launching injected conversions.

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

Allowed values:
0: Disabled: Trigger detection is disabled
1: RisingEdge: Each rising edge on the selected trigger makes a request to launch an injected conversion
2: FallingEdge: Each falling edge on the selected trigger makes a request to launch an injected conversion
3: BothEdges: Both rising edges and falling edges on the selected trigger make requests to launch injected conversions

Bit 17: Software start of a conversion on the regular channel.

Allowed values:
1: Start: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1

Bit 18: Continuous mode selection for regular conversions.

Allowed values:
0: Once: The regular channel is converted just once for each conversion request
1: Continuous: The regular channel is converted repeatedly after each conversion request

Bit 19: Launch regular conversion synchronously with DFSDM0.

Allowed values:
0: NoLaunch: Do not launch a regular conversion synchronously with DFSDM_FLT0
1: Launch: Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0

Bit 21: DMA channel enabled to read data for the regular conversion.

Allowed values:
0: Disabled: The DMA channel is not enabled to read regular data
1: Enabled: The DMA channel is enabled to read regular data

Bits 24-26: Regular channel selection.

Allowed values:
0: Channel0: Channel 0 is selected as regular channel
1: Channel1: Channel 1 is selected as regular channel
2: Channel2: Channel 2 is selected as regular channel
3: Channel3: Channel 3 is selected as regular channel
4: Channel4: Channel 4 is selected as regular channel
5: Channel5: Channel 5 is selected as regular channel
6: Channel6: Channel 6 is selected as regular channel
7: Channel7: Channel 7 is selected as regular channel

Bit 29: Fast conversion mode selection for regular conversions.

Allowed values:
0: Disabled: Fast conversion mode disabled
1: Enabled: Fast conversion mode enabled

Bit 30: Analog watchdog fast mode select.

Allowed values:
0: Output: Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
1: Transceiver: Analog watchdog on channel transceivers value (after watchdog filter)

control register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bit 0: Injected end of conversion interrupt enable.

Allowed values:
0: Disabled: Injected end of conversion interrupt is disabled
1: Enabled: Injected end of conversion interrupt is enabled

Bit 1: Regular end of conversion interrupt enable.

Allowed values:
0: Disabled: Regular end of conversion interrupt is disabled
1: Enabled: Regular end of conversion interrupt is enabled

Bit 2: Injected data overrun interrupt enable.

Allowed values:
0: Disabled: Injected data overrun interrupt is disabled
1: Enabled: Injected data overrun interrupt is enabled

Bit 3: Regular data overrun interrupt enable.

Allowed values:
0: Disabled: Regular data overrun interrupt is disabled
1: Enabled: Regular data overrun interrupt is enabled

Bit 4: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt is disabled
1: Enabled: Analog watchdog interrupt is enabled

Bit 5: Short-circuit detector interrupt enable.

Allowed values:
0: Disabled: Short-circuit detector interrupt is disabled
1: Enabled: Short-circuit detector interrupt is enabled

Bit 6: Clock absence interrupt enable.

Allowed values:
0: Disabled: Detection of channel input clock absence interrupt is disabled
1: Enabled: Detection of channel input clock absence interrupt is enabled

Bits 8-15: Extremes detector channel selection.

Allowed values:
0: Disabled: Extremes detector does not accept data from channel y
1: Enabled: Extremes detector accepts data from channel y

Bits 16-23: Analog watchdog channel selection.

Allowed values:
0: Disabled: Analog watchdog is disabled on channel y
1: Enabled: Analog watchdog is enabled on channel y

interrupt and status register

Offset: 0x288, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

Bit 0: End of injected conversion flag.

Allowed values:
0: Clear: No injected conversion has completed
1: Set: An injected conversion has completed and its data may be read

Bit 1: End of regular conversion flag.

Allowed values:
0: Clear: No regular conversion has completed
1: Set: A regular conversion has completed and its data may be read

Bit 2: Injected conversion overrun flag.

Allowed values:
0: Clear: No injected conversion overrun has occurred
1: Set: An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns

Bit 3: Regular conversion overrun flag.

Allowed values:
0: Clear: No regular conversion overrun has occurred
1: Set: A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns

Bit 4: Analog watchdog.

Allowed values:
0: Clear: No Analog watchdog event occurred
1: Set: The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers

Bit 13: Injected conversion in progress status.

Allowed values:
0: NotInProgress: No request to convert the injected channel group (neither by software nor by trigger) has been issued
1: InProgress: The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection

Bit 14: Regular conversion in progress status.

Allowed values:
0: NotInProgress: No request to convert the regular channel has been issued
1: InProgress: The conversion of the regular channel is in progress or a request for a regular conversion is pending

Bits 16-23: Clock absence flag.

Allowed values:
0: Clear: Clock signal on channel y is present.
1: Set: Clock signal on channel y is not present

Bits 24-31: short-circuit detector flag.

Allowed values:
0: Clear: No short-circuit detector event occurred on channel y
1: Set: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers

interrupt flag clear register

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 2: Clear the injected conversion overrun flag.

Allowed values:
1: Clear: Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register

Bit 3: Clear the regular conversion overrun flag.

Allowed values:
1: Clear: Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register

Bits 16-23: Clear the clock absence flag.

Allowed values: 0x0-0xff

Bits 24-31: Clear the short-circuit detector flag.

Allowed values: 0x0-0xff

injected channel group selection register

Offset: 0x290, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

Bits 0-7: Injected channel group selection.

Allowed values: 0x0-0xff

filter control register

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-7: Integrator oversampling ratio (averaging length).

Allowed values: 0x0-0xff

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

Allowed values: 0x0-0x3ff

Bits 29-31: Sinc filter order.

Allowed values:
0: FastSinc: FastSinc filter type
1: Sinc1: Sinc1 filter type
2: Sinc2: Sinc2 filter type
3: Sinc3: Sinc3 filter type
4: Sinc4: Sinc4 filter type
5: Sinc5: Sinc5 filter type

data register for injected group

Offset: 0x298, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-2: Injected channel most recently converted.

Allowed values: 0x0-0x7

Bits 8-31: Injected group conversion data.

Allowed values: 0x0-0xffffff

data register for the regular channel

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

Bits 0-2: Regular channel most recently converted.

Allowed values: 0x0-0x7

Bit 4: Regular channel pending data.

Bits 8-31: Regular channel conversion data.

Allowed values: 0x0-0xffffff

analog watchdog high threshold register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 1: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 2: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bit 3: Break signal assignment to analog watchdog high threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog high threshold event
1: Assigned: Break i signal is assigned to an analog watchdog high threshold event

Bits 8-31: Analog watchdog high threshold.

Allowed values: 0x0-0xffffff

analog watchdog low threshold register

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 1: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 2: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bit 3: Break signal assignment to analog watchdog low threshold event.

Allowed values:
0: NotAssigned: Break i signal is not assigned to an analog watchdog low threshold event
1: Assigned: Break i signal is assigned to an analog watchdog low threshold event

Bits 8-31: Analog watchdog low threshold.

Allowed values: 0x0-0xffffff

analog watchdog status register

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Bit 0: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 1: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 2: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 3: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 4: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 5: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 6: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 7: Analog watchdog low threshold flag.

Allowed values:
0: NoError: No low threshold error
1: Error: A low threshold error on channel y

Bit 8: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 9: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 10: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 11: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 12: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 13: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 14: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

Bit 15: Analog watchdog high threshold flag.

Allowed values:
0: NoError: No high threshold error
1: Error: A high threshold error on channel y

analog watchdog clear flag register

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Bit 0: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 1: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 2: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 3: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 4: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 5: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 6: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 7: Clear the analog watchdog low threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWLTF[y] bit

Bit 8: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 9: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 10: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 11: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 12: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 13: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 14: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Bit 15: Clear the analog watchdog high threshold flag.

Allowed values:
1: Clear: Clear the corresponding AWHTF[y] bit

Extremes detector maximum register

Offset: 0x2b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

Bits 0-2: Extremes detector maximum data channel.

Allowed values: 0x0-0x7

Bits 8-31: Extremes detector maximum value.

Allowed values: 0x0-0xffffff

Extremes detector minimum register

Offset: 0x2b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

Bits 0-2: Extremes detector minimum data channel.

Allowed values: 0x0-0x7

Bits 8-31: EXMIN.

Allowed values: 0x0-0xffffff

conversion timer register

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

Allowed values: 0x0-0xfffffff

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