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STM32H730 Peripheral Coverage

208/912 fields covered.

MDMA Global Interrupt/Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Bit 0: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 1: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 2: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 3: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 4: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 5: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 6: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 7: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 8: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 9: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 10: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 11: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 12: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 13: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 14: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

Bit 15: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

MDMA channel x interrupt/status register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x44, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x84, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x8c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0xcc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x104, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x10c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x14c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x184, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x18c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x1cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x1d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x1dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x1f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x204, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x20c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x230, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x234, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x240, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x244, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x248, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x24c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x258, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x280, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x284, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x288, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x28c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x2c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x2cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x304, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x30c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x340, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x344, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x348, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x34c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x354, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x358, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x35c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x360, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x364, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x368, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x374, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x380, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x384, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x388, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x38c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x390, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x394, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x398, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x39c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x3a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x3a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x3a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x3b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x3b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x3c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x3c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x3c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x3cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x3d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x3d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x3f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

MDMA channel x interrupt/status register

Offset: 0x400, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

Bit 4: channel x buffer transfer complete.

Bit 16: channel x request active flag.

MDMA channel x interrupt flag clear register

Offset: 0x404, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

MDMA Channel x error status register

Offset: 0x408, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

This register is used to control the concerned channel.

Offset: 0x40c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

Bit 0: channel enable.

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

Bit 12: byte Endianness exchange.

Bit 13: Half word Endianes exchange.

Bit 14: Word Endianness exchange.

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

This register is used to configure the concerned channel.

Offset: 0x410, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

Bits 8-9: source increment offset size.

Bits 10-11: Destination increment offset.

Bits 12-14: source burst transfer configuration.

Bits 15-17: Destination burst transfer configuration.

Bits 18-24: buffer transfer lengh.

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

MDMA Channel x block number of data register

Offset: 0x414, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-16: block number of data to transfer.

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

MDMA channel x source address register

Offset: 0x418, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: source adr base.

MDMA channel x destination address register

Offset: 0x41c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Destination adr base.

MDMA channel x Block Repeat address Update register

Offset: 0x420, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

Bits 0-15: source adresse update value.

Bits 16-31: destination address update.

MDMA channel x Link Address register

Offset: 0x424, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Link address register.

MDMA channel x Trigger and Bus selection Register

Offset: 0x428, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-5: Trigger selection.

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MDMA channel x Mask address register

Offset: 0x430, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask address.

MDMA channel x Mask Data register

Offset: 0x434, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Mask data.

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