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Showing content from https://stm32-rs.github.io/stm32-rs/STM32G474.html below:

STM32G474 Peripheral Coverage

493/551 fields covered.

Toggle registers CR1

Control Register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Toggle fields MUDIS

Bit 0: Master Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[A]UDIS

Bit 1: Timer A Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[B]UDIS

Bit 2: Timer B Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[C]UDIS

Bit 3: Timer C Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[D]UDIS

Bit 4: Timer D Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[E]UDIS

Bit 5: Timer E Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[F]UDIS

Bit 6: Timer F Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

AD[1]USRC

Bits 16-18: ADC Trigger 1 Update Source.

Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E
6: TimerF: ADC trigger update from timer F

AD[2]USRC

Bits 19-21: ADC Trigger 2 Update Source.

AD[3]USRC

Bits 22-24: ADC Trigger 3 Update Source.

AD[4]USRC

Bits 25-27: ADC Trigger 4 Update Source.

CR2

Control Register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

14/20 fields covered.

Toggle fields MSWU

Bit 0: Master Timer Software update.

Allowed values:
1: Update: Force immediate update

T[A]SWU

Bit 1: Timer A Software Update.

Allowed values:
1: Update: Force immediate update

T[B]SWU

Bit 2: Timer B Software Update.

Allowed values:
1: Update: Force immediate update

T[C]SWU

Bit 3: Timer C Software Update.

Allowed values:
1: Update: Force immediate update

T[D]SWU

Bit 4: Timer D Software Update.

Allowed values:
1: Update: Force immediate update

T[E]SWU

Bit 5: Timer E Software Update.

Allowed values:
1: Update: Force immediate update

T[F]SWU

Bit 6: Timer F Software Update.

Allowed values:
1: Update: Force immediate update

MRST

Bit 8: Master Counter software reset.

Allowed values:
1: Reset: Reset timer

T[A]RST

Bit 9: Timer A counter software reset.

Allowed values:
1: Reset: Reset timer

T[B]RST

Bit 10: Timer B counter software reset.

Allowed values:
1: Reset: Reset timer

T[C]RST

Bit 11: Timer C counter software reset.

Allowed values:
1: Reset: Reset timer

T[D]RST

Bit 12: Timer D counter software reset.

Allowed values:
1: Reset: Reset timer

T[E]RST

Bit 13: Timer E counter software reset.

Allowed values:
1: Reset: Reset timer

T[F]RST

Bit 14: Timer F counter software reset.

Allowed values:
1: Reset: Reset timer

SWP[A]

Bit 16: Swap Timer A outputs.

SWP[B]

Bit 17: Swap Timer B outputs.

SWP[C]

Bit 18: Swap Timer C outputs.

SWP[D]

Bit 19: Swap Timer D outputs.

SWP[E]

Bit 20: Swap Timer E outputs.

SWP[F]

Bit 21: Swap Timer F outputs.

ISR

Interrupt Status Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

Toggle fields FLT1

Bit 0: Fault 1 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT2

Bit 1: Fault 2 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT3

Bit 2: Fault 3 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT4

Bit 3: Fault 4 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT5

Bit 4: Fault 5 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

SYSFLT

Bit 5: System Fault Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT6

Bit 6: Fault 6 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

DLLRDY

Bit 16: DLL Ready Interrupt Flag.

Allowed values:
0: NoEvent: No DLL calibration ready interrupt occurred
1: Event: DLL calibration ready interrupt occurred

BMPER

Bit 17: Burst mode Period Interrupt Flag.

Allowed values:
0: NoEvent: No burst mode period interrupt occurred
1: Event: Burst mode period interrupt occured

ICR

Interrupt Clear Register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

Toggle fields FLT1C

Bit 0: Fault 1 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT2C

Bit 1: Fault 2 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT3C

Bit 2: Fault 3 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT4C

Bit 3: Fault 4 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT5C

Bit 4: Fault 5 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SYSFLTC

Bit 5: System Fault Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT6C

Bit 6: Fault 6 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLLRDYC

Bit 16: DLL Ready Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

BMPERC

Bit 17: Burst mode period flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Toggle fields FLT1IE

Bit 0: Fault 1 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT2IE

Bit 1: Fault 2 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT3IE

Bit 2: Fault 3 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT4IE

Bit 3: Fault 4 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT5IE

Bit 4: Fault 5 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

SYSFLTIE

Bit 5: System Fault Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT6IE

Bit 6: Fault 6 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

DLLRDYIE

Bit 16: DLL Ready Interrupt Enable.

Allowed values:
0: Disabled: DLL ready interrupt disabled
1: Enabled: DLL Ready interrupt enabled

BMPERIE

Bit 17: Burst mode period Interrupt Enable.

Allowed values:
0: Disabled: Burst mode period interrupt disabled
1: Enabled: Burst mode period interrupt enabled

OENR

Output Enable Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Toggle fields T[A]1OEN

Bit 0: Timer A Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[A]2OEN

Bit 1: Timer A Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[B]1OEN

Bit 2: Timer B Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[B]2OEN

Bit 3: Timer B Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[C]1OEN

Bit 4: Timer C Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[C]2OEN

Bit 5: Timer C Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[D]1OEN

Bit 6: Timer D Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[D]2OEN

Bit 7: Timer D Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[E]1OEN

Bit 8: Timer E Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[E]2OEN

Bit 9: Timer E Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[F]1OEN

Bit 10: Timer F Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[F]2OEN

Bit 11: Timer F Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

ODISR

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

12/12 fields covered.

Toggle fields T[A]1ODIS

Bit 0: TA1ODIS.

Allowed values:
1: Disable: Disable output

T[A]2ODIS

Bit 1: TA2ODIS.

Allowed values:
1: Disable: Disable output

T[B]1ODIS

Bit 2: TB1ODIS.

Allowed values:
1: Disable: Disable output

T[B]2ODIS

Bit 3: TB2ODIS.

Allowed values:
1: Disable: Disable output

T[C]1ODIS

Bit 4: TC1ODIS.

Allowed values:
1: Disable: Disable output

T[C]2ODIS

Bit 5: TC2ODIS.

Allowed values:
1: Disable: Disable output

T[D]1ODIS

Bit 6: TD1ODIS.

Allowed values:
1: Disable: Disable output

T[D]2ODIS

Bit 7: TD2ODIS.

Allowed values:
1: Disable: Disable output

T[E]1ODIS

Bit 8: TE1ODIS.

Allowed values:
1: Disable: Disable output

T[E]2ODIS

Bit 9: TE2ODIS.

Allowed values:
1: Disable: Disable output

T[F]1ODIS

Bit 10: TF1ODIS.

Allowed values:
1: Disable: Disable output

T[F]2ODIS

Bit 11: TF2ODIS.

Allowed values:
1: Disable: Disable output

ODSR

Output Disable Status Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

Toggle fields T[A]1ODS

Bit 0: Timer A Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[A]2ODS

Bit 1: Timer A Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[B]1ODS

Bit 2: Timer B Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[B]2ODS

Bit 3: Timer B Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[C]1ODS

Bit 4: Timer C Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[C]2ODS

Bit 5: Timer C Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[D]1ODS

Bit 6: Timer D Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[D]2ODS

Bit 7: Timer D Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[E]1ODS

Bit 8: Timer E Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[E]2ODS

Bit 9: Timer E Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[F]1ODS

Bit 10: Timer F Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[F]2ODS

Bit 11: Timer F Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

BMCR

Burst Mode Control Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

Toggle fields BME

Bit 0: Burst Mode enable.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

BMOM

Bit 1: Burst Mode operating mode.

Allowed values:
0: SingleShot: Single-shot mode
1: Continuous: Continuous operation

BMCLK

Bits 2-5: Burst Mode Clock source.

Allowed values:
0: Master: Master timer reset/roll-over
1: TimerA: Timer A counter reset/roll-over
2: TimerB: Timer B counter reset/roll-over
3: TimerC: Timer C counter reset/roll-over
4: TimerD: Timer D counter reset/roll-over
5: TimerE: Timer E counter reset/roll-over
6: Event1: On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock
7: Event2: On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock
8: Event3: On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock
9: Event4: On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock
10: Clock: Prescaled f_HRTIM clock (as per BMPRSC[3:0] setting

BMPRSC

Bits 6-9: Burst Mode Prescaler.

Allowed values:
0: Div1: Clock not divided
1: Div2: Division by 2
2: Div4: Division by 4
3: Div8: Division by 8
4: Div16: Division by 16
5: Div32: Division by 32
6: Div64: Division by 64
7: Div128: Division by 128
8: Div256: Division by 256
9: Div512: Division by 512
10: Div1024: Division by 1024
11: Div2048: Division by 2048
12: Div4096: Division by 4096
13: Div8192: Division by 8192
14: Div16384: Division by 16384
15: Div32768: Division by 32768

BMPREN

Bit 10: Burst Mode Preload Enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into active registers
1: Enabled: Preload enabled: the write access is done into preload registers

MTBM

Bit 16: Master Timer Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[A]BM

Bit 17: Timer A Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[B]BM

Bit 18: Timer B Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[C]BM

Bit 19: Timer C Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[D]BM

Bit 20: Timer D Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[E]BM

Bit 21: Timer E Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[F]BM

Bit 22: Timer F Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

BMSTAT

Bit 31: Burst Mode Status.

Allowed values:
0: Normal: Normal operation
1: Burst: Burst operation ongoing

BMTRGR

BMTRG

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields SW

Bit 0: SW.

Allowed values:
0: NoEffect: No effect
1: Trigger: Trigger immediate burst mode operation

MSTRST

Bit 1: MSTRST.

Allowed values:
0: NoEffect: Master timer reset/roll-over event has no effect
1: Trigger: Master timer reset/roll-over event triggers a burst mode entry

MSTREP

Bit 2: MSTREP.

Allowed values:
0: NoEffect: Master timer repetition event has no effect
1: Trigger: Master timer repetition event triggers a burst mode entry

MSTCMP1

Bit 3: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

MSTCMP2

Bit 4: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

MSTCMP3

Bit 5: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

MSTCMP4

Bit 6: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

TARST

Bit 7: TARST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TAREP

Bit 8: TAREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TACMP1

Bit 9: TACMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TACMP2

Bit 10: TACMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TBRST

Bit 11: TBRST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TBREP

Bit 12: TBREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TBCMP1

Bit 13: TBCMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TBCMP2

Bit 14: TBCMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TCRST

Bit 15: TCRST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TCREP

Bit 16: TCREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TCCMP1

Bit 17: TCCMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TFRST

Bit 18: Timer F reset.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TDRST

Bit 19: TDRST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TDREP

Bit 20: TDREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TFREP

Bit 21: Timer F repetition.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TDCMP2

Bit 22: TDCMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TFCMP1

Bit 23: Timer F compare 1 event.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TEREP

Bit 24: TEREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TECMP1

Bit 25: TECMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TECMP2

Bit 26: TECMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TAEEV7

Bit 27: Timer A period following external event 7.

Allowed values:
0: NoEffect: Timer X period following external event Y has no effect
1: Trigger: Timer X period following external event Y triggers a burst mode entry

TDEEV8

Bit 28: TDEEV8.

Allowed values:
0: NoEffect: Timer X period following external event Y has no effect
1: Trigger: Timer X period following external event Y triggers a burst mode entry

EEV7

Bit 29: EEV7.

Allowed values:
0: NoEffect: External event X has no effect
1: Trigger: External event X triggers a burst mode entry

EEV8

Bit 30: EEV8.

Allowed values:
0: NoEffect: External event X has no effect
1: Trigger: External event X triggers a burst mode entry

OCHPEV

Bit 31: OCHPEV.

Allowed values:
0: NoEffect: Rising edge on an on-chip event has no effect
1: Trigger: Rising edge on an on-chip event triggers a burst mode entry

BMCMPR

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BMCMP
rw Toggle fields BMCMP

Bits 0-15: BMCMP.

Allowed values: 0x0-0xffff

BMPER

Burst Mode Period Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BMPER
rw Toggle fields BMPER

Bits 0-15: Burst mode Period.

Allowed values: 0x0-0xffff

EECR1

Timer External Event Control Register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

Toggle fields EE[1]SRC

Bits 0-1: External Event 1 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[1]POL

Bit 2: External Event 1 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[1]SNS

Bits 3-4: External Event 1 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[1]FAST

Bit 5: External Event 1 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EE[2]SRC

Bits 6-7: External Event 2 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[2]POL

Bit 8: External Event 2 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[2]SNS

Bits 9-10: External Event 2 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[2]FAST

Bit 11: External Event 2 Fast mode.

EE[3]SRC

Bits 12-13: External Event 3 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[3]POL

Bit 14: External Event 3 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[3]SNS

Bits 15-16: External Event 3 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[3]FAST

Bit 17: External Event 3 Fast mode.

EE[4]SRC

Bits 18-19: External Event 4 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[4]POL

Bit 20: External Event 4 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[4]SNS

Bits 21-22: External Event 4 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[4]FAST

Bit 23: External Event 4 Fast mode.

EE[5]SRC

Bits 24-25: External Event 5 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[5]POL

Bit 26: External Event 5 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[5]SNS

Bits 27-28: External Event 5 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[5]FAST

Bit 29: External Event 5 Fast mode.

EECR2

Timer External Event Control Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

Toggle fields EE[6]SRC

Bits 0-1: EE6SRC.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[6]POL

Bit 2: EE6POL.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[6]SNS

Bits 3-4: EE6SNS.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[7]SRC

Bits 6-7: EE7SRC.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[7]POL

Bit 8: EE7POL.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[7]SNS

Bits 9-10: EE7SNS.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[8]SRC

Bits 12-13: EE8SRC.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[8]POL

Bit 14: EE8POL.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[8]SNS

Bits 15-16: EE8SNS.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[9]SRC

Bits 18-19: EE9SRC.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[9]POL

Bit 20: EE9POL.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[9]SNS

Bits 21-22: EE9SNS.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[10]SRC

Bits 24-25: EE10SRC.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[10]POL

Bit 26: EE10POL.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[10]SNS

Bits 27-28: EE10SNS.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EECR3

Timer External Event Control Register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Toggle fields EE[6]F

Bits 0-3: EE6F.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_EEVS/2, N=6
5: Div2_N8: f_SAMPLING=f_EEVS/2, N=8
6: Div4_N6: f_SAMPLING=f_EEVS/4, N=6
7: Div4_N8: f_SAMPLING=f_EEVS/4, N=8
8: Div8_N6: f_SAMPLING=f_EEVS/8, N=6
9: Div8_N8: f_SAMPLING=f_EEVS/8, N=8
10: Div16_N5: f_SAMPLING=f_EEVS/16, N=5
11: Div16_N6: f_SAMPLING=f_EEVS/16, N=6
12: Div16_N8: f_SAMPLING=f_EEVS/16, N=8
13: Div32_N5: f_SAMPLING=f_EEVS/32, N=5
14: Div32_N6: f_SAMPLING=f_EEVS/32, N=6
15: Div32_N8: f_SAMPLING=f_EEVS/32, N=8

EE[7]F

Bits 6-9: EE7F.

EE[8]F

Bits 12-15: EE8F.

EE[9]F

Bits 18-21: EE9F.

EE[10]F

Bits 24-27: EE10F.

EEVSD

Bits 30-31: EEVSD.

Allowed values:
0: Div1: f_EEVS=f_HRTIM
1: Div2: f_EEVS=f_HRTIM/2
2: Div4: f_EEVS=f_HRTIM/4
3: Div8: f_EEVS=f_HRTIM/8

ADC1R

ADC Trigger 1 Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields MC[1]

Bit 0: ADC trigger 1 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 1 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 1 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 1 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 1 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[1]

Bit 5: ADC trigger 1 on External Event 1.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[2]

Bit 6: ADC trigger 1 on External Event 2.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[3]

Bit 7: ADC trigger 1 on External Event 3.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[4]

Bit 8: ADC trigger 1 on External Event 4.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[5]

Bit 9: ADC trigger 1 on External Event 5.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

FC2

Bit 10: Bit 10 - ADC trigger 1 on timer F compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC3

Bit 11: ADC trigger 1 on Timer A compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 1 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 1 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ARST

Bit 14: ADC trigger 1 on Timer A Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

FC3

Bit 15: Bit 15 - ADC trigger 1 on timer F compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC3

Bit 16: ADC trigger 1 on Timer B compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 17: ADC trigger 1 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 18: ADC trigger 1 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BRST

Bit 19: ADC trigger 1 on Timer B Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

FC4

Bit 20: Bit 20 - ADC trigger 1 on timer F compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC3

Bit 21: ADC trigger 1 on Timer C compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 22: ADC trigger 1 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 23: ADC trigger 1 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

FPER

Bit 24: Bit 24 - ADC trigger 1 on timer F period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DC3

Bit 25: ADC trigger 1 on Timer D compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC4

Bit 26: ADC trigger 1 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 27: ADC trigger 1 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

FRST

Bit 28: Bit 28 - ADC trigger 1 on timer F reset and counter roll-over.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

EC3

Bit 29: ADC trigger 1 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 1 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EPER

Bit 31: ADC trigger 1 on Timer E Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ADC2R

ADC Trigger 2 Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields MC[1]

Bit 0: ADC trigger 2 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 2 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 2 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 2 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 2 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[6]

Bit 5: ADC trigger 2 on External Event 6.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[7]

Bit 6: ADC trigger 2 on External Event 7.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[8]

Bit 7: ADC trigger 2 on External Event 8.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[9]

Bit 8: ADC trigger 2 on External Event 9.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[10]

Bit 9: ADC trigger 2 on External Event 10.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

AC2

Bit 10: ADC trigger 2 on Timer A compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

FC2

Bit 11: Bit 11 - ADC trigger 3 on timer F compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 2 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 2 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BC2

Bit 14: ADC trigger 2 on Timer B compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

FC3

Bit 15: Bit 15 - ADC trigger 2 on timer F compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 16: ADC trigger 2 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 17: ADC trigger 2 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CC2

Bit 18: ADC trigger 2 on Timer C compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

FC4

Bit 19: Bit 19 - ADC trigger 2 on timer F compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 20: ADC trigger 2 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 21: ADC trigger 2 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CRST

Bit 22: ADC trigger 2 on Timer C Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

DC2

Bit 23: ADC trigger 2 on Timer D compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

FPER

Bit 24: Bit 24 - ADC trigger 2 on timer F period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DC4

Bit 25: ADC trigger 2 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 26: ADC trigger 2 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DRST

Bit 27: ADC trigger 2 on Timer D Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

EC2

Bit 28: ADC trigger 2 on Timer E compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC3

Bit 29: ADC trigger 2 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 2 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

ERST

Bit 31: ADC trigger 2 on Timer E Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

ADC3R

ADC Trigger 3 Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields MC[1]

Bit 0: ADC trigger 1 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 1 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 1 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 1 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 1 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[1]

Bit 5: ADC trigger 1 on External Event 1.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[2]

Bit 6: ADC trigger 1 on External Event 2.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[3]

Bit 7: ADC trigger 1 on External Event 3.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[4]

Bit 8: ADC trigger 1 on External Event 4.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[5]

Bit 9: ADC trigger 1 on External Event 5.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

FC2

Bit 10: Bit 10 - ADC trigger 1 on timer F compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC3

Bit 11: ADC trigger 1 on Timer A compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 1 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 1 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ARST

Bit 14: ADC trigger 1 on Timer A Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

FC3

Bit 15: Bit 15 - ADC trigger 1 on timer F compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC3

Bit 16: ADC trigger 1 on Timer B compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 17: ADC trigger 1 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 18: ADC trigger 1 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BRST

Bit 19: ADC trigger 1 on Timer B Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

FC4

Bit 20: Bit 20 - ADC trigger 1 on timer F compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC3

Bit 21: ADC trigger 1 on Timer C compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 22: ADC trigger 1 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 23: ADC trigger 1 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

FPER

Bit 24: Bit 24 - ADC trigger 1 on timer F period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DC3

Bit 25: ADC trigger 1 on Timer D compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC4

Bit 26: ADC trigger 1 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 27: ADC trigger 1 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

FRST

Bit 28: Bit 28 - ADC trigger 1 on timer F reset and counter roll-over.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

EC3

Bit 29: ADC trigger 1 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 1 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EPER

Bit 31: ADC trigger 1 on Timer E Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ADC4R

ADC Trigger 4 Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields MC[1]

Bit 0: ADC trigger 2 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 2 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 2 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 2 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 2 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[6]

Bit 5: ADC trigger 2 on External Event 6.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[7]

Bit 6: ADC trigger 2 on External Event 7.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[8]

Bit 7: ADC trigger 2 on External Event 8.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[9]

Bit 8: ADC trigger 2 on External Event 9.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[10]

Bit 9: ADC trigger 2 on External Event 10.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

AC2

Bit 10: ADC trigger 2 on Timer A compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

FC2

Bit 11: Bit 11 - ADC trigger 3 on timer F compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 2 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 2 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BC2

Bit 14: ADC trigger 2 on Timer B compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

FC3

Bit 15: Bit 15 - ADC trigger 2 on timer F compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 16: ADC trigger 2 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 17: ADC trigger 2 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CC2

Bit 18: ADC trigger 2 on Timer C compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

FC4

Bit 19: Bit 19 - ADC trigger 2 on timer F compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 20: ADC trigger 2 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 21: ADC trigger 2 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CRST

Bit 22: ADC trigger 2 on Timer C Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

DC2

Bit 23: ADC trigger 2 on Timer D compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

FPER

Bit 24: Bit 24 - ADC trigger 2 on timer F period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DC4

Bit 25: ADC trigger 2 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 26: ADC trigger 2 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DRST

Bit 27: ADC trigger 2 on Timer D Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

EC2

Bit 28: ADC trigger 2 on Timer E compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC3

Bit 29: ADC trigger 2 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 2 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

ERST

Bit 31: ADC trigger 2 on Timer E Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

DLLCR

DLL Control Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Toggle fields CAL

Bit 0: DLL Calibration Start.

Allowed values:
1: Start: Calibration start

CALEN

Bit 1: DLL Calibration Enable.

Allowed values:
0: Disabled: Periodic calibration disabled
1: Enabled: Calibration is performed periodically, as per CALRTE setting

CALRTE

Bits 2-3: DLL Calibration rate.

Allowed values:
0: Clk1048576: 1048576*t_HRTIM (6.168 ms for fHRTIM = 170 MHz)
1: Clk131072: 131072*t_HRTIM (771 µs for f_HRTIM = 170 MHz)
2: Clk16384: 16384*t_HRTIM (96 µs for f_HRTIM = 170 MHz)
3: Clk2048: 2048*t_HRTIM (12 µs for f_HRTIM = 170 MHz)

FLTINR1

HRTIM Fault Input Register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

Toggle fields FLT[1]E

Bit 0: FLT1E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[1]P

Bit 1: FLT1P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[1]SRC

Bit 2: Fault 1 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: CompOutput: Fault input is connected to a COMPx output

FLT[1]F

Bits 3-6: FLT1F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT1LCK

Bit 7: FLT1LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[2]E

Bit 8: FLT2E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[2]P

Bit 9: FLT2P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[2]SRC

Bit 10: Fault 2 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: CompOutput: Fault input is connected to a COMPx output

FLT[2]F

Bits 11-14: FLT2F.

FLT2LCK

Bit 15: FLT2LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[3]E

Bit 16: FLT3E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[3]P

Bit 17: FLT3P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[3]SRC

Bit 18: Fault 3 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: CompOutput: Fault input is connected to a COMPx output

FLT[3]F

Bits 19-22: FLT3F.

FLT3LCK

Bit 23: FLT3LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[4]E

Bit 24: FLT4E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[4]P

Bit 25: FLT4P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[4]SRC

Bit 26: Fault 4 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: CompOutput: Fault input is connected to a COMPx output

FLT[4]F

Bits 27-30: FLT4F.

FLT4LCK

Bit 31: FLT4LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLTINR2

HRTIM Fault Input Register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

Toggle fields FLT[5]E

Bit 0: FLT5E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[5]P

Bit 1: FLT5P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[5]SRC

Bit 2: Fault 5 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: CompOutput: Fault input is connected to a COMPx output

FLT[5]F

Bits 3-6: FLT5F.

FLT5LCK

Bit 7: FLT5LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[6]E

Bit 8: FLT6E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[6]P

Bit 9: FLT6P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[6]SRC

Bit 10: Fault 6 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: CompOutput: Fault input is connected to a COMPx output

FLT[6]F

Bits 11-14: FLT6F.

FLT6LCK

Bit 15: FLT6LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[1]SRC_1

Bit 16: Fault 1 source bit 1.

Allowed values:
0: Default: As described in FLTxSRC
1: Eev: Fault input is EEV5_muxout input pin (when FLTxSRC == 0) / reserved

FLT[2]SRC_1

Bit 17: Fault 2 source bit 1.

Allowed values:
0: Default: As described in FLTxSRC
1: Eev: Fault input is EEV5_muxout input pin (when FLTxSRC == 0) / reserved

FLT[3]SRC_1

Bit 18: Fault 3 source bit 1.

Allowed values:
0: Default: As described in FLTxSRC
1: Eev: Fault input is EEV5_muxout input pin (when FLTxSRC == 0) / reserved

FLT[4]SRC_1

Bit 19: Fault 4 source bit 1.

Allowed values:
0: Default: As described in FLTxSRC
1: Eev: Fault input is EEV5_muxout input pin (when FLTxSRC == 0) / reserved

FLT[5]SRC_1

Bit 20: Fault 5 source bit 1.

Allowed values:
0: Default: As described in FLTxSRC
1: Eev: Fault input is EEV5_muxout input pin (when FLTxSRC == 0) / reserved

FLT[6]SRC_1

Bit 21: Fault 6 source bit 1.

Allowed values:
0: Default: As described in FLTxSRC
1: Eev: Fault input is EEV5_muxout input pin (when FLTxSRC == 0) / reserved

FLTSD

Bits 24-25: FLTSD.

Allowed values:
0: Div1: f_FLTS=f_HRTIM
1: Div2: f_FLTS=f_HRTIM/2
2: Div4: f_FLTS=f_HRTIM/4
3: Div8: f_FLTS=f_HRTIM/8

BDMUPR

BDMUPDR

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Toggle fields MCR

Bit 0: MCR.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MICR

Bit 1: MICR.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MDIER

Bit 2: MDIER.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCNT

Bit 3: MCNT.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MPER

Bit 4: MPER.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MREP

Bit 5: MREP.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP1

Bit 6: MCMP1.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP2

Bit 7: MCMP2.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP3

Bit 8: MCMP3.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP4

Bit 9: MCMP4.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTAUPR

Burst DMA Timerx update Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

Toggle fields CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CR2

Bit 21: TIMxCR2.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR3

Bit 22: TIMxEEFR3.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTBUPR

Burst DMA Timerx update Register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

Toggle fields CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CR2

Bit 21: TIMxCR2.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR3

Bit 22: TIMxEEFR3.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTCUPR

Burst DMA Timerx update Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

Toggle fields CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CR2

Bit 21: TIMxCR2.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR3

Bit 22: TIMxEEFR3.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTDUPR

Burst DMA Timerx update Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

Toggle fields CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CR2

Bit 21: TIMxCR2.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR3

Bit 22: TIMxEEFR3.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTEUPR

Burst DMA Timerx update Register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

Toggle fields CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CR2

Bit 21: TIMxCR2.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR3

Bit 22: TIMxEEFR3.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDMADR

Burst DMA Data Register

Offset: 0x70, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDMADR
w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BDMADR
w Toggle fields BDMADR

Bits 0-31: Burst DMA Data register.

Allowed values: 0x0-0xffffffff

BDTFUPR

Burst DMA Timerx update Register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

Toggle fields CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CR2

Bit 21: TIMxCR2.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR3

Bit 22: TIMxEEFR3.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ADCER

HRTIM ADC Extended Trigger Register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

Toggle fields ADC5TRG

Bits 0-4: ADC5TRG.

ADC6TRG

Bits 5-9: ADC6TRG.

ADC7TRG

Bits 10-14: ADC7TRG.

ADC8TRG

Bits 16-20: ADC8TRG.

ADC9TRG

Bits 21-25: ADC9TRG.

ADC10TRG

Bits 26-30: ADC10TRG.

ADCUR

HRTIM ADC Trigger Update Register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

Toggle fields AD5USRC

Bits 0-2: AD5USRC.

AD6USRC

Bits 4-6: AD6USRC.

AD7USRC

Bits 8-10: AD7USRC.

AD8USRC

Bits 12-14: AD8USRC.

AD9USRC

Bits 16-18: AD9USRC.

AD10USRC

Bits 20-22: AD10USRC.

ADCPS1

HRTIM ADC Post Scaler Register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

Toggle fields ADC1PSC

Bits 0-4: ADC1PSC.

ADC2PSC

Bits 6-10: ADC2PSC.

ADC3PSC

Bits 12-16: ADC3PSC.

ADC4PSC

Bits 18-22: ADC4PSC.

ADC5PSC

Bits 24-28: ADC5PSC.

ADCPS2

HRTIM ADC Post Scaler Register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

Toggle fields ADC6PSC

Bits 0-4: ADC6PSC.

ADC7PSC

Bits 6-10: ADC7PSC.

ADC8PSC

Bits 12-16: ADC8PSC.

ADC9PSC

Bits 18-22: ADC9PSC.

ADC10PSC

Bits 24-28: ADC10PSC.

FLTINR3

HRTIM Fault Input Register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

Toggle fields FLT[1]BLKE

Bit 0: FLT1BLKE.

FLT[1]BLKS

Bit 1: FLT1BLKS.

FLT[1]CNT

Bits 2-5: FLT1CNT.

FLT[1]CRES

Bit 6: FLT1CRES.

FLT1RSTM

Bit 7: FLT1RSTM.

FLT[2]BLKE

Bit 8: FLT2BLKE.

FLT[2]BLKS

Bit 9: FLT2BLKS.

FLT[2]CNT

Bits 10-13: FLT2CNT.

FLT[2]CRES

Bit 14: FLT2CRES.

FLT2RSTM

Bit 15: FLT2RSTM.

FLT[3]BLKE

Bit 16: FLT3BLKE.

FLT[3]BLKS

Bit 17: FLT3BLKS.

FLT[3]CNT

Bits 18-21: FLT3CNT.

FLT[3]CRES

Bit 22: FLT3CRES.

FLT3RSTM

Bit 23: FLT3RSTM.

FLT[4]BLKE

Bit 24: FLT4BLKE.

FLT[4]BLKS

Bit 25: FLT4BLKS.

FLT[4]CNT

Bits 26-29: FLT4CNT.

FLT[4]CRES

Bit 30: FLT4CRES.

FLT4RSTM

Bit 31: FLT4RSTM.

FLTINR4

HRTIM Fault Input Register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

Toggle fields FLT[5]BLKE

Bit 0: FLT5BLKE.

FLT[5]BLKS

Bit 1: FLT5BLKS.

FLT[5]CNT

Bits 2-5: FLT5CNT.

FLT[5]CRES

Bit 6: FLT5CRES.

FLT5RSTM

Bit 7: FLT5RSTM.

FLT[6]BLKE

Bit 8: FLT6BLKE.

FLT[6]BLKS

Bit 9: FLT6BLKS.

FLT[6]CNT

Bits 10-13: FLT6CNT.

FLT[6]CRES

Bit 14: FLT6CRES.

FLT6RSTM

Bit 15: FLT6RSTM.

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