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Showing content from https://stm32-rs.github.io/stm32-rs/STM32G441.html below:

STM32G441 Peripheral Coverage

Overall: 5582/7238 fields covered

0x50000000: Analog-to-Digital Converter

187/197 fields covered.

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bit 0: ADC ready.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

Bit 1: End of sampling flag.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 2: End of conversion flag.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 3: End of regular sequence flag.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 4: ADC overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 5: Injected channel end of conversion flag.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 6: Injected channel end of sequence flag.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 10: Injected context queue overflow.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bit 0: ADC ready interrupt enable.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

Bit 1: End of sampling flag interrupt enable for regular conversions.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

Bit 2: End of regular conversion interrupt enable.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

Bit 3: End of regular sequence of conversions interrupt enable.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

Bit 4: Overrun interrupt enable.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

Bit 5: End of injected conversion interrupt enable.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

Bit 6: End of injected sequence of conversions interrupt enable.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 10: Injected context queue overflow interrupt enable.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

control register

Offset: 0x8, size: 32, reset: 0x20000000, access: read-write

10/10 fields covered.

Bit 0: ADC enable control.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

Bit 1: ADC disable command.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

Bit 2: ADC start of regular conversion.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

Bit 3: ADC start of injected conversion.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

Bit 4: ADC stop of regular conversion command.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

Bit 5: ADC stop of injected conversion command.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

Bit 28: ADC voltage regulator enable.

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

Bit 29: Deep-power-down enable.

Allowed values:
0: Disabled: ADC not in Deep-power down
1: Enabled: ADC in Deep-power-down (default reset state)

Bit 30: Differential mode for calibration.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

Bit 31: ADC calibration.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

configuration register

Offset: 0xc, size: 32, reset: 0x80000000, access: read-write

19/19 fields covered.

Bit 0: Direct memory access enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

Bit 1: Direct memory access configuration.

Allowed values:
0: OneShot: DMA One Shot Mode selected
1: Circular: DMA circular mode selected

Bits 3-4: Data resolution.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

Bits 5-9: External trigger selection for regular group.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
7: HRTIM_ADCTRG1: HRTIM_ADCTRG1 event
8: HRTIM_ADCTRG3: HRTIM_ADCTRG3 event
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

Bits 10-11: External trigger enable and polarity selection for regular channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 12: Overrun mode.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

Bit 13: Single / continuous conversion mode for regular conversions.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 14: Delayed conversion mode.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

Bit 15: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

Bit 16: Discontinuous mode for regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bits 17-19: Discontinuous mode channel count.

Allowed values: 0x0-0x7

Bit 20: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bit 21: JSQR queue mode.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

Bit 22: Enable the watchdog 1 on a single channel or on all channels.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

Bit 23: Analog watchdog 1 enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

Bit 24: Analog watchdog 1 enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

Bit 25: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bits 26-30: Analog watchdog 1 channel selection.

Allowed values: 0x0-0x12

Bit 31: Injected Queue disable.

Allowed values:
0: Enabled: Injected Queue enabled
1: Disabled: Injected Queue disabled

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bit 0: Regular Oversampling Enable.

Allowed values:
0: Disabled: Regular oversampling disabled
1: Enabled: Regular oversampling enabled

Bit 1: Injected Oversampling Enable.

Allowed values:
0: Disabled: Injected oversampling disabled
1: Enabled: Injected oversampling enabled

Bits 2-4: Oversampling ratio.

Allowed values:
0: OS2: Oversampling ratio of 2
1: OS4: Oversampling ratio of 4
2: OS8: Oversampling ratio of 8
3: OS16: Oversampling ratio of 16
4: OS32: Oversampling ratio of 32
5: OS64: Oversampling ratio of 64
6: OS128: Oversampling ratio of 128
7: OS256: Oversampling ratio of 256

Bits 5-8: Oversampling shift.

Allowed values:
0: NoShift: No right shift applied to oversampling result
1: Shift1: Shift oversampling result right by 1 bit
2: Shift2: Shift oversampling result right by 2 bits
3: Shift3: Shift oversampling result right by 3 bits
4: Shift4: Shift oversampling result right by 4 bits
5: Shift5: Shift oversampling result right by 5 bits
6: Shift6: Shift oversampling result right by 6 bits
7: Shift7: Shift oversampling result right by 7 bits
8: Shift8: Shift oversampling result right by 8 bits

Bit 9: Triggered Regular Oversampling.

Allowed values:
0: Automatic: All oversampled conversions for a channel are run following a trigger
1: Triggered: Each oversampled conversion for a channel needs a new trigger

Bit 10: Regular Oversampling mode.

Allowed values:
0: Continued: Oversampling is temporary stopped and continued after injection sequence
1: Resumed: Oversampling is aborted and resumed from start after injection sequence

Bit 16: Gain compensation mode.

Allowed values:
0: Disabled: Regular ADC operating mode
1: Enabled: Gain compensation enabled and applies to all channels

Bit 25: Software trigger bit for sampling time control trigger mode.

Allowed values:
0: Disabled: End sampling period and start conversion
1: Enabled: Start sampling period

Bit 26: Bulb sampling mode.

Allowed values:
0: Disabled: Bulb sampling mode disabled
1: Enabled: Bulb sampling mode enabled. Immediately start sampling after last conversion finishes.

Bit 27: Sampling time control trigger mode.

Allowed values:
0: Disabled: Sampling time control trigger mode disabled
1: Enabled: Sampling time control trigger mode enabled

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bit 31: Addition of one clock cycle to the sampling time.

Allowed values:
0: KeepCycles: The sampling time remains set to 2.5 ADC clock cycles remains
1: Add1Cycle: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/3 fields covered.

Bits 0-11: Analog watchdog 1 lower threshold.

Allowed values: 0x0-0xfff

Bits 12-14: Analog watchdog filtering parameter.

Bits 16-27: Analog watchdog 1 higher threshold.

Allowed values: 0x0-0xfff

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x00FF0000, access: read-write

2/2 fields covered.

Bits 0-7: Analog watchdog 2 lower threshold.

Allowed values: 0x0-0xff

Bits 16-23: Analog watchdog 2 higher threshold.

Allowed values: 0x0-0xff

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x00FF0000, access: read-write

2/2 fields covered.

Bits 0-7: Analog watchdog 3 lower threshold.

Allowed values: 0x0-0xff

Bits 16-23: Analog watchdog 3 higher threshold.

Allowed values: 0x0-0xff

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-3: Regular channel sequence length.

Allowed values: 0x0-0xf

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Regular Data converted.

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

Bits 0-1: Injected channel sequence length.

Allowed values: 0x0-0x3

Bits 2-6: External Trigger Selection for injected group.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

Bits 7-8: External Trigger Enable and Polarity Selection for injected channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bits 9-13: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 15-19: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 21-25: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 27-31: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bit 24: Positive offset.

Bit 25: Saturation enable.

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bit 24: Positive offset.

Bit 25: Saturation enable.

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bit 24: Positive offset.

Bit 25: Saturation enable.

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bit 24: Positive offset.

Bit 25: Saturation enable.

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 1: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 2: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 3: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 4: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 5: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 6: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 7: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 8: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 9: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 10: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 11: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 12: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 13: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 14: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 15: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 16: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 17: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 18: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 1: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 2: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 3: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 4: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 5: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 6: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 7: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 8: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 9: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 10: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 11: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 12: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 13: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 14: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 15: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 16: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 17: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 18: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

19/19 fields covered.

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-6: Calibration Factors In single-ended mode.

Allowed values: 0x0-0x7f

Bits 16-22: Calibration Factors in differential mode.

Allowed values: 0x0-0x7f

Gain compensation Register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-13: Gain compensation coefficient.

0x50000300: Analog-to-Digital Converter

30/33 fields covered.

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

Bit 0: ADDRDY_MST.

Bit 1: EOSMP_MST.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 2: EOC_MST.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 3: EOS_MST.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 4: OVR_MST.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 5: JEOC_MST.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 6: JEOS_MST.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 7: AWD1_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 8: AWD2_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 9: AWD3_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 10: JQOVF_MST.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

Bit 16: ADRDY_SLV.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

Bit 17: EOSMP_SLV.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 18: End of regular conversion of the slave ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 19: End of regular sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 20: Overrun flag of the slave ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 21: End of injected conversion flag of the slave ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 22: End of injected sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 23: Analog watchdog 1 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 24: Analog watchdog 2 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 25: Analog watchdog 3 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 26: Injected Context Queue Overflow flag of the slave ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/9 fields covered.

Bits 0-4: Dual ADC mode selection.

Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only

Bits 8-11: Delay between 2 sampling phases.

Allowed values: 0x0-0xf

Bit 13: DMA configuration (for multi-ADC mode).

Bits 14-15: Direct memory access mode for multi ADC mode.

Bits 16-17: ADC clock mode.

Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4

Bits 18-21: ADC prescaler.

Bit 22: VREFINT enable.

Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled

Bit 23: VTS selection.

Allowed values:
0: Disabled: Temperature sensor channel disabled
1: Enabled: Temperature sensor channel enabled

Bit 24: VBAT selection.

Allowed values:
0: Disabled: V_BAT channel disabled
1: Enabled: V_BAT channel enabled

ADC common regular data register for dual and triple modes

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-15: Regular data of the master ADC.

Bits 16-31: Regular data of the slave ADC.

0x50000100: Analog-to-Digital Converter

187/197 fields covered.

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bit 0: ADC ready.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

Bit 1: End of sampling flag.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 2: End of conversion flag.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 3: End of regular sequence flag.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 4: ADC overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 5: Injected channel end of conversion flag.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 6: Injected channel end of sequence flag.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 10: Injected context queue overflow.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bit 0: ADC ready interrupt enable.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

Bit 1: End of sampling flag interrupt enable for regular conversions.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

Bit 2: End of regular conversion interrupt enable.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

Bit 3: End of regular sequence of conversions interrupt enable.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

Bit 4: Overrun interrupt enable.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

Bit 5: End of injected conversion interrupt enable.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

Bit 6: End of injected sequence of conversions interrupt enable.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 10: Injected context queue overflow interrupt enable.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

control register

Offset: 0x8, size: 32, reset: 0x20000000, access: read-write

10/10 fields covered.

Bit 0: ADC enable control.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

Bit 1: ADC disable command.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

Bit 2: ADC start of regular conversion.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

Bit 3: ADC start of injected conversion.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

Bit 4: ADC stop of regular conversion command.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

Bit 5: ADC stop of injected conversion command.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

Bit 28: ADC voltage regulator enable.

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

Bit 29: Deep-power-down enable.

Allowed values:
0: Disabled: ADC not in Deep-power down
1: Enabled: ADC in Deep-power-down (default reset state)

Bit 30: Differential mode for calibration.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

Bit 31: ADC calibration.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

configuration register

Offset: 0xc, size: 32, reset: 0x80000000, access: read-write

19/19 fields covered.

Bit 0: Direct memory access enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

Bit 1: Direct memory access configuration.

Allowed values:
0: OneShot: DMA One Shot Mode selected
1: Circular: DMA circular mode selected

Bits 3-4: Data resolution.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

Bits 5-9: External trigger selection for regular group.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
7: HRTIM_ADCTRG1: HRTIM_ADCTRG1 event
8: HRTIM_ADCTRG3: HRTIM_ADCTRG3 event
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

Bits 10-11: External trigger enable and polarity selection for regular channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 12: Overrun mode.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

Bit 13: Single / continuous conversion mode for regular conversions.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 14: Delayed conversion mode.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

Bit 15: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

Bit 16: Discontinuous mode for regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bits 17-19: Discontinuous mode channel count.

Allowed values: 0x0-0x7

Bit 20: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bit 21: JSQR queue mode.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

Bit 22: Enable the watchdog 1 on a single channel or on all channels.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

Bit 23: Analog watchdog 1 enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

Bit 24: Analog watchdog 1 enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

Bit 25: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bits 26-30: Analog watchdog 1 channel selection.

Allowed values: 0x0-0x12

Bit 31: Injected Queue disable.

Allowed values:
0: Enabled: Injected Queue enabled
1: Disabled: Injected Queue disabled

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bit 0: Regular Oversampling Enable.

Allowed values:
0: Disabled: Regular oversampling disabled
1: Enabled: Regular oversampling enabled

Bit 1: Injected Oversampling Enable.

Allowed values:
0: Disabled: Injected oversampling disabled
1: Enabled: Injected oversampling enabled

Bits 2-4: Oversampling ratio.

Allowed values:
0: OS2: Oversampling ratio of 2
1: OS4: Oversampling ratio of 4
2: OS8: Oversampling ratio of 8
3: OS16: Oversampling ratio of 16
4: OS32: Oversampling ratio of 32
5: OS64: Oversampling ratio of 64
6: OS128: Oversampling ratio of 128
7: OS256: Oversampling ratio of 256

Bits 5-8: Oversampling shift.

Allowed values:
0: NoShift: No right shift applied to oversampling result
1: Shift1: Shift oversampling result right by 1 bit
2: Shift2: Shift oversampling result right by 2 bits
3: Shift3: Shift oversampling result right by 3 bits
4: Shift4: Shift oversampling result right by 4 bits
5: Shift5: Shift oversampling result right by 5 bits
6: Shift6: Shift oversampling result right by 6 bits
7: Shift7: Shift oversampling result right by 7 bits
8: Shift8: Shift oversampling result right by 8 bits

Bit 9: Triggered Regular Oversampling.

Allowed values:
0: Automatic: All oversampled conversions for a channel are run following a trigger
1: Triggered: Each oversampled conversion for a channel needs a new trigger

Bit 10: Regular Oversampling mode.

Allowed values:
0: Continued: Oversampling is temporary stopped and continued after injection sequence
1: Resumed: Oversampling is aborted and resumed from start after injection sequence

Bit 16: Gain compensation mode.

Allowed values:
0: Disabled: Regular ADC operating mode
1: Enabled: Gain compensation enabled and applies to all channels

Bit 25: Software trigger bit for sampling time control trigger mode.

Allowed values:
0: Disabled: End sampling period and start conversion
1: Enabled: Start sampling period

Bit 26: Bulb sampling mode.

Allowed values:
0: Disabled: Bulb sampling mode disabled
1: Enabled: Bulb sampling mode enabled. Immediately start sampling after last conversion finishes.

Bit 27: Sampling time control trigger mode.

Allowed values:
0: Disabled: Sampling time control trigger mode disabled
1: Enabled: Sampling time control trigger mode enabled

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bit 31: Addition of one clock cycle to the sampling time.

Allowed values:
0: KeepCycles: The sampling time remains set to 2.5 ADC clock cycles remains
1: Add1Cycle: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/3 fields covered.

Bits 0-11: Analog watchdog 1 lower threshold.

Allowed values: 0x0-0xfff

Bits 12-14: Analog watchdog filtering parameter.

Bits 16-27: Analog watchdog 1 higher threshold.

Allowed values: 0x0-0xfff

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x00FF0000, access: read-write

2/2 fields covered.

Bits 0-7: Analog watchdog 2 lower threshold.

Allowed values: 0x0-0xff

Bits 16-23: Analog watchdog 2 higher threshold.

Allowed values: 0x0-0xff

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x00FF0000, access: read-write

2/2 fields covered.

Bits 0-7: Analog watchdog 3 lower threshold.

Allowed values: 0x0-0xff

Bits 16-23: Analog watchdog 3 higher threshold.

Allowed values: 0x0-0xff

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-3: Regular channel sequence length.

Allowed values: 0x0-0xf

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Regular Data converted.

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

Bits 0-1: Injected channel sequence length.

Allowed values: 0x0-0x3

Bits 2-6: External Trigger Selection for injected group.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

Bits 7-8: External Trigger Enable and Polarity Selection for injected channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bits 9-13: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 15-19: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 21-25: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

Bits 27-31: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bit 24: Positive offset.

Bit 25: Saturation enable.

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bit 24: Positive offset.

Bit 25: Saturation enable.

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bit 24: Positive offset.

Bit 25: Saturation enable.

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

Bit 24: Positive offset.

Bit 25: Saturation enable.

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 1: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 2: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 3: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 4: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 5: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 6: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 7: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 8: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 9: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 10: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 11: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 12: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 13: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 14: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 15: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 16: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 17: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 18: Analog watchdog 2 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 1: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 2: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 3: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 4: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 5: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 6: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 7: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 8: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 9: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 10: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 11: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 12: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 13: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 14: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 15: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 16: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 17: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Bit 18: Analog watchdog 3 channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

19/19 fields covered.

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-6: Calibration Factors In single-ended mode.

Allowed values: 0x0-0x7f

Bits 16-22: Calibration Factors in differential mode.

Allowed values: 0x0-0x7f

Gain compensation Register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-13: Gain compensation coefficient.

0x50000700: Analog-to-Digital Converter

30/33 fields covered.

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

Bit 0: ADDRDY_MST.

Bit 1: EOSMP_MST.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 2: EOC_MST.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 3: EOS_MST.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 4: OVR_MST.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 5: JEOC_MST.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 6: JEOS_MST.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 7: AWD1_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 8: AWD2_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 9: AWD3_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 10: JQOVF_MST.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

Bit 16: ADRDY_SLV.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

Bit 17: EOSMP_SLV.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

Bit 18: End of regular conversion of the slave ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

Bit 19: End of regular sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

Bit 20: Overrun flag of the slave ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 21: End of injected conversion flag of the slave ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

Bit 22: End of injected sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

Bit 23: Analog watchdog 1 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 24: Analog watchdog 2 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 25: Analog watchdog 3 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 26: Injected Context Queue Overflow flag of the slave ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/9 fields covered.

Bits 0-4: Dual ADC mode selection.

Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only

Bits 8-11: Delay between 2 sampling phases.

Allowed values: 0x0-0xf

Bit 13: DMA configuration (for multi-ADC mode).

Bits 14-15: Direct memory access mode for multi ADC mode.

Bits 16-17: ADC clock mode.

Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4

Bits 18-21: ADC prescaler.

Bit 22: VREFINT enable.

Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled

Bit 23: VTS selection.

Allowed values:
0: Disabled: Temperature sensor channel disabled
1: Enabled: Temperature sensor channel enabled

Bit 24: VBAT selection.

Allowed values:
0: Disabled: V_BAT channel disabled
1: Enabled: V_BAT channel enabled

ADC common regular data register for dual and triple modes

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-15: Regular data of the master ADC.

Bits 16-31: Regular data of the slave ADC.

0x50060000: Advanced encryption standard hardware accelerator

40/40 fields covered.

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

Bit 0: AES enable.

Allowed values:
0: Disabled: Disable AES
1: Enabled: Enable AES

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

Allowed values:
0: None: Word
1: HalfWord: Half-word (16-bit)
2: Byte: Byte (8-bit)
3: Bit: Bit

Bits 3-4: AES operating mode.

Allowed values:
0: Mode1: Mode 1: encryption
1: Mode2: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
2: Mode3: Mode 3: decryption
3: Mode4: Mode 4: key derivation then single decryption

Bits 5-6: AES chaining mode.

Allowed values:
0: ECB: Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1
1: CBC: Cipher-block chaining (CBC)
2: CTR: Counter mode (CTR)
3: GCM: Galois counter mode (GCM) and Galois message authentication code (GMAC)

Bit 7: Computation Complete Flag Clear.

Allowed values:
1: Clear: Clear computation complete flag

Bit 8: Error clear.

Allowed values:
1: Clear: Clear RDERR and WRERR flags

Bit 9: CCF flag interrupt enable.

Allowed values:
0: Disabled: Disable (mask) CCF interrupt
1: Enabled: Enable CCF interrupt

Bit 10: Error interrupt enable.

Allowed values:
0: Disabled: Disable (mask) error interrupt
1: Enabled: Enable error interrupt

Bit 11: Enable DMA management of data input phase.

Allowed values:
0: Disabled: Disable DMA Input
1: Enabled: Enable DMA Input

Bit 12: Enable DMA management of data output phase.

Allowed values:
0: Disabled: Disable DMA Output
1: Enabled: Enabled DMA Output

Bits 13-14: GCMPH.

Allowed values:
0: Init: Init phase
1: Header: Header phase
2: Payload: Payload phase
3: Final: Final Phase

Bit 16: CHMOD_2.

Allowed values:
0: CHMOD: Mode as per CHMOD (ECB, CBC, CTR, GCM)
1: CCM: Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB)

Bit 18: KEYSIZE.

Allowed values:
0: AES128: 128
1: AES256: 256

Bits 20-23: NPBLB.

Allowed values: 0x0-0xf

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bit 0: Computation complete flag.

Allowed values:
0: Complete: Computation complete
1: NotComplete: Computation not complete

Bit 1: Read error flag.

Allowed values:
0: NoError: Read error not detected
1: Error: Read error detected

Bit 2: Write error flag.

Allowed values:
0: NoError: Write error not detected
1: Error: Write error detected

Bit 3: BUSY.

Allowed values:
0: Idle: Idle
1: Busy: Busy

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Data Input Register.

Allowed values: 0x0-0xffffffff

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-31: Data output register.

Allowed values: 0x0-0xffffffff

key register 0

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Data Output Register (LSB key [31:0]).

Allowed values: 0x0-0xffffffff

key register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES key register (key [63:32]).

Allowed values: 0x0-0xffffffff

key register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES key register (key [95:64]).

Allowed values: 0x0-0xffffffff

key register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES key register (MSB key [127:96]).

Allowed values: 0x0-0xffffffff

initialization vector register 0

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: initialization vector register (LSB IVR [31:0]).

Allowed values: 0x0-0xffffffff

initialization vector register 1

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Initialization Vector Register (IVR [63:32]).

Allowed values: 0x0-0xffffffff

initialization vector register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Initialization Vector Register (IVR [95:64]).

Allowed values: 0x0-0xffffffff

initialization vector register 3

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

Allowed values: 0x0-0xffffffff

key register 4

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES key.

Allowed values: 0x0-0xffffffff

key register 5

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES key.

Allowed values: 0x0-0xffffffff

key register 6

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES key.

Allowed values: 0x0-0xffffffff

key register 7

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES key.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

suspend registers

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: AES suspend.

Allowed values: 0x0-0xffffffff

0x40010200: Comparator control and status register

7/70 fields covered.

Comparator control/status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

Bit 0: EN.

Bits 4-6: INMSEL.

Bit 8: INPSEL.

Bit 15: POL.

Bits 16-18: HYST.

Bits 19-21: BLANKSEL.

Bit 22: BRGEN.

Bit 23: SCALEN.

Bit 30: VALUE.

Bit 31: LOCK.

Comparator control/status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

Bit 0: EN.

Bits 4-6: INMSEL.

Bit 8: INPSEL.

Bit 15: POL.

Bits 16-18: HYST.

Bits 19-21: BLANKSEL.

Bit 22: BRGEN.

Bit 23: SCALEN.

Bit 30: VALUE.

Bit 31: LOCK.

Comparator control/status register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

Bit 0: EN.

Bits 4-6: INMSEL.

Bit 8: INPSEL.

Bit 15: POL.

Bits 16-18: HYST.

Bits 19-21: BLANKSEL.

Bit 22: BRGEN.

Bit 23: SCALEN.

Bit 30: VALUE.

Bit 31: LOCK.

Comparator control/status register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

Bit 0: EN.

Bits 4-6: INMSEL.

Bit 8: INPSEL.

Bit 15: POL.

Bits 16-18: HYST.

Bits 19-21: BLANKSEL.

Bit 22: BRGEN.

Bit 23: SCALEN.

Bit 30: VALUE.

Bit 31: LOCK.

Comparator control/status register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

Bit 0: EN.

Bits 4-6: INMSEL.

Bit 8: INPSEL.

Bit 15: POL.

Bits 16-18: HYST.

Bits 19-21: BLANKSEL.

Bit 22: BRGEN.

Bit 23: SCALEN.

Bit 30: VALUE.

Bit 31: LOCK.

Comparator control/status register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

Bit 0: EN.

Bits 4-6: INMSEL.

Bit 8: INPSEL.

Bit 15: POL.

Bits 16-18: HYST.

Bits 19-21: BLANKSEL.

Bit 22: BRGEN.

Bit 23: SCALEN.

Bit 30: VALUE.

Bit 31: LOCK.

Comparator control/status register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

Bit 0: EN.

Bits 4-6: INMSEL.

Bit 8: INPSEL.

Bit 15: POL.

Bits 16-18: HYST.

Bits 19-21: BLANKSEL.

Bit 22: BRGEN.

Bit 23: SCALEN.

Bit 30: VALUE.

Bit 31: LOCK.

0x40020c00: CORDIC Co-processor

13/13 fields covered.

CORDIC Control Status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Bits 0-3: FUNC.

Allowed values:
0: Cosine: Cosine function
1: Sine: Sine function
2: Phase: Phase function
3: Modulus: Modulus function
4: Arctangent: Arctangent function
5: HyperbolicCosine: Hyperbolic Cosine function
6: HyperbolicSine: Hyperbolic Sine function
7: Arctanh: Arctanh function
8: NaturalLogarithm: Natural Logarithm function
9: SquareRoot: Square Root function

Bits 4-7: Precision (number of iterations/cycles) required.

Allowed values:
1: Iters4: 4 iterations
2: Iters8: 8 iterations
3: Iters12: 12 iterations
4: Iters16: 16 iterations
5: Iters20: 20 iterations
6: Iters24: 24 iterations
7: Iters28: 28 iterations
8: Iters32: 32 iterations
9: Iters36: 36 iterations
10: Iters40: 40 iterations
11: Iters44: 44 iterations
12: Iters48: 48 iterations
13: Iters52: 52 iterations
14: Iters56: 56 iterations
15: Iters60: 60 iterations

Bits 8-10: Scaling factor (2^-n for arguments, 2^n for results).

Allowed values: 0x0-0x7

Bit 16: IEN.

Allowed values:
0: Disabled: Disable interrupt request generation
1: Enabled: Enable interrupt request generation

Bit 17: DMAREN.

Allowed values:
0: Disabled: No DMA channel reads are generated
1: Enabled: Read requests are generated on the DMA channel when RRDY flag is set

Bit 18: DMAWEN.

Allowed values:
0: Disabled: No DMA channel writes are generated
1: Enabled: Write requests are generated on the DMA channel when no operation is pending

Bit 19: NRES.

Allowed values:
0: Num1: Only single result value will be returned. After a single read RRDY will be automatically cleared
1: Num2: Two return reads need to be performed. After two reads RRDY will be automatically cleared

Bit 20: NARGS.

Allowed values:
0: Num1: Only single argument write is needed for next calculation
1: Num2: Two argument writes need to be performed for next calculation

Bit 21: RESSIZE.

Allowed values:
0: Bits32: Use 32 bit output values
1: Bits16: Use 16 bit output values

Bit 22: ARGSIZE.

Allowed values:
0: Bits32: Use 32 bit input values
1: Bits16: Use 16 bit input values

Bit 31: RRDY.

Allowed values:
0: NotReady: Results from computation are not read
1: Ready: Results are ready, this flag will be automatically cleared once value is read

CORDIC argument register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: ARG.

Allowed values: 0x0-0xffffffff

CORDIC result register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-31: RES.

Allowed values: 0x0-0xffffffff

0x40023000: Cyclic redundancy check calculation unit

10/10 fields covered.

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

Bits 0-31: Data register bits.

Allowed values: 0x0-0xffffffff

Data register - half-word sized

Offset: 0x0, size: 16, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

Bits 0-15: Data register bits.

Allowed values: 0x0-0xffff

Data register - byte sized

Offset: 0x0, size: 8, reset: 0x000000FF, access: read-write

1/1 fields covered.

Bits 0-7: Data register bits.

Allowed values: 0x0-0xff

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: General-purpose 8-bit data register bits.

Allowed values: 0x0-0xffffffff

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

Bit 0: RESET bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

Bits 3-4: Polynomial size.

Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial

Bits 5-6: Reverse input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

Bit 7: Reverse output data.

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

Bits 0-31: Programmable initial CRC value.

Allowed values: 0x0-0xffffffff

polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

1/1 fields covered.

Bits 0-31: Programmable polynomial.

Allowed values: 0x0-0xffffffff

0x40002000: CRS

26/26 fields covered.

CRS control register

Offset: 0x0, size: 32, reset: 0x00004000, access: Unspecified

8/8 fields covered.

Bit 0: SYNC event OK interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Bit 1: SYNC warning interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Bit 2: Synchronization or trimming error interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Bit 3: Expected SYNC interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

Bit 5: Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified..

Allowed values:
0: Disabled: Frequency error counter disabled
1: Enabled: Frequency error counter enabled

Bit 6: Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details..

Allowed values:
0: Disabled: Automatic trimming disabled
1: Enabled: Automatic trimming enabled

Bit 7: Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware..

Allowed values:
1: Sync: A software sync is generated

Bits 8-14: HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only..

Allowed values: 0x0-0x3f

This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected.

Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write

5/5 fields covered.

Bits 0-15: Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior..

Allowed values: 0x0-0xffff

Bits 16-23: Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation..

Allowed values: 0x0-0xff

Bits 24-26: SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal..

Allowed values:
0: Div1: SYNC not divided
1: Div2: SYNC divided by 2
2: Div4: SYNC divided by 4
3: Div8: SYNC divided by 8
4: Div16: SYNC divided by 16
5: Div32: SYNC divided by 32
6: Div64: SYNC divided by 64
7: Div128: SYNC divided by 128

Bits 28-29: SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal..

Allowed values:
0: GPIO_AF: GPIO AF (crs_sync_in_1) selected as SYNC signal source
1: LSE: LSE (crs_sync_in_2) selected as SYNC signal source
2: USB_SOF: USB SOF (crs_sync_in_3) selected as SYNC signal source

Bit 31: SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source..

Allowed values:
0: RisingEdge: SYNC active on rising edge
1: FallingEdge: SYNC active on falling edge

CRS interrupt and status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

Bit 0: SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register..

Allowed values:
0: NotSignaled: Signal not set
1: Signaled: Signal set

Bit 1: SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register..

Allowed values:
0: NotSignaled: Signal not set
1: Signaled: Signal set

Bit 2: Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits..

Allowed values:
0: NotSignaled: Signal not set
1: Signaled: Signal set

Bit 3: Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register..

Allowed values:
0: NotSignaled: Signal not set
1: Signaled: Signal set

Bit 8: SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register..

Allowed values:
0: NotSignaled: Signal not set
1: Signaled: Signal set

Bit 9: SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register..

Allowed values:
0: NotSignaled: Signal not set
1: Signaled: Signal set

Bit 10: Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register..

Allowed values:
0: NotSignaled: Signal not set
1: Signaled: Signal set

Bit 15: Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target..

Allowed values:
0: UpCounting: Error in up-counting direction
1: DownCounting: Error in down-counting direction

Bits 16-31: Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage..

Allowed values: 0x0-0xffff

CRS interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bit 0: SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register..

Allowed values:
1: Clear: Clear flag

Bit 1: SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register..

Allowed values:
1: Clear: Clear flag

Bit 2: Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register..

Allowed values:
1: Clear: Clear flag

Bit 3: Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register..

Allowed values:
1: Clear: Clear flag

0x50000800: Digital-to-analog converter

77/77 fields covered.

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

Bit 1: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

Bits 2-5: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

Allowed values:
0: Swtrig: Software trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacReset1: hrtim_dac_reset_trg1
10: HrtimDacReset2: hrtim_dac_reset_trg2
11: HrtimDacReset3: hrtim_dac_reset_trg3
12: HrtimDacReset4: hrtim_dac_reset_trg4
13: HrtimDacReset5: hrtim_dac_reset_trg5
14: HrtimDacReset6: hrtim_dac_reset_trg6
15: HrtimDacX: hrtim_dac_trg1 (DAC1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

Bit 14: DAC channel1 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

Bit 17: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

Bits 18-21: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)..

Allowed values:
0: Swtrig: Software trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacReset1: hrtim_dac_reset_trg1
10: HrtimDacReset2: hrtim_dac_reset_trg2
11: HrtimDacReset3: hrtim_dac_reset_trg3
12: HrtimDacReset4: hrtim_dac_reset_trg4
13: HrtimDacReset5: hrtim_dac_reset_trg5
14: HrtimDacReset6: hrtim_dac_reset_trg6
15: HrtimDacX: hrtim_dac_trg1 (DAC1

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

Bit 29: DAC channel2 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

Bit 30: DAC channel2 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

Bit 0: DAC channel1 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

Bit 1: DAC channel2 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

Bit 16: DAC channel1 software trigger B.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger for sawtooth increment

Bit 17: DAC channel2 software trigger B.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger for sawtooth increment

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel1 12-bit right-aligned data B.

Allowed values: 0x0-0xfff

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

Bits 20-31: DAC channel1 12-bit left-aligned data B.

Allowed values: 0x0-0xfff

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

Bits 8-15: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

channel2 12-bit right-aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel1 12-bit right-aligned data B.

Allowed values: 0x0-0xfff

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

Bits 20-31: DAC channel1 12-bit left-aligned data B.

Allowed values: 0x0-0xfff

channel2 8-bit right aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

Bits 8-15: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel1 data output.

Allowed values: 0x0-0xfff

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel1 data output.

Allowed values: 0x0-0xfff

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

Bit 11: DAC channel1 ready status bit.

Allowed values:
0: NotReady: DAC channelX is not yet ready to accept the trigger nor output data
1: Ready: DAC channelX is ready to accept the trigger or output data

Bit 12: DAC channel1 output register status bit.

Allowed values:
0: Dor: DOR[11:0] is used actual DAC output
1: Dorb: DORB[11:0] is used actual DAC output

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

Bit 14: DAC channel1 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

Bit 15: DAC channel1 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

Bit 27: DAC channel2 ready status bit.

Allowed values:
0: NotReady: DAC channelX is not yet ready to accept the trigger nor output data
1: Ready: DAC channelX is ready to accept the trigger or output data

Bit 28: DAC channel2 output register status bit.

Allowed values:
0: Dor: DOR[11:0] is used actual DAC output
1: Dorb: DORB[11:0] is used actual DAC output

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

Bit 30: DAC channel2 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

Bit 31: DAC channel2 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-4: DAC channel1 offset trimming value.

Allowed values: 0x0-0x1f

Bits 16-20: DAC channel2 offset trimming value.

Allowed values: 0x0-0x1f

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

Bits 0-2: DAC channel1 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

Bit 8: DAC channel1 DMA double data mode.

Allowed values:
0: Normal: DMA Normal mode selected
1: DoubleData: DMA Double data mode selected

Bit 9: Enable signed format for DAC channel1.

Allowed values:
0: Unsigned: Input data is in unsigned format
1: Signed: Input data is in signed format (2's complement). The MSB bit represents the sign.

Bits 14-15: High frequency interface mode selection.

Allowed values:
0: Disabled: High frequency interface mode disabled
1: More80Mhz: High frequency interface mode enabled for AHB clock frequency > 80 MHz
2: More160Mhz: High frequency interface mode enabled for AHB clock frequency >160 MHz

Bits 16-18: DAC channel2 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

Bit 24: DAC channel2 DMA double data mode.

Allowed values:
0: Normal: DMA Normal mode selected
1: DoubleData: DMA Double data mode selected

Bit 25: Enable signed format for DAC channel2.

Allowed values:
0: Unsigned: Input data is in unsigned format
1: Signed: Input data is in signed format (2's complement). The MSB bit represents the sign.

DAC channel1 sample and hold sample time register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-9: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

DAC channel2 sample and hold sample time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-9: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

DAC Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

Bits 0-9: DAC channel1 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

Bits 16-25: DAC channel2 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

DAC Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

Bits 0-7: DAC channel1 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

Bits 16-23: DAC channel2 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

Sawtooth register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: DAC Channel 1 Sawtooth reset value.

Allowed values: 0x0-0xfff

Bit 12: DAC Channel1 Sawtooth direction setting.

Allowed values:
0: Decrement: Decrement
1: Increment: Increment

Bits 16-31: DAC CH1 Sawtooth increment value (12.4 bit format).

Allowed values: 0x0-0xffff

Sawtooth register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: DAC Channel 1 Sawtooth reset value.

Allowed values: 0x0-0xfff

Bit 12: DAC Channel1 Sawtooth direction setting.

Allowed values:
0: Decrement: Decrement
1: Increment: Increment

Bits 16-31: DAC CH1 Sawtooth increment value (12.4 bit format).

Allowed values: 0x0-0xffff

Sawtooth Mode register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-3: DAC Channel 1 Sawtooth Reset trigger selection.

Allowed values:
0: Swtrig: Software trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacReset1: hrtim_dac_reset_trg1
10: HrtimDacReset2: hrtim_dac_reset_trg2
11: HrtimDacReset3: hrtim_dac_reset_trg3
12: HrtimDacReset4: hrtim_dac_reset_trg4
13: HrtimDacReset5: hrtim_dac_reset_trg5
14: HrtimDacReset6: hrtim_dac_reset_trg6
15: HrtimDacX: hrtim_dac_trg1 (DAC1

Bits 8-11: DAC Channel 1 Sawtooth Increment trigger selection.

Allowed values:
0: Swtrig: Software sawtooth increment trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti10: EXTI line 10
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacStep1: hrtim_dac_step_trg1
10: HrtimDacStep2: hrtim_dac_step_trg2
11: HrtimDacStep3: hrtim_dac_step_trg3
12: HrtimDacStep4: hrtim_dac_step_trg4
13: HrtimDacStep5: hrtim_dac_step_trg5
14: HrtimDacStep6: hrtim_dac_step_trg6

Bits 16-19: DAC Channel 1 Sawtooth Reset trigger selection.

Allowed values:
0: Swtrig: Software trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacReset1: hrtim_dac_reset_trg1
10: HrtimDacReset2: hrtim_dac_reset_trg2
11: HrtimDacReset3: hrtim_dac_reset_trg3
12: HrtimDacReset4: hrtim_dac_reset_trg4
13: HrtimDacReset5: hrtim_dac_reset_trg5
14: HrtimDacReset6: hrtim_dac_reset_trg6
15: HrtimDacX: hrtim_dac_trg1 (DAC1

Bits 24-27: DAC Channel 2 Sawtooth Increment trigger selection.

Allowed values:
0: Swtrig: Software sawtooth increment trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti10: EXTI line 10
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacStep1: hrtim_dac_step_trg1
10: HrtimDacStep2: hrtim_dac_step_trg2
11: HrtimDacStep3: hrtim_dac_step_trg3
12: HrtimDacStep4: hrtim_dac_step_trg4
13: HrtimDacStep5: hrtim_dac_step_trg5
14: HrtimDacStep6: hrtim_dac_step_trg6

0x50000c00: Digital-to-analog converter

77/77 fields covered.

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

Bit 1: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

Bits 2-5: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

Allowed values:
0: Swtrig: Software trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacReset1: hrtim_dac_reset_trg1
10: HrtimDacReset2: hrtim_dac_reset_trg2
11: HrtimDacReset3: hrtim_dac_reset_trg3
12: HrtimDacReset4: hrtim_dac_reset_trg4
13: HrtimDacReset5: hrtim_dac_reset_trg5
14: HrtimDacReset6: hrtim_dac_reset_trg6
15: HrtimDacX: hrtim_dac_trg1 (DAC1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

Bit 14: DAC channel1 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

Bit 17: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

Bits 18-21: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)..

Allowed values:
0: Swtrig: Software trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacReset1: hrtim_dac_reset_trg1
10: HrtimDacReset2: hrtim_dac_reset_trg2
11: HrtimDacReset3: hrtim_dac_reset_trg3
12: HrtimDacReset4: hrtim_dac_reset_trg4
13: HrtimDacReset5: hrtim_dac_reset_trg5
14: HrtimDacReset6: hrtim_dac_reset_trg6
15: HrtimDacX: hrtim_dac_trg1 (DAC1

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

Bit 29: DAC channel2 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

Bit 30: DAC channel2 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

Bit 0: DAC channel1 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

Bit 1: DAC channel2 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

Bit 16: DAC channel1 software trigger B.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger for sawtooth increment

Bit 17: DAC channel2 software trigger B.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger for sawtooth increment

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel1 12-bit right-aligned data B.

Allowed values: 0x0-0xfff

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

Bits 20-31: DAC channel1 12-bit left-aligned data B.

Allowed values: 0x0-0xfff

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

Bits 8-15: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

channel2 12-bit right-aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel1 12-bit right-aligned data B.

Allowed values: 0x0-0xfff

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

Bits 20-31: DAC channel1 12-bit left-aligned data B.

Allowed values: 0x0-0xfff

channel2 8-bit right aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

Bits 8-15: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel1 data output.

Allowed values: 0x0-0xfff

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel1 data output.

Allowed values: 0x0-0xfff

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

Bit 11: DAC channel1 ready status bit.

Allowed values:
0: NotReady: DAC channelX is not yet ready to accept the trigger nor output data
1: Ready: DAC channelX is ready to accept the trigger or output data

Bit 12: DAC channel1 output register status bit.

Allowed values:
0: Dor: DOR[11:0] is used actual DAC output
1: Dorb: DORB[11:0] is used actual DAC output

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

Bit 14: DAC channel1 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

Bit 15: DAC channel1 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

Bit 27: DAC channel2 ready status bit.

Allowed values:
0: NotReady: DAC channelX is not yet ready to accept the trigger nor output data
1: Ready: DAC channelX is ready to accept the trigger or output data

Bit 28: DAC channel2 output register status bit.

Allowed values:
0: Dor: DOR[11:0] is used actual DAC output
1: Dorb: DORB[11:0] is used actual DAC output

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

Bit 30: DAC channel2 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

Bit 31: DAC channel2 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-4: DAC channel1 offset trimming value.

Allowed values: 0x0-0x1f

Bits 16-20: DAC channel2 offset trimming value.

Allowed values: 0x0-0x1f

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

Bits 0-2: DAC channel1 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

Bit 8: DAC channel1 DMA double data mode.

Allowed values:
0: Normal: DMA Normal mode selected
1: DoubleData: DMA Double data mode selected

Bit 9: Enable signed format for DAC channel1.

Allowed values:
0: Unsigned: Input data is in unsigned format
1: Signed: Input data is in signed format (2's complement). The MSB bit represents the sign.

Bits 14-15: High frequency interface mode selection.

Allowed values:
0: Disabled: High frequency interface mode disabled
1: More80Mhz: High frequency interface mode enabled for AHB clock frequency > 80 MHz
2: More160Mhz: High frequency interface mode enabled for AHB clock frequency >160 MHz

Bits 16-18: DAC channel2 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

Bit 24: DAC channel2 DMA double data mode.

Allowed values:
0: Normal: DMA Normal mode selected
1: DoubleData: DMA Double data mode selected

Bit 25: Enable signed format for DAC channel2.

Allowed values:
0: Unsigned: Input data is in unsigned format
1: Signed: Input data is in signed format (2's complement). The MSB bit represents the sign.

DAC channel1 sample and hold sample time register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-9: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

DAC channel2 sample and hold sample time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-9: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

DAC Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

Bits 0-9: DAC channel1 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

Bits 16-25: DAC channel2 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

DAC Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

Bits 0-7: DAC channel1 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

Bits 16-23: DAC channel2 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

Sawtooth register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: DAC Channel 1 Sawtooth reset value.

Allowed values: 0x0-0xfff

Bit 12: DAC Channel1 Sawtooth direction setting.

Allowed values:
0: Decrement: Decrement
1: Increment: Increment

Bits 16-31: DAC CH1 Sawtooth increment value (12.4 bit format).

Allowed values: 0x0-0xffff

Sawtooth register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

Bits 0-11: DAC Channel 1 Sawtooth reset value.

Allowed values: 0x0-0xfff

Bit 12: DAC Channel1 Sawtooth direction setting.

Allowed values:
0: Decrement: Decrement
1: Increment: Increment

Bits 16-31: DAC CH1 Sawtooth increment value (12.4 bit format).

Allowed values: 0x0-0xffff

Sawtooth Mode register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-3: DAC Channel 1 Sawtooth Reset trigger selection.

Allowed values:
0: Swtrig: Software trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacReset1: hrtim_dac_reset_trg1
10: HrtimDacReset2: hrtim_dac_reset_trg2
11: HrtimDacReset3: hrtim_dac_reset_trg3
12: HrtimDacReset4: hrtim_dac_reset_trg4
13: HrtimDacReset5: hrtim_dac_reset_trg5
14: HrtimDacReset6: hrtim_dac_reset_trg6
15: HrtimDacX: hrtim_dac_trg1 (DAC1

Bits 8-11: DAC Channel 1 Sawtooth Increment trigger selection.

Allowed values:
0: Swtrig: Software sawtooth increment trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti10: EXTI line 10
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacStep1: hrtim_dac_step_trg1
10: HrtimDacStep2: hrtim_dac_step_trg2
11: HrtimDacStep3: hrtim_dac_step_trg3
12: HrtimDacStep4: hrtim_dac_step_trg4
13: HrtimDacStep5: hrtim_dac_step_trg5
14: HrtimDacStep6: hrtim_dac_step_trg6

Bits 16-19: DAC Channel 1 Sawtooth Reset trigger selection.

Allowed values:
0: Swtrig: Software trigger
1: Tim1or8Trgo: Timer 8 (DAC1
2: Tim7Trgo: Timer 7 TRGO event
3: Tim15Trgo: Timer 15 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Tim6Trgo: Timer 6 TRGO event
8: Tim3Trgo: Timer 3 TRGO event
9: HrtimDacReset1: hrtim_dac_reset_trg1
10: HrtimDacReset2: hrtim_dac_reset_trg2
11: HrtimDacReset3: hrtim_dac_reset_trg3
12: HrtimDacReset4: hrtim_dac_reset_trg4
13: HrtimDacReset5: hrtim_dac_reset_trg5
14: HrtimDacReset6: hrtim_dac_reset_trg6
15: HrtimDacX: hrtim_dac_trg1 (DAC1