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STM32G0B0 Peripheral Coverage

118/187 fields covered.

Toggle registers CHEP[0]R

USB endpoint/channel 0 register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

11/17 fields covered.

Toggle fields EA

Bits 0-3: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction..

STATTX

Bits 4-5: Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can only be 'VALID' or 'DISABLED'. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STATTX bits to 'STALL' or 'NAK' for an isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode The STATTX bits contain the information about the channel status. Refer to for the full descriptions ('Host mode' descriptions). Whereas in Device mode, these bits contain the status that are given out on the following transaction, in Host mode they capture the status last received from the device. If a NAK is received, STATTX contains the value indicating NAK..

Allowed values:
0: Disabled: All transmission requests addressed to this endpoint/channel are ignored.
1: Stall: Device mode: the endpoint is stalled and all transmission requests result in a STALL handshake. Host mode: this indicates that the device has STALLed the channel.
2: Nak: Device mode: the endpoint is NAKed and all transmission requests result in a NAK handshake. Host mode: this indicates that the device has NAKed the transmission request.
3: Valid: This endpoint/channel is enabled for transmission.

DTOGTX

Bit 6: Data toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Device mode) If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1..

Allowed values:
1: Toggle: Flip bit

VTTX

Bit 7: Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written. Host mode Same as VTRX behavior but for USB OUT and SETUP transactions..

Allowed values:
0: Clear: Clear flag

EPKIND

Bit 8: endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints and usage in Device mode. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALL' instead of 'ACK'. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required..

UTYPE

Bits 9-10: USB type of transaction These bits configure the behavior of this endpoint/channel as described in Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of isochronous channels/endpoints is explained in transfers in Device mode.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Isochronous endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated..

STATRX

Bits 12-13: Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page2204. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can be only 'VALID' or 'DISABLED', so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to 'STALL' or 'NAK' for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate..

Allowed values:
0: Disabled: All reception requests addressed to this endpoint/channel are ignored.
1: Stall: Device mode: the endpoint is stalled and all reception requests result in a STALL handshake. Host mode: this indicates that the device has STALLed the channel.
2: Nak: Device mode: the endpoint is NAKed and all reception requests result in a NAK handshake. Host mode: this indicates that the device has NAKed the reception request.
3: Valid: This endpoint/channel is enabled for reception.

DTOGRX

Bit 14: Data Toggle, for reception transfers If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Device mode). If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1..

Allowed values:
1: Toggle: Flip bit

VTRX

Bit 15: USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. - A transaction ended with error sets this bit. Errors can be seen via the bits ERR_RX (host mode only). This bit is read/write but only 0 can be written, writing 1 has no effect..

Allowed values:
0: Clear: Clear flag

DEVADDR

Bits 16-22: Host mode Device address assigned to the endpoint during the enumeration process..

NAK

Bit 23: Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device..

Allowed values:
0: Clear: Clear flag

LS_EP

Bit 24: Low speed endpoint.

ERR_TX

Bit 25: Received error for an OUT/SETUP transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated..

Allowed values:
0: Clear: Clear flag

ERR_RX

Bit 26: Received error for an IN transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated..

Allowed values:
0: Clear: Clear flag

THREE_ERR_TX

Bits 27-28: Three errors for an OUT or SETUP transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:.

THREE_ERR_RX

Bits 29-30: Three errors for an IN transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:.

CHEP[1]R

USB endpoint/channel 1 register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

11/17 fields covered.

Toggle fields EA

STATTX

DTOGTX

Allowed values:
1: Toggle: Flip bit

VTTX

Allowed values:
0: Clear: Clear flag

EPKIND

UTYPE

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Isochronous endpoint
3: Interrupt: Interrupt endpoint

SETUP

STATRX

DTOGRX

Allowed values:
1: Toggle: Flip bit

VTRX

Allowed values:
0: Clear: Clear flag

DEVADDR

Bits 16-22: Host mode Device address assigned to the endpoint during the enumeration process..

NAK

Bit 23: Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device..

Allowed values:
0: Clear: Clear flag

LS_EP

Bit 24: Low speed endpoint.

ERR_TX

Allowed values:
0: Clear: Clear flag

ERR_RX

Allowed values:
0: Clear: Clear flag

THREE_ERR_TX

THREE_ERR_RX

CHEP[2]R

USB endpoint/channel 2 register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

11/17 fields covered.

Toggle fields EA

STATTX

DTOGTX

Allowed values:
1: Toggle: Flip bit

VTTX

Allowed values:
0: Clear: Clear flag

EPKIND

UTYPE

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Isochronous endpoint
3: Interrupt: Interrupt endpoint

SETUP

STATRX

DTOGRX

Allowed values:
1: Toggle: Flip bit

VTRX

Allowed values:
0: Clear: Clear flag

DEVADDR

Bits 16-22: Host mode Device address assigned to the endpoint during the enumeration process..

NAK

Bit 23: Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device..

Allowed values:
0: Clear: Clear flag

LS_EP

Bit 24: Low speed endpoint.

ERR_TX

Allowed values:
0: Clear: Clear flag

ERR_RX

Allowed values:
0: Clear: Clear flag

THREE_ERR_TX

THREE_ERR_RX

CHEP[3]R

USB endpoint/channel 3 register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

11/17 fields covered.

Toggle fields EA

STATTX

DTOGTX

Allowed values:
1: Toggle: Flip bit

VTTX

Allowed values:
0: Clear: Clear flag

EPKIND

UTYPE

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Isochronous endpoint
3: Interrupt: Interrupt endpoint

SETUP

STATRX

DTOGRX

Allowed values:
1: Toggle: Flip bit

VTRX

Allowed values:
0: Clear: Clear flag

DEVADDR

Bits 16-22: Host mode Device address assigned to the endpoint during the enumeration process..

NAK

Bit 23: Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device..

Allowed values:
0: Clear: Clear flag

LS_EP

Bit 24: Low speed endpoint.

ERR_TX

Allowed values:
0: Clear: Clear flag

ERR_RX

Allowed values:
0: Clear: Clear flag

THREE_ERR_TX

THREE_ERR_RX

CHEP[4]R

USB endpoint/channel 4 register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

11/17 fields covered.

Toggle fields EA

STATTX

DTOGTX

Allowed values:
1: Toggle: Flip bit

VTTX

Allowed values:
0: Clear: Clear flag

EPKIND

UTYPE

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Isochronous endpoint
3: Interrupt: Interrupt endpoint

SETUP

STATRX

DTOGRX

Allowed values:
1: Toggle: Flip bit

VTRX

Allowed values:
0: Clear: Clear flag

DEVADDR

Bits 16-22: Host mode Device address assigned to the endpoint during the enumeration process..

NAK

Bit 23: Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device..

Allowed values:
0: Clear: Clear flag

LS_EP

Bit 24: Low speed endpoint.

ERR_TX

Allowed values:
0: Clear: Clear flag

ERR_RX

Allowed values:
0: Clear: Clear flag

THREE_ERR_TX

THREE_ERR_RX

CHEP[5]R

USB endpoint/channel 5 register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

11/17 fields covered.

Toggle fields EA

STATTX

DTOGTX

Allowed values:
1: Toggle: Flip bit

VTTX

Allowed values:
0: Clear: Clear flag

EPKIND

UTYPE

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Isochronous endpoint
3: Interrupt: Interrupt endpoint

SETUP

STATRX

DTOGRX

Allowed values:
1: Toggle: Flip bit

VTRX

Allowed values:
0: Clear: Clear flag

DEVADDR

Bits 16-22: Host mode Device address assigned to the endpoint during the enumeration process..

NAK

Bit 23: Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device..

Allowed values:
0: Clear: Clear flag

LS_EP

Bit 24: Low speed endpoint.

ERR_TX

Allowed values:
0: Clear: Clear flag

ERR_RX

Allowed values:
0: Clear: Clear flag

THREE_ERR_TX

THREE_ERR_RX

CHEP[6]R

USB endpoint/channel 6 register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

11/17 fields covered.

Toggle fields EA

STATTX

DTOGTX

Allowed values:
1: Toggle: Flip bit

VTTX

Allowed values:
0: Clear: Clear flag

EPKIND

UTYPE

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Isochronous endpoint
3: Interrupt: Interrupt endpoint

SETUP

STATRX

DTOGRX

Allowed values:
1: Toggle: Flip bit

VTRX

Allowed values:
0: Clear: Clear flag

DEVADDR

Bits 16-22: Host mode Device address assigned to the endpoint during the enumeration process..

NAK

Bit 23: Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device..

Allowed values:
0: Clear: Clear flag

LS_EP

Bit 24: Low speed endpoint.

ERR_TX

Allowed values:
0: Clear: Clear flag

ERR_RX

Allowed values:
0: Clear: Clear flag

THREE_ERR_TX

THREE_ERR_RX

CHEP[7]R

USB endpoint/channel 7 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

11/17 fields covered.

Toggle fields EA

STATTX

DTOGTX

Allowed values:
1: Toggle: Flip bit

VTTX

Allowed values:
0: Clear: Clear flag

EPKIND

UTYPE

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Isochronous endpoint
3: Interrupt: Interrupt endpoint

SETUP

STATRX

DTOGRX

Allowed values:
1: Toggle: Flip bit

VTRX

Allowed values:
0: Clear: Clear flag

DEVADDR

Bits 16-22: Host mode Device address assigned to the endpoint during the enumeration process..

NAK

Bit 23: Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device..

Allowed values:
0: Clear: Clear flag

LS_EP

Bit 24: Low speed endpoint.

ERR_TX

Allowed values:
0: Clear: Clear flag

ERR_RX

Allowed values:
0: Clear: Clear flag

THREE_ERR_TX

THREE_ERR_RX

CNTR

Offset: 0x40, size: 32, reset: 0x00000003, access: Unspecified

4/17 fields covered.

Toggle fields USBRST

Bit 0: USB Reset Software can set this bit to reset the USB core, exactly as it happens when receiving a RESET signaling on the USB.The USB peripheral, in response to a RESET, resets its internal protocol state machine. Reception and transmission are disabled until the RST_DCON bit is cleared. All configuration registers do not reset: the microcontroller must explicitly clear these registers (this is to ensure that the RST_DCON interrupt can be safely delivered, and any transaction immediately followed by a RESET can be completed). The function address and endpoint registers are reset by an USB reset event. Software sets this bit to drive USB reset state on the bus and initialize the device. USB reset terminates as soon as this bit is cleared by software..

Allowed values:
0: NoEffect: No effect
1: Reset: USB core is under reset / USB reset driven

PDWN

Bit 1: Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used..

SUSPRDY

Bit 2: Suspend state effective This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wakeup logic and single ended receiver is kept alive to detect remote wakeup or resume events. Software must poll this bit to confirm it to be set before any STOP mode entry. This bit is cleared by hardware simultaneously to the WAKEUP flag being set..

SUSPEN

Bit 3: Suspend state enable Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Software can set this bit when host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set..

Allowed values:
0: NoEffect: No effect
1: Suspend: Enter L1/L2 suspend

L2RESUME

Bit 4: L2 remote wakeup / resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the host. It must be activated, according to USB specifications, for no less than 1ms and no more than 15ms after which the host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt..

L1RESUME

Bit 5: L1 remote wakeup / resume driver Device mode.

Allowed values:
0: NoEffect: No effect
1: WakeupResume: Send 50us remote-wakeup signaling to host / Send L1 resume signaling to device

L1REQM

Bit 7: LPM L1 state request interrupt mask.

ESOFM

Bit 8: Expected start of frame interrupt mask.

SOFM

Bit 9: Start of frame interrupt mask.

RST_DCONM

Bit 10: USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask.

SUSPM

Bit 11: Suspend mode interrupt mask.

WKUPM

Bit 12: Wakeup interrupt mask.

ERRM

Bit 13: Error interrupt mask.

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

CTRM

Bit 15: Correct transfer interrupt mask.

THR512M

Bit 16: 512 byte threshold interrupt mask.

HOST

Bit 31: HOST mode HOST bit selects betweens host or device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit..

ISTR

USB interrupt status register

Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

Toggle fields IDN

Bits 0-3: Device Endpoint / host channel identification number These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: two levels are defined, in order of priority: isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only..

DIR

Bit 4: Direction of transaction This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. If DIR bit=0, VTTX bit is set in the USB_CHEPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). If DIR bit=1, VTRX bit or both VTTX/VTRX are set in the USB_CHEPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. This information can be used by the application software to access the USB_CHEPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only..

Allowed values:
0: To: Data transmitted by the USB peripheral to the host PC
1: From: Data received by the USB peripheral from the host PC

L1REQ

Bit 7: LPM L1 state request Device mode This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. This bit is read/write but only 0 can be written and writing 1 has no effect..

Allowed values:
0: NotL1State: NotL1State
1: L1State: LPM command to enter the L1 state is successfully received and acknowledged

ESOF

Bit 8: Expected start of frame Device mode This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 1ms, but if the device does not receive it properly, the suspend timer issues this interrupt. If three consecutive ESOF interrupts are generated (for example three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the suspend timer is not yet locked. This bit is read/write but only 0 can be written and writing 1 has no effect..

Allowed values:
0: NotExpectedStartOfFrame: NotExpectedStartOfFrame
1: ExpectedStartOfFrame: An SOF packet is expected but not received

SOF

Bit 9: Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but only 0 can be written and writing 1 has no effect..

Allowed values:
0: NotStartOfFrame: NotStartOfFrame
1: StartOfFrame: Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus

RST_DCON

Bit 10: USB reset request (Device mode) or device connect/disconnect (Host mode) Device mode This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. Host mode This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22 cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is seen for 22 bit times consecutively from connected state..

Allowed values:
0: NotReset: NotReset
1: Reset: Peripheral detects an active USB RESET signal at its inputs

SUSP

Bit 11: Suspend mode request Device mode This bit is set by the hardware when no traffic has been received for 3ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only 0 can be written and writing 1 has no effect..

Allowed values:
0: NotSuspend: NotSuspend
1: Suspend: No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus

WKUP

Bit 12: Wakeup This bit is set to 1 by the hardware when, during suspend mode, activity is detected that wakes up the USB peripheral. This event asynchronously clears the SUSPRDY bit in the CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of the device (for example wakeup unit) about the start of the resume process. This bit is read/write but only 0 can be written and writing 1 has no effect..

Allowed values:
0: NotWakeup: NotWakeup
1: Wakeup: Activity is detected that wakes up the USB peripheral

ERR

Bit 13: Error This flag is set whenever one of the errors listed below has occurred: NANS: No ANSwer. The timeout for a host response has expired. CRC: Cyclic redundancy check error. One of the received CRCs, either in the token or in the data, was wrong. BST: Bit stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. FVIO: Framing format violation. A non-standard frame was received (EOP not in the right place, wrong token sequence, etc.). The USB software can usually ignore errors, since the USB peripheral and the PC host manage retransmission in case of errors in a fully transparent way. This interrupt can be useful during the software development phase, or to monitor the quality of transmission over the USB bus, to flag possible problems to the user (for example loose connector, too noisy environment, broken conductor in the USB cable and so on). This bit is read/write but only 0 can be written and writing 1 has no effect..

Allowed values:
0: NotError: Errors are not occurred
1: Error: One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred

PMAOVR

Bit 14: Packet memory area over / underrun This bit is set if the microcontroller has not been able to respond in time to an USB memory request. The USB peripheral handles this event in the following way: During reception an ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the transmitted stream; in both cases the host retries the transaction. The PMAOVR interrupt should never occur during normal operations. Since the failed transaction is retried by the host, the application software has the chance to speed-up device operations during this interrupt handling, to be ready for the next transaction retry; however this does not happen during isochronous transfers (no isochronous transaction is anyway retried) leading to a loss of data in this case. This bit is read/write but only 0 can be written and writing 1 has no effect..

Allowed values:
0: NotOverrun: Overrun is not occurred
1: Overrun: Microcontroller has not been able to respond in time to an USB memory request

CTR

Bit 15: Completed transfer in host mode This bit is set by the hardware to indicate that an endpoint/channel has successfully completed a transaction; using DIR and IDN bits software can determine which endpoint/channel requested the interrupt. This bit is read-only..

Allowed values:
1: Completed: Endpoint has successfully completed a transaction

THR512

Bit 16: 512 byte threshold interrupt This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no effect. Note that no information is available to indicate the associated channel/endpoint, however in practice only one ISO endpoint/channel with such large packets can be supported, so that channel..

Allowed values:
0: NotReached: 512 bytes threshold not reached
1: Reached: 512 bytes have been transmitted or received during isochronous transfers

DCON_STAT

Bit 29: Device connection status Host mode: This bit contains information about device connection status. It is set by hardware when a LS/FS device is attached to the host while it is reset when the device is disconnected..

LS_DCON

Bit 30: Low speed device connected Host mode: This bit is set by hardware when an LS device connection is detected. Device connection is signaled after LS J-state is sampled for 22 consecutive cycles of the USB clock (48MHz) from the unconnected state..

FNR

USB frame number register

Offset: 0x48, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

Toggle fields FN

Bits 0-10: Frame number This bit field contains the 11-bits frame number contained in the last received SOF packet. The frame number is incremented for every frame sent by the host and it is useful for isochronous transfers. This bit field is updated on the generation of an SOF interrupt..

LSOF

Bits 11-12: Lost SOF Device mode These bits are written by the hardware when an ESOF interrupt is generated, counting the number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are cleared..

LCK

Bit 13: Locked Device mode This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence. Once locked, the frame timer remains in this state until an USB reset or USB suspend event occurs..

RXDM

Bit 14: Receive data - line status This bit can be used to observe the status of received data minus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event..

RXDP

Bit 15: Receive data + line status This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event..

DADDR

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EF
rw ADD
rw Toggle fields ADD

Bits 0-6: Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel address (EA) field in the associated USB_CHEPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction.

Bit 7: Enable function This bit is set by the software to enable the USB Device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at 0 no transactions are handled, irrespective of the settings of USB_CHEPnR registers..

LPMCSR

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

3/4 fields covered.

Toggle fields LPMEN

Bit 0: LPM support enable Device mode This bit is set by the software to enable the LPM support within the USB Device. If this bit is at 0 no LPM transactions are handled..

LPMACK

Bit 1: LPM token acknowledge enable Device mode: The NYET/ACK is returned only on a successful LPM transaction: No errors in both the EXT token and the LPM token (else ERROR) A valid bLinkState = 0001B (L1) is received (else STALL).

Allowed values:
0: Nyet: The valid LPM Token will be NYET / NYET answer
1: Ack: The valid LPM Token will be ACK / ACK answer

REMWAKE

Bit 3: bRemoteWake value Device mode This bit contains the bRemoteWake value received with last ACKed LPM Token.

BESL

Bits 4-7: BESL value Device mode These bits contain the BESL value received with last ACKed LPM Token.

BCDR

Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified

4/9 fields covered.

Toggle fields BCDEN

Bit 0: Battery charging detector (BCD) enable Device mode This bit is set by the software to enable the BCD support within the USB Device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to 0 in order to allow the normal USB operation..

DCDEN

Bit 1: Data contact detection (DCD) mode enable Device mode This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly..

PDEN

Bit 2: Primary detection (PD) mode enable Device mode This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly..

SDEN

Bit 3: Secondary detection (SD) mode enable Device mode This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly..

DCDET

Bit 4: Data contact detection (DCD) status Device mode This bit gives the result of DCD..

PDET

Bit 5: Primary detection (PD) status Device mode This bit gives the result of PD..

SDET

Bit 6: Secondary detection (SD) status Device mode This bit gives the result of SD..

PS2DET

Bit 7: DM pull-up detection status Device mode This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification..

DPPU_DPD

Bit 15: DP pull-up / DPDM pull-down Device mode This bit is set by software to enable the embedded pull-up on DP line. Clearing it to 0 can be used to signal disconnect to the host when needed by the user software. Host mode This bit is set by software to enable the embedded pull-down on DP and DM lines..

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