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STM32F723 Peripheral Coverage

Overall: 6149/8732 fields covered

0x40012000: Analog-to-digital converter

84/84 fields covered.

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

Bit 5: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x12

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analogue watchdog interrupt disabled
1: Enabled: Analogue watchdog interrupt enabled

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: AllChannels: Analog watchdog enabled on all channels
1: SingleChannel: Analog watchdog enabled on a single channel

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

Bits 24-25: Resolution.

Allowed values:
0: TwelveBit: 12-bit (15 ADCCLK cycles)
1: TenBit: 10-bit (13 ADCCLK cycles)
2: EightBit: 8-bit (11 ADCCLK cycles)
3: SixBit: 6-bit (9 ADCCLK cycles)

Bit 26: Overrun interrupt enable.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: A/D Converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion and go to power down mode
1: Enabled: Enable ADC

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 8: Direct memory access mode (for single ADC mode).

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

Bit 9: DMA disable selection (for single ADC mode).

Allowed values:
0: Single: No new DMA request is issued after the last transfer
1: Continuous: DMA requests are issued as long as data are converted and DMA=1

Bit 10: End of conversion selection.

Allowed values:
0: EachSequence: The EOC bit is set at the end of each sequence of regular conversions
1: EachConversion: The EOC bit is set at the end of each regular conversion

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

Bits 16-19: External event select for injected group.

Allowed values:
0: TIM1TRGO: Timer 1 TRGO
1: TIM1CH4: Timer 1 CH4
2: TIM2TRGO: Timer 2 TRGO
3: TIM2CH1: Timer 2 CH1
4: TIM3CH4: Timer 3 CH4
5: TIM4TRGO: Timer 4 TRGO
7: TIM8CH4: Timer 8 CH4
8: TIM1TRGO2: Timer 1 TRGO(2)
9: TIM8TRGO: Timer 8 TRGO
10: TIM8TRGO2: Timer 8 TRGO(2)
11: TIM3CH3: Timer 3 CH3
12: TIM5TRGO: Timer 5 TRGO
13: TIM3CH1: Timer 3 CH1
14: TIM6TRGO: Timer 6 TRGO

Bits 20-21: External trigger enable for injected channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 22: Start conversion of injected channels.

Allowed values:
1: Start: Starts conversion of injected channels

Bits 24-27: External event select for regular group.

Allowed values:
0: TIM1CH1: Timer 1 CH1
1: TIM1CH2: Timer 1 CH2
2: TIM1CH3: Timer 1 CH3
3: TIM2CH2: Timer 2 CH2
4: TIM5TRGO: Timer 5 TRGO
5: TIM4CH4: Timer 4 CH4
6: TIM3CH4: Timer 3 CH4
7: TIM8TRGO: Timer 8 TRGO
8: TIM8TRGO2: Timer 8 TRGO(2)
9: TIM1TRGO: Timer 1 TRGO
10: TIM1TRGO2: Timer 1 TRGO(2)
11: TIM2TRGO: Timer 2 TRGO
12: TIM4TRGO: Timer 4 TRGO
13: TIM6TRGO: Timer 6 TRGO
15: EXTI11: EXTI line 11

Bits 28-29: External trigger enable for regular channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 30: Start conversion of regular channels.

Allowed values:
1: Start: Starts conversion of regular channels

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

injected channel data offset register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 4

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 5-9: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 10-14: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 15-19: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 20-23: Regular channel sequence length.

Allowed values: 0x0-0xf

regular sequence register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 5-9: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 10-14: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 15-19: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 20-24: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 25-29: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 5-9: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 10-14: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 15-19: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 20-24: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 25-29: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 1 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 5-9: 2 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 10-14: 3 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 15-19: 4 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 20-21: Injected sequence length.

Allowed values: 0x0-0x3

injected data register x

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Regular data.

0x40012100: Analog-to-digital converter

84/84 fields covered.

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

Bit 5: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x12

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analogue watchdog interrupt disabled
1: Enabled: Analogue watchdog interrupt enabled

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: AllChannels: Analog watchdog enabled on all channels
1: SingleChannel: Analog watchdog enabled on a single channel

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

Bits 24-25: Resolution.

Allowed values:
0: TwelveBit: 12-bit (15 ADCCLK cycles)
1: TenBit: 10-bit (13 ADCCLK cycles)
2: EightBit: 8-bit (11 ADCCLK cycles)
3: SixBit: 6-bit (9 ADCCLK cycles)

Bit 26: Overrun interrupt enable.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: A/D Converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion and go to power down mode
1: Enabled: Enable ADC

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 8: Direct memory access mode (for single ADC mode).

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

Bit 9: DMA disable selection (for single ADC mode).

Allowed values:
0: Single: No new DMA request is issued after the last transfer
1: Continuous: DMA requests are issued as long as data are converted and DMA=1

Bit 10: End of conversion selection.

Allowed values:
0: EachSequence: The EOC bit is set at the end of each sequence of regular conversions
1: EachConversion: The EOC bit is set at the end of each regular conversion

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

Bits 16-19: External event select for injected group.

Allowed values:
0: TIM1TRGO: Timer 1 TRGO
1: TIM1CH4: Timer 1 CH4
2: TIM2TRGO: Timer 2 TRGO
3: TIM2CH1: Timer 2 CH1
4: TIM3CH4: Timer 3 CH4
5: TIM4TRGO: Timer 4 TRGO
7: TIM8CH4: Timer 8 CH4
8: TIM1TRGO2: Timer 1 TRGO(2)
9: TIM8TRGO: Timer 8 TRGO
10: TIM8TRGO2: Timer 8 TRGO(2)
11: TIM3CH3: Timer 3 CH3
12: TIM5TRGO: Timer 5 TRGO
13: TIM3CH1: Timer 3 CH1
14: TIM6TRGO: Timer 6 TRGO

Bits 20-21: External trigger enable for injected channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 22: Start conversion of injected channels.

Allowed values:
1: Start: Starts conversion of injected channels

Bits 24-27: External event select for regular group.

Allowed values:
0: TIM1CH1: Timer 1 CH1
1: TIM1CH2: Timer 1 CH2
2: TIM1CH3: Timer 1 CH3
3: TIM2CH2: Timer 2 CH2
4: TIM5TRGO: Timer 5 TRGO
5: TIM4CH4: Timer 4 CH4
6: TIM3CH4: Timer 3 CH4
7: TIM8TRGO: Timer 8 TRGO
8: TIM8TRGO2: Timer 8 TRGO(2)
9: TIM1TRGO: Timer 1 TRGO
10: TIM1TRGO2: Timer 1 TRGO(2)
11: TIM2TRGO: Timer 2 TRGO
12: TIM4TRGO: Timer 4 TRGO
13: TIM6TRGO: Timer 6 TRGO
15: EXTI11: EXTI line 11

Bits 28-29: External trigger enable for regular channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 30: Start conversion of regular channels.

Allowed values:
1: Start: Starts conversion of regular channels

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

injected channel data offset register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 4

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 5-9: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 10-14: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 15-19: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 20-23: Regular channel sequence length.

Allowed values: 0x0-0xf

regular sequence register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 5-9: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 10-14: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 15-19: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 20-24: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 25-29: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 5-9: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 10-14: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 15-19: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 20-24: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 25-29: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 1 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 5-9: 2 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 10-14: 3 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 15-19: 4 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 20-21: Injected sequence length.

Allowed values: 0x0-0x3

injected data register x

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Regular data.

0x40012200: Analog-to-digital converter

84/84 fields covered.

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

Bit 5: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x12

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analogue watchdog interrupt disabled
1: Enabled: Analogue watchdog interrupt enabled

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: AllChannels: Analog watchdog enabled on all channels
1: SingleChannel: Analog watchdog enabled on a single channel

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

Bits 24-25: Resolution.

Allowed values:
0: TwelveBit: 12-bit (15 ADCCLK cycles)
1: TenBit: 10-bit (13 ADCCLK cycles)
2: EightBit: 8-bit (11 ADCCLK cycles)
3: SixBit: 6-bit (9 ADCCLK cycles)

Bit 26: Overrun interrupt enable.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: A/D Converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion and go to power down mode
1: Enabled: Enable ADC

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 8: Direct memory access mode (for single ADC mode).

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

Bit 9: DMA disable selection (for single ADC mode).

Allowed values:
0: Single: No new DMA request is issued after the last transfer
1: Continuous: DMA requests are issued as long as data are converted and DMA=1

Bit 10: End of conversion selection.

Allowed values:
0: EachSequence: The EOC bit is set at the end of each sequence of regular conversions
1: EachConversion: The EOC bit is set at the end of each regular conversion

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

Bits 16-19: External event select for injected group.

Allowed values:
0: TIM1TRGO: Timer 1 TRGO
1: TIM1CH4: Timer 1 CH4
2: TIM2TRGO: Timer 2 TRGO
3: TIM2CH1: Timer 2 CH1
4: TIM3CH4: Timer 3 CH4
5: TIM4TRGO: Timer 4 TRGO
7: TIM8CH4: Timer 8 CH4
8: TIM1TRGO2: Timer 1 TRGO(2)
9: TIM8TRGO: Timer 8 TRGO
10: TIM8TRGO2: Timer 8 TRGO(2)
11: TIM3CH3: Timer 3 CH3
12: TIM5TRGO: Timer 5 TRGO
13: TIM3CH1: Timer 3 CH1
14: TIM6TRGO: Timer 6 TRGO

Bits 20-21: External trigger enable for injected channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 22: Start conversion of injected channels.

Allowed values:
1: Start: Starts conversion of injected channels

Bits 24-27: External event select for regular group.

Allowed values:
0: TIM1CH1: Timer 1 CH1
1: TIM1CH2: Timer 1 CH2
2: TIM1CH3: Timer 1 CH3
3: TIM2CH2: Timer 2 CH2
4: TIM5TRGO: Timer 5 TRGO
5: TIM4CH4: Timer 4 CH4
6: TIM3CH4: Timer 3 CH4
7: TIM8TRGO: Timer 8 TRGO
8: TIM8TRGO2: Timer 8 TRGO(2)
9: TIM1TRGO: Timer 1 TRGO
10: TIM1TRGO2: Timer 1 TRGO(2)
11: TIM2TRGO: Timer 2 TRGO
12: TIM4TRGO: Timer 4 TRGO
13: TIM6TRGO: Timer 6 TRGO
15: EXTI11: EXTI line 11

Bits 28-29: External trigger enable for regular channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

Bit 30: Start conversion of regular channels.

Allowed values:
1: Start: Starts conversion of regular channels

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

injected channel data offset register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 4

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 5-9: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 10-14: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 15-19: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 20-23: Regular channel sequence length.

Allowed values: 0x0-0xf

regular sequence register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 5-9: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 10-14: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 15-19: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 20-24: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 25-29: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 5-9: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 10-14: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 15-19: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 20-24: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

Bits 25-29: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 1 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 5-9: 2 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 10-14: 3 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 15-19: 4 conversion in injected sequence.

Allowed values: 0x0-0x12

Bits 20-21: Injected sequence length.

Allowed values: 0x0-0x3

injected data register x

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Regular data.

0x40012300: Common ADC registers

27/27 fields covered.

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

Bit 0: Analog watchdog flag of ADC 1.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 1: End of conversion of ADC 1.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 2: Injected channel end of conversion of ADC 1.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 3: Injected channel Start flag of ADC 1.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

Bit 4: Regular channel Start flag of ADC 1.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

Bit 5: Overrun flag of ADC 1.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 8: Analog watchdog flag of ADC 2.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 9: End of conversion of ADC 2.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 10: Injected channel end of conversion of ADC 2.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 11: Injected channel Start flag of ADC 2.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

Bit 12: Regular channel Start flag of ADC 2.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

Bit 13: Overrun flag of ADC 2.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

Bit 16: Analog watchdog flag of ADC 3.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 17: End of conversion of ADC 3.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 18: Injected channel end of conversion of ADC 3.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 19: Injected channel Start flag of ADC 3.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

Bit 20: Regular channel Start flag of ADC 3.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

Bit 21: Overrun flag of ADC3.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

ADC common control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

Bits 0-4: Multi ADC mode selection.

Allowed values:
0: Independent: All the ADCs independent: independent mode
1: DualRJ: Dual ADC1 and ADC2, combined regular and injected simultaneous mode
2: DualRA: Dual ADC1 and ADC2, combined regular and alternate trigger mode
5: DualJ: Dual ADC1 and ADC2, injected simultaneous mode only
6: DualR: Dual ADC1 and ADC2, regular simultaneous mode only
7: DualI: Dual ADC1 and ADC2, interleaved mode only
9: DualA: Dual ADC1 and ADC2, alternate trigger mode only
17: TripleRJ: Triple ADC, regular and injected simultaneous mode
18: TripleRA: Triple ADC, regular and alternate trigger mode
21: TripleJ: Triple ADC, injected simultaneous mode only
22: TripleR: Triple ADC, regular simultaneous mode only
23: TripleI: Triple ADC, interleaved mode only
24: TripleA: Triple ADC, alternate trigger mode only

Bits 8-11: Delay between 2 sampling phases.

Allowed values: 0x0-0xf

Bit 13: DMA disable selection for multi-ADC mode.

Allowed values:
0: Single: No new DMA request is issued after the last transfer
1: Continuous: DMA requests are issued as long as data are converted and DMA=01, 10 or 11

Bits 14-15: Direct memory access mode for multi ADC mode.

Allowed values:
0: Disabled: DMA mode disabled
1: Mode1: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
2: Mode2: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
3: Mode3: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)

Bits 16-17: ADC prescaler.

Allowed values:
0: Div2: PCLK2 divided by 2
1: Div4: PCLK2 divided by 4
2: Div6: PCLK2 divided by 6
3: Div8: PCLK2 divided by 8

Bit 22: VBAT enable.

Allowed values:
0: Disabled: V_BAT channel disabled
1: Enabled: V_BAT channel enabled

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

ADC common regular data register for dual and triple modes

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-15: 1st data item of a pair of regular conversions.

Bits 16-31: 2nd data item of a pair of regular conversions.

0x40006400: Controller area network

82/266 fields covered.

master control register

Offset: 0x0, size: 32, reset: 0x00010002, access: read-write

0/10 fields covered.

Bit 0: INRQ.

Bit 1: SLEEP.

Bit 2: TXFP.

Bit 3: RFLM.

Bit 4: NART.

Bit 5: AWUM.

Bit 6: ABOM.

Bit 7: TTCM.

Bit 15: RESET.

Bit 16: DBF.

master status register

Offset: 0x4, size: 32, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

Bit 0: INAK.

Bit 1: SLAK.

Bit 2: ERRI.

Bit 3: WKUI.

Bit 4: SLAKI.

Bit 8: TXM.

Bit 9: RXM.

Bit 10: SAMP.

Bit 11: RX.

transmit status register

Offset: 0x8, size: 32, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

Bit 0: RQCP0.

Bit 1: TXOK0.

Bit 2: ALST0.

Bit 3: TERR0.

Bit 7: ABRQ0.

Bit 8: RQCP1.

Bit 9: TXOK1.

Bit 10: ALST1.

Bit 11: TERR1.

Bit 15: ABRQ1.

Bit 16: RQCP2.

Bit 17: TXOK2.

Bit 18: ALST2.

Bit 19: TERR2.

Bit 23: ABRQ2.

Bits 24-25: CODE.

Bit 26: Lowest priority flag for mailbox 0.

Bit 27: Lowest priority flag for mailbox 1.

Bit 28: Lowest priority flag for mailbox 2.

Bit 29: Lowest priority flag for mailbox 0.

Bit 30: Lowest priority flag for mailbox 1.

Bit 31: Lowest priority flag for mailbox 2.

receive FIFO 0 register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

Bits 0-1: FMP0.

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

receive FIFO 1 register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

Bits 0-1: FMP0.

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

interrupt enable register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

Bit 0: TMEIE.

Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set

Bit 1: FMPIE0.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

Bit 2: FFIE0.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

Bit 3: FOVIE0.

Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set

Bit 4: FMPIE1.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

Bit 5: FFIE1.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

Bit 6: FOVIE1.

Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set

Bit 8: EWGIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set

Bit 9: EPVIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set

Bit 10: BOFIE.

Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set

Bit 11: LECIE.

Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection

Bit 15: ERRIE.

Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR

Bit 16: WKUIE.

Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set

Bit 17: SLKIE.

Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set

interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

Bit 0: EWGF.

Bit 1: EPVF.

Bit 2: BOFF.

Bits 4-6: LEC.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

Bits 16-23: TEC.

Bits 24-31: REC.

bit timing register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

2/6 fields covered.

Bits 0-9: BRP.

Bits 16-19: TS1.

Bits 20-22: TS2.

Bits 24-25: SJW.

Bit 30: LBKM.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

Bit 31: SILM.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

TX mailbox identifier register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

Bit 0: TXRQ.

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

Bits 3-20: EXID.

Bits 21-31: STID.

mailbox data length control and time stamp register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

Bits 0-3: DLC.

Allowed values: 0x0-0x8

Bit 8: TGT.

Bits 16-31: TIME.

mailbox data low register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA0.

Bits 8-15: DATA1.

Bits 16-23: DATA2.

Bits 24-31: DATA3.

mailbox data high register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA4.

Bits 8-15: DATA5.

Bits 16-23: DATA6.

Bits 24-31: DATA7.

TX mailbox identifier register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

Bit 0: TXRQ.

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

Bits 3-20: EXID.

Bits 21-31: STID.

mailbox data length control and time stamp register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

Bits 0-3: DLC.

Allowed values: 0x0-0x8

Bit 8: TGT.

Bits 16-31: TIME.

mailbox data low register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA0.

Bits 8-15: DATA1.

Bits 16-23: DATA2.

Bits 24-31: DATA3.

mailbox data high register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA4.

Bits 8-15: DATA5.

Bits 16-23: DATA6.

Bits 24-31: DATA7.

TX mailbox identifier register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

Bit 0: TXRQ.

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

Bits 3-20: EXID.

Bits 21-31: STID.

mailbox data length control and time stamp register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

Bits 0-3: DLC.

Allowed values: 0x0-0x8

Bit 8: TGT.

Bits 16-31: TIME.

mailbox data low register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA0.

Bits 8-15: DATA1.

Bits 16-23: DATA2.

Bits 24-31: DATA3.

mailbox data high register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Bits 0-7: DATA4.

Bits 8-15: DATA5.

Bits 16-23: DATA6.

Bits 24-31: DATA7.

receive FIFO mailbox identifier register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

Bits 3-20: EXID.

Bits 21-31: STID.

mailbox data high register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

Bits 0-3: DLC.

Allowed values: 0x0-0x8

Bits 8-15: FMI.

Bits 16-31: TIME.

mailbox data high register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bits 0-7: DATA0.

Bits 8-15: DATA1.

Bits 16-23: DATA2.

Bits 24-31: DATA3.

receive FIFO mailbox data high register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bits 0-7: DATA4.

Bits 8-15: DATA5.

Bits 16-23: DATA6.

Bits 24-31: DATA7.

receive FIFO mailbox identifier register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

Bits 3-20: EXID.

Bits 21-31: STID.

mailbox data high register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

Bits 0-3: DLC.

Allowed values: 0x0-0x8

Bits 8-15: FMI.

Bits 16-31: TIME.

mailbox data high register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bits 0-7: DATA0.

Bits 8-15: DATA1.

Bits 16-23: DATA2.

Bits 24-31: DATA3.

receive FIFO mailbox data high register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bits 0-7: DATA4.

Bits 8-15: DATA5.

Bits 16-23: DATA6.

Bits 24-31: DATA7.

filter master register

Offset: 0x200, size: 32, reset: 0x2A1C0E01, access: read-write

0/1 fields covered.

Bit 0: FINIT.

filter mode register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bit 0: Filter mode.

Bit 1: Filter mode.

Bit 2: Filter mode.

Bit 3: Filter mode.

Bit 4: Filter mode.

Bit 5: Filter mode.

Bit 6: Filter mode.

Bit 7: Filter mode.

Bit 8: Filter mode.

Bit 9: Filter mode.

Bit 10: Filter mode.

Bit 11: Filter mode.

Bit 12: Filter mode.

Bit 13: Filter mode.

filter scale register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bit 0: Filter scale configuration.

Bit 1: Filter scale configuration.

Bit 2: Filter scale configuration.

Bit 3: Filter scale configuration.

Bit 4: Filter scale configuration.

Bit 5: Filter scale configuration.

Bit 6: Filter scale configuration.

Bit 7: Filter scale configuration.

Bit 8: Filter scale configuration.

Bit 9: Filter scale configuration.

Bit 10: Filter scale configuration.

Bit 11: Filter scale configuration.

Bit 12: Filter scale configuration.

Bit 13: Filter scale configuration.

filter FIFO assignment register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bit 0: Filter FIFO assignment for filter 0.

Bit 1: Filter FIFO assignment for filter 1.

Bit 2: Filter FIFO assignment for filter 2.

Bit 3: Filter FIFO assignment for filter 3.

Bit 4: Filter FIFO assignment for filter 4.

Bit 5: Filter FIFO assignment for filter 5.

Bit 6: Filter FIFO assignment for filter 6.

Bit 7: Filter FIFO assignment for filter 7.

Bit 8: Filter FIFO assignment for filter 8.

Bit 9: Filter FIFO assignment for filter 9.

Bit 10: Filter FIFO assignment for filter 10.

Bit 11: Filter FIFO assignment for filter 11.

Bit 12: Filter FIFO assignment for filter 12.

Bit 13: Filter FIFO assignment for filter 13.

filter activation register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

Bit 0: Filter active.

Bit 1: Filter active.

Bit 2: Filter active.

Bit 3: Filter active.

Bit 4: Filter active.

Bit 5: Filter active.

Bit 6: Filter active.

Bit 7: Filter active.

Bit 8: Filter active.

Bit 9: Filter active.

Bit 10: Filter active.

Bit 11: Filter active.

Bit 12: Filter active.

Bit 13: Filter active.

Filter bank x register 1

Offset: 0x240, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x244, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x248, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x258, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x278, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x27c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x288, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x2f8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x2fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 1

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

Filter bank x register 2

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Filter bits.

0x40023000: Cryptographic processor

10/10 fields covered.

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

Bits 0-31: Data Register.

Allowed values: 0x0-0xffffffff

Data register - half-word sized

Offset: 0x0, size: 16, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

Bits 0-15: Data register bits.

Allowed values: 0x0-0xffff

Data register - byte sized

Offset: 0x0, size: 8, reset: 0x000000FF, access: read-write

1/1 fields covered.

Bits 0-7: Data register bits.

Allowed values: 0x0-0xff

Independent Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-7: Independent Data register.

Allowed values: 0x0-0xff

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

Bit 0: RESET bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

Bits 3-4: Polynomial size.

Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial

Bits 5-6: Reverse input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

Bit 7: Reverse output data.

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

Initial CRC value

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Programmable initial CRC value.

Allowed values: 0x0-0xffffffff

CRC polynomial

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-31: Programmable polynomial.

Allowed values: 0x0-0xffffffff

0x50060000: Cryptographic processor

7/38 fields covered.

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

Bit 0: AES enable.

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

Bits 3-4: AES operating mode.

Bits 5-6: AES chaining mode.

Bit 7: Computation complete flag clear.

Bit 8: Error clear.

Bit 9: CCF flag interrupt enable.

Bit 10: Error interrupt enable.

Bit 11: Enable DMA management of data input phase.

Bit 12: Enable DMA management of data output phase.

Bits 13-14: Used only for GCM, GMAC and CMAC algorithms and has no effect when other.

Bit 18: Key size selection.

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Bit 0: Computation complete flag.

Bit 1: Read error flag.

Bit 2: Write error flag.

Bit 3: Busy flag.

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Data input.

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-31: Data output.

key register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-30: Data output register.

key register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Data output register.

key register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-30: Data output register.

key register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-31: Data output register.

initialization vector register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: initialization vector register.

initialization vector register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Initialization vector register.

initialization vector register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Initialization vector register.

initialization vector register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Initialization vector register.

key registers

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Data output register.

key registers

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Data output register.

key registers

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Data output register.

key registers

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Data output register.

Suspend registers

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: AES Suspend.

Suspend registers

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: AES Suspend.

Suspend registers

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: AES Suspend.

Suspend registers

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: IV127.

Suspend registers

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: AES Suspend.

Suspend registers

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: AES Suspend.

Suspend registers

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: AES Suspend.

Suspend registers

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: AES Suspend.

0x40007400: Digital-to-analog converter

34/34 fields covered.

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

Bit 1: DAC channel1 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

Bit 2: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

Bits 3-5: DAC channel1 trigger selection.

Allowed values:
0: Tim6Trgo: Timer 6 TRGO event
1: Tim8Trgo: Timer 8 TRGO event
2: Tim7Trgo: Timer 7 TRGO event
3: Tim5Trgo: Timer 5 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Swtrig: Software trigger

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

Bit 17: DAC channel2 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

Bit 18: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

Bits 19-21: DAC channel2 trigger selection.

Allowed values:
0: Tim6Trgo: Timer 6 TRGO event
1: Tim8Trgo: Timer 8 TRGO event
2: Tim7Trgo: Timer 7 TRGO event
3: Tim5Trgo: Timer 5 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Swtrig: Software trigger

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

Bit 29: DAC channel2 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

Bit 0: DAC channel1 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

Bit 1: DAC channel2 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

channel2 12-bit right-aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

channel2 8-bit right aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-11: DAC channel1 data output.

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-11: DAC channel1 data output.

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

0xe0042000: Debug support

2/28 fields covered.

IDCODE

Offset: 0x0, size: 32, reset: 0x10006411, access: read-only

2/2 fields covered.

Bits 0-11: DEV_ID.

Bits 16-31: REV_ID.

Control Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

Bit 0: DBG_SLEEP.

Bit 1: DBG_STOP.

Bit 2: DBG_STANDBY.

Bit 5: TRACE_IOEN.

Bits 6-7: TRACE_MODE.

Debug MCU APB1 Freeze registe

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

Bit 0: DBG_TIM2_STOP.

Bit 1: DBG_TIM3 _STOP.

Bit 2: DBG_TIM4_STOP.

Bit 3: DBG_TIM5_STOP.

Bit 4: DBG_TIM6_STOP.

Bit 5: DBG_TIM7_STOP.

Bit 6: DBG_TIM12_STOP.

Bit 7: DBG_TIM13_STOP.

Bit 8: DBG_TIM14_STOP.

Bit 11: DBG_WWDG_STOP.

Bit 12: DBG_IWDEG_STOP.

Bit 21: DBG_J2C1_SMBUS_TIMEOUT.

Bit 22: DBG_J2C2_SMBUS_TIMEOUT.

Bit 23: DBG_J2C3SMBUS_TIMEOUT.

Bit 25: DBG_CAN1_STOP.

Bit 26: DBG_CAN2_STOP.

Debug MCU APB2 Freeze registe

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

Bit 0: TIM1 counter stopped when core is halted.

Bit 1: TIM8 counter stopped when core is halted.

Bit 16: TIM9 counter stopped when core is halted.

Bit 17: TIM10 counter stopped when core is halted.

Bit 18: TIM11 counter stopped when core is halted.

0x40026000: DMA controller

272/296 fields covered.

low interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

Bit 0: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 2: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 3: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 4: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 5: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 6: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 8: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 9: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 10: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 11: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 16: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 18: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 19: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 20: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 21: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 22: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 24: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 25: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 26: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 27: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

high interrupt status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

Bit 0: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 2: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 3: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 4: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 5: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 6: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 8: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 9: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 10: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 11: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 16: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 18: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 19: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 20: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 21: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 22: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 24: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 25: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 26: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 27: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

low interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

Bit 0: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 2: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 3: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 4: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 5: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 6: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 8: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 9: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 10: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 11: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 16: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 18: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 19: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 20: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 21: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 22: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 24: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 25: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 26: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 27: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

high interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

Bit 0: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 2: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 3: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 4: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 5: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 6: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 8: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 9: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 10: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 11: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 16: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 18: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 19: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 20: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 21: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 22: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 24: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 25: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 26: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 27: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

stream x configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-28: Channel selection.

Allowed values: 0x0-0xf

stream x number of data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0x24, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

stream x configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-28: Channel selection.

Allowed values: 0x0-0xf

stream x number of data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0x3c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

stream x configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-28: Channel selection.

Allowed values: 0x0-0xf

stream x number of data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0x54, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

stream x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer