Home - News ( United States | United Kingdom | Italy | Germany ) - Football scores

Showing content from https://stm32-rs.github.io/stm32-rs/STM32F410.html below:

STM32F410 Peripheral Coverage

272/296 fields covered.

low interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

Bit 0: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 2: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 3: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 4: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 5: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 6: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 8: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 9: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 10: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 11: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 16: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 18: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 19: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 20: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 21: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 22: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 24: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 25: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 26: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 27: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

high interrupt status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

Bit 0: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 2: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 3: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 4: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 5: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 6: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 8: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 9: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 10: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 11: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 16: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 18: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 19: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 20: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 21: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

Bit 22: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

Bit 24: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

Bit 25: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

Bit 26: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

Bit 27: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

low interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

Bit 0: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 2: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 3: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 4: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 5: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 6: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 8: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 9: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 10: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 11: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 16: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 18: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 19: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 20: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 21: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 22: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 24: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 25: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 26: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 27: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

high interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

Bit 0: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 2: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 3: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 4: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 5: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 6: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 8: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 9: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 10: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 11: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 16: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 18: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 19: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 20: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 21: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

Bit 22: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

Bit 24: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

Bit 25: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

Bit 26: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

Bit 27: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

stream x configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

stream x number of data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0x24, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

stream x configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

stream x number of data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0x3c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

stream x configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

stream x number of data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0x54, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

stream x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

stream x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0x6c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

stream x configuration register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

stream x number of data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0x84, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

stream x configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

stream x number of data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0x9c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

stream x configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

stream x number of data register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0xb4, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

stream x configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

stream x number of data register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

stream x peripheral address register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

stream x memory 0 address register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 0 address.

stream x memory 1 address register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

stream x FIFO control register

Offset: 0xcc, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

RetroSearch is an open source project built by @garambo | Open a GitHub Issue

Search and Browse the WWW like it's 1997 | Search results from DuckDuckGo

HTML: 3.2 | Encoding: UTF-8 | Version: 0.7.4