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Showing content from https://stm32-rs.github.io/stm32-rs/STM32F101.html below:

STM32F101 Peripheral Coverage

Overall: 3605/4622 fields covered

0x40012400: Analog to digital converter

83/83 fields covered.

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x11

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

Bits 16-19: Dual mode selection.

Allowed values:
0: Independent: Independent mode
1: RegularInjected: Combined regular simultaneous + injected simultaneous mode
2: RegularAlternateTrigger: Combined regular simultaneous + alternate trigger mode
3: InjectedFastInterleaved: Combined injected simultaneous + fast interleaved mode
4: InjectedSlowInterleaved: Combined injected simultaneous + slow interleaved mode
5: Injected: Injected simultaneous mode only
6: Regular: Regular simultaneous mode only
7: FastInterleaved: Fast interleaved mode only
8: SlowInterleaved: Slow interleaved mode only
9: AlternateTrigger: Alternate trigger mode only

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

Bit 0: A/D converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 2: A/D calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

Bit 3: Reset calibration.

Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register

Bit 8: Direct memory access mode.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

Bit 11: Data alignment.

Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment

Bits 12-14: External event select for injected group.

Allowed values:
0: Tim1Trgo: Timer 1 TRGO event
1: Tim1Cc4: Timer 1 CC4 event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim2Cc1: Timer 2 CC1 event
4: Tim3Cc4: Timer 3 CC4 event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti15: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)
7: Jswstart: JSWSTART

Bit 15: External trigger conversion mode for injected channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

Bits 17-19: External event select for regular group.

Allowed values:
0: Tim1Cc1: Timer 1 CC1 event
1: Tim1Cc2: Timer 1 CC2 event
2: Tim1Cc3: Timer 1 CC3 event
3: Tim2Cc2: Timer 2 CC2 event
4: Tim3Trgo: Timer 3 TRGO event
5: Tim4Cc4: Timer 4 CC4 event
6: Exti11: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)
7: Swstart: SWSTART

Bit 20: External trigger conversion mode for regular channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

Bit 21: Start conversion of injected channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels

Bit 22: Start conversion of regular channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

injected channel data offset register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 4

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 13 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 5-9: 14 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 10-14: 15 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 15-19: 16 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 20-23: Regular channel sequence length.

Allowed values: 0x0-0xf

regular sequence register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 7 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 5-9: 8 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 10-14: 9 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 15-19: 10 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 20-24: 11 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 25-29: 12 conversion in regular sequence.

Allowed values: 0x0-0x11

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 1 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 5-9: 2 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 10-14: 3 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 15-19: 4 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 20-24: 5 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 25-29: 6 conversion in regular sequence.

Allowed values: 0x0-0x11

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 1 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 5-9: 2 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 10-14: 3 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 15-19: 4 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 20-21: Injected sequence length.

Allowed values: 0x0-0x3

injected data register x

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-15: Regular data.

Bits 16-31: ADC2 data.

0x40012800: Analog to digital converter

81/81 fields covered.

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x11

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

Bit 0: A/D converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 2: A/D calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

Bit 3: Reset calibration.

Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register

Bit 8: Direct memory access mode.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

Bit 11: Data alignment.

Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment

Bits 12-14: External event select for injected group.

Allowed values:
0: Tim1Trgo: Timer 1 TRGO event
1: Tim1Cc4: Timer 1 CC4 event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim2Cc1: Timer 2 CC1 event
4: Tim3Cc4: Timer 3 CC4 event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti15: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)
7: Jswstart: JSWSTART

Bit 15: External trigger conversion mode for injected channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

Bits 17-19: External event select for regular group.

Allowed values:
0: Tim1Cc1: Timer 1 CC1 event
1: Tim1Cc2: Timer 1 CC2 event
2: Tim1Cc3: Timer 1 CC3 event
3: Tim2Cc2: Timer 2 CC2 event
4: Tim3Trgo: Timer 3 TRGO event
5: Tim4Cc4: Timer 4 CC4 event
6: Exti11: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)
7: Swstart: SWSTART

Bit 20: External trigger conversion mode for regular channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

Bit 21: Start conversion of injected channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels

Bit 22: Start conversion of regular channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

injected channel data offset register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 4

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 13 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 5-9: 14 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 10-14: 15 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 15-19: 16 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 20-23: Regular channel sequence length.

Allowed values: 0x0-0xf

regular sequence register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 7 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 5-9: 8 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 10-14: 9 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 15-19: 10 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 20-24: 11 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 25-29: 12 conversion in regular sequence.

Allowed values: 0x0-0x11

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 1 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 5-9: 2 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 10-14: 3 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 15-19: 4 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 20-24: 5 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 25-29: 6 conversion in regular sequence.

Allowed values: 0x0-0x11

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 1 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 5-9: 2 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 10-14: 3 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 15-19: 4 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 20-21: Injected sequence length.

Allowed values: 0x0-0x3

injected data register x

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Regular data.

0x40013c00: Analog to digital converter

81/81 fields covered.

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x11

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

Bit 0: A/D converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

Bit 2: A/D calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

Bit 3: Reset calibration.

Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register

Bit 8: Direct memory access mode.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

Bit 11: Data alignment.

Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment

Bits 12-14: External event select for injected group.

Allowed values:
0: Tim1Trgo: Timer 1 TRGO event
1: Tim1Cc4: Timer 1 CC4 event
2: Tim4Cc3: Timer 4 CC3 event
3: Tim8Cc2: Timer 8 CC2 event
4: Tim8Cc4: Timer 8 CC4 event
5: Tim5Trgo: Timer 5 TRGO event
6: Tim5Cc4: Timer 5 CC4 event
7: Jswstart: JSWSTART

Bit 15: External trigger conversion mode for injected channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

Bits 17-19: External event select for regular group.

Allowed values:
0: Tim3Cc1: Timer 3 CC1 event
1: Tim2Cc3: Timer 2 CC3 event
2: Tim1Cc3: Timer 1 CC3 event
3: Tim8Cc1: Timer 8 CC1 event
4: Tim8Trgo: Timer 8 TRGO event
5: Tim5Cc1: Timer 5 CC1 event
6: Tim5Cc3: Timer 5 CC3 event
7: Swstart: SWSTART

Bit 20: External trigger conversion mode for regular channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

Bit 21: Start conversion of injected channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels

Bit 22: Start conversion of regular channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

injected channel data offset register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

injected channel data offset register 4

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Data offset for injected channel.

Allowed values: 0x0-0xfff

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 13 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 5-9: 14 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 10-14: 15 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 15-19: 16 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 20-23: Regular channel sequence length.

Allowed values: 0x0-0xf

regular sequence register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 7 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 5-9: 8 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 10-14: 9 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 15-19: 10 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 20-24: 11 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 25-29: 12 conversion in regular sequence.

Allowed values: 0x0-0x11

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

Bits 0-4: 1 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 5-9: 2 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 10-14: 3 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 15-19: 4 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 20-24: 5 conversion in regular sequence.

Allowed values: 0x0-0x11

Bits 25-29: 6 conversion in regular sequence.

Allowed values: 0x0-0x11

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

Bits 0-4: 1 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 5-9: 2 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 10-14: 3 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 15-19: 4 conversion in injected sequence.

Allowed values: 0x0-0x11

Bits 20-21: Injected sequence length.

Allowed values: 0x0-0x3

injected data register x

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Injected data.

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-15: Regular data.

0x40010000: Alternate function I/O

16/42 fields covered.

Event Control Register (AFIO_EVCR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

Bits 0-3: Pin selection.

Bits 4-6: Port selection.

Bit 7: Event Output Enable.

AF remap and debug I/O configuration register (AFIO_MAPR)

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

Bit 0: SPI1 remapping.

Bit 1: I2C1 remapping.

Bit 2: USART1 remapping.

Bit 3: USART2 remapping.

Bits 4-5: USART3 remapping.

Bits 6-7: TIM1 remapping.

Bits 8-9: TIM2 remapping.

Bits 10-11: TIM3 remapping.

Bit 12: TIM4 remapping.

Bits 13-14: CAN1 remapping.

Bit 15: Port D0/Port D1 mapping on OSCIN/OSCOUT.

Bit 16: Set and cleared by software.

Bit 17: ADC 1 External trigger injected conversion remapping.

Bit 18: ADC 1 external trigger regular conversion remapping.

Bit 19: ADC 2 external trigger injected conversion remapping.

Bit 20: ADC 2 external trigger regular conversion remapping.

Bits 24-26: Serial wire JTAG configuration.

External interrupt configuration register 1 (AFIO_EXTICR1)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-3: EXTI0 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 4-7: EXTI1 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 8-11: EXTI2 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 12-15: EXTI3 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

External interrupt configuration register 2 (AFIO_EXTICR2)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-3: EXTI4 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 4-7: EXTI5 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 8-11: EXTI6 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 12-15: EXTI7 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

External interrupt configuration register 3 (AFIO_EXTICR3)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-3: EXTI8 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 4-7: EXTI9 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 8-11: EXTI10 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 12-15: EXTI11 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

External interrupt configuration register 4 (AFIO_EXTICR4)

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

Bits 0-3: EXTI12 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 4-7: EXTI13 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 8-11: EXTI14 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

Bits 12-15: EXTI15 configuration.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
3: PD: Select PDx as the source input for the EXTIx external interrupt
4: PE: Select PEx as the source input for the EXTIx external interrupt
5: PF: Select PFx as the source input for the EXTIx external interrupt
6: PG: Select PGx as the source input for the EXTIx external interrupt

AF remap and debug I/O configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

Bit 5: TIM9 remapping.

Bit 6: TIM10 remapping.

Bit 7: TIM11 remapping.

Bit 8: TIM13 remapping.

Bit 9: TIM14 remapping.

Bit 10: NADV connect/disconnect.

0x40006c04: Backup registers

52/53 fields covered.

Backup data register (BKP_DR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

RTC clock calibration register (BKP_RTCCR)

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

3/4 fields covered.

Bits 0-6: Calibration value.

Allowed values: 0x0-0x79

Bit 7: Calibration Clock Output.

Bit 8: Alarm or second output enable.

Allowed values:
0: Disabled: Disabled
1: Enabled: Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit

Bit 9: Alarm or second output selection.

Allowed values:
0: Alarm: RTC Alarm pulse output selected
1: Second: RTC Second pulse output selected

Backup control register (BKP_CR)

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bit 0: Tamper pin enable.

Allowed values:
0: General: The TAMPER pin is free for general purpose I/O
1: Alternate: Tamper alternate I/O function is activated

Bit 1: Tamper pin active level.

Allowed values:
0: High: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set)
1: Low: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set)

BKP_CSR control/status register (BKP_CSR)

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

Bit 0: Clear Tamper event.

Allowed values:
1: Reset: Reset the TEF Tamper event flag (and the Tamper detector)

Bit 1: Clear Tamper Interrupt.

Allowed values:
1: Clear: Clear the Tamper interrupt and the TIF Tamper interrupt flag

Bit 2: Tamper Pin interrupt enable.

Allowed values:
0: Disabled: Tamper interrupt disabled
1: Enabled: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register

Bit 8: Tamper Event Flag.

Bit 9: Tamper Interrupt Flag.

Backup data register (BKP_DR)

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

Backup data register (BKP_DR)

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

0x40023000: CRC calculation unit

3/3 fields covered.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

Bits 0-31: Data Register.

Allowed values: 0x0-0xffffffff

Independent Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-7: Independent Data register.

Allowed values: 0x0-0xff

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

Bit 0: Reset bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

0x40007400: Digital to analog converter

30/30 fields covered.

Control register (DAC_CR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

Bit 1: DAC channel1 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

Bit 2: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

Bits 3-5: DAC channel1 trigger selection.

Allowed values:
0: Tim6Trgo: Timer 6 TRGO event
1: Tim8Trgo: Timer 8 TRGO event
2: Tim7Trgo: Timer 7 TRGO event
3: Tim5Trgo: Timer 5 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Swtrig: Software trigger

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

Bit 17: DAC channel2 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

Bit 18: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

Bits 19-21: DAC channel2 trigger selection.

Allowed values:
0: Tim6Trgo: Timer 6 TRGO event
1: Tim8Trgo: Timer 8 TRGO event
2: Tim7Trgo: Timer 7 TRGO event
3: Tim5Trgo: Timer 5 TRGO event
4: Tim2Trgo: Timer 2 TRGO event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti9: EXTI line 9
7: Swtrig: Software trigger

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DAC software trigger register (DAC_SWTRIGR)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

Bit 0: DAC channel1 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

Bit 1: DAC channel2 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

channel2 12-bit right-aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

channel2 8-bit right aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-11: DAC channel1 data output.

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

Bits 0-11: DAC channel1 data output.

0xe0042000: Debug support

2/24 fields covered.

DBGMCU_IDCODE

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

Bits 0-11: DEV_ID.

Bits 16-31: REV_ID.

DBGMCU_CR

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

Bit 0: DBG_SLEEP.

Bit 1: DBG_STOP.

Bit 2: DBG_STANDBY.

Bit 5: TRACE_IOEN.

Bits 6-7: TRACE_MODE.

Bit 8: DBG_IWDG_STOP.

Bit 9: DBG_WWDG_STOP.

Bit 10: DBG_TIM1_STOP.

Bit 11: DBG_TIM2_STOP.

Bit 12: DBG_TIM3_STOP.

Bit 13: DBG_TIM4_STOP.

Bit 15: DBG_I2C1_SMBUS_TIMEOUT.

Bit 16: DBG_I2C2_SMBUS_TIMEOUT.

Bit 18: DBG_TIM5_STOP.

Bit 19: DBG_TIM6_STOP.

Bit 20: DBG_TIM7_STOP.

Bit 22: TIM15 counter stopped when core is halted.

Bit 23: TIM16 counter stopped when core is halted.

Bit 24: TIM17 counter stopped when core is halted.

Bit 25: TIM12 counter stopped when core is halted.

Bit 26: TIM13 counter stopped when core is halted.

Bit 27: TIM14 counter stopped when core is halted.

0x40020000: DMA controller

147/161 fields covered.

DMA interrupt status register (DMA_ISR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

DMA interrupt flag clear register (DMA_IFCR)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

28/28 fields covered.

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

DMA channel configuration register (DMA_CCR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

0x40020400: DMA controller

147/161 fields covered.

DMA interrupt status register (DMA_ISR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

DMA interrupt flag clear register (DMA_IFCR)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

28/28 fields covered.

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

DMA channel configuration register (DMA_CCR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

DMA channel configuration register (DMA_CCR)

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DMA channel 1 number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

DMA channel 1 peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Peripheral address.

DMA channel 1 memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Memory address.

0x40029000: Ethernet: DMA controller operation

14/70 fields covered.

Ethernet DMA bus mode register

Offset: 0x0, size: 32, reset: 0x00020101, access: read-write

0/10 fields covered.

Bit 0: Software reset.

Bit 1: DMA Arbitration.

Bits 2-6: Descriptor skip length.

Bits 8-13: Programmable burst length.

Bits 14-15: Rx Tx priority ratio.

Bit 16: Fixed burst.

Bits 17-22: Rx DMA PBL.

Bit 23: Use separate PBL.

Bit 24: 4xPBL mode.

Bit 25: Address-aligned beats.

Ethernet DMA transmit poll demand register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Transmit poll demand.

EHERNET DMA receive poll demand register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Receive poll demand.

Ethernet DMA receive descriptor list address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Start of receive list.

Ethernet DMA transmit descriptor list address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

Bits 0-31: Start of transmit list.

Ethernet DMA status register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

6/21 fields covered.

Bit 0: Transmit status.

Bit 1: Transmit process stopped status.

Bit 2: Transmit buffer unavailable status.

Bit 3: Transmit jabber timeout status.

Bit 4: Receive overflow status.

Bit 5: Transmit underflow status.

Bit 6: Receive status.

Bit 7: Receive buffer unavailable status.

Bit 8: Receive process stopped status.

Bit 9: Receive watchdog timeout status.

Bit 10: Early transmit status.

Bit 13: Fatal bus error status.

Bit 14: Early receive status.

Bit 15: Abnormal interrupt summary.

Bit 16: Normal interrupt summary.

Bits 17-19: Receive process state.

Bits 20-22: Transmit process state.

Bits 23-25: Error bits status.

Bit 27: MMC status.

Bit 28: PMT status.

Bit 29: Time stamp trigger status.

Ethernet DMA operation mode register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

Bit 1: SR.

Bit 2: OSF.

Bits 3-4: RTC.

Bit 6: FUGF.

Bit 7: FEF.

Bit 13: ST.

Bits 14-16: TTC.

Bit 20: FTF.

Bit 21: TSF.

Bit 24: DFRF.