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Showing content from https://stm32-rs.github.io/stm32-rs/STM32F0x2.html below:

STM32F0x2 Peripheral Coverage

82/323 fields covered.

Toggle registers MCR

CAN_MCR

Offset: 0x0, size: 32, reset: 0x00010002, access: read-write

0/10 fields covered.

Toggle fields INRQ

Bit 0: INRQ.

SLEEP

Bit 1: SLEEP.

TXFP

Bit 2: TXFP.

RFLM

Bit 3: RFLM.

NART

Bit 4: NART.

AWUM

Bit 5: AWUM.

ABOM

Bit 6: ABOM.

TTCM

Bit 7: TTCM.

RESET

Bit 15: RESET.

DBF

Bit 16: DBF.

MSR

CAN_MSR

Offset: 0x4, size: 32, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

Toggle fields INAK

Bit 0: INAK.

SLAK

Bit 1: SLAK.

ERRI

Bit 2: ERRI.

WKUI

Bit 3: WKUI.

SLAKI

Bit 4: SLAKI.

TXM

Bit 8: TXM.

RXM

Bit 9: RXM.

SAMP

Bit 10: SAMP.

Bit 11: RX.

TSR

CAN_TSR

Offset: 0x8, size: 32, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

Toggle fields RQCP[0]

Bit 0: RQCP0.

TXOK[0]

Bit 1: TXOK0.

ALST[0]

Bit 2: ALST0.

TERR[0]

Bit 3: TERR0.

ABRQ[0]

Bit 7: ABRQ0.

RQCP[1]

Bit 8: RQCP1.

TXOK[1]

Bit 9: TXOK1.

ALST[1]

Bit 10: ALST1.

TERR[1]

Bit 11: TERR1.

ABRQ[1]

Bit 15: ABRQ1.

RQCP[2]

Bit 16: RQCP2.

TXOK[2]

Bit 17: TXOK2.

ALST[2]

Bit 18: ALST2.

TERR[2]

Bit 19: TERR2.

ABRQ[2]

Bit 23: ABRQ2.

CODE

Bits 24-25: CODE.

TME[0]

Bit 26: Lowest priority flag for mailbox 0.

TME[1]

Bit 27: Lowest priority flag for mailbox 1.

TME[2]

Bit 28: Lowest priority flag for mailbox 2.

LOW[0]

Bit 29: Lowest priority flag for mailbox 0.

LOW[1]

Bit 30: Lowest priority flag for mailbox 1.

LOW[2]

Bit 31: Lowest priority flag for mailbox 2.

RF[0]R

CAN_RF0R

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

Toggle fields FMP

Bits 0-1: FMP0.

FULL

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

FOVR

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

RFOM

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

RF[1]R

CAN_RF1R

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

Toggle fields FMP

Bits 0-1: FMP0.

FULL

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

FOVR

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

RFOM

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

IER

CAN_IER

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

Toggle fields TMEIE

Bit 0: TMEIE.

Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set

FMPIE0

Bit 1: FMPIE0.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE0

Bit 2: FFIE0.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE0

Bit 3: FOVIE0.

Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set

FMPIE1

Bit 4: FMPIE1.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE1

Bit 5: FFIE1.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE1

Bit 6: FOVIE1.

Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set

EWGIE

Bit 8: EWGIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set

EPVIE

Bit 9: EPVIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set

BOFIE

Bit 10: BOFIE.

Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set

LECIE

Bit 11: LECIE.

Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection

ERRIE

Bit 15: ERRIE.

Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR

WKUIE

Bit 16: WKUIE.

Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set

SLKIE

Bit 17: SLKIE.

Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set

ESR

CAN_ESR

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REC
r TEC
r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LEC
rw BOFF
r EPVF
r EWGF
r Toggle fields EWGF

Bit 0: EWGF.

EPVF

Bit 1: EPVF.

BOFF

Bit 2: BOFF.

LEC

Bits 4-6: LEC.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TEC

Bits 16-23: TEC.

REC

Bits 24-31: REC.

BTR

CAN BTR

Offset: 0x1c, size: 32, reset: 0x01230000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SILM
rw LBKM
rw SJW
rw TS2
rw TS1
rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRP
rw Toggle fields BRP

Bits 0-9: BRP.

TS1

Bits 16-19: TS1.

TS2

Bits 20-22: TS2.

SJW

Bits 24-25: SJW.

LBKM

Bit 30: LBKM.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SILM

Bit 31: SILM.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

TIR [0]

CAN_TI0R

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STID
rw EXID
rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXID
rw IDE
rw RTR
rw TXRQ
rw Toggle fields TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDTR [0]

CAN_TDT0R

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TIME
rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TGT
rw DLC
rw Toggle fields DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDLR [0]

CAN_TDL0R

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Toggle fields DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

TDHR [0]

CAN_TDH0R

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Toggle fields DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

TIR [1]

CAN_TI0R

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STID
rw EXID
rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXID
rw IDE
rw RTR
rw TXRQ
rw Toggle fields TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDTR [1]

CAN_TDT0R

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TIME
rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TGT
rw DLC
rw Toggle fields DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDLR [1]

CAN_TDL0R

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Toggle fields DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

TDHR [1]

CAN_TDH0R

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Toggle fields DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

TIR [2]

CAN_TI0R

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STID
rw EXID
rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXID
rw IDE
rw RTR
rw TXRQ
rw Toggle fields TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDTR [2]

CAN_TDT0R

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TIME
rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TGT
rw DLC
rw Toggle fields DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDLR [2]

CAN_TDL0R

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Toggle fields DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

TDHR [2]

CAN_TDH0R

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

Toggle fields DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

RIR [0]

CAN_RI0R

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STID
r EXID
r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXID
r IDE
r RTR
r Toggle fields RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

RDTR [0]

CAN_RDT0R

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TIME
r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMI
r DLC
r Toggle fields DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

FMI

Bits 8-15: FMI.

TIME

Bits 16-31: TIME.

RDLR [0]

CAN_RDL0R

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Toggle fields DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

RDHR [0]

CAN_RDH0R

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Toggle fields DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

RIR [1]

CAN_RI0R

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STID
r EXID
r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXID
r IDE
r RTR
r Toggle fields RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

RDTR [1]

CAN_RDT0R

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TIME
r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMI
r DLC
r Toggle fields DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

FMI

Bits 8-15: FMI.

TIME

Bits 16-31: TIME.

RDLR [1]

CAN_RDL0R

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Toggle fields DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

RDHR [1]

CAN_RDH0R

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

Toggle fields DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

FMR

CAN_FMR

Offset: 0x200, size: 32, reset: 0x2A1C0E01, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAN2SB
rw FINIT
rw Toggle fields FINIT

Bit 0: FINIT.

CAN2SB

Bits 8-13: CAN2SB.

FM1R

CAN_FM1R

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

Toggle fields FBM[0]

Bit 0: Filter mode.

FBM[1]

Bit 1: Filter mode.

FBM[2]

Bit 2: Filter mode.

FBM[3]

Bit 3: Filter mode.

FBM[4]

Bit 4: Filter mode.

FBM[5]

Bit 5: Filter mode.

FBM[6]

Bit 6: Filter mode.

FBM[7]

Bit 7: Filter mode.

FBM[8]

Bit 8: Filter mode.

FBM[9]

Bit 9: Filter mode.

FBM[10]

Bit 10: Filter mode.

FBM[11]

Bit 11: Filter mode.

FBM[12]

Bit 12: Filter mode.

FBM[13]

Bit 13: Filter mode.

FBM[14]

Bit 14: Filter mode.

FBM[15]

Bit 15: Filter mode.

FBM[16]

Bit 16: Filter mode.

FBM[17]

Bit 17: Filter mode.

FBM[18]

Bit 18: Filter mode.

FBM[19]

Bit 19: Filter mode.

FBM[20]

Bit 20: Filter mode.

FBM[21]

Bit 21: Filter mode.

FBM[22]

Bit 22: Filter mode.

FBM[23]

Bit 23: Filter mode.

FBM[24]

Bit 24: Filter mode.

FBM[25]

Bit 25: Filter mode.

FBM[26]

Bit 26: Filter mode.

FBM[27]

Bit 27: Filter mode.

FS1R

CAN_FS1R

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

Toggle fields FSC[0]

Bit 0: Filter scale configuration.

FSC[1]

Bit 1: Filter scale configuration.

FSC[2]

Bit 2: Filter scale configuration.

FSC[3]

Bit 3: Filter scale configuration.

FSC[4]

Bit 4: Filter scale configuration.

FSC[5]

Bit 5: Filter scale configuration.

FSC[6]

Bit 6: Filter scale configuration.

FSC[7]

Bit 7: Filter scale configuration.

FSC[8]

Bit 8: Filter scale configuration.

FSC[9]

Bit 9: Filter scale configuration.

FSC[10]

Bit 10: Filter scale configuration.

FSC[11]

Bit 11: Filter scale configuration.

FSC[12]

Bit 12: Filter scale configuration.

FSC[13]

Bit 13: Filter scale configuration.

FSC[14]

Bit 14: Filter scale configuration.

FSC[15]

Bit 15: Filter scale configuration.

FSC[16]

Bit 16: Filter scale configuration.

FSC[17]

Bit 17: Filter scale configuration.

FSC[18]

Bit 18: Filter scale configuration.

FSC[19]

Bit 19: Filter scale configuration.

FSC[20]

Bit 20: Filter scale configuration.

FSC[21]

Bit 21: Filter scale configuration.

FSC[22]

Bit 22: Filter scale configuration.

FSC[23]

Bit 23: Filter scale configuration.

FSC[24]

Bit 24: Filter scale configuration.

FSC[25]

Bit 25: Filter scale configuration.

FSC[26]

Bit 26: Filter scale configuration.

FSC[27]

Bit 27: Filter scale configuration.

FFA1R

CAN_FFA1R

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

Toggle fields FFA[0]

Bit 0: Filter FIFO assignment for filter 0.

FFA[1]

Bit 1: Filter FIFO assignment for filter 1.

FFA[2]

Bit 2: Filter FIFO assignment for filter 2.

FFA[3]

Bit 3: Filter FIFO assignment for filter 3.

FFA[4]

Bit 4: Filter FIFO assignment for filter 4.

FFA[5]

Bit 5: Filter FIFO assignment for filter 5.

FFA[6]

Bit 6: Filter FIFO assignment for filter 6.

FFA[7]

Bit 7: Filter FIFO assignment for filter 7.

FFA[8]

Bit 8: Filter FIFO assignment for filter 8.

FFA[9]

Bit 9: Filter FIFO assignment for filter 9.

FFA[10]

Bit 10: Filter FIFO assignment for filter 10.

FFA[11]

Bit 11: Filter FIFO assignment for filter 11.

FFA[12]

Bit 12: Filter FIFO assignment for filter 12.

FFA[13]

Bit 13: Filter FIFO assignment for filter 13.

FFA[14]

Bit 14: Filter FIFO assignment for filter 14.

FFA[15]

Bit 15: Filter FIFO assignment for filter 15.

FFA[16]

Bit 16: Filter FIFO assignment for filter 16.

FFA[17]

Bit 17: Filter FIFO assignment for filter 17.

FFA[18]

Bit 18: Filter FIFO assignment for filter 18.

FFA[19]

Bit 19: Filter FIFO assignment for filter 19.

FFA[20]

Bit 20: Filter FIFO assignment for filter 20.

FFA[21]

Bit 21: Filter FIFO assignment for filter 21.

FFA[22]

Bit 22: Filter FIFO assignment for filter 22.

FFA[23]

Bit 23: Filter FIFO assignment for filter 23.

FFA[24]

Bit 24: Filter FIFO assignment for filter 24.

FFA[25]

Bit 25: Filter FIFO assignment for filter 25.

FFA[26]

Bit 26: Filter FIFO assignment for filter 26.

FFA[27]

Bit 27: Filter FIFO assignment for filter 27.

FA1R

CAN_FA1R

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

Toggle fields FACT[0]

Bit 0: Filter active.

FACT[1]

Bit 1: Filter active.

FACT[2]

Bit 2: Filter active.

FACT[3]

Bit 3: Filter active.

FACT[4]

Bit 4: Filter active.

FACT[5]

Bit 5: Filter active.

FACT[6]

Bit 6: Filter active.

FACT[7]

Bit 7: Filter active.

FACT[8]

Bit 8: Filter active.

FACT[9]

Bit 9: Filter active.

FACT[10]

Bit 10: Filter active.

FACT[11]

Bit 11: Filter active.

FACT[12]

Bit 12: Filter active.

FACT[13]

Bit 13: Filter active.

FACT[14]

Bit 14: Filter active.

FACT[15]

Bit 15: Filter active.

FACT[16]

Bit 16: Filter active.

FACT[17]

Bit 17: Filter active.

FACT[18]

Bit 18: Filter active.

FACT[19]

Bit 19: Filter active.

FACT[20]

Bit 20: Filter active.

FACT[21]

Bit 21: Filter active.

FACT[22]

Bit 22: Filter active.

FACT[23]

Bit 23: Filter active.

FACT[24]

Bit 24: Filter active.

FACT[25]

Bit 25: Filter active.

FACT[26]

Bit 26: Filter active.

FACT[27]

Bit 27: Filter active.

FR1 [0]

Filter bank x register 1

Offset: 0x240, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.