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LLVM: lib/CodeGen/GlobalISel/IRTranslator.cpp Source File

(

),

MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);

(!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())

R << (

+ MF.getName() +

).str();

(TPC.isGlobalISelAbortEnabled())

DILocationVerifier() =

;

~DILocationVerifier() =

;

*getCurrentInst()

{

CurrInst; }

setCurrentInst(

*Inst) { CurrInst = Inst; }

(getCurrentInst() &&

);

<<

<<

);

(

.getParent()->isEntryBlock() && !

.getDebugLoc()) ||

(

.isDebugInstr())) &&

);

IRTranslator::allocateVRegs(

&Val) {

VRegsIt = VMap.findVRegs(Val);

(VRegsIt != VMap.vregs_end())

*VRegsIt->second;

*Regs = VMap.getVRegs(Val);

*Offsets = VMap.getOffsets(Val);

Offsets->empty() ? Offsets :

);

(

i = 0; i < SplitTys.

(); ++i)

VRegsIt = VMap.findVRegs(Val);

(VRegsIt != VMap.vregs_end())

*VRegsIt->second;

*VMap.getVRegs(Val);

*VRegs = VMap.getVRegs(Val);

*Offsets = VMap.getOffsets(Val);

);

Offsets->empty() ? Offsets :

);

(!isa<Constant>(Val)) {

(

Ty : SplitTys)

&

= cast<Constant>(Val);

(

Elt =

.getAggregateElement(

++)) {

EltRegs = getOrCreateVRegs(*Elt);

(EltRegs, std::back_inserter(*VRegs));

(SplitTys.size() == 1 &&

);

= translate(cast<Constant>(Val), VRegs->front());

<<

<<

(

, Val.

());

IRTranslator::getOrCreateFrameIndex(

&AI) {

MapEntry = FrameIndices.find(&AI);

(MapEntry != FrameIndices.end())

MapEntry->second;

ElementSize * cast<ConstantInt>(AI.

())->getZExtValue();

= std::max<uint64_t>(

, 1u);

&FI = FrameIndices[&AI];

(

*SI = dyn_cast<StoreInst>(&

))

->getAlign();

(

*LI = dyn_cast<LoadInst>(&

))

LI->getAlign();

<<

<<

(

, &

);

(

&&

);

(NewPred &&

);

MachinePreds[Edge].push_back(NewPred);

U.getType()->getScalarType()->isBFloatTy() ||

return V->getType()->getScalarType()->isBFloatTy();

IRTranslator::translateBinaryOp(

Opcode,

&U,

Op0 = getOrCreateVReg(*

.getOperand(0));

Op1 = getOrCreateVReg(*

.getOperand(1));

(isa<Instruction>(U)) {

IRTranslator::translateUnaryOp(

Opcode,

&U,

Op0 = getOrCreateVReg(*

.getOperand(0));

(isa<Instruction>(U)) {

translateUnaryOp(TargetOpcode::G_FNEG, U, MIRBuilder);

IRTranslator::translateCompare(

&U,

*CI = cast<CmpInst>(&U);

Op0 = getOrCreateVReg(*

.getOperand(0));

Op1 = getOrCreateVReg(*

.getOperand(1));

MIRBuilder.

(Pred, Res, Op0, Op1, Flags);

MIRBuilder.

(Pred, Res, Op0, Op1, Flags);

VRegs = getOrCreateVRegs(*Ret);

CLI->

(MIRBuilder, Ret, VRegs, FuncInfo, SwiftErrorVReg);

IRTranslator::emitBranchForMergedCondition(

(

*BOp = dyn_cast<CmpInst>(

)) {

Condition = InvertCond ? IC->getInversePredicate() : IC->getPredicate();

Condition = InvertCond ?

->getInversePredicate() :

->getPredicate();

BOp->getOperand(1),

,

, FBB, CurBB,

CurBuilder->getDebugLoc(), TProb, FProb);

SL->SwitchCases.push_back(CB);

,

, FBB, CurBB, CurBuilder->getDebugLoc(), TProb, FProb);

SL->SwitchCases.push_back(CB);

->getParent() == BB;

IRTranslator::findMergedConditions(

PatternMatch;

((Opc == Instruction::And || Opc == Instruction::Or) &&

);

findMergedConditions(NotCond,

, FBB, CurBB, SwitchBB, Opc, TProb, FProb,

*BOpOp0, *BOpOp1;

(BOpc == Instruction::And)

BOpc = Instruction::Or;

(BOpc == Instruction::Or)

BOpc = Instruction::And;

BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->

();

emitBranchForMergedCondition(

,

, FBB, CurBB, SwitchBB, TProb, FProb,

(Opc == Instruction::Or) {

NewTrueProb = TProb / 2;

NewFalseProb = TProb / 2 + FProb;

findMergedConditions(BOpOp0,

, TmpBB, CurBB, SwitchBB, Opc, NewTrueProb,

NewFalseProb, InvertCond);

findMergedConditions(BOpOp1,

, FBB, TmpBB, SwitchBB, Opc, Probs[0],

Probs[1], InvertCond);

(Opc == Instruction::And &&

);

NewTrueProb = TProb + FProb / 2;

NewFalseProb = FProb / 2;

findMergedConditions(BOpOp0, TmpBB, FBB, CurBB, SwitchBB, Opc, NewTrueProb,

NewFalseProb, InvertCond);

findMergedConditions(BOpOp1,

, FBB, TmpBB, SwitchBB, Opc, Probs[0],

Probs[1], InvertCond);

IRTranslator::shouldEmitAsBranches(

std::vector<SwitchCG::CaseBlock> &Cases) {

(Cases.size() != 2)

((Cases[0].CmpLHS == Cases[1].CmpLHS &&

Cases[0].CmpRHS == Cases[1].CmpRHS) ||

(Cases[0].CmpRHS == Cases[1].CmpLHS &&

Cases[0].CmpLHS == Cases[1].CmpRHS)) {

(Cases[0].CmpRHS == Cases[1].CmpRHS &&

Cases[0].PredInfo.Pred == Cases[1].PredInfo.Pred &&

isa<Constant>(Cases[0].CmpRHS) &&

cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {

Cases[0].TrueBB == Cases[1].ThisBB)

Cases[0].FalseBB == Cases[1].ThisBB)

&BrInst = cast<BranchInst>(U);

&CurMBB = MIRBuilder.

();

!CurMBB.isLayoutSuccessor(Succ0MBB))

MIRBuilder.

(*Succ0MBB);

CurMBB.addSuccessor(&getMBB(*Succ));

PatternMatch;

*CondI = dyn_cast<Instruction>(CondVal);

!BrInst.

(LLVMContext::MD_unpredictable)) {

*BOp0, *BOp1;

Opcode = Instruction::And;

Opcode = Instruction::Or;

findMergedConditions(CondI, Succ0MBB, Succ1MBB, &CurMBB, &CurMBB, Opcode,

getEdgeProbability(&CurMBB, Succ0MBB),

getEdgeProbability(&CurMBB, Succ1MBB),

(SL->SwitchCases[0].ThisBB == &CurMBB &&

);

(shouldEmitAsBranches(SL->SwitchCases)) {

emitSwitchCase(SL->SwitchCases[0], &CurMBB, *CurBuilder);

SL->SwitchCases.erase(SL->SwitchCases.begin());

(

= 1, E = SL->SwitchCases.size();

!= E; ++

)

MF->

(SL->SwitchCases[

].ThisBB);

SL->SwitchCases.clear();

, Succ0MBB, Succ1MBB, &CurMBB,

CurBuilder->getDebugLoc());

emitSwitchCase(CB, &CurMBB, *CurBuilder);

(!FuncInfo.

) {

Src->addSuccessorWithoutProb(Dst);

Prob = getEdgeProbability(Src, Dst);

Src->addSuccessor(Dst, Prob);

*SrcBB = Src->getBasicBlock();

*DstBB = Dst->getBasicBlock();

(!FuncInfo.

) {

SuccSize = std::max<uint32_t>(

(SrcBB), 1);

SwitchCG;

Clusters.reserve(

.getNumCases());

(

&

:

.cases()) {

(Succ &&

);

Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));

(Clusters.empty()) {

SL->findJumpTables(Clusters, &SI, std::nullopt, DefaultMBB,

,

);

SL->findBitTestClusters(Clusters, &SI);

() <<

;

(

CaseCluster &

: Clusters) {

(

.Kind == CC_JumpTable)

(

.Kind == CC_BitTests)

.Low->getValue().print(

(),

);

(

.Low !=

.High) {

.High->getValue().print(

(),

);

(!Clusters.empty());

DefaultProb = getEdgeProbability(SwitchMBB, DefaultMBB);

WorkList.push_back({SwitchMBB,

,

,

,

, DefaultProb});

(!WorkList.empty()) {

SwitchWorkListItem

= WorkList.pop_back_val();

NumClusters =

.LastCluster -

.FirstCluster + 1;

(NumClusters > 3 &&

splitWorkItem(WorkList, W,

.getCondition(), SwitchMBB, MIB);

(!lowerSwitchWorkItem(W,

.getCondition(), SwitchMBB, DefaultMBB, MIB))

SwitchCG;

(

.FirstCluster->Low->getValue().slt(

.LastCluster->Low->getValue()) &&

);

(

.LastCluster -

.FirstCluster + 1 >= 2 &&

);

[LastLeft, FirstRight, LeftProb, RightProb] =

SL->computeSplitWorkItemInfo(W);

(PivotCluster >

.FirstCluster);

(PivotCluster <=

.LastCluster);

(FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&

FirstLeft->Low ==

.GE &&

(FirstLeft->High->getValue() + 1LL) == Pivot->

()) {

LeftMBB = FirstLeft->MBB;

FuncInfo.

->

(BBI, LeftMBB);

{LeftMBB, FirstLeft, LastLeft,

.GE, Pivot,

.DefaultProb / 2});

(FirstRight == LastRight && FirstRight->Kind == CC_Range &&

.LT &&

(FirstRight->High->getValue() + 1ULL) ==

.LT->getValue()) {

RightMBB = FirstRight->MBB;

FuncInfo.

->

(BBI, RightMBB);

{RightMBB, FirstRight, LastRight, Pivot,

.LT,

.DefaultProb / 2});

LeftMBB, RightMBB,

.MBB, MIB.

(), LeftProb,

(

.MBB == SwitchMBB)

emitSwitchCase(CB, SwitchMBB, MIB);

SL->SwitchCases.push_back(CB);

(

.Reg &&

);

SwitchOpReg = getOrCreateVReg(SValue);

Sub = MIB.

({SwitchTy}, SwitchOpReg, FirstCst);

.Reg = Sub.getReg(0);

Cst = getOrCreateVReg(

*CI = dyn_cast<ConstantInt>(CB.

);

);

(cast<ConstantInt>(CB.

)->isMinValue(

)) {

Sub = MIB.

({CmpTy}, CmpOpReg, CondLHS);

FallthroughUnreachable) {

SwitchCG;

JumpTableHeader *JTH = &SL->JTCases[

->JTCasesIndex].first;

CurMF->

(BBI, JumpMBB);

JumpProb =

->Prob;

FallthroughProb = UnhandledProbs;

(*SI == DefaultMBB) {

JumpProb += DefaultProb / 2;

FallthroughProb -= DefaultProb / 2;

addMachineCFGPred({SwitchMBB->

(), (*SI)->getBasicBlock()},

(FallthroughUnreachable)

JTH->FallthroughUnreachable =

;

(!JTH->FallthroughUnreachable)

addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);

addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);

JTH->HeaderBB = CurMBB;

->Default = Fallthrough;

(CurMBB == SwitchMBB) {

(!emitJumpTableHeader(*JT, *JTH, CurMBB))

JTH->Emitted =

;

FallthroughUnreachable,

SwitchCG;

(

->Low ==

->High) {

CaseBlock CB(Pred, FallthroughUnreachable, LHS, RHS, MHS,

->MBB, Fallthrough,

CurMBB, MIB.

(),

->Prob, UnhandledProbs);

emitSwitchCase(CB, SwitchMBB, MIB);

SwitchOpReg = getOrCreateVReg(*

.SValue);

SwitchOpTy = MRI->

(SwitchOpReg);

RangeSub = MIB.

(SwitchOpTy, SwitchOpReg, MinValReg);

MaskTy = SwitchOpTy;

(

= 0, E =

.Cases.size();

!= E; ++

) {

(SwitchOpTy != MaskTy)

(!

.FallthroughUnreachable)

addSuccessorWithProb(SwitchBB,

.Default,

.DefaultProb);

addSuccessorWithProb(SwitchBB,

,

.Prob);

(!

.FallthroughUnreachable) {

RangeSub, RangeCst);

(PopCount == 1) {

MaskTrailingZeros =

}

(PopCount == BB.

) {

MaskTrailingOnes =

SwitchVal = MIB.

(SwitchTy, CstOne, Reg);

AndOp = MIB.

(SwitchTy, SwitchVal, CstMask);

addSuccessorWithProb(SwitchBB,

.TargetBB,

.ExtraProb);

addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);

IRTranslator::lowerBitTestWorkItem(

FallthroughUnreachable) {

SwitchCG;

BitTestBlock *BTB = &SL->BitTestCases[

->BTCasesIndex];

(BitTestCase &BTC : BTB->Cases)

CurMF->

(BBI, BTC.ThisBB);

BTB->Parent = CurMBB;

BTB->Default = Fallthrough;

BTB->DefaultProb = UnhandledProbs;

(!BTB->ContiguousRange) {

BTB->Prob += DefaultProb / 2;

BTB->DefaultProb -= DefaultProb / 2;

(FallthroughUnreachable)

BTB->FallthroughUnreachable =

;

(CurMBB == SwitchMBB) {

emitBitTestHeader(*BTB, SwitchMBB);

BTB->Emitted =

;

SwitchCG;

(++BBI != FuncInfo.

->

())

[](

CaseCluster &a,

CaseCluster &b) {

return a.Prob != b.Prob

: a.Low->getValue().slt(b.Low->getValue());

(CaseClusterIt

=

.LastCluster;

>

.FirstCluster;) {

(

->Prob >

.LastCluster->Prob)

(

->Kind == CC_Range &&

->MBB == NextMBB) {

(CaseClusterIt

=

.FirstCluster;

<=

.LastCluster; ++

)

UnhandledProbs +=

->Prob;

(CaseClusterIt

=

.FirstCluster, E =

.LastCluster;

<= E; ++

) {

FallthroughUnreachable =

;

(

==

.LastCluster) {

Fallthrough = DefaultMBB;

FallthroughUnreachable = isa<UnreachableInst>(

CurMF->

(BBI, Fallthrough);

UnhandledProbs -=

->Prob;

(

->Kind) {

(!lowerBitTestWorkItem(W, SwitchMBB, CurMBB, DefaultMBB, MIB, BBI,

DefaultProb, UnhandledProbs,

, Fallthrough,

FallthroughUnreachable)) {

(!lowerJumpTableWorkItem(W, SwitchMBB, CurMBB, DefaultMBB, MIB, BBI,

UnhandledProbs,

, Fallthrough,

FallthroughUnreachable)) {

(!lowerSwitchRangeWorkItem(

,

, Fallthrough,

FallthroughUnreachable, UnhandledProbs,

CurMBB, MIB, SwitchMBB)) {

CurMBB = Fallthrough;

IRTranslator::translateIndirectBr(

&U,

(!AddedSuccessors.

(Succ).second)

(

Arg = dyn_cast<Argument>(V))

Arg->hasSwiftErrorAttr();

(

AI = dyn_cast<AllocaInst>(V))

&LI = cast<LoadInst>(U);

(StoreSize.

())

(Regs.

() == 1 &&

);

Regs.

() == 1 ? LI.

(LLVMContext::MD_range) :

;

(

i = 0; i < Regs.

(); ++i) {

BaseAlign = getMemOpAlign(LI);

(Vals.

() == 1 &&

);

.getPointerOperand());

(

i = 0; i < Vals.

(); ++i) {

BaseAlign = getMemOpAlign(SI);

.getSyncScopeID(),

.getOrdering());

*Src = U.getOperand(0);

Indices.

(ConstantInt::get(Int32Ty, 0));

(

: EVI->indices())

}

(

*IVI = dyn_cast<InsertValueInst>(&U)) {

(

: IVI->indices())

.getIndexedOffsetInType(Src->getType(), Indices));

IRTranslator::translateExtractValue(

&U,

*Src =

.getOperand(0);

&DstRegs = allocateVRegs(U);

(

i = 0; i < DstRegs.size(); ++i)

DstRegs[i] = SrcRegs[

++];

IRTranslator::translateInsertValue(

&U,

*Src =

.getOperand(0);

&DstRegs = allocateVRegs(U);

*InsertedIt = InsertedRegs.

();

(

i = 0; i < DstRegs.size(); ++i) {

(DstOffsets[i] >=

&& InsertedIt != InsertedRegs.

())

DstRegs[i] = *InsertedIt++;

DstRegs[i] = SrcRegs[i];

IRTranslator::translateSelect(

&U,

Tst = getOrCreateVReg(*

.getOperand(0));

(

*SI = dyn_cast<SelectInst>(&U))

(

i = 0; i < ResRegs.

(); ++i) {

MIRBuilder.

(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags);

IRTranslator::translateCopy(

&U,

&V,

&Regs = *VMap.getVRegs(U);

(Regs.

()) {

Regs.push_back(Src);

VMap.getOffsets(U)->push_back(0);

IRTranslator::translateBitCast(

&U,

(isa<ConstantInt>(

.getOperand(0)))

translateCast(TargetOpcode::G_CONSTANT_FOLD_BARRIER, U,

translateCopy(U, *

.getOperand(0), MIRBuilder);

translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);

IRTranslator::translateCast(

Opcode,

&U,

(

*

= dyn_cast<Instruction>(&U))

= getOrCreateVReg(*

.getOperand(0));

IRTranslator::translateGetElementPtr(

&U,

&Op0 = *

.getOperand(0);

BaseReg = getOrCreateVReg(Op0);

(

*

= dyn_cast<Instruction>(&U))

VectorWidth = 0;

WantSplatVector =

;

(

*VT = dyn_cast<VectorType>(

.getType())) {

VectorWidth = cast<FixedVectorType>(VT)->getNumElements();

WantSplatVector = VectorWidth > 1;

(WantSplatVector && !PtrTy.

()) {

BaseReg = MIRBuilder

*

= GTI.getOperand();

(

*StTy = GTI.getStructTypeOrNull()) {

= cast<Constant>(

)->getUniqueInteger().getZExtValue();

ElementSize = GTI.getSequentialElementStride(*DL);

(

*CI = dyn_cast<ConstantInt>(

)) {

(std::optional<int64_t> Val = CI->getValue().trySExtValue()) {

+= ElementSize * *Val;

BaseReg = MIRBuilder.

(PtrTy, BaseReg, OffsetMIB.getReg(0))

(IdxTy != OffsetTy) {

(!IdxTy.

() && WantSplatVector) {

(ElementSize != 1) {

MIRBuilder.

(OffsetTy, IdxReg, ElementSizeMIB).

(0);

GepOffsetReg = IdxReg;

(int64_t(

) >= 0 && cast<GEPOperator>(U).isInBounds())

MIRBuilder.

(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0),

MIRBuilder.

(getOrCreateVReg(U), BaseReg);

IRTranslator::translateMemFunc(

&CI,

(isa<UndefValue>(SrcPtr))

MinPtrSize = UINT_MAX;

(

AI = CI.

(), AE = CI.

(); std::next(AI) != AE; ++AI) {

SrcReg = getOrCreateVReg(**AI);

MinPtrSize = std::min<unsigned>(SrcTy.

(), MinPtrSize);

(MRI->

(SizeOpReg) != SizeTy)

ICall = MIRBuilder.

(Opcode);

(

*MCI = dyn_cast<MemCpyInst>(&CI)) {

DstAlign = MCI->getDestAlign().valueOrOne();

SrcAlign = MCI->getSourceAlign().valueOrOne();

CopySize = dyn_cast<ConstantInt>(MCI->getArgOperand(2));

}

(

*MCI = dyn_cast<MemCpyInlineInst>(&CI)) {

DstAlign = MCI->getDestAlign().valueOrOne();

SrcAlign = MCI->getSourceAlign().valueOrOne();

CopySize = dyn_cast<ConstantInt>(MCI->getArgOperand(2));

}

(

*MMI = dyn_cast<MemMoveInst>(&CI)) {

DstAlign = MMI->getDestAlign().valueOrOne();

SrcAlign = MMI->getSourceAlign().valueOrOne();

CopySize = dyn_cast<ConstantInt>(MMI->getArgOperand(2));

*MSI = cast<MemSetInst>(&CI);

DstAlign = MSI->getDestAlign().valueOrOne();

(Opcode != TargetOpcode::G_MEMCPY_INLINE) {

(AA && CopySize &&

ICall.addMemOperand(

StoreFlags, 1, DstAlign, AAInfo));

(Opcode != TargetOpcode::G_MEMSET)

IRTranslator::translateTrap(

&CI,

(TrapFuncName.

()) {

(Opcode == TargetOpcode::G_UBSANTRAP) {

(Opcode == TargetOpcode::G_UBSANTRAP)

CLI->

(MIRBuilder, Info);

IRTranslator::translateVectorInterleave2Intrinsic(

);

Res = getOrCreateVReg(CI);

IRTranslator::translateVectorDeinterleave2Intrinsic(

);

IRTranslator::getStackGuard(

DstReg,

MIRBuilder.

(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {});

AddrSpace =

->getType()->getPointerAddressSpace();

MIB.setMemRefs({

});

IRTranslator::translateOverflowIntrinsic(

&CI,

,

, {ResRegs[0], ResRegs[1]},

IRTranslator::translateFixedPointIntrinsic(

,

&CI,

Dst = getOrCreateVReg(CI);

MIRBuilder.

(

, {Dst}, { Src0, Src1, Scale });

Intrinsic::acos:

TargetOpcode::G_FACOS;

Intrinsic::asin:

TargetOpcode::G_FASIN;

Intrinsic::atan:

TargetOpcode::G_FATAN;

Intrinsic::atan2:

TargetOpcode::G_FATAN2;

Intrinsic::bswap:

TargetOpcode::G_BSWAP;

Intrinsic::bitreverse:

TargetOpcode::G_BITREVERSE;

Intrinsic::fshl:

TargetOpcode::G_FSHL;

Intrinsic::fshr:

TargetOpcode::G_FSHR;

Intrinsic::ceil:

TargetOpcode::G_FCEIL;

Intrinsic::cos:

TargetOpcode::G_FCOS;

Intrinsic::cosh:

TargetOpcode::G_FCOSH;

Intrinsic::ctpop:

TargetOpcode::G_CTPOP;

Intrinsic::exp:

TargetOpcode::G_FEXP;

Intrinsic::exp2:

TargetOpcode::G_FEXP2;

Intrinsic::exp10:

TargetOpcode::G_FEXP10;

Intrinsic::fabs:

TargetOpcode::G_FABS;

Intrinsic::copysign:

TargetOpcode::G_FCOPYSIGN;

Intrinsic::minnum:

TargetOpcode::G_FMINNUM;

Intrinsic::maxnum:

TargetOpcode::G_FMAXNUM;

Intrinsic::minimum:

TargetOpcode::G_FMINIMUM;

Intrinsic::maximum:

TargetOpcode::G_FMAXIMUM;

Intrinsic::canonicalize:

TargetOpcode::G_FCANONICALIZE;

Intrinsic::floor:

TargetOpcode::G_FFLOOR;

Intrinsic::fma:

TargetOpcode::G_FMA;

Intrinsic::log:

TargetOpcode::G_FLOG;

Intrinsic::log2:

TargetOpcode::G_FLOG2;

Intrinsic::log10:

TargetOpcode::G_FLOG10;

Intrinsic::ldexp:

TargetOpcode::G_FLDEXP;

Intrinsic::nearbyint:

TargetOpcode::G_FNEARBYINT;

Intrinsic::pow:

TargetOpcode::G_FPOW;

Intrinsic::powi:

TargetOpcode::G_FPOWI;

Intrinsic::rint:

TargetOpcode::G_FRINT;

Intrinsic::round:

TargetOpcode::G_INTRINSIC_ROUND;

Intrinsic::roundeven:

TargetOpcode::G_INTRINSIC_ROUNDEVEN;

Intrinsic::sin:

TargetOpcode::G_FSIN;

Intrinsic::sinh:

TargetOpcode::G_FSINH;

Intrinsic::sqrt:

TargetOpcode::G_FSQRT;

Intrinsic::tan:

TargetOpcode::G_FTAN;

Intrinsic::tanh:

TargetOpcode::G_FTANH;

Intrinsic::trunc:

TargetOpcode::G_INTRINSIC_TRUNC;

Intrinsic::readcyclecounter:

TargetOpcode::G_READCYCLECOUNTER;

Intrinsic::readsteadycounter:

TargetOpcode::G_READSTEADYCOUNTER;

Intrinsic::ptrmask:

TargetOpcode::G_PTRMASK;

Intrinsic::lrint:

TargetOpcode::G_INTRINSIC_LRINT;

Intrinsic::llrint:

TargetOpcode::G_INTRINSIC_LLRINT;

Intrinsic::vector_reduce_fmin:

TargetOpcode::G_VECREDUCE_FMIN;

Intrinsic::vector_reduce_fmax:

TargetOpcode::G_VECREDUCE_FMAX;

Intrinsic::vector_reduce_fminimum:

TargetOpcode::G_VECREDUCE_FMINIMUM;

Intrinsic::vector_reduce_fmaximum:

TargetOpcode::G_VECREDUCE_FMAXIMUM;

Intrinsic::vector_reduce_add:

TargetOpcode::G_VECREDUCE_ADD;

Intrinsic::vector_reduce_mul:

TargetOpcode::G_VECREDUCE_MUL;

Intrinsic::vector_reduce_and:

TargetOpcode::G_VECREDUCE_AND;

Intrinsic::vector_reduce_or:

TargetOpcode::G_VECREDUCE_OR;

Intrinsic::vector_reduce_xor:

TargetOpcode::G_VECREDUCE_XOR;

Intrinsic::vector_reduce_smax:

TargetOpcode::G_VECREDUCE_SMAX;

Intrinsic::vector_reduce_smin:

TargetOpcode::G_VECREDUCE_SMIN;

Intrinsic::vector_reduce_umax:

TargetOpcode::G_VECREDUCE_UMAX;

Intrinsic::vector_reduce_umin:

TargetOpcode::G_VECREDUCE_UMIN;

Intrinsic::experimental_vector_compress:

TargetOpcode::G_VECTOR_COMPRESS;

Intrinsic::lround:

TargetOpcode::G_LROUND;

Intrinsic::llround:

TargetOpcode::G_LLROUND;

Intrinsic::get_fpenv:

TargetOpcode::G_GET_FPENV;

Intrinsic::get_fpmode:

TargetOpcode::G_GET_FPMODE;

IRTranslator::translateSimpleIntrinsic(

&CI,

= getSimpleIntrinsicOpcode(

);

(

&Arg : CI.

())

VRegs.

(getOrCreateVReg(*Arg));

MIRBuilder.

(

, {getOrCreateVReg(CI)}, VRegs,

Intrinsic::experimental_constrained_fadd:

TargetOpcode::G_STRICT_FADD;

Intrinsic::experimental_constrained_fsub:

TargetOpcode::G_STRICT_FSUB;

Intrinsic::experimental_constrained_fmul:

TargetOpcode::G_STRICT_FMUL;

Intrinsic::experimental_constrained_fdiv:

TargetOpcode::G_STRICT_FDIV;

Intrinsic::experimental_constrained_frem:

TargetOpcode::G_STRICT_FREM;

Intrinsic::experimental_constrained_fma:

TargetOpcode::G_STRICT_FMA;

Intrinsic::experimental_constrained_sqrt:

TargetOpcode::G_STRICT_FSQRT;

Intrinsic::experimental_constrained_ldexp:

TargetOpcode::G_STRICT_FLDEXP;

IRTranslator::translateConstrainedFPIntrinsic(

MIRBuilder.

(Opcode, {getOrCreateVReg(FPI)}, VRegs,

);

std::optional<MCRegister> IRTranslator::getArgPhysReg(

&Arg) {

VRegs = getOrCreateVRegs(Arg);

(VRegs.

() != 1)

std::nullopt;

(!VRegDef || !VRegDef->isCopy())

std::nullopt;

IRTranslator::translateIfEntryValueArgument(

isDeclare,

*Val,

*Arg = dyn_cast<Argument>(Val);

std::optional<MCRegister> PhysReg = getArgPhysReg(*Arg);

(

() <<

<< (isDeclare ?

:

)

<<

<<

);

Intrinsic::experimental_convergence_anchor:

TargetOpcode::CONVERGENCECTRL_ANCHOR;

Intrinsic::experimental_convergence_entry:

TargetOpcode::CONVERGENCECTRL_ENTRY;

Intrinsic::experimental_convergence_loop:

TargetOpcode::CONVERGENCECTRL_LOOP;

IRTranslator::translateConvergenceControlIntrinsic(

OutputReg = getOrCreateConvergenceTokenVReg(CI);

(

== Intrinsic::experimental_convergence_loop) {

(Bundle &&

);

getOrCreateConvergenceTokenVReg(*Bundle->Inputs[0].get());

(

*

= dyn_cast<AnyMemIntrinsic>(&CI)) {

(ORE->enabled()) {

(*ORE,

, *DL, *LibInfo);

(translateSimpleIntrinsic(CI,

, MIRBuilder))

Intrinsic::lifetime_start:

Intrinsic::lifetime_end: {

=

== Intrinsic::lifetime_start ? TargetOpcode::LIFETIME_START

: TargetOpcode::LIFETIME_END;

(

*V : Allocas) {

*AI = dyn_cast<AllocaInst>(V);

Intrinsic::fake_use: {

(

&Arg : CI.

())

(

VReg : getOrCreateVRegs(*Arg))

MIRBuilder.

(TargetOpcode::FAKE_USE, {}, VRegs);

Intrinsic::dbg_declare: {

Intrinsic::dbg_label: {

);

Intrinsic::vaend:

Intrinsic::vastart: {

MIRBuilder.

(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*

)})

ListSize, Alignment));

Intrinsic::dbg_assign:

Intrinsic::dbg_value: {

Intrinsic::uadd_with_overflow:

translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);

Intrinsic::sadd_with_overflow:

translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);

Intrinsic::usub_with_overflow:

translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);

Intrinsic::ssub_with_overflow:

translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);

Intrinsic::umul_with_overflow:

translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);

Intrinsic::smul_with_overflow:

translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);

Intrinsic::uadd_sat:

translateBinaryOp(TargetOpcode::G_UADDSAT, CI, MIRBuilder);

Intrinsic::sadd_sat:

translateBinaryOp(TargetOpcode::G_SADDSAT, CI, MIRBuilder);

Intrinsic::usub_sat:

translateBinaryOp(TargetOpcode::G_USUBSAT, CI, MIRBuilder);

Intrinsic::ssub_sat:

translateBinaryOp(TargetOpcode::G_SSUBSAT, CI, MIRBuilder);

Intrinsic::ushl_sat:

translateBinaryOp(TargetOpcode::G_USHLSAT, CI, MIRBuilder);

Intrinsic::sshl_sat:

translateBinaryOp(TargetOpcode::G_SSHLSAT, CI, MIRBuilder);

Intrinsic::umin:

translateBinaryOp(TargetOpcode::G_UMIN, CI, MIRBuilder);

Intrinsic::umax:

translateBinaryOp(TargetOpcode::G_UMAX, CI, MIRBuilder);

Intrinsic::smin:

translateBinaryOp(TargetOpcode::G_SMIN, CI, MIRBuilder);

Intrinsic::smax:

translateBinaryOp(TargetOpcode::G_SMAX, CI, MIRBuilder);

Intrinsic::abs:

translateUnaryOp(TargetOpcode::G_ABS, CI, MIRBuilder);

Intrinsic::smul_fix:

translateFixedPointIntrinsic(TargetOpcode::G_SMULFIX, CI, MIRBuilder);

Intrinsic::umul_fix:

translateFixedPointIntrinsic(TargetOpcode::G_UMULFIX, CI, MIRBuilder);

Intrinsic::smul_fix_sat:

translateFixedPointIntrinsic(TargetOpcode::G_SMULFIXSAT, CI, MIRBuilder);

Intrinsic::umul_fix_sat:

translateFixedPointIntrinsic(TargetOpcode::G_UMULFIXSAT, CI, MIRBuilder);

Intrinsic::sdiv_fix:

translateFixedPointIntrinsic(TargetOpcode::G_SDIVFIX, CI, MIRBuilder);

Intrinsic::udiv_fix:

translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIX, CI, MIRBuilder);

Intrinsic::sdiv_fix_sat:

translateFixedPointIntrinsic(TargetOpcode::G_SDIVFIXSAT, CI, MIRBuilder);

Intrinsic::udiv_fix_sat:

translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIXSAT, CI, MIRBuilder);

Intrinsic::fmuladd: {

Dst = getOrCreateVReg(CI);

MIRBuilder.

(Dst, Op0, Op1, Op2,

Intrinsic::convert_from_fp16:

Intrinsic::convert_to_fp16:

Intrinsic::frexp: {

Intrinsic::sincos: {

Intrinsic::fptosi_sat:

Intrinsic::fptoui_sat:

Intrinsic::memcpy_inline:

translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMCPY_INLINE);

Intrinsic::memcpy:

translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMCPY);

Intrinsic::memmove:

translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMMOVE);

Intrinsic::memset:

translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMSET);

Intrinsic::eh_typeid_for: {

Intrinsic::objectsize:

Intrinsic::is_constant:

(

);

Intrinsic::stackguard:

getStackGuard(getOrCreateVReg(CI), MIRBuilder);

Intrinsic::stackprotector: {

getStackGuard(GuardVal, MIRBuilder);

FI = getOrCreateFrameIndex(*Slot);

GuardVal, getOrCreateVReg(*Slot),

Intrinsic::stacksave: {

MIRBuilder.

(TargetOpcode::G_STACKSAVE, {getOrCreateVReg(CI)}, {});

Intrinsic::stackrestore: {

MIRBuilder.

(TargetOpcode::G_STACKRESTORE, {},

Intrinsic::cttz:

Intrinsic::ctlz: {

isTrailing =

== Intrinsic::cttz;

Opcode = isTrailing

? Cst->

() ? TargetOpcode::G_CTTZ

: TargetOpcode::G_CTTZ_ZERO_UNDEF

: Cst->

() ? TargetOpcode::G_CTLZ

: TargetOpcode::G_CTLZ_ZERO_UNDEF;

MIRBuilder.

(Opcode, {getOrCreateVReg(CI)},

Intrinsic::invariant_start: {

Intrinsic::invariant_end:

Intrinsic::expect:

Intrinsic::expect_with_probability:

Intrinsic::annotation:

Intrinsic::ptr_annotation:

Intrinsic::launder_invariant_group:

Intrinsic::strip_invariant_group: {

MIRBuilder.

(getOrCreateVReg(CI),

Intrinsic::assume:

Intrinsic::experimental_noalias_scope_decl:

Intrinsic::var_annotation:

Intrinsic::sideeffect:

Intrinsic::read_volatile_register:

Intrinsic::read_register: {

.

(TargetOpcode::G_READ_REGISTER, {getOrCreateVReg(CI)}, {})

.addMetadata(cast<MDNode>(cast<MetadataAsValue>(Arg)->getMetadata()));

Intrinsic::write_register: {

MIRBuilder.

(TargetOpcode::G_WRITE_REGISTER)

.

(cast<MDNode>(cast<MetadataAsValue>(Arg)->getMetadata()))

Intrinsic::localescape: {

(isa<ConstantPointerNull>(Arg))

FI = getOrCreateFrameIndex(*cast<AllocaInst>(Arg));

EntryMBB.

(EntryMBB.

(), LocalEscape);

Intrinsic::vector_reduce_fadd:

Intrinsic::vector_reduce_fmul: {

Dst = getOrCreateVReg(CI);

Opc =

== Intrinsic::vector_reduce_fadd

? TargetOpcode::G_VECREDUCE_SEQ_FADD

: TargetOpcode::G_VECREDUCE_SEQ_FMUL;

MIRBuilder.

(Opc, {Dst}, {ScalarSrc, VecSrc},

(

== Intrinsic::vector_reduce_fadd) {

Opc = TargetOpcode::G_VECREDUCE_FADD;

ScalarOpc = TargetOpcode::G_FADD;

Opc = TargetOpcode::G_VECREDUCE_FMUL;

ScalarOpc = TargetOpcode::G_FMUL;

MIRBuilder.

(ScalarOpc, {Dst}, {ScalarSrc, Rdx},

Intrinsic::trap:

translateTrap(CI, MIRBuilder, TargetOpcode::G_TRAP);

Intrinsic::debugtrap:

translateTrap(CI, MIRBuilder, TargetOpcode::G_DEBUGTRAP);

Intrinsic::ubsantrap:

translateTrap(CI, MIRBuilder, TargetOpcode::G_UBSANTRAP);

Intrinsic::allow_runtime_check:

Intrinsic::allow_ubsan_check:

MIRBuilder.

(getOrCreateVReg(CI),

Intrinsic::amdgcn_cs_chain:

translateCallBase(CI, MIRBuilder);

Intrinsic::fptrunc_round: {

std::optional<RoundingMode> RoundMode =

.

(TargetOpcode::G_INTRINSIC_FPTRUNC_ROUND,

{getOrCreateVReg(CI)},

.addImm((

)*RoundMode);

Intrinsic::is_fpclass: {

.

(TargetOpcode::G_IS_FPCLASS, {getOrCreateVReg(CI)},

{getOrCreateVReg(*FpValue)})

Intrinsic::set_fpenv: {

Intrinsic::reset_fpenv:

Intrinsic::set_fpmode: {

Intrinsic::reset_fpmode:

Intrinsic::vscale: {

Intrinsic::scmp:

MIRBuilder.

(getOrCreateVReg(CI),

Intrinsic::ucmp:

MIRBuilder.

(getOrCreateVReg(CI),

Intrinsic::vector_extract:

translateExtractVector(CI, MIRBuilder);

Intrinsic::vector_insert:

translateInsertVector(CI, MIRBuilder);

Intrinsic::stepvector: {

Intrinsic::prefetch: {

RW = cast<ConstantInt>(CI.

(1))->getZExtValue();

Locality = cast<ConstantInt>(CI.

(2))->getZExtValue();

CacheType = cast<ConstantInt>(CI.

(3))->getZExtValue();

Intrinsic::vector_interleave2:

Intrinsic::vector_deinterleave2: {

translateVectorInterleave2Intrinsic(CI, MIRBuilder);

translateVectorDeinterleave2Intrinsic(CI, MIRBuilder);

translateConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(CI),

Intrinsic::experimental_convergence_anchor:

Intrinsic::experimental_convergence_entry:

Intrinsic::experimental_convergence_loop:

translateConvergenceControlIntrinsic(CI,

, MIRBuilder);

IRTranslator::translateInlineAsm(

&CB,

() <<

);

MIRBuilder, CB, [&](

&Val) {

getOrCreateVRegs(Val); });

IRTranslator::translateCallBase(

&CB,

(

&Arg : CB.

()) {

(SwiftInVReg == 0 &&

);

&CB, &MIRBuilder.

(), Arg));

.push_back(getOrCreateVRegs(*Arg));

(

*CI = dyn_cast<CallInst>(&CB)) {

(ORE->enabled()) {

(*ORE,

, *DL, *LibInfo);

std::optional<CallLowering::PtrAuthInfo> PAI;

*

= Bundle->Inputs[0];

*CalleeCPA = dyn_cast<ConstantPtrAuth>(CB.

());

(!CalleeCPA || !isa<Function>(CalleeCPA->getPointer()) ||

!CalleeCPA->isKnownCompatibleWith(Key, Discriminator, *DL)) {

DiscReg = getOrCreateVReg(*Discriminator);

&Token = *Bundle->Inputs[0].get();

ConvergenceCtrlToken = getOrCreateConvergenceTokenVReg(Token);

MIRBuilder, CB, Res, Args, SwiftErrorVReg, PAI, ConvergenceCtrlToken,

(!HasTailCall &&

);

&CI = cast<CallInst>(U);

(

&& (

->hasDLLImportStorageClass() ||

->hasExternalWeakLinkage())))

(isa<GCStatepointInst, GCRelocateInst, GCResultInst>(U))

translateInlineAsm(CI, MIRBuilder);

(

&&

->isIntrinsic()) {

=

->getIntrinsicID();

translateCallBase(CI, MIRBuilder);

(translateKnownIntrinsic(CI,

, MIRBuilder))

ResultRegs = getOrCreateVRegs(CI);

(isa<FPMathOperator>(CI))

(CI.

(Arg.index(), Attribute::ImmArg)) {

(

*CI = dyn_cast<ConstantInt>(Arg.value())) {

(CI->getBitWidth() <= 64 &&

);

MIB.

(CI->getSExtValue());

MIB.

(cast<ConstantFP>(Arg.value()));

}

(

*MDVal = dyn_cast<MetadataAsValue>(Arg.value())) {

*MD = MDVal->getMetadata();

*MDN = dyn_cast<MDNode>(MD);

(

*ConstMD = dyn_cast<ConstantAsMetadata>(MD))

(VRegs.

() > 1)

->getABITypeAlign(

.memVT.getTypeForEVT(

->getContext())));

MemTy =

.memVT.isSimple()

:

::scalar(

.memVT.getStoreSizeInBits());

(

.fallbackAddressSpace)

*Token = Bundle->Inputs[0].get();

TokenReg = getOrCreateVReg(*Token);

IRTranslator::findUnwindDestinations(

(isa<LandingPadInst>(Pad)) {

UnwindDests.emplace_back(&getMBB(*EHPadBB), Prob);

(isa<CleanupPadInst>(Pad)) {

UnwindDests.emplace_back(&getMBB(*EHPadBB), Prob);

UnwindDests.

().first->setIsEHScopeEntry();

UnwindDests.back().first->setIsEHFuncletEntry();

(

*CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {

(

*CatchPadBB : CatchSwitch->handlers()) {

UnwindDests.emplace_back(&getMBB(*CatchPadBB), Prob);

(IsMSVCCXX || IsCoreCLR)

UnwindDests.back().first->setIsEHFuncletEntry();

UnwindDests.back().first->setIsEHScopeEntry();

NewEHPadBB = CatchSwitch->getUnwindDest();

(BPI && NewEHPadBB)

EHPadBB = NewEHPadBB;

IRTranslator::translateInvoke(

&U,

*Fn =

.getCalledFunction();

(

.hasDeoptState())

LowerInlineAsm =

.isInlineAsm();

NeedEHLabel =

;

MIRBuilder.

(TargetOpcode::G_INVOKE_REGION_START);

(LowerInlineAsm) {

(!translateInlineAsm(

, MIRBuilder))

}

(!translateCallBase(

, MIRBuilder))

(!findUnwindDestinations(EHPadBB, EHPadBBProb, UnwindDests))

&ReturnMBB = getMBB(*ReturnBB);

addSuccessorWithProb(InvokeMBB, &ReturnMBB);

(

&UnwindDest : UnwindDests) {

UnwindDest.first->setIsEHPad();

addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);

(BeginSymbol &&

);

(EndSymbol &&

);

MF->

(&EHPadMBB, BeginSymbol, EndSymbol);

MIRBuilder.

(ReturnMBB);

IRTranslator::translateCallBr(

&U,

IRTranslator::translateLandingPad(

&U,

MIRBuilder.

(TargetOpcode::EH_LABEL)

(

*RegMask =

.getCustomEHPadPreservedMask(*MF))

(

*Ty : cast<StructType>(LP.

())->elements())

(

.size() == 2 &&

);

MIRBuilder.

(ResRegs[0], ExceptionReg);

MIRBuilder.

(PtrVReg, SelectorReg);

MIRBuilder.

(ResRegs[1], PtrVReg);

IRTranslator::translateAlloca(

&U,

&AI = cast<AllocaInst>(U);

Res = getOrCreateVReg(AI);

FI = getOrCreateFrameIndex(AI);

(MRI->

(NumElts) != IntPtrTy) {

getOrCreateVReg(*ConstantInt::get(IntPtrIRTy,

->getTypeAllocSize(Ty)));

MIRBuilder.

(AllocSize, NumElts, TySize);

AllocAdd = MIRBuilder.

(IntPtrTy, AllocSize, SAMinusOne,

AlignedAlloc = MIRBuilder.

(IntPtrTy, AllocAdd, AlignCst);

Alignment = std::max(AI.

(),

->getPrefTypeAlign(Ty));

(Alignment <= StackAlign)

Alignment =

(1);

MIRBuilder.

(TargetOpcode::G_VAARG, {getOrCreateVReg(U)},

{getOrCreateVReg(*

.getOperand(0)),

->getABITypeAlign(

.getType()).value()});

&UI = cast<UnreachableInst>(U);

(

*Call = dyn_cast_or_null<CallInst>(UI.getPrevNode());

Call &&

->doesNotReturn()) {

(

->isNonContinuableTrap())

IRTranslator::translateInsertElement(

&U,

(

*FVT = dyn_cast<FixedVectorType>(

.getType());

FVT && FVT->getNumElements() == 1)

translateCopy(U, *

.getOperand(1), MIRBuilder);

Val = getOrCreateVReg(*

.getOperand(0));

Elt = getOrCreateVReg(*

.getOperand(1));

(

*CI = dyn_cast<ConstantInt>(

.getOperand(2))) {

(CI->getBitWidth() != PreferredVecIdxWidth) {

NewIdx = CI->getValue().zextOrTrunc(PreferredVecIdxWidth);

*NewIdxCI = ConstantInt::get(CI->

(), NewIdx);

= getOrCreateVReg(*NewIdxCI);

= getOrCreateVReg(*

.getOperand(2));

IRTranslator::translateInsertVector(

&U,

Vec = getOrCreateVReg(*

.getOperand(0));

Elt = getOrCreateVReg(*

.getOperand(1));

*CI = cast<ConstantInt>(

.getOperand(2));

(CI->

() != PreferredVecIdxWidth) {

CI = ConstantInt::get(CI->

(), NewIdx);

(

*ResultType = dyn_cast<FixedVectorType>(

.getOperand(1)->getType());

ResultType && ResultType->getNumElements() == 1) {

(

*InputType = dyn_cast<FixedVectorType>(

.getOperand(0)->getType());

InputType && InputType->getNumElements() == 1) {

translateCopy(U, *

.getOperand(0), MIRBuilder);

(isa<FixedVectorType>(

.getOperand(0)->getType())) {

(isa<ScalableVectorType>(

.getOperand(0)->getType())) {

ScaledIndex = MIRBuilder.

(

getOrCreateVReg(U), getOrCreateVReg(*

.getOperand(0)),

IRTranslator::translateExtractElement(

&U,

dyn_cast<FixedVectorType>(

.getOperand(0)->getType()))

(FVT->getNumElements() == 1)

translateCopy(U, *

.getOperand(0), MIRBuilder);

Val = getOrCreateVReg(*

.getOperand(0));

(

*CI = dyn_cast<ConstantInt>(

.getOperand(1))) {

(CI->

() != PreferredVecIdxWidth) {

*NewIdxCI = ConstantInt::get(CI->

(), NewIdx);

= getOrCreateVReg(*NewIdxCI);

= getOrCreateVReg(*

.getOperand(1));

IRTranslator::translateExtractVector(

&U,

Vec = getOrCreateVReg(*

.getOperand(0));

*CI = cast<ConstantInt>(

.getOperand(1));

(CI->

() != PreferredVecIdxWidth) {

CI = ConstantInt::get(CI->

(), NewIdx);

(

*ResultType = dyn_cast<FixedVectorType>(

.getType());

ResultType && ResultType->getNumElements() == 1) {

(

*InputType = dyn_cast<FixedVectorType>(

.getOperand(0)->getType());

InputType && InputType->getNumElements() == 1) {

translateCopy(U, *

.getOperand(0), MIRBuilder);

(isa<FixedVectorType>(

.getOperand(0)->getType())) {

(isa<ScalableVectorType>(

.getOperand(0)->getType())) {

ScaledIndex = MIRBuilder.

(

getOrCreateVReg(*

.getOperand(0)),

IRTranslator::translateShuffleVector(

&U,

(

.getOperand(0)->getType()->isScalableTy()) {

Val = getOrCreateVReg(*

.getOperand(0));

(

*SVI = dyn_cast<ShuffleVectorInst>(&U))

= SVI->getShuffleMask();

= cast<ConstantExpr>(U).getShuffleMask();

.

(TargetOpcode::G_SHUFFLE_VECTOR, {getOrCreateVReg(U)},

{getOrCreateVReg(*

.getOperand(0)),

getOrCreateVReg(*

.getOperand(1))})

.addShuffleMask(MaskAlloc);

&PI = cast<PHINode>(U);

(

Reg : getOrCreateVRegs(PI)) {

MIB = MIRBuilder.

(TargetOpcode::G_PHI, {

}, {});

PendingPHIs.emplace_back(&PI, std::move(Insts));

IRTranslator::translateAtomicCmpXchg(

&U,

Res = getOrCreateVRegs(

);

= getOrCreateVReg(*

.getCompareOperand());

NewVal = getOrCreateVReg(*

.getNewValOperand());

OldValRes, SuccessRes,

, Cmp, NewVal,

getMemOpAlign(

),

.getAAMetadata(),

,

.getSyncScopeID(),

.getSuccessOrdering(),

.getFailureOrdering()));

IRTranslator::translateAtomicRMW(

&U,

Val = getOrCreateVReg(*

.getValOperand());

Opcode = 0;

(

.getOperation()) {

Opcode = TargetOpcode::G_ATOMICRMW_XCHG;

Opcode = TargetOpcode::G_ATOMICRMW_ADD;

Opcode = TargetOpcode::G_ATOMICRMW_SUB;

Opcode = TargetOpcode::G_ATOMICRMW_AND;

Opcode = TargetOpcode::G_ATOMICRMW_NAND;

Opcode = TargetOpcode::G_ATOMICRMW_OR;

Opcode = TargetOpcode::G_ATOMICRMW_XOR;

Opcode = TargetOpcode::G_ATOMICRMW_MAX;

Opcode = TargetOpcode::G_ATOMICRMW_MIN;

Opcode = TargetOpcode::G_ATOMICRMW_UMAX;

Opcode = TargetOpcode::G_ATOMICRMW_UMIN;

Opcode = TargetOpcode::G_ATOMICRMW_FADD;

Opcode = TargetOpcode::G_ATOMICRMW_FSUB;

Opcode = TargetOpcode::G_ATOMICRMW_FMAX;

Opcode = TargetOpcode::G_ATOMICRMW_FMIN;

Opcode = TargetOpcode::G_ATOMICRMW_UINC_WRAP;

Opcode = TargetOpcode::G_ATOMICRMW_UDEC_WRAP;

Opcode = TargetOpcode::G_ATOMICRMW_USUB_COND;

Opcode = TargetOpcode::G_ATOMICRMW_USUB_SAT;

Opcode, Res,

, Val,

Flags, MRI->

(Val), getMemOpAlign(

),

.getAAMetadata(),

,

.getSyncScopeID(),

IRTranslator::translateFence(

&U,

&Fence = cast<FenceInst>(U);

IRTranslator::translateFreeze(

&U,

);

(

= 0;

< DstRegs.

(); ++

) {

IRTranslator::finishPendingPhis() {

(

&Phi : PendingPHIs) {

(

*Pred : getMachinePredBBs({IRPred, PI->

()})) {

SeenPreds.

(Pred);

(

j = 0;

< ValRegs.

(); ++

) {

MIB.

(ValRegs[j]);

IRTranslator::translateDbgValueRecord(

*V,

HasArgList,

);

(!V || HasArgList) {

(

*CI = dyn_cast<Constant>(V)) {

(

*AI = dyn_cast<AllocaInst>(V);

ExprOperands =

->getElements();

*ExprDerefRemoved =

(translateIfEntryValueArgument(

, V, Variable,

, DL,

(

Reg : getOrCreateVRegs(*V)) {

IRTranslator::translateDbgDeclareRecord(

*

,

HasArgList,

(

() <<

<< *Variable <<

);

);

AI = dyn_cast<AllocaInst>(

);

getOrCreateFrameIndex(*AI), DL);

(translateIfEntryValueArgument(

,

, Variable,

IRTranslator::translateDbgInfo(

&Inst,

(DLR->getLabel() &&

);

(DLR->getLabel()->isValidLocationForIntrinsic(

);

IRTranslator::translate(

&Inst) {

CurBuilder->setPCSections(Inst.

(LLVMContext::MD_pcsections));

CurBuilder->setMMRAMetadata(Inst.

(LLVMContext::MD_mmra));

(

CurrInstDL = CurBuilder->getDL())

EntryBuilder->setDebugLoc(

());

(

CI = dyn_cast<ConstantInt>(&

))

EntryBuilder->buildConstant(Reg, *CI);

(

CF = dyn_cast<ConstantFP>(&

))

EntryBuilder->buildFConstant(Reg, *CF);

(isa<UndefValue>(

))

EntryBuilder->buildUndef(Reg);

(isa<ConstantPointerNull>(

))

EntryBuilder->buildConstant(Reg, 0);

(

GV = dyn_cast<GlobalValue>(&

))

EntryBuilder->buildGlobalValue(Reg, GV);

(

CPA = dyn_cast<ConstantPtrAuth>(&

)) {

AddrDisc = getOrCreateVReg(*CPA->getAddrDiscriminator());

EntryBuilder->buildConstantPtrAuth(Reg, CPA,

, AddrDisc);

}

(

CAZ = dyn_cast<ConstantAggregateZero>(&

)) {

&Elt = *CAZ->getElementValue(0u);

(isa<ScalableVectorType>(CAZ->getType())) {

EntryBuilder->buildSplatVector(Reg, getOrCreateVReg(Elt));

NumElts = CAZ->getElementCount().getFixedValue();

translateCopy(

, Elt, *EntryBuilder);

EntryBuilder->buildSplatBuildVector(Reg, getOrCreateVReg(Elt));

}

(

CV = dyn_cast<ConstantDataVector>(&

)) {

(CV->getNumElements() == 1)

translateCopy(

, *CV->getElementAsConstant(0), *EntryBuilder);

(

i = 0; i < CV->getNumElements(); ++i) {

&Elt = *CV->getElementAsConstant(i);

EntryBuilder->buildBuildVector(Reg, Ops);

}

(

CE = dyn_cast<ConstantExpr>(&

)) {

(

->getOpcode()) {

}

(

CV = dyn_cast<ConstantVector>(&

)) {

(CV->getNumOperands() == 1)

translateCopy(

, *CV->getOperand(0), *EntryBuilder);

(

i = 0; i < CV->getNumOperands(); ++i) {

Ops.

(getOrCreateVReg(*CV->getOperand(i)));

EntryBuilder->buildBuildVector(Reg, Ops);

}

(

*BA = dyn_cast<BlockAddress>(&

)) {

EntryBuilder->buildBlockAddress(Reg, BA);

IRTranslator::finalizeBasicBlock(

&BB,

(

&BTB : SL->BitTestCases) {

emitBitTestHeader(BTB, BTB.Parent);

(

j = 0, ej = BTB.Cases.size(); j != ej; ++j) {

UnhandledProb -= BTB.Cases[

].ExtraProb;

((BTB.ContiguousRange || BTB.FallthroughUnreachable) && j + 2 == ej) {

NextMBB = BTB.Cases[

+ 1].TargetBB;

}

(j + 1 == ej) {

NextMBB = BTB.Default;

NextMBB = BTB.Cases[

+ 1].ThisBB;

emitBitTestCase(BTB, NextMBB, UnhandledProb, BTB.Reg, BTB.Cases[j],

);

((BTB.ContiguousRange || BTB.FallthroughUnreachable) && j + 2 == ej) {

addMachineCFGPred({BTB.Parent->getBasicBlock(),

BTB.Cases[ej - 1].TargetBB->getBasicBlock()},

BTB.Cases.pop_back();

CFGEdge HeaderToDefaultEdge = {BTB.Parent->getBasicBlock(),

BTB.Default->getBasicBlock()};

addMachineCFGPred(HeaderToDefaultEdge, BTB.Parent);

(!BTB.ContiguousRange) {

addMachineCFGPred(HeaderToDefaultEdge, BTB.Cases.back().ThisBB);

SL->BitTestCases.clear();

(

&JTCase : SL->JTCases) {

(!JTCase.first.Emitted)

emitJumpTableHeader(JTCase.second, JTCase.first, JTCase.first.HeaderBB);

emitJumpTable(JTCase.second, JTCase.second.MBB);

SL->JTCases.clear();

(

&SwCase : SL->SwitchCases)

emitSwitchCase(SwCase, &CurBuilder->getMBB(), *CurBuilder);

SL->SwitchCases.clear();

FunctionBasedInstrumentation =

SPDescriptor.

(&BB, &

, FunctionBasedInstrumentation);

(

() <<

);

SuccessMBB->

(SuccessMBB->

(), ParentMBB, SplitPoint,

ParentMBB->

());

(!emitSPDescriptorParent(SPDescriptor, ParentMBB))

(FailureMBB->

()) {

(!emitSPDescriptorFailure(SPDescriptor, FailureMBB))

CurBuilder->setInsertPt(*ParentBB, ParentBB->

());

StackSlotPtr = CurBuilder->buildFrameIndex(PtrTy, FI).getReg(0);

->buildLoad(PtrMemTy, StackSlotPtr,

(

() <<

);

(FnTy->getNumParams() == 1 &&

);

(GuardCheckFn->hasAttribute(1, Attribute::AttrKind::InReg))

{GuardVal, FnTy->getParamType(0), {

}});

.OrigArgs.push_back(GuardArgInfo);

.CallConv = GuardCheckFn->getCallingConv();

(!CLI->

(MIRBuilder, Info)) {

(

() <<

);

getStackGuard(Guard, *CurBuilder);

GuardPtr = getOrCreateVReg(*IRGuard);

->buildLoad(PtrMemTy, GuardPtr,

CurBuilder->setInsertPt(*FailureBB, FailureBB->

());

(!CLI->

(*CurBuilder, Info)) {

(

() <<

);

CurBuilder->buildInstr(TargetOpcode::G_TRAP);

IRTranslator::finalizeFunction() {

PendingPHIs.clear();

FrameIndices.clear();

MachinePreds.clear();

EntryBuilder.reset();

*CI = dyn_cast<CallInst>(&

);

CI && CI->isMustTailCall();

getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();

TPC = &getAnalysis<TargetPassConfig>();

EntryBuilder = std::make_unique<CSEMIRBuilder>(CurMF);

EntryBuilder->setCSEInfo(CSEInfo);

CurBuilder = std::make_unique<CSEMIRBuilder>(CurMF);

CurBuilder->setCSEInfo(CSEInfo);

EntryBuilder = std::make_unique<MachineIRBuilder>();

CurBuilder = std::make_unique<MachineIRBuilder>();

CurBuilder->setMF(*MF);

EntryBuilder->setMF(*MF);

= &

.getDataLayout();

ORE = std::make_unique<OptimizationRemarkEmitter>(&

);

TM.resetTargetOptions(

);

AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();

FuncInfo.

= &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();

FuncInfo.

=

;

AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(

LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(

);

SL = std::make_unique<GISelSwitchLowering>(

, FuncInfo);

SL->init(*TLI, TM, *

);

(PendingPHIs.empty() &&

);

.getSubprogram(), &

.getEntryBlock());

R <<

;

FinalizeOnReturn =

([

]() { finalizeFunction(); });

EntryBuilder->setMBB(*EntryBB);

DbgLoc =

.getEntryBlock().getFirstNonPHIIt()->getDebugLoc();

IsVarArg =

.isVarArg();

HasMustTailInVarArgFn =

;

FuncInfo.

.resize(

.getMaxBlockNumber());

(!HasMustTailInVarArgFn)

EntryBB->addSuccessor(&getMBB(

.front()));

.getSubprogram(), &

.getEntryBlock());

R <<

<<

(

,

.getFunctionType());

(

->getTypeStoreSize(Arg.

()).isZero())

(Arg.hasSwiftErrorAttr()) {

(VRegs.

() == 1 &&

);

.getSubprogram(), &

.getEntryBlock());

R <<

<<

(

,

.getFunctionType());

(EnableCSE && CSEInfo)

CurBuilder->setMBB(

);

HasTailCall =

;

translateDbgInfo(Inst, *CurBuilder);

(translate(Inst))

R <<

<<

(

, &Inst);

(ORE->allowExtraAnalysis(

)) {

std::string InstStrStorage;

R <<

<< InstStrStorage <<

;

(!finalizeBasicBlock(*BB,

)) {

BB->getTerminator()->getDebugLoc(), BB);

R <<

;

finishPendingPhis();

(EntryBB->succ_size() == 1 &&

);

);

NewEntryBB.

(NewEntryBB.

(), EntryBB, EntryBB->begin(),

EntryBB->removeSuccessor(&NewEntryBB);

);

amdgpu aa AMDGPU Address space based Alias Analysis Wrapper

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Analysis containing CSE Info

Provides analysis for continuously CSEing during GISel passes.

This file implements a version of MachineIRBuilder which CSEs insts within a MachineBasicBlock.

This file describes how to lower LLVM calls to machine code calls.

This file contains the declarations for the subclasses of Constant, which represent the different fla...

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

This contains common code to allow clients to notify changes to machine instr.

const HexagonInstrInfo * TII

IRTranslator LLVM IR static false void reportTranslationError(MachineFunction &MF, const TargetPassConfig &TPC, OptimizationRemarkEmitter &ORE, OptimizationRemarkMissed &R)

static bool checkForMustTailInVarArgFn(bool IsVarArg, const BasicBlock &BB)

Returns true if a BasicBlock BB within a variadic function contains a variadic musttail call.

static bool containsBF16Type(const User &U)

static unsigned getConvOpcode(Intrinsic::ID ID)

static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL)

static unsigned getConstrainedOpcode(Intrinsic::ID ID)

static cl::opt< bool > EnableCSEInIRTranslator("enable-cse-in-irtranslator", cl::desc("Should enable CSE in irtranslator"), cl::Optional, cl::init(false))

static bool isValInBlock(const Value *V, const BasicBlock *BB)

static bool isSwiftError(const Value *V)

This file declares the IRTranslator pass.

This file provides various utilities for inspecting and working with the control flow graph in LLVM I...

This file describes how to lower LLVM inline asm to machine code INLINEASM.

Legalize the Machine IR a function s Machine IR

Implement a low-level type suitable for MachineInstr level instruction selection.

Implement a low-level type suitable for MachineInstr level instruction selection.

This file declares the MachineIRBuilder class.

unsigned const TargetRegisterInfo * TRI

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

verify safepoint Safepoint IR Verifier

This file defines the make_scope_exit function, which executes user-defined cleanup logic at scope ex...

This file defines the SmallSet class.

This file defines the SmallVector class.

This file describes how to lower LLVM code to machine code.

Target-Independent Code Generator Pass Configuration Options pass.

A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.

bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)

Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...

Class for arbitrary precision integers.

APInt zextOrTrunc(unsigned width) const

Zero extend or truncate to width.

an instruction to allocate memory on the stack

bool isSwiftError() const

Return true if this alloca is used as a swifterror argument to a call.

bool isStaticAlloca() const

Return true if this alloca is in the entry block of the function and is a constant size.

Align getAlign() const

Return the alignment of the memory that is being allocated by the instruction.

PointerType * getType() const

Overload to return most specific pointer type.

Type * getAllocatedType() const

Return the type that is being allocated by the instruction.

const Value * getArraySize() const

Get the number of elements allocated.

Represent the analysis usage information of a pass.

AnalysisUsage & addRequired()

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

This class represents an incoming formal argument to a Function.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

bool empty() const

empty - Check if the array is empty.

An immutable pass that tracks lazily created AssumptionCache objects.

An instruction that atomically checks whether a specified value is in a memory location,...

an instruction that atomically reads a memory location, combines it with another value,...

@ USubCond

Subtract only if no unsigned overflow.

@ Min

*p = old <signed v ? old : v

@ USubSat

*p = usub.sat(old, v) usub.sat matches the behavior of llvm.usub.sat.

@ UIncWrap

Increment one up to a maximum value.

@ Max

*p = old >signed v ? old : v

@ UMin

*p = old <unsigned v ? old : v

@ FMin

*p = minnum(old, v) minnum matches the behavior of llvm.minnum.

@ UMax

*p = old >unsigned v ? old : v

@ FMax

*p = maxnum(old, v) maxnum matches the behavior of llvm.maxnum.

@ UDecWrap

Decrement one until a minimum value or zero.

Attribute getFnAttr(Attribute::AttrKind Kind) const

Return the attribute object that exists for the function.

StringRef getValueAsString() const

Return the attribute's value as a string.

LLVM Basic Block Representation.

unsigned getNumber() const

bool hasAddressTaken() const

Returns true if there are any uses of this basic block other than direct branches,...

InstListType::const_iterator getFirstNonPHIIt() const

Returns an iterator to the first instruction in this block that is not a PHINode instruction.

InstListType::const_iterator const_iterator

InstListType::const_iterator getFirstNonPHIOrDbg(bool SkipPseudoOp=true) const

Returns a pointer to the first instruction in this block that is not a PHINode or a debug intrinsic,...

const Function * getParent() const

Return the enclosing method, or null if none.

const Instruction & back() const

const Module * getModule() const

Return the module owning the function this basic block belongs to, or nullptr if the function does no...

Legacy analysis pass which computes BlockFrequencyInfo.

Conditional or Unconditional Branch instruction.

BasicBlock * getSuccessor(unsigned i) const

bool isUnconditional() const

Value * getCondition() const

Legacy analysis pass which computes BranchProbabilityInfo.

Analysis providing branch probability information.

BranchProbability getEdgeProbability(const BasicBlock *Src, unsigned IndexInSuccessors) const

Get an edge's probability, relative to other out-edges of the Src.

static BranchProbability getZero()

static void normalizeProbabilities(ProbabilityIter Begin, ProbabilityIter End)

Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...

bool isInlineAsm() const

Check if this call is an inline asm statement.

std::optional< OperandBundleUse > getOperandBundle(StringRef Name) const

Return an operand bundle by name, if present.

Function * getCalledFunction() const

Returns the function called, or null if this is an indirect function invocation or the function signa...

bool paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const

Determine whether the argument or parameter has the given attribute.

User::op_iterator arg_begin()

Return the iterator pointing to the beginning of the argument list.

unsigned countOperandBundlesOfType(StringRef Name) const

Return the number of operand bundles with the tag Name attached to this instruction.

Value * getCalledOperand() const

Value * getArgOperand(unsigned i) const

User::op_iterator arg_end()

Return the iterator pointing to the end of the argument list.

bool isConvergent() const

Determine if the invoke is convergent.

Intrinsic::ID getIntrinsicID() const

Returns the intrinsic ID of the intrinsic called or Intrinsic::not_intrinsic if the called function i...

iterator_range< User::op_iterator > args()

Iteration adapter for range-for loops.

unsigned arg_size() const

AttributeList getAttributes() const

Return the attributes for this call.

This class represents a function call, abstracting a target machine's calling convention.

bool checkReturnTypeForCallConv(MachineFunction &MF) const

Toplevel function to check the return type based on the target calling convention.

virtual bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const

This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...

virtual bool enableBigEndian() const

For targets which want to use big-endian can enable it with enableBigEndian() hook.

virtual bool supportSwiftError() const

virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const

This hook must be implemented to lower outgoing return values, described by Val, into the specified v...

virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const

This hook must be implemented to lower the given call instruction, including argument and return valu...

virtual bool fallBackToDAGISel(const MachineFunction &MF) const

This class is the base class for the comparison instructions.

Predicate

This enumeration lists the possible predicates for CmpInst subclasses.

@ FCMP_TRUE

1 1 1 1 Always true (always folded)

@ ICMP_SLT

signed less than

@ ICMP_SLE

signed less or equal

@ ICMP_UGT

unsigned greater than

@ ICMP_ULE

unsigned less or equal

@ FCMP_FALSE

0 0 0 0 Always false (always folded)

bool isFPPredicate() const

bool isIntPredicate() const

This is the shared class of boolean and integer constants.

static ConstantInt * getTrue(LLVMContext &Context)

bool isZero() const

This is just a convenience method to make client code smaller for a common code.

unsigned getBitWidth() const

getBitWidth - Return the scalar bitwidth of this constant.

uint64_t getZExtValue() const

Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...

const APInt & getValue() const

Return the constant as an APInt value reference.

This is an important base class in LLVM.

static Constant * getAllOnesValue(Type *Ty)

static Constant * getNullValue(Type *Ty)

Constructor to create a '0' constant of arbitrary type.

This is the common base class for constrained floating point intrinsics.

std::optional< fp::ExceptionBehavior > getExceptionBehavior() const

unsigned getNonMetadataArgCount() const

bool isEntryValue() const

Check if the expression consists of exactly one entry value operand.

static DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)

Append the opcodes Ops to DIExpr.

bool isValidLocationForIntrinsic(const DILocation *DL) const

Check that a location is valid for this label.

bool isValidLocationForIntrinsic(const DILocation *DL) const

Check that a location is valid for this variable.

This class represents an Operation in the Expression.

A parsed version of the target data layout string in and methods for querying it.

unsigned getPointerSizeInBits(unsigned AS=0) const

Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...

const StructLayout * getStructLayout(StructType *Ty) const

Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...

IntegerType * getIndexType(LLVMContext &C, unsigned AddressSpace) const

Returns the type of a GEP index in AddressSpace.

TypeSize getTypeAllocSize(Type *Ty) const

Returns the offset in bytes between successive objects of the specified type, including alignment pad...

TypeSize getTypeSizeInBits(Type *Ty) const

Size examples:

TypeSize getTypeStoreSize(Type *Ty) const

Returns the maximum number of bytes that may be overwritten by storing the specified type.

Align getPointerABIAlignment(unsigned AS) const

Layout pointer alignment.

This represents the llvm.dbg.declare instruction.

Value * getAddress() const

This represents the llvm.dbg.label instruction.

DILabel * getLabel() const

Records a position in IR for a source label (DILabel).

Base class for non-instruction debug metadata records that have positions within IR.

DebugLoc getDebugLoc() const

This represents the llvm.dbg.value instruction.

Value * getValue(unsigned OpIdx=0) const

DILocalVariable * getVariable() const

DIExpression * getExpression() const

Record of a variable value-assignment, aka a non instruction representation of the dbg....

DIExpression * getExpression() const

Value * getVariableLocationOp(unsigned OpIdx) const

DILocalVariable * getVariable() const

bool isDbgDeclare() const

Class representing an expression and its matching format.

This instruction compares its operands according to the predicate given to the constructor.

An instruction for ordering other memory operations.

SyncScope::ID getSyncScopeID() const

Returns the synchronization scope ID of this fence instruction.

AtomicOrdering getOrdering() const

Returns the ordering constraint of this fence instruction.

Class to represent fixed width SIMD vectors.

static FixedVectorType * get(Type *ElementType, unsigned NumElts)

BranchProbabilityInfo * BPI

void clear()

clear - Clear out all the function-specific state.

MachineBasicBlock * getMBB(const BasicBlock *BB) const

SmallVector< MachineBasicBlock * > MBBMap

A mapping from LLVM basic block number to their machine block.

bool CanLowerReturn

CanLowerReturn - true iff the function's return value can be lowered to registers.

bool skipFunction(const Function &F) const

Optional passes call this function to check whether the pass should be skipped.

const BasicBlock & getEntryBlock() const

DISubprogram * getSubprogram() const

Get the attached subprogram.

bool hasMinSize() const

Optimize this function for minimum size (-Oz).

Constant * getPersonalityFn() const

Get the personality function associated with this function.

const Function & getFunction() const

bool isIntrinsic() const

isIntrinsic - Returns true if the function's name starts with "llvm.".

bool hasOptNone() const

Do not optimize this function (-O0).

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

The actual analysis pass wrapper.

Simple wrapper that does the following.

Abstract class that contains various methods for clients to notify about changes.

Simple wrapper observer that takes several observers, and calls each one for each event.

void removeObserver(GISelChangeObserver *O)

void addObserver(GISelChangeObserver *O)

static StringRef dropLLVMManglingEscape(StringRef Name)

If the given string begins with the GlobalValue name mangling escape character '\1',...

bool hasExternalWeakLinkage() const

bool hasDLLImportStorageClass() const

Module * getParent()

Get the module that this global value is contained inside of...

bool isTailCall(const MachineInstr &MI) const override

This instruction compares its operands according to the predicate given to the constructor.

bool runOnMachineFunction(MachineFunction &MF) override

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

IRTranslator(CodeGenOptLevel OptLevel=CodeGenOptLevel::None)

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...

Indirect Branch Instruction.

bool lowerInlineAsm(MachineIRBuilder &MIRBuilder, const CallBase &CB, std::function< ArrayRef< Register >(const Value &Val)> GetOrCreateVRegs) const

Lower the given inline asm call instruction GetOrCreateVRegs is a callback to materialize a register ...

This instruction inserts a struct field of array element value into an aggregate value.

iterator_range< simple_ilist< DbgRecord >::iterator > getDbgRecordRange() const

Return a range over the DbgRecords attached to this instruction.

const DebugLoc & getDebugLoc() const

Return the debug location for this node as a DebugLoc.

const Module * getModule() const

Return the module owning the function this instruction belongs to or nullptr it the function does not...

bool hasMetadata() const

Return true if this instruction has any metadata attached to it.

MDNode * getMetadata(unsigned KindID) const

Get the metadata of given kind attached to this Instruction.

AAMDNodes getAAMetadata() const

Returns the AA metadata for this instruction.

unsigned getOpcode() const

Returns a member of one of the enums like Instruction::Add.

bool hasAllowReassoc() const LLVM_READONLY

Determine whether the allow-reassociation flag is set.

Intrinsic::ID getIntrinsicID() const

Return the intrinsic ID of this intrinsic.

constexpr LLT changeElementType(LLT NewEltTy) const

If this type is a vector, return a vector with the same number of elements but the new element type.

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

constexpr uint16_t getNumElements() const

Returns the number of elements in a vector LLT.

constexpr bool isVector() const

static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)

Get a low-level pointer in the given address space.

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

constexpr bool isPointer() const

constexpr LLT getElementType() const

Returns the vector's element type. Only valid for vector types.

static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)

Get a low-level fixed-width vector of some number of elements and element width.

constexpr bool isFixedVector() const

Returns true if the LLT is a fixed vector.

The landingpad instruction holds all of the information necessary to generate correct exception handl...

An instruction for reading from memory.

Value * getPointerOperand()

AtomicOrdering getOrdering() const

Returns the ordering constraint of this load instruction.

SyncScope::ID getSyncScopeID() const

Returns the synchronization scope ID of this load instruction.

static LocationSize precise(uint64_t Value)

Context object for machine code objects.

MCSymbol * createTempSymbol()

Create a temporary symbol with a unique name.

MCSymbol * getOrCreateFrameAllocSymbol(const Twine &FuncName, unsigned Idx)

Gets a symbol that will be defined to the final stack offset of a local variable after codegen.

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

unsigned pred_size() const

void normalizeSuccProbs()

Normalize probabilities of all successors so that the sum of them becomes one.

void setAddressTakenIRBlock(BasicBlock *BB)

Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.

instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

void setSuccProbability(succ_iterator I, BranchProbability Prob)

Set successor probability of a given iterator.

succ_iterator succ_begin()

void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())

Add Succ as a successor of this MachineBasicBlock.

SmallVectorImpl< MachineBasicBlock * >::iterator succ_iterator

void sortUniqueLiveIns()

Sorts and uniques the LiveIns vector.

bool isPredecessor(const MachineBasicBlock *MBB) const

Return true if the specified MBB is a predecessor of this block.

void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())

Adds the specified register as a live in.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

void setIsEHPad(bool V=true)

Indicates the block is a landing pad.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool hasVarSizedObjects() const

This method may be called any time after instruction selection is complete to determine if the stack ...

int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)

Create a new statically sized stack object, returning a nonnegative identifier to represent it.

int getStackProtectorIndex() const

Return the index for the stack protector object.

void setStackProtectorIndex(int I)

int CreateVariableSizedObject(Align Alignment, const AllocaInst *Alloca)

Notify the MachineFrameInfo object that a variable sized object has been created.

void setHasMustTailInVarArgFunc(bool B)

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

ArrayRef< int > allocateShuffleMask(ArrayRef< int > Mask)

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

unsigned getTypeIDFor(const GlobalValue *TI)

Return the type id for the specified typeinfo. This is function wide.

void push_back(MachineBasicBlock *MBB)

void setHasFakeUses(bool V)

MCContext & getContext() const

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

MCSymbol * addLandingPad(MachineBasicBlock *LandingPad)

Add a new panding pad, and extract the exception handling information from the landingpad instruction...

void deleteMachineBasicBlock(MachineBasicBlock *MBB)

DeleteMachineBasicBlock - Delete the given MachineBasicBlock.

Function & getFunction()

Return the LLVM function that this machine code represents.

void remove(iterator MBBI)

void setVariableDbgInfo(const DILocalVariable *Var, const DIExpression *Expr, int Slot, const DILocation *Loc)

Collect information used to emit debugging information of a variable in a stack slot.

const MachineBasicBlock & front() const

void addInvoke(MachineBasicBlock *LandingPad, MCSymbol *BeginLabel, MCSymbol *EndLabel)

Provide the begin and end labels of an invoke style call and associate it with a try landing pad bloc...

MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)

CreateMachineBasicBlock - Allocate a new MachineBasicBlock.

void erase(iterator MBBI)

void insert(iterator MBBI, MachineBasicBlock *MBB)

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

Helper class to build MachineInstr.

MachineInstrBuilder buildFPTOUI_SAT(const DstOp &Dst, const SrcOp &Src0)

Build and insert Res = G_FPTOUI_SAT Src0.

MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)

MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)

Build and insert Dst = G_FREEZE Src.

MachineInstrBuilder buildBr(MachineBasicBlock &Dest)

Build and insert G_BR Dest.

std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)

Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)

MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_ADD Op0, Op1.

MachineInstrBuilder buildUndef(const DstOp &Res)

Build and insert Res = IMPLICIT_DEF.

MachineInstrBuilder buildResetFPMode()

Build and insert G_RESET_FPMODE.

MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_FPEXT Op.

MachineInstrBuilder buildFPTOSI_SAT(const DstOp &Dst, const SrcOp &Src0)

Build and insert Res = G_FPTOSI_SAT Src0.

MachineInstrBuilder buildUCmp(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)

Build and insert a Res = G_UCMP Op0, Op1.

MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)

Build and insert Res = G_JUMP_TABLE JTI.

MachineInstrBuilder buildSCmp(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)

Build and insert a Res = G_SCMP Op0, Op1.

MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)

Build and insert G_FENCE Ordering, Scope.

MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert a Res = G_SELECT Tst, Op0, Op1.

MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_FMA Op0, Op1, Op2.

MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_MUL Op0, Op1.

MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0, const SrcOp &Src1, unsigned Index)

Build and insert Res = G_INSERT_SUBVECTOR Src0, Src1, Idx.

MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)

Build and insert Res = G_AND Op0, Op1.

MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)

Build and insert an appropriate cast between two registers of equal size.

MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert a Res = G_ICMP Pred, Op0, Op1.

MachineBasicBlock::iterator getInsertPt()

Current insertion point for new instructions.

MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...

MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.

MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_SUB Op0, Op1.

MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)

Build and insert a G_INTRINSIC instruction.

MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts)

Build and insert Res = G_VSCALE MinElts.

MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src)

Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.

MachineInstrBuilder buildSetFPMode(const SrcOp &Src)

Build and insert G_SET_FPMODE Src.

MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...

MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...

MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)

Build and insert G_BRCOND Tst, Dest.

MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)

Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.

MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)

Build and insert Res = G_LOAD Addr, MMO.

MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_PTR_ADD Op0, Op1.

MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...

MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res, const SrcOp &Val, const int Idx)

Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.

MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)

MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)

Build and insert G_STORE Val, Addr, MMO.

MachineInstrBuilder buildInstr(unsigned Opcode)

Build and insert <empty> = Opcode <empty>.

MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)

Build and insert Res = G_FRAME_INDEX Idx.

MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...

MachineInstrBuilder buildDbgLabel(const MDNode *Label)

Build and insert a DBG_LABEL instructions specifying that Label is given.

MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)

Build and insert G_BRJT TablePtr, JTI, IndexReg.

MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)

Build and insert Res = G_DYN_STACKALLOC Size, Align.

MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...

MachineInstrBuilder buildResetFPEnv()

Build and insert G_RESET_FPENV.

void setDebugLoc(const DebugLoc &DL)

Set the debug location to DL for all the next build instructions.

const MachineBasicBlock & getMBB() const

Getter for the basic block we currently build.

MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)

Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.

MachineInstrBuilder buildAtomicCmpXchgWithSuccess(const DstOp &OldValRes, const DstOp &SuccessRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO)

Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...

void setMBB(MachineBasicBlock &MBB)

Set the insertion point to the end of MBB.

const DebugLoc & getDebugLoc()

Get the current instruction's debug location.

MachineInstrBuilder buildTrap(bool Debug=false)

Build and insert G_TRAP or G_DEBUGTRAP.

MachineInstrBuilder buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)

Build and insert Fract, Exp = G_FFREXP Src.

MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_FPTRUNC Op.

MachineInstrBuilder buildFSincos(const DstOp &Sin, const DstOp &Cos, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)

Build and insert Sin, Cos = G_FSINCOS Src.

MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)

Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.

MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)

Build but don't insert <empty> = Opcode <empty>.

MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)

Build and insert Res = COPY Op.

MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW, unsigned Locality, unsigned CacheType, MachineMemOperand &MMO)

Build and insert G_PREFETCH Addr, RW, Locality, CacheType.

MachineInstrBuilder buildExtractSubvector(const DstOp &Res, const SrcOp &Src, unsigned Index)

Build and insert Res = G_EXTRACT_SUBVECTOR Src, Idx0.

const DataLayout & getDataLayout() const

MachineInstrBuilder buildBrIndirect(Register Tgt)

Build and insert G_BRINDIRECT Tgt.

MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val)

Build and insert Res = G_SPLAT_VECTOR Val.

MachineInstrBuilder buildStepVector(const DstOp &Res, unsigned Step)

Build and insert Res = G_STEP_VECTOR Step.

virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)

Build and insert Res = G_CONSTANT Val.

MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert a Res = G_FCMP PredOp0, Op1.

MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_FADD Op0, Op1.

MachineInstrBuilder buildSetFPEnv(const SrcOp &Src)

Build and insert G_SET_FPENV Src.

Register getReg(unsigned Idx) const

Get the register for the operand index.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addMetadata(const MDNode *MD) const

const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register use operand.

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register definition operand.

Representation of each machine instruction.

void copyIRFlags(const Instruction &I)

Copy all flags to MachineInst MIFlags.

static uint32_t copyFlagsFromInstruction(const Instruction &I)

const MachineOperand & getOperand(unsigned i) const

A description of a memory reference used in the backend.

Flags

Flags values. These may be or'd together.

@ MOVolatile

The memory access is volatile.

@ MODereferenceable

The memory access is dereferenceable (i.e., doesn't trap).

@ MOLoad

The memory access reads data.

@ MOInvariant

The memory access always returns the same value (or traps).

@ MOStore

The memory access writes data.

static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)

Register getReg() const

getReg - Returns the register number.

static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)

MachineInstr * getVRegDef(Register Reg) const

getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...

LLT getType(Register Reg) const

Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.

void setRegClass(Register Reg, const TargetRegisterClass *RC)

setRegClass - Set the register class of the specified virtual register.

Register createGenericVirtualRegister(LLT Ty, StringRef Name="")

Create and return a new generic virtual register with low-level type Ty.

void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)

addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.

Representation for a specific memory location.

A Module instance is used to store all the information related to an LLVM module.

BasicBlock * getIncomingBlock(unsigned i) const

Return incoming basic block number i.

Value * getIncomingValue(unsigned i) const

Return incoming value number x.

unsigned getNumIncomingValues() const

Return the number of incoming edges.

static PointerType * getUnqual(Type *ElementType)

This constructs a pointer to an object of the specified type in the default address space (address sp...

Class to install both of the above.

Wrapper class representing virtual and physical registers.

MCRegister asMCReg() const

Utility to check-convert this value to a MCRegister.

Return a value (possibly void), from a function.

Value * getReturnValue() const

Convenience accessor. Returns null if there is no return value.

This class represents the LLVM 'select' instruction.

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

size_type count(const T &V) const

count - Return 1 if the element is in the set, 0 otherwise.

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

Encapsulates all of the information needed to generate a stack protector check, and signals to isel w...

void initialize(const BasicBlock *BB, MachineBasicBlock *MBB, bool FunctionBasedInstrumentation)

Initialize the stack protector descriptor structure for a new basic block.

MachineBasicBlock * getSuccessMBB()

void resetPerBBState()

Reset state that changes when we handle different basic blocks.

void resetPerFunctionState()

Reset state that only changes when we switch functions.

MachineBasicBlock * getFailureMBB()

MachineBasicBlock * getParentMBB()

bool shouldEmitStackProtector() const

Returns true if all fields of the stack protector descriptor are initialized implying that we should/...

bool shouldEmitFunctionBasedCheckStackProtector() const

bool shouldEmitSDCheck(const BasicBlock &BB) const

void copyToMachineFrameInfo(MachineFrameInfo &MFI) const

An instruction for storing to memory.

StringRef - Represent a constant reference to a string, i.e.

constexpr bool empty() const

empty - Check if the string is empty.

constexpr const char * data() const

data - Get a pointer to the start of the string (which may not be null terminated).

TypeSize getElementOffset(unsigned Idx) const

Class to represent struct types.

bool createEntriesInEntryBlock(DebugLoc DbgLoc)

Create initial definitions of swifterror values in the entry block of the current function.

void setFunction(MachineFunction &MF)

Initialize data structures for specified new function.

void setCurrentVReg(const MachineBasicBlock *MBB, const Value *, Register)

Set the swifterror virtual register in the VRegDefMap for this basic block.

Register getOrCreateVRegUseAt(const Instruction *, const MachineBasicBlock *, const Value *)

Get or create the swifterror value virtual register for a use of a swifterror by an instruction.

Register getOrCreateVRegDefAt(const Instruction *, const MachineBasicBlock *, const Value *)

Get or create the swifterror value virtual register for a def of a swifterror by an instruction.

const Value * getFunctionArg() const

Get the (unique) function argument that was marked swifterror, or nullptr if this function has no swi...

void propagateVRegs()

Propagate assigned swifterror vregs through a function, synthesizing PHI nodes when needed to maintai...

Align getStackAlign() const

getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...

TargetInstrInfo - Interface to description of machine instruction set.

virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

virtual unsigned getVaListSizeInBits(const DataLayout &DL) const

Returns the size of the platform's va_list object.

EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const

Return the EVT corresponding to this LLVM type.

CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const

Get the CallingConv that should be used for the specified libcall.

virtual bool useStackGuardXorFP() const

If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...

virtual MVT getVectorIdxTy(const DataLayout &DL) const

Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...

const TargetMachine & getTargetMachine() const

virtual Value * getSDagStackGuard(const Module &M) const

Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...

bool isJumpExpensive() const

Return true if Flow Control is an expensive operation that should be avoided.

virtual Function * getSSPStackGuardCheck(const Module &M) const

If the target has a standard stack protection check function that performs validation and error handl...

MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const

virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...

MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const

MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const

virtual bool fallBackToDAGISel(const Instruction &Inst) const

virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const

If a physical register, this returns the register that receives the exception address on entry to an ...

const char * getLibcallName(RTLIB::Libcall Call) const

Get the libcall routine name for the specified libcall.

virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const

If a physical register, this returns the register that receives the exception typeid on entry to a la...

virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const

Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...

virtual bool useLoadStackGuardNode(const Module &M) const

If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...

Primary interface to the complete machine description for the target machine.

CodeGenOptLevel getOptLevel() const

Returns the optimization level: None, Less, Default, or Aggressive.

virtual const TargetIntrinsicInfo * getIntrinsicInfo() const

If intrinsic information is available, return it. If not, return null.

const Triple & getTargetTriple() const

unsigned NoTrapAfterNoreturn

Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...

unsigned TrapUnreachable

Emit target-specific trap instruction for 'unreachable' IR instructions.

Target-Independent Code Generator Pass Configuration Options.

virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const

Returns the CSEConfig object to use for the current optimization level.

virtual bool isGISelCSEEnabled() const

Check whether continuous CSE should be enabled in GISel passes.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const InlineAsmLowering * getInlineAsmLowering() const

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

virtual const CallLowering * getCallLowering() const

virtual const TargetFrameLowering * getFrameLowering() const

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetLowering * getTargetLowering() const

bool isOSWindows() const

Tests whether the OS is Windows.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

The instances of the Type class are immutable: once they are created, they are never changed.

bool isEmptyTy() const

Return true if this type is empty, that is, it has no elements or all of its elements are empty.

TypeID

Definitions of all of the base types for the Type system.

static Type * getVoidTy(LLVMContext &C)

bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const

Return true if it makes sense to take the size of this type.

bool isAggregateType() const

Return true if the type is an aggregate type.

static IntegerType * getInt32Ty(LLVMContext &C)

bool isTokenTy() const

Return true if this is 'token'.

bool isVoidTy() const

Return true if this is 'void'.

Value * getOperand(unsigned i) const

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

bool hasOneUse() const

Return true if there is exactly one use of this value.

const Value * stripPointerCasts() const

Strip off pointer casts, all-zero GEPs and address space casts.

LLVMContext & getContext() const

All values hold a context through their type.

int getNumOccurrences() const

constexpr bool isZero() const

const ParentTy * getParent() const

NodeTy * getNextNode()

Get the next node, or nullptr for the list tail.

A raw_ostream that writes to an std::string.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr char Args[]

Key for Kernel::Metadata::mArgs.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

@ C

The default llvm calling convention, compatible with C.

ID ArrayRef< Type * > Tys

bool match(Val *V, const Pattern &P)

specificval_ty m_Specific(const Value *V)

Match if we have a specific specified value.

TwoOps_match< Val_t, Idx_t, Instruction::ExtractElement > m_ExtractElt(const Val_t &Val, const Idx_t &Idx)

Matches ExtractElementInst.

OneUse_match< T > m_OneUse(const T &SubPattern)

auto m_LogicalOr()

Matches L || R where L and R are arbitrary values.

class_match< Value > m_Value()

Match an arbitrary value and ignore it.

auto m_LogicalAnd()

Matches L && R where L and R are arbitrary values.

BinaryOp_match< cst_pred_ty< is_all_ones >, ValTy, Instruction::Xor, true > m_Not(const ValTy &V)

Matches a 'Not' as 'xor V, -1' or 'xor -1, V'.

Libcall

RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.

@ Implicit

Not emitted register (e.g. carry, or temporary result).

@ Undef

Value of the register doesn't matter.

Offsets

Offsets in bytes from the start of the input buffer.

SmallVector< SwitchWorkListItem, 4 > SwitchWorkList

std::vector< CaseCluster > CaseClusterVector

void sortAndRangeify(CaseClusterVector &Clusters)

Sort Clusters and merge adjacent cases.

CaseClusterVector::iterator CaseClusterIt

@ CC_Range

A cluster of adjacent case labels with the same destination, or just one case.

@ CC_JumpTable

A cluster of cases suitable for jump table lowering.

@ CC_BitTests

A cluster of cases suitable for bit test lowering.

@ CE

Windows NT (Windows on ARM)

Reg

All possible values of the reg field in the ModR/M byte.

initializer< Ty > init(const Ty &Val)

ExceptionBehavior

Exception behavior used for floating point operations.

@ ebIgnore

This corresponds to "fpexcept.ignore".

DiagnosticInfoOptimizationBase::Argument NV

NodeAddr< PhiNode * > Phi

NodeAddr< CodeNode * > Code

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

@ Low

Lower the current thread's priority such that it does not affect foreground tasks significantly.

int popcount(T Value) noexcept

Count the number of set bits in a value.

bool isUIntN(unsigned N, uint64_t x)

Checks if an unsigned integer fits into the given (dynamic) bit width.

detail::scope_exit< std::decay_t< Callable > > make_scope_exit(Callable &&F)

auto enumerate(FirstRange &&First, RestRanges &&...Rest)

Given two or more input ranges, returns a new range whose values are tuples (A, B,...

int countr_one(T Value)

Count the number of ones from the least significant bit to the first zero bit.

void diagnoseDontCall(const CallInst &CI)

auto successors(const MachineBasicBlock *BB)

MVT getMVTForLLT(LLT Ty)

Get a rough equivalent of an MVT for a given LLT.

gep_type_iterator gep_type_end(const User *GEP)

MachineBasicBlock::iterator findSplitPointForStackProtector(MachineBasicBlock *BB, const TargetInstrInfo &TII)

Find the split point at which to splice the end of BB into its success stack protector check machine ...

LLT getLLTForMVT(MVT Ty)

Get a rough equivalent of an LLT for a given MVT.

int countr_zero(T Val)

Count number of 0's from the least significant bit to the most stopping at the first 1.

Align getKnownAlignment(Value *V, const DataLayout &DL, const Instruction *CxtI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr)

Try to infer an alignment for the specified pointer.

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

llvm::SmallVector< int, 16 > createStrideMask(unsigned Start, unsigned Stride, unsigned VF)

Create a stride shuffle mask.

auto reverse(ContainerTy &&C)

void computeValueLLTs(const DataLayout &DL, Type &Ty, SmallVectorImpl< LLT > &ValueTys, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)

computeValueLLTs - Given an LLVM IR type, compute a sequence of LLTs that represent all the individua...

void sort(IteratorTy Start, IteratorTy End)

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

auto succ_size(const MachineBasicBlock *BB)

EHPersonality classifyEHPersonality(const Value *Pers)

See if the given exception handling personality function is one that we understand.

CodeGenOptLevel

Code generation optimization level.

@ Global

Append to llvm.global_dtors.

@ First

Helpers to iterate all locations in the MemoryEffectsBase class.

void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)

Modify analysis usage so it preserves passes required for the SelectionDAG fallback.

auto lower_bound(R &&Range, T &&Value)

Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...

llvm::SmallVector< int, 16 > createInterleaveMask(unsigned VF, unsigned NumVecs)

Create an interleave shuffle mask.

@ FMul

Product of floats.

bool isAsynchronousEHPersonality(EHPersonality Pers)

Returns true if this personality function catches asynchronous exceptions.

OutputIt copy(R &&Range, OutputIt Out)

std::optional< RoundingMode > convertStrToRoundingMode(StringRef)

Returns a valid RoundingMode enumerator when given a string that is valid as input in constrained int...

gep_type_iterator gep_type_begin(const User *GEP)

GlobalValue * ExtractTypeInfo(Value *V)

ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.

void getUnderlyingObjects(const Value *V, SmallVectorImpl< const Value * > &Objects, const LoopInfo *LI=nullptr, unsigned MaxLookup=6)

This method is similar to getUnderlyingObject except that it can look through phi and select instruct...

Align commonAlignment(Align A, uint64_t Offset)

Returns the alignment that satisfies both alignments.

LLT getLLTForType(Type &Ty, const DataLayout &DL)

Construct a low-level type based on an LLVM type.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

A collection of metadata nodes that might be associated with a memory access used by the alias-analys...

This struct is a compact representation of a valid (non-zero power of two) alignment.

uint64_t value() const

This is a hole in the type system and should not be abused.

Pair of physical register and lane mask.

This class contains a discriminated union of information about pointers in memory operands,...

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

MachineBasicBlock * Parent

This structure is used to communicate between SelectionDAGBuilder and SDISel for the code generation ...

BranchProbability TrueProb

MachineBasicBlock * ThisBB

struct PredInfoPair PredInfo

BranchProbability FalseProb

MachineBasicBlock * TrueBB

MachineBasicBlock * FalseBB

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