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Sun Jul 12 23:01:40 PDT 2020 · https://lists.llvm.org/pipermail/llvm-dev/2020-July/143340.html

On Sat, Jul 11, 2020 at 1:55 PM peng wang via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Hi Alex,
>  Thanks for your replyï¼Our members in PLCT have read your content in
> the url[1]. We are very interested in "Code generation for RISC-V
> V-extension". We will communicate in time if there are new questions
> or progress.
>
> Thank you
> Best Regards
> William
>
> [1] http://lists.llvm.org/pipermail/llvm-dev/2020-July/143238.html
> _______________________________________________
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> llvm-dev at lists.llvm.org
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Hi William,

I found your code base is not based on current instruction definitions for
RISC-V âVâ vector extension. I think you could rebase your code base on the
LLVM master branch first. After that, you could help to implement
assemble/disassemble subextensions, i.e., Zvlsseg, Zvamo, and Zvqmac, based
on D69987[1]. MC implementation is agreed by the community. I think it is a
start point to contribute.

BSC(as part of EPI project) and SiFive have a proposal for code generation
strategy for vector extension. I found your code base is based on EPI
implementation[2]. I think we already have some agreements of the
implementation. Roger is preparing a RFC for the strategy. After Roger
publishes his proposal, we could discuss the code generation strategy based
on the proposal. After we all agree on the code generation strategy, we
could work together to implement vector extension in the upstream. There
are lots of vector builtins/intrinsics needed to implement. Thanks.

Best regards,
Kai

[1] https://reviews.llvm.org/D69987
[2]
https://github.com/isrc-cas/rvv-llvm/commit/fc14172539eb1747cb4f92e47d928f0fbc4902b2
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[llvm-dev] Reply : How to contribute to LLVM RISC-V Backend