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Wed Jul 1 17:41:43 PDT 2020 · https://lists.llvm.org/pipermail/llvm-dev/2020-July/143011.html

Hello all,
I am experimenting with the LLVM code and want to add a new intrinsic. I followed the steps in this article -Â Extending LLVM: Adding instructions, intrinsics, types, etc. â LLVM 10 documentation

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Extending LLVM: Adding instructions, intrinsics, types, etc. â LLVM 10 d...

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I am not using 'llvm_any*_tyÂ types'.Â My intrinsic function looks like: def int_foo: GCCBuiltin<"__foo">, Intrinsic<[llvm_i32_ty], [llvm_i16_ty, llvm_i16_ty], []>;
I also defined it in 'Builtins.def'.
If I use this, the generated IR shows up with the suffix 'i16.i16'. Why?
As a result, it doesn't match in the instruction selection & lowering phase. If I manually edit the IR file and remove, the .i16.i16 suffix, it matches.
Thanks in advance!
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[llvm-dev] Adding new Intrinsic - Overloading