An abstract VHDL language model written in Python.
This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.
Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.
libghdl
offered via pyghdl
.The following tiny example is based on GHDL's pyGHDL.dom
package implementing pyVHDLModel.
from pathlib import Path from pyGHDL.dom.NonStandard import Design, Document sourceFile = Path("example.vhdl") design = Design() library = design.GetLibrary("lib") document = Document(sourceFile) design.AddDocument(document, library) for entity in document.Entities.values(): print(f"{entity.Identifier}") print(" generics:") for generic in entity.GenericItems: identifiers = ", ".join([str(i) for i in generic.Identifiers]) print(f" - {identifiers} : {generic.Mode!s} {generic.Subtype}") print(" ports:") for port in entity.PortItems: identifiers = ", ".join([str(i) for i in port.Identifiers]) print(f" - {identifiers} : {port.Mode!s} {port.Subtype}")
This Python package (source code) licensed under Apache License 2.0.
The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).
SPDX-License-Identifier: Apache-2.0
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