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Showing content from https://github.com/stlink-org/stlink/commit/0145baeb2e3bac31bf9d3cbd0dab38d70618d46b below:

Fixed memory alignment for STM32L5/U5/H5 chips · stlink-org/stlink@0145bae · GitHub

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lines changed Original file line number Diff line number Diff line change

@@ -1140,7 +1140,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {

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// set bank 1 for erasure

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val &= ~(1 << FLASH_L5_NSCR_NSBKER);

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}

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// sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead 8 bits for U5 but

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// sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead of 8 bits for U5 but

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// the bit position for 8th bit reserved.

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// Maybe the best solution is to handle each one separately.

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val &= ~(0xFF << 3);

Original file line number Diff line number Diff line change

@@ -748,6 +748,11 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t

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sl->flash_type == STM32_FLASH_TYPE_G4 ||

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sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 ||

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sl->flash_type == STM32_FLASH_TYPE_C0) {

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if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 && (len % 16)) {

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WLOG("Data size is aligned to 16 byte");

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len += 16 - len%16;

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}

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DLOG("Starting %3u page write\n", len / sl->flash_pgsz);

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for (off = 0; off < len; off += sizeof(uint32_t)) {

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uint32_t data;

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