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sifferman (Ethan Sifferman) · GitHub

1. Verified visual schematics for all SKY130 Cells

   Tcl 10 13

2. An example repo showing how to get started with the Lite/NiteFury and Sqrl Acorn 101/215(+) FPGAs

   Tcl 6

3. This project demonstrates a scalable format for Verilog including build scripts, design verification, and synthesis.

   Tcl 4 3

4. This project aims to create visual representations of voltage propogating through analog circuits. It uses Ngspice, Xschem, and Blender.

   Python 1

5. Advanced Architecture Labs with CVA6

   SystemVerilog 65 26

6. Ethan Sifferman Master's Thesis: "Advancing Synthesizable Verilog/SystemVerilog Education with Open-Source Tools and Autograders"

   TeX 4 1

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