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GitHub - rata/SoC: Really simple RGB to BW filter in C, C -->(HLS) verilog, and manually optimized verilog for Xilinx Zybo SoC

This is just a (yet) unfinished project for university using the SoC. The idea is to write a BW filter in verilog, C+HLS and C (running in the ARM), use the AXI4-Stream for fast access and compare the time.

The manually written Verilog does clever tricks to divide by 3 using just shifts (mathematically correct :))

As the IDEs sucks, this was created on my ~/co-diseno/tp-final/soc/...

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