@@ -7,11 +7,11 @@ nRF54L15 porting guide
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:local:
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:depth: 2
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This page provides a comprehensive overview of the code structure, file hierarchy, and essential configurations and requirements needed to successfully port and implement an sQSPI aplication on the nRF54L15 device.
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This page provides a comprehensive overview of the code structure, file hierarchy, and essential configurations and requirements needed to successfully port and implement an sQSPI application on the nRF54L15 device.
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.. _nrf54l15_porting_guide_code:
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sQSPI Application code
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sQSPI application code
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**********************
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This structure shows the relevant files and directories in the `sdk-nrfxlib`_ repository:
@@ -67,16 +67,16 @@ The following list is a detailed breakdown of the necessary paths:
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#ifndef NRFX_CONFIG_H__
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#define NRFX_CONFIG_H__
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#include "softperipheral_regif.h" // To Resolve correct VPR IRQn for the SoC.
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#define nrf_sqspi_irq_handler SP_VPR_IRQHandler
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#define NRF_SQSPI_ENABLED (1)
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#define NRF_SQSPI_MAX_NUM_DATA_LINES (4)
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#define NRF_SQSPI_SP_FIRMWARE_ADDR 0x2003c000
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//^ This address is user defined, the location for the sQSPI firmware
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#endif // NRFX_CONFIG_H__
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Compiling source files
@@ -176,8 +176,8 @@ In some cases you might have to modify the sQSPI driver configuration.
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For example, when changing pin drive strength to guarantee signal integrity for a new PCB design.
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You must address these cases on the sQSPI application code:
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* If you set the :c:var:`nrf_sqspi_cfg_t.skip_gpio_cfg` variable to ``true``, the GPIO configuration is not managed by the sQSPI driver and it must be manually handled by the application.
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* If you set the :c:var:`nrf_sqspi_cfg_t.skip_pmux_cfg` variable to ``true``, the GPIO multiplexing is not managed by the sQSPI driver and it must be manually handled by the application.
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* If you set the :c:var:`nrf_sqspi_cfg_t.skip_gpio_cfg` variable to ``true``, the GPIO configuration is not managed by the sQSPI driver and it must be manually handled by the application.
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* If you set the :c:var:`nrf_sqspi_cfg_t.skip_pmux_cfg` variable to ``true``, the GPIO multiplexing is not managed by the sQSPI driver and it must be manually handled by the application.
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The following code snippet shows how the application code can allocate the required pins and override the sQSPI driver's default configuration:
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@@ -256,10 +256,10 @@ The following code snippet shows how the application code can enable and disable
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bool result = true;
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uint32_t gpiohs_bias_val;
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uint32_t gpiohs_ctrl_val;
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gpiohs_bias_val = 0x7;
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NRF_GPIOHSPADCTRL->BIAS = gpiohs_bias_val;
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gpiohs_ctrl_val =
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(0xF << GPIOHSPADCTRL_CTRL_DATAENABLE_Pos) |
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(0x1 << GPIOHSPADCTRL_CTRL_CSNEN_Pos) |
@@ -275,15 +275,15 @@ The following code snippet shows how the application code can enable and disable
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}
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return result;
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}
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bool disable_delayed_sampling(void) {
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bool result = true;
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uint32_t gpiohs_bias_val;
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uint32_t gpiohs_ctrl_val;
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gpiohs_bias_val = 0x7;
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NRF_GPIOHSPADCTRL->BIAS = gpiohs_bias_val;
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gpiohs_ctrl_val = (0x0 << GPIOHSPADCTRL_CTRL_DATAENABLE_Pos) |
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(0x0 << GPIOHSPADCTRL_CTRL_CSNEN_Pos) |
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(0x0 << GPIOHSPADCTRL_CTRL_SCKPHASE_Pos) |
@@ -323,7 +323,7 @@ The following code snippet shows how the application code can reset **P2** pins:
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// NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL,
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// NRF_GPIO_PIN_E0E1, NRF_GPIO_PIN_NOSENSE);
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}
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void set_serialPadE0E1(nrf_sqspi_dev_cfg_t qspi_dev_config){
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nrf_gpio_cfg(m_qspi_config.pins.sck, NRF_GPIO_PIN_DIR_OUTPUT,
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NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL,
@@ -350,7 +350,7 @@ The following code snippet shows how the application code can enable and disable
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nrf_sqspi_spi_lines_t mspi_lines) {
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wmissing-braces"
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nrf_sqspi_dev_cfg_t qspi_dev_config = {
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.csn_pin = NRF_PIN_PORT_TO_PIN_NUMBER(5, 2),
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.sck_freq_khz = sck_freq_khz,
@@ -363,27 +363,27 @@ The following code snippet shows how the application code can enable and disable
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.mspi_ddr = NRF_SQSPI_SPI_DDR_SINGLE,
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.spi_clk_stretch = false,
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.xip_cfg = NRF_SQSPI_SPI_XIP_MODE_DISABLED}}};
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if (!enable_delayed_sampling(2)) {
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error_exit();
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}
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#pragma GCC diagnostic pop
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static uint16_t context = 0x45b1;
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if (nrf_sqspi_dev_cfg(p_qspi, &qspi_dev_config, done_callback, &context) !=
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NRFX_SUCCESS) {
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error_exit();
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}
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set_serialPadE0E1(qspi_dev_config);
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}
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void configure_hs_r(nrf_sqspi_t *p_qspi, uint32_t sck_freq_khz,
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nrf_sqspi_spi_lines_t mspi_lines) {
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wmissing-braces"
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nrf_sqspi_dev_cfg_t qspi_dev_config = {
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.csn_pin = NRF_PIN_PORT_TO_PIN_NUMBER(5, 2),
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.sck_freq_khz = sck_freq_khz,
@@ -396,19 +396,19 @@ The following code snippet shows how the application code can enable and disable
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.mspi_ddr = NRF_SQSPI_SPI_DDR_SINGLE,
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.spi_clk_stretch = false,
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.xip_cfg = NRF_SQSPI_SPI_XIP_MODE_DISABLED}}};
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if (!enable_delayed_sampling(2)) {
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error_exit();
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}
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#pragma GCC diagnostic pop
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static uint16_t context = 0x45b1;
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if (nrf_sqspi_dev_cfg(p_qspi, &qspi_dev_config, done_callback, &context) !=
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NRFX_SUCCESS) {
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error_exit();
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}
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set_serialPadS0S1();
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set_serialPadE0E1(qspi_dev_config);
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}
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