First make sure that capf has been included in verilog-ext-feature-list before running verilog-ext-mode-setup.
Next select which backend you want to use for tags collection: builtin or tree-sitter if available.
(setq verilog-ext-tags-backend 'tree-sitter)
Then set the variable verilog-ext-project-alist:
(setq verilog-ext-project-alist
`(("ucontroller"
:root "/home/gonz/Repos/larumbe/ucontroller"
:files ("src/pkg/global_pkg.sv"
"src/alu/rtl/alu.sv"
"src/misc/rtl/bin2bcd.sv"
"src/cpu/rtl/cpu.sv"
"src/dma/rtl/dma.sv"
"src/dma/rtl/dma_arbiter.sv"
"src/dma/rtl/dma_rx.sv"
"src/dma/rtl/dma_tx.sv"
"src/uart/rtl/fifo_wrapper.sv"
"src/ram/rtl/gp_ram.sv"
"src/ram/rtl/ram.sv"
"src/top/rtl/ram_arbiter.sv"
"src/ram/rtl/regs_ram.sv"
"src/uart/rtl/sreg.sv"
"src/uart/rtl/uart.sv"
"src/uart/rtl/uart_rx.sv"
"src/uart/rtl/uart_tx.sv"
"src/top/rtl/ucontroller.sv"
"src/uart/tb/fifo_generator_0_sim_netlist.v"
"src/top/tb/tb_clocks.sv"
"src/top/tb/tb_program.sv"
"src/top/tb/tb_top.sv"
"src/dma/tb/tb_dma.sv"
"src/alu/tb/tb_alu.sv"
"src/misc/tb/tb_bin2bcd.sv"
"src/cpu/tb/tb_cpu.sv"
"src/ram/tb/tb_ram.sv"
"src/uart/tb/tb_uart.sv")
:ignore-files ("src/uart/tb/fifo_generator_0_sim_netlist.v")
:compile-cmd "make tb_top" ; command used to compile current project
;; `vhier' related properties
:command-file "commands.f" ; vhier command file
:lib-search-path nil))) ; list of dirs to look for include directories or libraries
And gather project tags through one of these commands:
M-x verilog-ext-tags-get RETM-x verilog-ext-tags-get-async RETA tag database will be created and cached for future sessions.
Finally run completion-at-point, or if you are using company add company-capf as a company backend.
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