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Showing content from https://github.com/espressif/openocd-esp32/releases below:

Releases · espressif/openocd-esp32 · GitHub

Releases · espressif/openocd-esp32

• ESP32-H4 — Added basic debugging support. Register/memory read-write, hardware breakpoints/watchpoints, and FreeRTOS thread awareness work in single-core mode. Dual-core support will arrive in the next release.
• ESP32-C5 — CSRs have been aligned with the ECO2 specification for stable debugging (use earlier OpenOCD versions with pre-ECO2 hardware).
• ESP32-C61 — CSRs have been aligned with the ECO3 specification for stable debugging (use earlier OpenOCD versions with pre-ECO3 hardware).
• SEGGER SystemView — Multicore support has been added. The esp sysview_mcore command now generates a single trace file for both cores, viewable with SEGGER SystemView v3.60 or later.

• Fixed issues in the Espressif board detection script.
• Fixed ESP32-S3 TRAX data corruption during gcov/sysview transfers by adding a CRC16 check for read packets and a TRAX address check for write packets, enabling retries of corrupted blocks.
• Corrected the memory map supplied to GDB for all targets: the ROM region is now included so hardware breakpoints can be set in ROM. Previously, GDB attempted to insert software breakpoints due to the missing region. (GH #1560)
• Fixed JTAG connection on single-core ESP32-Solo-1 DevKit boards; it no longer tries to connect to a non-existent second JTAG tap. (GH #367)
• Fixed an incorrect flash mapping issue on the ESP32-P4 that occurred after a reset-run.

• Synced with upstream up to commit 09a54c3.
• The deprecated files tcl/interface/ftdi/esp32_devkitj_v1.cfg and tcl/interface/ftdi/esp32p4_ftdi.cfg have been removed; they are no longer used. For all FTDI-based targets, use esp_ftdi.cfg as the interface.

• target/esp32c61: Added psram support.
• loaders/esp32p4: Added flash encryption support.

• target/esp32p4: Disable super watchdog on halt. That could lead to unexpected chip resets.
• target/esp32p4: Disable auto clock gating for all peripherals on reset, as it could lead to failure during memory read/write.
• src/freertos: Fixed target memory cleanup. If the target is running post reset, we still need to cleanup OpenOCD's rtos variables, but we cannot touch the target memory as the application code will clean it, and might have already updated the memory with new data.
• tcl/target: Fixed esp32 and esp32s3 PSRAM memory type and regions. While writing the memory mapped PSRAM regions, there was a failure like read-only memory cannot be written. Because psram addresses were set as DROM.
• tcl/esp32c[5|61]: Fixed WDT TG interrupt state clearing.
• target/esp32c5: Added halt delay to wait for haltreq response. This workarounds problem observed on some esp32c5 ECO2 chips when hart HALTED state in dmstatus is refelected with some delay after haltreq is set in dmcontrol.
• target/esp: Call timer callbacks in esp32_apptrace_wait_tracing_finished. Let registered timer callbacks to run while waiting for tracing to finish

• target/esp32[c5|c6|c61|h2]: Exposed user CSRs.
• target/esp32[c5|c61|p4]: Added support for memory protection.
• target/esp32[c5|61]: Configured debug assistant address
• target/riscv: add flag to pause sending events to GDB. OpenOCD can halt and resume the target to implement some features. This kind of internal events should not be reported to GDB. Otherwise gdb might stop unintentionally and asks for register read, and remove breakpoints when the target is running.
• rtos/nuttx: Added missing Espressif riscv targets: esp32[c2|c5|c6|c61|h2|p4]
• rtos/nuttx: Added TIE registers support for esp32s3.
• rtos/zephyr: Added Espressif targets esp32[c5|c61|p4].
• rtos/freertos: Added support for non-default FreeRTOS list structure fields offsets, e.g. when CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES is enabled in IDF config. Read them at runtime from target.
• contrib/loaders: Added support for MCU boot image format. Close #243
• contrib/loaders: Added support for Simple boot used by Nuttx and Zephyr.
• contrib/loaders: Added flasher stub's clock boost support for esp32[c5|c61|p4]
• tcl/esp_common: Added option for program_esp[_bins] to skip flashing the same binary.
• esp: Added a problem hints file to the distribution. It is intended for IDEs to suggest possible solutions to users based on error output in the OpenOCD log.

• target/esp32p4: Custom mintstatus declaration due to the changed register number. Can be accessed as csr_mintstatus.
• target/esp32p4: Fixed memory access; only perform writeback for DCACHE only.
• target/esp32p4: Set watchpoints on both cores; previously, watchpoints were set only on the active core.
• target/esp32p4: Avoid writeback/invalidate all cache memory. Do it according to cache line size.
• target/esp32s3: Fixed DROM memory boundaries.
• target/esp32: Fixed incorrect sampling of the ESP32 bootstrap pin GPIO12. When the flash is empty, the TDI pin remains floating and may be sampled at an incorrect level by the bootstrap circuit, which can cause the flash to operate at an unexpected voltage.
• target/xtensa: Reset the powered-off counter when an unexamined target is powered on, so that it can be polled to detect if it becomes active later on.
• target/riscv: Update mstatus.*ie bits only with set_maskisr steponly. When value of mstatus CSR changes while stepping with set_maskisr steponly, OpenOCD should not write back the old value to mstatus when reenabling interrupts.
• target/riscv: Reset dm after unexpected resets
• target/espressif: Clear algorithm state in case of a timeout. Fixes false Target is already running an algorithm error.
• rtos/nuttx: Fixed thread details query when OS is not initialized yet. Check g_nx_initstate before providing thread details.
• rtos/freertos: Fix incorrect register values returned in p packet for ESP32-C* (RISC-V) on FreeRTOS. Close #352
• rtos/freertos: Added several sanity checks when reading the symbol table from the target.
• flash/esp: Increase hash calculation algorithm timeout to 30 sec. If the targets don't yet have clock boost functionality, reading flash through the cache takes longer than accessing the flash directly—likely due to the cache_suspend, cache_resume, and cache_invalidation functions. As a result, the previous 3-second verification timeout was insufficient for the C5, as the customer's binary takes 3.2 seconds to verify.
• target/esp_semihosting: Fixed the WSL mingw64 build error. Close #347.
• target/esp32p4: Invalidated L2 cache during cache flush in the stub flasher, improving flash breakpoint hit reliability.
• target/esp32p4: Fixed ESP_RTOS variable setting. It was previously impossible to assign any value other than FreeRTOS.
• target/esp32p4: Fixed re-examination issue after hard reset of target.
• target/esp32p4: Unstall hart0 before issuing the reset; this fixes the reset issue on halted targets caused by exceptions.

• Synced with upstream.
• tcl/esp: Make usage of esp32_devkitj_v1.cfg deprecated in favor of esp_ftdi.cfg for all Espressif FTDI dev kits.

• target/esp32c[5|61]: Temporarily disabled access to some user registers to avoid GDB errors. Registers are cycle, time, instreth, cycleh, instret, timeh, hpmcounter8, hpmcounter9, hpmcounter13, hpmcounter8h, hpmcounter9h, hpmcounter13h.

• flash: Added esp32c61 flash support.
• target/esp32c5: Added reset reason logging.
• target/esp32c61: Added reset reason logging.
• target/esp32p4: Added TCM memory as a valid memory region.
• target/espressif: Added support for printing names of extended Espressif syscalls set in the log.

• target/riscv: Call target reset handler for also resets initiated outside of OpenOCD. Previously it was called only for resets initiated by OpenOCD itself.
  Therefore reset reasons were not printed when target is reset by HW signal or via SW reset initiated due to the panic.
• target/esp32p4: Invalidate L1 ICache after writing the memory to fix the SW breakpoint miss issue.
• target/esp_riscv: Halt other cores before running bp/wp set commands. Could lead to missing bp/wp hits by other core which were running at the moment of that semihosting call.
• target/esp_riscv: Avoid apptrace data polling during reset cycle.
• tcl/esp_riscv: Configure default riscv settings for each core. Previosuly some config options were applied to the first core only.
• target/esp_riscv: Clear WDT interrupt states when the target is halted. That could lead to spontaneous interrupt WDT panics during step/continue.
• target/esp_riscv: Avoid false floating point instruction faults which are normal and handled by panic code in IDF.
• target/esp_riscv: Filter out interrupts and report exceptions reasons only.
• tcl/esp_common: Added missing global variable in configure_esp_xtensa_default_settings TCL function.

• Synchronized with upstream.

• target/espressif: Added esp32c61 initial support.
• tools: Added script to detect Espressif devkits connected to the host.

• tcl/espressif: Clear breakpoints before shutdown openocd. When openocd gets the shutdown signal, it first executes shutdown commands. After that, invokes the gdb_detach event callbacks. This is fine for the xtensa but for the riscv, command order is important. Because we will disable the DM within the shutdown command.
• target/espressif: Fix add & remove lazy breakpoint process. The bug could lead to the condition when not all breakpoints are processed (added/removed).

• target/espressif: Added command to disable lazy breakpoints. This could help to workaround problems with lazy breakpoints handling.

• target/espressif: Added base debugging support for ESP32-C5.
• target/esp32c5: Added flash support.
• target/esp32c6: Add LP core debugging support. Added special config file for debugging HP + LP cores as two HW threads.
• target/espressif: Added esp32p4 smp config.
• target/espressif: Added batch process for flash breakpoints. Now to set/clear flash breakpoints stub is loaded to target memory only once upon target resume/halt. This improves debugging speed significantly.
• flash/espressif: Added support to use stub which is built into target application binary, so there is no need to load it every time flash breakpoint needs to be set/clered. This improves debugging speed significantly.
• target/esp_riscv: Added mideleg, medeleg, mie and mip regs to the esp32c6 and esp32h2 register list.
• target/esp32p4: Enabled debug assist monitor support.
• target/esp_riscv: Added floating point registers to the register list.
• target/espressif: Add RISCV read only regs (mvendorid, marchid, mimpid, mhartid) to the register list.
• rtos/zephyr: Added thread awareness for esp32, esp32s3 and RISCV.
• target/espressif: The algorithm timeout has been decreased from 40 seconds to 3 seconds.

• rtos/freertos: Fixed ESP32-P4 reset after cleaning memory in FreeRTOS post reset handler.
• contrib/loaders: Fixed esp32s3 flash init sequence. This led to flash probe failure for octal flash chips IDF app is built w/o PSRAM support.
• rtos/FreeRTOS: Fixed unknown symbol read errors on Amazon FreeRTOS SMP version.
• target/espressif: Fixed apptrace init error on riscv chips. During apptrace init, reading invalid memory caused an issue on some riscv targets such as esp32c2 and esp32p4.
• target/espressif: Fix smp flash command handlers. They were not working properly for the 2nd core, leading an error when running the appimage_offset or stub_log commands
• loaders/esp: Fixed dynamic mmu page size issue. With the 2MB flash config, the stub flasher could not properly configure the Cache MMU, so mapping and flash breakpoints were not working.
• target/riscv: Fixed handling external reset in halted state. Previously it led to busy timeout errors.
• target/esp_riscv: Added pre-shutdown command to ensure that debug module is deactivated before exit.
• target/riscv: Increased dm idle_count by dtmcs.idle. Make OpenOCD using dtmcs.idle value to decide how long stay in RunTest/Idle state during dmi_scan.
• jtag/esp_usb_jtag: Re-init usb port when replug or hard reset detected. On Windows, libusb_reset() is not functional. Libusb prints the error AbortPipe (pipe address 02) failed: [22] The device does not recognize the command and returns with a success code. So, OpenOCD still thinks that the revive_device has been completed successfully. But still, continue to get write_error from the endpoint.

• Added win64 package

• target/esp32p4: Added flasher support.
• target/esp32p4: Added custom registers support.
• tcl/board: Added ESP32-P4 config files.
• rtos/FreeRTOS: Added ESP32-P4 support.

• flash/esp: Fixed storing of a vaddr as a paddr for DROM flash bank. Close #318.
• Some typo fixes regarding ESP / RiscV files. Close #314.
• rtos/nuttx: Added sanity checks during thread updates. Added checks for the values read from target.
• target/esp32p4: Fixed max hw bp/wp nums.
• target/esp32p4: Fixed soc reset function.
• target/esp32p4: Writeback cache before memory read/write. While halted memory access works fine with the help of fence instruction, runtime memory reads returned garbage values. The issue is resolved by performing cache synchronization before memory read/write operations.
• target/esp_riscv: Ensure reading/writing aligned memory address. SBA access requires 4 byte alignment.
• target/esp: Avoided reading invalid apptrace config addresses. We may read mem_cfg_addr as zero, when target algorithm code is not running yet. For some targets (e.g. esp32p4), reading invalid address will be an error.
• contrib/loaders/flash/esp: Fixed last data chunk padding when writing to flash. This could cause to attempt to write beyond flash boundaries.
• flash/nor/esp: Fixed target endianess handling for flash mappings structs.
• flash/esp_xtensa: Removed limitation for accessing lower flash addresses. Removes SW limitation for writing flash 0x1000 for ESP32 and ESP32-S2.
• flash/nor: Fixed handling of zero-size flash chips in get_flash_bank_by_addr. Led to assertion failure when ESP virtual flash banks have zero size, e.g. there is no app image in flash, so flah mappings are not available.

• rtos/nuttx: Updated TCB structure for the recent Nuttx changes.
• target/esp32p4: Reordered mem access to better cache handling.
• loaders/espressif: Added license info to the flasher stub headers.
• tcl/target: Renamed ESP32_ONLYCPU with ESP_ONLYCPU TCL config variable.
• tcl/target: Added esp_gcov wrapper TCL functions for esp gcov command.
• flash/esp: Avoided probing flash bank for simple flash/flasher config commands.
• Synchronized with upstream

• target/esp32p4: Added ESP32-P4 target support. Basic debugging functionality without flash support is now available.
• target/esp32{c2,c3,h2,c6}: Exposed custom CSRs for RISC-V targets.
• target/esp32{h2,c6}: Added memory protection support.
• target/espressif: Added support to print details for abort(), assert() and pseudo exception reasons.
• target/espressif: Added GDB File I/O support (https://sourceware.org/gdb/onlinedocs/gdb/File_002dI_002fO-Overview.html).
• target/espressif: Added support for stack hardware protection in RISC-V chips.
• helper/log: Added log_non_error_levels_to_stdout command to send non-error logs to stdout. This can be useful for IDEs to detect errors messages.
• jtag/drivers: Added SWD bitbang support for esp_gpio driver.
• loaders/esp32{c2,h2,c6}: Added cpu_clock_configure functionality. This allows to improve flash access speed by temporary boosting CPU clock by flasher stub.
• loaders/esp32{h2,c6}: Added flash encryption support.

• target/xtensa: Fixed GDB watchpoint hit location handling to show previous and new value. Previously watchpoint hit just before memory access and no stepping over store/load instruction was performed, so GDB did not showed old and new variable value.
• target/esp32s3: Keep APP_CPU clock gating enabled after SW reset. It avoids extra core 1 reset by IDF code which can lead to loosing breakpoints set on that core.
• target/espressif: Suppressed empty Gcov file read error. During Gcov data dump, target code tries to read existing but empty Gcov data file. So for the first dump it generates error message what actually does not indicate an error.
• target/esp_common: Fixed handling of spaces in file paths ensuring that command arguments are handled properly.

• target/espressif: DRAM used as the single work area
• tcl/espressif: Removed alt-workarea-xxx commands.
• jtag/drivers: SWD bitbang changed to use dedicated gpio for esp_gpio driver. It sould improve latency and speed of communication (https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-reference/peripherals/dedic_gpio.html).
• jtag/drivers: Renamed esp32gpio driver to esp_gpio.
• target/espressif: Removed deprecated semihost_basedir command.
• tcl/esp32: Removed deprecated program_esp32 function.
• Synced with upstream at openocd-org/openocd@3b78b5c

• target/xtensa: Added NX processors support

• esp: libjaylink and hidapi support added into the release binaries. This will allow users to debug with Segger Jlink and CMSIS-DAP compatible adapters.
• target/xtensa: Implemented hit_watchpoint callback. It made watchpoint behavior on Xtensa similar to other architectures (e.g. RISCV and ARM). Previously target was stopped just before the data are changed. Now it is stopped just after the data are changed in memory.

• target/esp: Adds check for openocd binary and .cfg file versions match. Error message is printed when user try to run openocd with configured TCL scripts directory from another OpenOCD release. See #276 (comment).
• jtag/esp_usb_jtag: Try to reset usb device on read errors. Try to reset USB JTAG device on read errors as it is done for write errors.

• esp/apptrace: Fixes 'esp sysview stop' return code. After recent changes that command always returned error.
• target/esp32h2: Fixes reset reason value.
• target/esp_riscv: Clears apptrace ctrl block address on target reset. That prevents using old apptrace ctrl block address when application image is updated w/o OpenOCD restart.

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