+58
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lines changedFilter options
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lines changed Original file line number Diff line number Diff line change
@@ -128,6 +128,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
128 128
clk_ll_bbpll_set_config(pll_freq, xtal_freq);
129 129
/* WAIT CALIBRATION DONE */
130 130
while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
131 +
esp_rom_delay_us(10);
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/* BBPLL CALIBRATION STOP */
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regi2c_ctrl_ll_bbpll_calibration_stop();
133 134
@@ -350,6 +351,24 @@ bool rtc_dig_8m_enabled(void)
350 351
return clk_ll_rc_fast_digi_is_enabled();
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}
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// Workaround for bootloader not calibrated well issue.
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// Placed in IRAM because disabling BBPLL may influence the cache
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void rtc_clk_recalib_bbpll(void)
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{
358 +
rtc_cpu_freq_config_t old_config;
359 +
rtc_clk_cpu_freq_get_config(&old_config);
360 + 361 +
// There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
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// - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
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// Turn off the BBPLL and do calibration again to fix the issue.
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// - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
365 +
// requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
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if (old_config.source == SOC_CPU_CLK_SRC_PLL) {
367 +
rtc_clk_cpu_freq_set_xtal();
368 +
rtc_clk_cpu_freq_set_config(&old_config);
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}
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}
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/* Name used in libphy.a:phy_chip_v7.o
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* TODO: update the library to use rtc_clk_xtal_freq_get
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*/
@@ -140,6 +140,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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clk_ll_bbpll_set_config(pll_freq, xtal_freq);
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// Wait until calibration finishes
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while (!regi2c_ctrl_ll_bbpll_calibration_is_done());
143 +
esp_rom_delay_us(10);
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// Prevent BBPLL clock jitter
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regi2c_ctrl_ll_bbpll_calibration_stop();
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s_cur_pll_freq = pll_freq;
@@ -162,6 +162,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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clk_ll_bbpll_set_config(pll_freq, xtal_freq);
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/* WAIT CALIBRATION DONE */
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while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
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esp_rom_delay_us(10);
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/* BBPLL CALIBRATION STOP */
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regi2c_ctrl_ll_bbpll_calibration_stop();
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@@ -458,6 +459,25 @@ static bool rtc_clk_set_bbpll_always_on(void)
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return is_bbpll_on;
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}
460 461 462 +
// Workaround for bootloader not calibrated well issue.
463 +
// Placed in IRAM because disabling BBPLL may influence the cache
464 +
void rtc_clk_recalib_bbpll(void)
465 +
{
466 +
rtc_cpu_freq_config_t old_config;
467 +
rtc_clk_cpu_freq_get_config(&old_config);
468 + 469 +
// There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
470 +
// - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
471 +
// Turn off the BBPLL and do calibration again to fix the issue.
472 +
// - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
473 +
// requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
474 +
if (old_config.source == SOC_CPU_CLK_SRC_PLL) {
475 +
rtc_clk_cpu_freq_set_xtal();
476 +
rtc_clk_cpu_freq_set_config(&old_config);
477 +
}
478 +
}
479 + 480 + 461 481
/* Name used in libphy.a:phy_chip_v7.o
462 482
* TODO: update the library to use rtc_clk_xtal_freq_get
463 483
*/
@@ -543,6 +543,15 @@ menu "ESP System Settings"
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(2). For special workflow, the chip needs do more things instead of restarting directly. This part
544 544
needs to be done in callback function of interrupt.
545 545 546 +
config ESP_SYSTEM_BBPLL_RECALIB
547 +
bool "Re-calibration BBPLL at startup"
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depends on IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3
549 +
default y
550 +
help
551 +
This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version,
552 +
which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with
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ESP-IDF version v5.2 and above.
554 + 546 555
endmenu # ESP System Settings
547 556 548 557
menu "IPC (Inter-Processor Call)"
@@ -428,8 +428,16 @@ void IRAM_ATTR call_start_cpu0(void)
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* In this stage, we re-configure the Flash (and MSPI) to required configuration
429 429
*/
430 430
spi_flash_init_chip_state();
431 + 432 +
// In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough.
433 +
// Do calibration again here so that we can use better clock for the timing tuning.
434 +
#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
435 +
extern void rtc_clk_recalib_bbpll(void);
436 +
rtc_clk_recalib_bbpll();
437 +
#endif
431 438
#if CONFIG_IDF_TARGET_ESP32S3
432 -
//On other chips, this feature is not provided by HW, or hasn't been tested yet.
439 +
// This function needs to be called when PLL is enabled
440 +
// On other chips, this feature is not provided by HW, or hasn't been tested yet.
433 441
spi_timing_flash_tuning();
434 442
#endif
435 443 You can’t perform that action at this time.
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