+50
-3
lines changedFilter options
+50
-3
lines changed Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
1 1
/*
2 -
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
2 +
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
3 3
*
4 4
* SPDX-License-Identifier: Apache-2.0
5 5
*/
@@ -57,6 +57,13 @@ esp_err_t __attribute__((weak)) bootloader_flash_unlock(void);
57 57
*/
58 58
esp_err_t bootloader_flash_reset_chip(void);
59 59 60 + 61 +
/**
62 +
* @brief Get the spi flash working mode.
63 +
*
64 +
* @return The mode of flash working mode, see `esp_rom_spiflash_read_mode_t`
65 +
*/
66 +
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void);
60 67
#ifdef __cplusplus
61 68
}
62 69
#endif
Original file line number Diff line number Diff line change
@@ -122,6 +122,9 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
122 122
#include "hal/mmu_hal.h"
123 123
#include "hal/mmu_ll.h"
124 124
#include "hal/cache_hal.h"
125 +
#if CONFIG_IDF_TARGET_ESP32S3
126 +
#include "esp32s3/rom/opi_flash.h"
127 +
#endif
125 128
static const char *TAG = "bootloader_flash";
126 129 127 130
#if CONFIG_IDF_TARGET_ESP32
@@ -433,9 +436,9 @@ void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t fla
433 436
assert(false);
434 437
break;
435 438
}
436 -
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
439 +
cache_hal_disable(CACHE_TYPE_ALL);
437 440
esp_rom_opiflash_cache_mode_config(flash_mode, &cache_rd);
438 -
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
441 +
cache_hal_enable(CACHE_TYPE_ALL);
439 442
}
440 443
#endif
441 444
@@ -810,3 +813,40 @@ esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
810 813 811 814
return ESP_OK;
812 815
}
816 + 817 +
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
818 +
{
819 +
esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
820 +
#if CONFIG_IDF_TARGET_ESP32
821 +
uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
822 +
if (spi_ctrl & SPI_FREAD_QIO) {
823 +
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
824 +
} else if (spi_ctrl & SPI_FREAD_QUAD) {
825 +
spi_mode = ESP_ROM_SPIFLASH_QOUT_MODE;
826 +
} else if (spi_ctrl & SPI_FREAD_DIO) {
827 +
spi_mode = ESP_ROM_SPIFLASH_DIO_MODE;
828 +
} else if (spi_ctrl & SPI_FREAD_DUAL) {
829 +
spi_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
830 +
} else if (spi_ctrl & SPI_FASTRD_MODE) {
831 +
spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
832 +
} else {
833 +
spi_mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
834 +
}
835 +
#else
836 +
uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
837 +
if (spi_ctrl & SPI_MEM_FREAD_QIO) {
838 +
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
839 +
} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
840 +
spi_mode = ESP_ROM_SPIFLASH_QOUT_MODE;
841 +
} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
842 +
spi_mode = ESP_ROM_SPIFLASH_DIO_MODE;
843 +
} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
844 +
spi_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
845 +
} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
846 +
spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
847 +
} else {
848 +
spi_mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
849 +
}
850 +
#endif
851 +
return spi_mode;
852 +
}
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