+12
-4
lines changedFilter options
+12
-4
lines changed Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
1 1
/*
2 -
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
2 +
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
3 3
*
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* SPDX-License-Identifier: Apache-2.0
5 5
*/
@@ -394,20 +394,28 @@ IRAM_ATTR void esp_config_instruction_cache_mode(void)
394 394 395 395
IRAM_ATTR void esp_config_data_cache_mode(void)
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{
397 +
#define CACHE_SIZE_0KB 99 //If Cache set to 0 KB, cache is bypassed, the cache size doesn't take into effect. Set this macro to a unique value for log
398 + 397 399
cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
402 -
#if CONFIG_ESP32S2_DATA_CACHE_8KB
404 +
#if CONFIG_ESP32S2_DATA_CACHE_0KB
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_0KB;
407 +
#elif CONFIG_ESP32S2_DATA_CACHE_8KB
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_8KB;
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#else
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_16KB;
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#endif
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#else
410 -
#if CONFIG_ESP32S2_DATA_CACHE_8KB
415 +
#if CONFIG_ESP32S2_DATA_CACHE_0KB
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
417 +
cache_size = CACHE_SIZE_0KB;
418 +
#elif CONFIG_ESP32S2_DATA_CACHE_8KB
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_8KB;
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#else
@@ -422,7 +430,7 @@ IRAM_ATTR void esp_config_data_cache_mode(void)
422 430
#else
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cache_line_size = CACHE_LINE_SIZE_32B;
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#endif
425 -
ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32);
433 +
ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", (cache_size == CACHE_SIZE_0KB) ? 0 : ((cache_size == CACHE_SIZE_8KB) ? 8 : 16), 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32);
426 434
Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
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Cache_Invalidate_DCache_All();
428 436
}
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