Generate code that uses (does not use) AltiVec instructions. In 32-bit code, you cannot enable AltiVec instructions unless -mabi=altivec is used on the command line.

Generate code that uses (does not use) the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture.

Generate code that uses (does not use) the string-search ‘dlmzb’ instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targeting those processors.

Generate code that uses (does not use) the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture.

Generate code that uses (does not use) the decimal floating-point instructions implemented on some POWER processors.

Generate code that uses (does not use) ISEL instruction.

Generate code that uses (does not use) the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture.

Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. These instructions are generated by default when targeting those processors.

Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions.

Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location.

Generate code that uses (does not use) the popcount and double-precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture.

Generate code that uses (does not use) the popcount instruction implemented on the POWER7 processor and other processors that support the PowerPC V2.06 architecture.

Generate code that uses (does not use) the optional PowerPC architecture instructions in the Graphics group, including floating-point select.

Generate code that uses (does not use) the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root.

Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC ABI.

Generate code that uses (does not use) the load string instructions and the store string word instructions to save multiple registers and do small block moves.

Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. In 32-bit code, you cannot enable VSX or AltiVec instructions unless -mabi=altivec is used on the command line.

Generate (do not generate) the friz instruction when the -funsafe-math-optimizations option is used to optimize rounding a floating-point value to 64-bit integer and back to floating point. The friz instruction does not return the same value if the floating-point number is too large to fit in an integer.

Generate code that tries to avoid (not avoid) the use of indexed load or store instructions.

Generate code that uses (does not use) the generation of PAIRED simd instructions.

Generate code that assumes (does not assume) that all calls are far away so that a longer more expensive calling sequence is required.

Specify the architecture to generate code for when compiling the function. If you select the target("cpu=power7") attribute when generating 32-bit code, VSX and AltiVec instructions are not generated unless you use the -mabi=altivec option on the command line.

Specify the architecture to tune for when compiling the function. If you do not specify the target("tune=TUNE") attribute and you do specify the target("cpu=CPU") attribute, compilation tunes for the CPU architecture, and not the default tuning specified on the command line.