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CUDA - Wikipedia

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Parallel computing platform and programming model

In computing, CUDA (Compute Unified Device Architecture) is a proprietary^[2] parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for accelerated general-purpose processing, an approach called general-purpose computing on GPUs. CUDA was created by Nvidia in 2006.^[3] When it was first introduced, the name was an acronym for Compute Unified Device Architecture,^[4] but Nvidia later dropped the common use of the acronym and now rarely expands it.^[5]

CUDA is a software layer that gives direct access to the GPU's virtual instruction set and parallel computational elements for the execution of compute kernels.^[6] In addition to drivers and runtime kernels, the CUDA platform includes compilers, libraries and developer tools to help programmers accelerate their applications.

CUDA is designed to work with programming languages such as C, C++, Fortran, Python and Julia. This accessibility makes it easier for specialists in parallel programming to use GPU resources, in contrast to prior APIs like Direct3D and OpenGL, which require advanced skills in graphics programming.^[7] CUDA-powered GPUs also support programming frameworks such as OpenMP, OpenACC and OpenCL.^[8][6]

The graphics processing unit (GPU), as a specialized computer processor, addresses the demands of real-time high-resolution 3D graphics compute-intensive tasks. By 2012, GPUs had evolved into highly parallel multi-core systems allowing efficient manipulation of large blocks of data. This design is more effective than general-purpose central processing unit (CPUs) for algorithms in situations where processing large blocks of data is done in parallel, such as:

• cryptographic hash functions
• machine learning
• molecular dynamics simulations
• physics engines

Ian Buck, while at Stanford in 2000, created an 8K gaming rig using 32 GeForce cards, then obtained a DARPA grant to perform general purpose parallel programming on GPUs. He then joined Nvidia, where since 2004 he has been overseeing CUDA development. In pushing for CUDA, Jensen Huang aimed for the Nvidia GPUs to become a general hardware for scientific computing. CUDA was released in 2007. Around 2015, the focus of CUDA changed to neural networks.^[9]

The following table offers a non-exact description for the ontology of CUDA framework.

1. Copy data from main memory to GPU memory
2. CPU initiates the GPU compute kernel
3. GPU's CUDA cores execute the kernel in parallel
4. Copy the resulting data from GPU memory to main memory

The CUDA platform is accessible to software developers through CUDA-accelerated libraries, compiler directives such as OpenACC, and extensions to industry-standard programming languages including C, C++, Fortran and Python. C/C++ programmers can use 'CUDA C/C++', compiled to PTX with nvcc, Nvidia's LLVM-based C/C++ compiler, or by clang itself.^[10] Fortran programmers can use 'CUDA Fortran', compiled with the PGI CUDA Fortran compiler from The Portland Group.^{[needs update]} Python programmers can use the cuNumeric library to accelerate applications on Nvidia GPUs.

In addition to libraries, compiler directives, CUDA C/C++ and CUDA Fortran, the CUDA platform supports other computational interfaces, including the Khronos Group's OpenCL,^[11] Microsoft's DirectCompute, OpenGL Compute Shader and C++ AMP.^[12] Third party wrappers are also available for Python, Perl, Fortran, Java, Ruby, Lua, Common Lisp, Haskell, R, MATLAB, IDL, Julia, and native support in Mathematica.

In the computer game industry, GPUs are used for graphics rendering, and for game physics calculations (physical effects such as debris, smoke, fire, fluids); examples include PhysX and Bullet. CUDA has also been used to accelerate non-graphical applications in computational biology, cryptography and other fields by an order of magnitude or more.^{[13][14][15][16][17]}

CUDA provides both a low level API (CUDA Driver API, non single-source) and a higher level API (CUDA Runtime API, single-source). The initial CUDA SDK was made public on 15 February 2007, for Microsoft Windows and Linux. Mac OS X support was later added in version 2.0,^[18] which supersedes the beta released February 14, 2008.^[19] CUDA works with all Nvidia GPUs from the G8x series onwards, including GeForce, Quadro and the Tesla line. CUDA is compatible with most standard operating systems.

CUDA 8.0 comes with the following libraries (for compilation & runtime, in alphabetical order):

• cuBLAS – CUDA Basic Linear Algebra Subroutines library
• CUDART – CUDA Runtime library
• cuFFT – CUDA Fast Fourier Transform library
• cuRAND – CUDA Random Number Generation library
• cuSOLVER – CUDA based collection of dense and sparse direct solvers
• cuSPARSE – CUDA Sparse Matrix library
• NPP – NVIDIA Performance Primitives library
• nvGRAPH – NVIDIA Graph Analytics library
• NVML – NVIDIA Management Library
• NVRTC – NVIDIA Runtime Compilation library for CUDA C++

CUDA 8.0 comes with these other software components:

• nView – NVIDIA nView Desktop Management Software
• NVWMI – NVIDIA Enterprise Management Toolkit
• GameWorks PhysX – is a multi-platform game physics engine

CUDA 9.0–9.2 comes with these other components:

• CUTLASS 1.0 – custom linear algebra algorithms,
• NVIDIA Video Decoder was deprecated in CUDA 9.2; it is now available in NVIDIA Video Codec SDK

CUDA 10 comes with these other components:

• nvJPEG – Hybrid (CPU and GPU) JPEG processing

CUDA 11.0–11.8 comes with these other components:^{[20][21][22][23]}

• CUB is new one of more supported C++ libraries
• MIG multi instance GPU support
• nvJPEG2000 – JPEG 2000 encoder and decoder

CUDA has several advantages over traditional general-purpose computation on GPUs (GPGPU) using graphics APIs:

• Scattered reads – code can read from arbitrary addresses in memory.
• Unified virtual memory (CUDA 4.0 and above)
• Unified memory (CUDA 6.0 and above)
• Shared memory – CUDA exposes a fast shared memory region that can be shared among threads. This can be used as a user-managed cache, enabling higher bandwidth than is possible using texture lookups.^[24]
• Faster downloads and readbacks to and from the GPU
• Full support for integer and bitwise operations, including integer texture lookups

• Whether for the host computer or the GPU device, all CUDA source code is now processed according to C++ syntax rules.^[25] This was not always the case. Earlier versions of CUDA were based on C syntax rules.^[26] As with the more general case of compiling C code with a C++ compiler, it is therefore possible that old C-style CUDA source code will either fail to compile or will not behave as originally intended.
• Interoperability with rendering languages such as OpenGL is one-way, with OpenGL having access to registered CUDA memory but CUDA not having access to OpenGL memory.
• Copying between host and device memory may incur a performance hit due to system bus bandwidth and latency (this can be partly alleviated with asynchronous memory transfers, handled by the GPU's DMA engine).
• Threads should be running in groups of at least 32 for best performance, with total number of threads numbering in the thousands. Branches in the program code do not affect performance significantly, provided that each of 32 threads takes the same execution path; the SIMD execution model becomes a significant limitation for any inherently divergent task (e.g. traversing a space partitioning data structure during ray tracing).
• No emulation or fallback functionality is available for modern revisions.
• Valid C++ may sometimes be flagged and prevent compilation due to the way the compiler approaches optimization for target GPU device limitations.^{[citation needed]}
• C++ run-time type information (RTTI) and C++-style exception handling are only supported in host code, not in device code.
• In single-precision on first generation CUDA compute capability 1.x devices, denormal numbers are unsupported and are instead flushed to zero, and the precision of both the division and square root operations are slightly lower than IEEE 754-compliant single precision math. Devices that support compute capability 2.0 and above support denormal numbers, and the division and square root operations are IEEE 754 compliant by default. However, users can obtain the prior faster gaming-grade math of compute capability 1.x devices if desired by setting compiler flags to disable accurate divisions and accurate square roots, and enable flushing denormal numbers to zero.^[27]
• Unlike OpenCL, CUDA-enabled GPUs are only available from Nvidia as it is proprietary.^[28][2] Attempts to implement CUDA on other GPUs include:
  • Project Coriander: Converts CUDA C++11 source to OpenCL 1.2 C. A fork of CUDA-on-CL intended to run TensorFlow.^[29][30][31]
  • CU2CL: Convert CUDA 3.2 C++ to OpenCL C.^[32]
  • GPUOpen HIP: A thin abstraction layer on top of CUDA and ROCm intended for AMD and Nvidia GPUs. Has a conversion tool for importing CUDA C++ source. Supports CUDA 4.0 plus C++11 and float16.
  • ZLUDA is a drop-in replacement for CUDA on AMD GPUs and formerly Intel GPUs with near-native performance.^[33] The developer, Andrzej Janik, was separately contracted by both Intel and AMD to develop the software in 2021 and 2022, respectively. However, neither company decided to release it officially due to the lack of a business use case. AMD's contract included a clause that allowed Janik to release his code for AMD independently, allowing him to release the new version that only supports AMD GPUs.^[34]
  • chipStar can compile and run CUDA/HIP programs on advanced OpenCL 3.0 or Level Zero platforms.^[35]

This example code in C++ loads a texture from an image into an array on the GPU:

texture<float, 2, cudaReadModeElementType> tex;

void foo()
{
  cudaArray* cu_array;

  // Allocate array
  cudaChannelFormatDesc description = cudaCreateChannelDesc<float>();
  cudaMallocArray(&cu_array, &description, width, height);

  // Copy image data to array
  cudaMemcpyToArray(cu_array, image, width*height*sizeof(float), cudaMemcpyHostToDevice);

  // Set texture parameters (default)
  tex.addressMode[0] = cudaAddressModeClamp;
  tex.addressMode[1] = cudaAddressModeClamp;
  tex.filterMode = cudaFilterModePoint;
  tex.normalized = false; // do not normalize coordinates

  // Bind the array to the texture
  cudaBindTextureToArray(tex, cu_array);

  // Run kernel
  dim3 blockDim(16, 16, 1);
  dim3 gridDim((width + blockDim.x - 1)/ blockDim.x, (height + blockDim.y - 1) / blockDim.y, 1);
  kernel<<< gridDim, blockDim, 0 >>>(d_data, height, width);

  // Unbind the array from the texture
  cudaUnbindTexture(tex);
} //end foo()

__global__ void kernel(float* odata, int height, int width)
{
   unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
   unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
   if (x < width && y < height) {
      float c = tex2D(tex, x, y);
      odata[y*width+x] = c;
   }
}

Below is an example given in Python that computes the product of two arrays on the GPU. The unofficial Python language bindings can be obtained from PyCUDA.^[36]

import pycuda.compiler as comp
import pycuda.driver as drv
import numpy
import pycuda.autoinit

mod = comp.SourceModule(
    """
__global__ void multiply_them(float *dest, float *a, float *b)
{
  const int i = threadIdx.x;
  dest[i] = a[i] * b[i];
}
"""
)

multiply_them = mod.get_function("multiply_them")

a = numpy.random.randn(400).astype(numpy.float32)
b = numpy.random.randn(400).astype(numpy.float32)

dest = numpy.zeros_like(a)
multiply_them(drv.Out(dest), drv.In(a), drv.In(b), block=(400, 1, 1))

print(dest - a * b)

Additional Python bindings to simplify matrix multiplication operations can be found in the program pycublas.^[37]

 
import numpy
from pycublas import CUBLASMatrix

A = CUBLASMatrix(numpy.mat([[1, 2, 3], [4, 5, 6]], numpy.float32))
B = CUBLASMatrix(numpy.mat([[2, 3], [4, 5], [6, 7]], numpy.float32))
C = A * B
print(C.np_mat())

while CuPy directly replaces NumPy:^[38]

import cupy

a = cupy.random.randn(400)
b = cupy.random.randn(400)

dest = cupy.zeros_like(a)

print(dest - a * b)

Supported CUDA compute capability versions for CUDA SDK version and microarchitecture (by code name):

Note: CUDA SDK 10.2 is the last official release for macOS, as support will not be available for macOS in newer releases.

CUDA compute capability by version with associated GPU semiconductors and GPU card models (separated by their various application areas):

* – OEM-only products

^[58]

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.^[59]

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.^{[63][64] [65] [66] [67] [68]}

^{[76][77][78][79]}

^[81]

^[82]

For more information read the Nvidia CUDA C++ Programming Guide.^[115]

• Accelerated rendering of 3D graphics
• Accelerated interconversion of video file formats
• Accelerated encryption, decryption and compression
• Bioinformatics, e.g. NGS DNA sequencing BarraCUDA^[116]
• Distributed calculations, such as predicting the native conformation of proteins
• Medical analysis simulations, for example virtual reality based on CT and MRI scan images
• Physical simulations,^[117] particularly in fluid dynamics
• Neural network training in machine learning problems
• Large Language Model inference
• Face recognition
• Volunteer computing projects, such as SETI@home and other projects using BOINC software
• Molecular dynamics
• Mining cryptocurrencies
• Structure from motion (SfM) software

CUDA competes with other GPU computing stacks: Intel OneAPI and AMD ROCm.

Whereas Nvidia's CUDA is closed-source, Intel's OneAPI and AMD's ROCm are open source.

oneAPI is an initiative based in open standards, created to support software development for multiple hardware architectures.^[118] The oneAPI libraries must implement open specifications that are discussed publicly by the Special Interest Groups, offering the possibility for any developer or organization to implement their own versions of oneAPI libraries.^[119][120]

Originally made by Intel, other hardware adopters include Fujitsu and Huawei.

Unified Acceleration Foundation (UXL) is a new technology consortium working on the continuation of the OneAPI initiative, with the goal to create a new open standard accelerator software ecosystem, related open standards and specification projects through Working Groups and Special Interest Groups (SIGs). The goal is to offer open alternatives to Nvidia's CUDA. The main companies behind it are Intel, Google, ARM, Qualcomm, Samsung, Imagination, and VMware.^[121]

ROCm^[122] is an open source software stack for graphics processing unit (GPU) programming from Advanced Micro Devices (AMD).

• SYCL – an open standard from Khronos Group for programming a variety of platforms, including GPUs, with single-source modern C++, similar to higher-level CUDA Runtime API (single-source)
• BrookGPU – the Stanford University graphics group's compiler
• Array programming
• Parallel computing
• Stream processing
• rCUDA – an API for computing on remote computers
• Molecular modeling on GPUs
• Vulkan – low-level, high-performance 3D graphics and computing API
• OptiX – ray tracing API by NVIDIA
• CUDA binary (cubin) – a type of fat binary
• Numerical Library Collection – by NEC for their vector processor

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60. ^ Fused-Multiply-Add, actually executed, Dense Matrix
61. ^ as SASS since 7.5, as PTX since 8.0
62. ^ ^{a b} unofficial support in SASS
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74. ^ ^{a b} = product first 3 table rows
75. ^ ^{a b} = product of previous 2 table rows; shape: e.g. 8x8x4xFP16 = 512 Bytes
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83. ^ dependent on device
84. ^ ^{a b} "Tegra X1". 9 January 2015.
85. ^ NVIDIA H100 Tensor Core GPU Architecture
86. ^ H.1. Features and Technical Specifications – Table 14. Technical Specifications per Compute Capability
87. ^ NVIDIA Hopper Architecture In-Depth
88. ^ can only execute 160 integer instructions according to programming guide
89. ^ 128 according to [1]. 64 from FP32 + 64 separate units?
90. ^ 64 by FP32 cores and 64 by flexible FP32/INT cores.
91. ^ "CUDA C++ Programming Guide".
92. ^ 32 FP32 lanes combine to 16 FP64 lanes. Maybe lower depending on model.
93. ^ only supported by 16 FP32 lanes, they combine to 4 FP64 lanes
94. ^ ^{a b c d e f} depending on model
95. ^ Effective speed, probably over FP32 ports. No description of actual FP64 cores.
96. ^ Can also be used for integer additions and comparisons
97. ^ 2 clock cycles/instruction for each SM partition Burgess, John (2019). "RTX ON – The NVIDIA TURING GPU". 2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27. doi:10.1109/HOTCHIPS.2019.8875651. ISBN 978-1-7281-2089-8. S2CID 204822166.
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99. ^ The schedulers and dispatchers have dedicated execution units unlike with Fermi and Kepler.
100. ^ Dispatching can overlap concurrently, if it takes more than one cycle (when there are less execution units than 32/SM Partition)
101. ^ Can dual issue MAD pipe and SFU pipe
102. ^ No more than one scheduler can issue 2 instructions at once. The first scheduler is in charge of warps with odd IDs. The second scheduler is in charge of warps with even IDs.
103. ^ ^{a b c d e f} shared memory separate, but L1 includes texture cache
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111. ^ ^{a b} for access with texture engine only
112. ^ 25% disabled on RTX 4060, RTX 4070, RTX 4070 Ti and RTX 4090
113. ^ 25% disabled on RTX 5070 Ti and RTX 5090
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• Official website

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