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Showing content from https://clang.llvm.org/doxygen/SemaRISCV_8cpp_source.html below:

clang: lib/Sema/SemaRISCV.cpp Source File

;

RVVIntrinsicDef {

std::string BuiltinName;

RVVOverloadIntrinsicDef {

IntrinsicKind::RVV:

IntrinsicKind::SIFIVE_VECTOR:

llvm_unreachable(

);

(

->getScalarType()) {

ScalarTypeKind::Void:

ScalarTypeKind::Size_t:

ScalarTypeKind::Ptrdiff_t:

ScalarTypeKind::UnsignedLong:

ScalarTypeKind::SignedLong:

ScalarTypeKind::Boolean:

ScalarTypeKind::SignedInteger:

ScalarTypeKind::UnsignedInteger:

ScalarTypeKind::BFloat:

ScalarTypeKind::Float:

(

->getElementBitwidth()) {

llvm_unreachable(

);

llvm_unreachable(

);

(

->isVector()) {

(

->isTuple())

(

->isConstant())

(

->isPointer())

ConstructedRISCVVBuiltins;

ConstructedRISCVSiFiveVectorBuiltins;

std::vector<RVVIntrinsicDef> IntrinsicList;

StringMap<uint32_t> Intrinsics;

StringMap<RVVOverloadIntrinsicDef> OverloadIntrinsics;

StringRef OverloadedSuffixStr,

IsMask,

RISCVIntrinsicManagerImpl(

&S) : S(S), Context(S.Context) {

ConstructedRISCVVBuiltins =

;

ConstructedRISCVSiFiveVectorBuiltins =

;

RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(

std::pair<const char *, RVVRequire> FeatureCheckList[] = {

(

&

: Recs) {

(llvm::any_of(FeatureCheckList, [&](

&Item) {

(

.RequiredExtensions & Item.second) == Item.second &&

K,

.OverloadedSuffixIndex,

.OverloadedSuffixSize);

DefaultPolicy;

BasicProtoSeq,

,

UnMaskedPolicyScheme, DefaultPolicy,

.IsTuple);

BasicProtoSeq,

,

.HasMaskedOffOperand,

.HasVL,

.NF, MaskedPolicyScheme, DefaultPolicy,

UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone;

MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone;

(

TypeRangeMaskShift = 0;

TypeRangeMaskShift <= static_cast<unsigned int>(BasicType::MaxOffset);

++TypeRangeMaskShift) {

BaseTypeI = 1 << TypeRangeMaskShift;

BaseType =

(BaseTypeI);

((BaseTypeI &

.TypeRangeMask) != BaseTypeI)

(

Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {

(!(

.Log2LMULMask & (1 << (Log2LMUL + 3))))

std::optional<RVVTypes> Types =

TypeCache.computeTypes(BaseType, Log2LMUL,

.NF, ProtoSeq);

(!Types.has_value())

TypeCache, BaseType, Log2LMUL, SuffixProto);

TypeCache, BaseType, Log2LMUL, OverloadedSuffixProto);

InitRVVIntrinsic(

, SuffixStr, OverloadedSuffixStr,

, *Types,

UnMaskedHasPolicy, DefaultPolicy);

(

.UnMaskedPolicyScheme != PolicyScheme::SchemeNone) {

(

: SupportedUnMaskedPolicies) {

BasicProtoSeq,

,

UnMaskedPolicyScheme,

,

.IsTuple);

std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(

BaseType, Log2LMUL,

.NF, PolicyPrototype);

InitRVVIntrinsic(

, SuffixStr, OverloadedSuffixStr,

, *PolicyTypes, UnMaskedHasPolicy,

std::optional<RVVTypes> MaskTypes =

TypeCache.computeTypes(BaseType, Log2LMUL,

.NF, ProtoMaskSeq);

InitRVVIntrinsic(

, SuffixStr, OverloadedSuffixStr,

,

*MaskTypes, MaskedHasPolicy, DefaultPolicy);

(

.MaskedPolicyScheme == PolicyScheme::SchemeNone)

(

: SupportedMaskedPolicies) {

BasicProtoSeq,

,

.HasMaskedOffOperand,

std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(

BaseType, Log2LMUL,

.NF, PolicyPrototype);

InitRVVIntrinsic(

, SuffixStr, OverloadedSuffixStr,

, *PolicyTypes, MaskedHasPolicy,

);

RISCVIntrinsicManagerImpl::InitIntrinsicList() {

ConstructedRISCVVBuiltins =

;

!ConstructedRISCVSiFiveVectorBuiltins) {

ConstructedRISCVSiFiveVectorBuiltins =

;

IntrinsicKind::SIFIVE_VECTOR);

RISCVIntrinsicManagerImpl::InitRVVIntrinsic(

StringRef OverloadedSuffixStr,

IsMasked,

&Signature,

HasPolicy,

PolicyAttrs) {

std::string Name =

.Name;

(!SuffixStr.empty())

Name +=

+ SuffixStr.str();

std::string OverloadedName;

(!

.OverloadedName)

OverloadedName = StringRef(

.Name).split(

).first.str();

OverloadedName =

.OverloadedName;

(!OverloadedSuffixStr.empty())

OverloadedName +=

+ OverloadedSuffixStr.str();

std::string BuiltinName = std::string(

.Name);

OverloadedName, PolicyAttrs,

.HasFRMRoundModeOp);

Index = IntrinsicList.size();

assert(IntrinsicList.size() == (

)Index &&

);

IntrinsicList.push_back({BuiltinName, Signature});

Intrinsics.insert({Name, Index});

RVVOverloadIntrinsicDef &OverloadIntrinsicDef =

OverloadIntrinsics[OverloadedName];

OverloadIntrinsicDef.Indexes.push_back(Index);

RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(

&LR,

RVVIntrinsicDef &IDef = IntrinsicList[Index];

SigLength = Sigs.size();

(

i = 1; i < SigLength; ++i)

PI.Variadic =

;

Context,

,

,

, II, BuiltinFuncType,

,

*FP = cast<FunctionProtoType>(BuiltinFuncType);

(

IParm = 0,

= FP->getNumParams(); IParm !=

; ++IParm) {

FP->getParamType(IParm),

,

,

);

ParmList.push_back(Parm);

RVVIntrinsicDecl->setParams(ParmList);

RVVIntrinsicDecl->

(OverloadableAttr::CreateImplicit(Context));

BuiltinAliasAttr::CreateImplicit(S.

, &IntrinsicII));

LR.

(RVVIntrinsicDecl);

RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(

&LR,

StringRef Name = II->

();

(!Name.consume_front(

))

OvIItr = OverloadIntrinsics.find(Name);

(OvIItr != OverloadIntrinsics.end()) {

RVVOverloadIntrinsicDef &OvIntrinsicDef = OvIItr->second;

(

Index : OvIntrinsicDef.Indexes)

CreateRVVIntrinsicDecl(LR, II, PP, Index,

Itr = Intrinsics.find(Name);

(Itr != Intrinsics.end()) {

CreateRVVIntrinsicDecl(LR, II, PP, Itr->second,

std::unique_ptr<clang::sema::RISCVIntrinsicManager>

std::make_unique<RISCVIntrinsicManagerImpl>(S);

int64_t Val =

.getSExtValue();

((Val >= 0 && Val <= 3) || (Val >= 5 && Val <= 7))

(TheCall->

(), diag::err_riscv_builtin_invalid_lmul)

assert((EGW == 128 || EGW == 256) &&

);

MinElemCount = Info.

.getKnownMinValue();

EGS = EGW / ElemSize;

(EGS <= MinElemCount)

assert(EGS % MinElemCount == 0);

VScaleFactor = EGS / MinElemCount;

MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;

std::string RequiredExt =

+ std::to_string(MinRequiredVLEN) +

;

diag::err_riscv_type_requires_extension)

<<

<< RequiredExt;

RISCVVector::BI__builtin_rvv_vmulhsu_vv:

RISCVVector::BI__builtin_rvv_vmulhsu_vx:

RISCVVector::BI__builtin_rvv_vmulhsu_vv_tu:

RISCVVector::BI__builtin_rvv_vmulhsu_vx_tu:

RISCVVector::BI__builtin_rvv_vmulhsu_vv_m:

RISCVVector::BI__builtin_rvv_vmulhsu_vx_m:

RISCVVector::BI__builtin_rvv_vmulhsu_vv_mu:

RISCVVector::BI__builtin_rvv_vmulhsu_vx_mu:

RISCVVector::BI__builtin_rvv_vmulhsu_vv_tum:

RISCVVector::BI__builtin_rvv_vmulhsu_vx_tum:

RISCVVector::BI__builtin_rvv_vmulhsu_vv_tumu:

RISCVVector::BI__builtin_rvv_vmulhsu_vx_tumu:

RISCVVector::BI__builtin_rvv_vmulhu_vv:

RISCVVector::BI__builtin_rvv_vmulhu_vx:

RISCVVector::BI__builtin_rvv_vmulhu_vv_tu:

RISCVVector::BI__builtin_rvv_vmulhu_vx_tu:

RISCVVector::BI__builtin_rvv_vmulhu_vv_m:

RISCVVector::BI__builtin_rvv_vmulhu_vx_m:

RISCVVector::BI__builtin_rvv_vmulhu_vv_mu:

RISCVVector::BI__builtin_rvv_vmulhu_vx_mu:

RISCVVector::BI__builtin_rvv_vmulhu_vv_tum:

RISCVVector::BI__builtin_rvv_vmulhu_vx_tum:

RISCVVector::BI__builtin_rvv_vmulhu_vv_tumu:

RISCVVector::BI__builtin_rvv_vmulhu_vx_tumu:

RISCVVector::BI__builtin_rvv_vmulh_vv:

RISCVVector::BI__builtin_rvv_vmulh_vx:

RISCVVector::BI__builtin_rvv_vmulh_vv_tu:

RISCVVector::BI__builtin_rvv_vmulh_vx_tu:

RISCVVector::BI__builtin_rvv_vmulh_vv_m:

RISCVVector::BI__builtin_rvv_vmulh_vx_m:

RISCVVector::BI__builtin_rvv_vmulh_vv_mu:

RISCVVector::BI__builtin_rvv_vmulh_vx_mu:

RISCVVector::BI__builtin_rvv_vmulh_vv_tum:

RISCVVector::BI__builtin_rvv_vmulh_vx_tum:

RISCVVector::BI__builtin_rvv_vmulh_vv_tumu:

RISCVVector::BI__builtin_rvv_vmulh_vx_tumu:

RISCVVector::BI__builtin_rvv_vsmul_vv:

RISCVVector::BI__builtin_rvv_vsmul_vx:

RISCVVector::BI__builtin_rvv_vsmul_vv_tu:

RISCVVector::BI__builtin_rvv_vsmul_vx_tu:

RISCVVector::BI__builtin_rvv_vsmul_vv_m:

RISCVVector::BI__builtin_rvv_vsmul_vx_m:

RISCVVector::BI__builtin_rvv_vsmul_vv_mu:

RISCVVector::BI__builtin_rvv_vsmul_vx_mu:

RISCVVector::BI__builtin_rvv_vsmul_vv_tum:

RISCVVector::BI__builtin_rvv_vsmul_vx_tum:

RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:

RISCVVector::BI__builtin_rvv_vsmul_vx_tumu: {

llvm::StringMap<bool> FunctionFeatureMap;

!FunctionFeatureMap.lookup(

))

diag::err_riscv_builtin_requires_extension)

RISCVVector::BI__builtin_rvv_vsetvli:

RISCVVector::BI__builtin_rvv_vsetvlimax:

RISCVVector::BI__builtin_rvv_vget_v: {

MaxIndex = (VecInfo.

.getKnownMinValue() * VecInfo.

) /

(ResVecInfo.

.getKnownMinValue() * ResVecInfo.

);

RISCVVector::BI__builtin_rvv_vset_v: {

MaxIndex = (ResVecInfo.

.getKnownMinValue() * ResVecInfo.

) /

(VecInfo.

.getKnownMinValue() * VecInfo.

);

RISCVVector::BI__builtin_rvv_vaeskf1_vi_tu:

RISCVVector::BI__builtin_rvv_vaeskf2_vi_tu:

RISCVVector::BI__builtin_rvv_vaeskf2_vi:

RISCVVector::BI__builtin_rvv_vsm4k_vi_tu: {

RISCVVector::BI__builtin_rvv_vsm3c_vi_tu:

RISCVVector::BI__builtin_rvv_vsm3c_vi: {

RISCVVector::BI__builtin_rvv_vaeskf1_vi:

RISCVVector::BI__builtin_rvv_vsm4k_vi: {

RISCVVector::BI__builtin_rvv_vaesdf_vv:

RISCVVector::BI__builtin_rvv_vaesdf_vs:

RISCVVector::BI__builtin_rvv_vaesdm_vv:

RISCVVector::BI__builtin_rvv_vaesdm_vs:

RISCVVector::BI__builtin_rvv_vaesef_vv:

RISCVVector::BI__builtin_rvv_vaesef_vs:

RISCVVector::BI__builtin_rvv_vaesem_vv:

RISCVVector::BI__builtin_rvv_vaesem_vs:

RISCVVector::BI__builtin_rvv_vaesz_vs:

RISCVVector::BI__builtin_rvv_vsm4r_vv:

RISCVVector::BI__builtin_rvv_vsm4r_vs:

RISCVVector::BI__builtin_rvv_vaesdf_vv_tu:

RISCVVector::BI__builtin_rvv_vaesdf_vs_tu:

RISCVVector::BI__builtin_rvv_vaesdm_vv_tu:

RISCVVector::BI__builtin_rvv_vaesdm_vs_tu:

RISCVVector::BI__builtin_rvv_vaesef_vv_tu:

RISCVVector::BI__builtin_rvv_vaesef_vs_tu:

RISCVVector::BI__builtin_rvv_vaesem_vv_tu:

RISCVVector::BI__builtin_rvv_vaesem_vs_tu:

RISCVVector::BI__builtin_rvv_vaesz_vs_tu:

RISCVVector::BI__builtin_rvv_vsm4r_vv_tu:

RISCVVector::BI__builtin_rvv_vsm4r_vs_tu: {

RISCVVector::BI__builtin_rvv_vsha2ch_vv:

RISCVVector::BI__builtin_rvv_vsha2cl_vv:

RISCVVector::BI__builtin_rvv_vsha2ms_vv:

RISCVVector::BI__builtin_rvv_vsha2ch_vv_tu:

RISCVVector::BI__builtin_rvv_vsha2cl_vv_tu:

RISCVVector::BI__builtin_rvv_vsha2ms_vv_tu: {

(ElemSize == 64 && !TI.

(

))

diag::err_riscv_builtin_requires_extension)

RISCVVector::BI__builtin_rvv_sf_vc_i_se:

RISCVVector::BI__builtin_rvv_sf_vc_iv_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_i:

RISCVVector::BI__builtin_rvv_sf_vc_v_i_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_iv:

RISCVVector::BI__builtin_rvv_sf_vc_v_iv_se:

RISCVVector::BI__builtin_rvv_sf_vc_ivv_se:

RISCVVector::BI__builtin_rvv_sf_vc_ivw_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_ivv:

RISCVVector::BI__builtin_rvv_sf_vc_v_ivw:

RISCVVector::BI__builtin_rvv_sf_vc_v_ivv_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_ivw_se:

RISCVVector::BI__builtin_rvv_sf_vc_x_se:

RISCVVector::BI__builtin_rvv_sf_vc_xv_se:

RISCVVector::BI__builtin_rvv_sf_vc_vv_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_x:

RISCVVector::BI__builtin_rvv_sf_vc_v_x_se:

RISCVVector::BI__builtin_rvv_sf_vc_vvv_se:

RISCVVector::BI__builtin_rvv_sf_vc_xvv_se:

RISCVVector::BI__builtin_rvv_sf_vc_vvw_se:

RISCVVector::BI__builtin_rvv_sf_vc_xvw_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_xv:

RISCVVector::BI__builtin_rvv_sf_vc_v_vv:

RISCVVector::BI__builtin_rvv_sf_vc_v_xv_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_vv_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_xvv:

RISCVVector::BI__builtin_rvv_sf_vc_v_vvv:

RISCVVector::BI__builtin_rvv_sf_vc_v_xvw:

RISCVVector::BI__builtin_rvv_sf_vc_v_vvw:

RISCVVector::BI__builtin_rvv_sf_vc_v_xvv_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_vvv_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_xvw_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_vvw_se:

RISCVVector::BI__builtin_rvv_sf_vc_fv_se:

RISCVVector::BI__builtin_rvv_sf_vc_fvv_se:

RISCVVector::BI__builtin_rvv_sf_vc_fvw_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_fvv:

RISCVVector::BI__builtin_rvv_sf_vc_v_fvw:

RISCVVector::BI__builtin_rvv_sf_vc_v_fvv_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_fvw_se:

RISCVVector::BI__builtin_rvv_sf_vc_v_fv:

RISCVVector::BI__builtin_rvv_sf_vc_v_fv_se:

RISCV::BI__builtin_riscv_aes32dsi:

RISCV::BI__builtin_riscv_aes32dsmi:

RISCV::BI__builtin_riscv_aes32esi:

RISCV::BI__builtin_riscv_aes32esmi:

RISCV::BI__builtin_riscv_sm4ks:

RISCV::BI__builtin_riscv_sm4ed:

RISCV::BI__builtin_riscv_aes64ks1i:

RISCVVector::BI__builtin_rvv_vaaddu_vv:

RISCVVector::BI__builtin_rvv_vaaddu_vx:

RISCVVector::BI__builtin_rvv_vaadd_vv:

RISCVVector::BI__builtin_rvv_vaadd_vx:

RISCVVector::BI__builtin_rvv_vasubu_vv:

RISCVVector::BI__builtin_rvv_vasubu_vx:

RISCVVector::BI__builtin_rvv_vasub_vv:

RISCVVector::BI__builtin_rvv_vasub_vx:

RISCVVector::BI__builtin_rvv_vsmul_vv:

RISCVVector::BI__builtin_rvv_vsmul_vx:

RISCVVector::BI__builtin_rvv_vssra_vv:

RISCVVector::BI__builtin_rvv_vssra_vx:

RISCVVector::BI__builtin_rvv_vssrl_vv:

RISCVVector::BI__builtin_rvv_vssrl_vx:

RISCVVector::BI__builtin_rvv_vnclip_wv:

RISCVVector::BI__builtin_rvv_vnclip_wx:

RISCVVector::BI__builtin_rvv_vnclipu_wv:

RISCVVector::BI__builtin_rvv_vnclipu_wx:

RISCVVector::BI__builtin_rvv_vaaddu_vv_tu:

RISCVVector::BI__builtin_rvv_vaaddu_vx_tu:

RISCVVector::BI__builtin_rvv_vaadd_vv_tu:

RISCVVector::BI__builtin_rvv_vaadd_vx_tu:

RISCVVector::BI__builtin_rvv_vasubu_vv_tu:

RISCVVector::BI__builtin_rvv_vasubu_vx_tu:

RISCVVector::BI__builtin_rvv_vasub_vv_tu:

RISCVVector::BI__builtin_rvv_vasub_vx_tu:

RISCVVector::BI__builtin_rvv_vsmul_vv_tu:

RISCVVector::BI__builtin_rvv_vsmul_vx_tu:

RISCVVector::BI__builtin_rvv_vssra_vv_tu:

RISCVVector::BI__builtin_rvv_vssra_vx_tu:

RISCVVector::BI__builtin_rvv_vssrl_vv_tu:

RISCVVector::BI__builtin_rvv_vssrl_vx_tu:

RISCVVector::BI__builtin_rvv_vnclip_wv_tu:

RISCVVector::BI__builtin_rvv_vnclip_wx_tu:

RISCVVector::BI__builtin_rvv_vnclipu_wv_tu:

RISCVVector::BI__builtin_rvv_vnclipu_wx_tu:

RISCVVector::BI__builtin_rvv_vaaddu_vv_m:

RISCVVector::BI__builtin_rvv_vaaddu_vx_m:

RISCVVector::BI__builtin_rvv_vaadd_vv_m:

RISCVVector::BI__builtin_rvv_vaadd_vx_m:

RISCVVector::BI__builtin_rvv_vasubu_vv_m:

RISCVVector::BI__builtin_rvv_vasubu_vx_m:

RISCVVector::BI__builtin_rvv_vasub_vv_m:

RISCVVector::BI__builtin_rvv_vasub_vx_m:

RISCVVector::BI__builtin_rvv_vsmul_vv_m:

RISCVVector::BI__builtin_rvv_vsmul_vx_m:

RISCVVector::BI__builtin_rvv_vssra_vv_m:

RISCVVector::BI__builtin_rvv_vssra_vx_m:

RISCVVector::BI__builtin_rvv_vssrl_vv_m:

RISCVVector::BI__builtin_rvv_vssrl_vx_m:

RISCVVector::BI__builtin_rvv_vnclip_wv_m:

RISCVVector::BI__builtin_rvv_vnclip_wx_m:

RISCVVector::BI__builtin_rvv_vnclipu_wv_m:

RISCVVector::BI__builtin_rvv_vnclipu_wx_m:

RISCVVector::BI__builtin_rvv_vaaddu_vv_tum:

RISCVVector::BI__builtin_rvv_vaaddu_vv_tumu:

RISCVVector::BI__builtin_rvv_vaaddu_vv_mu:

RISCVVector::BI__builtin_rvv_vaaddu_vx_tum:

RISCVVector::BI__builtin_rvv_vaaddu_vx_tumu:

RISCVVector::BI__builtin_rvv_vaaddu_vx_mu:

RISCVVector::BI__builtin_rvv_vaadd_vv_tum:

RISCVVector::BI__builtin_rvv_vaadd_vv_tumu:

RISCVVector::BI__builtin_rvv_vaadd_vv_mu:

RISCVVector::BI__builtin_rvv_vaadd_vx_tum:

RISCVVector::BI__builtin_rvv_vaadd_vx_tumu:

RISCVVector::BI__builtin_rvv_vaadd_vx_mu:

RISCVVector::BI__builtin_rvv_vasubu_vv_tum:

RISCVVector::BI__builtin_rvv_vasubu_vv_tumu:

RISCVVector::BI__builtin_rvv_vasubu_vv_mu:

RISCVVector::BI__builtin_rvv_vasubu_vx_tum:

RISCVVector::BI__builtin_rvv_vasubu_vx_tumu:

RISCVVector::BI__builtin_rvv_vasubu_vx_mu:

RISCVVector::BI__builtin_rvv_vasub_vv_tum:

RISCVVector::BI__builtin_rvv_vasub_vv_tumu:

RISCVVector::BI__builtin_rvv_vasub_vv_mu:

RISCVVector::BI__builtin_rvv_vasub_vx_tum:

RISCVVector::BI__builtin_rvv_vasub_vx_tumu:

RISCVVector::BI__builtin_rvv_vasub_vx_mu:

RISCVVector::BI__builtin_rvv_vsmul_vv_mu:

RISCVVector::BI__builtin_rvv_vsmul_vx_mu:

RISCVVector::BI__builtin_rvv_vssra_vv_mu:

RISCVVector::BI__builtin_rvv_vssra_vx_mu:

RISCVVector::BI__builtin_rvv_vssrl_vv_mu:

RISCVVector::BI__builtin_rvv_vssrl_vx_mu:

RISCVVector::BI__builtin_rvv_vnclip_wv_mu:

RISCVVector::BI__builtin_rvv_vnclip_wx_mu:

RISCVVector::BI__builtin_rvv_vnclipu_wv_mu:

RISCVVector::BI__builtin_rvv_vnclipu_wx_mu:

RISCVVector::BI__builtin_rvv_vsmul_vv_tum:

RISCVVector::BI__builtin_rvv_vsmul_vx_tum:

RISCVVector::BI__builtin_rvv_vssra_vv_tum:

RISCVVector::BI__builtin_rvv_vssra_vx_tum:

RISCVVector::BI__builtin_rvv_vssrl_vv_tum:

RISCVVector::BI__builtin_rvv_vssrl_vx_tum:

RISCVVector::BI__builtin_rvv_vnclip_wv_tum:

RISCVVector::BI__builtin_rvv_vnclip_wx_tum:

RISCVVector::BI__builtin_rvv_vnclipu_wv_tum:

RISCVVector::BI__builtin_rvv_vnclipu_wx_tum:

RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:

RISCVVector::BI__builtin_rvv_vsmul_vx_tumu:

RISCVVector::BI__builtin_rvv_vssra_vv_tumu:

RISCVVector::BI__builtin_rvv_vssra_vx_tumu:

RISCVVector::BI__builtin_rvv_vssrl_vv_tumu:

RISCVVector::BI__builtin_rvv_vssrl_vx_tumu:

RISCVVector::BI__builtin_rvv_vnclip_wv_tumu:

RISCVVector::BI__builtin_rvv_vnclip_wx_tumu:

RISCVVector::BI__builtin_rvv_vnclipu_wv_tumu:

RISCVVector::BI__builtin_rvv_vnclipu_wx_tumu:

RISCVVector::BI__builtin_rvv_vfsqrt_v_rm:

RISCVVector::BI__builtin_rvv_vfrec7_v_rm:

RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm:

RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm:

RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm:

RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm:

RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm:

RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm:

RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm:

RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm:

RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm:

RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm:

RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm:

RISCVVector::BI__builtin_rvv_vfadd_vv_rm:

RISCVVector::BI__builtin_rvv_vfadd_vf_rm:

RISCVVector::BI__builtin_rvv_vfsub_vv_rm:

RISCVVector::BI__builtin_rvv_vfsub_vf_rm:

RISCVVector::BI__builtin_rvv_vfrsub_vf_rm:

RISCVVector::BI__builtin_rvv_vfwadd_vv_rm:

RISCVVector::BI__builtin_rvv_vfwadd_vf_rm:

RISCVVector::BI__builtin_rvv_vfwsub_vv_rm:

RISCVVector::BI__builtin_rvv_vfwsub_vf_rm:

RISCVVector::BI__builtin_rvv_vfwadd_wv_rm:

RISCVVector::BI__builtin_rvv_vfwadd_wf_rm:

RISCVVector::BI__builtin_rvv_vfwsub_wv_rm:

RISCVVector::BI__builtin_rvv_vfwsub_wf_rm:

RISCVVector::BI__builtin_rvv_vfmul_vv_rm:

RISCVVector::BI__builtin_rvv_vfmul_vf_rm:

RISCVVector::BI__builtin_rvv_vfdiv_vv_rm:

RISCVVector::BI__builtin_rvv_vfdiv_vf_rm:

RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm:

RISCVVector::BI__builtin_rvv_vfwmul_vv_rm:

RISCVVector::BI__builtin_rvv_vfwmul_vf_rm:

RISCVVector::BI__builtin_rvv_vfredosum_vs_rm:

RISCVVector::BI__builtin_rvv_vfredusum_vs_rm:

RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm:

RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm:

RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tu:

RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tu:

RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tu:

RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tu:

RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tu:

RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tu:

RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tu:

RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tu:

RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tu:

RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tu:

RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tu:

RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tu:

RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tu:

RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_m:

RISCVVector::BI__builtin_rvv_vfrec7_v_rm_m:

RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_m:

RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_m:

RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_m:

RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_m:

RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_m:

RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_m:

RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_m:

RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_m:

RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_m:

RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_m:

RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_m:

RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tu:

RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tu:

RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tu:

RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tu:

RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tu:

RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tu:

RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tu:

RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tu:

RISCVVector::BI__builtin_rvv_vfmacc_vv_rm:

RISCVVector::BI__builtin_rvv_vfmacc_vf_rm:

RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm:

RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm:

RISCVVector::BI__builtin_rvv_vfmsac_vv_rm:

RISCVVector::BI__builtin_rvv_vfmsac_vf_rm:

RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm:

RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm:

RISCVVector::BI__builtin_rvv_vfmadd_vv_rm:

RISCVVector::BI__builtin_rvv_vfmadd_vf_rm:

RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm:

RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm:

RISCVVector::BI__builtin_rvv_vfmsub_vv_rm:

RISCVVector::BI__builtin_rvv_vfmsub_vf_rm:

RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm:

RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm:

RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm:

RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm:

RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm:

RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm:

RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm:

RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm:

RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm:

RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm:

RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tu:

RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tu:

RISCVVector::BI__builtin_rvv_vfadd_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfadd_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfsub_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfsub_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_m:

RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_m:

RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_m:

RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_m:

RISCVVector::BI__builtin_rvv_vfmul_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfmul_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_m:

RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_m:

RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_m:

RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_m:

RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tum:

RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tum:

RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tum:

RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tum:

RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tum:

RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tum:

RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tum:

RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tum:

RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tum:

RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tum:

RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tum:

RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tum:

RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tum:

RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tumu:

RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tumu:

RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tumu:

RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tumu:

RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tumu:

RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tumu:

RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tumu:

RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tumu:

RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tumu:

RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tumu:

RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tumu:

RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_mu:

RISCVVector::BI__builtin_rvv_vfrec7_v_rm_mu:

RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_mu:

RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_mu:

RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_mu:

RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_mu:

RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_mu:

RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_mu:

RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_mu:

RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_mu:

RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_mu:

RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_mu:

RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_mu:

RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_m:

RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_m:

RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tum:

RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tum:

RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tum:

RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tum:

RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tum:

RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tum:

RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tum:

RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tum:

RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tum:

RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tum:

RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tumu:

RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tumu:

RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfsub_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_mu:

RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_mu:

RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_mu:

RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_mu:

RISCVVector::BI__builtin_rvv_vfmul_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfmul_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_mu:

RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_mu:

RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu:

RISCV::BI__builtin_riscv_ntl_load:

RISCV::BI__builtin_riscv_ntl_store:

assert((BuiltinID == RISCV::BI__builtin_riscv_ntl_store ||

BuiltinID == RISCV::BI__builtin_riscv_ntl_load) &&

);

IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store;

NumArgs = IsStore ? 3 : 2;

PointerArg = PointerArgResult.

();

(DRE->

(), diag::err_nontemporal_builtin_must_be_pointer)

diag::err_nontemporal_builtin_must_be_pointer_intfltptr_or_vector)

Context, ValType,

);

llvm::StringMap<bool> &FeatureMap) {

MinElts = Info.

.getKnownMinValue();

!FeatureMap.lookup(

))

(

, diag::err_riscv_type_requires_extension,

) << Ty <<

;

!FeatureMap.lookup(

))

(

, diag::err_riscv_type_requires_extension,

) << Ty <<

;

!FeatureMap.lookup(

))

(

, diag::err_riscv_type_requires_extension,

)

<< Ty <<

;

(

, diag::err_riscv_type_requires_extension,

) << Ty <<

;

!FeatureMap.lookup(

))

(

, diag::err_riscv_type_requires_extension,

) << Ty <<

;

(!FeatureMap.lookup(

))

(

, diag::err_riscv_type_requires_extension,

) << Ty <<

;

ValidScalableConversion = [](

FirstType,

SecondType) {

*VecTy = SecondType->getAs<

>();

ValidScalableConversion(srcTy, destTy) ||

ValidScalableConversion(destTy, srcTy);

(

*A =

->

<RISCVInterruptAttr>()) {

diag::warn_riscv_repeated_interrupt_attribute);

(A->getLocation(), diag::note_riscv_repeated_interrupt_attribute);

RISCVInterruptAttr::InterruptType Kind;

(!RISCVInterruptAttr::ConvertStrToInterruptType(Str, Kind)) {

(AL.

(), diag::warn_attribute_type_not_supported)

<< AL << Str << ArgLoc;

(!Ext.consume_front(

))

-1 != RISCVISAInfo::getRISCVFeaturesBitsInfo(Ext).second;

Defines the clang::ASTContext interface.

Defines enum values for all the target-independent builtin functions.

llvm::MachO::Record Record

Defines the clang::Preprocessor interface.

static const RVVIntrinsicRecord RVSiFiveVectorIntrinsicRecords[]

static const RVVIntrinsicRecord RVVIntrinsicRecords[]

static const PrototypeDescriptor RVSiFiveVectorSignatureTable[]

static QualType RVVType2Qual(ASTContext &Context, const RVVType *Type)

static ArrayRef< PrototypeDescriptor > ProtoSeq2ArrayRef(IntrinsicKind K, uint16_t Index, uint8_t Length)

static const PrototypeDescriptor RVVSignatureTable[]

This file declares semantic analysis functions specific to RISC-V.

Enumerates target-specific builtins in their own namespaces within namespace clang.

Holds long-lived AST nodes (such as types and decls) that can be referred to throughout the semantic ...

BuiltinVectorTypeInfo getBuiltinVectorTypeInfo(const BuiltinType *VecTy) const

Returns the element type, element count and number of vectors (in case of tuple) for a builtin vector...

TranslationUnitDecl * getTranslationUnitDecl() const

QualType getScalableVectorType(QualType EltTy, unsigned NumElts, unsigned NumFields=1) const

Return the unique reference to a scalable vector type of the specified element type and scalable numb...

CallingConv getDefaultCallingConvention(bool IsVariadic, bool IsCXXMethod, bool IsBuiltin=false) const

Retrieves the default calling convention for the current target.

QualType getPointerType(QualType T) const

Return the uniqued reference to the type for a pointer to the specified type.

QualType getConstType(QualType T) const

Return the uniqued reference to the type for a const qualified type.

QualType getPointerDiffType() const

Return the unique type for "ptrdiff_t" (C99 7.17) defined in <stddef.h>.

QualType getIntTypeForBitwidth(unsigned DestWidth, unsigned Signed) const

getIntTypeForBitwidth - sets integer QualTy according to specified details: bitwidth,...

CanQualType UnsignedLongTy

CanQualType getSizeType() const

Return the unique type for "size_t" (C99 7.17), defined in <stddef.h>.

uint64_t getTypeSize(QualType T) const

Return the size of the specified (complete) type T, in bits.

QualType getFunctionType(QualType ResultTy, ArrayRef< QualType > Args, const FunctionProtoType::ExtProtoInfo &EPI) const

Return a normal function type with a typed argument list.

const TargetInfo & getTargetInfo() const

void getFunctionFeatureMap(llvm::StringMap< bool > &FeatureMap, const FunctionDecl *) const

SourceRange getRange() const

bool isRegularKeywordAttribute() const

SourceLocation getLoc() const

This class is used for builtin types like 'int'.

CallExpr - Represents a function call (C99 6.5.2.2, C++ [expr.call]).

Expr * getArg(unsigned Arg)

getArg - Return the specified argument.

void setArg(unsigned Arg, Expr *ArgExpr)

setArg - Set the specified argument.

SourceLocation getBeginLoc() const LLVM_READONLY

unsigned getNumArgs() const

getNumArgs - Return the number of actual arguments to this call.

DeclContext - This is used only as base class of specific decl types that can act as declaration cont...

A reference to a declared variable, function, enum, etc.

SourceLocation getBeginLoc() const LLVM_READONLY

Decl - This represents one declaration (or definition), e.g.

const FunctionType * getFunctionType(bool BlocksToo=true) const

Looks through the Decl's underlying type to extract a FunctionType when possible.

SourceLocation getLocation() const

This represents one expression.

Expr * IgnoreParenCasts() LLVM_READONLY

Skip past any parentheses and casts which might surround this expression until reaching a fixed point...

bool isValueDependent() const

Determines whether the value of this expression depends on.

bool isTypeDependent() const

Determines whether the type of this expression depends on.

bool isFPConstrained() const

Represents a function declaration or definition.

static FunctionDecl * Create(ASTContext &C, DeclContext *DC, SourceLocation StartLoc, SourceLocation NLoc, DeclarationName N, QualType T, TypeSourceInfo *TInfo, StorageClass SC, bool UsesFPIntrin=false, bool isInlineSpecified=false, bool hasWrittenPrototype=true, ConstexprSpecKind ConstexprKind=ConstexprSpecKind::Unspecified, Expr *TrailingRequiresClause=nullptr)

One of these records is kept for each identifier that is lexed.

StringRef getName() const

Return the actual identifier string.

IdentifierInfo & get(StringRef Name)

Return the identifier token info for the specified named identifier.

Describes an entity that is being initialized.

static InitializedEntity InitializeParameter(ASTContext &Context, ParmVarDecl *Parm)

Create the initialization entity for a parameter.

Represents the results of name lookup.

void addDecl(NamedDecl *D)

Add a declaration to these results with its natural access.

void resolveKind()

Resolves the result kind of the lookup, possibly hiding decls.

SourceLocation getNameLoc() const

Gets the location of the identifier.

Represents a parameter to a function.

void setScopeInfo(unsigned scopeDepth, unsigned parameterIndex)

static ParmVarDecl * Create(ASTContext &C, DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, const IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, StorageClass S, Expr *DefArg)

ParsedAttr - Represents a syntactic attribute.

unsigned getNumArgs() const

getNumArgs - Return the number of actual arguments to this attribute.

bool checkAtMostNumArgs(class Sema &S, unsigned Num) const

Check if the attribute has at most as many args as Num.

PointerType - C99 6.7.5.1 - Pointer Declarators.

QualType getPointeeType() const

Engages in a tight little dance with the lexer to efficiently preprocess tokens.

IdentifierTable & getIdentifierTable()

A (possibly-)qualified type.

const Type * getTypePtr() const

Retrieves a pointer to the underlying (unqualified) type.

QualType getCanonicalType() const

QualType getUnqualifiedType() const

Retrieve the unqualified variant of the given type, removing as little sugar as possible.

static llvm::SmallVector< Policy > getSupportedMaskedPolicies(bool HasTailPolicy, bool HasMaskPolicy)

static llvm::SmallVector< PrototypeDescriptor > computeBuiltinTypes(llvm::ArrayRef< PrototypeDescriptor > Prototype, bool IsMasked, bool HasMaskedOffOperand, bool HasVL, unsigned NF, PolicyScheme DefaultScheme, Policy PolicyAttrs, bool IsTuple)

static void updateNamesAndPolicy(bool IsMasked, bool HasPolicy, std::string &Name, std::string &BuiltinName, std::string &OverloadedName, Policy &PolicyAttrs, bool HasFRMRoundModeOp)

static std::string getSuffixStr(RVVTypeCache &TypeCache, BasicType Type, int Log2LMUL, llvm::ArrayRef< PrototypeDescriptor > PrototypeDescriptors)

static llvm::SmallVector< Policy > getSupportedUnMaskedPolicies()

SemaDiagnosticBuilder Diag(SourceLocation Loc, unsigned DiagID, bool DeferHint=false)

Emit a diagnostic.

ASTContext & getASTContext() const

bool CheckBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, CallExpr *TheCall)

bool CheckLMUL(CallExpr *TheCall, unsigned ArgNum)

bool isAliasValid(unsigned BuiltinID, llvm::StringRef AliasName)

bool isValidFMVExtension(StringRef Ext)

bool DeclareSiFiveVectorBuiltins

Indicate RISC-V SiFive vector builtin functions enabled or not.

void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D, const llvm::StringMap< bool > &FeatureMap)

bool isValidRVVBitcast(QualType srcType, QualType destType)

Are the two types RVV-bitcast-compatible types? I.e.

void handleInterruptAttr(Decl *D, const ParsedAttr &AL)

bool DeclareRVVBuiltins

Indicate RISC-V vector builtin functions enabled or not.

Sema - This implements semantic analysis and AST building for C.

bool checkArgCountAtMost(CallExpr *Call, unsigned MaxArgCount)

Checks that a call expression's argument count is at most the desired number.

FunctionDecl * getCurFunctionDecl(bool AllowLambda=false) const

Returns a pointer to the innermost enclosing function, or nullptr if the current context is not insid...

ExprResult DefaultFunctionArrayLvalueConversion(Expr *E, bool Diagnose=true)

FPOptions & getCurFPFeatures()

bool checkArgCountAtLeast(CallExpr *Call, unsigned MinArgCount)

Checks that a call expression's argument count is at least the desired number.

bool BuiltinConstantArg(CallExpr *TheCall, int ArgNum, llvm::APSInt &Result)

BuiltinConstantArg - Handle a check if argument ArgNum of CallExpr TheCall is a constant expression.

ExprResult PerformCopyInitialization(const InitializedEntity &Entity, SourceLocation EqualLoc, ExprResult Init, bool TopLevelOfInitList=false, bool AllowExplicit=false)

bool BuiltinConstantArgRange(CallExpr *TheCall, int ArgNum, int Low, int High, bool RangeIsError=true)

BuiltinConstantArgRange - Handle a check if argument ArgNum of CallExpr TheCall is a constant express...

bool checkStringLiteralArgumentAttr(const AttributeCommonInfo &CI, const Expr *E, StringRef &Str, SourceLocation *ArgLocation=nullptr)

Check if the argument E is a ASCII string literal.

Encodes a location in the source.

SourceLocation getBegin() const

SourceRange getSourceRange() const LLVM_READONLY

SourceLocation tokens are not useful in isolation - they are low level value objects created/interpre...

Exposes information about the current target.

virtual bool hasFeature(StringRef Feature) const

Determine whether the given target has the given feature.

The base class of the type hierarchy.

bool isBlockPointerType() const

bool isFloat16Type() const

bool isIntegerType() const

isIntegerType() does not include complex integers (a GCC extension).

const T * castAs() const

Member-template castAs<specific type>.

bool isSpecificBuiltinType(unsigned K) const

Test for a particular builtin type.

bool isBFloat16Type() const

bool isVectorType() const

bool isRVVSizelessBuiltinType() const

Returns true for RVV scalable vector types.

bool isFloatingType() const

bool isAnyPointerType() const

const T * getAs() const

Member-template getAs<specific type>'.

Represents a GCC generic vector type.

VectorKind getVectorKind() const

virtual bool CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II, Preprocessor &PP)=0

virtual void InitIntrinsicList()=0

Defines the clang::TargetInfo interface.

@ RVV_REQ_Xsfvfnrclipxfqf

std::vector< RVVTypePtr > RVVTypes

The JSON file list parser is used to communicate input to InstallAPI.

QualType getFunctionOrMethodResultType(const Decl *D)

std::unique_ptr< sema::RISCVIntrinsicManager > CreateRISCVIntrinsicManager(Sema &S)

@ Result

The result type of a method or function.

static bool CheckInvalidVLENandLMUL(const TargetInfo &TI, CallExpr *TheCall, Sema &S, QualType Type, int EGW)

bool hasFunctionProto(const Decl *D)

hasFunctionProto - Return true if the given decl has a argument information.

unsigned getFunctionOrMethodNumParams(const Decl *D)

getFunctionOrMethodNumParams - Return number of function or method parameters.

@ RVVFixedLengthData

is RISC-V RVV fixed-length data vector

Diagnostic wrappers for TextAPI types for error reporting.

Extra information about a function prototype.

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