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A Fast Forward Error Correction Toolbox

Run simulations on your computer. Experiment various configurations.

Choose between Polar, Turbo, LDPC (Low-Density Parity-Check), RSC (Recursive Systematic Convolutional), TPC (Turbo Product Code), BCH (Bose, Ray-Chaudhuri and Hocquenghem), RS (Reed-Solomon), Repetition and RA (Repeat and Accumulate) codes. Play with a set of decoders with different complexities and characteristics. See comparison with other FEC libraries.

CPU Vendor Architecture ISA SIMD SIMD length # Proc. # Cores per proc. Freq. (GHz) SMT Turbo Boost ThunderX2 CN9975 Cavium Vulcan ARMv8.1 NEON 128-bit 2 28 2.00 4 Unavailable Xeon Phi 7230 Intel Knights Landing x86_64 AVX-512F 512-bit 1 64 1.30 4 On Xeon E5-2680 v3 Intel Haswell x86_64 AVX2 256-bit 2 12 2.50 1 Off Xeon Gold 6140 Intel Skylake x86_64 AVX-512F+BW 512-bit 2 18 2.30 2 On Xeon Gold 6240 Intel Skylake x86_64 AVX-512F+BW 512-bit 2 18 2.60 1 Off EPYC 7702 AMD Zen 2 x86_64 AVX2 256-bit 2 64 2.00 1 Off M1 Pro Apple Silicon Firestorm ARMv8 NEON 128-bit 1 10 (8 big, 2 LITTLE) 2.00 1 On

A N=2048 and K=1723 Polar code (FA-SCL decoder, L=32, 32-bit GZip 0x04C11DB7 CRC) is simulated with a BPSK modulation and over an AWGN channel (E_b/N_0 = 4.5 dB, BER = 4.34e-10). The frozen bits of the Polar code have been generated with the GA method. The communication chain is fully vectorized with the MIPP wrapper and multi-threaded with C++11 threads. For all the CPU targets, the code has been compiled with the C++ GNU compiler version 8.2, with the following optimization flags: -O3 -funroll-loops -march=native.

AFF3CT command line (v2.2.2-14-g4d14567)


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