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Parallel processing (DSP implementation) - Wikipedia

From Wikipedia, the free encyclopedia

In digital signal processing (DSP), parallel processing is a technique duplicating function units to operate different tasks (signals) simultaneously.[1] Accordingly, we can perform the same processing for different signals on the corresponding duplicated function units. Further, due to the features of parallel processing, the parallel DSP design often contains multiple outputs, resulting in higher throughput than not parallel.

Conceptual example[edit]

Consider a function unit ( F 0 {\displaystyle F_{0}} ) and three tasks ( T 0 {\displaystyle T_{0}} , T 1 {\displaystyle T_{1}} , and T 2 {\displaystyle T_{2}} ). The required time for the function unit F 0 {\displaystyle F_{0}} to process those tasks is t 0 {\displaystyle t_{0}} , t 1 {\displaystyle t_{1}} , and t 2 {\displaystyle t_{2}} , respectively. Then, if we operate these three tasks in a sequential order, the required time to complete them is t 0 + t 1 + t 2 {\displaystyle t_{0}+t_{1}+t_{2}} .

However, if we duplicate the function unit to another two copies ( F {\displaystyle F} ), the aggregate time is reduced to m a x ( t 0 , t 1 , t 2 ) {\displaystyle max(t_{0},t_{1},t_{2})} , which is smaller than in a sequential order.

Mechanism:

Objective:

Consider a condition that we are able to apply both parallel processing and pipelining techniques, it is better to choose parallel processing techniques with the following reasons

Parallel FIR filters[edit]

Consider a 3-tap FIR filter:[2]

y ( n ) = a x ( n ) + b x ( n − 1 ) + c x ( n − 2 ) {\displaystyle y(n)=ax(n)+bx(n-1)+cx(n-2)}

which is shown in the following figure.

Assume the calculation time for multiplication units is Tm and Ta for add units. The sample period is given by

T sample ≥ T m + 2 T a {\displaystyle T_{\text{sample}}\geq T_{m}+2T_{a}}

By parallelizing it, the resultant architecture is shown as follows. The sample rate now becomes

T sample ≥ T clock N = T m + 2 T a 3 {\displaystyle T_{\text{sample}}\geq {\frac {T_{\text{clock}}}{N}}={\frac {T_{m}+2T_{a}}{3}}}

where N represents the number of copies.

Please note that, in a parallel system, T sample ≠ T clock {\displaystyle T_{\text{sample}}\neq T_{\text{clock}}} while T sample = T clock {\displaystyle T_{\text{sample}}=T_{\text{clock}}} holds in a pipelined system.

Parallel 1st-order IIR filters[edit]

Consider the transfer function of a 1st-order IIR filter formulated as

H ( z ) = z − 1 1 − a z − 1 {\displaystyle H(z)={\frac {z^{-1}}{1-az^{-1}}}}

where |a| ≤ 1 for stability, and such filter has only one pole located at z = a;

The corresponding recursive representation is

y ( n + 1 ) = a y ( n ) + u ( n ) {\displaystyle y(n+1)=ay(n)+u(n)}

Consider the design of a 4-parallel architecture (N = 4). In such parallel system, each delay element means a block delay and the clock period is four times the sample period.

Therefore, by iterating the recursion with n = 4k, we have

y ( n + 4 ) = a 4 y ( n ) + a 3 u ( n ) + a 2 u ( n + 1 ) + a u ( n + 2 ) + u ( n + 3 ) {\displaystyle y(n+4)=a^{4}y(n)+a^{3}u(n)+a^{2}u(n+1)+au(n+2)+u(n+3)}
→ y ( 4 k + 4 ) = a 4 y ( 4 k ) + a 3 u ( 4 k ) + a 2 u ( 4 k + 1 ) + a u ( 4 k + 2 ) + u ( 4 k + 3 ) {\displaystyle \rightarrow y(4k+4)=a^{4}y(4k)+a^{3}u(4k)+a^{2}u(4k+1)+au(4k+2)+u(4k+3)}

The corresponding architecture is shown as follows.

The resultant parallel design has the following properties.

The square increase in hardware complexity can be reduced by exploiting the concurrency and the incremental computation to avoid repeated computing.

Parallel processing for low power[edit]

Another advantage for the parallel processing techniques is that it can reduce the power consumption of a system by reducing the supply voltage.

Consider the following power consumption in a normal CMOS circuit.

P seq = C total ⋅ V 0 2 ⋅ f {\displaystyle P_{\text{seq}}=C_{\text{total}}\cdot V_{0}^{2}\cdot f}

where the Ctotal represents the total capacitance of the CMOS circuit.

For a parallel version, the charging capacitance remains the same but the total capacitance increases by N times.

In order to maintain the same sample rate, the clock period of the N-parallel circuit increases to N times the propagation delay of the original circuit.

It makes the charging time prolongs N times. The supply voltage can be reduced to βV0.

Therefore, the power consumption of the N-parallel system can be formulated as

P para = ( N C total ) ⋅ ( β V 0 2 ) ⋅ f N = β 2 P seq {\displaystyle P_{\text{para}}=(NC_{\text{total}})\cdot (\beta V_{0}^{2})\cdot {\frac {f}{N}}=\beta ^{2}P_{\text{seq}}}

where β can be computed by

N ( β V 0 − V t ) 2 = β ( V 0 − V t ) 2 . {\displaystyle N(\beta V_{0}-V_{t})^{2}=\beta (V_{0}-V_{t})^{2}.\,}

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