Driver API for NAND Flash Device Interface (Driver_NAND.h). More...
ARM_DRIVER_VERSION ARM_NAND_GetVersion (void) Get driver version. More...Driver API for NAND Flash Device Interface (Driver_NAND.h).
NAND devices are a type of non-volatile storage and do not require power to hold data. Wikipedia offers more information about the Flash Memories, including NAND.
Block Diagram
Simplified NAND Flash Schematic
NAND API
The following header files define the Application Programming Interface (API) for the NAND interface:
The driver implementation is a typical part of the Device Family Pack (DFP) that supports the peripherals of the microcontroller family.
NAND Flash is organized in pages, grouped into blocks as the smallest erasable unit. The addressing of data is achieved by byte_address = block * block_size + page_in_block * page_size + offset_in_page. In terms of this NAND API blocks and pages are referred to as row and the byte offset within the page as col. Thus one can calculate the byte_address = row * page_size + col. The parameters page_size and block_size are device specific and must be handled by the driver user appropriately.
Driver Functions
The driver functions are published in the access struct as explained in Common Driver Functions
#define ONFI_CMD_READ_1ST 0x00
#define ONFI_CMD_PROGRAM_2ND 0x10
#define ONFI_CMD_READ_2ND 0x30
#define ONFI_CMD_PROGRAM_1ST 0x80
#define ONFI_CMD_RESET 0xFF
volatile uint32_t NAND_Events;
void NAND_SignalEventCallback (uint32_t dev_num, uint32_t event) {
if (dev_num == 0) {
NAND_Events |= event;
}
else {
}
}
uint32_t volt = 0U;
if (volt != 0U) {
}
}
}
}
uint32_t volt = 0U;
if (volt) {
}
}
voidReadPage (
ARM_DRIVER_NAND*drv, uint32_t row, uint8_t *data, uint32_t cnt) {
uint32_t dev_num = 0;
uint32_t mode;
}
}
}
voidWritePage_Seq (
ARM_DRIVER_NAND*drv, uint32_t row,
constuint8_t *data, uint32_t cnt) {
uint32_t dev_num = 0;
uint32_t cmd;
uint32_t code;
uint32_t seq;
cmd = ONFI_CMD_PROGRAM_1ST | (ONFI_CMD_PROGRAM_2ND << 8);
seq = 1;
code,
cmd,
0,
row,
(void *)data,
cnt,
NULL,
&seq);
}
NAND Status.
Structure with information about the status of a NAND. The data fields encode flags for the driver.
Returned by:
Data Fields uint32_t busy: 1 Driver busy flag. uint32_t ecc_error: 1 ECC error detected (cleared on next Read/WriteData or ExecuteSequence) uint32_t reserved: 30Access structure of the NAND Driver.
The functions of the NAND driver are accessed by function pointers exposed by this structure. Refer to Common Driver Functions for overview information.
Each instance of a NAND interface provides such an access structure. The instance is identified by a postfix number in the symbol name of the access structure, for example:
A middleware configuration setting allows connecting the middleware to a specific driver instance Driver_NANDn. The default is 0, which connects a middleware to the first instance of a driver.
Data Fields ARM_DRIVER_VERSION(* GetVersion )(void) Pointer to ARM_NAND_GetVersion : Get driver version. More...Pointer to ARM_NAND_DevicePower : Set device power supply voltage.
int32_t(* WriteProtect)(uint32_t dev_num, bool enable)Pointer to ARM_NAND_WriteProtect : Control WPn (Write Protect).
int32_t(* ChipEnable)(uint32_t dev_num, bool enable)Pointer to ARM_NAND_ChipEnable : Control CEn (Chip Enable).
int32_t(* SendCommand)(uint32_t dev_num, uint8_t cmd)Pointer to ARM_NAND_SendCommand : Send command to NAND device.
int32_t(* SendAddress)(uint32_t dev_num, uint8_t addr)Pointer to ARM_NAND_SendAddress : Send address to NAND device.
int32_t(* ReadData)(uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)Pointer to ARM_NAND_ReadData : Read data from NAND device.
int32_t(* WriteData)(uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)Pointer to ARM_NAND_WriteData : Write data to NAND device.
int32_t(* ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd, uint32_t addr_col, uint32_t addr_row, void *data, uint32_t data_cnt, uint8_t *status, uint32_t *count)Pointer to ARM_NAND_ExecuteSequence : Execute sequence of operations.
int32_t(* Control)(uint32_t dev_num, uint32_t control, uint32_t arg)Pointer to ARM_NAND_Control : Control NAND Interface.
struct ARM_NAND_CAPABILITIESNAND Driver Capabilities.
A NAND driver can be implemented with different capabilities. The data fields of this struct encode the capabilities implemented by this driver.
Returned by:
Data Fields uint32_t event_device_ready: 1 Signal Device Ready event (R/Bn rising edge) uint32_t reentrant_operation: 1 Supports re-entrant operation (SendCommand/Address, Read/WriteData) uint32_t sequence_operation: 1 Supports Sequence operation (ExecuteSequence, AbortSequence) uint32_t vcc: 1 Supports VCC Power Supply Control. uint32_t vcc_1v8: 1 Supports 1.8 VCC Power Supply. uint32_t vccq: 1 Supports VCCQ I/O Power Supply Control. uint32_t vccq_1v8: 1 Supports 1.8 VCCQ I/O Power Supply. uint32_t vpp: 1 Supports VPP High Voltage Power Supply Control. uint32_t wp: 1 Supports WPn (Write Protect) Control. uint32_t ce_lines: 4 Number of CEn (Chip Enable) lines: ce_lines + 1. uint32_t ce_manual: 1 Supports manual CEn (Chip Enable) Control. uint32_t rb_monitor: 1 Supports R/Bn (Ready/Busy) Monitoring. uint32_t data_width_16: 1 Supports 16-bit data. uint32_t ddr: 1 Supports NV-DDR Data Interface (ONFI) uint32_t ddr2: 1 Supports NV-DDR2 Data Interface (ONFI) uint32_t sdr_timing_mode: 3 Fastest (highest) SDR Timing Mode supported (ONFI) uint32_t ddr_timing_mode: 3 Fastest (highest) NV_DDR Timing Mode supported (ONFI) uint32_t ddr2_timing_mode: 3 Fastest (highest) NV_DDR2 Timing Mode supported (ONFI) uint32_t driver_strength_18: 1 Supports Driver Strength 2.0x = 18 Ohms. uint32_t driver_strength_25: 1 Supports Driver Strength 1.4x = 25 Ohms. uint32_t driver_strength_50: 1 Supports Driver Strength 0.7x = 50 Ohms. uint32_t reserved: 2 Reserved (must be zero)NAND ECC (Error Correction Code) Information.
Stores the characteristics of a ECC (Error Correction Code) algorithm and provides the information about necessary application data handling in order to protect stored data from NAND bit errors.
ECC algorithms applied on NAND memory typically operate on NAND device page level which is virtually divided to multiple main and spare areas. Data from main and spare area is taken into account when generating ECC data which is also stored into spare area. ECC codeword defines how much data will be protected and how much ECC data will be generated.
To describe how application data must be organized, ECC information structure specifies protection type which defines the protected part of data. As main and spare are of different size, two different algorithms could be provided, we can describe them as ECC0 and ECC1. Type can then have the following values:
Type Description 0 ECC algorithm not used 1 ECC0 algorithm protects main data 2 ECC0 algorithm protects main and spare data 3 ECC0 algorithm protects main and ECC1 algorithm protects spare dataVirtual page division is described with page layout (page_layout), number of pages (page_count) and virtual page size (page_size or virtual_page_size). Virtual page size used by ECC algorithm can be defined by either page_size or virtual_page_size, depending on the page_size values:
Value Main + Spare size 0 512 + 16 1 1024 + 32 2 2048 + 64 3 4096 + 128 4 8192 + 256 8 512 + 28 9 1024 + 56 10 2048 + 112 11 4096 + 224 12 8192 + 448 15 Not used, use virtual_page_sizeStructure member virtual_page_size is an array of two 16-bit values. First field of array (i.e. virtual_page_size[0]) contains main area size while second (i.e. virtual_page_size[1]) contains spare area size. Number of virtual pages N is defined with page_count and must be calculated as N = 2 ^ page_count.
Page layout defines main and spare ordering and two different page layouts are possible. First ordering assumes that spare area follows after every main area, while in second case all main areas build one contiguous region followed by contiguous region of spare areas. This is defined by member page_layout:
Layout Description 0 Single spare follows after single main: Main0,Spare0 ... MainN-1,SpareN-1 1 Contiguous spare follows after contiguous main: Main0 ... MainN-1,Spare0 ... SpareN-1ECC codeword size defines the size of data that is protected by ECC algorithm and is different for main and spare area. All structure members that define the codeword are therefore arrays of two 16-bit values. Codeword offset defines where ECC protected data starts in main (codeword_offset[0]) or spare (codeword_offset[1]) area, codeword size (codeword_size) defines the number of data that is protected i.e. data over which ECC is calculated and codeword gap (codeword_gap) defines the space between two consecutive codeword regions.
Generated ECC data is stored into spare area and is described similar as codeword, with offset from start of spare area (ecc_offset), size of generated data (ecc_size) and gap (ecc_gap) between two consecutive ECC data regions.
Number of bits that ECC algorithm can correct per codeword is defined with correctable_bits.
Parameter for:
Data Fields uint32_t type: 2 Type: 1=ECC0 over Main, 2=ECC0 over Main+Spare, 3=ECC0 over Main and ECC1 over Spare. uint32_t page_layout: 1 Page layout: 0=|Main0|Spare0|...|MainN-1|SpareN-1|, 1=|Main0|...|MainN-1|Spare0|...|SpareN-1|. uint32_t page_count: 3 Number of virtual pages: N = 2 ^ page_count. uint32_t page_size: 4 Virtual Page size (Main+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448, 15=Not used (extended description) uint32_t reserved: 14 Reserved (must be zero) uint32_t correctable_bits: 8 Number of correctable bits (based on 512 byte codeword size) uint16_t codeword_size[2] Number of bytes over which ECC is calculated. uint16_t ecc_size[2] ECC size in bytes (rounded up) uint16_t ecc_offset[2] ECC offset in bytes (where ECC starts in Spare) uint16_t virtual_page_size[2] Virtual Page size in bytes (Main/Spare) uint16_t codeword_offset[2] Codeword offset in bytes (where ECC protected data starts in Main/Spare) uint16_t codeword_gap[2] Codeword gap in bytes till next protected data. uint16_t ecc_gap[2] ECC gap in bytes till next generated ECC.Get driver version.
The function ARM_NAND_GetVersion returns version information of the driver implementation in ARM_DRIVER_VERSION
Example:
void setup_nand (void) {
drv_info = &Driver_NAND0;
if(version.
api< 0x10A) {
return;
}
}
Get driver capabilities.
The function ARM_NAND_GetCapabilities retrieves information about capabilities in this driver implementation. The data fields of the structure ARM_NAND_CAPABILITIES encode various capabilities, for example if a hardware is able to create signal events using the ARM_NAND_SignalEvent callback function.
Example:
void read_capabilities (void) {
drv_info = &Driver_NAND0;
}
Initialize the NAND Interface.
The function ARM_NAND_Initialize initializes the NAND interface. It is called when the middleware component starts operation.
The function performs the following operations:
The parameter cb_event is a pointer to the ARM_NAND_SignalEvent callback function; use a NULL pointer when no callback signals are required.
Example:
De-initialize the NAND Interface.
The function ARM_NAND_Uninitialize de-initializes the resources of NAND interface.
It is called when the middleware component stops operation and releases the software resources used by the interface.
Control the NAND interface power.
The function ARM_NAND_PowerControl controls the power modes of the NAND interface.
The parameter state sets the operation and can have the following values:
Refer to Function Call Sequence for more information.
int32_t ARM_NAND_DevicePower ( uint32_t voltage )Set device power supply voltage.
The function ARM_NAND_DevicePower controls the power supply of the NAND device.
The parameter voltage sets the device supply voltage as defined in the table.
AMR_NAND_POWER_xxx_xxx specifies power settings.
int32_t ARM_NAND_WriteProtect ( uint32_t dev_num, bool enable )Control WPn (Write Protect).
The function ARM_NAND_WriteProtect controls the Write Protect (WPn) pin of a NAND device.
The parameter dev_num is the device number.
The parameter enable specifies whether to enable or disable write protection.
Control CEn (Chip Enable).
The function ARM_NAND_ChipEnable control the Chip Enable (CEn) pin of a NAND device.
The parameter dev_num is the device number.
The parameter enable specifies whether to enable or disable the device.
This function is optional and supported only when the data field ce_manual = 1 in the structure ARM_NAND_CAPABILITIES. Otherwise, the Chip Enable (CEn) signal is controlled automatically by SendCommand/Address, Read/WriteData and ExecuteSequence (for example when the NAND device is connected to a memory bus).
int32_t ARM_NAND_GetDeviceBusy ( uint32_t dev_num )Get Device Busy pin state.
The function ARM_NAND_GetDeviceBusy returns the status of the Device Busy pin: [1=busy; 0=not busy or error].
The parameter dev_num is the device number.
int32_t ARM_NAND_SendCommand ( uint32_t dev_num, uint8_t cmd )Send command to NAND device.
The function ARM_NAND_SendCommand sends a command to the NAND device.
The parameter dev_num is the device number.
The parameter cmd is the command sent to the NAND device.
Send address to NAND device.
Send an address to the NAND device. The parameter dev_num is the device number. The parameter addr is the address.
int32_t ARM_NAND_ReadData ( uint32_t dev_num, void * data, uint32_t cnt, uint32_t mode )Read data from NAND device.
The function ARM_NAND_ReadData reads data from a NAND device.
The parameter dev_num is the device number.
The parameter data is a pointer to the buffer that stores the data read from a NAND device.
The parameter cnt is the number of data items to read.
The parameter mode defines the operation mode as listed in the table below.
The data item size is defined by the data type, which depends on the configured data bus width.
Data type is:
The function executes in the following ways:
Write data to NAND device.
The function ARM_NAND_WriteData writes data to a NAND device.
The parameter dev_num is the device number.
The parameter data is a pointer to the buffer with data to write.
The parameter cnt is the number of data items to write.
The parameter mode defines the operation mode as listed in the table below.
The data item size is defined by the data type, which depends on the configured data bus width.
Data type is:
The function executes in the following ways:
Execute sequence of operations.
The function ARM_NAND_ExecuteSequence executes a sequence of operations for a NAND device.
The parameter dev_num is the device number.
The parameter code is the sequence encoding as defined in the table Sequence execution Code.
The parameter cmd is the command or a series of commands.
The parameter addr_col is the column address.
The parameter addr_row is the row address.
The parameter data is a pointer to the buffer that stores the data to or loads the data from.
The parameter data_cnt is the number of data items to read or write in one iteration.
The parameter status is a pointer to the buffer that stores the status read.
The parameter count is a pointer to the number of iterations.
ARM_NAND_CODE_xxx specifies sequence execution codes.
The data item size is defined by the data type, which depends on the configured data bus width.
Data type is:
The function is non-blocking and returns as soon as the driver has started executing the specified sequence. When the operation is completed, the ARM_NAND_EVENT_DRIVER_DONE event is generated (if enabled by ARM_NAND_DRIVER_DONE_EVENT). Progress of the operation can also be monitored by calling the ARM_NAND_GetStatus function and checking the busy data field.
Driver executes the number of specified iterations where in each iteration items specified by ARM_NAND_CODE_xxx are executed in the order as listed in the table Sequence execution Code. The parameter count is holding the current number of iterations left.
Execution is automatically aborted and ARM_NAND_EVENT_DRIVER_DONE event is generated (if enabled by ARM_NAND_DRIVER_DONE_EVENT):
Abort sequence execution.
The function ARM_NAND_AbortSequence aborts execution of the current sequence for a NAND device.
The parameter dev_num is the device number.
int32_t ARM_NAND_Control ( uint32_t dev_num, uint32_t control, uint32_t arg )Get NAND status.
The function ARM_NAND_GetStatus returns the current NAND device status.
The parameter dev_num is the device number.
Inquire about available ECC.
The function ARM_NAND_InquireECC reads error correction code information.
The parameter index is the ECC index and is used to retrieve different ECC configurations.
The parameter info is a pointer of type ARM_NAND_ECC_INFO. The data fields store the information.
When multiple different ECC configurations exist, ARM_NAND_ECC_INFO structure exists for each configuration. Parameter index denotes which configuration will be retrieved. Value of index should start with zero to retrieve first ECC configuration and should be incremented in order to retrieve next ECC configuration. When index is out of range function ARM_NAND_InquireECC returns with error.
Parameter index is used by ARM_NAND_ECC(n) in ARM_NAND_ReadData, ARM_NAND_WriteData and ARM_NAND_ExecuteSequence to select suitable ECC configuration.
Example
int32_t idx;
idx = 0;
}
idx++;
}
void ARM_NAND_SignalEvent ( uint32_t dev_num, uint32_t event )Signal NAND event.
The function ARM_NAND_SignalEvent is a callback function registered by the function ARM_NAND_Initialize.
The parameter dev_num is the device number.
The parameter event indicates one or more events that occurred during driver operation. Each event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call.
Not every event is necessarily generated by the driver. This depends on the implemented capabilities stored in the data fields of the structure ARM_NAND_CAPABILITIES, which can be retrieved with the function ARM_NAND_GetCapabilities.
The following events can be generated:
The event ARM_NAND_EVENT_DEVICE_READY occurs after complete execution of commands (initiated with the functions ARM_NAND_SendCommand, ARM_NAND_SendAddress, ARM_NAND_ReadData, ARM_NAND_WriteData, ARM_NAND_ExecuteSequence). It is useful to indicate completion of complex operations (such as erase). The event is only generated when ARM_NAND_GetCapabilities returns data field event_device_ready = 1 and was enabled by calling ARM_NAND_Control (ARM_NAND_DEVICE_READY_EVENT, 1). If the event is not available, poll the busy data field using the function ARM_NAND_GetStatus.
The event ARM_NAND_EVENT_DRIVER_READY occurs when previously a function (ARM_NAND_SendCommand, ARM_NAND_SendAddress, ARM_NAND_ReadData, ARM_NAND_WriteData, ARM_NAND_ExecuteSequence) returned with ARM_DRIVER_ERROR_BUSY. It is useful when functions are called simultaneously from independent threads (for example to control multiple devices) and the threads have no knowledge about each other (driver rejects reentrant calls with return of ARM_DRIVER_ERROR_BUSY). dev_num indicates the device that returned previously busy.
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